LP8555_技术文档

Sample &

Buy

Support &

Community

Product

Folder

Tools &

Software

Technical

Documents

LP8555

SNVS857 –FEBRUARY 2014

LP8555 High-Efficiency LED Backlight Driver for Tablet PCs

1 Features

3 Description

The LP8555 is a high efficiency LED driver with

integrated dual DC-DC boost converters. It has 12

high-precision current sinks that can be controlled by

a PWM input signal, an I²C master, or both.

1

•

Dual High-Efficiency DC/DC Boost Converters

2.7-V to 20-V VDD Range

12 50-mA High-Precision LED Current Sinks With

12-Bit Brightness Control

Dual-boost configuration of LP8555 shares the load

to two inductors and allows thinner overall solution

size and better efficiency compared to single-boost

solutions. 12 LED strings allows driving high number

of LEDs with optimal efficiency since boost

conversion ratio can be kept low.

•

Adaptive LED Current Sink Headroom Controls for

Maximum System Efficiency

•

LED String Count Auto-Detection

Phase-Shifted PWM Mode for Reduced Audible

Noise

The boost converter has adaptive output voltage

control based on the LED current sink headroom

voltages. This feature minimizes the power

consumption by adjusting the voltage to lowest

sufficient level in all conditions.

•

PWM Input Duty-Cycle and/or I²C-Register

Brightness Control

Hybrid PWM and Current Dimming for Higher LED

Drive Optical Efficiency

•

Flexible CABC Support

EPROM, I²C-Register, or External Resistors for

Configuration

The LED string auto-detect function enables use of

the same device in systems with 2 to 12 LED strings

for the maximum design flexibility. Proprietary Hybrid

PWM and Current dimming mode enables additional

system power savings. Phase-shift PWM allows

reduced audible noise and smaller boost output

capacitors. Flexible CABC support combines

brightness level selections based on the PWM input

and I²C commands.

•

Improved Boost EMI Performance with Slew-Rate

Control, Spread Spectrum, and Phase-Shifted

Switching

•

Extensive Fault Detection Schemes

2 Applications

Device Information

•

Tablet LCD Display LED Backlight

ORDER NUMBER PACKAGE

BODY SIZE

LP8555YFQR

DSBGA (36)

2,478mm x 2,478mm

4 Simplified Schematic

7 - 28V

1.3 ꢀ9_OUT/ V_INꢀ10

L1

D1

V_BATT

LED Drive Efficiency

2.7V ± 20V

C_VDD

V_{OUT_A}

C_{IN_A}

C_{OUT_A}

92

Inductor: IHLP2525CZER6R8M01

SW_A

FB_A

VDD

VLDO

C_VLDO

LCD Display

90

88

86

84

82

80

LEDA1

LEDA2

LEDA3

LEDA4

LP8555

EN/VDDIO

FSET/SDA

EN

LEDA5

LEDA6

R_PULL-UP

SDA

VIN = 3.0 V

VIN = 3.7 V

VIN = 4.2 V

VIN = 5.4 V

VIN = 7.4 V

VIN = 8.4 V

ISET/SCL

PWM/INT

SCL

INT

LEDB1

LEDB2

LEDB3

VDDIO

R_PULL-UP

LEDB4

LEDB5

0

20

40

60

80

100

LEDB6

Brightness (%)

C002

FB_B

GNDs

C_{IN_B}

SW_B

V_{OUT_B}

V_BATT

2.7V ± 20V

C_{OUT_B}

7 - 28V

1.3 ꢀ9_OUT/ V_INꢀ10

L2

D2

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

Table of Contents

8.2 Functional Block Diagram ....................................... 11

8.3 Features Description............................................... 12

8.4 Device Functional Modes........................................ 29

8.5 Register Maps......................................................... 30

Application and Implementation ........................ 46

9.1 Application Information............................................ 46

9.2 Typical Applications ................................................ 46

1

2

3

4

5

6

7

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Simplified Schematic............................................. 1

Revision History..................................................... 2

Terminal Configuration and Functions................ 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 Handling Ratings....................................................... 4

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics⁽³⁾....................................... 5

9

10 Power Supply Recommendations ..................... 54

11 Layout................................................................... 55

11.1 Layout Guidelines ................................................. 55

11.2 Layout Example .................................................... 56

12 Device and Documentation Support ................. 57

12.1 Trademarks........................................................... 57

12.2 Electrostatic Discharge Caution............................ 57

12.3 Glossary................................................................ 57

7.6 I²C Serial Bus Timing Parameters (FSET/SDA,

ISET/SCL).................................................................. 7

7.7 Typical Characteristics ............................................. 8

Detailed Description ............................................ 11

8.1 Overview ................................................................. 11

13 Mechanical, Packaging, and Orderable

8

Information ........................................................... 58

5 Revision History

DATE

REVISION

NOTES

February 21, 2014

*

Initial Release

2

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

6 Terminal Configuration and Functions

YFQ (DSBGA)

36 Bumps

TOP

BOTTOM

6

5

4

3

2

1

LEDB1

LEDB3

LEDB5

LEDA5

LEDA3

LEDB2

LEDB4

LEDB6

LEDA6

LEDA4

FB_B

SW_B

FB_B

LEDB2

LEDB4

LEDB6

LEDA6

LEDA4

LEDB1

LEDB3

LEDB5

LEDA5

LEDA3

6

5

4

3

2

1

EN

VDDIO

GND

SW_B

GND

SW_B

GND

SW_B

GND

SW_B

GND

SW_B

GND

SW_B

EN

VDDIO

ISET/

SCL

ISET/

SCL

GND

VDD

GND

FSET/

SDA

FSET/

SDA

VLDO

PWM/

INT

GND

SW_A

GND

SW_A

GND

SW_A

GND

SW_A

GND

SW_A

GND

SW_A

PWM/

INT

LEDA1

LEDA2

FB_A

SW_A

FB_A

LEDA2

LEDA1

A

B

C

D

E

F

E

D

C

B

A

Terminal Functions

TERMINAL

TYPE

DESCRIPTION

NUMBER

NAME

A1, A2, A3,

B1, B2, B3,

LEDAx

A

LED Bank A Current Sink Terminal. If unused, this terminal may be left floating.

Feedback terminal for the Bank A Boost Converter.

A4, A5, A6,

B4, B5, B6

LEDBx

A

C1

C2

FB_A

A

I

PWM/INT

Dual function terminal. When BRTMODE = 00, 10, or 11, this is a PWM input terminal. When

BRTMODE = 01, this terminal is a programmable interrupt terminal. In this mode, this is an

open drain output that pulls low when a fault condition occurs.

C3, C4, D3, D4

C5

GND

G

I

Ground for analog and digital blocks. These terminals should be connected to a noise-free

GND plane if possible (separate plane than GND_SW_x terminals).

Backlight Enable terminal and VDDIO power terminal + reference terminal for I²C

communication. This terminal should be connected to IO voltage with low impedance route to

avoid voltage ripple on this terminal.

EN/VDDIO

C6

FB_B

SW_A

A

G

Feedback terminal for the Bank B Boost Converter.

Bank A Boost Converter Switch

D1, E1, F1

D2, E2, F2

GND_SW_A

Bank A Boost Converter Switch Ground. These terminals can be connected to noisy GND due

to high current spikes.

D5, E5, F5

GND_SW_B

G

A

Bank B Boost Converter Switch Ground. These terminals can be connected to noisy GND due

to high current spikes.

D6, E6, F6

E3

SW_B

Bank B Boost Converter Switch

FSET/SDA

I/O/A Dual Function terminal. When I²C is not used (for example, BRTMODE = 00), this terminal

can be used to set the boost switching frequency and/or LED PWM frequency by connecting

a resistor between the terminal and a ground reference. When I²C is used (for example,

BRTMODE = 01, 10, or 11), this terminal is connected to a SDA line of an I²C bus.

E4

ISET/SCL

I/A

Dual Function terminal. When I²C is not used (for example, if BRTMODE=00), this terminal

can be used to set the full-scale LED current by connecting a resistor between the terminal

and a ground reference. When I²C is used (for example, BRTMODE = 01, 10, or 11), this

terminal is connected to a SCL line of an I²C bus.

F3

F4

VLDO

VDD

P

Internal LDO Output terminal. C_VLDObypass capacitor must be connected between this

terminal and ground.

Device power supply terminal. Provide 2.7-V to 20-V supply to this terminal. This terminal is

an input of the internal LDO regulator. The output of the internal LDO powers the device

blocks.

A: Analog, G: Ground Terminal, P: Power Terminal, I: Input Terminal, O: Output Terminal

Submit Documentation Feedback

3

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

Over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

VDD

Voltage on VDD

Voltage on VLDO

–0.3

22

VLDO

V(PWM/INT,

EN/VDDIO/

FSET/SDA,

ISET/SCL)

–0.3

6

V

Voltage on logic terminals

V(SW_A, SW_B,

LEDxy, FB_x)

Voltage on analog terminals

Continuous Power Dissipation

31

Internally

limited

(2)

P_D

(3)

T_A

Operating ambient temperature range

–40

85

(3)

T_J

Maximum operating junction temperature

125

°C

(4)

T_soldering

Note

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J= 150°C (typ.) and

disengages at T_J= 137°C (typ.).

(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be degraded. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP

= 125ºC), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal resistance of the

part/package in the application (θ_JA), as given by the following equation: T_A-MAX= T_J-MAX-OP– (θ_JA× P_D-MAX).

(4) For detailed soldering specifications and information, please refer to Application Note AN1112.

7.2 Handling Ratings

MIN

MAX

150

UNIT

T_STORAGE

V_HBM

Storage temp range

Human body model (HBM) voltage⁽¹⁾

–65

°C

2000

250

V

(2)

V_CDM

Charged device model (CDM)

(1) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe

manufacturing with a standard ESD control process. Terminals listed as 2 kV may actually have higher performance.

(2) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe

manufacturing with a standard ESD control process. Terminals listed as 250 V may actually have higher performance

4

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

7.3 Recommended Operating Conditions⁽¹⁾⁽²⁾

Over operating free-air temperature range (unless otherwise noted)

MIN

2.7

1.7

0

MAX

20

UNIT

VDD – Voltage on VDD

VLDO – Voltage on VLDO

5.5

28

V (EN/VDDIO) – Supply voltage for digital I/O

V (PWM/INT, FSET/SDA, ISET/SCL) – Voltage on logic terminals

V (SW_A, SW_B, LEDxy, FB_x)

V

0

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device a these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the potential at the GND terminals.

7.4 Thermal Information

Over operating free-air temperature range (unless otherwise noted)

DSBGA

(36 TERMINALS)

THERMAL METRIC⁽¹⁾

UNIT

(2)

θ_JA

θ_JC

θ_JB

Ψ_JT

Ψ_JB

Junction-to-ambient thermal resistance (θ_JA

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

)

76.2

0.3

°C/W

16.3

1.8

Junction-to-top characterization parameter

Junction-to-board characterization parameter

16.3

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

7.5 Electrical Characteristics⁽¹⁾⁽²⁾

Limits apply over the full ambient temperature range –40°C ≤ T_A≤ 85°C. Unless otherwise specified: VDD = 3.6 V, EN/VDDIO

= 1.8 V, L1 = L2 = 6.8 µH, C_{IN_A}= C_{IN_B}= 10 µF, C_{OUT_A}= C_{OUT_B}= 10 µF, C_VLDO= 10 µF, C_VDD= 1 µF.⁽³⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

1

UNIT

I_IN

Shutdown supply current

Standby supply current

EN = L and PWM/INT = L

µA

EN = H and PWM/INT = L, ON bit =

0

19

30

EN = H, ON bit = 1, no current going

through LED outputs

4.2

Normal mode supply current

mA

f_OSC

Internal oscillator frequency

accuracy

-7%

7%

7

T_TSD

Thermal shutdown threshold

Thermal shutdown hysteresis

Start-up time⁽⁴⁾

150

13

5

°C

T_{TSD_hyst}

t_START-UP

ms

BOOST CONVERTER (Applies for both boost converters)

V_{BST_MIN}

V_{BST_MAX}

Minimum output voltage

Maximum output voltage

7

V

VMAX = 00

VMAX = 01

VMAX = 10

VMAX = 11

18

22

25

28

I_MAX

SW FET current limit

2.7

3.1

3.5

A

R_NMOS

I_LOAD

NMOS switch-ON resistance

Continuous load current

I_SW= 0.5 A

0.16

Ω

VBATT = 3 V, VOUT = 26.6 V.

Typical application.

180

mA

(1) All voltages are with respect to the potential at the GND terminals.

(2) Min and Max limits are specified by design, test, or statistical analysis.

(3) Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics

(4) Start-up time is measured from the moment the ON bit is set high to the moment when backlight is enabled.

Submit Documentation Feedback

5

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

Electrical Characteristics⁽¹⁾⁽²⁾(continued)

Limits apply over the full ambient temperature range –40°C ≤ T_A≤ 85°C. Unless otherwise specified: VDD = 3.6 V, EN/VDDIO

= 1.8 V, L1 = L2 = 6.8 µH, C_{IN_A}= C_{IN_B}= 10 µF, C_{OUT_A}= C_{OUT_B}= 10 µF, C_VLDO= 10 µF, C_VDD= 1 µF.⁽³⁾

PARAMETER

TEST CONDITIONS

MIN

–7%

1.3

TYP

MAX

7%

UNIT

ƒ_SW

Switching frequency

BFREQ = 0

BFREQ = 1

500

1000

kHz

ƒ_{SW_ACCURACY}

V_{OVP_THR}

Boost oscillator accuracy

Overvoltage protection voltage

threshold

V_{BST_MAX}

+1.6 V

V

V_OUT/V_IN

Conversion ratio

No load, BFREQ = 1

10

ΔV_SW/t_off-on

SW node voltage slew rate

during OFF-to-ON transition

Load current 120 mA. Boost slew

rate set to fastest (SRON = 00b).

12.5

19.5

V/ns

ΔV_SW/t_on-off

SW node voltage slew rate

during ON-to-OFF transition

ƒ_MOD

Modulation frequency

(percentage of the SW

frequency)

FMOD_DIV = 00

FMOD_DIV = 01

FMOD_DIV = 10

FMOD_DIV = 11

0.47%

0.27%

0.17%

0.12%

CURRENT SINKS

Outputs LEDA1...LEDB6, V_LEDxx

28 V

=

I_LEAKAGE

Leakage current

1

µA

Maximum sink current

LEDA1...B6

I_MAX

50

mA

I_OUT

Output current accuracy⁽⁵⁾

Output current set to 23 mA.

Current scale set to 23 mA. PWM =

100%

–4%

4%

5%

(5)

I_MATCH

Matching

1%

PFREQ = 000b

PFREQ = 111b

4.9

39.1

ƒ_{LED_PWM}

V_SAT

LED switching frequency

kHz

mV

Output current set to 23 mA

Output current set to 30 mA

200

250

260

340

(6)

Saturation voltage

PWM INTERFACE CHARACTERISTICS

ƒ_PWM

PWM input frequency

Minimum pulse ON time

Minimum pulse OFF time

75

50000

Hz

ns

t_{MIN_ON}

t_{MIN_OFF}

100

Turn-on delay from standby to PWM input active, ON bit written

t_start-up

t_STBY

7

ms

backlight on

high

PWM input low time before entering

standby mode (if PWMSB = 1)

Turn-off delay

52

ƒ_IN< 2.4 kHz

ƒ_IN< 4.8 kHz

ƒ_IN< 9.6 kHz

ƒ_IN< 19.5 kHz

ƒ_IN< 25 kHz

ƒ_IN< 50 kHz

12

11

10

9

PWM_RES

PWM input resolution

bits

8

UNDERVOLTAGE PROTECTION

VDD falling

VDD rising

2.5

2.6

V_UVLO

VDD UVLO threshold voltage

V

LOGIC INTERFACE

Logic Input EN/VDDIO

V_EN/VDDIO

I_I

Supply voltage range

Input current

1.7

5.5

V

20

µA

(5) Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current.

Matching is the maximum difference from the average. For the constant current sinks on the part (OUTA1 to OUTB6), the following are

determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG).

Matching number is calculated: (MAX-MIN)/AVG. The typical specification provided is the most likely norm of the matching figure for all

parts. LED current sinks were characterized with 1 V headroom voltage. Note that some manufacturers have different definitions in use.

(6) Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at 1 V.

6

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

Electrical Characteristics⁽¹⁾⁽²⁾(continued)

Limits apply over the full ambient temperature range –40°C ≤ T_A≤ 85°C. Unless otherwise specified: VDD = 3.6 V, EN/VDDIO

= 1.8 V, L1 = L2 = 6.8 µH, C_{IN_A}= C_{IN_B}= 10 µF, C_{OUT_A}= C_{OUT_B}= 10 µF, C_VLDO= 10 µF, C_VDD= 1 µF.⁽³⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Logic Input PWM/INT, FSET/SDA, ISET/SCL

V_IL

V_IH

I_I

Input low level

0.3 x

EN/VDDIO

V

Input high level

0.7 x

EN/VDDIO

V

Input current, VIO = 1.7 V to

5.5 V

-1.0

1.0

0.4

µA

Logic Output FSET/SDA, PWM/INT

V_OLOutput low level

I_PULL-UP= 3 mA

0.3

V

7.6 I²C Serial Bus Timing Parameters (FSET/SDA, ISET/SCL)

MIN

TYP

MAX

UNIT

kHz

μs

f_SCL

1

Clock Frequency

400

Hold Time (repeated) START Condition

Clock Low Time

0.6

1.3

2

μs

3

Clock High Time

600

ns

4

Setup Time for a Repeated START Condition

Data Hold Time

600

ns

5

50

ns

6

Data Setup Time

100

ns

7

Rise Time of SDA and SCL

Fall Time of SDA and SCL

Set-up Time for STOP condition

Bus Free Time between a STOP and a START Condition

20+0.1xC_b

15+0.1xC_b

600

300

ns

8

ns

9

ns

10

1.3

μs

Capacitive Load Parameter for Each Bus Line.

Load of One Picofarad Corresponds to One Nanosecond.

Delay from EN/VDDIO rising to I²C bus active

C_b

10

200

1

ns

t_response

ms

Figure 1. I²C Timing Parameters

Submit Documentation Feedback

7

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

7.7 Typical Characteristics

Measured at room temperature unless otherwise noted. Maximum LED current set to 23 mA per string. DC-DC Efficiency is

defined as P_OUT/P_IN, where P_OUTis total output power measured from boost output(s). LED Drive Efficiency is defined as

P_LED/P_IN, where P_LEDis actual power consumed in LEDs.

94

92

90

88

86

84

82

80

92

90

88

86

84

82

80

Inductor: IHLP2525CZER6R8M01

VIN = 3.0 V

VIN = 3.7 V

VIN = 4.2 V

VIN = 5.4 V

VIN = 7.4 V

VIN = 8.4 V

VIN = 3.0 V

VIN = 3.7 V

VIN = 4.2 V

VIN = 5.4 V

VIN = 7.4 V

VIN = 8.4 V

0

50

100

150

200

250

300

0

20

40

60

80

100

Total Load (mA)

12 x 6 LEDs

Brightness (%)

C001

C002

L = 6.8 µH

+25°C

L = 6.8 µH

12 x 6 LEDs

+25°C

Figure 2. Boost Efficiency

Figure 3. LED Drive Efficiency

95

90

85

80

75

70

Inductor: IHLP2525CZER6R8M01

90

85

80

75

70

VIN = 3.0 V

VIN = 3.7 V

VIN = 4.2 V

VIN = 5.4 V

VIN = 7.4 V

VIN = 8.4 V

VIN = 3.0 V

VIN = 3.7 V

VIN = 4.2 V

VIN = 5.4 V

VIN = 7.4 V

VIN = 8.4 V

0

50

100

150

200

250

300

0

20

40

60

80

100

Total Load (mA)

12 x 7 LEDs

Brightness (%)

C003

C004

L = 6.8 µH

+25°C

L = 6.8 µH

12 x 7 LEDs

+25°C

Figure 4. Boost Efficiency

Figure 5. LED Drive Efficiency

95

90

85

80

75

70

Inductor: IHLP2525CZER6R8M01

90

85

80

75

70

VIN = 3.0 V

VIN = 3.7 V

VIN = 4.2 V

VIN = 5.4 V

VIN = 7.4 V

VIN = 8.4 V

VIN = 3.0 V

VIN = 3.7 V

VIN = 4.2 V

VIN = 5.4 V

VIN = 7.4 V

VIN = 8.4 V

0

50

100

150

200

250

300

0

20

40

60

80

100

Total Load (mA)

12 x 7 LEDs

Brightness (%)

C005

C006

L = 6.8 µH

-40°C

L = 6.8 µH

12 x 7 LEDs

-40°C

Figure 6. Boost Efficiency

Figure 7. LED Drive Efficiency

8

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

Typical Characteristics (continued)

Measured at room temperature unless otherwise noted. Maximum LED current set to 23 mA per string. DC-DC Efficiency is

defined as P_OUT/P_IN, where P_OUTis total output power measured from boost output(s). LED Drive Efficiency is defined as

P_LED/P_IN, where P_LEDis actual power consumed in LEDs.

95

90

85

80

75

70

95

90

85

80

75

70

Inductor: IHLP2525CZER6R8M01

VIN = 3.0 V

VIN = 3.7 V

VIN = 4.2 V

VIN = 5.4 V

VIN = 7.4 V

VIN = 8.4 V

VIN = 3.0 V

VIN = 3.7 V

VIN = 4.2 V

VIN = 5.4 V

VIN = 7.4 V

VIN = 8.4 V

0

50

100

150

200

250

300

0

20

40

60

80

100

Total Load (mA)

Brightness (%)

C007

C008

L = 6.8 µH

12 x 7 LEDs

+85°C

L = 6.8 µH

12 x 7 LEDs

+85°C

Figure 8. Boost Efficiency

Figure 9. LED Drive Efficiency

95

90

Inductor: FDSD0415-H-4R7M

88

86

84

82

80

78

76

74

72

70

90

85

80

75

70

VIN = 3.0 V

VIN = 3.7 V

VIN = 4.2 V

VIN = 5.4 V

VIN = 7.4 V

VIN = 8.4 V

VIN = 3.0 V

VIN = 3.7 V

VIN = 4.2 V

VIN = 5.4 V

VIN = 7.4 V

VIN = 8.4 V

0

50

100

150

200

250

300

0

20

40

60

80

100

Total Load (mA)

12 x 6 LEDs

Brightness (%)

C009

C010

L = 4.7 µH

+25°C

L = 4.7 µH

12 x 6 LEDs

+25°C

Figure 10. Boost Efficiency

Figure 11. LED Drive Efficiency

95

90

88

86

84

82

80

78

76

74

72

70

Inductor: FDSD0415-H-4R7M

90

85

80

75

70

VIN = 3.0 V

VIN = 3.7 V

VIN = 4.2 V

VIN = 5.4 V

VIN = 7.4 V

VIN = 8.4 V

VIN = 3.0 V

VIN = 3.7 V

VIN = 4.2 V

VIN = 5.4 V

VIN = 7.4 V

VIN = 8.4 V

0

50

100

150

200

250

300

0

20

40

60

80

100

Total Load (mA)

12 x 7 LEDs

Brightness (%)

C011

C012

L = 4.7 µH

+25°C

L = 4.7 µH

12 x 7 LEDs

+25°C

Figure 12. Boost Efficiency

Figure 13. LED Drive Efficiency

Submit Documentation Feedback

9

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

Typical Characteristics (continued)

Measured at room temperature unless otherwise noted. Maximum LED current set to 23 mA per string. DC-DC Efficiency is

defined as P_OUT/P_IN, where P_OUTis total output power measured from boost output(s). LED Drive Efficiency is defined as

P_LED/P_IN, where P_LEDis actual power consumed in LEDs.

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

8

7

6

5

4

3

2

1

0

+25 °C

±40 C

+85 °C

Inductor: IHLP2525CZER6R8

+25 °C

±40 C

+85 °C

Inductor: IHLP2525CZER6R8

20 40

0

20

40

60

80

100

0

60

80

100

Brightness (%)

C013

C014

VDD = 3.7 V

12 x 7 LEDs

VDD = 3.7 V

12 x 7 LEDs

Figure 14. LED Current Mismatch

Figure 15. VDD Current vs. Load

140

120

100

80

60

50

40

30

20

10

0

5 mA

Phase

Gain

10 mA

15 mA

20 mA

23 mA

25 mA

30 mA

50 mA

60

40

20

0

±20

1000

10000

100000

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Frequency (Hz)

Headroom Voltage (V)

C015

C016

L = 4.7 µH

VDD = 3.7V

V_BOOST= 23 V

+25°C

VDD = 3.7 V

I_OUT= 138 mA/boost

Figure 17. LED Current Vs. Headroom Voltage

Figure 16. Typical Boost Converter Gain and Phase Plot

60

50

40

30

20

10

0

5 mA

10 mA

15 mA

20 mA

23 mA

25 mA

30 mA

50 mA

5 mA

10 mA

15 mA

20 mA

23 mA

25 mA

30 mA

50 mA

50

40

30

20

10

0

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Headroom Voltage (V)

C017

C018

-40°C

VDD = 3.7 V

+85°C

VDD = 3.7 V

Figure 18. LED Current Vs. Headroom Voltage

Figure 19. LED Current Vs. Headroom Voltage

10

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

8 Detailed Description

8.1 Overview

The LP8555 is a white LED driver featuring an asynchronous boost converter and 12 high-precision current sinks

that can be controlled by a PWM input signal, an I²C master, or both. The boost converter uses adaptive output

voltage control for setting the optimal LED driver voltages as high as 28 V. This feature minimizes the power

consumption by adjusting the voltage to the lowest sufficient level under all conditions. The converter can

operate at two switching frequencies: 500 and 1000 kHz pre-configured via EPROM.

Proprietary Hybrid PWM and Current Dimming mode allows higher system power saving. In addition, phase-

shifted LED PWM dimming allows reduced audible noise and smaller boost output capacitors.

The LP8555 has a full set of safety features that ensure robust operation of the device and external components.

The set consists of input undervoltage lockout, thermal shutdown, overcurrent protection, four levels of

overvoltage protection, and LED open and short detection.

8.2 Functional Block Diagram

V_BATT

VDD

SW_A

FB_A

LP8555

VLDO

LDO

Boost Converter Bank A

PWM Control

Reference

Voltage

Switching

Frequency

500, 1000 kHz

Thermal

Shutdown

GND_SW_A

Oscillator

EN/VDDIO

POR

EPROM

UVLO

Headroom

Control

Fault Detection

(Open LED, Over-

current, Over-voltage)

LED Current Sinks

LEDA1

LEDA2

PWM/INT

LEDA3

LEDA4

LEDA5

LEDA6

PWM Detector

R_FSET

FSET/SDA

ISET/SCLK

I²C Slave

R_ISET

LEDB1

LEDB2

PWM Generator

ADCs for LED

Current and PWM/

Boost Frequency

Selection

PWM & Current

Dimming Control

LEDB3

LEDB4

LEDB5

LEDB6

Boost Converter Bank B

GND_SW_B

Switching

Frequency

500, 1000 kHz

PWM Control

Headroom

Control

V_BATT

SW_B

FB_B

Submit Documentation Feedback

11

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

8.3 Features Description

8.3.1 Boost Converter Overview

8.3.1.1 Operation

The boost DC/DC converters generate 7-V to 28-V boost output voltage from a 2.7-V to 20-V boost input voltage

(input voltage must be lower than V_BOOST). The maximum boost output voltage can be set digitally by pre-

configuring EPROM memory (VMAX field).

The converter is a magnetic switching PWM mode DC/DC boost converter with a current limit. It uses CPM

(current programmed mode) control, where the inductor current is measured and controlled with the feedback.

During start-up, the soft-start function reduces the peak inductor current. Figure 20 shows the boost block

diagram.

FB

SW

Startup

Light

Load

OVP

R

VREF

+

g_m

-

+

R

S

R

-

Boost Output

Voltage

Switch

Driver

Adjustment

Osc/

Ramp

OCP

+

-

Figure 20. Boost Converter Functional Block Diagram

Both boost converters are operating at 180° phase shift to reduce current spikes from the input rail and EMI.

8.3.1.2 Protection

Three different protection schemes are implemented:

1. Overvoltage protection, limits the maximum output voltage:

–

Overvoltage protection limit changes dynamically based on output voltage setting. If the boost voltage is

over 1.6 V higher than the adaptive control set value, the boost will stop switching.

Keeps the output below breakdown voltage. The output voltage control limits the boost maximum voltage

to 18...28 V (EPROM programmable).

Prevents boost operation if battery voltage is much higher than desired output.

2. Overcurrent protection, limits the maximum inductor current to 3.1 A (EPROM programmable).

3. Duty cycle limiting.

8.3.1.3 Setting Boost Switching Frequency

The LP8555 boost converter switching frequency can be set by pre-configuring EPROM memory with the choice

of boost frequency (BFREQ field). Table 1 summarizes setting of the switching frequency.

Table 1. Setting Boost Switching Frequency

BFREQ

ƒ_SW[kHz]

500

0

1

1000

12

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

8.3.1.4 Adaptive Boost Output Voltage Control

The boost converters operate in adaptive voltage control mode in typical application. The voltages at the LED

terminals is monitored by the control loop. It raises the boost voltage when the measured voltage of ANY of the

LED strings in a bank falls below the voltage threshold of its corresponding LOW comparator. If the headrooms

of ALL of the LED strings in a bank are above the voltage threshold of their corresponding MID comparator, then

the boost voltage is lowered. Both banks have independent boost voltage control to save power in case of Vf

mismatch between LED strings.

The initial boost voltage is configured with the VINIT field. The VMAX field sets the maximum boost voltage.

When an LED terminal is open, the monitored voltage will never have enough headroom and the adaptive mode

control loop will keep raising the boost voltage. The VMAX field allows the boost voltage to be limited to stay

under the voltage rating of the external components.

Driver

Headroom

V_BOOST

VOUT_A

Time

Figure 21. Boost Adaptive Control Principle for Bank A Boost Converter With Phase Shifted Outputs

8.3.1.5 EMI Reduction

The LP8555 features three EMI reduction schemes.

First scheme, Programmable Slew Rate Control, uses a combination of four drivers for boost switch. Enabling all

four drivers allows boost switch on/off transition times to be the shortest. On the other hand, enabling just one

driver allows boost switch on/off transition times to be the longest. The longer the transition times, the lower the

switching noise on the SW node. It should also be noted that the shortest transition times bring the best

efficiency as the switching losses are the lowest. Same controls effect both boost converters.

The second EMI reduction scheme is the Spread Spectrum Scheme which deliberately spreads the frequency

content of the boost switching waveform, which inherently has a narrow bandwidth, makes the switching

waveform's noise spectrum bandwidth wider and ultimately reduces its EMI spectral density.

The third feature for reducing EMI is Phase Shifted Clocking mode, where boost converters’ clocks are operating

180° phase shifted. This prevents boost switches switching on at the same time when operating in PWM mode.

This reduces input rail load transient spikes caused by boost inductor current and gate driver currents.

Slew Rate Control,

Programmable

Duty Cycle D = 1 - V_IN/ V_OUT

Spread Spectrum Scheme,

Programmable Pseudo Random SW

Frequency Changes to Reduce EMI

t_SW= 1 / f_SW

f_SW= 500 or 1000 kHz

Figure 22. Boost Converter EMI Reduction Schemes

Submit Documentation Feedback

13

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

8.3.2 Brightness Control

The brightness can be controlled using an external PWM signal or the Brightness registers accessible via an I²C

interface, or both. Which of these two input sources are selected is set by the BRTMODE EPROM bits. How the

brightness is controlled in each of the four possible modes is described in the following sections.

8.3.2.1 PWM Input Duty Measurement

When using PWM input for brightness control the input PWM duty cycle is measured as described in following

diagram and the brightness is controlled based on the result. When changing the brightness it must be noted that

the measurement cycle is from rising edge to next rising edge and brightness change must be done accordingly

(time from rising to rising edge is constant (=cycle time) and falling edge defines the brightness).

Cycle Time

t_PWM

Cycle Time

t_PWM

t_ON

Duty =

PWM/INT

t_PWM

Change in Duty

on this Edge

On-time

t_ON1

On-time

t_ON2

Figure 23. PWM Input Duty Cycle Measurement

8.3.2.2 BRTMODE = 00

With BRTMODE = 00, the LED output current is controlled by the PWM input duty cycle. The PWM detector

block measures the duty cycle at the PWM/INT terminal and uses it to generate a PWM-based brightness code.

Before the output is generated, the code goes through the curve Shaper block. Then the code goes into the

Hybrid PWM and Current Dimming block which determines the range of the PWM and Current control. The

outcome of the Hybrid PWM and Current Dimming block is Current and/or up to 6 PWM output signals.

MAXCURR

CURRENT

Hybrid PWM

PWM Input

PWM Detector

Curve Shaper

and Current

Dimming

PWM

Generator

PWM

THRESHOLD

Figure 24. BRTMODE = 00 Brightness Control

14

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

8.3.2.3 BRTMODE = 01

With BRTMODE = 01, the LED output current is controlled by the BRTHI/BRTLO registers. Before the output is

generated the BRTHI/BRTLO registers-based brightness code goes through the Curve Shaper block. Then the

code goes into the Hybrid PWM and Current Dimming block which determines the range of the PWM and

Current control. The outcome of the Hybrid PWM and Current Dimming block is Current and/or up to 6 PWM

output signals.

MAXCURR

CURRENT

Hybrid PWM

and Current

Dimming

I²C Input

Brightness

Curve Shaper

PWM

Generator

PWM

THRESHOLD

Figure 25. BRTMODE = 01 Brightness Control

8.3.2.4 BRTMODE = 10

With BRTMODE = 10, the LED output current is controlled by PWM input duty cycle and the BRTHI/BRTLO

registers. The PWM detector block measures the duty cycle at the PWM/INT terminal and uses it to generate

PWM-based brightness code. Before the code is multiplied with the BRTHI/BRTLO registers-based brightness

code, it goes through the Curve Shaper block. After the multiplication, the resulting code goes into the Hybrid

PWM and Current Dimming block which determines the range of the PWM and Current control. The outcome of

the Hybrid PWM and Current Dimming block is Current and/or up to 6 PWM output signals.

MAXCURR

I²C Input

Brightness

CURRENT

PWM

Hybrid PWM

and Current

Dimming

PWM Input

PWM Detector

Curve Shaper

PWM

Generator

THRESHOLD

Figure 26. BRTMODE = 10 Brightness Control

Submit Documentation Feedback

15

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

8.3.2.5 BRTMODE = 11

With BRTMODE = 11, the LED output current is controlled by the PWM input duty cycle and the BRTHI/BRTLO

registers. The PWM detector block measures the duty cycle at the PWM/INT terminal and uses it to generate

PWM-based brightness code. In this mode, the BRTHI/BRTLO registers-based brightness code goes through the

Curve Shaper block before it is multiplied with the PWM input duty cycle-based brightness code. After the

multiplication, the resulting code goes into the Hybrid PWM and Current Dimming block which determines the

range of the PWM and Current control. The outcome of the Hybrid PWM and Current dimming block is Current

and/or up to 6 PWM output signals.

MAXCURR

I²C Input

Brightness

Curve Shaper

CURRENT

PWM

Hybrid PWM

and Current

Dimming

PWM Input

PWM Detector

PWM

Generator

THRESHOLD

Figure 27. BRTMODE = 11 Brightness Control

16

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

8.3.2.6 Hybrid PWM and Current Dimming Control

Hybrid PWM and Current Dimming control combines PWM dimming and LED current-dimming control methods.

With this dimming control, it is possible to achieve better optical efficiency from the LEDs compared to pure PWM

control while still achieving smooth and accurate control and low brightness levels. The switch point from current-

to-PWM control is set with THRESHOLD EPROM field, available settings are Pure PWM dimming (THRESHOLD

= 111b), 25% switch point (THRESHOLD = 101b) and Pure Current Dimming (THRESHOLD = 000b). 25%

setting allows good compromise between good matching of the LEDs brightness/white point at low brightness

and good optical efficiency.

PWM CONTROL

(THRESHOLD = 111b)

Max Current can be set with <MAXCURR>

EPROM Bits or R

Resistor

ISET

25%

50%

100%

Brightness (Controlled

with PWM Input Duty)

Figure 28.

PWM & CURRENT CONTROL with

Switch Point of 25% of ILED_MAX

(THRESHOLD = 101b)

PWM CONTROL

100%

CURRENT CONTROL

Max Current can be set with <MAXCURR>

EPROM Bits or R

ISET

Resistor

50%

25%

100%

Brightness (Controlled

with PWM Input Duty)

Figure 29.

CURRENT CONTROL

(THRESHOLD = 000b)

CURRENT CONTROL

100%

Max Current can be set with <MAXCURR>

EPROM Bits or R Resistor

ISET

100%

Figure 30.

Submit Documentation Feedback

17

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

8.3.2.7 Setting PWM Dimming Frequency

The LP8555 LED PWM dimming frequency can be set either by an external resistor (PFSET = 1 selection),

R_FSET, or by pre-configuring EPROM memory with the choice of PWM dimming frequency (PFREQ field). Table 2

summarizes setting of the PWM dimming frequency. Setting the PWM dimming frequency using an external

resistor is separately shown in Table 3.

Table 2. Setting PWM Dimming Frequency

PFSET

R_FSET

PFREQ

Don't Care

000

ƒ_PWM[kHz]

See Table 3

4.9

1

0

See Table 3

Don't Care

001

9.8

011

19.5

111

39.1

Table 3. Setting PWM Dimming Frequency With an External Resistor

PFSET

R_FSET[Ω] (Tolerance)

63.4k (±1%)

ƒ_PWM[kHz]

4.9

1

52.3k, 53.6k (±1%)

39.2k (±1%)

9.8

19.5

23.2k (±1%)

39.1

Grounded or floating

19.5

18

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

8.3.2.8 Setting Full-Scale LED Current

The LP8555 full-scale LED current can be set either by an external resistor R_ISET(ISET = 1 selection), or by pre-

configuring EPROM memory with the choice of full-scale LED current (MAXCURR field, ISET = 0). This register

can be also written with I²C before turning on backlight. Table 4 summarizes setting of the full-scale LED current.

Table 4. Setting Full-Scale LED Current

ISET

1

R_ISET[Ω] (Tolerance)

Floating

MAXCURR

Don't Care

000

ILED [mA]

23

5

1

63.4k (±1%)

52.3k, 53.6k (±1%)

44.2k, 45.3k (±1%)

39.2k (±1%)

34.0k (±1%)

30.1k (±1%)

26.1k (±1%)

23.2k (±1%)

0 (grounded)

Don't Care

1

10

15

20

23

25

30

50

23

5

1

0

Don't Care

001

10

15

20

23

25

30

50

0

Don't Care

010

0

Don't Care

011

0

Don't Care

100

0

Don't Care

101

0

Don't Care

110

0

Don't Care

111

Submit Documentation Feedback

19

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

8.3.2.9 Phase-Shift PWM Scheme

The Phase-Shift PWM Scheme (PSPWM) allows delaying of the time when each LED current sink is active.

When the LED current sinks are not activated simultaneously, the peak load current from the boost output is

greatly decreased during PWM dimming. This reduces the ripple seen on the boost output and allows smaller

output capacitors to be used. Reduced ripple also reduces the output ceramic capacitor audible ringing. The

PSPWM scheme also increases the load frequency seen on the boost output by up to six times and therefore

transfers the possible audible noise to the frequencies outside of the audible range.

The phase difference between each active driver is automatically determined and is 360º / number of active

drivers in a bank.

Phase Difference Cycle Time

60 Degrees

1/(f_PWM)

LEDA1

LEDA2

LEDA3

LEDA4

LEDA5

LEDA6

LEDB1

LEDB2

LEDB3

LEDB4

LEDB5

LEDB6

Figure 31. Phase Shifting Example With All 12 Channels Active. (Note: Bank A And Bank B are in the

Same Phase.)

8.3.3 LED Brightness Slopes, Normal and Advanced

The transition time between two brightness values can be programmed with the STEP EPROM field from 0 to

200 ms. The same slope time is used for sloping up and down. With advanced slope the brightness changes can

be made more pleasing to the human eye. It is implemented with a digital smoothing filter. The filter strength is

set with SMOOTH EPROM field.

20

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

Brightness (PWM)

Sloper Input

Time

Brightness (PWM)

PWM Output

Normal Slope

Advanced Slope

Time

tSlope Timet

Figure 32. Sloping Principle

8.3.4 Start-up and Shutdown Sequences

Depending on brightness control mode the LP8555 can be started up or shut down differently. Below are

explained typical start-up/shutdown sequences with corresponding timings for operation states. Diagrams have

more details and illustrated waveforms for typical usage cases.

8.3.4.1 Start-up With PWM Input Brightness Control Mode (BRTMODE = 00b)

When VDD and EN/VDDIO are above min operational value the LP8555 enters start-up mode. During start-up

mode the LDO is started, and EPROM values are read. I²C is available after the start-up sequence has ended.

In standby mode the device waits for the ON bit to go high to start the boost start-up sequence. In standby mode

PWM input duty cycle measurement is active.

Once the ON bit is set to 1 (it can be also programmed to 1 by default in EPROM, and no I²C write is then

needed for entering active mode), boost is started, and device enters active mode with brightness set by PWM

input duty cycle. If no brightness is set, the backlight stays off until two PWM pulses are received in the PWM

input, or if PWM input is set high for more than 1/75 Hz time. Boost starts initially to the level programmed in

EPROM, and after backlight is turned on the adaptive control adjusts the voltage to get to the minimal headroom

voltage.

8.3.4.2 Shutdown With PWM Input Brightness Control Mode (BRTMODE = 00b)

The backlight can be turned off by setting PWM input low or by writing the ON bit low. After a 1/75Hz timeout

period in the PWM input, the backlight slopes down (if slope is enabled), and boost is returned to the initial

voltage level programmed to the EPROM. If the backlight is shut down with the ON bit, it shuts down immediately

even if slopes are enabled and boost turns off as well. To enter standby mode where boost is disabled and the

power consumption is minimal, the ON bit must be written to 0. If PWMSB bit has been programmed to 1, then

the LP8555 enters standby mode when PWM input has been low for more than 50 ms even if the ON bit is high.

The device shuts down completely by setting EN/VDDIO and/or VDD to low state.

Submit Documentation Feedback

21

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

200µs typ.

1ms max

5ms typ.

7ms max

MODE

OFF

STARTUP

STANDBY

BOOST STARTUP

ACTIVE

STANDBY

OFF

UVLO

Timing between these

two signals is not critical

VDD

Timing between these

two signals is not critical

EN/VDDIO

I²C unavailable

ON bit (I²C)

I²C unavailable

Backlight started with

writing ON bit high

2 Full PWM Cycles needed

for sampling PWM input

BRT[11:0] register

1/75Hz timeout

PWM/INT

VLDO

V_INIT

Adaptation to LED V_F

No active discharge

V_BOOSTx

Ramp time and shape

defined in registers

I_{LED_OUTx}

Figure 33. Start-up and Shutdown with PWM Input Control, ON Bit = 0 (BRTMODE = 00b)

200µs typ.

1ms max

5ms typ.

7ms max

MODE

OFF

STARTUP

STANDBY

BOOST STARTUP

ACTIVE

STANDBY

OFF

UVLO

Timing between these

two signals is not critical

VDD

Timing between these

two signals is not critical

EN/VDDIO

I²C unavailable

Note: If PWMSB = 1, then device enters

standby mode after PWM input has been low

for 50ms timeout period even if ON bit is 1.

ON bit (I²C)

I²C unavailable

2 Full PWM Cycles needed

for sampling PWM input

BRT[11:0] register

1/75Hz timeout

PWM/INT

VLDO

V_INIT

Adaptation to LED V_F

No active discharge

V_BOOSTx

Ramp time and shape

defined in registers

I_{LED_OUTx}

Figure 34. Start-up and Shutdown with PWM Input Control, ON Bit = 1 (BRTMODE = 00b)

22

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

8.3.4.3 Start-up With I²C Brightness Control Mode (BRTMODE = 01b)

When VDD and EN/VDDIO are above min operational value, the LP8555 enters start-up mode. During start-up

mode the LDO is started, and EPROM values are read. I²C is available after the start-up sequence has ended.

In standby mode the device waits for the ON bit to go high to start the boost start-up sequence. In standby mode

I²C is active, and brightness / other registers can be written.

Once the ON bit is set to 1 (it can be also programmed to 1 by default in EPROM and no I²C write is then

needed for entering active mode), boost is started, and device enters active mode with brightness set by I²C

brightness registers. If no brightness is set, the backlight stays off until brightness value is written to the I²C

register(s). Boost starts initially to the level programmed in EPROM and, after backlight is turned on, the adaptive

control adjusts the voltage to get to the minimal headroom voltage.

8.3.4.4 Shutdown With I²C Brightness Control Mode (BRTMODE = 01b)

The backlight can be turned off by setting the ON bit low, or by writing brightness to 0. The backlight shuts down

immediately if the ON bit is written low even if slope is enabled. If the backlight is turned off by writing brightness

to 0, brightness control does slope (if enabled), and the boost is returned to the initial voltage level programmed

to EPROM. To enter standby mode where boost is disabled and the power consumption is minimal, the ON bit

must be written to 0.

The device shuts down completely by setting EN/VDDIO and/or VDD to low state.

200µs typ.

1ms max

5ms typ.

7ms max

MODE

OFF

STARTUP

STANDBY

BOOST STARTUP

ACTIVE

STANDBY

OFF

VDD

Timing between these

two signals is not critical

Timing between these

two signals is not critical

EN/VDDIO

I²C unavailable

ON bit (I²C)

I²C unavailable

Brightness value can be also written after ON bit is

high. Boost is enabled anyway after writing ON bit high

BRT[11:0] register

RESET

PWM/INT

VLDO

V_INIT

Adaptation to LED V_F

No active discharge

Ramp time and shape

V_BOOSTx

defined in registers

I_{LED_OUTx}

Figure 35. Start-up And Shutdown With I²C Brightness Control Mode (BRTMODE = 01b)

Submit Documentation Feedback

23

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

8.3.4.5 Start-up with I²C + PWM Input Brightness Control Mode (BRTMODE = 10 or 11b)

When VDD and EN/VDDIO are above min operational value, the LP8555 enters start-up mode. During start-up

mode the LDO is started, and EPROM values are read. I²C is available after the start-up sequence has ended.

In standby mode the device waits for the ON bit to go high to start the boost start-up sequence. In standby mode

I²C registers can be written and PWM input duty cycle measurement is active.

Once the ON bit is set to 1 (it can be also programmed to 1 by default in EPROM and no I²C write is then

needed for entering active mode), boost is started, and device enters active mode with brightness set by PWM

input duty cycle multiplied by I²C brightness register value. If no brightness is set, the backlight stays off until I²C

brightness register receives value and two PWM pulses are received in the PWM input, or if PWM input is set

high for more than 1/75 Hz time. Boost starts initially to the level programmed in EPROM and after backlight is

turned on, the adaptive control adjusts the voltage to get to the minimal headroom voltage.

8.3.4.6 Shutdown with I²C + PWM Input Brightness Control Mode (BRTMODE = 10 or 11b)

The backlight can be turned off by setting the ON bit low, or by setting brightness to 0 either by PWM input

(same 1/75 Hz timeout applies here as in PWM input control mode) or by I²C brightness register writes. The

backlight shuts down immediately if the ON bit is written low even if slope is enabled. If the backlight is turned off

by setting brightness to 0, brightness control does slope (if enabled, depending on which input is used – see

brightness control modes for details), and the boost is returned to the initial voltage level programmed to

EPROM. To enter standby mode where boost is disabled and the power consumption is minimal, the ON bit

must be written to 0.

The device shuts down completely by setting EN/VDDIO and/or VDD to low state.

200µs typ.

1ms max

5ms typ.

7ms max

MODE

OFF

STARTUP

STANDBY

BOOST STARTUP

ACTIVE

STANDBY

OFF

VDD

Timing between these

two signals is not critical

Timing between these

two signals is not critical

EN/VDDIO

I²C unavailable

ON bit (I²C)

I²C unavailable

BRT[11:0] register

multiplied with

PWM input duty

Brightness value can be also set after ON bit is high.

Boost is enabled anyway after writing ON bit high

RESET

VLDO

V_INIT

Adaptation to LED V_F

No active discharge

Ramp time and shape

V_BOOSTx

defined in registers

I_{LED_OUTx}

Figure 36. Start-up and Shutdown with I²C + PWM Input Brightness Control (BRTMODE = 01b)

24

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

8.3.5 LED String Count Auto Detection

The LP8555 can be pre-configured to auto-detect the number of the LED strings attached. If the CONFIG.AUTO

bit is set to 1, the LP8555 will automatically remove the unused current sink and adjust phasing of the remaining

current sinks. The LED OPEN fault condition will not be set in this mode.

8.3.6 Fault Detection

The LP8555 has fault detection for LED OPEN, LED SHORT, UVLO, BST_OVP, BST_OCP, BST_UV and TSD.

Faults are recorded in the STATUS register. Each time the STATUS register is read, it is automatically cleared.

When BRTMODE is set to 01b any fault may be enabled to cause an interrupt on the PWM/INT terminal.

8.3.6.1 LED Short Detection

Voltages at the individual current sinks are constantly monitored for the LED SHORT fault. This fault may occur

when some LEDs in a string are electrically bypassed making that LED string shorter than the other LED strings.

The reduced forward voltage causes the current sink attached to that string to have a higher headroom voltage

than the other current sinks. When the headroom voltage is higher than the fault comparator threshold

(configured with the OV field in the LEDEN register) that current sink is disabled and the PWM phasing is

automatically adjusted. The fault comparator threshold may be configured for 1 V, 2 V, 3 V or 4 V.

8.3.6.2 LED Open Detection

Each current sink is also monitored for an LED OPEN condition. The condition is set when the headroom voltage

on one or more current sinks is below the LOW comparator threshold and the boost voltage is at the maximum.

This fault condition may be caused by one or more OPEN LED strings or by one or more current sinks shorted to

GND.

The AUTO bit of the CONFIG register determines how the LP8555 responds to an LED OPEN condition. If the

CONFIG.AUTO bit is set to 1, the LP8555 will automatically adjust the phasing to remove the current sink with

the LED OPEN condition. In this case the condition is normal and indicates an unpopulated LED string. If the

CONFIG.AUTO bit is set to 0, the LP8555 will immediately shut down the backlight whenever an LED OPEN

condition is detected on any enabled LED drivers. The backlight will not turn on again (regardless of the

COMMAND.ON bit) until the STATUS register is read.

8.3.6.3 Undervoltage Detection

The LP8555 continuously monitors the voltage on the VDD terminal. When the VDD voltage drops below 2.5 V

the backlight will be immediately shut down, and the UVLO bit will be set in the STATUS register. The backlight

will automatically start again when the voltage has increased above 2.5 V + 50 mV hysteresis. Hysteresis is

implemented to avoid continuously triggering undervoltage.

8.3.6.4 Thermal Shutdown

If the internal temperature reaches 150°C, the LP8555 will immediately shut down the backlight to protect it from

damage. The TSD bit will also be set in the STATUS register. The device will re-activate the backlight again

when the internal temperature drops below 137°C (typ).

8.3.6.5 Boost Overcurrent Protection

The LP8555 will automatically limit boost current to 3.1 A (EPROM programmable). When the 3.1-A limit is

reached the BST_OCP bit is set in the STATUS register.

8.3.6.6 Boost Overvoltage Protection

The LP8555 will automatically limit boost voltage to VBOOST_MAX+1.6 V. When the limit is reached the

BST_OVP bit is set in the STATUS register. It is possible to set the limit to four threshold levels programmable

via EPROM bits.

8.3.6.7 Boost Undervoltage Protection

The LP8555 can detect when the boost voltage is below VBOOST – 2.5 V for longer than 6ms. When the

threshold is reached the BST_UV bit is set in the STATUS register.

Submit Documentation Feedback

25

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

8.3.7 I²C-Compatible Serial Bus Interface

8.3.7.1 Interface Bus Overview

The I²C compatible synchronous serial interface provides access to the programmable functions and registers on

the device. This protocol use a two-wire interface for bi-directional communications between the IC’s connected

to the bus. The two interface lines are the Serial Data Line (FSET/SDA), and the Serial Clock Line (ISET/SCL).

These lines should be connected to a positive supply, via a pull-up resistor and remain HIGH even when the bus

is idle.

Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on

whether it generates or receives the serial clock (ISET/SCL). The LP8555 is always a slave device.

See the LP8555EVM User Guide for full register map details and programming considerations.

8.3.7.2 Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock

(SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the

SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New

data should be sent during the low SCL state. This protocol permits a single data line to transfer both

command/control information and data using the synchronous serial clock.

SDA

SCL

Data Line

Stable:

Data Valid

Change

of Data

Allowed

Figure 37. Bit Transfer

Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a

Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is

transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following

sections provide further details of this process.

Data Output

by

Transmitter Stays Off the

Bus During the

Transmitter

Acknowledgment Clock

Data Output

by

Receiver

Acknowledgment

Signal From Receiver

SCL

3 - 6

1

2

7

8

9

S

Start

Condition

Figure 38. Start And Stop

The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start

Condition is generated, the bus is considered busy and it retains this status until a certain time after a Stop

Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a

Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition.

26

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

SDA

SCL

S

P

Start

Stop

Condition

Figure 39. Start And Stop Conditions

In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction.

This allows another device to be accessed, or a register read cycle.

8.3.7.3 Acknowledge Cycle

The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte

transferred, and the acknowledge signal sent by the receiving device.

The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter

releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver

must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the

high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to

receive the next byte.

8.3.7.4 “Acknowledge After Every Byte” Rule

The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge

signal after every byte received.

There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must

indicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clocked

out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the

master), but the SDA line is not pulled down.

8.3.7.5 Addressing Transfer Formats

Each device on the bus has a unique slave address. The LP8555 operates as a slave device with 7-bit address

combined with data direction bit. Slave address is 2Ch as 7-bit or 58h for write, and 59h for read in an 8-bit

format.

Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device

should send an acknowledge signal on the SDA line, once it recognizes its address. The slave address is the

first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the

slave address — the eighth bit.

When the slave address is sent, each device in the system compares this slave address with its own. If there is a

match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the

R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver.

MSB

LSB

ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 R/W

Bit7

x

bit6

bit5

x

bit4

x

bit3

x

bit2

x

bit1

x

bit0

x

2

I C SLAVE address (chip address)

Figure 40. I²C Slave Address

Submit Documentation Feedback

27

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

8.3.7.6 Control Register Write Cycle

•

Master device generates start condition.

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

Slave device sends acknowledge signal if the slave address is correct.

Master sends control register address (8 bits).

Slave sends acknowledge signal.

Master sends data byte to be written to the addressed register.

Slave sends acknowledge signal.

If master will send further data bytes, the control register address will be incremented by one after

acknowledge signal.

•

Write cycle ends when the master creates stop condition.

8.3.7.7 Control Register Read Cycle

•

Master device generates a start condition.

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

Slave device sends acknowledge signal if the slave address is correct.

Master sends control register address (8 bits).

Slave sends acknowledge signal.

Master device generates repeated start condition.

Master sends the slave address (7 bits) and the data direction bit (r/w = 1).

Slave sends acknowledge signal if the slave address is correct.

Slave sends data byte from addressed register.

If the master device sends acknowledge signal, the control register address will be incremented by one. Slave

device sends data byte from addressed register.

•

Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop

condition.

ADDRESS MODE

Data Read

Data Write

<Slave Address><r/w = '0'>[Ack]

<Register Addr.>[Ack]

<Slave Address><r/w = '1'>[Ack]

[Register Data]<Ack or Nack>...additional reads from subsequent register address possible

<Slave Address><r/w = '0'>[Ack]

<Register Addr.>[Ack]

<Register Data>[Ack]...additional writes to subsequent register address possible

<> Data from master; [ ] Data from slave.

Slave Address

Control Register Add.

(8 bits)

Register Data

(8 bits)

S

'0' A

A

A P

(7 bits)

Data transfered,

byte + Ack

R/W

From Slave to Master

From Master to Slave

A - ACKNOWLEDGE (SDA Low)

S - START CONDITION

P - STOP CONDITION

Figure 41. Register Write Format

28

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

Slave Address

(7 bits)

Slave Address

(7 bits)

Data- Data

(8 bits)

Control Register Add.

(8 bits)

A/

NA

S

'0' A

A Sr

'1' A

P

Data transfered, byte +

Ack/NAck

R/W

Direction of the transfer

will change at this point

From Slave to Master

From Master to Slave

A

- ACKNOWLEDGE (SDA Low)

NA - ACKNOWLEDGE (SDA High)

- START CONDITION

Sr - REPEATED START CONDITION

- STOP CONDITION

S

P

Figure 42. Register Read Format

8.4 Device Functional Modes

8.4.1 Operation Without I²C Control

The device can operate without I²C control in applications where I²C bus is not available. Special EPROM

configuration is needed for this setup. In this mode the EN/VDDIO terminal enables the device, and PWM input

duty cycle adjusts the brightness. Slopes, PSPWM modes, different boost modes etc. are predefined in the

EPROM which device loads at start-up. FSET/SDA and ISET/SCL terminals can be used to set the PWM

frequency and LED current based on specific needs (see corresponding sections for setting the frequency and

current), without needing separate EPROM configuration for each application. The backlight start-up happens

when EN/VDDIO terminal is high and PWM input receives measurable duty cycle. If the PWMSB bit is set 1 in

EPROM, the device enters standby mode automatically when PWM/INT is set low. If PWMSB is 0, the device is

shut down setting EN/VDDIO low. See start-up and shutdown diagrams for more details.

8.4.2 Operation With I²C Control

With I²C control, user may set the device configuration more freely and have additional I²C brightness control.

The backlight brightness can be controlled with either PWM input, with I²C, or a combination of both.

Configuration for slopes, PSPWM, or different boost modes can be used from EPROM defaults, or user can set

own configuration before backlight is turned on. Configuration setting is done when EN/VDDIO is high (I²C is

active) and the ON bit is low. R_FSETand R_ISETresistors cannot be used in I²C control mode, because they are

multiplexed as the I²C bus terminals (SDA/SCL). The backlight is started by setting the ON bit high, and

shutdown is done by setting ON bit low. See start-up and shutdown diagrams for more details. Details of the I²C

registers and programming considerations are seen in the LP8555EVM User Guide.

8.4.3 Shutdown Mode

The device is in shutdown mode when the EN/VDDIO terminal is low. the EN/VDDIO terminal enables an LDO,

which is used for powering internal logic and analog blocks. Current consumption in this mode from VDD terminal

is <1 µA.

8.4.4 Standby Mode

In standby mode the EN/VDDIO terminal is set high (with VDD power present), and logic is powered from an

LDO. The device goes through the start-up sequence where NVM (EPROM) is loaded to the registers. I²C is

available in standby mode, and register settings can be changed. Current consumption is < 30 µA in this mode

from VDD terminal.

8.4.5 Active Mode

In active mode the backlight is enabled either with setting the ON register bit high (I²C control mode) or by

activating PWM input. The EN/VDDIO terminal must be high, and VDD must be present. Brightness is controlled

with I²C writes to brightness registers or by changing PWM input duty cycle (operation without I²C control).

Configuration registers are not accessible in Active mode to prevent damage to the device by accidental writes.

Current consumption from VDD terminal in this mode is typically 4.2 mA when LEDs are not drawing any current.

Submit Documentation Feedback

29

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

Some register fields are loaded from an internal EPROM (shaded above). This EPROM is programmed by TI

during final test. This allows default values to be assigned. This feature is intended for applications where the I²C

interface is not used. With the exception of the ID fields, all EPROM based fields can be written via I²C writes like

a normal register field. There are limitations on certain configuration bits, their operation and can they be

changed "on-the-fly". It is noted in the description of corresponding bit.

8.5.1 COMMAND

Address: 0x00

D7

D6

D5

D4

D3

D2

D1

D0

RESET

—

SREN

SSEN

ON

Bits

Field

RESET

reserved

SREN

Type

Description

7

6:3

2

R/W

R/O

R/W

Write 1 to reset the device. This bit is self-cleaning and will always be 0 when read.

0 = Slew rate limited disabled

1 = Enable slower boost gate drive slew rate. Reduces EMI energy in high frequencies and reduces

boost efficiency.

1

0

SSEN

ON

R/W

0 = Spread Spectrum Scheme disabled

1 = Enable spread-spectrum boost clocking. Spreads EMI spectrum spikes.

Turn on the backlight.

0 = backlight off

1 = backlight on

The COMMAND.ON bit must be programmed to 1 in the EPROM for applications without I²C access to the

device. The COMMAND.SSEN bit may be updated at any time. It is not necessary for the backlight to be off

when changing COMMAND.SSEN and/or COMMAND.SREN.

Submit Documentation Feedback

31

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

8.5.2 STATUS/MASK

Address: 0x01/0x02

D7

D6

D5

—

D4

D3

D2

D1

D0

DRV_FAULT

DRV_OV

BST_UV

BST_OVP

BST_OCP

TSD

UVLO

Bits

Field

Type

Description

An open/short condition was detected on one or more LED strings. Once set this bit will stay set until the

7

LED_OPEN

R/O

STATUS register is read. An LED open/short condition will turn off the backlight when CONFIG.AUTO is

0.

An overvoltage condition was detected on one or more LED strings. Once set this bit will stay set until

the STATUS register is read.

6

5

4

LED_OV

reserved

BST_UV

R/O

The boost reported an undervoltage condition. Once set this bit will stay set until the STATUS register is

read.

The boost reported an overvoltage protection condition when the maximum allowed voltage is

requested. Once set this bit will stay set until the STATUS register is read.

3

2

1

BST_OVP

BST_OCP

TSD

R/O

The boost reported an undervoltage condition longer than 50 ms in time when the backlight on.

A thermal shutdown condition was detected. Once set this bit will stay set until the STATUS register is

read. A thermal shutdown condition will turn off the backlight.

An undervoltage lockout condition was detected. Once set this bit will stay set until the STATUS register

is read. An undervoltage lockout condition will turn off the backlight.

0

UVLO

R/O

Each fault bit of the STATUS register has a corresponding bit in the MASK register, which enables interrupts for

the fault. For example, an interrupt will occur if the MASK.BST_UV and STATUS.BST_UV bits are both set. If a

fault bit is cleared in the MASK register then that fault will not trigger an interrupt.

32

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

8.5.3 BRTLO

Address: 0x03

D7

D6

D5

D4

D3

D2

D1

D0

BRT[3:0]

Type

RESERVED

Bits

7:4

Field

Description

BRT[3:0]

reserved

R/W

R/O

Least significant bits of the brightness level.

3:0

8.5.4 BTHI

Address: 0x04

D7

D6

D5

D4

D3

D2

D1

D0

BRT[11:4]

Bits

Field

BRT[11:4]

Type

Description

7:0

R/W

Most significant bits of the brightness level.

The brightness level can be updated with 8-bit precision or 12-bit precision. To make brightness level updates

effective the internal brightness level is only updated when the BRTHI register is written. If the BRTHI register is

written without a previous write to the BRTLO register, then the lower 4 bits of the internal 12-bit brightness will

be synthesized from the BRTHI register value.

BRTLO

write 0x95

write 0x10

no write

BRTHI

Brightness

0xFC9

0xDC1

0x8C8

Comments

write 0xFC

write 0xDC

write 0x8C

write 0x0C

write 0x00

write 0xFF

BRTLO[3:0] is ignored

set to an exact 12-bit value

synthesize low order bits

0% brightness

no write

0x0C0

no write

0x000

no write

0xFFF

100% brightness

Submit Documentation Feedback

33

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

8.5.5 CONFIG

Address: 0x10

D7

D6

PWMFILT

Field

D5

EN_BPHASE180 RESERVED

Type

D4

D3

D2

D1

D0

PWMSB

RELOAD

AUTO

BRTMODE

Bits

Description

Enables PWM standby mode

7

6

PWMSB

R/W

0 = CONTROL.ON alone turns the backlight on/off

1 = turn off the backlight after 50 ms of PWM low

0 = PWM input filter disabled

1 = Enable 50 ns glitch filter on PWM input.

PWMFILT

0 = Boosts operate in same phase

1 = Enable 180° phase shift between the 2 boost switchers.

5

4

EN_BPHASE180

reserved

R/W

R/O

Automatically re-read the EPROM at each turn-on.

0 = only read the EPROM upon power-up

1 = re-read the EPROM when the backlight turns on

3

2

RELOAD

AUTO

R/W

Automatic LED string configuration

0 = enable LED strings using just LEDEN.ENABLE

1 = disable all open LED strings

Brightness mode

00 = PWM

1:0

BRTMODE

R/W

01 = BRTHI/BRTLO registers

10 = PWM × unshaped BRTHI/BRTLO registers

11 = BRTHI/BRTLO registers × unshaped PWM

When the AUTO bit is set the LED configuration is done dynamically. When an OPEN/SHORT condition is

detected on an LED string it will be removed, and PWM output phasing will be adjusted. Conversely, an LED

string will be added back for operation if the LED string is not open.

The BRTMODE field selects how LED brightness is controlled. When BRTMODE is set to 00b the PWM/INT

terminal duty cycle controls the LED brightness. When BRTMODE is set to 01b the BRTLO and BRTHI registers

will control the LED brightness. When the backlight is turned on the brightness level is reset to 0% and will

automatically transition to the brightness value programmed in the BRTLO and BRTHI registers.

When the BRTMODE field is set to 00b, and the PWMSB bit is set to 1, the backlight will be turned off whenever

the PWM/INT terminal is held low for 50 ms. This will also put the device into its lowest power state. When the

PWM/INT terminal becomes active the backlight will automatically turn back on.

A 50 ns glitch filter will be applied to the PWM input signal when the PWMFILT bit is set to 1. When BRTMODE

is set to 10b or 11b the LED brightness is controlled by both the PWM/INT terminal duty cycle and the BRTLO

and BRTHI registers.

When BRTMODE is set to 10b the PWM/INT terminal duty cycle is routed through the smoothing function

(controlled via the STEP register). The smoothed duty cycle is multiplied with the value from the BRTLO/BRTHI

registers. Updates to the BRTLO/BRTHI registers have an immediate effect on the LED brightness, while

PWM/INT terminal duty cycle changes may be smoothed.

When BRTMODE is set to 11b the BRTLO/BRTHI register value is routed through the smoothing function. The

smoothed brightness level is multiplied with the PWM/INT terminal duty cycle. In this configuration PWM/INT

terminal duty cycle changes have an immediate effect on the LED brightness, while BRTLO/BRTHI register

changes may be smoothed.

34

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

8.5.6 CURRENT

Address: 0x11

D7

D6

D5

D4

D3

D2

D1

MAXCURR

D0

ISET

—

Bits

Field

ISET

Type

Description

0 = LED maximum current set with MAXCURR bits

1 = Set MAXCURR via the ISET/SCL terminal. This terminal should only set to 1 as an EPROM default,

writing to this bit "on-the-fly" does not have effect. Resistor values and their corresponding LED current

setting is seen in Full-Scale LED Current section.

7

R/W

R/O

6:3

reserved

Full-scale current, 100% brightness (typical).

000 = 5 mA

001 = 10 mA

010 = 15 mA

2:0

MAXCURR

R/W

011 = 20 mA

100 = 23 mA

101 = 25 mA

110 = 30 mA

111 = 50 mA

The full-scale current can be configured into two different ways: EPROM or ISET/SCL terminal. The ISET/SCL

terminal resistor is automatically measured during start-up. The CURRENT.ISET bit is used to select between

the maximum current value measured from the ISET/SCL terminal and the EPROM value. When the ISET bit is

set to 1 the ISET/SCL terminal value is used; otherwise the EPROM value is used. Regardless of EPROM

programming, the maximum current can always be configured from I²C by clearing the CURRENT.ISET bit and

configuring the CURRENT.MAXCURR field as needed.

When the CURRENT register is read via I²C the MAXCURR field will contain the active full-scale current value.

To read the EPROM value the ISET bit must be set to 0. To read the R_ISETresistor value the ISET bit must be

set to 1 during start-up, which means it must be set in EPROM.

If the ISET/SCL terminal is grounded or floating the MAXCURR value will be set to 23 mA if ISET = 1.

Submit Documentation Feedback

35

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

8.5.7 PGEN

Address: 0x12

D7

D6

RESERVED

D5

D4

D3

D2

D1

D0

PFSET

THRESHOLD

PFREQ

Bits

Field

Type

Description

0 = PWM frequency is set with PFREQ register bits

7

PFSET

R/W

1 = Set PFREQ via the FSET/SDA terminal. This bit should only be set to 1 as an EPROM default,

writing to this bit "on-the-fly" does not have effect. Resistor values and their corresponding frequency

settings are seen in Setting PWM Dimming Frequency section.

6

RESERVED

R/O

R/W

0

Adaptive dimming threshold. PWM dimming is used below the threshold and current dimming is used

above the threshold.

000 = 100% current dimming

101 = PWM below 25% (10-bit PWM)

111 = 100% PWM (12-bit PWM)

5:3

THRESHOLD

PWM output frequency (typical)

000 = 4.9 kHz

2:0

PFREQ

R/W

001 = 9.8 kHz

011 = 19.5 kHz

111 = 39.1 kHz

The output PWM frequency can be configured in two different ways: EPROM or FSET/SDA terminal. The

FSET/SDA terminal is always automatically measured. The PGEN.PFSET bit is used to select between the PWM

frequency value measured from the FSET/SDA terminal and the EPROM value. When the PFSET bit is set to 1

the FSET/SDA terminal value is used; otherwise the EPROM value is used. Regardless of EPROM

programming, the PWM frequency can always be configured from I²C by clearing the PGEN.PFSET bit and

configuring the PGEN.PFREQ field as needed.

Full 12-bit precision is achieved in all adaptive dimming thresholds and PWM output frequencies. When the

PGEN register is read via I²C the PFREQ field will contain the active PWM output frequency value. To read the

EPROM value the PFSET bit must be set to 0. To read the R_FSETresistor value the PFSET bit must be set to 1.

If the FSET/SDA terminal is grounded or floating the PFREQ value will be set to 19.5 kHz.

36

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

8.5.8 BOOST

Address: 0x13

D7

D6

D5

D4

D3

D2

D1

BIND

D0

RESERVED

Field

RESERVED

BFREQ

Bits

7:6

5:4

3:2

Type

Description

RESERVED

R/W

BIND bit is used to set boost inductor size.

0 = 4.7 µH … 6.8 µH

1

BIND

R/W

1 = 10 µH … 22 µH

Boost frequency (typical). This setting must be configured in EPROM, changing it with I2C register write

does not have desired effect.

0 = 500 kHz

0

BFREQ

R/W

1 = 1 MHz

8.5.9 LEDEN

Address: 0x14

D7

D6

D5

D4

D3

D2

D1

D0

OV

Field

ENABLE[6:1]

Bits

7:6

Type

R/W

Description

Set LED overvoltage level (typical).

00 = 1V

01 = 2V

10 = 3V

11 = 4V

OV

5:0

ENABLE

LED string enables for Bank A.

The ENABLE field configures the enabled LED strings. If the CONFIG.AUTO bit is 0 these LED strings will stay

active when the backlight is on. If the CONFIG.AUTO bit is set, then an LED open/short condition will cause that

LED string to be removed. A given LED string will never be enabled if the corresponding bit of the ENABLE field

is set to 0. The OV field configures the threshold for detecting an LED overvoltage condition; which may occur

when one or more LEDs are bypassed (shorted) within an LED string.

Submit Documentation Feedback

37

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

8.5.10 STEP

Address: 0x15

D7

D6

D5

D4

D3

D2

D1

D0

SMOOTH

PWM_IN_HYST

STEP

Bits

Field

Type

Description

Advanced Slope control. Filter strength for digital smoothing filter.

00 = no smoothing

7:6

SMOOTH

R/W 01 = light smoothing

10 = medium smoothing

11 = heavy smoothing

PWM input hysteresis

000 = None

001 = >1 LSB steps

010 = >2 LSB steps

R/W 011 = >4 LSB steps

100 = >8 LSB steps

101 = >16 LSB steps

110 = >32 LSB steps

111 = >64 LSB steps

5:2

PWM_IN_HYST

Linear Sloping time (typical)

000 = 0 ms

001 = 8 ms

010 = 16 ms

2:0

STEP

R/W 011 = 24 ms

100 = 28 ms

101 = 32 ms (12.2 µs / 12-bit LSB)

110 = 100 ms (24.4 µs / 12-bit LSB)

111 = 200 ms (48.8 µs / 12-bit LSB)

The STEP field controls the rate of brightness level changes. Brightness transitions have a fixed step time. The

time required to complete a ramp between two levels is independent upon the difference between the starting

and ending current levels. For example, when STEP is set to 110b a brightness transition between any

brightness values will take 100 ms. The SMOOTH field controls the digital smoothing filter, Advanced Sloping.

This filter behaves much like an RC filter. It can be used to remove the overshoot that appears to occur (for eye)

on large brightness changes. The actual amount of smoothing is tailored for the STEP field setting. For example

medium filter strength is higher for 100 ms ramp times than for 32 ms Linear Sloping times. This gives 32

possible brightness level ramping configurations.

The PWM detector over-samples the input PWM signal at 20 MHz. The accuracy of the duty-cycle measurement

depends upon the frequency of the PWM signal. The maximum possible accuracy is 12-bit precision. To allow

12-bit precision the LP8555 must take at least 8192 samples.

20 MHz

C

8192 samples

2.44 KHz

0

2.4 kHz

4.8 kHz

9.6 kHz

19.5 kHz

39 kHz

78 kHz

156 kHz

6-bit

12-bit

11-bit

10-bit

9-bit

8-bit

7-bit

When the PWM detector detects new PWM-value, it is effective only when it differs from previous value more

than selected hysteresis. Hysteresis is selected with PWM_IN_HYST in register 0x15.

38

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

8.5.11 Brightness Transitions, Typical Times

STEP

SMOOTH

RAMP TIME

(0 to 100%) (ms)

000

001

010

011

100

101

110

111

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

0.0

0.9

1.7

3.4

8.2

14.6

22.3

38.7

16.0

28.4

43.5

75.5

24.2

42.9

65.8

114.2

27.9

49.5

75.8

131.7

32.0

56.8

87.0

151.1

102.0

181.0

277.2

481.5

204.8

363.4

556.6

966.9

Submit Documentation Feedback

39

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

8.5.12 VOLTAGE_0

Address: 0x16

D7

D6

D5

D4

D3

D2

D1

D0

VMAX

ADAPT

VINIT

Bits

Field

Type

Description

Maximum boost voltage for Boost A (typical).

00 = 18V

01 = 22V

10 = 25V

11 = 28V

7:6

VMAX

R/W

5

ADAPT

VINIT

R/W

Enable adaptive headroom optimization.

Initial boost voltage. When ADAPT is 0 the boost voltage will remain at the VINIT setting. The voltage

range is from 7V to 28V; where 0x00 equals 7V and 0x3F equals 28V (typical).

4:0

The VOLTAGE_0.VMAX bit sets the maximum allowed boost voltage for Boost A. The boost control loop will

never request a higher voltage than the VMAX value. When the VOLTAGE.ADAPT bit is set to 1 the boost

voltage may vary from 7V to the VMAX configured voltage.

VINIT (DEC)

Voltage (V)

7.00

VINIT (DEC)

Voltage (V)

14.45

15.13

15.8

VINIT (DEC)

Voltage (V)

21.91

22.58

23.26

23.94

24.61

25.29

25.97

26.65

27.32

28.00

0

1

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

7.68

2

8.35

3

9.03

16.48

17.16

17.84

18.52

19.2

4

9.71

5

10.39

11.06

11.74

12.42

13.09

13.77

6

7

8

19.87

20.55

21.23

9

10

Example: For system where is 7 LEDs in series with 2.9 V Vf. Target value for boost initial voltage would be: 7 x

(2.9 V + 0.1 V) + 2 V = 23 V → VINIT = 24(DEC). 0.1 V represents Vf variation of single LED, and 2 V is worst

case headroom. So it is desirable to set the initial voltage little higher than the actual Vf voltage to take the worst-

case condition in consideration.

40

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

8.5.13 LEDEN1

Address: 0x19

D7

D6

D5

D4

D3

D2

D1

D0

RESERVED

ENABLE[6:1]

Bits

7:6

Field

Type

Description

RESERVED

ENABLE1

R/O

R/W

5:0

LED string enables for Bank B.

The ENABLE field configures the enabled LED strings. If the CONFIG.AUTO bit is 0 these LED strings will stay

active when the backlight is on. If the CONFIG.AUTO bit is set, then an LED open/short condition will cause that

LED string to be removed. A given LED string will never be enabled if the corresponding bit of the ENABLE field

is set to 0. The OV field configures the threshold for detecting an LED overvoltage condition; which may occur

when one or more LEDs are bypassed (shorted) within an LED string.

8.5.14 VOLTAGE1

Address: 0x1A

D7

D6

D5

D4

D3

D2

D1

D0

VMAX1

ADAPT1

VINIT1

Bits

Field

Type

Description

Maximum boost voltage for Boost B (typical).

00 = 18 V

01 = 22 V

10 = 25 V

11 = 28 V

7:6

VMAX

R/W

5

ADAPT

VINIT1

R/W

Enable adaptive headroom optimization.

Initial boost voltage. When ADAPT is 0 the boost voltage will remain at the VINIT setting. The voltage

range is from 7 V to 28 V; where 0x00 equals 7 V and 0x3F equals 28 V (typical).

4:0

The VOLTAGE1.VMAX bit sets the maximum allowed boost voltage for Boost B. The boost control loop will

never request a higher voltage than the VMAX value. When the VOLTAGE.ADAPT bit is set to 1 the boost

voltage may vary from 7 V to the VMAX configured voltage.

VINIT (DEC)

VOLTAGE (V)

7.00

VINIT (DEC)

VOLTAGE (V)

14.45

15.13

15.8

VINIT (DEC)

VOLTAGE (V)

21.91

0

1

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

7.68

22.58

2

8.35

23.26

3

9.03

16.48

17.16

17.84

18.52

19.2

23.94

4

9.71

24.61

5

10.39

11.06

11.74

12.42

13.09

13.77

25.29

6

25.97

7

26.65

8

19.87

20.55

21.23

27.32

9

28.00

10

Submit Documentation Feedback

41

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

8.5.15 OPTION

Address: 0x1C

D7

D6

D5

D4

D3

D2

D1

D0

RESERVED

Type

OPTION

Bits

7:4

Field

Description

reserved

OPTION

R/O

3:0

Metal option identifier.

8.5.16 EXTRA

Address: 0x1D

D7

D6

D5

D4

D3

D2

D1

D0

EXTRA

Bits

Field

Type

Description

7:0

EXTRA

R/W

User accessible extra identifier register

8.5.17 ID

Address: 0x0E

D7

D6

D5

D4

D3

D2

D1

D0

ID_CUST

ID_CFG

Bits

7:4

Field

Type

R/W

Description

ID_CUST

ID_CFG

TI Customer ID code.

3:0

TI Configuration ID code.

The ID field is configured by TI when the EPROM is programmed.

8.5.18 REVISION

Address: 0x0F

D7

D6

D5

D4

D3

D2

D1

D0

MAJOR

MINOR

Bits

7:4

Field

Type

Description

MAJOR

MINOR

R/O

Major silicon revision.

Minor silicon revision.

3:0

The REVISION register provides silicon revision information in case test SW needs to distinguish between

different revisions of the device or later identification is needed. REVISION register content comes from read only

metal register (connected at COM level).

42

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

8.5.19 CONF0

Address: 0x76

D7

D6

D5

RESERVED

Type

D4

D3

D2

D1

D0

BOOST_IS_DIV2

ALTID

SRON

Description

CURR_LIMIT

Bits

Field

7

BOOST_IS_DIV2

R/W Divide inductor peak current by 2

0 = Normal operation

1 = Inductor currents divided by 2

6:5

4

RESERVED

ALTID

R/W

I²C Slave ID selector

R/W 0 = 2Ch

1 = 2Eh

Slowed boost slew rate. When COMMAND.SREN is set to 1 boost slew rate is controlled with this

value.

3:2

1:0

SRON

R/W

Boost inductor peak current limit (typical). BOOST_IS_DIV2 sets which of the limits is used.

00 = 0.9 A / 1.55 A

R/W 01 = 1.2 A / 2.1 A

10 = 1.5 A / 2.6 A

CURR_LIMIT

11 = 1.8 A / 3.1 A

8.5.20 CONF1

Address: 0x77

D7

D6

D5

D4

D3

D2

D1

D0

FMOD_DIV

Field

RESERVED

Bits

7:6

Type

Description

Spread spectrum modulation frequency divisor.

00 = 0.45%

01 = 0.27%

10 = 0.17%

11 = 0.12%

FMOD_DIV

RESERVED

R/W

5:0

The FMOD_DIV field controls modulation frequency for spread spectrum clocking. The actual modulation

frequency scales with the boost frequency.

FMOD_DIV = 01b

(kHz)

FMOD_DIV = 11b

(kHz)

BOOST FREQUENCY (kHz)

FMOD_DIV = 00b (kHz)

FMOD_DIV = 10b (kHz)

1000

500

4.17

2.08

2.78

1.39

1.67

0.83

1.19

0.64

Submit Documentation Feedback

43

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

8.5.21 VHR0

Address: 0x78

D7

D6

D5

D4

D3

D2

D1

D0

RESERVED

VHR_SLOPE

RESERVED

VHR_VERT

Bits

Field

Type

Description

7

RESERVED

VHR_SLOPE

RESERVED

VHR_VERT

R/O

Typical headroom voltage at maximum current (50 mA)

000 = 210 mV

001 = 223 mV

010 = 235 mV

011 = 248 mV

100 = 260 mV

101 = 273 mV

110 = 285 mV

111 = 300 mV

6:4

3

R/W

Typical minimum headroom voltage

000 = 50 mV

001 = 80 mV

010 = 110 mV

011 = 140 mV

100 = 170 mV

101 = 200 mV

110 = 230 mV

111 = 260 mV

2:0

R/W

8.5.22 VHR1

Address: 0x79

D7

D6

D5

D4

D3

D2

D1

D0

RESERVED

VHR_HYST

RESERVED

VHR_HORZ

Bits

Field

Type

Description

7:6

RESERVED

R/O

Typical hysteresis for the mid comparator threshold (above the low comparator threshold).

00 = 200 mV

01 = 233 mV

10 = 466 mV

11 = 600 mV

5:4

3:2

1:0

VHR_HYST

RESERVED

VHR_HORZ

R/W

R/O

R/W

Percentage of full driver range (horizontal component)

00 = 1%

01 = 25%

10 = 37.5%

11 = 50%

44

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

8.5.23 JUMP

Address: 0x7A

D7

D6

D5

D4

D3

D2

D1

D0

JEN

RESERVED

JTHR

JVOLT

Bits

7

Field

JEN

Type

Description

R/W

Enable boost voltage jumping on large brightness percentage increases.

6:4

RESERVED

Jump brightness percentage threshold.

00 = 6.25%

01 = 12.5%

10 = 25%

11 = 50%

3:2

1:0

JTHR

R/W

Typical Boost voltage jump size (10.26 mV/step)

00 = 195 steps (2 V)

01 = 390 steps (4 V)

JVOLT

10 = 585 steps (6 V)

11 = 780 steps (8 V)

The jump feature operates outside of the normal adaptive headroom loop. Whenever the brightness percentage

instantaneously increases above the configured threshold the boost voltage is instructed to immediately jump up.

This can be used in some rare cases where extremely fast boost reaction time to brightness changes is needed.

The JTHR field configures the threshold and the JVOLT field configures the voltage increase. The requested

boost voltage will never exceed the value set by the VOLTAGE.VMAX field.

Submit Documentation Feedback

45

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

9 Application and Implementation

9.1 Application Information

The LP8555 designed for LCD backlighting, especially for high-resolution tablet panels where more backlight

power is needed due to smaller aperture ratio of the LCD. With single-boost configuration the inductor selection

is difficult for height restricted applications; to overcome this LP8555 uses dual-boost configuration. This shares

the total load to two boost inductors and allows using two smaller inductors instead of one large inductor while

maintaining good efficiency. 12 LED current sinks allow driving up to 96 LEDs with high efficiency. Better

efficiency is achieved with using lower conversion ratio for boost and driving more LEDs in parallel, compared to

using fewer LED strings and higher boost conversion ratio. Main limiting factor for output power is inductor

current limit, which is calculated in the Detailed Design Procedure. PCB thermal performance must be

considered in high power applications where thermal dissipation of LP8555 can become limiting factor.

Due to a flexible input voltage configuration, the LP8555 can be used also in various other applications, such as

laptop backlighting, as well as other LED lighting where high number of LEDs are needed and must be driven

with highest possible efficiency. The following design procedure can be used to select component values for the

LP8555. An example for default EPROM configuration is given with corresponding design parameters.

LP8555EVM User Guide has reference bill of materials and example layout pictures.

9.2 Typical Applications

9.2.1 Application for Default LP8555YFQR EPROM Configuration

With the default EPROM configuration PWM input is used for brightness control. The backlight is

enabled/disabled and also configuration can be changed before backlight turning on with I²C writes. Up to 12

LED strings can be used with max 28-V boost output voltage. LED current is set to 25 mA by default. See

detailed EPROM setup in LP8555YFQR EPROM Configuration.

9.2.1.1 Schematic

L1

D1

7 - 28V

V

BATT

4.7 ± 6.8µH

2.7V ± 4.5V

C

VDD

OUT_A

2 x 4.7 PF

10µF

IN_A

(Single Li-Ion Cell)

C

OUT_A

C

1µF

SW_A

VDD

VLDO

39 pF

LCD Display

FB_A

C

VLDO

10µF

LEDA1

LEDA2

LEDA3

LEDA4

LED

Current up

to 25mA /

string

LP8555

EN

EN/VDDIO

FSET/SDA

LEDA5

LEDA6

R_PULL-UP

SDA

SCL

ISET/SCL

PWM/INT

Brightness Control

PWM input only

PWM

LEDB1

LEDB2

LEDB3

LED

Current up

to 25mA /

string

LEDB4

LEDB5

LEDB6

FB_B

SW_B

GNDs

39 pF

V

L2

OUT_B

V

BATT

2.7V ± 4.5V

4.7 ± 6.8µH

C

7 - 28V

OUT_B

2 x 4.7 PF

IN_B

D2

10µF

Figure 43. Application Diagram for Default EPROM Setup

46

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

Typical Applications (continued)

9.2.1.2 LP8555YFQR EPROM Configuration

ADDRESS

(HEX)

BIT

BIT NAME

BIT DESCRIPTION

VALUE MEANING

REG VALUE

(HEX)

00

10

2

1

0

SREN

SSEN

ON

Boost slew rate limit enable

Spread spectrum enable

Backlight enable

0b

0 = Boost slew rate not limited

0 = Spread spectrum disabled

00

0b

0 = Backlight enabled only by writing

this bit to 1

7

6

PWMSB

Enable automatic PWM input shutdown

Enable PWM input filtering

0b

1b

0 = Shutdown function disabled

64

PWMFILT

1 = PWM input analog 50 ns filter

enabled

5

4

3

EN_BPHASE180

Enable boost 180° phase difference

1b

0b

1 = Boosts clocks are 180° shifted

-

RELOAD

Enable EPROM read at every BL enable

sequence

0 = EPROM is read only at first start-

up

2

AUTO

Enable auto detect for number of LEDs

during start-up

1b

1 = LED string auto detection

enabled

1:0

7

BRTMODE

ISET

Brightness control mode

00b

0b

00 = PWM input duty control only

0 = LED current set with registers

11

12

Enable external resistor setting of LED

string current

05

2B

6:3

2:0

7

-

0000b

101b

0b

MAXCURR

PFSET

Set maximum DC current per string

101 = 25 mA

Enable external resistor PWM frequency

setting

0 = PWM frequency selected with

registers

6

-

0b

5:3

THRESHOLD

Hybrid PMW and Current Control switch

point control

101b

101 = 25% switch point

011 = 19.5 kHz

2:0

7

PFSET

-

PWM frequency selection

011b

0b

13

01

6

-

0b

5:2

1

-

0000b

0b

BIND

Boost inductor selection

0 = 4.7 µH ... 6.8 µH inductor

1 = 1 MHz

0

BFREQ

OV

Boost SW frequency

1b

14

15

7:6

5:0

7:6

5:3

2:0

7:6

5

Set LED high comparator detection level

LED bank A string enable

10b

10 = 3 V

BF

20

ENABLE_0

SMOOTH

PWM_IN_HYST

STEP

111111b 1 = Enabled (all six strings)

Advanced Sloping smoothing factor

PWM input hysteresis

00b

100b

000b

11b

1b

00 = No smoothing

100 = >8 LSB steps

000 = 0ms

Linear Slope time

16

VMAX_0

ADAPT_0

VINIT_0

ENABLE_1

VMAX_1

ADAPT_1

VINIT_1

ID_CUST

ID_CFG

BOOST_IS_DIV2

-

Bank A boost maximum voltage

Enable boost adaptive control for bank A

Initial voltage for bank A boost

LED bank B string enable

11 = 28 V

F8

1 = Adaptive headroom enabled

4:0

5:0

7

11000b 11000 = 23.26 V

19

1A

111111b 1 = Enabled (all six strings)

3F

F8

Bank B boost maximum voltage

Enable boost adaptive control for bank B

Initial voltage for bank B boost

ID register, Customer ID

11b

1b

11 = 28 V

6

1 = Adaptive headroom enabled

5

11000b 11000 = 23.26 V

1E

76

7:4

3:0

7

0000b

0b

0000

00

0B

ID register, EPROM config

0000

Option divide Imax peak current by 2

0 = Normal current limit

6:5

4

00b

ALTID

I2C slave ID selector

0b

0 = 2Ch (7-bit)

3:2

SRON

Slowed boost slew rate

10b

When COMMAND.SREN is set to 1

this value is used.

10 = Second slowest

1:0

CURR_LIMIT

Inductor peak current limit

11b

11 = 3.1 A

Submit Documentation Feedback

47

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

Typical Applications (continued)

ADDRESS

BIT

BIT NAME

BIT DESCRIPTION

VALUE MEANING

REG VALUE

(HEX)

77

7:6

FMOD_DIV

Spread spectrum modulation frequency

divisor

00b

When COMMAND.SSEN is set to 1

this value is used.

00 = 0.42%

17

5:0

6:4

-

010111b

110b

78

VHR_SLOPE

LED driver maximum headroom voltage at

maximum current (50mA)

110 = 285 mV

60

3

-

0b

2:0

VHR_VERT

LED driver maximum headroom voltage at

minimum current

000b

000 = 50 mV

01 = 233 mV

79

7A

5:4

VHR_HYST

LED driver hysteresis for mid comparator

level

01b

11

88

3:2

1:0

-

00b

01b

VHR_HORZ

LED driver headroom control knee

percentage of full LED current

01 = 25%

7

JEN

Enable boost voltage jumping on

brightness change

1b

1 = Jump enabled

6:4

3:2

1:0

-

000b

10b

JTHR

JVOLT

Jump brightness threshold

Jump voltage

10 = 25%

00 = 2 V

00b

9.2.1.3 Design Requirements

Example requirements based on default EPROM setup.

DESIGN PARAMETER

Input voltage range

Brightness Control

Backlight enabled

PWM output frequency

LED Current

EXAMPLE VALUE

2.7 V to 4.5 V (Single Li-Ion cell battery)

PWM input duty cycle

Writing ON bit 1 with I²C

19.2 kHz with PSPWM enabled

25 mA / channel

Number of Channels

Brightness slopes

External set resistors

Inductor

Up to 12 with string auto detection enabled

Disabled

4.7 µH to 6.8 µH, at least 3.1-A saturation current

Boost SW frequency

Maximum output voltage

SW current limit

1 MHz

28 V

3.1 A

CABC

Jump enabled for >25% brightness changes

48

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

9.2.1.4 Detailed Design Procedure

9.2.1.4.1 Inductor

There are two main considerations when choosing an inductor; the inductor should not saturate, and the inductor

current ripple should be small enough to achieve the desired output voltage ripple. Different saturation current

rating specifications are followed by different manufacturers so attention must be given to details. Saturation

current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of

application should be requested from the manufacturer. Shielded inductors radiate less noise and should be

preferred.

The saturation current should be greater than the sum of the maximum load current and the worst case average

to peak inductor current.

Figure 44 shows the worst case conditions.

I_OUTMAX

I_SAT

>

+ I_RIPPLE

'¶

V_IN

(V_OUT± V_IN)

x

Where I_RIPPLE

=

V_OUT

(2 x L x f)

(V_OUT± V_IN)

(V_OUT

DQGꢀ'¶ꢀ= (1 - D)

Where D =

)

Figure 44. Calculating Inductor Maximum Current

•

I_RIPPLE: peak inductor current

I_OUTMAX: maximum load current

V_IN: minimum input voltage in application

L : min inductor value including worst case tolerances

f : minimum switching frequency

V_OUT: output voltage

D: Duty Cycle for CCM Operation

V_OUT: Output Voltage

As a result the inductor should be selected according to the I_SAT. A more conservative and recommended

approach is to choose an inductor that has a saturation current rating greater than the maximum current limit of

3.1 A. A 4.7-µH to 6.8-µH inductor with a saturation current rating of at least 3.1 A is recommended for most

applications. The inductor’s resistance should be less than 300 mΩ for good efficiency.

9.2.1.4.2 Output Capacitor

A ceramic capacitor with 50-V voltage rating is recommended for the output capacitor. The DC-bias effect can

reduce the effective capacitance by up to 80% especially with small package size capacitors, which needs to be

considered in capacitance value and package selection. Typically one 10-µF or two 4.7-µF capacitors is

sufficient. Effectively the capacitance should be at least 2 µF at boost maximum output voltage.

9.2.1.4.3 LDO Capacitor

A ceramic capacitor with at least 10 V voltage rating is recommended for the output capacitor of the LDO. The

DC-bias effect can reduce the effective capacitance by up to 80%, which needs to be considered in capacitance

value selection. Typically 10 µF capacitor is sufficient.

9.2.1.4.4 VDD Capacitor

A ceramic capacitor with at least 10-V voltage rating is recommended for the VDD input capacitor. If input

voltage is higher, then the rating should be selected accordingly. The DC-bias effect can reduce the effective

capacitance by up to 80%, which needs to be considered in capacitance value selection. Typically, a 1-μF

capacitor is sufficient. X5R/X7R are recommended types.

Submit Documentation Feedback

49

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

9.2.1.4.5 Boost Input Capacitor

A ceramic capacitor with at least 10-V voltage rating is recommended for the boost input capacitor. If input

voltage is higher, then the rating should be selected accordingly. The DC-bias effect can reduce the effective

capacitance by up to 80%, which needs to be considered in capacitance value selection. Typically, a 10-μF

capacitor per boost is sufficient. X5R/X7R are recommended types.

9.2.1.4.6 Diode

A Schottky diode should be used for the output diode. Peak repetitive current should be greater than inductor

peak current (3.1 A) to ensure reliable operation. Average current rating should be greater than the maximum

output current. Schottky diodes with a low forward drop and fast switching speeds are ideal for increasing

efficiency in portable applications. Choose a reverse breakdown voltage of the Schottky diode significantly larger

(~40 V) than the output voltage. Do not use ordinary rectifier diodes, since slow switching speeds and long

recovery times cause the efficiency and the load regulation to suffer.

9.2.1.5 Application Performance Plots

Typical performance plots with default EPROM configuration. The LP8555EVM was used for taking the

oscilloscope plots.

VDD = 3.7V

I_LED= 25 mA

12 x 7 LEDs

VDD = 3.7V

V_BOOST= 28V

Load = 150 mA

Figure 45. Start-up Waveform with I²C Write

Full Brightness Slope Function Disabled.

Figure 46. Typical Boost Waveform, Boost A

VDD = 3.7V

f_SW= 1 MHz

ƒ_PWM= 19.5 kHz

6 Strings

Figure 47. 180° Phase Difference Between Boost A and B

Figure 48. Typical LED Current and Voltage Waveforms.

50

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

9.2.2 Application Example With Different LED Configuration for Each Bank

In the following example schematic it is shown how the LED banks can have different LED configuration. Bank A

has 4 active LED outputs and Bank B has 5 active LED outputs. LP8555 will automatically detect open outputs

and adjust phase shifting for both banks optimally. Control in this example is from I²C bus and PWM/INT terminal

is used for interrupt signal, notifying processor on possible fault conditions. Component selection and

performance plots follow the examples shown in first application example with default EPROM configuration, but

the PSPWM is adjusted based on the number of connected strings. Details on I²C registers and EPROM settings

are seen in the Register Map section. If custom EPROM is required, please contact TI Sales representative for

availability.

9.2.2.1 Schematic

7 - 28V

1.3 ꢀ9_OUT/ V_INꢀ10

L1

D1

V_BATT

2.7V ± 20V

C_VDD

V_{OUT_A}

C_{IN_A}

C_{OUT_A}

SW_A

VDD

VLDO

C_VLDO

FB_A

LCD Display

LEDA1

LEDA2

LEDA3

LEDA4

LP8555

EN

EN/VDDIO

FSET/SDA

LEDA5

LEDA6

R_PULL-UP

SDA

SCL

ISET/SCL

PWM/INT

LEDB1

LEDB2

LEDB3

INT

VDDIO

R_PULL-UP

LEDB4

LEDB5

LEDB6

FB_B

GNDs

C_{IN_B}

SW_B

V_{OUT_B}

V_BATT

2.7V ± 20V

C_{OUT_B}

7 - 28V

1.3 ꢀ9_OUT/ V_INꢀ10

L2

D2

Figure 49. Application Example With Different LED Configurations on Each Bank

Submit Documentation Feedback

51

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

9.2.3 Application Example With 12 LED Strings and PWM Input Brightness Control

In the following example schematic it is shown how the LP8555 can be configured for operating without I²C

control. Only controls needed are PWM input for brightness control and EN for enabling and disabling device.

PWM frequency is set with R_FSETresistor and LED current is set with I_SETresistor. Full 12 channels are used in

this example, but other configurations can be used as well. Component selection and performance plots follow

the examples shown in first application example with default EPROM configuration. Details on I²C registers and

EPROM settings are seen in the Register Map section. If custom EPROM is required, please contact TI Sales

representative for availability. Since this configuration relies on pre-programmed EPROM for basic setup

(although LED current and PWM frequency are set with resistors), special EPROM configuration is needed for

this application.

9.2.3.1 Schematic

7 - 28V

1.3 ꢀ9_OUT/ V_INꢀ10

L1

D1

V_BATT

2.7V ± 20V

C_VDD

V_{OUT_A}

C_{IN_A}

C_{OUT_A}

SW_A

VDD

C_VLDO

FB_A

VLDO

LCD Display

LEDA1

LEDA2

LEDA3

LEDA4

LP8555

LEDA5

LEDA6

EN/VDDIO

FSET/SDA

EN

R_FSET

R_ISET

ISET/SCL

PWM/INT

PWM

LEDB1

LEDB2

LEDB3

LEDB4

LEDB5

LEDB6

FB_B

GNDs

C_{IN_B}

SW_B

V_{OUT_B}

V_BATT

2.7V ± 20V

C_{OUT_B}

7 - 28V

1.3 ꢀ9_OUT/ V_INꢀ10

L2

D2

Figure 50. Application Example with 12 LED Strings and PWM Input Brightness Control

52

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

9.2.4 Application With 12 LED Strings, I²C Brightness Control

In the following example full 12 channels are used with I²C brightness control. PWM/INT terminal is used for

interrupt signal, notifying processor on possible fault conditions. LED current and PWM frequency are set with

I²C writes, or default EPROM values can be used as well. Component selection and performance plots follow the

examples shown in first application example with default EPROM configuration. Configuration registers can be

set before backlight is enabled, so special pre-set EPROM is not necessarily needed. Details on I²C registers

and EPROM settings are seen in the Register Map section. If custom EPROM is required, please contact TI

Sales representative for availability.

9.2.4.1 Schematic

7 - 28V

1.3 ꢀ9_OUT/ V_INꢀ10

L1

D1

V_BATT

2.7V ± 20V

C_VDD

V_{OUT_A}

C_{IN_A}

C_{OUT_A}

SW_A

VDD

VLDO

C_VLDO

FB_A

LCD Display

LEDA1

LEDA2

LEDA3

LEDA4

LP8555

EN/VDDIO

FSET/SDA

EN

LEDA5

LEDA6

R_PULL-UP

SDA

ISET/SCL

PWM/INT

SCL

INT

LEDB1

LEDB2

LEDB3

VDDIO

R_PULL-UP

LEDB4

LEDB5

LEDB6

FB_B

GNDs

C_{IN_B}

SW_B

V_{OUT_B}

V_BATT

2.7V ± 20V

C_{OUT_B}

7 - 28V

1.3 ꢀ9_OUT/ V_INꢀ10

L2

D2

Figure 51. Application Example With 12 LED Strings, I²C Brightness Control

Submit Documentation Feedback

53

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

10 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 2.7 V and 20 V. This input supply

should be well regulated and able to withstand maximum input current and maintain stable voltage without

voltage drop even at load transition condition (start-up or rapid brightness change). The resistance of the input

supply rail should be low enough that the input current transient does not cause drop high enough in the LP8555

supply voltage that can cause false UVLO fault triggering.

If the input supply is located more than a few inches from the LP8555 additional bulk capacitance may be

required in addition to the ceramic bypass capacitors. Depending on device EPROM configuration and usage

case the boost converter is configured to operate optimally with certain input voltage range. Examples are seen

in the Detailed Design Procedures. In uncertain cases, it is recommended to contact TI Sales Representative for

confirmation of the compatibility of the use case, EPROM configuration and input voltage range.

54

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

11 Layout

11.1 Layout Guidelines

In Layout Example is a layout recommendation for LP8555. The figure is used for demonstrating the principle of

good layout. This layout can be adapted to the actual application layout if/where possible.

It is important that all boost components are close to the chip and the high current traces should be wide enough.

By placing one boost component on one side of the chip it is easy to keep the ground plane intact below the high

current paths. This way other chip terminals can be routed more easily without splitting the ground plane. VDD

and VLDO need to be as noise-free as possible. Place the bypass capacitors near the corresponding terminals

and ground them to as noise-free ground as possible.

Here are some main points to help the PCB layout work:

•

Current loops need to be minimized:

–

For low frequency the minimal current loop can be achieved by placing the boost components as close to

the SW and SW_GND terminals as possible. Input and output capacitor grounds need to be close to each

other to minimize current loop size.

–

Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact

under the current traces. High frequency return currents try to find route with minimum impedance, which

is the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when

return current flows just under the “positive” current route in the ground plane, if the ground plane is intact

under the route. Traces from inner pads of the LP8555 need to be routed from below the part in the inner

layer so that traces do not split the ground plane under the boost traces or components.

•

GND plane needs to be intact under the high current boost traces to provide shortest possible return path and

smallest possible current loops for high frequencies.

Current loops when the boost switch is conducting and not conducting needs to be on the same direction in

optimal case.

Inductor placement should be so that the current flows in the same direction as in the current loops. Rotating

inductor 180° changes current direction.

Use separate power and noise free grounds. Power ground is used for boost converter return current and

noise free ground for more sensitive signals, like VDD and VLDO bypass capacitor grounding as well as

grounding the GND terminals of LP8555 itself.

•

Boost output feedback voltage to LEDs need to be taken out “after” the output capacitors, not straight from

the diode cathode.

A small (for example, 39 pF) bypass capacitor should be placed close to the FB terminal(s) to suppress high

frequency noise

VDD line should be separated from the high current supply path to the boost converter(s) to prevent high

frequency ripple affecting the chip behavior. A separate 1-µF bypass capacitor is used for the VDD terminal,

and it is grounded to noise-free ground.

•

Input and output capacitors need strong grounding (wide traces, many vias to GND plane)

If two output capacitors are used they need symmetrical layout to get both capacitors working ideally

Output capacitors DC-bias effect. If the output capacitance is too low, it can cause boost to become instable

on some loads and this increases EMI. DC bias characteristics need to be obtained from the component

manufacturer; it is not taken into account on component tolerance. X5R/X7R capacitors are recommended.

Submit Documentation Feedback

55

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

11.2 Layout Example

BOOST A

VBATT rail

C_{IN_A}

Vboost Node

C_{OUT_A}

Power

GND Area

Pin A1

Small ~39pF cap

Feedback line

Vias to Power

GND plane

SW_A

FB_A

LEDA1

LEDA3

LEDA5

LEDB5

LEDB3

LEDB1

SW_A

LEDA2

LEDA4

LEDA6

LEDB6

LEDB4

LEDB2

PWM/

INT

GND

SW_A

GND

SW_A

GND

SW_A

C_VLDO

FSET/

SDA

VLDO

VDD

GND

LED outputs

ISET

/SCL

Grounded to noise

free GND plane

GND

SW_B

GND

SW_B

GND

SW_B

EN

VDDIO

C_VDD

SW_B

FB_B

Vias to Power

GND plane

Feedback line

Small ~39pF cap

Power GND

Area

C_{IN_B}

C_{OUT_B}

VBATT rail

Vboost Node

BOOST B

Via to Power GND plane

Via to noise free GND plane

56

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555

www.ti.com

SNVS857 –FEBRUARY 2014

12 Device and Documentation Support

12.1 Trademarks

All trademarks are the property of their respective owners.

12.2 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.3 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms and definitions.

Submit Documentation Feedback

57

Product Folder Links: LP8555

LP8555

SNVS857 –FEBRUARY 2014

www.ti.com

13 Mechanical, Packaging, and Orderable Information

The following packaging information and addendum reflect the most current data available for the designated

devices. This data is subject to change without notice and revision of this document

58

Submit Documentation Feedback

Product Folder Links: LP8555

MECHANICAL DATA

YFQ0036xxx

D

0.600

±0.075

E

TMD36XXX (Rev B)

D: Max = 2.478 mm, Min =2.418 mm

E: Max = 2.478 mm, Min =2.418 mm

4215086/A

12/12

NOTES:

A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LP8555
厂家：	TEXAS INSTRUMENTS
描述：	适用于平板电脑的高效 LED 背光驱动器驱动电脑驱动器
文件：	总63页 (文件大小：1321K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LP8555 [TI]

相关型号：

LP8555YFQR

LP8556

LP8556SQ-E00/NOPB

LP8556SQ-E08/NOPB

LP8556SQ-E09/NOPB

LP8556SQE-E00/NOPB

LP8556SQE-E08/NOPB

LP8556SQE-E09/NOPB

LP8556SQX-E00/NOPB

LP8556SQX-E08/NOPB

LP8556SQX-E09/NOPB

LP8556TME-E02/NOPB