LP8732-Q1_V02_技术文档

LP8732-Q1

SNVSB63A – SEPTEMBER 2018 – REVISED JUNE 2021

LP8732xx-Q1 Dual High-Current Buck Converter and Dual Linear Regulator

1 Features

2 Applications

•

AEC-Q100 qualified with the following results:

– Device temperature grade 1: –40°C to +125°C

ambient operating temperature

•

Automotive head unit and cluster

Automotive camera module

Surround view system ECU

Radar system ECU

•

Input voltage: 2.8 V to 5.5 V

Two high-efficiency step-down DC/DC converters:

– Output voltage: 0.7 V to 3.36 V

– Maximum output current 2 A per phase

– Adding and shedding auto phase and

force multi-phase operations in dual-phase

configuration

– Remote differential feedback voltage sensing in

dual-phase configuration

– Programmable output-voltage slew rate from

0.5 mV/µs to 10 mV/µs

3 Description

The LP8732xx-Q1 is designed to meet the power

management requirements in automotive applications.

The device has two step-down DC/DC converters

(which can be configured as a single dual-phase

regulator or two single-phase regulators), two linear

regulators, and two general-purpose digital-output

signals. The device is controlled by an I²C-compatible

serial interface and by an enable signal.

– 2-MHz switching frequency

– Spread-spectrum mode and phase interleaving

for EMI reduction

Two linear regulators:

– Input voltage: 2.5 V to 5.5 V

– Output voltage: 0.8 V to 3.3 V

– Maximum output current 300 mA

Configurable general-purpose output signals

(GPO, GPO2)

Interrupt function with programmable masking

Programmable power-good signal (PGOOD)

Output short-circuit and overload protection

Overtemperature warning and protection

Overvoltage protection (OVP) and undervoltage

lockout (UVLO)

The automatic PWM/PFM (AUTO mode) operation

together with the automatic phase adding/shedding

gives high efficiency over a wide output-current

range. The LP8732xx-Q1 supports remote voltage

sensing (differential in dual-phase configuration) to

compensate IR drop between the regulator output and

the point-of-load (POL), thus improving the accuracy

of the output voltage. In addition, the switching clock

can be forced to PWM mode and also synchronized to

an external clock to minimize the disturbances.

•

The LP8732xx-Q1 device supports programmable

start-up and shutdown delays and sequences

including GPO signals synchronized to the enable

signal. During start-up and voltage change, the device

controls the output slew rate to minimize output

voltage overshoot and the in-rush current.

•

28-pin, 5-mm × 5-mm VQFN package with

wettable flanks

Device Information⁽¹⁾

Configurable

multi-phase

VIN

PART NUMBER

PACKAGE

BODY SIZE (NOM)

VIN_B0

VIN_B1

SW_B0

SW_B1

LP8732xx-Q1

VQFN (28)

5.00 mm × 5.00 mm

1 œ 2

Outputs

VIN_LDO0

VIN_LDO1

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

FB_B0

FB_B1

VANA

100

SDA

SCL

nINT

EN

90

VOUT_LDO0

VOUT_LDO1

VOUT_LDO0

VOUT_LDO1

80

CLKIN (GPO2)

GPO

70

PGOOD

GNDs

1PH, Vin=3.7V, Vout=1.0V

1PH, Vin=3.7V, Vout=2.5V

60

2PH, Vin=3.7V, Vout=1.0V

2PH, Vin=3.7V, Vout=2.5V

50

0.025

0.1

1

4

Output Current (A)

D421

Simplified Schematic

DC/DC Efficiency vs Output Current (Dual-Phase)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LP8732-Q1

SNVSB63A – SEPTEMBER 2018 – REVISED JUNE 2021

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................6

6.5 Electrical Characteristics.............................................6

6.6 I²C Serial Bus Timing Parameters............................ 12

6.7 Typical Characteristics..............................................15

7 Detailed Description......................................................16

7.1 Overview...................................................................16

7.2 Functional Block Diagram.........................................17

7.3 Feature Description...................................................17

7.4 Device Functional Modes..........................................37

7.5 Programming............................................................ 38

7.6 Register Maps...........................................................41

8 Application and Implementation..................................62

8.1 Application Information............................................. 62

8.2 Typical Applications ................................................. 62

9 Power Supply Recommendations................................74

10 Layout...........................................................................75

10.1 Layout Guidelines................................................... 75

10.2 Layout Example...................................................... 76

11 Device and Documentation Support..........................77

11.1 Device Support........................................................77

11.2 Receiving Notification of Documentation Updates..77

11.3 Support Resources................................................. 77

11.4 Trademarks............................................................. 77

11.5 Electrostatic Discharge Caution..............................77

11.6 Glossary..................................................................77

12 Mechanical, Packaging, and Orderable

Information.................................................................... 77

4 Revision History

Changes from Revision * (September 2019) to Revision A (June 2021)

Page

Updated the numbering format for tables, figures, and cross-references throughout the document..................1

Updated the LDO Output Capacitor Selection section..................................................................................... 64

•

2

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5 Pin Configuration and Functions

21

20

19

18

17

16

15

SW_B0

SW_B1

VIN_B1

CLKIN

22

14

13

12

11

10

9

SW_B0

23

VIN_B0

24

VIN_B0

25

THERMAL PAD

GPO

26

PGOOD

nINT

27

VIN_LDO0

VIN_LDO1

28

8

1

2

3

4

5

6

7

Figure 5-1. RHD Package 28-Pin VQFN With Thermal Pad Top View

Table 5-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NUMBER

NAME

1

2

VOUT_LDO0

FB_B0

P/O

A

LDO0 output. If the LDO0 is not used, leave the pin floating.

Output voltage feedback (positive) for Buck 0.

Output voltage feedback (positive) for Buck 1 in two single-phase configuration and output

ground feedback (negative) for Buck 0 in dual-phase configuration.

3

FB_B1

A

4

5

AGND

VANA

G

Ground.

P/I

Supply voltage for analog and digital blocks. Must be connected to same node with VIN_Bx.

Programmable enable signal for regulators and GPOs. If the pin is not used, leave the pin

floating.

6

EN

D/I

7

8

9

VOUT_LDO1

VIN_LDO1

nINT

P/O

P/I

LDO1 output. If LDO1 is not used, leave the pin floating.

Power input for LDO1. If LDO1 is not used, connect the pin to VANA.

Open-drain interrupt output. Active LOW. If the pin is not used, connect the pin to ground.

D/O

External clock input. Alternative function is general-purpose digital output (GPO2). If the pin is

not used, leave the pin floating.

10

CLKIN

D/I/O

P/I

Input for Buck 1. The separate power pins VIN_Bx are not connected together internally -

VIN_Bx pins must be connected together in the application and be locally bypassed.

11, 12

VIN_B1

13, 14

15, 16

SW_B1

P/O

P/G

Buck 1 switch node. If the Buck 1 is not used, leave the pin floating.

Power ground for Buck 1.

PGND_B1

Serial interface clock input for I²C access. Connect a pullup resistor. If the I²C interface is not

used, connect the pin to Ground.

17

18

SCL

SDA

D/I

Serial interface data input and output for I²C access. Connect a pullup resistor. If the I²C

interface is not used, connect the pin to Ground.

D/I/O

19

SGND

PGND_B0

SW_B0

G

Ground.

20, 21

22, 23

P/G

P/O

Power ground for Buck 0.

Buck 0 switch node. If the Buck 0 is not used, leave the pin floating.

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Table 5-1. Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NUMBER

NAME

Input for Buck 0. The separate power pins VIN_Bx are not connected together internally -

VIN_Bx pins must be connected together in the application and be locally bypassed.

24, 25

VIN_B0

P/I

26

27

28

GPO

D/O

P/I

General-purpose digital output. If the pin is not used, leave the pin floating.

Power-good indication signal. If the pin is not used, leave the pin floating.

Power input for LDO0. If the LDO0 is not used, connect the pin to VANA.

PGOOD

VIN_LDO0

—

Thermal

Pad

—

Connect to PCB ground plane using multiple vias for good thermal performance.

(1) A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, and O: Output Pin.

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6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

–0.3

MAX UNIT

Voltage on power connections (must use the same

VIN_Bx, VANA

input supply)

6

V

VIN_LDOx

SW_Bx

Voltage on power connections

Voltage on buck switch nodes

(VIN_Bx + 0.3 V) with 6-V

maximum

(VANA + 0.3 V) with 6-V

maximum

FB_Bx

Voltage on buck voltage sense nodes

–0.3

V

(VIN_LDOx + 0.3 V) with 6-V

maximum

VOUT_LDOx

Voltage on LDO output

-0.3

–0.3

V

SDA, SCL, nINT, EN

Voltage on logic pins (input or output pins)

6

PGOOD, GPO, CLKIN

(GPO2)

(VANA + 0.3 V) with 6-V

maximum

T_J-MAX

T_stg

Junction temperature

Storage temperature

−40

–65

150

260

°C

Maximum lead temperature (soldering, 10 seconds)

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 6.3.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM)

All pins

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM)

Corner pins (1, 7, 8, 14,

15, 21, 22, 28)

±750

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

INPUT VOLTAGE

Voltage on power connections (must use the same input

VIN_Bx, VANA

supply)

2.8

5.5

V

VIN_LDOx

EN, nINT

Voltage on LDO inputs

2.5

0

5.5

V

Voltage on logic pins (input or output pins)

Voltage on logic pins (input pin)

0

VANA with 5.5-V

maximum

CLKIN

V

PGOOD, GPO, GPO2

Voltage on logic pins (output pins)

0

VANA

1.95

Voltage on I2C interface, Standard (100 kHz), Fast (400

kHz), Fast+ (1 MHz), and High-Speed (3.4 MHz) Modes

SCL, SDA

Voltage on I2C interface, Standard (100 kHz), Fast (400

kHz), and Fast+ (1 MHz) Modes

VANA with 3.6-V

maximum

0

V

TEMPERATURE

T_J

Junction temperature

Ambient temperature

−40

140

125

°C

T_A

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6.4 Thermal Information

LP8732xx-Q1

THERMAL METRIC⁽¹⁾

RHD (VQFN)

28 PINS

36.7

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJCtop

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

26.6

8.9

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.4

ψ_JB

8.8

R_θJCbot

2.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

note.

6.5 Electrical Characteristics

Limits apply over the junction temperature range –40°C ≤ T_J≤ +140°C, specified V_VANA, V_{VIN_Bx}, V_{VIN_LDOx}, V_{VOUT_Bx}

,

V_{VOUT_LDOx}and I_OUTrange, unless otherwise noted. Typical values are at T_J= 25°C, V_VANA= V_{VIN_Bx}= V_{VIN_LDOx}= 3.7 V,

and V_OUT= 1 V, unless otherwise noted^{(1) (2)}

.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

EXTERNAL COMPONENTS

Input filtering

capacitance for buck

regulators

Effective capacitance, connected from VIN_Bx

to PGND_Bx

C_{IN_BUCK}

1.9

10

22

µF

Output filtering

capacitance for buck

regulators

C_{OUT_BUCK}

Effective capacitance per phase

500

µF

Point-of-load (POL)

capacitance for buck

regulators

C_{POL_BUCK}

Optional POL capacitance

µF

C_OUT-

Buck output capacitance,

total (local and POL)

Total output capacitance per phase

TOTAL_BUCK

Input filtering

capacitance for LDO

regulators

Effective capacitance, connected from

VIN_LDOx to AGND. C_{IN_LDO}must be at least

two times larger than C_{OUT_LDO}

C_{IN_LDO}

0.6

0.4

2.2

1

Output filtering

capacitance for LDO

regulators

C_{OUT_LDO}

Effective capacitance

2.7

10

µF

Input and output

capacitor ESR

ESR_C

[1-10] MHz

2

mΩ

0.47

L

Inductor

Inductance of the inductor

µH

–30%

30%

DCR_L

Inductor DCR

25

mΩ

BUCK REGULATORS

V_{(VIN_Bx)}

V_(VANA)

,

VIN_Bx and VANA pins must be connected to

the same supply line

Input voltage range

Output voltage

2.8

0.7

3.7

5.5

V

Programmable voltage range

1

10

5

3.36

Step size, 0.7 V ≤ V_OUT< 0.73 V

Step size, 0.73 V ≤ V_OUT< 1.4 V

Step size, 1.4 V ≤ V_OUT≤ 3.36 V

Output current, single-phase output

Output current, dual-phase output

V_{OUT_Bx}

mV

20

2⁽³⁾

4⁽³⁾

I_{OUT_Bx}

Output current

A

V

Input and Output voltage Minimum voltage between V_{(VIN_Bx)}and

difference

0.8

V_OUTto fulfill the electrical characteristics

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6.5 Electrical Characteristics (continued)

Limits apply over the junction temperature range –40°C ≤ T_J≤ +140°C, specified V_VANA, V_{VIN_Bx}, V_{VIN_LDOx}, V_{VOUT_Bx}

,

V_{VOUT_LDOx}and I_OUTrange, unless otherwise noted. Typical values are at T_J= 25°C, V_VANA= V_{VIN_Bx}= V_{VIN_LDOx}= 3.7 V,

and V_OUT= 1 V, unless otherwise noted^{(1) (2)}

.

PARAMETER

TEST CONDITIONS

MIN

–20

TYP

MAX UNIT

Force PWM mode, V_OUT< 1 V

Force PWM mode, V_OUT≥ 1 V

20

mV

DC output voltage

accuracy, includes

voltage reference, DC

load and line regulations,

process and temperature

–2%

2%

PFM mode, V_OUT< 1 V, the average output

voltage level is increased by max. 20 mV

V_{OUT_Bx_DC}

–20

40

mV

PFM mode, V_OUT≥ 1 V, the average output

voltage level is increased by max. 20 mV

2% + 20

mV

–2%

PWM mode

10

25

Ripple voltage, single-

phase output

mV_p-p

PFM mode, I_OUT= 10 mA

PWM mode

5

Ripple voltage, dual-

phase output

mV_p-p

%/V

PFM mode, I_OUT= 10 mA

I_OUT= 1 A

4

DC_LNR

DC_LDR

DC line regulation

±0.05

DC load regulation in

PWM mode

V_{OUT_Bx}= 1 V, I_OUTfrom 0 to I_OUT(max)

0.3%

±55

Transient load step

I_OUT= 0.1 A to 2 A, T_R= T_F= 400 ns, PWM

mV

response, single-phase mode

output

T_LDSR

Transient load step

response, dual-phase

output

I_OUT= 0.1 A to 4 A, T_R= T_F= 400 ns, PWM

mode

±50

±10

V_{(VIN_Bx)}stepping 3 V ↔ 3.5 V, T_R= T_F= 10

µs, I_OUT= I_OUT(max)

T_LNSR

Transient line response

mV

A

Programmable range

1.5

3

Forward current limit per

phase (peak for every

switching cycle)

Step size

0.5

7.5%

I_{LIM FWD}

Accuracy, V_{(VIN_Bx)}≥ 3 V, I_LIM= 3 A

Accuracy, 2.8 V ≤ V_{(VIN_Bx)}< 3 V, I_LIM= 3 A

–5%

20%

–20%

Negative current limit per

phase

I_{LIM NEG}

1.6

2.0

50

3.0

A

On-resistance, high-side Each phase, between VIN_Bx and SW_Bx

FET pins (I = 1 A)

R_{DS(ON) HS FET}

110

mΩ

On-resistance, low-side Each phase, between SW_Bx and PGND_Bx

R_{DS(ON) LS FET}

ƒ_SW

45

2

90

2.2

mΩ

FET

pins (I = 1 A)

Switching frequency

PWM mode

1.8

MHz

Current balancing for

dual-phase output

Current mismatch between phases, I_OUT> 1

mA

10%

From ENx to V_{OUT_Bx}= 0.35 V (slew-rate

control begins)

Start-up time (soft start)

120

10

µs

SLEW_RATEx[2:0] = 010, C_{OUT-TOTAL_BUCK}

80 µF per phase

<

SLEW_RATEx[2:0] = 011, C_{OUT-TOTAL_BUCK}

130 µF per phase

<

7.5

SLEW_RATEx[2:0] = 100, C_{OUT-TOTAL_BUCK}

250 µF per phase

3.8

Output voltage slew-

rate⁽⁴⁾

–15%

15% mV/µs

SLEW_RATEx[2:0] = 101, C_{OUT-TOTAL_BUCK}

< 500 µF per phase

1.9

SLEW_RATEx[2:0] = 110, C_{OUT-TOTAL_BUCK}

< 500 µF per phase

0.94

0.47

SLEW_RATEx[2:0] = 111, C_{OUT-TOTAL_BUCK}

< 500 µF per phase

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6.5 Electrical Characteristics (continued)

Limits apply over the junction temperature range –40°C ≤ T_J≤ +140°C, specified V_VANA, V_{VIN_Bx}, V_{VIN_LDOx}, V_{VOUT_Bx}

,

V_{VOUT_LDOx}and I_OUTrange, unless otherwise noted. Typical values are at T_J= 25°C, V_VANA= V_{VIN_Bx}= V_{VIN_LDOx}= 3.7 V,

and V_OUT= 1 V, unless otherwise noted^{(1) (2)}

.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

PFM-to-PWM - current

I_PFM-PWM

550

mA

threshold⁽⁵⁾

PWM-to-PFM - current

I_PWM-PFM

290

1000

650

mA

threshold⁽⁵⁾

Phase adding level

(dual-phase output)

I_ADD

From 1-phase to 2-phase

From 2-phase to 1-phase

Regulator disabled

Phase shedding level

(dual-phase output)

I_SHED

R_{DIS_Bx}

Output pulldown

resistance

150

250

350

Ω

V_{(VIN_Bx)}and V_(VANA)fixed 3.7 V

Overvoltage threshold (compared to DC output

39

–53

4

50

64

–29

15

Output voltage

voltage level, V_{VOUT_Bx_DC}

Undervoltage threshold (compared to DC

output voltage level, V_{VOUT_Bx_DC}

)

monitoring for PGOOD

pin and for power-good

Interrupt

mV

–40

)

Deglitch time during operation and after

voltage change

µs

Gating time for PGOOD

signal after regulator

PGOOD_MODE = 0

800

enable or voltage change

LDO REGULATORS

Input voltage range for

V_{IN_LDOx}

V_{IN_LDOx}can be higher or lower than V_(VANA)

2.5

0.8

3.7

0.1

5.5

3.3

V

LDO power inputs

Output voltage

Output current

Programmable voltage range

Step size

V_{OUT_LDOx}

I_{OUT_LDOx}

V

300

200

20

mA

V_{(VIN_LDOx)}– V_{(VOUT_LDOx)}, I_OUT= I_OUT(max)

Programmed output voltage is higher than

V_{(VIN_LDOx)}

,

Dropout voltage

mV

DC output voltage

V_OUT< 1 V

–20

accuracy, includes

V_{OUT_LDO_DC}

voltage reference, DC

load and line regulations,

process, temperature

V_OUT≥ 1 V

–2%

2%

DC_LNR

DC_LDR

DC line regulation

DC load regulation

I_OUT= 1 mA

0.1

%/V

I_OUT= 1 mA to I_OUT(max)

0.8%

Transient load step

response

T_LDSR

T_LNSR

PSRR

I_OUT= 1 mA to 300 mA, T_R= T_F= 1 µs

–50/+40

±7

mV

dB

V_{(VIN_LDOx)}stepping 3 V ↔ 3.5 V, T_R= T_F= 10

µs, I_OUT= I_OUT(max)

Transient line response

Power supply ripple

rejection

ƒ = 10 kHz, I_OUT= I_OUT(max)

53

Noise

10 Hz < F < 100 kHz, I_OUT= I_OUT(max)

V_OUT= 0 V

82

500

300

15

µV_rms

mA

I_SHORT(LDOx)

LDO current limit

Start-up time

400

150

600

350

From enable to valid output voltage

µs

Slew rate during start-up

mV/µs

Output pulldown

resistance

R_{DIS_LDOx}

Regulator disabled

250

Ω

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6.5 Electrical Characteristics (continued)

Limits apply over the junction temperature range –40°C ≤ T_J≤ +140°C, specified V_VANA, V_{VIN_Bx}, V_{VIN_LDOx}, V_{VOUT_Bx}

,

V_{VOUT_LDOx}and I_OUTrange, unless otherwise noted. Typical values are at T_J= 25°C, V_VANA= V_{VIN_Bx}= V_{VIN_LDOx}= 3.7 V,

and V_OUT= 1 V, unless otherwise noted^{(1) (2)}

.

PARAMETER

TEST CONDITIONS

MIN

106%

3%

TYP

108%

3.5%

92%

MAX UNIT

Overvoltage monitoring, voltage rising

(compared to DC output voltage level,

110%

4%

V_{OUT_LDO_DC}

)

Overvoltage monitoring, hysteresis

Output voltage

monitoring for PGOOD

pin and for power-good

interrupt

Undervoltage monitoring, voltage falling

(compared to DC output voltage level,

90%

94%

4%

V_{OUT_LDO_DC}

)

Undervoltage monitoring, hysteresis

3%

4

3.5%

Deglitch time during operation and after

voltage change

15

µs

Gating time for PGOOD

signal after regulator

PGOOD_MODE = 0

800

enable or voltage change

EXTERNAL CLOCK AND PLL

Nominal frequency

1

24

MHz

µs

f_{EXT_CLK}

External input clock⁽⁶⁾

Nominal frequency step size

1

Required accuracy from nominal frequency

Delay for missing clock detection

Delay and debounce for clock detection

–30%

10%

1.8

20

External clock detection

Clock change delay

(internal to external)

Delay from valid clock detection to use of

external clock

600

300

µs

PLL output clock jitter

Cycle to cycle

ps, p-p

PROTECTION FUNCTIONS

Temperature rising, TDIE_WARN_LEVEL = 0

115

127

125

137

20

135

147

Thermal warning

Temperature rising, TDIE_WARN_LEVEL = 1

Hysteresis

°C

Temperature rising

Hysteresis

140

150

20

160

Thermal shutdown

VANA overvoltage

Voltage rising

5.6

5.45

40

5.8

6.1

V

mV

V

VANA_OVP

Voltage falling

5.73

5.96

Hysteresis

Voltage rising

2.51

2.5

2.63

2.6

2.75

2.7

VANA undervoltage

lockout

VANA_UVLO

Voltage falling

Buck short-circuit

detection

Threshold

280

190

360

300

440

450

mV

LDO short-circuit

detection

LOAD CURRENT MEASUREMENT FOR BUCK REGULATORS

Current measurement

Maximum code

range

10.22

A

Resolution

Measurement accuracy I_OUT> 1 A per phase

PFM mode (automatically changing to PWM

LSB

20

mA

<10%

45

4

mode for the measurement)

Measurement time

µs

PWM mode

CURRENT CONSUMPTION

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6.5 Electrical Characteristics (continued)

Limits apply over the junction temperature range –40°C ≤ T_J≤ +140°C, specified V_VANA, V_{VIN_Bx}, V_{VIN_LDOx}, V_{VOUT_Bx}

,

V_{VOUT_LDOx}and I_OUTrange, unless otherwise noted. Typical values are at T_J= 25°C, V_VANA= V_{VIN_Bx}= V_{VIN_LDOx}= 3.7 V,

and V_OUT= 1 V, unless otherwise noted^{(1) (2)}

.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Standby current

consumption, regulators

disabled

9

µA

Active current

consumption, one buck

regulator enabled in

auto mode, internal

RC oscillator, PGOOD

monitoring enabled

Single-phase output: I_{OUT_Bx}= 0 mA, not

switching

58

100

72

µA

Active current

consumption, two buck

regulators enabled in

auto mode, internal

RC oscillator, PGOOD

monitoring enabled

Single-phase output: I_{OUT_Bx}= 0 mA, not

switching

Active current

consumption, one buck

regulator enabled in

auto mode, internal

RC oscillator, PGOOD

monitoring enabled

Dual-phase output: I_{OUT_Bx}= 0 mA, not

switching

Active current

consumption during

PWM operation, one

buck regulator enabled

Single-phase output: I_{OUT_Bx}= 0 mA

Dual-phase output: I_{OUT_Bx}= 0 mA

15

30

15

mA

Active current

consumption during

PWM operation, two

buck regulators enabled

Active current

consumption during

PWM operation, buck

regulator enabled

Additional current consumption per LDO,

I_{OUT_LDOx}= 0 mA

LDO regulator enabled

86

2

µA

PLL and clock detector

current consumption

f_{EXT_CLK}= 1 MHz, Additional current

consumption when enabled

mA

DIGITAL INPUT SIGNALS EN, SCL, SDA, CLKIN

V_IL

V_IH

Input low level

Input high level

0.4

V

1.2

10

Hysteresis of Schmitt

Trigger inputs

V_HYS

80

200

mV

kΩ

EN/CLKIN pulldown

resistance

EN_PD/CLKIN_PD = 1

500

DIGITAL OUTPUT SIGNALS nINT, SDA

nINT: I_SOURCE= 2 mA

SDA: I_SOURCE= 20 mA

0.4

V

V_OL

R_P

Output low level

External pullup resistor

for nINT

To VIO Supply

10

kΩ

DIGITAL OUTPUT SIGNALS PGOOD, GPO, GPO2

V_OL

V_OH

Output low level

I_SOURCE= 2 mA

I_SINK= 2 mA

0.4

V

Output high level,

configured to push-pull

V_VANA– 0.4

V_VANA

10

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6.5 Electrical Characteristics (continued)

Limits apply over the junction temperature range –40°C ≤ T_J≤ +140°C, specified V_VANA, V_{VIN_Bx}, V_{VIN_LDOx}, V_{VOUT_Bx}

,

V_{VOUT_LDOx}and I_OUTrange, unless otherwise noted. Typical values are at T_J= 25°C, V_VANA= V_{VIN_Bx}= V_{VIN_LDOx}= 3.7 V,

and V_OUT= 1 V, unless otherwise noted^{(1) (2)}

.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Supply voltage for

V_PU

external pullup resistor,

configured to open-drain

V_VANA

V

External pullup resistor,

configured to open-drain

R_PU

10

kΩ

ALL DIGITAL INPUTS

I_LEAKInput current

All logic inputs over pin voltage range

−1

1

µA

(1) All voltage values are with respect to network ground.

(2) Minimum (MIN) and Maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers are not verified,

but do represent the most likely norm.

(3) The maximum output current can be limited by the forward current limit I_{LIM FWD}. The power dissipation inside the die increases the

junction temperature and limits the maximum current depending of the length of the current pulse, efficiency, board and ambient

temperature.

(4) The slew-rate can be limited by the current limit (forward or negative current limit), output capacitance and load current.

(5) The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage and

the inductor current level.

(6) The external clock frequency must be selected so that buck switching frequency is above 1.7 MHz.

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6.6 I²C Serial Bus Timing Parameters

These specifications are ensured by design. Unless otherwise noted, V_{IN_Bx}= 3.7 V (see ⁽¹⁾). See Figure 6-1 for details about

the I²C-Compatible Timing diagram.

MIN

MAX

100

400

1

UNIT

Standard mode

kHz

Fast mode

f_SCL

Serial clock frequency

Fast mode+

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

3.4

1.7

MHz

µs

4.7

1.3

0.5

0.16

0.32

4

Fast mode

t_LOW

SCL low time

Fast mode+

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

Fast mode

0.6

0.26

0.06

0.12

250

100

50

t_HIGH

SCL high time

Data setup time

Data hold time

Fast mode+

µs

ns

µs

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

Fast mode

t_SU;DAT

t_HD;DAT

t_SU;STA

Fast mode+

High-speed mode

Standard mode

10

3450

900

Fast mode

10

Fast mode+

10

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

10

70

10

150

4.7

0.6

0.26

0.16

4

Setup time for a start

or a repeated start

condition

Fast mode

Fast mode+

High-speed mode

Standard mode

Fast mode

0.6

0.26

0.16

4.7

1.3

0.5

4

Hold time for a start or a

repeated start condition

t_HD;STA

µs

Fast mode+

High-speed mode

Standard mode

Bus free time between a

stop and start condition

t_BUF

Fast mode

Fast mode +

Standard mode

Fast mode

0.6

0.26

0.16

Setup time for a stop

condition

t_SU;STO

Fast mode+

High-speed mode

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6.6 I²C Serial Bus Timing Parameters (continued)

These specifications are ensured by design. Unless otherwise noted, V_{IN_Bx}= 3.7 V (see ⁽¹⁾). See Figure 6-1 for details about

the I²C-Compatible Timing diagram.

MIN

MAX

1000

300

120

80

UNIT

Standard mode

Fast mode

20

t_rDA

Rise time of SDA signal Fast mode+

ns

High-speed mode, C_b= 100 pF

10

20

High-speed mode, C_b= 400 pF

Standard mode

160

300

20 × (V_DD/ 5.5

V)

Fast mode

300

120

t_fDA

Fall time of SDA signal

20 × (V_DD/ 5.5

V)

ns

Fast mode+

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

10

30

80

160

1000

300

120

40

Fast mode

20

t_rCL

Rise time of SCL signal Fast mode+

High-speed mode, C_b= 100 pF

ns

10

20

10

High-speed mode, C_b= 400 pF

80

Rise time of SCL signal High-speed mode, C_b= 100 pF

after a repeated start

80

t_rCL1

condition and after an

acknowledge bit

High-speed mode, C_b= 400 pF

20

160

Standard mode

Fast mode

300

20 × (V_DD/ 5.5

V)

t_fCL

Fall time of a SCL signal

20 × (V_DD/ 5.5

V)

ns

Fast mode+

120

High-speed mode, C_b= 10 – 100 pF

High-speed mode, C_b= 400 pF

10

20

40

80

Capacitive load for each

bus line (SCL and SDA)

C_b

400

50

pF

ns

Pulse width of spike

suppressed (SCL and

SDA spikes that are less

then the indicated width

are suppressed)

Standard mode, fast mode, and fast mode+

High-speed mode

t_SP

10

(1) C_brefers to the capacitance of one bus line.

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t_BUF

SDA

t_HD;STA

t_rCL

t_fDA

t_rDA

t_SP

t_LOW

t_fCL

SCL

t_HD;STA

t_SU;STA

t_SU;STO

t_HIGH

t_HD;DAT

S

t_SU;DAT

S

RS

P

START

REPEATED

START

STOP

START

Figure 6-1. I²C-Compatible Timing

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6.7 Typical Characteristics

Unless otherwise specified: V_{(VIN_Bx)}= V_{(VIN_LDOx)}= V_(VANA)= 3.7 V, V_{OUT_Bx}= 1 V, V_{OUT_LDO}= 1 V, T_A= 25°C, L = 0.47 µH

(TOKO DFE252012PD-R47M), C_{OUT_BUCK}= 22 µF / phase, C_{POL_BUCK}= 22 µF, and C_{OUT_LDO}= 1 µF.

15

14

13

12

11

10

9

70

68

66

64

62

60

58

56

54

52

50

8

7

6

5

2.5

3

3.5

4

Input Voltage (V)

4.5

5

5.5

2.5

3

3.5

4

Input Voltage (V)

4.5

5

5.5

D101

D102

Regulators disabled

V_{OUT_Bx}= 1 V

Load = 0 mA

Figure 6-2. Standby Current Consumption vs Input Voltage

Figure 6-3. Active State Current Consumption vs Input Voltage,

One Buck Regulator Enabled in PFM Mode (single-phase)

24

22

20

18

16

14

12

10

8

90

87

84

81

78

75

72

69

66

63

60

6

4

2.5

3

3.5

4

Input Voltage (V)

4.5

5

5.5

2.5

3

3.5

4

Input Voltage (V)

4.5

5

5.5

D103

D422

V_{OUT_Bx}= 1 V

Load = 0 mA

V_{OUT_Bx}= 1 V

Load = 0 mA

Figure 6-5. Active State Current Consumption vs Input Voltage,

One Buck Regulator Enabled in Forced PWM Mode (single-

phase)

Figure 6-4. Active State Current Consumption vs Input Voltage,

Regulator Enabled in PFM Mode (dual-phase)

100

98

96

94

92

90

88

86

84

82

80

24

22

20

18

16

14

12

10

8

6

4

2.5

3

3.5

4

Input Voltage (V)

4.5

5

5.5

2.5

3

3.5

4

Input Voltage (V)

4.5

5

5.5

D104

D423

V_{OUT_LDOx}= 1 V

Load = 0 mA

'

V_{OUT_Bx}= 1 V

Load = 0 mA

Figure 6-7. Active State Current Consumption vs Input Voltage,

One LDO Regulator Enabled

Figure 6-6. Active State Current Consumption vs Input Voltage,

Regulator Enabled in Forced PWM Mode (dual-phase)

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7 Detailed Description

7.1 Overview

The LP8732xx-Q1 is a high-efficiency, high-performance flexible power supply device with two step-down

DC/DC converter cores (Buck0 and Buck1) and two low-dropout (LDO) linear regulators (LDO0 and LDO1)

for automotive applications. The cores can be configured for a two single-phase output and dual-phase single

output configuration. Table 7-1 lists the output characteristics of the regulators.

Table 7-1. Supply Specification

OUTPUT

SUPPLY

V_OUTRANGE (V)

RESOLUTION (mV)

10 (0.7 V to 0.73 V)

I_MAXMAXIMUM OUTPUT CURRENT (mA)

Buck0 (single-phase)

Buck1 (single-phase)

0.7 to 3.36

5 (0.73 V to 1.4 V)

20 (1.4 V to 3.36 V)

2000

10 (0.7 V to 0.73 V)

5 (0.73 V to 1.4 V)

20 (1.4 V to 3.36 V)

0.7 to 3.36

2000

4000

10 (0.7 V to 0.73 V)

5 (0.73 V to 1.4 V)

20 (1.4 V to 3.36 V)

Buck0 and Buck1

(dual-phase)

LDO0

LDO1

0.8 to 3.3

100

300

The LP8732xx-Q1 also supports switching clock synchronization to an external clock (CLKIN pin). The nominal

frequency of the external clock can be from 1 MHz to 24 MHz with 1-MHz steps.

Additional features include:

•

Soft-start

Input voltage protection:

– Undervoltage lockout

– Overvoltage protection

Output voltage monitoring and protection:

•

– Overvoltage monitoring

– Undervoltage monitoring

– Overload protection

Thermal warning

•

Thermal shutdown

The LP8732xx-Q1 has one dedicated general purpose digital output (GPO) signal. The CLKIN pin can be

programmed as a second GPO signal (GPO2), if the external clock is not needed. The output type (open-drain

or push-pull) is programmable for the GPOs.

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7.2 Functional Block Diagram

VANA

nINT

Interrupts

Buck0

ILIM Det

Pwrgood Det

Enable

and Disable,

Delay

Control

Slew-Rate

Control

Overload and

SC Det

EN

Iload ADC

GPO

Buck1

ILIM Det

Pwrgood Det

SDA

SCL

I2C

Overload and

SC Det

Iload ADC

OTP

EPROM

Registers

LDO0

PGOOD

ILIM Det

Pwrgood Det

Overload

Digital

Logic

and SC Det

Thermal

Monitor

UVLO

LDO1

ILIM Det

Pwrgood Det

Overload

SW

Reset

Ref &

Bias

Oscillator

and SC Det

CLKIN (GPO2)

7.3 Feature Description

7.3.1 DC/DC Converters

7.3.1.1 Overview

The LP8732xx-Q1 includes two step-down DC/DC converter cores. The cores are designed for flexibility; most of

the functions are programmable, thus giving a possibility to optimize the regulator operation for each application.

The cores can be configured either for a dual-phase single output configuration or for a single-phase dual output

configuration. The buck regulators deliver 0.7-V to 3.36-V regulated voltage rails from a 2.8-V to 5.5-V supply

voltage.

The LP8732xx-Q1 has the following features:

•

DVS support with programmable slew rate

Automatic mode control based on the loading (PFM or PWM mode)

Forced PWM mode option

Optional external clock input to minimize crosstalk

Optional spread-spectrum technique to reduce EMI

Phase control for optimized EMI

Synchronous rectification

Current mode loop with PI compensator

Soft start

Power Good flag with maskable interrupt

Power Good signal (PGOOD) with selectable sources

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•

Average output current sensing (for PFM entry, phase shedding and adding in dual-phase configuration, and

load current measurement)

•

Current balancing between the phases of the converter in dual-phase configuration

Differential voltage sensing from point of the load in dual-phase configuration

Dynamic phase shedding and adding, each output being phase shifted in dual-phase configuration

The following parameters can be programmed through the registers, the default values are set by OTP bits:

•

Output voltage

Forced PWM operation

Forced dual-phase operation (forces also the PWM operation)

Switch current limit

Output voltage slew rate

Enable and disable delays

There are two modes of operation for the buck converter, depending on the output current required: pulse-width

modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load

currents of approximately 600 mA or higher. When operating in PWM mode in dual-phase configuration the

phases are automatically added and shedded based on the load current level. Lighter output current loads cause

the converter to automatically switch into PFM mode for reduced current consumption when forced PWM mode

is disabled. The forced PWM mode can be selected to maintain fixed switching frequency at all load current

levels.

A block diagram of a single core is shown in Figure 7-1.

HS FET

CURRENT

SENSE

VIN

FB

POS

CURRENT

LIMIT

RAMP

GENERATOR

V

OUT

-

GATE

CONTROL

ERROR

AMP

SW

+

LOOP

COMP

VOLTAGE

SETTING

SLEW RATE

CONTROL

NEG

CURRENT

LIMIT

POWER

GOOD

+

-

VDAC

ZERO

CROSS

DETECT

LS FET

CURRENT

SENSE

MASTER

INTERFACE

PROGRAMMABLE

PARAMETERS

CONTROL

BLOCK

SLAVE

INTERFACE

IADC

GND

Figure 7-1. Detailed Block Diagram Showing One Core

7.3.1.2 Dual-Phase Operation and Phase-Adding/Shedding

Under heavy load conditions, the dual-phase converter switches both channel 180° apart. As a result, the

dual-phase converter has an effective ripple frequency two times greater than the switching frequency of a single

phase. However, the parallel operation decreases the efficiency at light load conditions. In order to overcome this

operational inefficiency, the LP8732xx-Q1 can change the number of active phases to optimize efficiency for the

variations of the load. This is called phase adding and shedding. The concept is shown in Figure 7-2.

The converter can be forced to dual-phase operation by the BUCK0_FPWM_MP bit in the BUCK0_CTRL_1

register. If the regulator operates in forced dual-phase mode the forced PWM operation is automatically used. If

the dual-phase operation is not forced, the number of phases are added and shedded automatically to follow the

required output current.

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BEST EFFICIENCY OBTAINED WITH

N=1

N=2

LOAD CURRENT

Figure 7-2. Multiphase Buck Converter Efficiency vs Number of Phases. All Converters in PWM mode.

(UPDATE) ¹

Interleaving switching action of the converters and channels in a 2-phase configuration is shown in Figure 7-3.

1

Graph is not in scale and is for illustrative purposes only.

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I_{L_TOT_2PH}

I_L0

I_L1

0

90

180

270

360

450

540

630

720

PWM₀

PWM₁

SWITCHING CYCLE 360º

0

90

180

270

360

450

540

630

720

PHASE, DEGREES

Figure 7-3. PWM Timings and Inductor Current Waveforms in 2-phase Configuration. (UPDATE) ²

7.3.1.3 Transition Between PWM and PFM Modes

The PWM mode operation with phase-adding and shedding optimizes efficiency at mid to full load at the

expense of light-load efficiency. The LP8732xx-Q1 converter operates in the PWM mode at load current of about

600 mA or higher. At lighter load current levels the device automatically switches into the PFM mode for reduced

current consumption when forced PWM mode is disabled (AUTO mode operation). By combining the PFM and

the PWM modes, a high efficiency is achieved over a wide output-load current range.

7.3.1.4 Dual-Phase Switcher Configurations

The LP8732xx-Q1 device supports the following regulator configurations:

•

Single dual-phase configuration, Buck0 is master (Buck0 and Buck1)

Two single-phase configuration (Buck0 and Buck1)

In the dual-phase configuration the control of the dual-phase regulator settings is done using the control registers

of the master buck. The following slave registers are ignored:

•

The BUCK1_CTRL_1 (except the EN_RDIS1 bit)

The BUCK1_CTRL_2 (except the ILIM1[2:0] bits)

The BUCK1_VOUT

The BUCK1_DELAY

The Interrupt bits related to the slave buck (except the BUCK1_ILIM_INT)

7.3.1.5 Buck Converter Load Current Measurement

The buck load current can be monitored through I²C registers. The monitored buck converter is selected with

the LOAD_CURRENT_BUCK_SELECT bit in the SEL_I_LOAD register. A write to this selection register starts a

current measurement sequence. The regulator is automatically forced to the PWM mode for the measurement

period. The measurement sequence is 50 µs long, maximum.

2

Graph is not in scale and is for illustrative purposes only.

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The LP8732xx-Q1 device can be configured to give out an interrupt (the I_MEAS_INT bit in the INT_TOP_1

register) after the load current measurement sequence is finished. The load current measurement interrupt can

be masked with the I_MEAS_MASK bit (TOP_MASK_1 register). The measurement result can be read from

the registers I_LOAD_1 and I_LOAD_2. The register I_LOAD_1 bits BUCK_LOAD_CURRENT[7:0] gives out the

LSB bits, and the register I_LOAD_2 bit BUCK_LOAD_CURRENT[8] gives out the MSB bit. The measurement

result BUCK_LOAD_CURRENT[8:0] LSB is 20 mA, and the maximum code value of the measurement

corresponds to 10.22 A. In dual-phase configuration, the measured current is the total value of the master

and slave phases.

7.3.1.6 Spread-Spectrum Mode

Systems with periodic switching signals may generate a large amount of switching noise in a set of narrowband

frequencies (the switching frequency and its harmonics). The usual solution to reduce noise coupling is to add

EMI-filters and shields to the boards. The LP8732xx-Q1 has a register-selectable spread-spectrum mode which

minimizes the need for output filters, ferrite beads, or chokes. In spread spectrum mode, the switching frequency

varies around the center frequency, reducing the EMI emissions radiated by the converter and associated

passive components and PCB traces (see Figure 7-4). Spread-spectrum mode is only available when an internal

RC oscillator is used (EN_PLL bit is 0 in PLL_CTRL register), it is enabled with the EN_SPREAD_SPEC bit in

the CONFIG register, and it affects both buck cores.

Frequency

Where a fixed frequency converter exhibits large amounts of spectral energy at the switching frequency, the spread spectrum

architecture of the LP8732xx-Q1 spreads that energy over a large bandwidth.

Figure 7-4. Spread-Spectrum Modulation

7.3.2 Sync Clock Functionality

The LP8732xx-Q1 device contains a CLKIN input to synchronize the switching clock of the buck regulators with

the external clock. The block diagram of the clocking and PLL module is shown in Figure 7-5. Depending on

the EN_PLL bit in the PLL_CTRL register and the external clock availability, the external clock is selected and

interrupt is generated as shown in Table 7-2. The interrupt can be masked with the SYNC_CLK_MASK bit in

the TOP_MASK_1 register. The nominal frequency of the external input clock is set by the EXT_CLK_FREQ[4:0]

bits in the PLL_CTRL register, and it can be from 1 MHz to 24 MHz with 1-MHz steps. The external clock must

be inside accuracy limits (–30%/+10%) of the selected frequency for valid clock detection.

The SYNC_CLK_INT interrupt in the INT_TOP_1 register is also generated in cases where the external clock

is expected but is not available. These cases occur when EN_PLL is 1 during start-up (read OTP-to-standby

transition) and during Buck regulator enable (standby-to-active transition).

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24 MHz

RC

Oscillator

Internal

24 MHz

clock

CLKIN

Detector

Divider

“EXT_CLK

_FREQ“

Clock Select

Logic

1 MHz

CLKIN

24 MHz

PLL

“EN_PLL“

1 MHz

Divider

24

Figure 7-5. Clock and PLL Module

Table 7-2. PLL Operation

DEVICE

OPERATION MODE

PLL AND CLOCK

DETECTOR STATE

INTERRUPT FOR

EXTERNAL CLOCK

EN_PLL

CLOCK

STANDBY

ACTIVE

0

Disabled

No

Internal RC

When external clock

appears or disappears

Automatic change to external

clock when available

STANDBY

ACTIVE

1

Enabled

When external clock

appears or disappears

Automatic change to external

clock when available

7.3.3 Low-Dropout Linear Regulators (LDOs)

The LP8732xx-Q1 device includes two identical linear regulators, LDO0 and LDO1, which target analog loads

with low noise requirements. The LDO regulators deliver 0.8-V to 3.3-V regulated voltage rails from a 2.5-V to

5.5-V input voltage. Both regulators have dedicated inputs which can be higher or lower than the device system

voltage V_(VANA)to minimize the power dissipation.

7.3.4 Power-Up

The power-up sequence for the LP8732xx-Q1 is as follows:

•

The VANA and VIN_Bx reach minimum recommended levels (V_VANA> VANA_UVLO). This initiates power-on-

reset (POR), OTP reading, and enables the system I/O interface. The I²C host should allow at least 1.2 ms

before writing or reading data to the LP8732xx-Q1.

•

The device enters standby mode.

The host can change the default register setting by I²C if needed.

The regulators can be enabled and disabled.

The GPO signals can be controlled by the EN pin and the I²C interface.

Transitions between the operating modes are shown in Section 7.4.1.

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7.3.5 Regulator Control

7.3.5.1 Enabling and Disabling Regulators

The regulators can be enabled when the device is in STANDBY or ACTIVE state. There are two ways to enable

and disable the buck regulators:

•

Using the BUCKx_EN bit in the BUCKx_CTRL_1 register (the BUCKx_EN_PIN_CTRL bit is 0 in the

BUCKx_CTRL_1 register).

•

Using the EN control pin (the BUCKx_EN bit and the BUCKx_EN_PIN_CTRL bit is 1).

Similarly, there are two ways to enable and disable the LDO regulators:

•

Using the LDOx_EN bit in the LDOx_CTRL register (the LDOx_EN_PIN_CTRL bit is 0 in the LDOx_CTRL

register).

•

Using the EN control pin (the LDOx_EN bit is 1 and the LDOx_EN_PIN_CTRL bit is 1).

If the EN control pin is used for enable and disable, then the following occurs:

•

The delay from the control signal rising edge to start-up is set by the BUCKx_STARTUP_DELAY[3:0] bits in

the BUCKx_DELAY register and the LDOx_STARTUP_DELAY[3:0] bits in the LDOx_DELAY register.

The delay from the control signal falling edge to shutdown is set by the BUCKx_SHUTDOWN_DELAY[3:0]

bits in the BUCKx_DELAY register and the LDOx_SHUTDOWN_DELAY[3:0] bits in the LDOx_DELAY

register.

The delays are only valid for the EN signal transitions and not for control with I²C writings to the BUCKx_EN and

the LDOx_EN bits.

The control of the regulator (with 0-ms delays) is shown in Table 7-3. Dual-phase regulator is controlled with

registers of the master phase.

Table 7-3. Regulator Control

BUCKx_EN AND

LDOx_EN

BUCKx_EN_PIN_CTRL AND

LDOx_EN_PIN_CTRL

BUCKx OUTPUT VOLTAGE AND

LDOx OUTPUT VOLTAGE

EN PIN

Enable and disable control

with the BUCKx_EN and the

LDOx_EN bit

0

1

Don't Care

0

Don't Care

Disabled

BUCKx_VSET[7:0] and LDOx_VSET[4:0]

Enable and disable control

with the EN pin

1

Low

Disabled

High

BUCKx_VSET[7:0] and LDOx_VSET[4:0]

The buck regulator is enabled by the EN pin or by I²C writing, as shown in Figure 7-6. The soft-start circuit

limits the in-rush current during start-up. When the output voltage rises to a 0.35-V level, the output voltage

becomes slew-rate controlled. If there is a short circuit at the output, and the output voltage does not increase

above the 0.35-V level in 1 ms or the output voltage drops below 0.35-V level during operation (for minimum

of 1 ms), then the regulator is disabled, and the BUCKx_SC_INT interrupt in the INT_BUCK register is set.

When the output voltage reaches the the Power-Good threshold level, the BUCKx_PG_INT interrupt flag in

the INT_BUCK register is set. The Power-Good interrupt flag, when reaching the valid output voltage, can be

masked using the BUCKx_PGR_MASK bit in the BUCK_MASK register. The Power-Good interrupt flag can also

be generated when the output voltage becomes invalid. The interrupt mask for invalid output voltage detection

is set by the BUCKx_PGF_MASK bit in the BUCK_MASK register. A BUCKx_PG_STAT bit in the BUCK_STAT

register always shows the validity of the output voltage; 1 means valid and 0 means invalid output voltage.

A PGOOD_WINDOW_BUCK bit in the PGOOD_CTRL_1 register sets the detection method for the valid buck

output voltage, either under-voltage detection, or under-voltage and over-voltage detection.

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Voltage decrease because of load

Voltage

BUCKx_VSET[7:0]

Powergood

Ramp

BUCKx_CTRL_2(BUCKx_SLEW_RATE[2:0])

0.6V

0.35V

Time

Resistive pull-down

(if enabled)

Soft start

Enable

BUCK_STAT(BUCKx_STAT)

BUCK_STAT(BUCKx_PG_STAT)

INT_BUCK(BUCKx_PG_INT)

nINT

0

1

0

1

0

1

0

0 1

0

Powergood

interrupts

Host clears

interrupts

BUCK_MASK(BUCKx_PGF_MASK) = 0

BUCK_MASK(BUCKx_PGR_MASK) = 0

Figure 7-6. Buck Regulator Enable and Disable

The LDO regulator is enabled by the EN pin or by I²C writing, as shown in Figure 7-7. The soft-start circuit

limits the in-rush current during start-up. The output voltage increase rate is less than 100 mV/μsec during

soft-start. If there is a short circuit at the output, and the output voltage does not increase above the 0.3-V

level in 1 ms or the output voltage drops below 0.3-V level during operation (for minimum of 1 ms), then the

regulator is disabled, and the LDOx_SC_INT interrupt in the INT_LDO register is set. When the output voltage

reaches the Power-Good threshold level, the LDOx_PG_INT interrupt flag in the INT_LDO register is set. The

Power-Good interrupt flag, when reaching valid output voltage, can be masked using the LDOx_PGR_MASK

bit in the LDO_MASK register. The Power-Good interrupt flag can also be generated when the output voltage

becomes invalid. The interrupt mask for invalid output voltage detection is set by the LDOx_PGF_MASK bit

in the LDO_MASK register. A LDOx_PG_STAT bit in the LDO_STAT register always shows the validity of

the output voltage; 1 means valid, and 0 means invalid output voltage. A PGOOD_WINDOW_LDO bit in the

PGOOD_CTRL_1 register sets the detection method for the valid LDO output voltage, either undervoltage

detection or undervoltage and overvoltage detection.

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Voltage decrease because of load

Voltage

LDOx_VSET[4:0]

Powergood

Resistive pull-down

(if enabled)

Time

Enable

0

1

0

1

LDO_STAT(LDOx_STAT)

LDO_STAT(LDOx_PG_STAT)

INT_LDO(LDOx_PG_INT)

nINT

1

0

1

0

0 1

0

Powergood

interrupts

Host clears

interrupts

LDO_MASK(LDOx_PGF_MASK) = 0

LDO_MASK(LDOx_PGR_MASK) = 0

Figure 7-7. LDO Regulator Enable and Disable

The EN input pin has an integrated pulldown resistor. The pulldown resistor is controlled with the EN_PD bit in

the CONFIG register.

7.3.5.2 Changing Output Voltage

The output voltage of the regulator can be changed by writing to the BUCKx_VOUT and LDOx_VOUT register.

The voltage change for the buck regulator is always slew-rate controlled, and the slew-rate is defined by the

BUCKx_SLEW_RATE[2:0] bits in the BUCKx_CTRL_2 register. During voltage change, the forced PWM mode is

used automatically. If the dual-phase operation is forced by the BUCK0_FPWM_MP bit in the BUCK0_CTRL_1

register, the regulator operates in dual-phase mode. If the dual-phase operation is not forced, the number of

phases are added and shedded automatically to follow the required slew rate. When the programmed output

voltage is achieved, the mode becomes the one defined by the load current, the BUCKx_FPWM bit in the

BUCKx_CTRL_1 register, and the BUCK0_FPWM_MP bit.

The voltage change and Power-Good interrupts are shown in Figure 7-8.

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Ramp for Buck

BUCKx_CTRL2(SLEW_RATEx[2:0])

Voltage

BUCKx_VSET /

LDOx_VSET

Powergood

Time

BUCK_STAT(BUCKx_STAT) /

LDO_STAT(LDOx_STAT)

1

0

BUCK_STAT(BUCKx_PG_STAT) /

LDO_STAT(LDOx_PG_STAT)

0

1

0

1

INT_BUCK(BUCKx_PG_INT) /

INT_LDO(LDOx_PG_INT)

0

nINT

Powergood

interrupt

Host clears

interrupt

Powergood

interrupt

Host clears

interrupt

BUCK_MASK(BUCKx_PGF_MASK)=0

BUCK_MASK(BUCKx_PGR_MASK)=0

LDO_MASK(LDOx_PGF_MASK)=0

LDO_MASK(LDOx_PGR_MASK)=0

Figure 7-8. Regulator Output Voltage Change

During an LDO voltage change, the internal reference for the Power-Good detection is also changed. For this

reason when the output voltage is changing, toggling of the Power-Good signal may still indicate a valid output.

This period takes less than 100 µs and after that time the Power-Good gives correct value.

7.3.6 Enable and Disable Sequences

The LP8732xx-Q1 device supports start-up and shutdown sequencing with programmable delays for different

regulator outputs using a single EN control signal. The Buck regulator is selected for delayed control with:

•

The BUCKx_EN = 1 in the BUCKx_CTRL_1 register

The BUCKx_EN_PIN_CTRL = 1 in the BUCKx_CTRL_1 register

The BUCKx_VSET[7:0] bits in the BUCKx_VOUT register defines the voltage when the EN pin is high

The delay from the rising edge of the EN pin to the regulator enable is set by the

BUCKx_STARTUP_DELAY[3:0] bits in the BUCKx_DELAY register.

The delay from the falling edge of the EN pin to the regulator disable is set by the

BUCKx_SHUTDOWN_DELAY[3:0] bits in the BUCKx_DELAY register.

•

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In the same way, the LDO regulator is selected for delayed control with:

•

The LDOx_EN = 1 in the LDOx_CTRL register

The LDOx_EN_PIN_CTRL = 1 in the LDOx_CTRL register

The LDOx_VSET[4:0] bits in the LDOx_VOUT register defines the voltage when the EN pin is high

The delay from the rising edge of the EN pin to the regulator enable is set by the

LDOx_STARTUP_DELAY[3:0] bits in the LDOx_DELAY register.

•

The delay from the falling edge of the EN pin to the regulator disable is set by the

LDOx_SHUTDOWN_DELAY[3:0] bits in the LDOx_DELAY register.

The GPO and GPO2 digital output signals can be also controlled as a part of start-up and shutdown sequencing

with the following settings:

•

GPOx_EN = 1 in GPO_CTRL register

GPOx_EN_PIN_CTRL = 1 in GPO_CTRL register

The delay from the rising edge of the EN pin to the rising edge of the GPO or GPO2 signal is set by the

GPOx_STARTUP_DELAY[3:0] bits in the GPOx_DELAY register.

The delay from the falling edge of the EN pin to the falling edge of the GPO or GPO2 signal is set by the

GPOx_SHUTDOWN_DELAY[3:0] bits in the GPOx_DELAY register.

•

An example of the start-up and shutdown sequences for the buck regulators are shown in Figure 7-9. The

start-up and shutdown delays for the Buck0 regulator are 1 ms and 4 ms, and for the Buck1 regulator the

start-up and shutdown delays are 3 ms and 1 ms. The delay settings are only used for enable or disable control

with the EN signal.

Typical sequence

EN

EN_BUCK0

EN_BUCK1

1 ms

4 ms

3 ms

1 ms

Sequence with short EN low and high periods

EN

Startup cntr

0

1

0

1

2

3

4

5

6

0

2

Shutdown cntr

EN_BUCK0

EN_BUCK1

0

1

0

1

0

1

2

3

4

5

1 ms

4 ms

3 ms

1 ms

Figure 7-9. Start-Up and Shutdown Sequencing

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7.3.7 Device Reset Scenarios

There are two reset methods implemented on the LP8732xx-Q1:

•

Software reset with the SW_RESET bit in the RESET register.

Undervoltage lockout (UVLO) reset from the VANA supply.

An software reset occurs when 1 is written to the SW_RESET bit. The bit is automatically cleared after writing.

This event disables all the regulators immediately, drives the GPO or GPO2 signals low, resets all the register

bits to the default values, and loads the OTP bits (see Figure 7-15). The I²C interface is not reset during a

software reset.

If the VANA supply voltage falls below the UVLO threshold level, then all the regulators are disabled

immediately, the GPO or GPO2 signals are driven low, and all the register bits are reset to the default values.

When the VANA supply voltage transitions above the UVLO threshold level, an internal POR occurs. The OTP

bits are loaded to the registers and a startup is initiated according to the register settings.

7.3.8 Diagnosis and Protection Features

The LP8732xx-Q1 is capable of providing four levels of protection features:

•

Information of valid regulator output voltage, which sets the interrupt or PGOOD signal.

Warnings for diagnosis, which sets the interrupt.

Protection events, which are disabling the regulators.

Faults, which are causing the device to shutdown.

The LP8732xx-Q1 sets the flag bits indicating what protection or warning conditions have occurred, and the nINT

pin is pulled low. The nINT is released again after a clear of flags is complete. The nINT signal stays low until all

the pending interrupts are cleared.

When a fault is detected or software requested reset, it is indicated by a RESET_REG_INT interrupt flag in

the INT_TOP_2 register after next start-up. If the RESET_REG_MASK is set to masked in the OTP, then the

interrupt is not generated. The mask bit change with I²C does not affect, because the RESET_REG_MASK bit is

loaded from the OTP during reset sequence.

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Table 7-4. Summary of Interrupt Signals

RECOVERY AND INTERRUPT

CLEAR

EVENT

DEVICE RESPONSE

INTERRUPT BIT

INTERRUPT MASK BIT

STATUS BIT

Write 1 to the BUCKx_ILIM_INT

bit.

Interrupt is not cleared if the

current limit is active

BUCK_INT

BUCKx_ILIM_INT

Buck current limit triggered

LDO current limit triggered

No effect

BUCKx_ILIM_MASK

BUCKx_ILIM_STAT

Write 1 to the LDOx_ILIM_INT bit

Interrupt is not cleared if the

current limit is active

LDO_INT

LDOx_ILIM_INT

No effect

LDOx_ILIM_MASK

N/A

LDOx_ILIM_STAT

N/A

Buck short circuit (V_VOUT

<

0.35 V at 1 ms after enable)

BUCK_INT

BUCKx_SC_INT

or overload (V_VOUTdecreasing Regulator disable

below 0.35 V during operation,

1-ms debounce)

Write 1 to the BUCKx_SC_INT bit

Write 1 to the LDOx_SC_INT bit

LDO short circuit (V_VOUT

<

0.3 V at 1 ms after enable)

LDO_INT

LDOx_SC_INT

or overload (V_VOUTdecreasing Regulator disable

below 0.3 V during operation,

1-ms debounce)

N/A

Write 1 to tge TDIE_WARN_INT

bit

Thermal warning

No effect

TDIE_WARN_INT

TDIE_WARN_MASK

TDIE_WARN_STAT

Interrupt is not cleared if the

temperature is above the thermal

warning level

All the regulators are

disabled immediately, and

the GPO and GPO2 are

set to low

Write 1 to the TDIE_SD_INT bit

Interrupt is not cleared if the

temperature is above the thermal

shutdown level

Thermal shutdown

TDIE_SD_INT

OVP_INT

N/A

TDIE_SD_STAT

OVP_STAT

All the regulators are

disabled immediately, and

the GPO and GPO2 are

set to low

Write 1 to the OVP_INT bit

Interrupt is not cleared if the VANA

voltage is above the VANA_OVP

level

VANA overvoltage (VANA_OVP

)

Buck power good, output

voltage becomes valid

BUCK_INT

BUCKx_PG_INT

No effect

BUCKx_PGR_MASK

BUCKx_PGF_MASK

LDOx_PGR_MASK

LDOx_PGF_MASK

PGOOD_MASK

BUCKx_PG_STAT

LDOx_PG_STAT

PGOOD_STAT

SYNC_CLK_STAT

N/A

Write 1 to the BUCKx_PG_INT bit

Write 1 to the LDOx_PG_INT bit

Write 1 to the PGOOD_INT bit

Write 1 to the SYNC_CLK_INT bit

Write 1 to the I_MEAS_INT bit

Buck power good, output

voltage becomes invalid

BUCK_INT

BUCKx_PG_INT

No effect

LDO Power good, output

voltage becomes valid

LDO_INT

LDOx_PG_INT

No effect

LDO power good, output

voltage becomes invalid

LDO_INT

LDOx_PG_INT

No effect

PGOOD pin changing from

active to inactive state⁽¹⁾

No effect

PGOOD_INT

External clock appears or

disappears

No effect to regulators

No effect

SYNC_CLK_INT⁽²⁾

I_MEAS_INT

SYNC_CLK_MASK

I_MEAS_MASK

Load current measurement is

ready

Immediate shutdown and

the registers reset to

default values

Supply voltage VANA_UVLO

triggered (VANA falling)

N/A

Startup and the registers

reset to default values

and the OTP bits are

loaded

Supply voltage VANA_UVLO

triggered (VANA rising)

Write 1 to the RESET_REG_INT

bit

RESET_REG_INT

RESET_REG_MASK

Immediate shutdown is

followed by power up and

the registers are reset to

their default values

Write 1 to the RESET_REG_INT

bit

Software requested reset

RESET_REG_INT

RESET_REG_MASK

N/A

(1) The PGOOD_STAT bit is 1 when the PGOOD pin shows valid voltages. The PGOOD_POL bit in the PGOOD_CTRL_1 register affects

only the PGOOD pin polarity, not the Power Good and PGOOD_INT interrupt polarity.

(2) If the clock is not available when the clock detector is enabled, then an interrupt is generated during the clock-dector operation.

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7.3.8.1 Power-Good Information (PGOOD pin)

In addition to the interrupt-based indication of the current limit and the Power-Good level, the LP8732xx-Q1

device supports monitoring with PGOOD signal:

•

Regulator output voltage

Input supply overvoltage

Thermal warning

Thermal shutdown

The regulator output voltage monitoring (not current limit monitoring) can be selected for the PGOOD

indication. This selection is individual for both buck regulators (only master buck in dual-phase configuration)

and LDO regulators, and is set by the EN_PGOOD_BUCKx bits in the PGOOD_CTRL_1 register and the

EN_PGOOD_LDOx bits in the PGOOD_CTRL_1 register. When a regulator is disabled, the monitoring is

automatically masked to prevent it forcing the PGOOD inactive. A thermal warning can also be selected for

the PGOOD indication with the EN_PGOOD_TWARN bit in the PGOOD_CTRL_2 register. The monitoring from

all the output rails, thermal warning (TDIE_WARN_STAT), input overvoltage interrupt (OVP_INT), and thermal

shutdown interrupt (TDIE_SD_INT) are combined, and the PGOOD pin is active only if all the selected sources

shows a valid status.

The type of output voltage monitoring for the PGOOD signal is selected by the PGOOD_WINDOW_x bits in the

PGOOD_CTRL_1 register. If the bit is 0, only undervoltage is monitored; if the bit is 1, both undervoltage and

overvoltage are monitored.

The polarity and the output type (push-pull or open-drain) are selected by the PGOOD_POL and PGOOD_OD

bits in the PGOOD_CTRL_1 register.

The PGOOD is only active and asserted when all enabled power resource output voltages are within specified

tolerance for each requested and programmed output voltage.

The PGOOD is inactive and de-asserted if any enabled power resource output voltages is outside specified

tolerance for each requested and programmed output voltage.

The device OTP setting selects either gated (or unusual) or continuous (or invalid) mode of operation.

7.3.8.1.1 PGOOD Pin Gated Mode

The gated (or unusual) mode of operation is selected by setting the PGOOD_MODE bit to 0 in the

PGOOD_CTRL_2 register.

For the gated mode of operation, the PGOOD behaves as follows:

•

PGOOD is set to active or asserted state upon exiting the OTP configuration as an initial default state.

PGOOD status is suspended or unchanged during an 800-µs gated time period, thereby gating-off the status

indication.

•

During normal power-up sequencing and requested voltage changes, the PGOOD state is not changed

during an 800-µs gated time period. It typically remains active or asserted for normal conditions.

During an abnormal power-up sequencing and requested voltage changes, the PGOOD status could change

to inactive or de-asserted after an 800-µs gated time period if any output voltage is outside of regulation

range.

•

Using the gated mode of operation could allow the PGOOD signal to initiate an immediate power

shutdown sequence if the PGOOD signal is wired-OR with signal connected to the EN input. This type of

circuit configuration provides a smart PORz function for processor that eliminates the need for additional

components to generate PORz upon start-up and to monitor voltage levels of key voltage domains.

Each detected fault sets the correcting fault bit in the PG_FAULT register to 1. The detected fault must be

cleared to continue the PGOOD monitoring. The overvoltage and thermal shutdown are cleared by writing 1

to the OVP_INT and TDIE_SD_INT interrupt bits in the INT_TOP_1 register. The regulator fault is cleared by

writing 1 to the corresponding register bit in the PG_FAULT register. The interrupts can also be cleared with the

VANA UVLO by toggling the input supply. An example of the PGOOD pin operation in gated mode is shown in

Figure 7-10.

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V_(VANA)

VANA_UVLO

State

Read

OTP

Shutdown

Standby

Active

PGOOD pin

Clear fault

EN pin

4 ms

Buck internal enable

VOUT (Buck1)

800 µs Timer

Buck1 internal powergood

LDO0 internal enable

2 ms

800 µs Timer

VOUT (LDO0)

LDO0 internal powergood

Figure 7-10. PGOOD Pin Operation in Gated Mode

7.3.8.1.2 PGOOD Pin Continuous Mode

The continuous (or invalid) mode of operation is selected by setting the PGOOD_MODE bit to 1 in the

PGOOD_CTRL_2 register.

For the continuous mode of operation, PGOOD behaves as follows:

•

PGOOD is set to active or asserted state upon exiting OTP configuration.

PGOOD is set to inactive or de-asserted as soon as the regulator is enabled.

PGOOD status begins indicating output voltage regulation status immediately and continuously.

During power-up sequencing and requested voltage changes, PGOOD will toggle between inactive or

de-asserted while output voltages are outside of regulation ranges and active or asserted when inside of

regulation ranges.

The PG_FAULT register bits are latched, and maintain the fault information until the host clears the fault bit by

writing 1 to the bit. The PGOOD signal also indicates a thermal shutdown and input overvoltage interrupts, which

are cleared by clearing the interrupt bits.

When the regulator voltage is transitioning from one target voltage to another, the PGOOD signal becomes

inactive.

7.3.8.1.3 PGOOD Pin Inactive Mode

When the PGOOD signal becomes inactive, the source for the fault can be read from the PG_FAULT register.

If the invalid output voltage becomes valid again, then the PGOOD signal becomes active. Thus the PGOOD

signal always shows if the monitored output voltages are valid. The block diagram for this operation is shown in

Figure 7-11 and an example of operation is shown in Figure 7-12.

The PGOOD signal can also be configured so that it maintains an inactive state even when the monitored

outputs are valid, but there are PG_FAULT_x bits in the PG_FAULT register pending clearance. This type of

operation is selected by setting the PGFAULT_GATES_PGOOD bit to 1 in the PGOOD_CTRL_2 register.

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EN_PGOOD

_BUCK0

Power Good

Buck0

EN_PGOOD

_BUCK1

Power Good

Buck1

EN_PGOOD

_LDO0

Power Good

LDO0

PGOOD

Active High

EN_PGOOD

_LDO1

Power Good

LDO1

EN_PGOOD

_TWARN

TDIE_WARN_STAT

TDIE_SD_INT

OVP_INT

Figure 7-11. PGOOD Block Diagram (Continuous Mode)

V_(VANA)

VANA_UVLO

Read

OTP

Standby

State Shutdown

Active

PGOOD pin

EN pin

Buck1 internal enable

VOUT (Buck1)

4 ms

Buck1 internal powergood

LDO0 internal enable

2 ms

VOUT (LDO0)

LDO0 internal powergood

Figure 7-12. PGOOD Pin Operation in Continuous Mode

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7.3.8.2 Warnings for Diagnosis (Interrupt)

7.3.8.2.1 Output Power Limit

The Buck regulators have programmable output peak current limits. The limits are individually programmed

for both regulators with the BUCKx_ILIM[2:0] bits in the BUCKx_CTRL_2 register. The current limit settings

of master and slave regulators used for the same output voltage rail must be identical. If the load current

is increased so that the current limit is triggered, then the regulator continues to regulate at the limit current

level (peak current regulation). The voltage may decrease if the load current is higher than the limit current.

If the current regulation continues for 20 µs, than the LP8732xx-Q1 device sets the BUCKx_ILIM_INT bit in

the INT_BUCK register and pulls the nINT pin low. The host processor can read the BUCKx_ILIM_STAT bits

in the BUCK_STAT register to see if the regulator is still in peak current regulation mode, and the interrupt

is cleared by writing 1 to the BUCKx_ILIM_INT bit. The current limit interrupt can be masked by setting the

BUCKx_ILIM_MASK bit in the BUCK_MASK register to 1. The Buck overload situation is shown in Figure 7-13.

Regulator disabled by

digital

New startup if

enable is valid

Voltage

VOUTx

350 mV

Resistive

pull-down

1 ms

Time

Current

ILIMx

Time

20 µs

0

1

0

INT_BUCK(BUCKx_ILIM_INT)

INT_BUCK(BUCKx_SC_INT)

BUCK_STAT(BUCKx_STAT)

nINT

1

0

1

Host clearing the interrupt by writing to flags

Figure 7-13. Buck Regulator Overload Situation

The LDO regulators also include current limit circuitry. If the load current is increased so that the current limit

is triggered, the regulator limits the output current to the threshold level. The voltage may decrease if the load

current is higher than the current limit. If the current regulation continues for 20 µs, the LP8732xx-Q1 device sets

the LDOx_ILIM_INT bit in the INT_LDO register and pulls the nINT pin low. The host processor can read the

LDOx_ILIM_STAT bits in the LDO_STAT register to see if the regulator is still in current regulation mode and the

interrupt is cleared by writing 1 to the LDOx_ILIM_INT bit. The current limit interrupt can be masked by setting

the LDOx_ILIM_MASK bit in the LDO_MASK register to 1. The LDO overload situation is shown in Figure 7-14.

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Regulator disabled by

digital

New startup if

enable is valid

Voltage

VOUTx

300 mV

Resistive

pull-down

1 ms

Time

Current

ILIMx

Time

20 µs

0

1

0

INT_LDO(LDOx_ILIM_INT)

INT_LDO(LDOx_SC_INT)

LDO_STAT(LDOx_STAT)

nINT

1

0

1

Host clearing the interrupt by writing to flags

Figure 7-14. LDO Regulator Overload Situation

7.3.8.2.2 Thermal Warning

The LP8732xx-Q1 device includes a protection feature against overtemperature by setting an interrupt for the

host processor. The threshold level of the thermal warning is selected with the TDIE_WARN_LEVEL bit in the

CONFIG register.

If the LP8732xx-Q1 device temperature increases above the thermal warning level, then the device sets the

TDIE_WARN_INT bit in the INT_TOP_1 register and pulls the nINT pin low. The status of the thermal warning

can be read from the TDIE_WARN_STAT bit in the TOP_STAT register, and the interrupt is cleared by writing 1

to the TDIE_WARN_INT bit. The thermal warning interrupt can be masked by setting the TDIE_WARN_MASK

bit in the TOP_MASK_1 register to 1.

7.3.8.3 Protection (Regulator Disable)

If the regulator is disabled, because of protection or fault (short-circuit protection, overload protection, thermal

shutdown, input overvoltage protection, or UVLO), then the output power FETs are set to high-impedance mode

and the output pulldown resistor is enabled (if enabled with the BUCKx_RDIS_EN bit in the BUCKx_CTRL_1

register and the LDOx_RDIS_EN bit in the LDOx_CTRL register). The turnoff time of the output voltage is

defined by the output capacitance, load current, and resistance of the integrated pull-down resistor. The pull-

down resistors are active as long as the VANA voltage is above approximately a 1.2-V level.

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7.3.8.3.1 Short-Circuit and Overload Protection

A short-circuit protection feature allows the LP8732xx-Q1 to protect itself and the external components against

a short circuit at the output or against overload during start-up. For the buck and LDO regulators, the fault

thresholds are about 350 mV (buck) and 300 mV (LDO). The protection is triggered and the regulator is disabled

if the output voltage is below the threshold level (1 ms) after the regulator is enabled.

In a similar way, the overload situation is protected during normal operation. If the output voltage falls below 0.35

V and 0.3 V and remains below the threshold level for 1 ms, then the regulator is disabled.

In Buck regulator short-circuit and overload situations, the BUCKx_SC_INT bit in the INT_BUCK register and the

INT_BUCKx bit in the INT_TOP_1 register are set to 1, the BUCKx_STAT bit in BUCK_STAT register is set to

0, and the nINT signal is pulled low. In LDO regulator short-circuit and overload situations, the LDOx_SC_INT

bit in the INT_LDO register and the INT_LDOx bit in the INT_TOP_1 register are set to 1, the LDOx_STAT bit in

the LDO_STAT register is set to 0, and the nINT signal is pulled low. The host processor clears the interrupt by

writing 1 to the BUCKx_SC_INT or to the LDOx_SC_INT bit. Upon clearing the interrupt, the regulator makes a

new start-up attempt if the regulator is in an enabled state.

7.3.8.3.2 Overvoltage Protection

The LP8732xx-Q1 device monitors the input voltage from the VANA pin in standby and active operation modes.

If the input voltage rises above the VANA_OVPvoltage level, the following occurs:

•

All regulators are disabled immediately (without switching ramp or shutdown delays).

The pull-down resistors discharge the output voltages, if the pull-down resistors are enabled (the

BUCKx_RDIS_EN = 1 in the BUCKx_CTRL_1 register and the LDOx_RDIS_EN = 1 in the LDOx_CTRL

register).

•

The GPOs are set to logic low level.

The nINT signal is pulled low.

The OVP_INT bit in the INT_TOP_1 register is set to 1.

The BUCKx_STAT bit in the BUCK_STAT register and the LDOx_STAT bit in the LDO_STAT register are set

to 0.

The host processor clears the interrupt by writing 1 to the OVP_INT bit. If the input voltage is above the

overvoltage detection level, then the interrupt is not cleared. The host can read the status of the overvoltage

from the OVP_STAT bit in the TOP_STAT register. The regulators cannot be enabled as long as the input

voltage is above the overvoltage detection level or while the overvoltage interrupt is pending.

7.3.8.3.3 Thermal Shutdown

The LP8732xx-Q1 has an overtemperature protection function that operates to protect itself from short-term

misuse and overload conditions. When the junction temperature exceeds around 150°C, the regulators are

disabled immediately (without switching ramp and shutdown delays), the TDIE_SD_INT bit in the INT_TOP_1

register is set to 1, the nINT signal is pulled low, and the device enters STANDBY. The nINT is cleared by writing

1 to the TDIE_SD_INT bit. If the temperature is above thermal shutdown level, then the interrupt is not cleared.

The host can read the status of the thermal shutdown from the TDIE_SD_STAT bit in the TOP_STAT register.

The regulators cannot be enabled as long as the junction temperature is above the thermal shutdown level or

while the thermal shutdown interrupt is pending.

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7.3.8.4 Fault (Power Down)

7.3.8.4.1 Undervoltage Lockout

When the input voltage falls below the VANA_UVLOat the VANA pin, the buck and LDO regulators are disabled

immediately (without switching ramp and shutdown delays), the output capacitor is discharged using the

pulldown resistor, and the LP8732xx-Q1 device enters SHUTDOWN. When the V_(VANA)voltage is above the

VANA_UVLOthreshold level, the device powers up to STANDBY state.

If the reset interrupt is unmasked by default (OTP bit for RESET_REG_MASK is 0 in TOP_MASK_2 register),

then the RESET_REG_INT interrupt bit in the INT_TOP_2 register indicates that the device has been in

SHUTDOWN. The host processor must clear the interrupt by writing 1 to the RESET_REG_INT bit. If the host

processor reads the RESET_REG_INT interrupt bit after detecting an nINT low signal, then it detects that the

input supply voltage has been below the VANA_UVLOlevel (or the host has requested reset with the SW_RESET

bit in the RESET register), and the registers are reset to default values.

7.3.9 Operation of the GPO Signals

The LP8732xx-Q1 device supports up to two general purpose output signals, GPO and GPO2. The GPO2 signal

is multiplexed with the CLKIN signal. The selection between the CLKIN and GPO2 pin function is set with the

CLKIN_PIN_SEL bit in the CONFIG register.

The GPO pins are configured with the following bits:

•

The GPOx_OD bit in The GPO_CTRL register defines the type of the output, either push-pull with V_(VANA)

level or open drain.

The logic level of the GPOx pin is set by the EN_GPOx bit in the GPO_CTRL register.

The control of the GPOs can be included to start-up and shutdown sequences. The GPO control for a sequence

with an EN pin is selected by the GPOx_EN_PIN_CTRL bit in the GPO_CTRL register. For start-up and

shutdown sequence control, see Section 7.3.6.

7.3.10 Digital Signal Filtering

The digital signals have a debounce filtering. The signal or supply is sampled with a clock signal and a counter.

This results as an accuracy of one clock period for the debounce window.

Table 7-5. Digital Signal Filtering

RISING EDGE

FALLING EDGE

LENGTH

EVENT

SIGNAL/SUPPLY

LENGTH

Enable/disable for BUCKx,

LDOx or GPOx

EN

3 µs⁽¹⁾

VANA UVLO

VANA

3 µs⁽¹⁾(VANA voltage rising)

Immediate (VANA voltage falling)

VANA overvoltage

Thermal warning

Thermal shutdown

Current limit

1 µs (VANA voltage rising)

20 µs (VANA voltage falling)

TDIE_WARN_INT

20 µs

TDIE_SD_INT

VOUTx_ILIM

FB_B0, FB_B1,

VOUT_LDO0, VOUT_LDO1

Overload

1 ms

6 µs

N/V

PGOOD pin and power-good

interrupt

PGOOD / FB_B0, FB_B1,

VOUT_LDO0, VOUT_LDO1

6 µs

(1) No glitch filtering, only synchronization.

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7.4 Device Functional Modes

7.4.1 Modes of Operation

SHUTDOWN: The V_(VANA)voltage is below VANA_UVLOthreshold level. All switch, reference, control, and bias

circuitry of the LP8732xx-Q1 device are turned off.

READ OTP: The main supply voltage V_(VANA)is above VANA_UVLOlevel. The regulators are disabled, and

the reference and bias circuitry of the LP8732xx-Q1 are enabled. The OTP bits are loaded to

registers.

STANDBY:

The main supply voltage V_(VANA)is above VANA_UVLOlevel. The regulators are disabled, and

the reference, control, and bias circuitry of the LP8732xx-Q1 are enabled. All registers can be

read or written by the host processor through the system serial interface. The regulators can be

enabled if needed.

ACTIVE:

The main supply voltage V_(VANA)is above VANA_UVLOlevel. At least one regulator is enabled. All

registers can be read or written by the host processor through the system serial interface.

The operating modes and transitions between the modes are shown in Figure 7-15.

SHUTDOWN

V(_VANA)< VANA_UVLO

V(_VANA)> VANA_UVLO

FROM ANY STATE

EXCEPT SHUTDOWN

READ

OTP

REG

RESET

STANDBY

I²C RESET

REGULATORS

ENABLED

REGULATORS

DISABLED

ACTIVE

Figure 7-15. Device Operation Modes

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7.5 Programming

7.5.1 I²C-Compatible Interface

The I²C-compatible synchronous serial interface provides access to the programmable functions and registers

on the device. This protocol uses a two-wire interface for bidirectional communications between the ICs

connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL).

Every device on the bus is assigned a unique address, and acts as either a master or a slave depending on

whether it generates or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor

placed on the line and remain HIGH even when the bus is idle. The LP8732xx-Q1 supports standard mode (100

kHz), fast mode (400 kHz), fast mode plus (1 MHz), and high-speed mode (3.4 MHz).

7.5.1.1 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the

state of the data line can only be changed when clock signal is LOW.

SCL

SDA

data

change

allowed

data

change

allowed

data

change

allowed

data

valid

data

valid

Figure 7-16. Data Validity Diagram

7.5.1.2 Start and Stop Conditions

The LP8732xx-Q1 is controlled through an I²C-compatible interface. START and STOP conditions classify the

beginning and end of the I²C session. A START condition is defined as SDA transitions from HIGH to LOW while

SCL is HIGH. A STOP condition is defined as an SDA transition from LOW to HIGH while SCL is HIGH. The I²C

master always generates the START and STOP conditions.

SDA

SCL

S

P

START

STOP

Condition

Figure 7-17. Start and Stop Sequences

The I²C bus is considered busy after a START condition and free after a STOP condition. During data

transmission, the I²C master can generate repeated START conditions. A START and a repeated START

condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock

signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 7-18 shows the

SDA and SCL signal timing for the I²C-compatible bus. See Section 6.6 for the timing values.

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t_BUF

SDA

t_HD;STA

t_rCL

t_fDA

t_rDA

t_SP

t_LOW

t_fCL

SCL

t_HD;STA

t_SU;STA

t_SU;STO

t_HIGH

t_HD;DAT

S

t_SU;DAT

S

RS

P

START

REPEATED

START

STOP

START

Figure 7-18. I²C-Compatible Timing

7.5.1.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each

byte of data has to be followed by an acknowledge bit. The acknowledge-related clock pulse is generated by

the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP8732xx-Q1

pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP8732xx-Q1 generates an

acknowledge after each byte has been received.

There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must

indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out

of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),

but the SDA line is not pulled down.

Note

If the V_(VANA)voltage is below the VANA_UVLOthreshold level during I²C communication, the LP8732xx-

Q1 device does not drive SDA line. The ACK signal and data transfer to the master is disabled at that

time.

After the START condition, the bus master sends a chip address. This address is seven bits long, followed by

an eighth bit, which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE, and a 1

indicates a READ. The second byte selects the register to which the data will be written. The third byte contains

data to write to the selected register.

ACK from slave

START MSB Chip Address LSB

W

ACK MSB Register Address LSB ACK

MSB Data LSB

ACK STOP

SCL

SDA

START

id = 0x60

W

ACK

address = 0x40

ACK

address 0x40 data

ACK STOP

Figure 7-19. Write Cycle (w = write; SDA = 0). Example Device Address = 0x60

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ACK from slave

ACK from slave REPEATED START

ACK from slave Data from slave NACK from master

START MSB Chip Address LSB

W

MSB Register Address LSB

RS

MSB Chip Address LSB

R

MSB Data LSB

STOP

SCL

SDA

START

ACK

NACK

STOP

id = 0x60

W

address = 0x3F

RS

id = 0x60

R

address 0x3F data

When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.

Figure 7-20. Read Cycle (r = read; SDA = 1). Example Device Address = 0x60

7.5.1.4 I²C-Compatible Chip Address

After the START condition, the I²C master sends the 7-bit address followed by an eighth bit, read or write (R/W).

R/W = 0 indicates a WRITE and R/W = 1 indicates a READ. The second byte following the device address

selects the register address to which the data is written. The third byte contains the data for the selected register.

MSB

LSB

1

Bit 7

1

Bit 6

0

Bit 5

0

Bit 4

0

Bit 3

0

Bit 2

0

Bit 1

R/W

Bit 0

I²C Slave Address (chip address)

Here in an example with device address of 1100000Bin = 60Hex.

Figure 7-21. Device Address Example

7.5.1.5 Auto-Increment Feature

The auto-increment feature allows writing several consecutive registers within one transmission. Every time an

8-bit word is sent to the LP8732xx-Q1, the internal address index counter is incremented by one and the next

register is written. Table 7-6 shows writing sequence to two consecutive registers. The auto-increment feature

does not work for read.

Table 7-6. Auto-Increment Example

MASTER

ACTION

DEVICE

ADDRESS = X

REGISTER

ADDRESS

START

WRITE

DATA

STOP

LP8732xx-Q1

ACK

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7.6 Register Maps

7.6.1 Register Descriptions

The LP8732xx-Q1 is controlled by a set of registers through the I²C-compatible interface. The device registers

addresses and abbreviations are listed in Table 7-7. A more detailed description is given in the Section 7.6.1.1 to

Section 7.6.1.39 sections.

Note

This register map describes the default values for bits that are not read from OTP memory. The

orderable code and the default register bit values are defined in part-number specific Technical

Reference Manuals.

Table 7-7. Summary of LP8732xx-Q1 Control Registers

Addr

0x00

Register

Read / Write D7

D6

D5

D4

D3

D2

D1

D0

DEV_REV

OTP_REV

R

DEVICE_ID[1:0]

Reserved - do not use

0x01

0x02

OTP_ID[7:0]

BUCK0_

CTRL_1

R/W

Reserved - do not use

BUCK0_FP BUCK0_FP BUCK0_RDI

WM_MP

BUCK0_

EN_PIN_CT

RL

BUCK0_EN

WM

S_EN

0x03

0x04

BUCK0_

CTRL_2

R/W

Reserved - do not use

BUCK0_ILIM[2:0]

BUCK0_SLEW_RATE[2:0]

BUCK1_

CTRL_1

BUCK1_FP BUCK1_RDI

WM S_EN

BUCK1_

EN_PIN_CT

RL

BUCK1_EN

0x05

0x06

0x07

0x08

BUCK1_

CTRL_2

R/W

Reserved - do not use

BUCK1_ILIM[2:0]

BUCK1_SLEW_RATE[2:0]

BUCK0_

VOUT

BUCK0_VSET[7:0]

BUCK1_VSET[7:0]

BUCK1_

VOUT

LDO0_

CTRL

Reserved - do not use

LDO0_RDIS

LDO0_

EN_PIN_CT

RL

LDO0_EN

_EN

0x09

LDO1_

CTRL

R/W

LDO1_RDIS

_EN

LDO1_

EN_PIN_CT

RL

LDO1_EN

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

LDO0_

VOUT

R/W

Reserved - do not use

LDO0_VSET[4:0]

LDO1_

VOUT

Reserved - do not use

LDO1_VSET[4:0]

BUCK0_

DELAY

BUCK0_SHUTDOWN_DELAY[3:0]

BUCK1_SHUTDOWN_DELAY[3:0]

LDO0_SHUTDOWN_DELAY[3:0]

LDO1_SHUTDOWN_DELAY[3:0]

GPO_SHUTDOWN_DELAY[3:0]

GPO2_SHUTDOWN_DELAY[3:0]

BUCK0_STARTUP_DELAY[3:0]

BUCK1_STARTUP_DELAY[3:0]

LDO0_STARTUP_DELAY[3:0]

LDO1_STARTUP_DELAY[3:0]

GPO_STARTUP_DELAY[3:0]

GPO2_STARTUP_DELAY[3:0]

BUCK1_

DELAY

LDO0_

DELAY

LDO1_

DELAY

GPO_

DELAY

GPO2_

DELAY

GPO_

CTRL

R/W

Reserved -

do not use

GPO2_OD

GPO2_

EN_PIN_CT

RL

GPO2_EN

Reserved -

do not use

GPO_OD

EN_PD

GPO_

EN_PIN_CT

RL

GPO_EN

0x13

0x14

CONFIG

Reserved - STARTUP_D SHUTDOW CLKIN_PIN_ CLKIN_PD

TDIE

_WARN

_LEVEL

EN_

SPREAD

_SPEC

do not use

ELAY_SEL N_DELAY_S

EL

SEL

PLL_CTRL

Reserved -

do not use

EN_PLL

Reserved -

do not use

EXT_CLK_FREQ[4:0]

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Table 7-7. Summary of LP8732xx-Q1 Control Registers (continued)

Addr

0x15

Register

Read / Write D7

D6

D5

D4

D3

D2

D1

PGOOD_CT

RL_1

R/W

PGOOD_PO PGOOD_OD PGOOD_WI PGOOD_WI EN_PGOOD EN_PGOOD EN_PGOOD EN_PGOOD

L

NDOW_LDO NDOW_BUC

K

_LDO1

_LDO0

_BUCK1

_BUCK0

0x16

PGOOD_CT

RL_2

R/W

Reserved - do not use

EN_PGOOD PG_FAULT_ PGOOD_M

_TWARN

GATES_PG

OOD

ODE

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

PG_FAULT

RESET

R

Reserved - do not use

PG_FAULT_ PG_FAULT_ PG_FAULT_ PG_FAULT_

LDO1

LDO0

BUCK1

BUCK0

R/W

R

Reserved - do not use

SW_

RESET

INT_TOP_1

INT_TOP_2

INT_BUCK

INT_LDO

PGOOD_

INT

INT_

LDO

INT_

BUCK

SYNC_

CLK_INT

TDIE_SD_IN

T

TDIE_

WARN_INT

OVP_INT

I_MEAS_

INT

Reserved - do not use

RESET_

REG_INT

Reserved -

do not use

BUCK1_

PG_INT

BUCK1_

SC_INT

BUCK1_

ILIM_INT

Reserved -

do not use

BUCK0_

PG_INT

BUCK0_

SC_INT

BUCK0_

ILIM_INT

Reserved -

do not use

LDO1_

ILIM_INT

Reserved -

do not use

LDO0_

PG_INT

LDO0_

SC_INT

LDO0_

ILIM_INT

PG_INT

SC_INT

TOP_

STAT

PGOOD_ST

AT

Reserved - do not use

SYNC_CLK

_STAT

TDIE_SD

_STAT

TDIE_

WARN_

STAT

OVP_

STAT

Reserved -

do not use

0x1E

0x1F

0x20

0x21

0x22

BUCK_STAT

LDO_STAT

R

BUCK1_

STAT

BUCK1_

PG_STAT

Reserved -

do not use

BUCK1_

ILIM_STAT

BUCK0_

STAT

BUCK0_

PG_STAT

Reserved -

do not use

BUCK0_

ILIM_STAT

R

LDO1_

STAT

LDO1_

PG_STAT

Reserved -

do not use

LDO1_

ILIM_STAT

LDO0_

STAT

LDO0_

PG_STAT

Reserved -

do not use

LDO0_

ILIM_STAT

TOP_

MASK_1

R/W

PGOOD_

INT_MASK

Reserved - do not use

SYNC_CLK Reserved - TDIE_WARN Reserved -

_MASK do not use _MASK do not use

I_MEAS_

MASK

TOP_

MASK_2

Reserved - do not use

RESET_

REG_MASK

BUCK_MAS

K

BUCK1_PG BUCK1_PG Reserved -

F_MASK R_MASK do not use

BUCK1_

ILIM_

BUCK0_PG BUCK0_PG Reserved -

F_MASK R_MASK do not use

BUCK0_

ILIM_

MASK

0x23

0x24

LDO_MASK

R/W

LDO1_PGF_ LDO1_PGR Reserved -

LDO1_

ILIM_

MASK

LDO0_PGF_ LDO0_PGR Reserved -

MASK _MASK do not use

LDO0_

ILIM_

MASK

_MASK

do not use

SEL_I_

LOAD

Reserved - do not use

LOAD_CUR

RENT_

BUCK_SEL

ECT

0x25

0x26

I_LOAD_2

I_LOAD_1

R

Reserved - do not use

BUCK_LOA

D_CURREN

T[8]

BUCK_LOAD_CURRENT[7:0]

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7.6.1.1 DEV_REV

DEV_REV is shown in Table 7-9, Address: 0x00

Table 7-8. DEV_REV Register

D7

D6

D5

D4

D3

D2

D1

D0

DEVICE_ID[1:0]

Reserved - do not use

Table 7-9. DEV_REV Register Field Descriptions

Bits

7:6

Field

Type

R

Default

Description

DEVICE_ID[1:0]

X

Device specific ID code.

5:0

Reserved - do not

use

R

00 0010

7.6.1.2 OTP_REV

OTP_REV is shown in Table 7-11, Address: 0x01

Table 7-10. OTP_REV Register

D7

D6

D5

D4

D3

D2

D1

D0

OTP_ID[7:0]

Table 7-11. OTP_REV Register Field Descriptions

Bits

Field

Type

Default

Description

7:0

OTP_ID[7:0]

R

X

Identification Code of the OTP EPROM Version.

7.6.1.3 BUCK0_CTRL_1

BUCK0_CTRL_1 is shown in Table 7-13, Address: 0x02

Table 7-12. BUCK0_CTRL_1 Register

D7

D6

D5

D4

D3

D2

D1

D0

Reserved - do not use

BUCK0_FPWM BUCK0_FPWM BUCK0_RDIS_ BUCK0_EN_PI

_MP EN N_CTRL

BUCK0_EN

Table 7-13. BUCK0_CTRL_1 Register Field Descriptions

Bits

Field

Type

Default

Description

7:5

Reserved - do not

use

R/W

000

4

BUCK0_FPWM

_MP

R/W

X

Forces the Buck0 regulator to always operate in the multi-phase and forced PWM

operation mode:

0 - Automatic phase adding and shedding.

1 - Forced to multi-phase operation, 2 phases in the 2-phase configuration.

3

2

1

0

BUCK0_FPWM

R/W

X

1

Buck0 mode selection:

0 - Automatic transitions between the PFM and PWM modes (AUTO mode).

1 - Forced to the PWM operation.

BUCK0_RDIS_EN

Enable output discharge resistor (R_{DIS_Bx}) when the Buck0 is disabled:

0 - Discharge resistor disabled.

1 - Discharge resistor enabled.

BUCK0_EN_PIN

_CTRL

X

Enable control for the Buck0:

0 - only the BUCK0_EN bit controls the Buck0.

1 - BUCK0_EN bit and the EN pin control the Buck0.

BUCK0_EN

Enable the Buck0 regulator:

0 - Buck0 regulator is disabled.

1 - Buck0 regulator is enabled.

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7.6.1.4 BUCK0_CTRL_2

BUCK0_CTRL_2 is shown in Table 7-15, Address: 0x03

Table 7-14. BUCK0_CTRL_2 Register

D7

D6

D5

D4

D3

D2

D1

D0

Reserved - do not use

BUCK0_ILIM[2:0]

BUCK0_SLEW_RATE[2:0]

Table 7-15. BUCK0_CTRL_2 Register Field Descriptions

Bits

Field

Type

Default

Description

7:6

Reserved - do not

use

R/W

00

5:3

BUCK0_ILIM[2:0]

R/W

X

Sets the switch current limit of Buck0. Can be programmed at any time during

operation:

0x0 - 1.5 A

0x1 - 2.0 A

0x2 - 2.5 A

0x3 - 3.0 A

0x4 - Reserved - do not use.

0x5 - Reserved

0x6 - Reserved - do not use.

0x7 - Reserved - do not use.

2:0 BUCK0_SLEW_RA

TE[2:0]

R/W

X

Sets the output voltage slew rate for Buck0 regulator (rising and falling edges):

0x0 - Reserved - do not use.

0x1 - Reserved - do not use.

0x2 - 10 mV/µs

0x3 - 7.5 mV/µs

0x4 - 3.8 mV/µs

0x5 - 1.9 mV/µs

0x6 - 0.94 mV/µs

0x7 - 0.47 mV/µs

7.6.1.5 BUCK1_CTRL_1

BUCK1_CTRL_1 is shown in Table 7-17, Address: 0x04

Table 7-16. BUCK1_CTRL_1 Register

D7

D6

D5

D4

D3

D2

D1

D0

Reserved - do not use

BUCK1_FPWM BUCK1_RDIS_ BUCK1_EN_PI

EN N_CTRL

BUCK1_EN

Table 7-17. BUCK1_CTRL_1 Register Field Descriptions

Bits

Field

Type

Default

Description

7:4

Reserved - do not

use

R/W

0000

3

2

1

0

BUCK1_FPWM

R/W

X

1

Buck1 mode selection:

0 - Automatic transitions between the PFM and PWM modes (AUTO mode).

1 - Forced to PWM operation.

BUCK1_RDIS_EN

Enable output discharge resistor (R_{DIS_Bx}) when the Buck1 is disabled:

0 - Discharge resistor is disabled.

1 - Discharge resistor is enabled.

BUCK1_EN_PIN

_CTRL

X

Enable control for the Buck1:

0 - only the BUCK1_EN bit controls the Buck1

1 - BUCK1_EN bit and the EN pin control the Buck1.

BUCK1_EN

Enable the Buck1 regulator:

0 - Buck1 regulator is disabled.

1 - Buck1 regulator is enabled.

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7.6.1.6 BUCK1_CTRL_2

BUCK1_CTRL_2 is shown in Table 7-19, Address: 0x05

Table 7-18. BUCK1_CTRL_2 Register

D7

D6

D5

D4

D3

D2

D1

D0

Reserved - do not use

BUCK1_ILIM[2:0]

BUCK1_SLEW_RATE[2:0]

Table 7-19. BUCK1_CTRL_2 Register Field Descriptions

Bits

Field

Type

Default

Description

7:6

Reserved - do not

use

R/W

00

5:3

BUCK1_ILIM[2:0]

R/W

X

Sets the switch current limit of the Buck1. Can be programmed at any time during

operation:

0x0 - 1.5 A

0x1 - 2.0 A

0x2 - 2.5 A

0x3 - 3.0 A

0x4 - Reserved - do not use.

0x5 - Reserved - do not use.

0x6 - Reserved - do not use.

0x7 - Reserved - do not use.

2:0 BUCK1_SLEW_RA

TE[2:0]

R/W

X

Sets the output voltage slew rate for the Buck1 regulator (rising and falling edges):

0x0 - Reserved - do not use.

0x1 - Reserved - do not use.

0x2 - 10 mV/µs

0x3 - 7.5 mV/µs

0x4 - 3.8 mV/µs

0x5 - 1.9 mV/µs

0x6 - 0.94 mV/µs

0x7 - 0.47 mV/µs

7.6.1.7 BUCK0_VOUT

BUCK0_VOUT is shown in Table 7-21, Address: 0x06

Table 7-20. BUCK0_VOUT Register

D7

D6

D5

D4

D3

D2

D1

D0

BUCK0_VSET[7:0]

Table 7-21. BUCK0_VOUT Register Field Descriptions

Bits

Field

Type

Default

Description

7:0 BUCK0_VSET[7:0]

R/W

X

Sets the output voltage of the Buck0 regulator:

Reserved; do not use.

0x00 ... 0x13

0.7 V - 0.73 V, 10 mV steps

0x14 - 0.7V

...

0x17 - 0.73 V

0.73 V - 1.4 V, 5 mV steps

0x18 - 0.735 V

...

0x9D - 1.4 V

1.4 V - 3.36 V, 20 mV steps

0x9E - 1.42 V

...

0xFF - 3.36 V

7.6.1.8 BUCK1_VOUT

BUCK1_VOUT is shown in Table 7-23, Address: 0x07

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Table 7-22. BUCK1_VOUT Register

D7

D6

D5

D4

D3

D2

D1

D0

BUCK1_VSET[7:0]

Table 7-23. BUCK1_VOUT Register Field Descriptions

Bits

Field

Type

Default

Description

7:0 BUCK1_VSET[7:0]

R/W

X

Sets the output voltage of the Buck0 regulator:

Reserved; do not use.

0x00 ... 0x13

0.7 V - 0.73 V, 10 mV steps

0x14 - 0.7V

...

0x17 - 0.73 V

0.73 V - 1.4 V, 5 mV steps

0x18 - 0.735 V

...

0x9D - 1.4 V

1.4 V - 3.36 V, 20 mV steps

0x9E - 1.42 V

...

0xFF - 3.36 V

7.6.1.9 LDO0_CTRL

LDO0_CTRL is shown in Table 7-25, Address: 0x08

Table 7-24. LDO0_CTRL Register

D7

D6

D5

D4

D3

D2

D1

D0

Reserved - do not use

LDO0_RDIS_E LDO0_EN_PIN

_CTRL

LDO0_EN

N

Table 7-25. LDO0_CTRL Register Field Descriptions

Bits

Field

Type

Default

Description

7:3

Reserved - do not

use

R/W

0 0000

2

1

0

LDO0_RDIS_EN

R/W

1

X

Enable output discharge resistor (R_{DIS_LDOx}) when the LDO0 is disabled:

0 - Discharge resistor is disabled.

1 - Discharge resistor is enabled.

LDO0_EN_PIN

_CTRL

Enable control for the LDO0:

0 - only the LDO0_EN bit controls the LDO0.

1 - LDO0_EN bit and the EN pin control the LDO0.

LDO0_EN

Enable the LDO0 regulator:

0 - LDO0 regulator is disabled.

1 - LDO0 regulator is enabled.

7.6.1.10 LDO1_CTRL

LDO1_CTRL is shown in Table 7-27, Address: 0x09

Table 7-26. LDO1_CTRL Register

D7

D6

D5

D4

D3

D2

D1

D0

Reserved - do not use

LDO1_RDIS_E LDO1_EN_PIN

_CTRL

LDO1_EN

N

Table 7-27. LDO1_CTRL Register Field Descriptions

Bits

Field

Type

Default

Description

7:3

Reserved - do not

use

R/W

0 0000

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Table 7-27. LDO1_CTRL Register Field Descriptions (continued)

Field

Type

Default

Description

2

1

0

LDO1_RDIS_EN

R/W

1

Enable output discharge resistor (R_{DIS_LDOx}) when the LDO1 is disabled:

0 - Discharge resistor is disabled.

1 - Discharge resistor is enabled.

LDO1_EN_PIN

_CTRL

R/W

X

Enable control for the LDO1:

0 - only the LDO1_EN bit controls the LDO1.

1 - LDO1_EN bit and the EN pin control the LDO1.

LDO1_EN

Enable the LDO1 regulator:

0 - LDO1 regulator is disabled.

1 - LDO1 regulator is enabled.

7.6.1.11 LDO0_VOUT

LDO0_VOUT is shown in Table 7-29, Address: 0x0A

Table 7-28. LDO0_VOUT Register

D7

D6

D5

D4

D3

D2

D1

D0

Reserved - do not use

LDO0_VSET[4:0]

Table 7-29. LDO0_VOUT Register Field Descriptions

Bits

Field

Type

Default

Description

7:5

Reserved - do not

use

R/W

000

4:0

LDO0_VSET[4:0]

R/W

X

Sets the output voltage of the LDO0 regulator:

0.8 V - 3.3 V, 100 mV steps

0x00 - 0.8V

...

0x19 - 3.3 V

Reserved; do not use.

0x1A ... 0x1F

7.6.1.12 LDO1_VOUT

LDO1_VOUT is shown in Table 7-31, Address: 0x0B

Table 7-30. LDO1_VOUT Register

D7

D6

D5

D4

D3

D2

Reserved - do not use

LDO1_VSET[4:0]

Table 7-31. LDO1_VOUT Register Field Descriptions

Bits

Field

Type

Default

Description

7:5

Reserved - do not

use

R/W

000

4:0

LDO1_VSET[4:0]

R/W

X

Sets the output voltage of the LDO1 regulator:

0.8 V - 3.3 V, 100 mV steps

0x00 - 0.8V

...

0x19 - 3.3 V

Reserved; do not use.

0x1A ... 0x1F

7.6.1.13 BUCK0_DELAY

BUCK0_DELAY is shown in Table 7-33, Address: 0x0C

Table 7-32. BUCK0_DELAY Register

D7

D6

D5

D4

D3

D2

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BUCK0_SHUTDOWN_DELAY[3:0]

BUCK0_STARTUP_DELAY[3:0]

Table 7-33. BUCK0_DELAY Register Field Descriptions

Bits

Field

Type

Default

Description

7:4

BUCK0_

SHUTDOWN_

DELAY[3:0]

R/W

X

Shutdown delay of the Buck0 from the EN signal's falling edge:

0x0 - 0 ms

0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in the CONFIG register.)

...

0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in the CONFIG register.)

3:0

BUCK0_

STARTUP_

DELAY[3:0]

R/W

X

Startup delay of the Buck0 from the EN signal's rising edge:

0x0 - 0 ms

0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in the CONFIG register.)

...

0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in the CONFIG register.)

7.6.1.14 BUCK1_DELAY

BUCK1_DELAY is shown in Table 7-35, Address: 0x0D

Table 7-34. BUCK1_DELAY Register

D7

D6

D5

D4

D3

D2

D1

D0

BUCK1_SHUTDOWN_DELAY[3:0]

BUCK1_STARTUP_DELAY[3:0]

Table 7-35. BUCK1_DELAY Register Field Descriptions

Bits

Field

Type

Default

Description

7:4

BUCK1_

SHUTDOWN_

DELAY[3:0]

R/W

X

Shutdown delay of the Buck1 from the EN signal's falling edge:

0x0 - 0 ms

0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in the CONFIG register.)

...

0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in the CONFIG register.)

3:0

BUCK1_

STARTUP_

DELAY[3:0]

R/W

X

Startup delay of the Buck1 from the EN signal's rising edge:

0x0 - 0 ms

0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in the CONFIG register.)

...

0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in the CONFIG register.)

7.6.1.15 LDO0_DELAY

LDO0_DELAY is shown in Table 7-37, Address: 0x0E

Table 7-36. LDO0_DELAY Register

D7

D6

D5

D4

D3

D2

D1

D0

LDO0_SHUTDOWN_DELAY[3:0]

LDO0_STARTUP_DELAY[3:0]

Table 7-37. LDO0_DELAY Register Field Descriptions

Bits

Field

Type

Default

Description

7:4

LDO0_

R/W

X

Shutdown delay of the LDO0 from the EN signal's falling edge:

SHUTDOWN_

DELAY[3:0]

0x0 - 0 ms

0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in the CONFIG register.)

...

0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in the CONFIG register.)

3:0

LDO0_

R/W

X

Startup delay of the LDO0 from the EN signal's rising edge:

STARTUP_

DELAY[3:0]

0x0 - 0 ms

0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in the CONFIG register.)

...

0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in the CONFIG register.)

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7.6.1.16 LDO1_DELAY

LDO1_DELAY is shown in Table 7-39, Address: 0x0F

Table 7-38. LDO1_DELAY Register

D7

D6

D5

D4

D3

D2

D1

D0

LDO1_SHUTDOWN_DELAY[3:0]

LDO1_STARTUP_DELAY[3:0]

Table 7-39. LDO1_DELAY Register Field Descriptions

Bits

Field

Type

Default

Description

7:4

LDO1_

R/W

X

Shutdown delay of the LDO1 from the EN signal's falling edge:

SHUTDOWN_

DELAY[3:0]

0x0 - 0 ms

0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in the CONFIG register.)

...

0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in the CONFIG register.)

3:0

LDO1_

R/W

X

Startup delay of the LDO1 from the EN signal's rising edge:

STARTUP_

DELAY[3:0]

0x0 - 0 ms

0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in the CONFIG register.)

...

0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in the CONFIG register.)

7.6.1.17 GPO_DELAY

GPO_DELAY is shown in Table 7-41, Address: 0x10

Table 7-40. GPO_DELAY Register

D7

D6

D5

D4

D3

D2

D1

D0

GPO_SHUTDOWN_DELAY[3:0]

GPO_STARTUP_DELAY[3:0]

Table 7-41. GPO_DELAY Register Field Descriptions

Bits

Field

Type

Default

Description

7:4

GPO_

R/W

X

Delay for the GPO falling edge from the EN signal's falling edge:

SHUTDOWN_

DELAY[3:0]

0x0 - 0 ms

0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in the CONFIG register)

...

0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in the CONFIG register)

3:0

GPO_

R/W

X

Delay for the GPO rising edge from the EN signal's rising edge:

STARTUP_

DELAY[3:0]

0x0 - 0 ms

0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in the CONFIG register.)

...

0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in the CONFIG register.)

7.6.1.18 GPO2_DELAY

GPO2_DELAY is shown in Table 7-43, Address: 0x11

Table 7-42. GPO2_DELAY Register

D7

D6

D5

D4

D3

D2

D1

D0

GPO2_SHUTDOWN_DELAY[3:0]

GPO2_STARTUP_DELAY[3:0]

Table 7-43. GPO2_DELAY Register Field Descriptions

Bits

Field

Type

Default

Description

7:4

GPO2_

R/W

X

Delay for the GPO2 falling edge from the EN signal's falling edge:

SHUTDOWN_

DELAY[3:0]

0x0 - 0 ms

0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in the CONFIG register.)

...

0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in the CONFIG register.)

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Table 7-43. GPO2_DELAY Register Field Descriptions (continued)

Bits

Field

Type

Default

Description

3:0

GPO2_

R/W

X

Delay for the GPO2 rising edge from the EN signal's rising edge:

STARTUP_

DELAY[3:0]

0x0 - 0 ms

0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in the CONFIG register.)

...

0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in the CONFIG register.)

7.6.1.19 GPO_CTRL

GPO_CTRL is shown in Table 7-45, Address: 0x12

Table 7-44. GPO_CTRL Register

D7

D6

D5

D4

D3

D2

D1

D0

Reserved - do

not use

GPO2_OD

GPO2_EN_PIN

_CTRL

GPO2_EN

Reserved - do

not use

GPO_OD

GPO_EN_PIN_

CTRL

GPO_EN

Table 7-45. GPO_CTRL Register Field Descriptions

Bits

Field

Reserved - do not

Type

Default

Description

7

R

0

use

6

5

4

GP02_OD

R/W

X

GPO2 signal type when configured as the General Purpose Output (CLKIN pin):

0 - Push-pull output (VANA level)

1 - Open-drain output

GPO2_EN_PIN_CT

RL

Control for the GPO2:

0 - Only the GPO2_EN bit controls the GPO2

1 - GPO2_EN bit and the EN pin control the GPO2.

GPO2_EN

Output level of the GPO2 signal (when configured as the General Purpose Output):

0 - Logic low level

1 - Logic high level

3

2

Reserved - do not

use

R

0

GPO_OD

R/W

X

GPO signal type:

0 - Push-pull output (VANA level)

1 - Open-drain output

1

0

GPO_EN_PIN_CTR

L

R/W

X

Control for the GPO:

0 - Only the GPO_EN bit controls the GPO

1 - GPO_EN bit and the EN pin control the GPO.

GPO_EN

Output level of the GPO signal:

0 - Logic low level

1 - Logic high level

7.6.1.20 CONFIG

CONFIG is shown in Table 7-47, Address: 0x13

Table 7-46. CONFIG Register

D7

D6

D5

D4

D3

D2

D1

D0

Reserved - do STARTUP_DEL SHUTDOWN_D CLKIN_PIN_SE

not use AY_SEL ELAY_SEL

CLKIN_PD

EN2_PD

TDIE_WARN_

LEVEL

EN_SPREAD

_SPEC

L

Table 7-47. CONFIG Register Field Descriptions

Bits

Field

Type

Default

Description

7

Reserved - do not

use

R/W

0

6

STARTUP_DELAY_

SEL

R/W

X

Startup delay range from the EN signals:

0 - 0 ms - 7.5 ms with 0.5 ms steps

1 - 0 ms - 15 ms with 1 ms steps

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Table 7-47. CONFIG Register Field Descriptions (continued)

Field

Type

Default

Description

5

4

3

SHUTDOWN_DELA

Y_SEL

R/W

X

Shutdown delay range from the EN signals:

0 - 0 ms - 7.5 ms with 0.5 ms steps

1 - 0 ms - 15 ms with 1 ms steps

CLKIN_PIN_SEL

CLKIN_PD

R/W

X

CLKIN pin function:

0 - GPO2

1 - CLKIN

Selects the pull down resistor on the CLKIN input pin (valid also when selected as

GPO2):

0 - Pull-down resistor is disabled.

1 - Pull-down resistor is enabled.

2

1

0

EN_PD

R/W

X

Selects the pull down resistor on the EN input pin.

0 - Pull-down resistor is disabled.

1 - Pull-down resistor is enabled.

TDIE_WARN_

LEVEL

Thermal warning threshold level:

0 - 125°C

1 - 137°C

EN_SPREAD

_SPEC

Enable spread spectrum feature:

0 - Disabled

1 - Enabled

7.6.1.21 PLL_CTRL

PLL_CTRL is shown in Table 7-49, Address: 0x14

Table 7-48. PLL_CTRL Register

D7

D6

D5

D4

D3

D2

D1

D0

Reserved - do

not use

EN_PLL

Reserved - do

not use

EXT_CLK_FREQ[4:0]

Table 7-49. PLL_CTRL Register Field Descriptions

Bits

Field

Reserved - do not

Type

Default

Description

7

R/W

0

use

6

EN_PLL

R/W

X

Selection of the external clock and PLL operation:

0 - Forced to the internal RC oscillator. The PLL is disabled.

1 - PLL is enabled in the STANDBY and ACTIVE modes. Automatic external clock

use when available, and interrupt is generated if the external clock appears or

disappears.

5

Reserved - do not

use

R/W

0

This bit must be set to '''0 .''

4:0 EXT_CLK_FREQ[4:

0]

X

Frequency of the external clock (CLKIN):

0x00 - 1 MHz

0x01 - 2 MHz

0x02 - 3 MHz

...

0x16 - 23 MHz

0x17 - 24 MHz

0x18...0x1F - Reserved - do not use

See electrical specification for the input clock frequency tolerance.

7.6.1.22 PGOOD_CTRL_1

PGOOD_CTRL_1 is shown in Table 7-51, Address: 0x15

Table 7-50. PGOOD_CTRL_1 Register

D7

D6

D5

D4

D3

D2

D1

D0

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PGOOD_POL

PGOOD_OD

PGOOD_

EN_PGOOD_L EN_PGOOD_L EN_PGOOD_B EN_PGOOD_B

WINDOW_LDO WINDOW_BUC

K

DO1

DO0

UCK1

UCK0

Table 7-51. PGOOD_CTRL_1 Register Field Descriptions

Bits

Field

Type

Default

Description

7

PGOOD_POL

R/W

X

PGOOD signal polarity:

0 - PGOOD signal high when the monitored outputs are valid.

1 - PGOOD signal low when the monitored outputs are valid.

6

5

4

3

2

1

0

PGOOD_OD

X

PGOOD signal type:

0 - Push-pull output (VANA level)

1 - Open-drain output

PGOOD_

WINDOW_LDO

LDO Output voltage monitoring method for the PGOOD signal:

0 - Only undervoltage monitoring

1 - Overvoltage and undervoltage monitoring

PGOOD_

WINDOW_BUCK

Buck Output voltage monitoring method for the PGOOD signal:

0 - Only undervoltage monitoring

1 - Overvoltage and undervoltage monitoring

EN_PGOOD_LDO1

EN_PGOOD_LDO0

PGOOD signal source control from LDO1:

0 - LDO1 is not monitored.

1 - LDO1 Power-Good threshold voltage is monitored.

PGOOD signal source control from theLDO0:

0 - LDO0 is not monitored.

1 - LDO0 Power-Good threshold voltage is monitored.

EN_PGOOD_BUCK

1

PGOOD signal source control from the Buck1:

0 - Buck1 is not monitored.

1 - Buck1 Power-Good threshold voltage is monitored.

EN_PGOOD_BUCK

0

PGOOD signal source control from the Buck0:

0 - Buck0 is not monitored.

1 - Buck0 Power-Good threshold voltage is monitored.

7.6.1.23 PGOOD_CTRL_2

PGOOD_CTRL_2 is shown in Table 7-53, Address: 0x16

Table 7-52. PGOOD_CTRL_2 Register

D7

D6

D5

D4

D3

D2

D1

D0

Reserved - do not use

EN_PGOOD_T PG_FAULT_GA PGOOD_MOD

WARN

TES_PGOOD

E

Table 7-53. PGOOD_CTRL_2 Register Field Descriptions

Bits

Field

Type

Default

Description

7:3

Reserved - do not

use

R/W

0 0000

2

1

EN_PGOOD_TWA

RN

R/W

X

Thermal warning control for the PGOOD signal:

0 - Thermal warning is not monitored.

1 - PGOOD inactive if the thermal warning flag is active.

PG_FAULT_GATES

_PGOOD

Type of operation for the PGOOD signal:

0 - Indicates live status of monitored voltage outputs.

1 - Indicates status of the PG_FAULT register, inactive when at least one

PG_FAULT_x bit is inactive.

0

PGOOD_MODE

R/W

X

Operating mode for the PGOOD signal:

0 - Gated mode

1 - Continuous mode

7.6.1.24 PG_FAULT

PG_FAULT is shown in Table 7-55, Address: 0x17

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Table 7-54. PG_FAULT Register

D7

D6

D5

D4

D3

D2

D1

D0

Reserved - do not use

PG_FAULT_LD PG_FAULT_LD PG_FAULT_BU PG_FAULT_BU

O1 O0 CK1 CK0

Table 7-55. PG_FAULT Register Field Descriptions

Bits

Field

Type

Default

Description

7:4

Reserved - do not

use

R/W

0000

3

PG_FAULT_LDO1

PG_FAULT_LDO0

PG_FAULT_BUCK1

PG_FAULT_BUCK0

R/W

0

Source for the PGOOD inactive signal:

0 - LDO1 has not set the PGOOD signal inactive.

1 - LDO1 is selected for the PGOOD signal and it has set the PGOOD signal inactive.

This bit can be cleared by writing '1' to this bit when the LDO1 output is valid.

2

1

0

Source for PGOOD inactive signal:

0 - LDO0 has not set the PGOOD signal inactive.

1 - LDO0 is selected for the PGOOD signal and it has set the PGOOD signal inactive.

This bit can be cleared by writing '1' to this bit when the LDO0 output is valid.

Source for PGOOD inactive signal:

0 - Buck1 has not set PGOOD signal inactive.

1 - Buck1 is selected for the PGOOD signal and it has set the PGOOD signal inactive.

This bit can be cleared by writing '1' to this bit when the Buck1 output is valid.

Source for PGOOD inactive signal:

0 - Buck0 has not set PGOOD signal inactive.

1 - Buck0 is selected for the PGOOD signal and it has set the PGOOD signal inactive.

This bit can be cleared by writing '1' to this bit when the Buck0 output is valid.

7.6.1.25 RESET

RESET is shown in Table 7-57, Address: 0x18

Table 7-56. RESET Register

D7

D6

D5

D4

D3

D2

D1

D0

Reserved - do not use

SW_RESET

Table 7-57. RESET Register Field Descriptions

Bits

Field

Type

Default

Description

7:1

Reserved - do not

use

R/W

000 0000

0

SW_RESET

R/W

0

Software commanded reset. When written to 1, the registers will be reset to the

default values, the OTP memory is read, and the I²C interface is reset.

The bit is automatically cleared.

7.6.1.26 INT_TOP_1

INT_TOP_1 is shown in Table 7-59, Address: 0x19

Table 7-58. INT_TOP_1 Register

D7

D6

D5

D4

D3

D2

D1

D0

PGOOD_INT

LDO_INT

BUCK_INT

SYNC_CLK_IN TDIE_SD_INT TDIE_WARN_I

NT

OVP_INT

I_MEAS_INT

T

Table 7-59. INT_TOP_1 Register Field Descriptions

Bits

Field

PGOOD_INT

Type

Default

Description

7

R/W

0

Latched status bit indicating that the PGOOD pin has changed from active to inactive.

Write 1 to clear interrupt.

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Table 7-59. INT_TOP_1 Register Field Descriptions (continued)

Bits

Field

Type

Default

Description

6

LDO_INT

R

0

Interrupt indicating that the LDO1 and LDO0 have a pending interrupt. The reason for

the interrupt is indicated in the INT_LDO register.

This bit is cleared automatically when the INT_LDO register is cleared to 0x00.

5

BUCK_INT

R

0

Interrupt indicating that the Buck1 and Buck0 have a pending interrupt. The reason

for the interrupt is indicated in the INT_BUCK register.

This bit is cleared automatically when INT_BUCK register is cleared to 0x00.

4

3

SYNC_CLK_INT

TDIE_SD_INT

R/W

0

Latched status bit indicating that the external clock has appeared or disappeared.

Write 1 to clear interrupt.

Latched status bit indicating that the die junction temperature has exceeded the

thermal shutdown level. The regulators have been disabled if they were enabled

and the GPO and GPO2 signals are driven low. The regulators cannot be enabled

if this bit is active. The actual status of the thermal shutdown is indicated by the

TDIE_SD_STAT bit in the TOP_STAT register.

Write 1 to clear interrupt.

2

1

TDIE_WARN_INT

OVP_INT

R/W

0

Latched status bit indicating that the die junction temperature has exceeded the

thermal warning level. The actual status of the thermal warning is indicated by the

TDIE_WARN_STAT bit in the TOP_STAT register.

Write 1 to clear interrupt.

Latched status bit indicating that the input voltage has exceeded the over-voltage

detection level. The regulators have been disabled if they were enabled and the GPO

and GPO2 signals are driven low. The actual status of the over-voltage is indicated by

the OVP_STAT bit in the TOP_STAT register.

Write 1 to clear interrupt.

0

I_MEAS_INT

R/W

0

Latched status bit indicating that the load current measurement result is available in

the I_LOAD_1 and I_LOAD_2 registers.

Write 1 to clear interrupt.

7.6.1.27 INT_TOP_2

INT_TOP_2 is shown in Table 7-61, Address: 0x1A

Table 7-60. INT_TOP_2 Register

D7

D6

D5

D4

D3

D2

D1

D0

Reserved - do not use

RESET_REG_I

NT

Table 7-61. INT_TOP_2 Register Field Descriptions

Bits

Field

Type

Default

Description

7:1

Reserved - do not

use

R/W

000 0000

0

RESET_REG_INT

R/W

0

Latched status bit indicating that either VANA supply voltage has been below the

undervoltage threshold level or the host has requested a reset using the SW_RESET

bit in RESET register. The regulators have been disabled, the registers are reset to

the default values, and the normal startup procedure is done.

Write 1 to clear interrupt.

7.6.1.28 INT_BUCK

INT_BUCK is shown in Table 7-63, Address: 0x1B

Table 7-62. INT_BUCK Register

D7

D6

D5

D4

D3

D2

D1

D0

Reserved - do

not use

BUCK1_PG

_INT

BUCK1_SC

_INT

BUCK1_ILIM

_INT

Reserved - do

not use

BUCK0_PG

_INT

BUCK0_SC

_INT

BUCK0_ILIM

_INT

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Table 7-63. INT_BUCK Register Field Descriptions

Field

Type

Default

Description

7

6

5

Reserved - do not

use

R/W

0

BUCK1_PG_INT

R/W

0

Latched status bit indicating that Buck1 Power-Good event has been detected.

Write 1 to clear.

BUCK1_SC_INT

Latched status bit indicating that the Buck1 output voltage has been over 1 ms below

the short-circuit threshold level.

Write 1 to clear.

4

3

2

1

BUCK1_ILIM_INT

R/W

0

Latched status bit indicating that the Buck1 output current limit has been active.

Write 1 to clear.

Reserved - do not

use

BUCK0_PG_INT

Latched status bit indicating that the Buck0 Power-Good event has been detected.

Write 1 to clear.

BUCK0_SC_INT

Latched status bit indicating that the Buck0 output voltage has been over 1 ms below

the short-circuit threshold level.

Write 1 to clear.

0

BUCK0_ILIM_INT

R/W

0

Latched status bit indicating that the Buck0 output current limit has been active.

Write 1 to clear.

7.6.1.29 INT_LDO

INT_LDO is shown in Table 7-65, Address: 0x1C

Table 7-64. INT_LDO Register

D7

D6

D5

D4

D3

D2

D1

D0

Reserved - do

not use

LDO1_PG

_INT

LDO1_SC

_INT

LDO1_ILIM

_INT

Reserved - do

not use

LDO0_PG

_INT

LDO0_SC

_INT

LDO0_ILIM

_INT

Table 7-65. INT_LDO Register Field Descriptions

Bits

Field

Reserved - do not

Type

Default

Description

7

R/W

0

use

6

5

LDO1_PG_INT

R/W

0

Latched status bit indicating that the LDO1 Power-Good event has been detected.

Write 1 to clear.

LDO1_SC_INT

LDO1_ILIM_INT

Latched status bit indicating that the LDO1 output voltage has been over 1 ms below

the short-circuit threshold level.

Write 1 to clear.

4

3

2

1

R/W

0

Latched status bit indicating that the LDO1 output current limit has been active.

Write 1 to clear.

Reserved - do not

use

LDO0_PG_INT

Latched status bit indicating that the LDO0 Power-Good event has been detected.

Write 1 to clear.

LDO0_SC_INT

Latched status bit indicating that the LDO0 output voltage has been over 1 ms below

the short-circuit threshold level.

Write 1 to clear.

0

LDO0_ILIM_INT

R/W

0

Latched status bit indicating that the LDO0 output current limit has been active.

Write 1 to clear.

7.6.1.30 TOP_STAT

TOP_STAT is shown in Table 7-67, Address: 0x1D

Table 7-66. TOP_STAT Register

D7

D6

D5

D4

D3

D2

D1

D0

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PGOOD_STAT

Reserved - do not use

SYNC_CLK

_STAT

TDIE_SD

_STAT

TDIE_WARN

_STAT

OVP_STAT

Reserved - do

not use

Table 7-67. TOP_STAT Register Field Descriptions

Bits

Field

Type

Default

Description

7

PGOOD_STAT

R

0

Status bit indicating the status of the PGOOD pin:

0 - PGOOD pin is inactive.

1 - PGOOD pin is active.

6:5

4

Reserved - do not

use

R

00

0

SYNC_CLK_STAT

Status bit indicating the status of the external clock (CLKIN):

0 - External clock frequency is valid.

1 - External clock frequency is not valid.

3

2

1

0

TDIE_SD_STAT

R

0

Status bit indicating the status of the thermal shutdown:

0 - Die temperature below the thermal shutdown level.

1 - Die temperature above the thermal shutdown level.

TDIE_WARN

_STAT

Status bit indicating the status of thermal warning:

0 - Die temperature below the thermal warning level.

1 - Die temperature above the thermal warning level.

OVP_STAT

Status bit indicating the status of the input overvoltage monitoring:

0 - Input voltage is below overvoltage threshold level.

1 - Input voltage above overvoltage threshold level.

Reserved - do not

use

7.6.1.31 BUCK_STAT

BUCK_STAT is shown in Table 7-69, Address: 0x1E

Table 7-68. BUCK_STAT Register

D7

D6

D5

D4

D3

D2

D1

D0

BUCK1_STAT

BUCK1_PG

_STAT

Reserved - do

not use

BUCK1_ILIM

_STAT

BUCK0_STAT

BUCK0_PG

_STAT

Reserved - do

not use

BUCK0_ILIM

_STAT

Table 7-69. BUCK_STAT Register Field Descriptions

Bits

Field

BUCK1_STAT

Type

Default

Description

7

R

0

Status bit indicating the enable and disable status of the Buck1:

0 - Buck1 regulator is disabled.

1 - Buck1 regulator is enabled.

6

BUCK1_PG_STAT

R

0

Status bit indicating the Buck1 output voltage validity (raw status):

0 - Buck1 output voltage is valid.

1 - Buck1 output voltage is invalid.

5

4

Reserved - do not

use

R

0

BUCK1_ILIM

_STAT

Status bit indicating the Buck1 current limit status (raw status):

0 - Buck1 output current is below the current limit level.

1 - Buck1 output current limit is active.

3

2

1

BUCK0_STAT

R

0

Status bit indicating the enable and disable status of the Buck0:

0 - Buck0 regulator is disabled.

1 - Buck0 regulator is enabled.

BUCK0_PG_STAT

Status bit indicating the Buck0 output voltage validity (raw status):

0 - Buck0 output voltage is valid.

1 - Buck0 output voltage is invalid.

Reserved - do not

use

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Table 7-69. BUCK_STAT Register Field Descriptions (continued)

Bits

Field

Type

Default

Description

0

BUCK0_ILIM

_STAT

R

0

Status bit indicating the Buck0 current limit status (raw status):

0 - Buck0 output current is below the current limit level.

1 - Buck0 output current limit is active.

7.6.1.32 LDO_STAT

LDO_STAT is shown in Table 7-71, Address: 0x1F

Table 7-70. LDO_STAT Register

D7

D6

D5

D4

D3

D2

D1

D0

LDO1_STAT

LDO1_PG

_STAT

Reserved - do

not use

LDO1_ILIM

_STAT

LDO0_STAT

LDO0_PG

_STAT

Reserved - do

not use

LDO0_ILIM

_STAT

Table 7-71. LDO_STAT Register Field Descriptions

Bits

Field

Type

Default

Description

7

LDO1_STAT

R

0

Status bit indicating the enable and disable status of the LDO1:

0 - LDO1 regulator is disabled.

1 - LDO1 regulator is enabled.

6

LDO1_PG_STAT

R

0

Status bit indicating the LDO1 output voltage validity (raw status):

0 - LDO1 output voltage is valid.

1 - LDO1 output voltage is invalid.

5

4

Reserved - do not

use

R

0

LDO1_ILIM

_STAT

Status bit indicating the LDO1 current limit status (raw status):

0 - LDO1 output current is below the current limit level.

1 - LDO1 output current limit is active.

3

2

LDO0_STAT

R

0

Status bit indicating the enable and disable status of the LDO0:

0 - LDO0 regulator is disabled.

1 - LDO0 regulator is enabled.

LDO0_PG_STAT

Status bit indicating the LDO0 output voltage validity (raw status):

0 - LDO0 output voltage is valid.

1 - LDO0 output voltage is invalid.

1

0

Reserved - do not

use

R

0

LDO0_ILIM

_STAT

Status bit indicating the LDO0 current limit status (raw status):

0 - LDO0 output current is below the current limit level.

1 - LDO0 output current limit is active.

7.6.1.33 TOP_MASK_1

TOP_MASK_1 is shown in Table 7-73, Address: 0x20

Table 7-72. TOP_MASK_1 Register

D7

D6

D5

D4

D3

D2

D1

D0

PGOOD_INT_

MASK

Reserved - do not use

SYNC_CLK

_MASK

Reserved - do

not use

TDIE_WARN

_MASK

Reserved - do

not use

I_LOAD_

READY_MASK

Table 7-73. TOP_MASK_1 Register Field Descriptions

Bits

Field

Type

Default

Description

7

PGOOD_INT

_MASK

R/W

X

Masking for Power-Good interrupt (PGOOD_INT in INT_TOP_1 register):

0 - Interrupt is generated.

1 - Interrupt is not generated.

This bit does not affect the PGOOD_STAT status bit in the TOP_STAT register.

6:5

Reserved - do not

use

R/W

00

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Table 7-73. TOP_MASK_1 Register Field Descriptions (continued)

Bits

Field

Type

Default

Description

4

SYNC_CLK

_MASK

R/W

X

Masking for the external clock detection interrupt (SYNC_CLK_INT in INT_TOP_1

register):

0 - Interrupt is generated.

1 - Interrupt is not generated.

This bit does not affect the SYNC_CLK_STAT status bit in the TOP_STAT register.

3

2

Reserved - do not

use

R/W

0

TDIE_WARN

_MASK

X

Masking for the thermal warning interrupt (TDIE_WARN_INT in INT_TOP_1 register):

0 - Interrupt is generated.

1 - Interrupt is not generated.

This bit does not affect the TDIE_WARN_STAT status bit in the TOP_STAT register.

1

0

Reserved - do not

use

R/W

0

I_MEAS

_MASK

X

Masking for the load current measurement ready interrupt (MEAS_INT in INT_TOP_1

register):

0 - Interrupt is generated.

1 - Interrupt is not generated.

7.6.1.34 TOP_MASK_2

TOP_MASK_2 is shown in Table 7-75, Address: 0x21

Table 7-74. TOP_MASK_2 Register

D7

D6

D5

D4

D3

D2

D1

D0

Reserved - do not use

RESET_REG

_MASK

Table 7-75. TOP_MASK_2 Register Field Descriptions

Bits

Field

Type

Default

Description

7:1

Reserved - do not

use

R/W

000 0000

0

RESET_REG

_MASK

R/W

X

Masking for register reset interrupt (RESET_REG_INT in INT_TOP_2 register):

0 - Interrupt is generated.

1 - Interrupt is not generated.

This change of this bit by I²C writing has no effect because it will be read from OTP

memory during reset.

7.6.1.35 BUCK_MASK

BUCK_MASK is shown in Table 7-77, Address: 0x22

Table 7-76. BUCK_MASK Register

D7

D6

D5

D4

D3

D2

D1

D0

BUCK1_PGF

_MASK

BUCK1_PGR

_MASK

Reserved - do

not use

BUCK1_ILIM

_MASK

BUCK0_PGF

_MASK

BUCK0_PGR

_MASK

Reserved - do

not use

BUCK0_ILIM

_MASK

Table 7-77. BUCK_MASK Register Field Descriptions

Bits

Field

Type

Default

Description

7

BUCK1_PGF_MAS

K

R/W

X

Masking of the Power Good invalid detection for the Buck1 power good interrupt

(BUCK1_PG_INT in INT_BUCK register):

0 - Interrupt is generated.

1 - Interrupt is not generated.

This bit does not affect the BUCK1_PG_STAT status bit in the BUCK_STAT register.

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Table 7-77. BUCK_MASK Register Field Descriptions (continued)

Field

Type

Default

Description

6

BUCK1_PGR_MAS

K

R/W

X

Masking of the Power Good valid detection for the Buck1 Power Good interrupt

(BUCK1_PG_INT in INT_BUCK register):

0 - Interrupt is generated.

1 - Interrupt is not generated.

This bit does not affect the BUCK1_PG_STAT status bit in the BUCK_STAT register.

5

4

Reserved - do not

use

R

0

BUCK1_ILIM

_MASK

R/W

X

Masking for the Buck1 current limit detection interrupt (BUCK1_ILIM_INT in

INT_BUCK register):

0 - Interrupt is generated.

1 - Interrupt is not generated.

This bit does not affect the BUCK1_ILIM_STAT status bit in the BUCK_STAT register.

3

2

BUCK0_PGF_MAS

K

R/W

X

Masking of the Power Good invalid detection for the Buck0 power good interrupt

(BUCK0_PG_INT in INT_BUCK register):

0 - Interrupt is generated.

1 - Interrupt is not generated.

This bit does not affect BUCK0_PG_STAT status bit in BUCK_STAT register.

BUCK0_PGR_MAS

K

Masking of the Power Good valid detection for the Buck0 power good interrupt

(BUCK0_PG_INT in INT_BUCK register):

0 - Interrupt is generated.

1 - Interrupt is not generated.

This bit does not affect the BUCK0_PG_STAT status bit in the BUCK_STAT register.

1

0

Reserved - do not

use

R

0

BUCK0_ILIM

_MASK

R/W

X

Masking for the Buck0 current limit detection interrupt (BUCK0_ILIM_INT in

INT_BUCK register):

0 - Interrupt is generated.

1 - Interrupt is not generated.

This bit does not affect the BUCK0_ILIM_STAT status bit in the BUCK_STAT register.

7.6.1.36 LDO_MASK

LDO_MASK is shown in Table 7-79, Address: 0x23

Table 7-78. LDO_MASK Register

D7

D6

D5

D4

D3

D2

D1

D0

LDO1_PGF

_MASK

LDO1_PGR

_MASK

Reserved - do

not use

LDO1_ILIM

_MASK

LDO0_PGF

_MASK

LDO0_PGR

_MASK

Reserved - do

not use

LDO0_ILIM

_MASK

Table 7-79. LDO_MASK Register Field Descriptions

Bits

Field

Type

Default

Description

7

6

LDO1_PGF_MASK

LDO1_PGR_MASK

R/W

X

Masking of the Power Good invalid detection for the LDO1 power good interrupt

(LDO1_PG_INT in INT_LDO register):

0 - Interrupt is generated.

1 - Interrupt is not generated.

This bit does not affect the LDO1_PG_STAT status bit in the LDO_STAT register.

R/W

X

Masking of the Power Good valid detection for the LDO1 power good interrupt

(LDO1_PG_INT in INT_LDO register):

0 - Interrupt is generated.

1 - Interrupt is not generated.

This bit does not affect the LDO1_PG_STAT status bit in the LDO_STAT register.

5

4

Reserved - do not

use

R

0

LDO1_ILIM

_MASK

R/W

X

Masking for the LDO1 current limit detection interrupt (LDO1_ILIM_INT in INT_LDO

register):

0 - Interrupt is generated.

1 - Interrupt is not generated.

This bit does not affect the LDO1_ILIM_STAT status bit in the LDO_STAT register.

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Table 7-79. LDO_MASK Register Field Descriptions (continued)

Bits

Field

Type

Default

Description

3

LDO0_PGF_MASK

R/W

X

Masking of the Power Good invalid detection for the LDO0 power good interrupt

(LDO0_PG_INT in INT_LDO register):

0 - Interrupt is generated.

1 - Interrupt is not generated.

This bit does not affect the LDO0_PG_STAT status bit in the LDO_STAT register.

2

LDO0_PGR_MASK

R/W

X

0

Masking of Power Good valid detection for the LDO0 power good interrupt

(LDO0_PG_INT in INT_LDO register):

0 - Interrupt is generated.

1 - Interrupt is not generated.

This bit does not affect the LDO0_PG_STAT status bit in the LDO_STAT register.

1

0

Reserved - do not

use

R

LDO0_ILIM

_MASK

R/W

Masking for the LDO0 current limit detection interrupt (LDO0_ILIM_INT in INT_LDO

register):

0 - Interrupt is generated.

1 - Interrupt is not generated.

This bit does not affect the LDO0_ILIM_STAT status bit in the LDO_STAT register.

7.6.1.37 SEL_I_LOAD

SEL_I_LOAD is shown in Table 7-81, Address: 0x24

Table 7-80. SEL_I_LOAD Register

D7

D6

D5

D4

D3

D2

D1

D0

Reserved - do not use

LOAD_CURRE

NT_BUCK

_SELECT

Table 7-81. SEL_I_LOAD Register Field Descriptions

Bits

Field

Type

Default

Description

7:1

Reserved - do not

use

R/W

000 0000

0

LOAD_CURRENT_

BUCK_SELECT

R/W

0

Start the current measurement on the selected regulator:

0 - Buck0

1 - Buck1

The measurement is started when the register is written.

If the selected buck is master, then the measurement result is a sum current of the

master and slave buck.

If the selected buck is slave, then the measurement result is a current of the selected

slave buck.

7.6.1.38 I_LOAD_2

I_LOAD_2 is shown in Table 7-83, Address: 0x25

Table 7-82. I_LOAD_2 Register

D7

D6

D5

D4

D3

D2

D1

D0

Reserved - do not use

BUCK_LOAD_

CURRENT[8]

Table 7-83. I_LOAD_2 Register Field Descriptions

Bits

Field

Type

Default

Description

7:1

Reserved - do not

use

R

000 0000

0

BUCK_LOAD_

CURRENT[8]

R

0

This register describes the MSB bit of the average load current on the selected

regulator with a resolution of 20 mA per LSB and maximum 10.22-A current.

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7.6.1.39 I_LOAD_1

I_LOAD_1 is shown in Table 7-85, Address: 0x26

Table 7-84. I_LOAD_1 Register

D7

D6

D5

D4

D3

D2

D1

D0

BUCK_LOAD_CURRENT[7:0]

Table 7-85. I_LOAD_1 Register Field Descriptions

Bits

Field

Type

Default

Description

7:0

BUCK_LOAD_

CURRENT[7:0]

R

0000 0000 This register describes 8 LSB bits of the average load current on the selected

regulator with a resolution of 20 mA per LSB and maximum 10.22-A current.

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8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and

TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

8.1 Application Information

The LP8732xx-Q1 is a power management unit including two step-down regulators, two linear regulators, and

two general-purpose digital output signals.

8.2 Typical Applications

L₀

V_{OUT_B0}

V_IN

VIN_B0

VIN_B1

SW_B0

FB_B0

C_{IN_BUCK0}

C_{IN_BUCK1}

C_{OUT_BUCK0}

LOAD

C_{POL_BUCK0}

VIN_LDO0

VIN_LDO1

L₁

C_{IN_LDO0}

C_{IN_LDO1}

V_{OUT_B1}

SW_B1

FB_B1

VANA

C_ANA

SDA

SCL

nINT

EN

C_{OUT_BUCK1}

LOAD

C_{POL_BUCK1}

V_{OUT_LDO0}

VOUT_LDO0

VOUT_LDO1

CLKIN (GPO2)

GPO

V_{OUT_LDO1}

PGOOD

GNDs

C_{OUT_LDO0}C_{OUT_LDO1}

Figure 8-1. Two Single-Phase Buck Outputs Configuration

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L₀

V_{OUT_B0}

V_IN

VIN_B0

VIN_B1

SW_B0

FB_B0

C_{IN_BUCK0}

C_{IN_BUCK1}

C_{OUT_BUCK0}

VIN_LDO0

VIN_LDO1

L₁

C_{IN_LDO0}

C_{IN_LDO1}

LOAD

C_{POL_BUCK}

SW_B1

FB_B1

VANA

C_ANA

C_{OUT_BUCK1}

SDA

SCL

nINT

EN

V_{OUT_LDO0}

VOUT_LDO0

VOUT_LDO1

CLKIN (GPO2)

GPO

V_{OUT_LDO1}

PGOOD

GNDs

C_{OUT_LDO0}C_{OUT_LDO1}

Figure 8-2. Single Dual-Phase Buck Output Configuration

8.2.1 Design Requirements

8.2.1.1 Inductor Selection

The inductors L₀and L₁are shown in the Section 8.2. The inductance and DCR of the inductor affects the

control loop of the buck regulator. TI recommends using inductors similar to those listed in Table 8-1. Pay

attention to the saturation current and temperature rise current of the inductor. Check that the saturation current

is higher than the peak current limit and the temperature rise current is higher than the maximum expected rms

output current. The minimum effective inductance to ensure good performance is 0.22 μH at maximum peak

output current over the operating temperature range. DC resistance of the inductor must be less than 0.05 Ω

for good efficiency at high-current conditions. The inductor AC loss also affects conversion efficiency. Higher Q

factor at switching frequency usually gives better efficiency at light load to middle load. Shielded inductors are

preferred, as they radiate less noise.

Table 8-1. Recommended Inductors

RATED DC CURRENT

I_SATmaximum (typical) /

I_TEMPmaximum (typical) (A)

DCR

typical / maximum

(mΩ)

MANUFACTURER

TOKO

PART NUMBER

VALUE

DIMENSIONS L × W × H (mm)

2.5 × 2 × 1.2

DFE252012PD-

R47M

0.47 µH (20%)

5.2 (–) / 4 (–)⁽¹⁾

— / 27

Tayo Yuden

MDMK2020TR47MM 0.47 µH (20%)

V

2 × 2 ×1.2

4.2 (4.8) / 2.3 (2.45)

40 / 46

(1) Operating temperature range is up to 125°C including self temperature rise.

8.2.1.2 Buck Input Capacitor Selection

The input capacitors C_{IN_BUCK0}and C_{IN_BUCK1}are shown in the Section 8.2. A ceramic input bypass capacitor of

10 μF is required for each phase of the regulator. Place the input capacitor as close as possible to the VIN_Bx

pin and PGND_Bx pin of the device. A larger value or higher voltage rating improves the input voltage filtering.

Use X7R type of capacitors, not Y5V or F. Also, the DC bias characteristics capacitors must be considered.

The minimum effective input capacitance to ensure good performance is 1.9 μF per buck input at maximum

input voltage including tolerances, ambient temperature range, and aging (assuming at least 22 μF of additional

capacitance is common for all the power input pins on the system power rail). See Table 8-2.

The input filter capacitor supplies current to the high-side FET switch in the first half of each cycle and reduces

voltage ripple imposed on the input power source. The low ESR of the ceramic capacitor provides the best

noise filtering of the input voltage spikes due to this rapidly changing current. Select an input filter capacitor with

sufficient ripple current rating. In addition, ferrite can be used in front of the input capacitor to reduce the EMI.

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Table 8-2. Recommended Buck Input Capacitor (X7R Dielectric)

DIMENSIONS L × W × H

(mm)

MANUFACTURER

PART NUMBER

VALUE

CASE SIZE

VOLTAGE RATING

Murata

GCM21BR71A106KE22

10 µF (10%)

0805

2 × 1.25 × 1.25

10 V

8.2.1.3 Buck Output Capacitor Selection

The output capacitor C_{OUT_BUCK0}and C_{OUT_BUCK1}are shown in Section 8.2. A ceramic local output capacitor

of 22 μF is required per phase. Use ceramic capacitors, X7R type; do not use Y5V or F. DC bias voltage

characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out current flow

from the inductor to the load, which helps maintain a steady output voltage during transient load changes and

reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently

low ESR and ESL to perform these functions. The minimum effective output capacitance to ensure good

performance is 10 μF per phase, including the DC voltage rolloff, tolerances, aging, and temperature effects.

The output voltage ripple is caused by the charging and discharging of the output capacitor and due to its R_ESR

.

The R_ESRis frequency dependent (and temperature dependent); ensure the value used for selection process is

at the switching frequency of the part. See Table 8-3.

POL capacitors C_{POL_BUCKx}can be used to improve load transient performance and to decrease the ripple

voltage. A higher output capacitance improves the load step behavior, reduces the output voltage ripple, and

decreases the PFM switching frequency. However, output capacitance higher than 150 μF per phase is not

necessarily of any benefit. The output capacitor may be the limiting factor in the output voltage ramp, see

Section 6 for maximum output capacitance for different slew-rate settings. For large output capacitors, the

output voltage might be slower than the programmed ramp rate at voltage transitions, because of the higher

energy stored on the output capacitance. Also at start-up, the time required to charge the output capacitor to

target value might be longer. At shutdown, the output voltage is discharged to a 0.6 V level using forced-PWM

operation. This can increase the input voltage if the load current is small and the output capacitor is large

compared to input capacitor. Below the 0.6 V level, the output capacitor is discharged by the internal discharge

resistor, and with large capacitor more time is required to settle V_OUTdown as a consequence of the increased

time constant.

Table 8-3. Recommended Buck Output Capacitors (X7R Dielectric)

MANUFACTURER

PART NUMBER

VALUE

CASE SIZE

DIMENSIONS L × W × H

(mm)

VOLTAGE RATING

Murata

GCM31CR71A226KE02

22 µF (10%)

1206

3.2 × 1.6 × 1.6

10 V

8.2.1.4 LDO Input Capacitor Selection

The input capacitors C_{IN_LDO0}and C_{IN_LDO1}are shown in the Table 8-4. A ceramic input capacitor of 2.2 μF, 6.3

V is sufficient for most applications. Place the input capacitor as close as possible to the VIN_LDOx pin and

AGND pin of the device. A larger value or higher voltage rating improves the input voltage filtering. Use X7R type

of capacitors, not Y5V or F. DC bias characteristics of capacitors must be considered, the minimum effective

input capacitance to ensure good performance is 0.6 μF per LDO input at maximum input voltage including

tolerances, ambient temperature range, and aging. See Table 8-4.

Table 8-4. Recommended LDO Input Capacitors (X7R Dielectric)

MANUFACTURER

PART NUMBER

VALUE

CASE SIZE

DIMENSIONS L × W × H

(mm)

VOLTAGE RATING

Murata

GCM188R70J225KE22

GCM21BR71C475KA73

2.2 µF (10%)

4.7 µF (10%)

0603

0805

1.6 × 0.8 × 0.8

2 × 1.25 × 1.25

6.3 V

16 V

8.2.1.5 LDO Output Capacitor Selection

The output capacitors C_{OUT_LDO0}and C_{OUT_LDO1}are shown in the Section 8.2. A ceramic output capacitor of

minimum 1.0 μF is required. Place the output capacitor as close to the VOUT_LDOx pin and AGND pin of the

device as possible. Use X7R type of capacitors, not Y5V or F. DC bias characteristics of capacitors must be

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considered, the minimum effective output capacitance to ensure good performance is 0.4 μF per LDO input at

maximum input voltage including tolerances, ambient temperature range, and aging. See Table 8-5.

Note: the output capcitor requirements excludes any capacitance seen at the point of load and only refers to the

capacitance seen close to the device. Additional capacitance placed near the load can be supported, but the

end applcation system should be evaluated for stability and to ensure the sequencing requirements are met. The

shutdown decay will be longer with higher output capcitance, which can also impact the startup time. Total output

capacitance should be kept below 100 µF.

The output capacitance must be smaller than the input capacitance to ensure the stability of the LDO. With a

1-μF output capacitor, TI recommends using at least a 2.2-μF input capacitor; with a 2.2-μF output capacitor at

least 4.7-μF input capacitance.

The VANA input is used to supply analog and digital circuits in the device. See Table 8-6 for recommended

components from for VANA input supply filtering.

Table 8-5. Recommended LDO Output Capacitors (X7R Dielectric)

MANUFACTURER

Murata

PART NUMBER

VALUE

CASE SIZE

DIMENSIONS L × W × H (mm)

VOLTAGE RATING

GCM188R71C105KA64

GCM188R70J225KE22

1 µF (10%)

2.2 µF (10%)

0603

1.6 × 0.8 × 0.8

16 V

Murata

0603

1.6 × 0.8 × 0.8

6.3 V

Table 8-6. Recommended Supply Filtering Components

MANUFACTURER

Murata

PART NUMBER

VALUE

CASE SIZE

DIMENSIONS L × W × H (mm)

VOLTAGE RATING

GCM155R71C104KA55 100 nF (10%)

GCM188R71C104KA37 100 nF (10%)

0402

1 × 0.5 × 0.5

16 V

Murata

0603

1.6 × 0.8 × 0.8

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8.2.1.6 Current Limit vs. Maximum Output Current

The inductor current ripple can be calculated using Equation 1 and Equation 2:

V_OUT

D =

V

ì h

IN(max)

(1)

(2)

(V_IN(max)- V_OUT) ì D

f_SWì L

DI_L=

Example using Equation 1 and Equation 2:

V_IN(max)= 5.5 V

V_OUT= 1 V

η = 0.75

f_SW= 1.8 MHz

L = 0.38 µH

then D = 0.242 and ΔI_L= 1.59 A

Peak current is half of the current ripple. If I_{LIM_FWD_SET_OTP}is 3 A, the minimum forward current limit would be

2.85 A when taking the –5% tolerance into account. In this case the difference between set peak current and

maximum load current = 0.795 A + 0.15 A = 0.945 A.

Inductor current =

Forward current

I_{LIM_FWD_MAX}(+20%)

I_{LIM_FWD_TYP}(+7.5%)

I_{LIM_FWD_SET_OTP}(1.5...3 A, 0.5-A step)

I_{LIM_FWD_MIN}(-5%)

Minimum 1A guard band

to take current ripple,

inductor inductance

variation into account

I_{L_AVG}= I_OUT

1 / f_SW

I_{OUT_MAX}< I_{LIM_FWD_SET_OTP}œ 1 A

Figure 8-3. Current Limit vs Maximum Output Current

8.2.2 Detailed Design Procedure

The performance of the LP8732xx-Q1 device depends greatly on the care taken in designing the printed circuit

board (PCB). The use of low-inductance and low serial-resistance ceramic capacitors is strongly recommended,

while proper grounding is crucial. Attention must be given to decoupling the power supplies. Decoupling

capacitors must be connected close to the device and between the power and ground pins to support high peak

currents being drawn from system power rail during turnon of the switching MOSFETs. Keep input and output

traces as short as possible, because trace inductance, resistance, and capacitance can become performance

limiting items. The separate buck regulator power pins VIN_Bx are not connected together internally. Connect

the VIN_Bx power connections together outside the package using power plane construction.

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8.2.3 Application Curves

Measurements are done using typical application set up with connections shown in Section 8.2. Graphs may not

reflect the OTP default settings. Unless otherwise specified: V_{(VIN_Bx)}= V_{(VIN_LDOx)}= V_(VANA)= 3.7 V, V_{OUT_Bx}

=

1 V, V_{OUT_LDOx}= 1 V, T_A= 25°C, L = 0.47 µH (TOKO DFE252012PD-R47M), C_{OUT_BUCK}= 22 µF / phase, and

C_{POL_BUCK}= 22 µF, C_{OUT_LDO}= 1 µF.

100

90

80

70

60

50

40

100

90

80

70

60

50

40

Vin=5V, AUTO

Vin=3.3V, AUTO

Vin=5V, FPWM

Vin=3.3V, FPWM

Vin=5V, AUTO

Vin=3.3V, AUTO

Vin=5V, FPWM

Vin=3.3V, FPWM

0.001

0.01

0.1

Output Current (A)

1

2

0.001

0.01

0.1

Output Current (A)

1

4

D004

D006

V_OUT= 1.8 V

Figure 8-4. Buck Efficiency in PFM/PWM and

Forced PWM Mode (Single-Phase Output)

Figure 8-5. Buck Efficiency in PFM/PWM and

Forced PWM Mode (Dual-Phase Output)

100

90

80

70

60

100

90

80

70

60

Vout=1V

Vout=1.8V

Vout=2.5V

Vout=1V

Vout=1.8V

Vout=2.5V

50

40

0.001

0.01

0.1

Output Current (A)

1

2

0.001

0.01

0.1

Output Current (A)

1

4

D008

D010

V_IN= 3.3 V

Figure 8-6. Buck Efficiency in Forced PWM Mode

(Single-Phase Output)

Figure 8-7. Buck Efficiency in Forced PWM Mode

(Dual-Phase Output)

100

90

80

70

60

100

90

80

70

60

Vout=1V

Vout=1.8V

Vout=2.5V

Vout=1V

Vout=1.8V

Vout=2.5V

50

40

0.001

0.01

0.1

Output Current (A)

1

2

0.001

0.01

0.1

Output Current (A)

1

4

D012

D014

V_IN= 5 V

Figure 8-8. Buck Efficiency in Forced PWM Mode

(Single-Phase Output)

Figure 8-9. Buck Efficiency in Forced PWM Mode

(Dual-Phase Output)

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1.02

1.016

1.012

1.008

1.004

1

1.02

1.016

1.012

1.008

1.004

1

0.996

0.992

0.988

0.996

0.992

0.988

0.984

0.98

Vin=3.3V, FPWM

Vin=5.0V, FPWM

Vin=3.3V, FPWM

Vin=5.0V, FPWM

0.984

0.98

0

0.5

1

Output Current (A)

1.5

2

0

0.5

1

1.5

2

2.5

Output Current (A)

3

3.5

4

D016

D018

V_OUT= 1 V

Figure 8-10. Buck Output Voltage vs Load Current

in Forced PWM Mode (Single-Phase Output)

Figure 8-11. Buck Output Voltage vs Load Current

in Forced PWM Mode (Dual-Phase Output)

1.02

1.015

1.01

1.005

1

1.02

1.016

1.012

1.008

1.004

1

0.996

0.992

0.988

0.995

0.99

0.985

0.98

Vin=3.3V, AUTO

Vin=5.0V, AUTO

Vin=3.3V, AUTO

0.984

Vin=5.0V, AUTO

0.98

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

0

0.2

0.4 0.6

Output Current (A)

0.8

1

D019

D020

V_OUT= 1 V

Figure 8-12. Buck Output Voltage vs Load Current

in PFM/PWM Mode (Single-Phase Output)

Figure 8-13. Buck Output Voltage vs Load Current

in PFM/PWM Mode (Dual-Phase Output)

1.02

1.016

1.012

1.008

1.004

1

1.02

1.016

1.012

1.008

1.004

1

0.996

0.992

0.988

0.984

0.98

0.996

0.992

0.988

0.984

0.98

2.5

3

3.5

4

Input Voltage (V)

4.5

5

5.5

2.5

3

3.5

4

Input Voltage (V)

4.5

5

5.5

D021

D022

V_OUT= 1 V

Load = 1 A

V_OUT= 1 V

Load = 1 A

Figure 8-14. Buck Output Voltage vs Input Voltage

in PWM Mode (Single-Phase Output)

Figure 8-15. Buck Output Voltage vs Input Voltage

in PWM Mode (Dual-Phase Output)

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1.02

3

2

1

0

1.015

1.01

1.005

1

0.995

0.99

0.985

0.98

PFM

PWM

ADDING

SHEDDING

-40

-20

0

20

40

60

80

100 120 140

0

0.2 0.4 0.6 0.8

1

Output Current (A)

1.2 1.4 1.6 1.8

2

Temperature (èC)

D023

D025

Load = 1 A (PWM) and 0.1 A (PFM)

V_IN= 3.7 V

Figure 8-16. Buck Output Voltage vs Temperature

Figure 8-17. Buck Phase Adding and Shedding vs

Load Current (Dual-Phase Output)

Slew-rate = 10 mV/µs

I_LOAD= 0 A

V_OUT= 1 V

Slew-rate = 10 mV/µs

I_LOAD= 0 A

V_OUT= 1 V

Figure 8-19. Buck Start-Up With EN1, Forced PWM

Mode (Dual-Phase Output)

Figure 8-18. Buck Start-Up With EN1, Forced PWM

Mode (Single-Phase Output)

Slew-rate = 10 mV/µs

R_LOAD= 1 Ω

V_OUT= 1 V

Slew-rate = 10 mV/µs

R_LOAD= 0.5 Ω

V_OUT= 1 V

Figure 8-20. Buck Start-Up with EN1, Forced PWM Figure 8-21. Buck Start-Up with EN1, Forced PWM

Mode (Single-Phase Output) Mode (Dual-Phase Output)

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Slew-rate = 10 mV/µs

R_LOAD= 1 Ω

V_OUT= 1 V

Slew-rate = 10 mV/µs

R_LOAD= 0.5 Ω

V_OUT= 1 V

Figure 8-22. Buck Shutdown With EN1, Forced

PWM Mode (Single-Phase Output)

Figure 8-23. Buck Shutdown With EN1, Forced

PWM Mode (Dual-Phase Output)

I_OUT= 10 mA

Figure 8-24. Buck Output Voltage Ripple, PFM

Mode (Single-Phase Output)

Figure 8-25. Buck Output Voltage Ripple, PFM

Mode (Dual-Phase Output)

I_OUT= 200 mA

Figure 8-26. Buck Output Voltage Ripple, Forced

PWM Mode (Single-Phase Output)

Figure 8-27. Buck Output Voltage Ripple, Forced

PWM Mode (Dual-Phase Output)

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Figure 8-28. Buck Transient From PFM-to-PWM

Figure 8-29. Buck Transient From PFM-to-PWM

Mode (Dual-Phase Output)

Mode (Single-Phase Output)

Figure 8-30. Buck Transient From PWM-to-PFM

Mode (Single-Phase Output)

Figure 8-31. Buck Transient From PWM-to-PFM

Mode (Dual-Phase Output)

Figure 8-32. Buck Transient From 1-Phase to 2-

Phase Operation (Dual-Phase Output)

Figure 8-33. Buck Transient From 2-Phase to 1-

Phase Operation (Dual-Phase Output)

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I_OUT= 0.1 A → 2 A

→ 0.1 A

T_R= T_F= 400 ns

I_OUT= 0.1 A → 4 A

→ 0.1 A

T_R= T_F= 400 ns

Figure 8-34. Buck Transient Load Step Response, Figure 8-35. Buck Transient Load Step Response,

AUTO Mode (Single-Phase Output) AUTO Mode (Dual-Phase Output)

I_OUT= 0.1 A → 2 A

→ 0.1 A

T_R= T_F= 400 ns

I_OUT= 0.1 A → 4 A

→ 0.1 A

T_R= T_F= 400 ns

Figure 8-36. Buck Transient Load Step Response, Figure 8-37. Buck Transient Load Step Response,

Forced PWM Mode (Single-Phase Output)

Forced PWM Mode (Dual-Phase Output)

V_OUT(200mV/div)

Time (400 µs/div)

Figure 8-38. Buck V_OUTTransition from 0.6 V to 1.4 Figure 8-39. Buck V_OUTTransition from 1.4 V to 0.6

V With Different Slew Rate Settings

72

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Figure 8-40. Buck Start-Up With Short on Output

(Single-Phase Output)

Figure 8-41. Buck Start-up With Short on Output

(Dual-Phase Output)

1.02

1.015

1.01

1.005

1

1.02

1.015

1.01

1.005

1

0.995

0.99

0.985

0.98

0.995

0.99

0.985

0.98

Vin=3.3V

Vin=5V

0

50

100

150

Output Current (mA)

200

250

300

2.5

3

3.5

4

Input Voltage (V)

4.5

5

5.5

D050

D051

V_OUT= 1 V

Load = 200 mA

Figure 8-42. LDO Output Voltage vs Load Current

Figure 8-43. LDO Output Voltage vs Input Voltage

1.02

1.015

1.01

1.005

1

0.995

0.99

0.985

0.98

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D052

I_LOAD= 0 A

V_OUT= 1 V

Load = 200 mA

Figure 8-45. LDO Start-Up

Figure 8-44. LDO Output Voltage vs Temperature

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R_LOAD= 3.3 Ω

V_OUT= 1 V

I_LOAD= 0 A

V_OUT= 1 V

Figure 8-46. LDO Start-Up

Figure 8-47. LDO Shutdown

I_OUT= 0 A → 0.3 A → 0 A

T_R= T_F= 1 µs

Figure 8-49. LDO V_OUTTransition from 1.8 V to 1.2

V

Figure 8-48. LDO Transient Load Step Response

Start-up

delay is 500

µs

Figure 8-50. LDO V_OUTTransition from 1.2 V to 1.8

V

Figure 8-51. LDO Start-Up With Short on Output

9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 2.8 V and 5.5 V. The VANA

input and VIN_Bx buck inputs must be connected together, and they must use the same input supply. This

input supply must be well regulated and able to withstand maximum input current and maintain stable voltage

without voltage drop even at load transition condition. The resistance of the input supply rail must be low enough

that the input current transient does not cause too high a drop in the LP8732xx-Q1 supply voltage that can

cause false UVLO fault triggering. If the input supply is located more than a few inches from the LP8732xx-Q1,

additional bulk capacitance may be required in addition to the ceramic bypass capacitors. The VIN_LDOx LDO

input supply voltage range is 2.5 V to 5.5 V and can be higher or lower than VANA supply voltage.

74

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10 Layout

10.1 Layout Guidelines

The high frequency and large switching currents of the LP8732xx-Q1 make the choice of layout important. Good

power supply results only occur when care is given to proper design and layout. Layout affects noise pickup

and generation and can cause a good design to perform with less-than-expected results. With a range of output

currents from milliamps to several amps, good power supply layout is much more difficult than most general PCB

design. Use the following steps as a reference to ensure the device is stable and maintains proper voltage and

current regulation across its intended operating voltage and current range.

1. Place C_INas close as possible to the VIN_Bx pin and the PGND_Bx pin. Route the V_INtrace wide and

thick to avoid IR drops. The trace between the positive node of the input capacitor and the VIN_Bx pins

of LP8732xx-Q1, as well as the trace between the negative node of the input capacitor and the power

PGND_Bx pins, must be kept as short as possible. The input capacitance provides a low-impedance voltage

source for the switching converter. The inductance of the connection is the most important parameter of a

local decoupling capacitor — parasitic inductance on these traces must be kept as small as possible for

proper device operation. The parasitic inductance can be reduced by using a ground plane as close as

possible to the top layer by using thin dielectric layer between the top layer and the ground plane.

2. The output filter, consisting of L and COUT, converts the switching signal at SW_Bx to the noiseless output

voltage. The output filter must be placed as close as possible to the device, keeping the switch node small

for best EMI behavior. Route the traces between the output capacitors of the LP8732xx-Q1 and the input

capacitors of the load direct and wide to avoid losses due to the IR drop.

3. Input for analog blocks (VANA and AGND) must be isolated from noisy signals. Connect VANA directly to a

quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling

capacitor as close as possible to the VANA pin.

4. If remote voltage sensing can be used for the load, connect the LP8732xx-Q1 feedback pins FB_Bx to the

respective sense pins on the load capacitor. The sense lines are susceptible to noise. They must be kept

away from noisy signals such as PGND_Bx, VIN_Bx, and SW_Bx, as well as high bandwidth signals such

as the I²C. Avoid both capacitive and inductive coupling by keeping the sense lines short and direct, and

close to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground

plane if possible. If series resistors are used for load current measurement, place them after connection of

the voltage feedback.

5. PGND_Bx, VIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers

which are not able to withstand interference from noisy PGND_Bx, VIN_Bx and SW_Bx.

6. LDO performance (PSRR, noise, and transient response) depend on the layout of the PCB. Best

performance is achieved by placing CIN and COUT as close to the LP8732xx-Q1 device as practical.

The ground connections for CIN and COUT must be back to the LP8732xx-Q1 AGND with as wide

and as short of a copper trace as is practical and with multiple vias if routing is done on other layer.

Avoid connections using long trace lengths, narrow trace widths, or connection through small via. These

add parasitic inductances and resistance that results in inferior performance, especially during transient

conditions.

Due to the small package of this converter and the overall small solution size, the thermal performance of the

PCB layout is important. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and

convection surfaces, and the presence of other heat-generating components affect the power dissipation limits

of a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures.

Wide power traces can sink dissipated heat. This can be improved further on multi-layer PCB designs with

vias to different planes. This results in reduced junction-to-ambient (R_θJA) and junction-to-board (R_θJB) thermal

resistances, thereby reducing the device junction temperature, T_J. TI strongly recommends performance of a

careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design process by using a

thermal modeling analysis software.

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10.2 Layout Example

VOUT0

VOUT1

C_OUT0

C_OUT1

GND

L1

L0

21 20 19

17

16

18

15

14

SW_B0

SW_B1

VIN_B1

22

13

12

23

24

C_IN0

C_IN1

29

AGND

VIN_B0

VIN

11

GND

25

VIN_B1

CLKIN

nINT

10

9

GPO

26

27

PGOOD

C_IN2

C_IN3

8

VIN_LDO0

28

VIN_LDO1

VIN

AGND

VIN

AGND

1

2

3

4

5

6

7

C_OUT3

AGND

C_OUT2

VIN

C_ANA

AGND

VOUT2

VOUT3

Figure 10-1. LP8732xx-Q1 Board Layout

In dual-phase buck configuration, short VOUT0 and VOUT1 together.

76

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

20-Dec-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LP873200RHDRQ1

LP873200RHDTQ1

LP873244RHDRQ1

LP873244RHDTQ1

LP873245RHDRQ1

VQFN

RHD

28

3000

250

330.0

180.0

330.0

180.0

330.0

12.4

5.25

1.1

8.0

12.0

Q2

3000

250

3000

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Dec-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LP873200RHDRQ1

LP873200RHDTQ1

LP873244RHDRQ1

LP873244RHDTQ1

LP873245RHDRQ1

VQFN

RHD

28

3000

250

367.0

213.0

367.0

213.0

367.0

191.0

367.0

191.0

367.0

38.0

35.0

38.0

35.0

38.0

3000

250

3000

Pack Materials-Page 2

PACKAGE OUTLINE

RHD0028W

VQFN - 1 mm max height

S

C

A

L

E

2

.

5

0

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

B

A

PIN 1 INDEX AREA

5.1

4.9

0.1 MIN

(0.05)

A

-

A

2

5

.

0

SECTION A-A

TYPICAL

C

1 MAX

SEATING PLANE

0.08

0.05

0.00

3.4 0.1

(0.2) TYP

8

14

EXPOSED

THERMAL PAD

24X 0.5

7

15

A

SYMM

A

4X

3

1

21

0.3

28X

0.2

0.1

C A B

28

22

PIN 1 ID

(OPTIONAL)

SYMM

0.05

0.65

0.45

28X

4222120/B 02/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RHD0028W

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

3.4)

SYMM

22

28

28X (0.75)

1

21

28X (0.25)

(1.45)

SYMM

(4.65)

(0.5) TYP

15

7

(R0.05) TYP

(

0.2) TYP

VIA

8

14

(1.45)

(4.65)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL EDGE

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222120/B 02/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RHD0028W

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

(0.84) TYP

28

22

METAL

TYP

28X (0.75)

1

21

28X (0.25)

(0.84)

TYP

SYMM

(4.65)

24X (0.5)

7

15

(R0.05) TYP

8

14

4X ( 1.47)

(4.65)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

75% PRINTED SOLDER COVERAGE BY AREA

SCALE:20X

4222120/B 02/2018

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LP8732-Q1_V02
厂家：	TEXAS INSTRUMENTS
描述：	LP8732xx-Q1 Dual High-Current Buck Converter and Dual Linear Regulator
文件：	总86页 (文件大小：2889K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LP8732-Q1_V02 [TI]

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