LP8733-Q1_V01 [TI]
LP8733xx-Q1 Dual High-Current Buck Converter and Dual Linear Regulator;型号: | LP8733-Q1_V01 |
厂家: | TEXAS INSTRUMENTS |
描述: | LP8733xx-Q1 Dual High-Current Buck Converter and Dual Linear Regulator |
文件: | 总85页 (文件大小:6530K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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LP8733-Q1
SNVSB64 –SEPTEMBER 2018
LP8733xx-Q1 Dual High-Current Buck Converter and Dual Linear Regulator
1 Features
2 Applications
1
•
AEC-Q100 Qualified With the Following Results:
•
•
•
•
Automotive Head Unit and Cluster
Automotive Camera Module
Surround View System ECU
Radar System ECU
–
Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
•
•
Input Voltage: 2.8 V to 5.5 V
Two High-Efficiency Step-Down DC/DC
Converters:
3 Description
The LP8733xx-Q1 is designed to meet the power
–
–
–
Output Voltage: 0.7 V to 3.36 V
management
requirements
in
automotive
Maximum Output Current 3 A per phase
applications. The device has two step-down DC/DC
converters which can be configured as single dual-
phase regulator or two single-phase regulators and
two linear regulators and general-purpose digital-
output signals. The device is controlled by an I2C-
compatible serial interface and by an enable signal.
Auto Phase Adding/Shedding and Force Multi-
Phase Operations in Dual-Phase Configuration
–
–
Remote Differential Feedback Voltage Sensing
in Dual-Phase Configuration
Programmable Output-Voltage Slew Rate
From 0.5 mV/µs to 10 mV/µs
The automatic PWM/PFM (AUTO mode) operation
together with the automatic phase adding/shedding
maximizes gives high efficiency over a wide output-
current range. The LP8733xx-Q1 supports remote
–
–
2-MHz Switching Frequency
Spread-Spectrum Mode and Phase
Interleaving for EMI Reduction
voltage
sensing
(differential
in
dual-phase
configuration) to compensate IR drop between the
regulator output and the point-of-load (POL), thus
improving the accuracy of the output voltage. In
addition, the switching clock can be forced to PWM
mode and also synchronized to an external clock to
minimize the disturbances.
•
•
Two Linear Regulators:
–
–
–
Input Voltage: 2.5 V to 5.5 V
Output Voltage: 0.8 V to 3.3 V
Maximum Output Current 300 mA
Configurable General-Purpose Output Signals
(GPO, GPO2)
The LP8733xx-Q1 device supports programmable
start-up and shutdown delays and sequences
including GPO signals synchronized to the enable
signal. During start-up and voltage change, the
device controls the output slew rate to minimize
output voltage overshoot and the in-rush current.
•
•
•
•
•
Interrupt Function With Programmable Masking
Programmable Power-Good Signal (PGOOD)
Output Short-Circuit and Overload Protection
Overtemperature Warning and Protection
Overvoltage Protection (OVP) and Undervoltage
Lockout (UVLO)
Device Information
PART NUMBER
PACKAGE
BODY SIZE (NOM)
•
28-pin, 5-mm × 5-mm VQFN Package with
Wettable Flanks
LP8733xx-Q1
VQFN (28)
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Configurable
multi-phase
VIN
DC/DC Efficiency vs Output Current (Dual-Phase)
VIN_B0
VIN_B1
SW_B0
SW_B1
100
1 œ 2
Outputs
VIN_LDO0
VIN_LDO1
90
80
FB_B0
FB_B1
VANA
SDA
SCL
nINT
EN
VOUT_LDO0
VOUT_LDO1
70
VOUT_LDO0
VOUT_LDO1
CLKIN (GPO2)
GPO
1PH, Vin=3.7V, Vout=1.0V
1PH, Vin=3.7V, Vout=2.5V
60
PGOOD
2PH, Vin=3.7V, Vout=1.0V
2PH, Vin=3.7V, Vout=2.5V
50
GNDs
0.025
0.1
1
6
Output Current (A)
D420
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP8733-Q1
SNVSB64 –SEPTEMBER 2018
www.ti.com
Table of Contents
7.5 Programming........................................................... 39
7.6 Register Maps......................................................... 42
Application and Implementation ........................ 60
8.1 Application Information............................................ 60
8.2 Typical Applications ................................................ 60
Power Supply Recommendations...................... 73
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings ............................................................ 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 I2C Serial Bus Timing Parameters.......................... 12
6.7 Typical Characteristics............................................ 14
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ....................................... 17
7.3 Feature Description ................................................ 17
7.4 Device Functional Modes........................................ 38
8
9
10 Layout................................................................... 73
10.1 Layout Guidelines ................................................. 73
10.2 Layout Example .................................................... 75
11 Device and Documentation Support ................. 76
11.1 Device Support...................................................... 76
11.2 Receiving Notification of Documentation Updates 76
11.3 Community Resources.......................................... 76
11.4 Trademarks........................................................... 76
11.5 Electrostatic Discharge Caution............................ 76
11.6 Glossary................................................................ 76
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 76
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
September 2018
*
Initial release
2
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SNVSB64 –SEPTEMBER 2018
5 Pin Configuration and Functions
RHD Package
28-Pin VQFN With Thermal Pad
Top View
21
20
19
18
17
16
15
SW_B0
SW_B0
VIN_B0
VIN_B0
GPO
SW_B1
SW_B1
VIN_B1
VIN_B1
CLKIN
22
23
24
25
26
27
28
14
13
12
11
10
9
THERMAL PAD
PGOOD
VIN_LDO0
nINT
VIN_LDO1
8
1
2
3
4
5
6
7
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NUMBER
NAME
1
2
VOUT_LDO0
FB_B0
P/O
A
LDO0 output. If LDO0 is not used, leave the pin floating.
Output voltage feedback (positive) for Buck 0
Output voltage feedback (positive) for Buck 1 in two single-phase configuration / Output ground
feedback (negative) for Buck 0 in dual-phase configuration
3
FB_B1
A
4
5
AGND
VANA
G
Ground
P/I
Supply voltage for analog and digital blocks. Must be connected to same node with VIN_Bx.
Programmable enable signal for regulators and GPOs. If the pin is not used, leave the pin
floating.
6
EN
D/I
7
8
9
VOUT_LDO1
VIN_LDO1
nINT
P/O
P/I
LDO1 output. If LDO1 is not used, leave the pin floating.
Power input for LDO1. If LDO1 is not used, connect the pin to VANA.
Open-drain interrupt output. Active LOW. If the pin is not used, connect the pin to ground.
D/O
External clock input. Alternative function is general-purpose digital output (GPO2). If the pin is not
used, leave the pin floating.
10
CLKIN
D/I/O
P/I
Input for Buck 1. The separate power pins VIN_Bx are not connected together internally -
VIN_Bx pins must be connected together in the application and be locally bypassed.
11, 12
VIN_B1
13, 14
15, 16
SW_B1
P/O
P/G
Buck 1 switch node. If the Buck 1 is not used, leave the pin floating.
Power ground for Buck 1
PGND_B1
Serial interface clock input for I2C access. Connect a pullup resistor. If the I2C interface is not
used, connect the pin to Ground.
17
SCL
D/I
Serial interface data input and output for I2C access. Connect a pullup resistor. If the I2C
interface is not used, connect the pin to Ground.
18
19
SDA
D/I/O
G
SGND
Ground
(1) A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin
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Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NUMBER
20, 21
NAME
PGND_B0
SW_B0
P/G
P/O
Power ground for Buck 0
Buck 0 switch node. If the Buck 0 is not used, leave the pin floating.
22, 23
Input for Buck 0. The separate power pins VIN_Bx are not connected together internally -
VIN_Bx pins must be connected together in the application and be locally bypassed.
24, 25
VIN_B0
P/I
26
27
28
GPO
D/O
D/O
P/I
General-purpose digital output. If the pin is not used, leave the pin floating.
Power-good indication signal. If the pin is not used, leave the pin floating.
Power input for LDO0. If LDO0 is not used, connect the pin to VANA.
PGOOD
VIN_LDO0
Thermal
Pad
—
—
Connect to PCB ground plane using multiple vias for good thermal performance.
4
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
–0.3
–0.3
–0.3
MAX
UNIT
Voltage on power connections (must use the same
VIN_Bx, VANA
input supply)
6
6
V
V
V
VIN_LDOx
Voltage on power connections
(VIN_Bx + 0.3 V) with 6-V
maximum
SW_Bx
Voltage on buck switch nodes
(VANA + 0.3 V) with 6-V
maximum
FB_Bx
Voltage on buck voltage sense nodes
–0.3
V
(VIN_LDOx + 0.3 V) with 6-V
maximum
VOUT_LDOx
Voltage on LDO output
-0.3
–0.3
–0.3
V
V
V
SDA, SCL, nINT, EN
Voltage on logic pins (input or output pins)
Voltage on logic pins (input or output pins)
6
PGOOD, GPO, CLKIN
(GPO2)
(VANA + 0.3 V) with 6-V
maximum
TJ-MAX
Tstg
Junction temperature
Storage temperature
−40
150
150
260
–65
°C
Maximum lead temperature (soldering, 10 seconds)
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM)
All pins
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM)
Corner pins (1, 7, 8, 14,
15, 21, 22, 28)
±750
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
INPUT VOLTAGE
Voltage on power connections (must use the same input
VIN_Bx, VANA
supply)
2.8
5.5
V
VIN_LDOx
EN, nINT
Voltage on LDO inputs
2.5
0
5.5
5.5
V
V
Voltage on logic pins (input or output pins)
Voltage on logic pins (input pin)
0
VANA with 5.5-V
maximum
CLKIN
V
V
V
PGOOD, GPO, GPO2
Voltage on logic pins (output pins)
0
0
VANA
Voltage on I2C interface, Standard (100 kHz), Fast (400
kHz), Fast+ (1 MHz), and High-Speed (3.4 MHz) Modes
1.95
SCL, SDA
Voltage on I2C interface, Standard (100 kHz), Fast (400
kHz), and Fast+ (1 MHz) Modes
VANA with 3.6-V
maximum
0
V
TEMPERATURE
TJ
Junction temperature
Ambient temperature
−40
−40
140
125
°C
°C
TA
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6.4 Thermal Information
LP8733xx-Q1
THERMAL METRIC(1)
RHD (VQFN)
28 PINS
36.7
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
26.6
8.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ψJB
8.8
RθJCbot
2.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
note.
6.5 Electrical Characteristics
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVIN_LDOx, VVOUT_Bx, VVOUT_LDOx
and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = VVIN_LDOx = 3.7 V, and VOUT = 1 V,
unless otherwise noted.(1)(2)
PARAMETER
.
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EXTERNAL COMPONENTS
Input filtering
capacitance for buck
regulators
Effective capacitance, connected from VIN_Bx
to PGND_Bx
CIN_BUCK
1.9
10
10
22
22
µF
µF
Output filtering
capacitance for buck
regulators
COUT_BUCK
Effective capacitance per phase
500
500
Point-of-load (POL)
capacitance for buck
regulators
CPOL_BUCK
Optional POL capacitance
µF
µF
µF
COUT-
TOTAL_BUCK
Buck output capacitance,
total (local and POL)
Total output capacitance per phase
Input filtering
capacitance for LDO
regulators
Effective capacitance, connected from
VIN_LDOx to AGND. CIN_LDO must be at least
two times larger than COUT_LDO
CIN_LDO
0.6
0.4
2.2
1
Output filtering
capacitance for LDO
regulators
COUT_LDO
Effective capacitance
2.7
10
µF
Input and output
capacitor ESR
ESRC
[1-10] MHz
2
mΩ
0.47
L
Inductor
Inductance of the inductor
µH
–30%
30%
DCRL
Inductor DCR
25
mΩ
BUCK REGULATORS
V(VIN_Bx)
V(VANA)
,
VIN_Bx and VANA pins must be connected to
the same supply line
Input voltage range
Output voltage
2.8
0.7
3.7
5.5
V
V
Programmable voltage range
1
10
5
3.36
Step size, 0.7 V ≤ VOUT < 0.73 V
Step size, 0.73 V ≤ VOUT < 1.4 V
Step size, 1.4 V ≤ VOUT ≤ 3.36 V
Output current, single-phase output
Output current, dual-phase output
VOUT_Bx
mV
A
20
3(3)
6(3)
IOUT_Bx
Output current
(1) All voltage values are with respect to network ground.
(2) Minimum (MIN) and Maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers are not verified,
but do represent the most likely norm.
(3) The maximum output current can be limited by the forward current limit ILIM FWD. The power dissipation inside the die increases the
junction temperature and limits the maximum current depending of the length of the current pulse, efficiency, board and ambient
temperature.
6
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Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVIN_LDOx, VVOUT_Bx, VVOUT_LDOx
and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = VVIN_LDOx = 3.7 V, and VOUT = 1 V,
unless otherwise noted.(1)(2)
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
Input and Output voltage Minimum voltage between V(VIN_Bx) and
difference
0.8
VOUT to fulfill the electrical characteristics
Force PWM mode, VOUT < 1 V
–20
20
mV
DC output voltage
accuracy, includes
voltage reference, DC
load and line regulations,
process and temperature
Force PWM mode, VOUT ≥ 1 V
–2%
2%
PFM mode, VOUT < 1 V, the average output
voltage level is increased by max. 20 mV
VOUT_Bx_DC
–20mV
–2%
40mV
mV
PFM mode, VOUT ≥ 1 V, the average output
voltage level is increased by max. 20 mV
2% + 20
mV
PWM mode
10
25
Ripple voltage, single-
phase output
mVp-p
PFM mode, IOUT = 10 mA
PWM mode
5
Ripple voltage, dual-
phase output
mVp-p
%/V
PFM mode, IOUT = 10 mA
IOUT = 1 A
4
DCLNR
DCLDR
DC line regulation
±0.05
DC load regulation in
PWM mode
VOUT_Bx = 1 V, IOUT from 0 to IOUT(max)
0.3%
±55
Transient load step
response, single-phase
output
IOUT = 0.1 A to 2 A, TR = TF = 400 ns, PWM
mode
mV
mV
TLDSR
Transient load step
response, dual-phase
output
IOUT = 0.1 A to 4 A, TR = TF = 400 ns, PWM
mode
±50
±10
V(VIN_Bx) stepping 3 V ↔ 3.5 V, TR = TF = 10
µs, IOUT = IOUT(max)
TLNSR
Transient line response
mV
A
Programmable range
1.5
4
Forward current limit per
phase (peak for every
switching cycle)
Step size
0.5
7.5%
7.5%
ILIM FWD
Accuracy, V(VIN_Bx) ≥ 3 V, ILIM = 4 A
Accuracy, 2.8 V ≤ V(VIN_Bx) < 3 V, ILIM = 4 A
–5%
20%
20%
–20%
Negative current limit per
phase
ILIM NEG
1.6
2.0
50
3.0
A
On-resistance, high-side Each phase, between VIN_Bx and SW_Bx
FET
RDS(ON) HS FET
110
mΩ
pins (I = 1 A)
On-resistance, low-side
FET
Each phase, between SW_Bx and PGND_Bx
pins (I = 1 A)
RDS(ON) LS FET
ƒSW
45
2
90
2.2
mΩ
Switching frequency
PWM mode
1.8
MHz
Current balancing for
dual-phase output
Current mismatch between phases, IOUT > 1
mA
10%
From ENx to VOUT_Bx = 0.35 V (slew-rate
control begins)
Start-up time (soft start)
120
10
µs
SLEW_RATEx[2:0] = 010, COUT-TOTAL_BUCK
80 µF per phase
<
<
<
SLEW_RATEx[2:0] = 011, COUT-TOTAL_BUCK
130 µF per phase
7.5
SLEW_RATEx[2:0] = 100, COUT-TOTAL_BUCK
250 µF per phase
3.8
Output voltage slew-
rate(4)
–15%
15% mV/µs
SLEW_RATEx[2:0] = 101, COUT-TOTAL_BUCK
< 500 µF per phase
1.9
SLEW_RATEx[2:0] = 110, COUT-TOTAL_BUCK
< 500 µF per phase
0.94
0.47
SLEW_RATEx[2:0] = 111, COUT-TOTAL_BUCK
< 500 µF per phase
(4) The slew-rate can be limited by the current limit (forward or negative current limit), output capacitance and load current.
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Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVIN_LDOx, VVOUT_Bx, VVOUT_LDOx
and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = VVIN_LDOx = 3.7 V, and VOUT = 1 V,
unless otherwise noted.(1)(2)
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PFM-to-PWM - current
threshold(5)
IPFM-PWM
IPWM-PFM
IADD
550
mA
PWM-to-PFM - current
threshold(5)
290
1000
650
mA
mA
mA
Ω
Phase adding level
(dual-phase output)
From 1-phase to 2-phase
Phase shedding level
(dual-phase output)
ISHED
From 2-phase to 1-phase
Regulator disabled
Output pulldown
resistance
RDIS_Bx
150
250
350
V(VIN_Bx) and V(VANA) fixed 3.7 V
Overvoltage threshold (compared to DC
39
–53
4
50
64
–29
15
Output voltage
output voltage level, VVOUT_Bx_DC
Undervoltage threshold (compared to DC
output voltage level, VVOUT_Bx_DC
)
monitoring for PGOOD
pin and for power-good
Interrupt
mV
–40
)
Deglitch time during operation and after
voltage change
µs
µs
Gating time for PGOOD
signal after regulator
enable or voltage
change
PGOOD_MODE = 0
800
LDO REGULATORS
Input voltage range for
VIN_LDOx
VIN_LDOx can be higher or lower than V(VANA)
2.5
0.8
3.7
0.1
5.5
3.3
V
LDO power inputs
Output voltage
Output current
Programmable voltage range
Step size
VOUT_LDOx
IOUT_LDOx
V
300
200
20
mA
V(VIN_LDOx) – V(VOUT_LDOx), IOUT = IOUT(max)
Programmed output voltage is higher than
V(VIN_LDOx)
,
Dropout voltage
mV
mV
DC output voltage
VOUT < 1 V
–20
accuracy, includes
VOUT_LDO_DC
voltage reference, DC
load and line regulations,
process, temperature
VOUT ≥ 1 V
–2%
2%
DCLNR
DCLDR
DC line regulation
DC load regulation
IOUT = 1 mA
0.1
%/V
IOUT = 1 mA to IOUT(max)
0.8%
Transient load step
response
TLDSR
TLNSR
PSRR
IOUT = 1 mA to 300 mA, TR = TF = 1 µs
–50/+40
±7
mV
mV
dB
V(VIN_LDOx) stepping 3 V ↔ 3.5 V, TR = TF
10 µs, IOUT = IOUT(max)
=
Transient line response
Power supply ripple
rejection
ƒ = 10 kHz, IOUT = IOUT(max)
53
Noise
10 Hz < F < 100 kHz, IOUT = IOUT(max)
VOUT = 0 V
82
500
300
15
µVrms
mA
ISHORT(LDOx)
LDO current limit
Start-up time
400
150
600
350
From enable to valid output voltage
µs
Slew rate during start-up
mV/µs
Output pulldown
resistance
RDIS_LDOx
Regulator disabled
250
Ω
(5) The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage and
the inductor current level.
8
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Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVIN_LDOx, VVOUT_Bx, VVOUT_LDOx
and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = VVIN_LDOx = 3.7 V, and VOUT = 1 V,
unless otherwise noted.(1)(2)
.
PARAMETER
TEST CONDITIONS
MIN
106%
3%
TYP
108%
3.5%
92%
MAX
110%
4%
UNIT
Overvoltage monitoring, voltage rising
(compared to DC output voltage level,
VOUT_LDO_DC
)
Overvoltage monitoring, hysteresis
Output voltage
monitoring for PGOOD
pin and for power-good
interrupt
Undervoltage monitoring, voltage falling
(compared to DC output voltage level,
90%
94%
VOUT_LDO_DC
)
Undervoltage monitoring, hysteresis
3%
4
3.5%
4%
15
Deglitch time during operation and after
voltage change
µs
µs
Gating time for PGOOD
signal after regulator
enable or voltage
change
PGOOD_MODE = 0
800
EXTERNAL CLOCK AND PLL
Nominal frequency
1
24
MHz
µs
fEXT_CLK
External input clock(6)
Nominal frequency step size
1
Required accuracy from nominal frequency
Delay for missing clock detection
Delay and debounce for clock detection
–30%
10%
1.8
20
External clock detection
Clock change delay
(internal to external)
Delay from valid clock detection to use of
external clock
600
300
µs
PLL output clock jitter
Cycle to cycle
ps, p-p
PROTECTION FUNCTIONS
Temperature rising, TDIE_WARN_LEVEL = 0
115
127
125
137
20
135
147
Thermal warning
Temperature rising, TDIE_WARN_LEVEL = 1
Hysteresis
°C
°C
Temperature rising
Hysteresis
140
150
20
160
Thermal shutdown
VANA overvoltage
Voltage rising
5.6
5.45
40
5.8
6.1
V
mV
V
VANAOVP
Voltage falling
5.73
5.96
Hysteresis
Voltage rising
2.51
2.5
2.63
2.6
2.75
2.7
VANA undervoltage
lockout
VANAUVLO
Voltage falling
Buck short-circuit
detection
Threshold
Threshold
280
190
360
300
440
450
mV
mV
LDO short-circuit
detection
LOAD CURRENT MEASUREMENT FOR BUCK REGULATORS
Current measurement
Maximum code
range
10.22
A
Resolution
LSB
20
mA
Measurement accuracy
IOUT > 1 A per phase
<10%
PFM mode (automatically changing to PWM
mode for the measurement)
45
4
Measurement time
µs
PWM mode
CURRENT CONSUMPTION
(6) The external clock frequency must be selected so that buck switching frequency is above 1.7 MHz.
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Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVIN_LDOx, VVOUT_Bx, VVOUT_LDOx
and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = VVIN_LDOx = 3.7 V, and VOUT = 1 V,
unless otherwise noted.(1)(2)
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Standby current
consumption, regulators
disabled
9
µA
Active current
consumption, one buck
regulator enabled in auto Single-phase output: IOUT_Bx = 0 mA, not
58
100
72
µA
µA
µA
mode, internal RC
oscillator, PGOOD
monitoring enabled
switching
Active current
consumption, two buck
regulators enabled in
auto mode, internal RC
oscillator, PGOOD
monitoring enabled
Single-phase output: IOUT_Bx = 0 mA, not
switching
Active current
consumption, one buck
regulator enabled in auto Dual-phase output: IOUT_Bx = 0 mA, not
mode, internal RC
oscillator, PGOOD
monitoring enabled
switching
Active current
consumption during
PWM operation, one
buck regulator enabled
Single-phase output: IOUT_Bx = 0 mA
Single-phase output: IOUT_Bx = 0 mA
Dual-phase output: IOUT_Bx = 0 mA
15
30
15
mA
mA
mA
Active current
consumption during
PWM operation, two
buck regulators enabled
Active current
consumption during
PWM operation, buck
regulator enabled
Additional current consumption per LDO,
IOUT_LDOx = 0 mA
LDO regulator enabled
86
2
µA
PLL and clock detector
current consumption
fEXT_CLK = 1 MHz, Additional current
consumption when enabled
mA
DIGITAL INPUT SIGNALS EN, SCL, SDA, CLKIN
VIL
VIH
Input low level
Input high level
0.4
V
1.2
10
Hysteresis of Schmitt
Trigger inputs
VHYS
80
200
mV
EN/CLKIN pulldown
resistance
EN_PD/CLKIN_PD = 1
500
kΩ
DIGITAL OUTPUT SIGNALS nINT, SDA
nINT: ISOURCE = 2 mA
SDA: ISOURCE = 20 mA
0.4
0.4
V
V
VOL
RP
Output low level
External pullup resistor
for nINT
To VIO Supply
10
kΩ
DIGITAL OUTPUT SIGNALS PGOOD, GPO, GPO2
VOL
Output low level
ISOURCE = 2 mA
0.4
V
V
Output high level,
configured to push-pull
VVANA
–
VOH
ISINK = 2 mA
VVANA
0.4
10
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Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVIN_LDOx, VVOUT_Bx, VVOUT_LDOx
and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = VVIN_LDOx = 3.7 V, and VOUT = 1 V,
unless otherwise noted.(1)(2)
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply voltage for
VPU
external pullup resistor,
configured to open-drain
VVANA
V
External pullup resistor,
configured to open-drain
RPU
10
kΩ
ALL DIGITAL INPUTS
ILEAK
Input current
All logic inputs over pin voltage range
−1
1
µA
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6.6 I2C Serial Bus Timing Parameters
These specifications are ensured by design. Unless otherwise noted, VIN_Bx = 3.7 V. See (1) and Figure 1.
MIN
MAX
100
400
1
UNIT
Standard mode
Fast mode
kHz
fSCL
Serial clock frequency
Fast mode+
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
3.4
1.7
MHz
µs
4.7
1.3
0.5
0.16
0.32
4
Fast mode
tLOW
SCL low time
Fast mode+
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
Fast mode
0.6
0.26
0.06
0.12
250
100
50
tHIGH
SCL high time
Data setup time
Data hold time
Fast mode+
µs
ns
ns
µs
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
Fast mode
tSU;DAT
tHD;DAT
tSU;STA
Fast mode+
High-speed mode
Standard mode
10
10
3450
900
Fast mode
10
Fast mode+
10
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
10
70
10
150
4.7
0.6
0.26
0.16
4
Setup time for a start or
a repeated start
condition
Fast mode
Fast mode+
High-speed mode
Standard mode
Fast mode
0.6
0.26
0.16
4.7
1.3
0.5
4
Hold time for a start or a
repeated start condition
tHD;STA
µs
µs
µs
Fast mode+
High-speed mode
Standard mode
Bus free time between a
stop and start condition
tBUF
Fast mode
Fast mode +
Standard mode
Fast mode
0.6
0.26
0.16
Setup time for a stop
condition
tSU;STO
Fast mode+
High-speed mode
Standard mode
1000
300
120
80
Fast mode
20
trDA
Rise time of SDA signal Fast mode+
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
ns
10
20
160
(1) Cb refers to the capacitance of one bus line.
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I2C Serial Bus Timing Parameters (continued)
These specifications are ensured by design. Unless otherwise noted, VIN_Bx = 3.7 V. See (1) and Figure 1.
MIN
MAX
UNIT
Standard mode
300
20 × (VDD / 5.5
Fast mode
300
120
V)
tfDA
Fall time of SDA signal
20 × (VDD / 5.5
V)
ns
Fast mode+
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
10
30
80
160
1000
300
120
40
Fast mode
20
trCL
Rise time of SCL signal Fast mode+
High-speed mode, Cb = 100 pF
ns
ns
10
20
10
High-speed mode, Cb = 400 pF
80
Rise time of SCL signal High-speed mode, Cb = 100 pF
after a repeated start
80
trCL1
condition and after an
acknowledge bit
High-speed mode, Cb = 400 pF
20
160
Standard mode
Fast mode
300
300
20 × (VDD / 5.5
V)
tfCL
Fall time of a SCL signal
20 × (VDD / 5.5
V)
ns
Fast mode+
120
High-speed mode, Cb = 10 – 100 pF
High-speed mode, Cb = 400 pF
10
20
40
80
Capacitive load for each
bus line (SCL and SDA)
Cb
400
50
pF
ns
Pulse width of spike
suppressed (SCL and
SDA spikes that are less
then the indicated width
are suppressed)
Standard mode, fast mode, and fast mode+
High-speed mode
tSP
10
tBUF
SDA
tHD;STA
trCL
tfDA
trDA
tSP
tLOW
tfCL
SCL
tHD;STA
tSU;STA
tSU;STO
tHIGH
tHD;DAT
S
tSU;DAT
S
RS
P
START
REPEATED
START
STOP
START
Figure 1. I2C Timing
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6.7 Typical Characteristics
Unless otherwise specified: V(VIN_Bx) = V(VIN_LDOx) = V(VANA) = 3.7 V, VOUT_Bx = 1 V, VOUT_LDO = 1 V, TA = 25°C, L = 0.47 µH
(TOKO DFE252012PD-R47M), COUT_BUCK = 22 µF / phase, CPOL_BUCK = 22 µF, and COUT_LDO = 1 µF.
15
14
13
12
11
10
9
70
68
66
64
62
60
58
56
54
52
50
8
7
6
5
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
Input Voltage (V)
D101
D102
Regulators disabled
VOUT_Bx = 1 V
Load = 0 mA
Figure 2. Standby Current Consumption vs Input Voltage
Figure 3. Active State Current Consumption vs Input
Voltage, One Buck Regulator Enabled in PFM Mode (single-
phase)
24
22
20
18
16
14
12
10
8
90
87
84
81
78
75
72
69
66
63
60
6
4
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
Input Voltage (V)
D103
D422
VOUT_Bx = 1 V
Load = 0 mA
VOUT_Bx = 1 V
Load = 0 mA
Figure 5. Active State Current Consumption vs Input
Voltage, One Buck Regulator Enabled in Forced PWM Mode
(single-phase)
Figure 4. Active State Current Consumption vs Input
Voltage, Regulator Enabled in PFM Mode (dual-phase)
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Typical Characteristics (continued)
Unless otherwise specified: V(VIN_Bx) = V(VIN_LDOx) = V(VANA) = 3.7 V, VOUT_Bx = 1 V, VOUT_LDO = 1 V, TA = 25°C, L = 0.47 µH
(TOKO DFE252012PD-R47M), COUT_BUCK = 22 µF / phase, CPOL_BUCK = 22 µF, and COUT_LDO = 1 µF.
100
98
96
94
92
90
88
86
84
82
80
24
22
20
18
16
14
12
10
8
6
4
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
Input Voltage (V)
D104
D423
VOUT_LDOx = 1 V
Load = 0 mA
'
VOUT_Bx = 1 V
Load = 0 mA
Figure 7. Active State Current Consumption vs Input
Voltage, One LDO Regulator Enabled
Figure 6. Active State Current Consumption vs Input
Voltage, Regulator Enabled in Forced PWM Mode (dual-
phase)
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7 Detailed Description
7.1 Overview
The LP8733xx-Q1 is a high-efficiency, high-performance flexible power supply device with two step-down DC/DC
converter cores (Buck0 and Buck1) and two low-dropout (LDO) linear regulators (LDO0 and LDO1) for
automotive applications. The cores can be configured for a two single-phase output and dual-phase single output
configuration. Table 1 lists the output characteristics of the regulators.
Table 1. Supply Specification
OUTPUT
SUPPLY
VOUT RANGE (V)
RESOLUTION (mV)
IMAX MAXIMUM OUTPUT CURRENT (mA)
10 (0.7 V to 0.73 V)
5 (0.73 V to 1.4 V)
20 (1.4 V to 3.36 V)
Buck0 (single-phase)
Buck1 (single-phase)
Buck0/1 (dual-phase)
0.7 to 3.36
3000
10 (0.7 V to 0.73 V)
5 (0.73 V to 1.4 V)
20 (1.4 V to 3.36 V)
0.7 to 3.36
0.7 to 3.36
3000
6000
10 (0.7 V to 0.73 V)
5 (0.73 V to 1.4 V)
20 (1.4 V to 3.36 V)
LDO0
LDO1
0.8 to 3.3
0.8 to 3.3
100
100
300
300
The LP8733xx-Q1 also supports switching clock synchronization to an external clock (CLKIN pin). The nominal
frequency of the external clock can be from 1 MHz to 24 MHz with 1-MHz steps.
Additional features include:
•
•
Soft-start
Input voltage protection:
–
–
Undervoltage lockout
Overvoltage protection
•
Output voltage monitoring and protection:
–
–
–
Overvoltage monitoring
Undervoltage monitoring
Overload protection
•
•
Thermal warning
Thermal shutdown
The LP8733xx-Q1 has one dedicated general purpose digital output (GPO) signal. CLKIN pin can be
programmed as a second GPO signal (GPO2) if external clock is not needed. The output type (open-drain or
push-pull) is programmable for the GPOs.
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7.2 Functional Block Diagram
VANA
nINT
Interrupts
Buck0
ILIM Det
Pwrgood Det
Enable/
Disable,
Delay
Control
Slew-Rate
Control
Overload and
SC Det
EN
Iload ADC
GPO
Buck1
ILIM Det
Pwrgood Det
SDA
SCL
I2C
Overload and
SC Det
Iload ADC
OTP
EPROM
Registers
LDO0
PGOOD
ILIM Det
Pwrgood Det
Overload
Digital
Logic
and SC Det
Thermal
Monitor
UVLO
LDO1
ILIM Det
Pwrgood Det
Overload
SW
Reset
Ref &
Bias
Oscillator
and SC Det
CLKIN (GPO2)
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 DC/DC Converters
7.3.1.1 Overview
The LP8733xx-Q1 includes two step-down DC/DC converter cores. The cores are designed for flexibility; most of
the functions are programmable, thus giving a possibility to optimize the regulator operation for each application.
The cores can be configured either for a dual-phase single output configuration or for a single-phase dual output
configuration. The buck regulators deliver 0.7-V to 3.36-V regulated voltage rails from a 2.8-V to 5.5-V supply
voltage.
The LP8733xx-Q1 has the following features:
•
•
•
•
•
•
•
•
•
DVS support with programmable slew rate
Automatic mode control based on the loading (PFM or PWM mode)
Forced PWM mode option
Optional external clock input to minimize crosstalk
Optional spread-spectrum technique to reduce EMI
Phase control for optimized EMI
Synchronous rectification
Current mode loop with PI compensator
Soft start
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Feature Description (continued)
•
•
•
Power Good flag with maskable interrupt
Power Good signal (PGOOD) with selectable sources
Average output current sensing (for PFM entry, phase shedding/adding in dual-phase configuration, and load
current measurement)
•
•
•
Current balancing between the phases of the converter in dual-phase configuration
Differential voltage sensing from point of the load in dual-phase configuration
Dynamic phase shedding/adding, each output being phase shifted in dual-phase configuration
The following parameters can be programmed via registers, the default values are set by OTP bits:
•
•
•
•
•
•
Output voltage
Forced PWM operation
Forced dual-phase operation (forces also the PWM operation)
Switch current limit
Output voltage slew rate
Enable and disable delays
There are two modes of operation for the buck converter, depending on the output current required: pulse-width
modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load
currents of approximately 600 mA or higher. When operating in PWM mode in dual-phase configuration the
phases are automatically added/shedded based on the load current level. Lighter output current loads cause the
converter to automatically switch into PFM mode for reduced current consumption when forced PWM mode is
disabled. The forced PWM mode can be selected to maintain fixed switching frequency at all load current levels.
A block diagram of a single core is shown in Figure 8.
HS FET
CURRENT
SENSE
VIN
FB
POS
CURRENT
LIMIT
RAMP
GENERATOR
V
OUT
-
GATE
CONTROL
ERROR
AMP
SW
+
LOOP
COMP
VOLTAGE
SETTING
SLEW RATE
CONTROL
NEG
CURRENT
LIMIT
POWER
+
VDAC
-
GOOD
ZERO
CROSS
DETECT
LS FET
CURRENT
SENSE
MASTER
INTERFACE
PROGRAMMABLE
PARAMETERS
CONTROL
BLOCK
SLAVE
INTERFACE
IADC
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 8. Detailed Block Diagram Showing One Core
7.3.1.2 Dual-Phase Operation and Phase-Adding/Shedding
Under heavy load conditions, the dual-phase converter switches both channel 180° apart. As a result, the dual-
phase converter has an effective ripple frequency two times greater than the switching frequency of a single
phase. However, the parallel operation decreases the efficiency at light load conditions. In order to overcome this
operational inefficiency, the LP8733xx-Q1 can change the number of active phases to optimize efficiency for the
variations of the load. This is called phase adding/shedding. The concept is shown in Figure 9.
The converter can be forced to dual-phase operation by the BUCK0_FPWM_MP bit in BUCK0_CTRL_1 register.
If the regulator operates in forced dual-phase mode the forced PWM operation is automatically used. If the dual-
phase operation is not forced, the number of phases are added and shedded automatically to follow the required
output current.
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Feature Description (continued)
BEST EFFICIENCY OBTAINED WITH
N=1
N=2
Figure 9. Multiphase Buck Converter Efficiency vs Number of Phases. All Converters in PWM mode.
(1)
(UPDATE)
Interleaving switching action of the converters and channels in a 2-phase configuration is shown in Figure 10.
(1) Graph is not in scale and is for illustrative purposes only.
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Feature Description (continued)
IL_TOT_2PH
IL0
IL1
0
90
180
270
360
450
540
630
720
PWM0
PWM1
SWITCHING CYCLE 360º
0
90
180
270
360
450
540
630
720
PHASE, DEGREES
(2)
Figure 10. PWM Timings and Inductor Current Waveforms in 2-phase Configuration. (UPDATE)
7.3.1.3 Transition Between PWM and PFM Modes
PWM mode operation with phase-adding/shedding optimizes efficiency at mid to full load at the expense of light-
load efficiency. The LP8733xx-Q1 converter operates in PWM mode at load current of about 600 mA or higher.
At lighter load current levels the device automatically switches into PFM mode for reduced current consumption
when forced PWM mode is disabled (AUTO mode operation). By combining the PFM and the PWM modes a
high efficiency is achieved over a wide output-load current range.
7.3.1.4 Dual-Phase Switcher Configurations
The LP8733xx-Q1 device supports the following regulator configurations:
•
•
Single dual-phase configuration, Buck0 is master (buck0 and buck1)
Two single-phase configuration (buck0 and buck1)
In the dual-phase configuration the control of the dual-phase regulator settings is done using the control registers
of the master buck. The following slave registers are ignored:
•
•
•
•
•
BUCK1_CTRL_1, except EN_RDIS1 bit
BUCK1_CTRL_2, except ILIM1[2:0] bits
BUCK1_VOUT
BUCK1_DELAY
interrupt bits related to the slave buck, except BUCK1_ILIM_INT
(2) Graph is not in scale and is for illustrative purposes only.
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Feature Description (continued)
7.3.1.5 Buck Converter Load Current Measurement
Buck load current can be monitored via I2C registers. The monitored buck converter is selected with the
LOAD_CURRENT_BUCK_SELECT bit in SEL_I_LOAD register. A write to this selection register starts a current
measurement sequence. The regulator is automatically forced to PWM mode for the measurement period. The
measurement sequence is 50 µs long, maximum.
LP8733xx-Q1 can be configured to give out an interrupt (I_MEAS_INT bit in INT_TOP_1 register) after the load
current measurement sequence is finished. Load current measurement interrupt can be masked with
I_MEAS_MASK bit (TOP_MASK_1 register). The measurement result can be read from registers I_LOAD_1 and
I_LOAD_2. Register I_LOAD_1 bits BUCK_LOAD_CURRENT[7:0] give out the LSB bits and register I_LOAD_2
bit BUCK_LOAD_CURRENT[8] the MSB bit. The measurement result BUCK_LOAD_CURRENT[8:0] LSB is 20
mA, and maximum code value of the measurement corresponds to 10.22 A. In dual-phase configuration the
measured current is the total value of the master and slave phases.
7.3.1.6 Spread-Spectrum Mode
Systems with periodic switching signals may generate a large amount of switching noise in a set of narrowband
frequencies (the switching frequency and its harmonics). The usual solution to reduce noise coupling is to add
EMI-filters and shields to the boards. The LP8733xx-Q1 has register selectable spread-spectrum mode which
minimizes the need for output filters, ferrite beads, or chokes. In spread spectrum mode, the switching frequency
varies around the center frequency, reducing the EMI emissions radiated by the converter and associated
passive components and PCB traces (see Figure 11). This feature is available only when internal RC oscillator is
used (EN_PLL bit is 0 in PLL_CTRL register), and it is enabled with the EN_SPREAD_SPEC bit in CONFIG
register, and it affects both buck cores.
Frequency
Where a fixed frequency converter exhibits large amounts of spectral energy at the switching frequency, the spread
spectrum architecture of the LP8733xx-Q1 spreads that energy over a large bandwidth.
Figure 11. Spread-Spectrum Modulation
7.3.2 Sync Clock Functionality
The LP8733xx-Q1 device contains a CLKIN input to synchronize the switching clock of the buck regulators with
the external clock. The block diagram of the clocking and PLL module is shown in Figure 12. Depending on the
EN_PLL bit in PLL_CTRL register and the external clock availability, the external clock is selected and interrupt
is generated as shown in Table 2. The interrupt can be masked with SYNC_CLK_MASK bit in TOP_MASK_1
register. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[4:0] bits in PLL_CTRL
register, and it can be from 1 MHz to 24 MHz with 1-MHz steps. The external clock must be inside accuracy
limits (–30%/+10%) of the selected frequency for valid clock detection.
The SYNC_CLK_INT interrupt in INT_TOP_1 register is also generated in cases where the external clock is
expected but it is not available. These cases are start-up (read OTP-to-standby transition) when EN_PLL is 1
and Buck regulator enable (standby-to-active transition) when EN_PLL is 1.
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Feature Description (continued)
24MHz
RC
Oscillator
Internal
24MHz
clock
CLKIN
Detector
Divider
“EXT_CLK_
FREQ“
Clock Select
Logic
CLKIN
1MHz
24MHz
PLL
“EN_PLL“
1MHz
Divider
24
Figure 12. Clock and PLL Module
Table 2. PLL Operation
DEVICE
OPERATION MODE
PLL AND CLOCK
DETECTOR STATE
INTERRUPT FOR
EXTERNAL CLOCK
EN_PLL
CLOCK
STANDBY
ACTIVE
0
0
Disabled
Disabled
No
No
Internal RC
Internal RC
When external clock
appears or disappears
Automatic change to external
clock when available
STANDBY
ACTIVE
1
1
Enabled
Enabled
When external clock
appears or disappears
Automatic change to external
clock when available
7.3.3 Low-Dropout Linear Regulators (LDOs)
The LP8733xx-Q1 device includes two identical linear regulators, LDO0 and LDO1, targeting analog loads with
low noise requirements. The LDO regulators deliver 0.8-V to 3.3-V regulated voltage rails from a 2.5-V to 5.5-V
input voltage. Both regulators have dedicated inputs which can be higher or lower than the device system voltage
V(VANA) to minimize the power dissipation.
7.3.4 Power-Up
The power-up sequence for the LP8733xx-Q1 is as follows:
•
VANA (and VIN_Bx) reach minimum recommended levels (VVANA > VANAUVLO). This initiates power-on-reset
(POR), OTP reading, and enables the system I/O interface. The I2C host should allow at least 1.2 ms before
writing or reading data to the LP8733xx-Q1.
•
•
•
Device enters standby mode.
The host can change the default register setting by I2C if needed.
The regulators can be enabled/disabled and the GPO signals can be controlled by EN pin and by I2C
interface.
Transitions between the operating modes are shown in Modes of Operation.
7.3.5 Regulator Control
7.3.5.1 Enabling and Disabling Regulators
The regulators can be enabled when the device is in STANDBY or ACTIVE state. There are two ways for enable
and disable the buck regulators:
•
Using BUCKx_EN bit in BUCKx_CTRL_1 register (BUCKx_EN_PIN_CTRL bit is 0 in BUCKx_CTRL_1
register)
•
Using EN control pin (BUCKx_EN bit is 1 AND BUCKx_EN_PIN_CTRL bit is 1)
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Similarly there are two ways to enable and disable the LDO regulators:
•
•
Using LDOx_EN bit in LDOx_CTRL register (LDOx_EN_PIN_CTRL bit is 0 in LDOx_CTRL register)
Using EN control pin (LDOx_EN bit is 1 AND LDOx_EN_PIN_CTRL bit is 1)
If the EN control pin is used for enable and disable then the delay from the control signal rising edge to start-up
is set by BUCKx_STARTUP_DELAY[3:0] bits in BUCKx_DELAY register and LDOx_STARTUP_DELAY[3:0] bits
in LDOx_DELAY register and the delay from control signal falling edge to shutdown is set by
BUCKx_SHUTDOWN_DELAY[3:0] bits in BUCKx_DELAY register and LDOx_SHUTDOWN_DELAY[3:0] bits in
LDOx_DELAY register. The delays are valid only for EN signal transitions and not for control with I2C writings to
BUCKx_EN and LDOx_EN bits.
The control of the regulator (with 0-ms delays) is shown in Table 3. Dual-phase regulator is controlled with
registers of the master phase.
Table 3. Regulator Control
BUCKx_EN /
LDOx_EN
BUCKx_EN_PIN_CTRL /
LDOx_EN_PIN_CTRL
BUCKx OUTPUT VOLTAGE /
LDOx OUTPUT VOLTAGE
EN PIN
Enable/disable control with
BUCKx_EN/LDOx_EN bit
0
1
1
1
Don't Care
Don't Care
Don't Care
Low
Disabled
0
1
1
BUCKx_VSET[7:0] / LDOx_VSET[4:0]
Disabled
Enable/disable control with
EN pin
High
BUCKx_VSET[7:0] / LDOx_VSET[4:0]
The buck regulator is enabled by the EN pin or by I2C writing as shown in Figure 13. The soft-start circuit limits
the in-rush current during start-up. When the output voltage rises to a 0.35-V level, the output voltage becomes
slew-rate controlled. If there is a short circuit at the output, and the output voltage does not increase above the
0.35-V level in 1 ms or the output voltage drops below 0.35-V level during operation (for minimum of 1 ms), the
regulator is disabled, and BUCKx_SC_INT interrupt in INT_BUCK register is set. When the output voltage
reaches the Power-Good threshold level the BUCKx_PG_INT interrupt flag in INT_BUCK register is set. The
Power-Good interrupt flag when reaching valid output voltage can be masked using BUCKx_PGR_MASK bit in
BUCK_MASK register. The Power-Good interrupt flag can be also generated when the output voltage becomes
invalid. The interrupt mask for invalid output voltage detection is set by BUCKx_PGF_MASK bit in BUCK_MASK
register. A BUCKx_PG_STAT bit in BUCK_STAT register shows always the validity of the output voltage: 1
means valid and 0 means invalid output voltage. A PGOOD_WINDOW_BUCK bit in PGOOD_CTRL_1 register
sets the detection method for the valid buck output voltage, either undervoltage detection or undervoltage and
overvoltage detection.
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Voltage decrease because of load
Voltage
BUCKx_VSET[7:0]
Powergood
Ramp
BUCKx_CTRL_2(BUCKx_SLEW_RATE[2:0])
0.6V
0.35V
Time
Resistive pull-down
(if enabled)
Soft start
Enable
0
0
0
1
0
0
1
BUCK_STAT(BUCKx_STAT)
BUCK_STAT(BUCKx_PG_STAT)
INT_BUCK(BUCKx_PG_INT)
nINT
1
1
0
1
1
0
0 1
0
0
Powergood
interrupts
Host clears
interrupts
BUCK_MASK(BUCKx_PGF_MASK) = 0
BUCK_MASK(BUCKx_PGR_MASK) = 0
Figure 13. Buck Regulator Enable and Disable
The LDO regulator is enabled by the EN pin or by I2C writing as shown in Figure 14. The soft-start circuit limits
the in-rush current during start-up. Output voltage increase rate is less than 100 mV/μsec during soft-start. If
there is a short circuit at the output, and the output voltage does not increase above the 0.3-V level in 1 ms or
the output voltage drops below 0.3-V level during operation (for minimum of 1 ms), the regulator is disabled, and
LDOx_SC_INT interrupt in INT_LDO register is set. When the output voltage reaches the Power-Good threshold
level the LDOx_PG_INT interrupt flag in INT_LDO register is set. The Power-Good interrupt flag when reaching
valid output voltage can be masked using LDOx_PGR_MASK bit in LDO_MASK register. The Power-Good
interrupt flag can be also generated when the output voltage becomes invalid. The interrupt mask for invalid
output voltage detection is set by LDOx_PGF_MASK bit in LDO_MASK register. A LDOx_PG_STAT bit in
LDO_STAT register shows always the validity of the output voltage; 1 means valid, and 0 means invalid output
voltage. A PGOOD_WINDOW_LDO bit in PGOOD_CTRL_1 register sets the detection method for the valid LDO
output voltage, either undervoltage detection or undervoltage and overvoltage detection.
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Voltage decrease because of load
Voltage
LDOx_VSET[4:0]
Powergood
Resistive pull-down
(if enabled)
Time
Enable
0
0
0
1
0
0
1
LDO_STAT(LDOx_STAT)
LDO_STAT(LDOx_PG_STAT)
INT_LDO(LDOx_PG_INT)
nINT
1
0
1
1
1
0
0 1
0
0
Powergood
interrupts
Host clears
interrupts
LDO_MASK(LDOx_PGF_MASK) = 0
LDO_MASK(LDOx_PGR_MASK) = 0
Figure 14. LDO Regulator Enable and Disable
The EN input pin have an integrated pulldown resistor. The pulldown resistor is controlled with EN_PD bit in
CONFIG register.
7.3.5.2 Changing Output Voltage
The output voltage of the regulator can be changed by writing to the BUCKx_VOUT / LDOx_VOUT register. The
voltage change for buck regulator is always slew-rate controlled, and the slew-rate is defined by the
BUCKx_SLEW_RATE[2:0] bits in BUCKx_CTRL_2 register. During voltage change the forced PWM mode is
used automatically. If the dual-phase operation is forced by the BUCK0_FPWM_MP bit in BUCK0_CTRL_1
register, the regulator operates in dual-phase mode. If the dual-phase operation is not forced, the number of
phases are added and shedded automatically to follow the required slew rate. When the programmed output
voltage is achieved, the mode becomes the one defined by load current, and the BUCKx_FPWM bit in
BUCKx_CTRL_1 register and by BUCK0_FPWM_MP bit.
The voltage change and Power-Good interrupts are shown in Figure 15.
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Ramp for Buck
BUCKx_CTRL2(SLEW_RATEx[2:0])
Voltage
BUCKx_VSET /
LDOx_VSET
Powergood
Powergood
Time
BUCK_STAT(BUCKx_STAT) /
LDO_STAT(LDOx_STAT)
1
1
0
BUCK_STAT(BUCKx_PG_STAT) /
LDO_STAT(LDOx_PG_STAT)
0
1
1
0
1
1
INT_BUCK(BUCKx_PG_INT) /
INT_LDO(LDOx_PG_INT)
0
0
nINT
Powergood
interrupt
Host clears
interrupt
Powergood
interrupt
Host clears
interrupt
BUCK_MASK(BUCKx_PGF_MASK)=0
BUCK_MASK(BUCKx_PGR_MASK)=0
LDO_MASK(LDOx_PGF_MASK)=0
LDO_MASK(LDOx_PGR_MASK)=0
Figure 15. Regulator Output Voltage Change
During an LDO voltage change the internal reference for the Power-Good detection is also changed. For this
reason the Power Good may toggle during the LDO voltage change can indicate valid output even when the
output voltage is changing. This period takes less than 100 µs and after that time the Power Good gives correct
value.
7.3.6 Enable and Disable Sequences
The LP8733xx-Q1 device supports start-up and shutdown sequencing with programmable delays for different
regulator outputs using single EN control signal. The Buck regulator is selected for delayed control with:
•
•
•
•
BUCKx_EN = 1 in BUCKx_CTRL_1 register
BUCKx_EN_PIN_CTRL = 1 in BUCKx_CTRL_1 register
BUCKx_VSET[7:0] bits in BUCKx_VOUT register defines the voltage when EN pin is high
The delay from rising edge of EN pin to the regulator enable is set by BUCKx_STARTUP_DELAY[3:0] bits in
BUCKx_DELAY register and
•
The delay from falling edge of EN pin to the regulator disable is set by BUCKx_SHUTDOWN_DELAY[3:0] bits
in BUCKx_DELAY register.
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In the same way the LDO regulator is selected for delayed control with:
•
•
•
•
LDOx_EN = 1 in LDOx_CTRL register
LDOx_EN_PIN_CTRL = 1 in LDOx_CTRL register
LDOx_VSET[4:0] bits in LDOx_VOUT register defines the voltage when EN pin is high
The delay from rising edge of EN pin to the regulator enable is set by LDOx_STARTUP_DELAY[3:0] bits in
LDOx_DELAY register and
•
The delay from falling edge of EN pin to the regulator disable is set by LDOx_SHUTDOWN_DELAY[3:0] bits
in LDOx_DELAY register.
The GPO (and GPO2) digital output signals can be also controlled as a part of start-up and shutdown
sequencing with the following settings:
•
•
•
GPOx_EN = 1 in GPO_CTRL register
GPOx_EN_PIN_CTRL = 1 in GPO_CTRL register
The delay from rising edge of EN pin to the rising edge of GPO/GPO2 signal is set by
GPOx_STARTUP_DELAY[3:0] bits in GPOx_DELAY register and
•
The delay from falling edge of EN pin to the falling edge of GPO/GPO2 signal is set by
GPOx_SHUTDOWN_DELAY[3:0] bits in GPOx_DELAY register.
An example of the start-up and shutdown sequences for the buck regulators are shown in Figure 16. The start-up
and shutdown delays for the Buck0 regulator are 1 ms and 4 ms; for the Buck1 regulator start-up and shutdown
delays are 3 ms and 1 ms. The delay settings are used only for enable/disable control with EN signal.
Typical sequence
EN
EN_BUCK0
EN_BUCK1
1ms
4ms
3ms
1ms
Sequence with short EN low and high periods
EN
Startup cntr
0
0
0
1
0
1
2
3
4
5
6
0
Shutdown cntr
EN_BUCK0
EN_BUCK1
0
1
0
1
2 0
1
2
3
4
5
1ms
4ms
3ms
1ms
Figure 16. Start-Up and Shutdown Sequencing
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7.3.7 Device Reset Scenarios
There are three reset methods implemented on the LP8733xx-Q1:
•
•
Software reset with SW_RESET bit in RESET register
Undervoltage lockout (UVLO) reset from VANA supply
An SW reset occurs when SW_RESET bit is written 1. The bit is automatically cleared after writing. This event
disables all the regulators immediately, drives GPO and GPO2 signals low, resets all the register bits to the
default values and OTP bits are loaded (see Figure 22). I2C interface is not reset during software reset.
If VANA supply voltage falls below the UVLO threshold level then all the regulators are disabled immediately,
GPO and GPO2 signals are driven low, and all the register bits are reset to the default values. When the VANA
supply voltage transition above UVLO threshold level an internal POR occurs. OTP bits are loaded to the
registers and a startup is initiated according to the register settings.
7.3.8 Diagnosis and Protection Features
The LP8733xx-Q1 is capable of providing four levels of protection features:
•
•
•
•
Information of valid regulator output voltage which sets interrupt or PGOOD signal;
Warnings for diagnosis which sets interrupt;
Protection events which are disabling the regulators; and
Faults which are causing the device to shutdown.
The LP8733xx-Q1 sets the flag bits indicating what protection or warning conditions have occurred, and the nINT
pin is pulled low. nINT is released again after a clear of flags is complete. The nINT signal stays low until all the
pending interrupts are cleared.
When a fault is detected or software requested reset, it is indicated by a RESET_REG_INT interrupt flag in
INT_TOP_2 register after next start-up. If the RESET_REG_MASK is set to masked in the OTP, the interrupt is
not generated. The mask bit change with I2C does not affect, because the RESET_REG_MASK bit is loaded
from OTP during reset sequence.
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Table 4. Summary of Interrupt Signals
RECOVERY/INTERRUPT
CLEAR
EVENT
OUTCOME
INTERRUPT BIT
INTERRUPT MASK BIT
STATUS BIT
Write 1 to BUCKx_ILIM_INT bit
Interrupt is not cleared if current
limit is active
BUCK_INT
BUCKx_ILIM_INT
Buck current limit triggered
LDO current limit triggered
No effect
BUCKx_ILIM_MASK
BUCKx_ILIM_STAT
Write 1 to LDOx_ILIM_INT bit
Interrupt is not cleared if current
limit is active
LDO_INT
LDOx_ILIM_INT
No effect
LDOx_ILIM_MASK
N/A
LDOx_ILIM_STAT
N/A
Buck short circuit (VVOUT < 0.35
V at 1 ms after enable) or
overload (VVOUT decreasing
below 0.35 V during operation,
1-ms debounce)
BUCK_INT
BUCKx_SC_INT
Regulator disable
Write 1 to BUCKx_SC_INT bit
Write 1 to LDOx_SC_INT bit
LDO short circuit (VVOUT < 0.3
V at 1 ms after enable) or
overload (VVOUT decreasing
below 0.3 V during operation,
1-ms debounce)
LDO_INT
LDOx_SC_INT
Regulator disable
No effect
N/A
N/A
Write 1 to TDIE_WARN_INT bit
Interrupt is not cleared if
temperature is above thermal
warning level
Thermal warning
TDIE_WARN_INT
TDIE_WARN_MASK
TDIE_WARN_STAT
Write 1 to TDIE_SD_INT bit
Interrupt is not cleared if
temperature is above thermal
shutdown level
All regulators disabled
immediately and GPO
and GPO2 are set to low
Thermal shutdown
TDIE_SD_INT
OVP_INT
N/A
N/A
TDIE_SD_STAT
OVP_STAT
All regulators disabled
immediately and GPO
and GPO2 are set to low
Write 1 to OVP_INT bit
Interrupt is not cleared if VANA
voltage is above VANAOVP level
VANA overvoltage (VANAOVP
)
Buck power good, output
voltage becomes valid
BUCK_INT
BUCKx_PG_INT
No effect
BUCKx_PGR_MASK
BUCKx_PGF_MASK
LDOx_PGR_MASK
LDOx_PGF_MASK
PGOOD_MASK
BUCKx_PG_STAT
BUCKx_PG_STAT
LDOx_PG_STAT
LDOx_PG_STAT
PGOOD_STAT
SYNC_CLK_STAT
N/A
Write 1 to BUCKx_PG_INT bit
Write 1 to BUCKx_PG_INT bit
Write 1 to LDOx_PG_INT bit
Write 1 to LDOx_PG_INT bit
Write 1 to PGOOD_INT bit
Write 1 to SYNC_CLK_INT bit
Write 1 to I_MEAS_INT bit
Buck power good, output
voltage becomes invalid
BUCK_INT
BUCKx_PG_INT
No effect
LDO Power Good, output
voltage becomes valid
LDO_INT
LDOx_PG_INT
No effect
LDO power good, output
voltage becomes invalid
LDO_INT
LDOx_PG_INT
No effect
PGOOD pin changing from
active to inactive state(1)
No effect
PGOOD_INT
External clock appears or
disappears
No effect to regulators
No effect
SYNC_CLK_INT(2)
I_MEAS_INT
SYNC_CLK_MASK
I_MEAS_MASK
Load current measurement
ready
Immediate shutdown,
registers reset to default
values
Supply voltage VANAUVLO
triggered (VANA falling)
N/A
N/A
N/A
N/A
N/A
Startup, registers reset to
default values and OTP
bits loaded
Supply voltage VANAUVLO
triggered (VANA rising)
RESET_REG_INT
RESET_REG_MASK
Write 1 to RESET_REG_INT bit
Immediate shutdown
followed by power up,
registers reset to default
values
Software requested reset
RESET_REG_INT
RESET_REG_MASK
N/A
Write 1 to RESET_REG_INT bit
(1) PGOOD_STAT bit is 1 when the PGOOD pin shows valid voltages. PGOOD_POL bit in PGOOD_CTRL_1 register affects only PGOOD
pin polarity, not Power Good and PGOOD_INT interrupt polarity.
(2) Interrupt is generated during clock-detector operation and if clock is not available when clock detector is enabled.
7.3.8.1 Power-Good Information (PGOOD pin)
In addition to the interrupt-based indication of the current limit and the Power-Good level the LP8733xx-Q1
device supports monitoring with PGOOD signal:
•
•
•
•
Regulator output voltage,
Input supply overvoltage,
Thermal warning and
Thermal shutdown.
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Regulator output voltage monitoring (not current limit monitoring) can be selected for PGOOD indication. This
selection is individual for both buck regulators (only master buck in dual-phase configuration) and both LDO
regulators and is set by EN_PGOOD_BUCKx bits in PGOOD_CTRL_1 register and EN_PGOOD_LDOx bits in
PGOOD_CTRL_1 register. When a regulator is disabled, the monitoring is automatically masked to prevent it
forcing PGOOD inactive.
A
thermal warning can be also selected for PGOOD indication with
EN_PGOOD_TWARN bit in PGOOD_CTRL_2 register. The monitoring from all the output rails, thermal warning
(TDIE_WARN_STAT), input overvoltage interrupt (OVP_INT), and thermal shutdown interrupt (TDIE_SD_INT)
are combined, and PGOOD pin is active only if all the selected sources shows a valid status.
The type of output voltage monitoring for PGOOD signal is selected by PGOOD_WINDOW_x bits in
PGOOD_CTRL_1 register. If the bit is 0, only undervoltage is monitored; if the bit is 1, both undervoltage and
overvoltage are monitored.
The polarity and the output type (push-pull or open-drain) are selected by the PGOOD_POL and PGOOD_OD
bits in the PGOOD_CTRL_1 register.
PGOOD is only active or asserted when all enabled power resource output voltages are within specified
tolerance for each requested/programmed output voltage.
PGOOD is inactive or de-asserted if any enabled power resource output voltages is outside specified tolerance
for each requested/programmed output voltage.
The device OTP setting selects either gated (that is, unusual) or continuous (that is, invalid) mode of operation.
7.3.8.1.1 PGOOD Pin Gated mode
The gated (or unusual) mode of operation is selected by setting PGOOD_MODE bit to 0 in PGOOD_CTRL_2
register.
For the gated mode of operation, PGOOD behaves as follows:
•
•
PGOOD is set to active or asserted state upon exiting OTP configuration as an initial default state.
PGOOD status is suspended or unchanged during an 800-µs gated time period, thereby gating-off the status
indication.
•
•
•
During normal power-up sequencing and requested voltage changes, PGOOD state is not changed during an
800-µs gated time period. It typically remains active or asserted for normal conditions.
During an abnormal power-up sequencing and requested voltage changes, PGOOD status could change to
inactive or de-asserted after an 800-µs gated time period if any output voltage is outside of regulation range.
Using the gated mode of operation could allow the PGOOD signal to initiate an immediate power shutdown
sequence if the PGOOD signal is wired-OR with signal connected to EN input. This type of circuit
configuration provides a smart PORz function for processor that eliminates the need for additional
components to generate PORz upon start-up and to monitor voltage levels of key voltage domains.
The fault sets corresponding fault bit 1 in PG_FAULT register. The detected fault must be cleared to continue the
PGOOD monitoring. The overvoltage and thermal shutdown are cleared by writing 1 to the OVP_INT and
TDIE_SD_INT interrupt bits in INT_TOP_1 register. The regulator fault is cleared by writing 1 to the
corresponding register bit in PG_FAULT register. The interrupts can be also cleared with VANA UVLO by
toggling the input supply. An example of PGOOD pin operation in gated mode is shown in Figure 17.
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V(VANA)
VANA_UVLO
State
Shut
down
Read
OTP
Standby
Active
PGOOD pin
Clear fault
EN pin
4ms
Buck internal enable
VOUT (Buck1)
800us Timer
Buck1 internal powergood
LDO0 internal enable
2ms
800us Timer
VOUT (LDO0)
LDO0 internal powergood
Figure 17. PGOOD Pin Operation in Gated Mode
7.3.8.1.2 PGOOD Pin Continuous Mode
The continuous (or unvalid) mode of operation is selected by setting PGOOD_MODE bit to 1 in
PGOOD_CTRL_2 register.
For the continuous mode of operation, PGOOD behaves as follows:
•
•
•
•
PGOOD is set to active or asserted state upon exiting OTP configuration.
PGOOD is set to inactive or de-asserted as soon as regulator is enabled.
PGOOD status begins indicating output voltage regulation status immediately and continuously.
During power-up sequencing and requested voltage changes, PGOOD will toggle between inactive or de-
asserted while output voltages are outside of regulation ranges and active or asserted when inside of
regulation ranges.
The PG_FAULT register bits are latched and maintain the fault information until host clears the fault bit by writing
1 to the bit. The PGOOD signal indicates also a thermal shutdown and input overvoltage interrupts, which are
cleared by clearing the interrupt bits.
When regulator voltage is transitioning from one target voltage to another, the PGOOD signal is set inactive.
When the PGOOD signal becomes inactive, the source for the fault can be read from PG_FAULT register. If the
invalid output voltage becomes valid again the PGOOD signal becomes active. Thus the PGOOD signal shows
all the time if the monitored output voltages are valid. The block diagram for this operation is shown in Figure 18
and an example of operation is shown in Figure 19.
The PGOOD signal can be also configured so that it maintains inactive state even when the monitored outputs
are valid but there are PG_FAULT_x bits in PG_FAULT register pending clearance. This type of operation is
selected by setting PGFAULT_GATES_PGOOD bit to 1 in PGOOD_CTRL_2 register.
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EN_PGOOD
_BUCK0
Power Good
Buck0
Buck1
LDO0
LDO1
EN_PGOOD
_BUCK1
Power Good
Power Good
EN_PGOOD
_LDO0
PGOOD
Active high
EN_PGOOD
_LDO1
Power Good
EN_PGOOD
_TWARN
TDIE_WARN_STAT
TDIE_SD_INT
OVP_INT
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Figure 18. PGOOD Block Diagram (Continuous Mode)
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V(VANA)
VANA_UVLO
State
Shut
down
Read
OTP
Standby
Active
PGOOD pin
EN pin
4ms
Buck1 internal enable
VOUT (Buck1)
Buck1 internal powergood
LDO0 internal enable
2ms
VOUT (LDO0)
LDO0 internal powergood
Figure 19. PGOOD Pin Operation in Continuous Mode
7.3.8.2 Warnings for Diagnosis (Interrupt)
7.3.8.2.1 Output Power Limit
The Buck regulators have programmable output peak current limits. The limits are individually programmed for
both regulators with BUCKx_ILIM[2:0] bits in BUCKx_CTRL_2 register. The current limit settings of master and
slave regulators used for the same output voltage rail must be identical. If the load current is increased so that
the current limit is triggered, the regulator continues to regulate to the limit current level (peak current regulation).
The voltage may decrease if the load current is higher than limit current. If the current regulation continues for 20
µs, the LP8733xx-Q1 device sets the BUCKx_ILIM_INT bit in INT_BUCK register and pulls the nINT pin low. The
host processor can read BUCKx_ILIM_STAT bits in BUCK_STAT register to see if the regulator is still in peak
current regulation mode and the interrupt is cleared by writing 1 to BUCKx_ILIM_INT bit. The current limit
interrupt can be masked by setting BUCKx_ILIM_MASK bit in BUCK_MASK register to 1. The Buck overload
situation is shown in Figure 20.
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Regulator disabled
by digital
New startup if
enable is valid
Voltage
VOUTx
350mV
Resistive
pull-down
1ms
Time
Time
Current
ILIMx
20ms
0
0
1
1
0
INT_BUCK(BUCKx_ILIM_INT)
INT_BUCK(BUCKx_SC_INT)
BUCK_STAT(BUCKx_STAT)
nINT
1
0
0
1
Host clearing the interrupt by writing to flags
Figure 20. Buck Regulator Overload Situation
The LDO regulators include also current limit circuitry. If the load current is increased so that the current limit is
triggered, the regulator limits the output current to the threshold level. The voltage may decrease if the load
current is higher than the current limit. If the current regulation continues for 20 µs, the LP8733xx-Q1 device sets
the LDOx_ILIM_INT bit in INT_LDO register and pulls the nINT pin low. The host processor can read
LDOx_ILIM_STAT bits in LDO_STAT register to see if the regulator is still in current regulation mode and the
interrupt is cleared by writing 1 to LDOx_ILIM_INT bit. The current limit interrupt can be masked by setting
LDOx_ILIM_MASK bit in LDO_MASK register to 1. The LDO overload situation is shown in Figure 21.
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Regulator disabled
by digital
New startup if
enable is valid
Voltage
VOUTx
300 mV
Resistive
pull-down
1ms
Time
Time
Current
ILIMx
20ms
0
0
1
1
0
INT_LDO(LDOx_ILIM_INT)
INT_LDO(LDOx_SC_INT)
LDO_STAT(LDOx_STAT)
nINT
1
0
0
1
Host clearing the interrupt by writing to flags
Figure 21. LDO Regulator Overload Situation
7.3.8.2.2 Thermal Warning
The LP8733xx-Q1 device includes a protection feature against overtemperature by setting an interrupt for host
processor. The threshold level of the thermal warning is selected with TDIE_WARN_LEVEL bit in CONFIG
register.
If the LP8733xx-Q1 device temperature increases above thermal warning level the device sets TDIE_WARN_INT
bit in INT_TOP_1 register and pulls the nINT pin low. The status of the thermal warning can be read from
TDIE_WARN_STAT bit in TOP_STAT register, and the interrupt is cleared by writing 1 to TDIE_WARN_INT bit.
The thermal warning interrupt can be masked by setting TDIE_WARN_MASK bit in TOP_MASK_1 register to 1.
7.3.8.3 Protection (Regulator Disable)
If the regulator is disabled because of protection or fault (short-circuit protection, overload protection, thermal
shutdown, input overvoltage protection, or UVLO), the output power FETs are set to high-impedance mode, and
the output pulldown resistor is enabled (if enabled with BUCKx_RDIS_EN bit in BUCKx_CTRL_1 register and
LDOx_RDIS_EN bit in LDOx_CTRL register). The turnoff time of the output voltage is defined by the output
capacitance, load current, and the resistance of the integrated pull-down resistor. The pulldown resistors are
active as long as VANA voltage is above approximately a 1.2-V level.
7.3.8.3.1 Short-Circuit and Overload Protection
A short-circuit protection feature allows the LP8733xx-Q1 to protect itself and external components against short
circuit at the output or against overload during start-up. For buck and LDO regulators the fault thresholds are
about 350 mV (buck) and 300 mV (LDO), and the protection is triggered and the regulator is disabled if the
output voltage is below the threshold level 1 ms after the regulator is enabled.
In a similar way the overload situation is protected during normal operation. If the output voltage falls below 0.35
V and 0.3 V and remains below the threshold level for 1 ms the regulator is disabled.
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In buck regulator short-circuit and overload situations the BUCKx_SC_INT bit in INT_BUCK register and the
INT_BUCKx bit in INT_TOP_1 register are set to 1, the BUCKx_STAT bit in BUCK_STAT register is set to 0, and
the nINT signal is pulled low. In LDO regulator short-circuit and overload situations the LDOx_SC_INT bit in
INT_LDO register and the INT_LDOx bit in INT_TOP_1 register are set to 1, the LDOx_STAT bit in LDO_STAT
register is set to 0, and the nINT signal is pulled low. The host processor clears the interrupt by writing 1 to the
BUCKx_SC_INT or to the LDOx_SC_INT bit. Upon clearing the interrupt the regulator makes a new start-up
attempt if the regulator is in an enabled state.
7.3.8.3.2 Overvoltage Protection
The LP8733xx-Q1 device monitors the input voltage from the VANA pin in standby and active operation modes.
If the input voltage rises above VANAOVP voltage level, all the regulators are disabled immediately (without
switching ramp, no shutdown delays), pulldown resistors discharge the output voltages if they are enabled
(BUCKx_RDIS_EN = 1 in BUCKx_CTRL_1 register and LDOx_RDIS_EN = 1 in LDOx_CTRL register), GPOs are
set to logic low level, nINT signal is pulled low, OVP_INT bit in INT_TOP_1 register is set to 1, and
BUCKx_STAT bit in BUCK_STAT register and LDOx_STAT bit in LDO_STAT register are set to 0. The host
processor clears the interrupt by writing 1 to the OVP_INT bit. If the input voltage is above overvoltage detection
level the interrupt is not cleared. The host can read the status of the overvoltage from the OVP_STAT bit in
TOP_STAT register. Regulators cannot be enabled as long as the input voltage is above overvoltage detection
level or the overvoltage interrupt is pending.
7.3.8.3.3 Thermal Shutdown
The LP8733xx-Q1 has an overtemperature protection function that operates to protect itself from short-term
misuse and overload conditions. When the junction temperature exceeds around 150°C, the regulators are
disabled immediately (without switching ramp, no shutdown delays), the TDIE_SD_INT bit in INT_TOP_1 register
is set to 1, the nINT signal is pulled low, and the device enters STANDBY. nINT is cleared by writing 1 to the
TDIE_SD_INT bit. If the temperature is above thermal shutdown level the interrupt is not cleared. The host can
read the status of the thermal shutdown from the TDIE_SD_STAT bit in TOP_STAT register. Regulators cannot
be enabled as long as the junction temperature is above thermal shutdown level or the thermal shutdown
interrupt is pending.
7.3.8.4 Fault (Power Down)
7.3.8.4.1 Undervoltage Lockout
When the input voltage falls below VANAUVLO at the VANA pin, the buck and LDO regulators are disabled
immediately (without switching ramp, no shutdown delays), and the output capacitor is discharged using the
pulldown resistor, and the LP8733xx-Q1 device enters SHUTDOWN. When V(VANA) voltage is above VANAUVLO
threshold level, the device powers up to STANDBY state.
If the reset interrupt is unmasked by default (OTP bit for RESET_REG_MASK is 0 in TOP_MASK_2 register) the
RESET_REG_INT interrupt bit in INT_TOP_2 register indicates that the device has been in SHUTDOWN. The
host processor must clear the interrupt by writing 1 to the RESET_REG_INT bit. If the host processor reads the
RESET_REG_INT interrupt bit after detecting an nINT low signal, it knows that the input supply voltage has been
below VANAUVLO level (or the host has requested reset with SW_RESET bit in RESET register), and the
registers are reset to default values.
7.3.9 Operation of the GPO Signals
The LP8733xx-Q1 device supports up to 2 general purpose output signals, GPO and GPO2. The GPO2 signal is
multiplexed with CLKIN signal. The selection between CLKIN and GPO2 pin function is set with CLKIN_PIN_SEL
bit in CONFIG register.
The GPO pins are configured with the following bits:
•
GPOx_OD bit in GPO_CTRL register defines the type of the output, either push-pull with V(VANA) level or open
drain
The logic level of the GPOx pin is set by EN_GPOx bit in GPO_CTRL register.
The control of the GPOs can be included to start-up and shutdown sequences. The GPO control for a sequence
with EN pin is selected by GPOx_EN_PIN_CTRL bit in GPO_CTRL register. For start-up and shutdown
sequence control see Enable and Disable Sequences.
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7.3.10 Digital Signal Filtering
The digital signals have a debounce filtering. The signal or supply is sampled with a clock signal and a counter.
This results as an accuracy of one clock period for the debounce window.
Table 5. Digital Signal Filtering
RISING EDGE
LENGTH
FALLING EDGE
LENGTH
EVENT
SIGNAL/SUPPLY
Enable/disable for BUCKx,
LDOx or GPOx
EN
3 µs(1)
3 µs(1)
VANA UVLO
VANA
VANA
3 µs(1) (VANA voltage rising)
Immediate (VANA voltage falling)
VANA overvoltage
Thermal warning
Thermal shutdown
Current limit
1 µs (VANA voltage rising)
20 µs (VANA voltage falling)
TDIE_WARN_INT
TDIE_SD_INT
VOUTx_ILIM
20 µs
20 µs
20 µs
20 µs
20 µs
20 µs
FB_B0, FB_B1,
VOUT_LDO0, VOUT_LDO1
Overload
1 ms
6 µs
N/V
PGOOD pin and power-good
interrupt
PGOOD / FB_B0, FB_B1,
VOUT_LDO0, VOUT_LDO1
6 µs
(1) No glitch filtering, only synchronization.
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7.4 Device Functional Modes
7.4.1 Modes of Operation
SHUTDOWN: The V(VANA) voltage is below VANAUVLO threshold level. All switch, reference, control, and bias
circuitry of the LP8733xx-Q1 device are turned off.
READ OTP: The main supply voltage V(VANA) is above VANAUVLO level. The regulators are disabled, and the
reference and bias circuitry of the LP8733xx-Q1 are enabled. The OTP bits are loaded to registers.
STANDBY: The main supply voltage V(VANA) is above VANAUVLO level. The regulators are disabled, and the
reference, control and bias circuitry of the LP8733xx-Q1 are enabled. All registers can be read or
written by the host processor via the system serial interface. The regulators can be enabled if
needed.
ACTIVE:
The main supply voltage V(VANA) is above VANAUVLO level. At least one regulator is enabled. All
registers can be read or written by the host processor via the system serial interface.
The operating modes and transitions between the modes are shown in Figure 22.
SHUTDOWN
V(
< VANAUVLO
VANA)
V(
> VANAUVLO
FROM ANY STATE
VANA)
EXCEPT SHUTDOWN
READ
OTP
REG
RESET
STANDBY
2
I C RESET
REGULATOR
ENABLED
REGULATOR(S)
DISABLED
ACTIVE
Figure 22. Device Operation Modes
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7.5 Programming
7.5.1 I2C-Compatible Interface
The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on
the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected
to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). Every device on
the bus is assigned a unique address and acts as either a master or a slave depending on whether it generates
or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor placed on the line and
remain HIGH even when the bus is idle. The LP8733xx-Q1 supports standard mode (100 kHz), fast mode (400
kHz), fast mode plus (1 MHz), and high-speed mode (3.4 MHz).
7.5.1.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the
state of the data line can only be changed when clock signal is LOW.
SCL
SDA
data
change
allowed
data
change
allowed
data
change
allowed
data
valid
data
valid
Figure 23. Data Validity Diagram
7.5.1.2 Start and Stop Conditions
The LP8733xx-Q1 is controlled via an I2C-compatible interface. START and STOP conditions classify the
beginning and end of the I2C session. A START condition is defined as SDA transitions from HIGH to LOW while
SCL is HIGH. A STOP condition is defined as SDA transition from LOW to HIGH while SCL is HIGH. The I2C
master always generates the START and STOP conditions.
SDA
SCL
S
P
START
STOP
Condition
Condition
Figure 24. Start and Stop Sequences
The I2C bus is considered busy after a START condition and free after a STOP condition. During data
transmission the I2C master can generate repeated START conditions. A START and a repeated START
condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock
signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 25 shows the
SDA and SCL signal timing for the I2C-compatible bus. See the Figure 1 for timing values.
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Programming (continued)
tBUF
SDA
tHD;STA
trCL
tfDA
trDA
tSP
tLOW
tfCL
SCL
tHD;STA
tSU;STA
tSU;STO
tHIGH
tHD;DAT
S
tSU;DAT
S
RS
P
START
REPEATED
START
STOP
START
Figure 25. I2C-Compatible Timing
7.5.1.3 Transferring Data
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP8733xx-Q1
pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP8733xx-Q1 generates an
acknowledge after each byte has been received.
There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must
indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out
of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),
but the SDA line is not pulled down.
NOTE
If the V(VANA) voltage is below VANAUVLO threshold level during I2C communication the
LP8733xx-Q1 device does not drive SDA line. The ACK signal and data transfer to the
master is disabled at that time.
After the START condition, the bus master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE, and a 1
indicates a READ. The second byte selects the register to which the data will be written. The third byte contains
data to write to the selected register.
ACK from slave
ACK from slave
ACK from slave
START MSB Chip Address LSB
W
ACK MSB Register Address LSB ACK
MSB Data LSB
ACK STOP
SCL
SDA
START
id = 0x60
W
ACK
address = 0x40
ACK
address 0x40 data
ACK STOP
Figure 26. Write Cycle (w = write; SDA = 0). Example Device Address = 0x60
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Programming (continued)
ACK from slave
ACK from slave REPEATED START
ACK from slave Data from slave NACK from master
START MSB Chip Address LSB
W
MSB Register Address LSB
RS
MSB Chip Address LSB
R
MSB Data LSB
STOP
SCL
SDA
START
ACK
ACK
ACK
NACK
STOP
id = 0x60
W
address = 0x3F
RS
id = 0x60
R
address 0x3F data
When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.
Figure 27. Read Cycle (r = read; SDA = 1). Example Device Address = 0x60
7.5.1.4 I2C-Compatible Chip Address
After the START condition, the I2C master sends the 7-bit address followed by an eighth bit, read or write (R/W).
R/W = 0 indicates a WRITE and R/W = 1 indicates a READ. The second byte following the device address
selects the register address to which the data is written. The third byte contains the data for the selected register.
MSB
LSB
1
Bit 7
1
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
R/W
Bit 0
I2C Slave Address (chip address)
Here in an example with device address of 1100000Bin = 60Hex.
Figure 28. Device Address Example
7.5.1.5 Auto-Increment Feature
The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8-
bit word is sent to the LP8733xx-Q1, the internal address index counter is incremented by one and the next
register is written. Table 6 shows writing sequence to two consecutive registers. Note that auto-increment feature
does not work for read.
Table 6. Auto-Increment Example
DEVICE
ADDRES WRITE
S = X
MASTER
ACTION
REGISTER
ADDRESS
START
DATA
DATA
STOP
LP8733x
x-Q1
ACK
ACK
ACK
ACK
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7.6 Register Maps
7.6.1 Register Descriptions
The LP8733xx-Q1 is controlled by a set of registers through the I2C-compatible interface. The device registers,
their addresses and their abbreviations are listed in Table 7. A more detailed description is given in the
DEV_REV to I_LOAD_1 sections.
NOTE
This register map describes the default values for bits that are not read from OTP
memory. The orderable code and the default register bit values are defined in part-number
specific Technical Reference Manuals.
Table 7. Summary of LP8733xx-Q1 Control Registers
Read /
Write
Addr
Register
D7
D6
D5
D4
D3
D2
D1
D0
0x00
0x01
DEV_REV
OTP_REV
R
DEVICE_ID[1:0]
Reserved
R
OTP_ID[7:0]
BUCK0_
EN_PIN_CT BUCK0_EN
RL
BUCK0_
CTRL_1
BUCK0_FP BUCK0_FP BUCK0_RDI
0x02
0x03
0x04
R/W
R/W
R/W
Reserved
WM_MP
WM
S_EN
BUCK0_
CTRL_2
Reserved
BUCK0_ILIM[2:0]
BUCK0_SLEW_RATE[2:0]
BUCK1_
EN_PIN_CT BUCK1_EN
RL
BUCK1_
CTRL_1
BUCK1_FP BUCK1_RDI
Reserved
WM
S_EN
BUCK1_
CTRL_2
0x05
0x06
0x07
R/W
R/W
R/W
Reserved
BUCK1_ILIM[2:0]
BUCK1_SLEW_RATE[2:0]
BUCK0_
VOUT
BUCK0_VSET[7:0]
BUCK1_VSET[7:0]
BUCK1_
VOUT
LDO0_
EN_PIN_CT
RL
LDO0_
CTRL
LDO0_RDIS
_EN
0x08
0x09
R/W
R/W
Reserved
Reserved
LDO0_EN
LDO1_EN
LDO1_
EN_PIN_CT
RL
LDO1_
CTRL
LDO1_RDIS
_EN
LDO0_
VOUT
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
Reserved
LDO0_VSET[4:0]
LDO1_VSET[4:0]
LDO1_
VOUT
BUCK0_
DELAY
BUCK0_SHUTDOWN_DELAY[3:0]
BUCK1_SHUTDOWN_DELAY[3:0]
LDO0_SHUTDOWN_DELAY[3:0]
LDO1_SHUTDOWN_DELAY[3:0]
GPO_SHUTDOWN_DELAY[3:0]
BUCK0_STARTUP_DELAY[3:0]
BUCK1_STARTUP_DELAY[3:0]
LDO0_STARTUP_DELAY[3:0]
LDO1_STARTUP_DELAY[3:0]
GPO_STARTUP_DELAY[3:0]
BUCK1_
DELAY
LDO0_
DELAY
LDO1_
DELAY
GPO_
DELAY
GPO2_
DELAY
GPO2_SHUTDOWN_DELAY[3:0]
GPO2_
GPO2_STARTUP_DELAY[3:0]
GPO_
GPO_
CTRL
0x12
R/W
Reserved
GPO2_OD EN_PIN_CT GPO2_EN
RL
Reserved
GPO_OD
EN_PIN_CT
RL
GPO_EN
STARTUP_ SHUTDOW
CLKIN_PIN
TDIE
_WARN
_LEVEL
EN_
SPREAD
_SPEC
0x13
0x14
CONFIG
R/W
R/W
Reserved
Reserved
DELAY_SE N_DELAY_
_SEL
CLKIN_PD
EN_PD
L
SEL
PLL_CTRL
EN_PLL
Reserved
EXT_CLK_FREQ[4:0]
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Register Maps (continued)
Table 7. Summary of LP8733xx-Q1 Control Registers (continued)
Read /
Write
Addr
Register
D7
D6
D5
D4
D3
D2
D1
D0
PGOOD_WI PGOOD_WI
PGOOD_CT
RL_1
PGOOD_P
OL
PGOOD_O
D
EN_PGOOD EN_PGOOD EN_PGOOD EN_PGOOD
0x15
R/W
R/W
NDOW_LD
O
NDOW_BU
CK
_LDO1
_LDO0
_BUCK1
_BUCK0
PG_FAULT
_GATES_P
GOOD
PGOOD_CT
RL_2
EN_PGOOD
_TWARN
PGOOD_M
ODE
0x16
Reserved
PG_FAULT PG_FAULT PG_FAULT PG_FAULT
0x17
0x18
0x19
0x1A
0x1B
0x1C
PG_FAULT
RESET
R
Reserved
_LDO1
_LDO0
_BUCK1
_BUCK0
SW_
RESET
R/W
R/W
R/W
R/W
R/W
Reserved
PGOOD_
INT
INT_
LDO
INT_
SYNC_
CLK_INT
TDIE_SD_I
NT
TDIE_
WARN_INT
I_MEAS_
INT
INT_TOP_1
INT_TOP_2
INT_BUCK
INT_LDO
OVP_INT
BUCK
RESET_
REG_INT
Reserved
BUCK1_
PG_INT
BUCK1_
SC_INT
BUCK1_
ILIM_INT
BUCK0_
PG_INT
BUCK0_
SC_INT
BUCK0_
ILIM_INT
Reserved
Reserved
Reserved
Reserved
LDO1_
LDO1_
LDO1_
ILIM_INT
LDO0_
PG_INT
LDO0_
SC_INT
LDO0_
ILIM_INT
PG_INT
SC_INT
TDIE_
WARN_
STAT
TOP_
STAT
PGOOD_ST
AT
SYNC_CLK
_STAT
TDIE_SD
_STAT
OVP_
STAT
0x1D
R
Reserved
Reserved
BUCK_STA
T
BUCK1_
STAT
BUCK1_
PG_STAT
BUCK1_
ILIM_STAT
BUCK0_
STAT
BUCK0_
PG_STAT
BUCK0_
ILIM_STAT
0x1E
0x1F
0x20
0x21
R
Reserved
Reserved
Reserved
Reserved
Reserved
LDO1_
STAT
LDO1_
PG_STAT
LDO1_
ILIM_STAT
LDO0_
STAT
LDO0_
PG_STAT
LDO0_
ILIM_STAT
LDO_STAT
R
TOP_
MASK_1
PGOOD_
INT_MASK
SYNC_CLK
_MASK
TDIE_WAR
N_MASK
I_MEAS_
MASK
R/W
R/W
Reserved
Reserved
TOP_
MASK_2
RESET_
REG_MASK
Reserved
BUCK1_
ILIM_
MASK
BUCK0_
ILIM_
MASK
BUCK_MAS
K
BUCK1_PG BUCK1_PG
F_MASK R_MASK
BUCK0_PG BUCK0_PG
F_MASK R_MASK
0x22
0x23
R/W
R/W
Reserved
Reserved
Reserved
Reserved
LDO1_
ILIM_
MASK
LDO0_
ILIM_
MASK
LDO1_PGF LDO1_PGR
_MASK _MASK
LDO0_PGF LDO0_PGR
_MASK _MASK
LDO_MASK
LOAD_CUR
RENT_
BUCK_SEL
ECT
SEL_I_
LOAD
0x24
R/W
Reserved
Reserved
BUCK_LOA
D_CURREN
T[8]
0x25
0x26
I_LOAD_2
I_LOAD_1
R
R
BUCK_LOAD_CURRENT[7:0]
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7.6.1.1 DEV_REV
Address: 0x00
D7
D6
D5
D4
D3
D2
D1
D0
DEVICE_ID[1:0]
Reserved
Bits
7:6
Field
Type
R
Default
X
Description
DEVICE_ID[1:0]
Reserved
Device specific ID code.
5:0
R
00 0010
7.6.1.2 OTP_REV
Address: 0x01
D7
D6
D5
D4
D3
D2
D1
D0
OTP_ID[7:0]
Bits
Field
Type
Default
Description
7:0
OTP_ID[7:0]
R
X
Identification Code of the OTP EPROM Version.
7.6.1.3 BUCK0_CTRL_1
Address: 0x02
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK0_FPWM BUCK0_FPWM BUCK0_RDIS_ BUCK0_EN_PI
BUCK0_EN
_MP
EN
N_CTRL
Bits
7:5
4
Field
Reserved
Type
R/W
R/W
Default
000
Description
BUCK0_FPWM
_MP
X
Forces the Buck0 regulator to operate always in multi-phase and forced PWM
operation mode:
0 - Automatic phase adding and shedding.
1 - Forced to multi-phase operation, 2 phases in the 2-phase configuration.
3
2
1
0
BUCK0_FPWM
R/W
R/W
R/W
R/W
X
1
Buck0 mode selection:
0 - Automatic transitions between PFM and PWM modes (AUTO mode)
1 - Forced to PWM operation.
BUCK0_RDIS_EN
Enable output discharge resistor (RDIS_Bx) when Buck0 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled.
BUCK0_EN_PIN
_CTRL
X
X
Enable control for Buck0:
0 - only BUCK0_EN bit controls Buck0
1 - BUCK0_EN bit AND EN pin control Buck0.
BUCK0_EN
Enable Buck0 regulator:
0 - Buck0 regulator is disabled
1 - Buck0 regulator is enabled.
7.6.1.4 BUCK0_CTRL_2
Address: 0x03
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK0_ILIM[2:0]
BUCK0_SLEW_RATE[2:0]
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Bits
Field
Type
R/W
R/W
Default
Description
7:6
Reserved
00
X
5:3
BUCK0_ILIM[2:0]
Sets the switch current limit of Buck0. Can be programmed at any time during
operation:
0x0 - 1.5 A
0x1 - 2.0 A
0x2 - 2.5 A
0x3 - 3.0 A
0x4 - 3.5 A
0x5 - 4.0 A
0x6 - Reserved
0x7 - Reserved
2:0 BUCK0_SLEW_RA
TE[2:0]
R/W
X
Sets the output voltage slew rate for Buck0 regulator (rising and falling edges):
0x0 - Reserved
0x1 - Reserved
0x2 - 10 mV/µs
0x3 - 7.5 mV/µs
0x4 - 3.8 mV/µs
0x5 - 1.9 mV/µs
0x6 - 0.94 mV/µs
0x7 - 0.47 mV/µs
7.6.1.5 BUCK1_CTRL_1
Address: 0x04
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK1_FPWM BUCK1_RDIS_ BUCK1_EN_PI
BUCK1_EN
EN
N_CTRL
Bits
7:4
3
Field
Type
R/W
R/W
Default
0000
X
Description
Reserved
BUCK1_FPWM
Buck1 mode selection:
0 - Automatic transitions between PFM and PWM modes (AUTO mode)
1 - Forced to PWM operation.
2
1
0
BUCK1_RDIS_EN
R/W
R/W
R/W
1
X
X
Enable output discharge resistor (RDIS_Bx) when Buck1 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled.
BUCK1_EN_PIN
_CTRL
Enable control for Buck1:
0 - only BUCK1_EN bit controls Buck1
1 - BUCK1_EN bit AND EN pin control Buck1.
BUCK1_EN
Enable Buck1 regulator:
0 - Buck1 regulator is disabled
1 - Buck1 regulator is enabled.
7.6.1.6 BUCK1_CTRL_2
Address: 0x05
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK1_ILIM[2:0]
BUCK1_SLEW_RATE[2:0]
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Bits
7:6
Field
Type
R/W
R/W
Default
Description
Reserved
00
X
5:3
BUCK1_ILIM[2:0]
Sets the switch current limit of Buck1. Can be programmed at any time during
operation:
0x0 - 1.5 A
0x1 - 2.0 A
0x2 - 2.5 A
0x3 - 3.0 A
0x4 - 3.5 A
0x5 - 4.0 A
0x6 - Reserved
0x7 - Reserved
2:0 BUCK1_SLEW_RA
TE[2:0]
R/W
X
Sets the output voltage slew rate for Buck1 regulator (rising and falling edges):
0x0 - Reserved
0x1 - Reserved
0x2 - 10 mV/µs
0x3 - 7.5 mV/µs
0x4 - 3.8 mV/µs
0x5 - 1.9 mV/µs
0x6 - 0.94 mV/µs
0x7 - 0.47 mV/µs
7.6.1.7 BUCK0_VOUT
Address: 0x06
D7
D6
D5
D4
D3
D2
D1
D0
BUCK0_VSET[7:0]
Bits
Field
Type
Default
Description
7:0 BUCK0_VSET[7:0]
R/W
X
Sets the output voltage of Buck0 regulator
Reserved, DO NOT USE
0x00 ... 0x13
0.7 V - 0.73 V, 10 mV steps
0x14 - 0.7V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
7.6.1.8 BUCK1_VOUT
Address: 0x07
D7
D6
D5
D4
D3
D2
D1
D0
BUCK1_VSET[7:0]
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Bits
SNVSB64 –SEPTEMBER 2018
Field
Type
Default
Description
Sets the output voltage of Buck0 regulator
7:0 BUCK1_VSET[7:0]
R/W
X
Reserved, DO NOT USE
0x00 ... 0x13
0.7 V - 0.73 V, 10 mV steps
0x14 - 0.7V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
7.6.1.9 LDO0_CTRL
Address: 0x08
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
LDO0_RDIS_E LDO0_EN_PIN
LDO0_EN
N
_CTRL
Bits
7:3
2
Field
Type
R/W
R/W
Default
0 0000
1
Description
Reserved
LDO0_RDIS_EN
Enable output discharge resistor (RDIS_LDOx) when LDO0 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled.
1
0
LDO0_EN_PIN
_CTRL
R/W
R/W
X
X
Enable control for LDO0:
0 - only LDO0_EN bit controls LDO0
1 - LDO0_EN bit AND EN pin control LDO0.
LDO0_EN
Enable LDO0 regulator:
0 - LDO0 regulator is disabled
1 - LDO0 regulator is enabled.
7.6.1.10 LDO1_CTRL
Address: 0x09
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
LDO1_RDIS_E LDO1_EN_PIN
LDO1_EN
N
_CTRL
Bits
7:3
2
Field
Type
R/W
R/W
Default
0 0000
1
Description
Reserved
LDO1_RDIS_EN
Enable output discharge resistor (RDIS_LDOx) when LDO1 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled.
1
0
LDO1_EN_PIN
_CTRL
R/W
R/W
X
X
Enable control for LDO1:
0 - only LDO1_EN bit controls LDO1
1 - LDO1_EN bit AND EN pin control LDO1.
LDO1_EN
Enable LDO1 regulator:
0 - LDO1 regulator is disabled
1 - LDO1 regulator is enabled.
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7.6.1.11 LDO0_VOUT
Address: 0x0A
D7
D6
D5
D4
D3
D2
D1
D1
D1
D0
Reserved
LDO0_VSET[4:0]
Bits
7:5
Field
Reserved
LDO0_VSET[4:0]
Type
R/W
R/W
Default
000
Description
4:0
X
Sets the output voltage of LDO0 regulator
0.8 V - 3.3 V, 100 mV steps
0x00 - 0.8V
...
0x19 - 3.3 V
Reserved, DO NOT USE
0x1A ... 0x1F
7.6.1.12 LDO1_VOUT
Address: 0x0B
D7
D6
D5
D4
D3
D2
D0
Reserved
LDO1_VSET[4:0]
Bits
7:5
Field
Reserved
LDO1_VSET[4:0]
Type
R/W
R/W
Default
000
Description
4:0
X
Sets the output voltage of LDO1 regulator
0.8 V - 3.3 V, 100 mV steps
0x00 - 0.8V
...
0x19 - 3.3 V
Reserved, DO NOT USE
0x1A ... 0x1F
7.6.1.13 BUCK0_DELAY
Address: 0x0C
D7
D6
D5
D4
D3
D2
D0
BUCK0_SHUTDOWN_DELAY[3:0]
BUCK0_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
Description
7:4
BUCK0_
SHUTDOWN_
DELAY[3:0]
R/W
X
Shutdown delay of Buck0 from falling edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
3:0
BUCK0_
STARTUP_
DELAY[3:0]
R/W
X
Startup delay of Buck0 from rising edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
7.6.1.14 BUCK1_DELAY
Address: 0x0D
D7
D6
D5
D4
D3
D2
D1
D0
BUCK1_SHUTDOWN_DELAY[3:0]
BUCK1_STARTUP_DELAY[3:0]
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Bits
Field
Type
Default
Description
7:4
BUCK1_
SHUTDOWN_
DELAY[3:0]
R/W
X
Shutdown delay of Buck1 from falling edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
3:0
BUCK1_
STARTUP_
DELAY[3:0]
R/W
X
Startup delay of Buck1 from rising edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
7.6.1.15 LDO0_DELAY
Address: 0x0E
D7
D6
D5
D4
D3
D2
D1
D0
D0
D0
LDO0_SHUTDOWN_DELAY[3:0]
LDO0_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
Description
7:4
LDO0_
R/W
X
Shutdown delay of LDO0 from falling edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
SHUTDOWN_
DELAY[3:0]
...
0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
3:0
LDO0_
STARTUP_
DELAY[3:0]
R/W
X
Startup delay of LDO0 from rising edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
7.6.1.16 LDO1_DELAY
Address: 0x0F
D7
D6
D5
D4
D3
D2
D1
LDO1_SHUTDOWN_DELAY[3:0]
LDO1_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
Description
7:4
LDO1_
R/W
X
Shutdown delay of LDO1 from falling edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
SHUTDOWN_
DELAY[3:0]
...
0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
3:0
LDO1_
STARTUP_
DELAY[3:0]
R/W
X
Startup delay of LDO1 from rising edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
7.6.1.17 GPO_DELAY
Address: 0x10
D7
D6
D5
D4
D3
D2
D1
GPO_SHUTDOWN_DELAY[3:0]
GPO_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
Description
7:4
GPO_
R/W
X
Delay for GPO falling edge from falling edge of EN signal:
SHUTDOWN_
DELAY[3:0]
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
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Bits
Field
Type
Default
Description
3:0
GPO_
R/W
X
Delay for GPO rising edge from rising edge of EN signal:
STARTUP_
DELAY[3:0]
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
7.6.1.18 GPO2_DELAY
Address: 0x11
D7
D6
D5
D4
D3
D2
D1
D0
GPO2_SHUTDOWN_DELAY[3:0]
GPO2_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
Description
7:4
GPO2_
R/W
X
Delay for GPO2 falling edge from falling edge of EN signal:
SHUTDOWN_
DELAY[3:0]
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
3:0
GPO2_
R/W
X
Delay for GPO2 rising edge from rising edge of EN signal:
STARTUP_
DELAY[3:0]
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
7.6.1.19 GPO_CTRL
Address: 0x12
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
GPO2_OD
GPO2_EN_PIN
_CTRL
GPO2_EN
Reserved
GPO_OD
GPO_EN_PIN_
CTRL
GPO_EN
Bits
Field
Type
Default
Description
7
6
Reserved
GP02_OD
R
0
R/W
X
GPO2 signal type when configured as General Purpose Output (CLKIN pin):
0 - Push-pull output (VANA level)
1 - Open-drain output
5
4
GPO2_EN_PIN_C
TRL
R/W
R/W
X
X
Control for GPO2:
0 - Only GPO2_EN bit controls GPO2
1 - GPO2_EN bit AND EN pin control GPO2.
GPO2_EN
Output level of GPO2 signal (when configured as General Purpose Output):
0 - Logic low level
1 - Logic high level
3
2
Reserved
GPO_OD
R
0
R/W
X
GPO signal type:
0 - Push-pull output (VANA level)
1 - Open-drain output
1
0
GPO_EN_PIN_CT
RL
R/W
R/W
X
X
Control for GPO:
0 - Only GPO_EN bit controls GPO
1 - GPO_EN bit AND EN pin control GPO.
GPO_EN
Output level of GPO signal:
0 - Logic low level
1 - Logic high level
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7.6.1.20 CONFIG
Address: 0x13
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
STARTUP_DE SHUTDOWN_ CLKIN_PIN_SE
CLKIN_PD
EN2_PD
TDIE_WARN_
LEVEL
EN_SPREAD
_SPEC
LAY_SEL
DELAY_SEL
L
Bits
Field
Type
R/W
R/W
Default
Description
7
6
Reserved
0
STARTUP_DELAY
_SEL
X
Startup delay range from EN signals.
0 - 0 ms - 7.5 ms with 0.5 ms steps
1 - 0 ms - 15 ms with 1 ms steps
5
4
3
SHUTDOWN_DEL
AY_SEL
R/W
R/W
R/W
X
X
X
Shutdown delay range from EN signals.
0 - 0 ms - 7.5 ms with 0.5 ms steps
1 - 0 ms - 15 ms with 1 ms steps
CLKIN_PIN_SEL
CLKIN_PD
CLKIN pin function:
0 - GPO2
1 - CLKIN
Selects the pull down resistor on the CLKIN input pin. (valid also when selected as
GPO2)
0 - Pull-down resistor is disabled.
1 - Pull-down resistor is enabled.
2
1
0
EN_PD
R/W
R/W
R/W
X
X
X
Selects the pull down resistor on the EN input pin.
0 - Pull-down resistor is disabled.
1 - Pull-down resistor is enabled.
TDIE_WARN_
LEVEL
Thermal warning threshold level.
0 - 125°C
1 - 137°C.
EN_SPREAD
_SPEC
Enable spread spectrum feature:
0 - Disabled
1 - Enabled
7.6.1.21 PLL_CTRL
Address: 0x14
D7
D6
EN_PLL
D5
D4
D3
D2
D1
D0
Reserved
Reserved
EXT_CLK_FREQ[4:0]
Bits
Field
Type
R/W
R/W
Default
Description
7
6
Reserved
EN_PLL
0
X
Selection of external clock and PLL operation:
0 - Forced to internal RC oscillator. PLL disabled.
1 - PLL is enabled in STANDBY and ACTIVE modes. Automatic external clock use
when available, interrupt generated if external clock appears or disappears.
5
Reserved
R/W
R/W
0
This bit must be set to '0'.
4:0 EXT_CLK_FREQ[4
:0]
X
Frequency of the external clock (CLKIN):
0x00 - 1 MHz
0x01 - 2 MHz
0x02 - 3 MHz
...
0x16 - 23 MHz
0x17 - 24 MHz
0x18...0x1F - Reserved
See electrical specification for input clock frequency tolerance.
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7.6.1.22 PGOOD_CTRL_1
Address: 0x15
D7
D6
D5
D4
D3
D2
D1
D0
PGOOD_POL
PGOOD_OD
PGOOD_
PGOOD_
EN_PGOOD_L EN_PGOOD_L EN_PGOOD_B EN_PGOOD_B
WINDOW_LDO WINDOW_BUC
K
DO1
DO0
UCK1
UCK0
Bits
Field
PGOOD_POL
Type
Default
Description
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
PGOOD signal polarity.
0 - PGOOD signal high when monitored outputs are valid
1 - PGOOD signal low when monitored outputs are valid
6
5
4
3
2
1
0
PGOOD_OD
X
X
X
X
X
X
X
PGOOD signal type:
0 - Push-pull output (VANA level)
1 - Open-drain output
PGOOD_
WINDOW_LDO
LDO Output voltage monitoring method for PGOOD signal:
0 - Only undervoltage monitoring
1 - Overvoltage and undervoltage monitoring.
PGOOD_
WINDOW_BUCK
Buck Output voltage monitoring method for PGOOD signal:
0 - Only undervoltage monitoring
1 - Overvoltage and undervoltage monitoring.
EN_PGOOD_LDO
1
PGOOD signal source control from LDO1
0 - LDO1 is not monitored
1 - LDO1 Power-Good threshold voltage monitored
EN_PGOOD_LDO
0
PGOOD signal source control from LDO0
0 - LDO0 is not monitored
1 - LDO0 Power-Good threshold voltage monitored
EN_PGOOD_BUC
K1
PGOOD signal source control from Buck1
0 - Buck1 is not monitored
1 - Buck1 Power-Good threshold voltage monitored
EN_PGOOD_BUC
K0
PGOOD signal source control from Buck0
0 - Buck0 is not monitored
1 - Buck0 Power-Good threshold voltage monitored
7.6.1.23 PGOOD_CTRL_2
Address: 0x16
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
EN_PGOOD_T PG_FAULT_G PGOOD_MOD
WARN
ATES_PGOOD
E
Bits
7:3
2
Field
Type
R/W
R/W
Default
0 0000
X
Description
Reserved
EN_PGOOD_TWA
RN
Thermal warning control for PGOOD signal:
0 - Thermal warning not monitored
1 - PGOOD inactive if thermal warning flag is active.
1
0
PG_FAULT_GATE
S_PGOOD
R/W
R/W
X
X
Type of operation for PGOOD signal:
0 - Indicates live status of monitored voltage outputs.
1 - Indicates status of PG_FAULT register, inactive when at least one PG_FAULT_x
bit is inactive.
PGOOD_MODE
Operating mode for PGOOD signal:
0 - Gated mode
1 - Continuous mode
7.6.1.24 PG_FAULT
Address: 0x17
D7
D6
D5
D4
D3
PG_FAULT_LD PG_FAULT_LD PG_FAULT_BU PG_FAULT_BU
O1 O0 CK1 CK0
D2
D1
D0
Reserved
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Bits
Field
Type
R/W
R/W
Default
0000
0
Description
7:4
Reserved
3
2
1
0
PG_FAULT_LDO1
Source for PGOOD inactive signal:
0 - LDO1 has not set PGOOD signal inactive.
1 - LDO1 is selected for PGOOD signal and it has set PGOOD signal inactive. This bit
can be cleared by writing '1' to this bit when LDO1 output is valid.
PG_FAULT_LDO0
R/W
R/W
R/W
0
0
0
Source for PGOOD inactive signal:
0 - LDO0 has not set PGOOD signal inactive.
1 - LDO0 is selected for PGOOD signal and it has set PGOOD signal inactive. This bit
can be cleared by writing '1' to this bit when LDO0 output is valid.
PG_FAULT_BUCK
1
Source for PGOOD inactive signal:
0 - Buck1 has not set PGOOD signal inactive.
1 - Buck1 is selected for PGOOD signal and it has set PGOOD signal inactive. This bit
can be cleared by writing '1' to this bit when Buck1 output is valid.
PG_FAULT_BUCK
0
Source for PGOOD inactive signal:
0 - Buck0 has not set PGOOD signal inactive.
1 - Buck0 is selected for PGOOD signal and it has set PGOOD signal inactive. This bit
can be cleared by writing '1' to this bit when Buck0 output is valid.
7.6.1.25 RESET
Address: 0x18
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
SW_RESET
Bits
7:1
0
Field
Type
R/W
R/W
Default
000 0000
0
Description
Reserved
SW_RESET
Software commanded reset. When written to 1, the registers will be reset to default
values, OTP memory is read, and the I2C interface is reset.
The bit is automatically cleared.
7.6.1.26 INT_TOP_1
Address: 0x19
D7
D6
D5
D4
D3
D2
D1
D0
PGOOD_INT
LDO_INT
BUCK_INT
SYNC_CLK_IN TDIE_SD_INT TDIE_WARN_I
OVP_INT
I_MEAS_INT
T
NT
Bits
Field
Type
Default
Description
7
PGOOD_INT
R/W
0
Latched status bit indicating that the PGOOD pin has changed from active to inactive.
Write 1 to clear interrupt.
6
LDO_INT
R
R
0
0
Interrupt indicating that LDO1 and/or LDO0 have a pending interrupt. The reason for
the interrupt is indicated in INT_LDO register.
This bit is cleared automatically when INT_LDO register is cleared to 0x00.
5
BUCK_INT
Interrupt indicating that Buck1 and/or Buck0 have a pending interrupt. The reason for
the interrupt is indicated in INT_BUCK register.
This bit is cleared automatically when INT_BUCK register is cleared to 0x00.
4
3
SYNC_CLK_INT
TDIE_SD_INT
R/W
R/W
0
0
Latched status bit indicating that the external clock has appeared or disappeared.
Write 1 to clear interrupt.
Latched status bit indicating that the die junction temperature has exceeded the
thermal shutdown level. The regulators have been disabled if they were enabled and
GPO and GPO2 signals are driven low. The regulators cannot be enabled if this bit is
active. The actual status of the thermal shutdown is indicated by TDIE_SD_STAT bit in
TOP_STAT register.
Write 1 to clear interrupt.
2
TDIE_WARN_INT
R/W
0
Latched status bit indicating that the die junction temperature has exceeded the
thermal warning level. The actual status of the thermal warning is indicated by
TDIE_WARN_STAT bit in TOP_STAT register.
Write 1 to clear interrupt.
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Bits
Field
Type
Default
Description
1
OVP_INT
R/W
0
Latched status bit indicating that the input voltage has exceeded the over-voltage
detection level. The regulators have been disabled if they were enabled and GPO and
GPO2 signals are driven low. The actual status of the over-voltage is indicated by
OVP_STAT bit in TOP_STAT register.
Write 1 to clear interrupt.
0
I_MEAS_INT
R/W
0
Latched status bit indicating that the load current measurement result is available in
I_LOAD_1 and I_LOAD_2 registers.
Write 1 to clear interrupt.
7.6.1.27 INT_TOP_2
Address: 0x1A
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
RESET_REG_I
NT
Bits
7:1
0
Field
Type
R/W
R/W
Default
000 0000
0
Description
Reserved
RESET_REG_INT
Latched status bit indicating that either VANA supply voltage has been below
undervoltage threshold level or the host has requested a reset using SW_RESET bit in
RESET register. The regulators have been disabled, and registers are reset to default
values and the normal startup procedure is done.
Write 1 to clear interrupt.
7.6.1.28 INT_BUCK
Address: 0x1B
D7
D6
BUCK1_PG
_INT
D5
D4
D3
D2
D1
D0
Reserved
BUCK1_SC
_INT
BUCK1_ILIM
_INT
Reserved
BUCK0_PG
_INT
BUCK0_SC
_INT
BUCK0_ILIM
_INT
Bits
Field
Type
R/W
R/W
Default
Description
7
6
Reserved
0
0
BUCK1_PG_INT
Latched status bit indicating that Buck1 Power-Good event has been detected.
Write 1 to clear.
5
4
BUCK1_SC_INT
R/W
R/W
0
0
Latched status bit indicating that the Buck1 output voltage has been over 1 ms below
short-circuit threshold level.
Write 1 to clear.
BUCK1_ILIM_INT
Latched status bit indicating that the Buck1 output current limit has been active.
Write 1 to clear.
3
2
Reserved
R/W
R/W
0
0
BUCK0_PG_INT
Latched status bit indicating that Buck0 Power-Good event has been detected.
Write 1 to clear.
1
0
BUCK0_SC_INT
BUCK0_ILIM_INT
R/W
R/W
0
0
Latched status bit indicating that the Buck0 output voltage has been over 1 ms below
short-circuit threshold level.
Write 1 to clear.
Latched status bit indicating that the Buck0 output current limit has been active.
Write 1 to clear.
7.6.1.29 INT_LDO
Address: 0x1C
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
LDO1_PG
_INT
LDO1_SC
_INT
LDO1_ILIM
_INT
Reserved
LDO0_PG
_INT
LDO0_SC
_INT
LDO0_ILIM
_INT
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Bits
Field
Type
R/W
R/W
Default
Description
7
Reserved
0
0
6
LDO1_PG_INT
Latched status bit indicating that LDO1 Power-Good event has been detected.
Write 1 to clear.
5
LDO1_SC_INT
R/W
R/W
0
0
Latched status bit indicating that the LDO1 output voltage has been over 1 ms below
short-circuit threshold level.
Write 1 to clear.
4
LDO1_ILIM_INT
Latched status bit indicating that the LDO1 output current limit has been active.
Write 1 to clear.
3
2
Reserved
R/W
R/W
0
0
LDO0_PG_INT
Latched status bit indicating that LDO0 Power-Good event has been detected.
Write 1 to clear.
1
0
LDO0_SC_INT
LDO0_ILIM_INT
R/W
R/W
0
0
Latched status bit indicating that the LDO0 output voltage has been over 1 ms below
short-circuit threshold level.
Write 1 to clear.
Latched status bit indicating that the LDO0 output current limit has been active.
Write 1 to clear.
7.6.1.30 TOP_STAT
Address: 0x1D
D7
D6
D5
D4
D3
D2
D1
D0
PGOOD_STAT
Reserved
SYNC_CLK
_STAT
TDIE_SD
_STAT
TDIE_WARN
_STAT
OVP_STAT
Reserved
Bits
Field
PGOOD_STAT
Type
Default
Description
7
R
0
Status bit indicating the status of PGOOD pin:
0 - PGOOD pin is inactive
1 - PGOOD pin is active
6:5
4
Reserved
R
R
00
0
SYNC_CLK_STAT
Status bit indicating the status of external clock (CLKIN):
0 - External clock frequency is valid
1 - External clock frequency is not valid.
3
2
1
0
TDIE_SD_STAT
R
R
R
R
0
0
0
0
Status bit indicating the status of thermal shutdown:
0 - Die temperature below thermal shutdown level
1 - Die temperature above thermal shutdown level.
TDIE_WARN
_STAT
Status bit indicating the status of thermal warning:
0 - Die temperature below thermal warning level
1 - Die temperature above thermal warning level.
OVP_STAT
Reserved
Status bit indicating the status of input overvoltage monitoring:
0 - Input voltage below overvoltage threshold level
1 - Input voltage above overvoltage threshold level.
7.6.1.31 BUCK_STAT
Address: 0x1E
D7
D6
D5
D4
D3
D2
D1
D0
BUCK1_STAT
BUCK1_PG
_STAT
Reserved
BUCK1_ILIM
_STAT
BUCK0_STAT
BUCK0_PG
_STAT
Reserved
BUCK0_ILIM
_STAT
Bits
Field
Type
Default
Description
7
BUCK1_STAT
R
0
Status bit indicating the enable/disable status of Buck1:
0 - Buck1 regulator is disabled
1 - Buck1 regulator is enabled.
6
BUCK1_PG_STAT
R
0
Status bit indicating Buck1 output voltage validity (raw status)
0 - Buck1 output voltage is valid.
1 - Buck1 output voltage is invalid.
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Bits
5
Field
Type
R
Default
Description
Reserved
0
0
4
BUCK1_ILIM
_STAT
R
Status bit indicating Buck1 current limit status (raw status)
0 - Buck1 output current is below current limit level
1 - Buck1 output current limit is active.
3
2
BUCK0_STAT
BUCK0_PG_STAT
Reserved
R
R
0
0
Status bit indicating the enable/disable status of Buck0:
0 - Buck0 regulator is disabled
1 - Buck0 regulator is enabled.
Status bit indicating Buck0 output voltage validity (raw status)
0 - Buck0 output voltage is valid.
1 - Buck0 output voltage is invalid.
1
0
R
R
0
0
BUCK0_ILIM
_STAT
Status bit indicating Buck0 current limit status (raw status)
0 - Buck0 output current is below current limit level
1 - Buck0 output current limit is active.
7.6.1.32 LDO_STAT
Address: 0x1F
D7
D6
D5
D4
D3
D2
D1
D0
LDO1_STAT
LDO1_PG
_STAT
Reserved
LDO1_ILIM
_STAT
LDO0_STAT
LDO0_PG
_STAT
Reserved
LDO0_ILIM
_STAT
Bits
Field
Type
Default
Description
7
LDO1_STAT
LDO1_PG_STAT
Reserved
R
0
Status bit indicating the enable/disable status of LDO1:
0 - LDO1 regulator is disabled
1 - LDO1 regulator is enabled.
6
R
0
Status bit indicating LDO1 output voltage validity (raw status)
0 - LDO1 output voltage is valid.
1 - LDO1 output voltage is invalid.
5
4
R
R
0
0
LDO1_ILIM
_STAT
Status bit indicating LDO1 current limit status (raw status)
0 - LDO1 output current is below current limit level
1 - LDO1 output current limit is active.
3
2
LDO0_STAT
LDO0_PG_STAT
Reserved
R
R
0
0
Status bit indicating the enable/disable status of LDO0:
0 - LDO0 regulator is disabled
1 - LDO0 regulator is enabled.
Status bit indicating LDO0 output voltage validity (raw status)
0 - LDO0 output voltage is valid.
1 - LDO0 output voltage is invalid.
1
0
R
R
0
0
LDO0_ILIM
_STAT
Status bit indicating LDO0 current limit status (raw status)
0 - LDO0 output current is below current limit level
1 - LDO0 output current limit is active.
7.6.1.33 TOP_MASK_1
Address: 0x20
D7
D6
D5
D4
D3
D2
D1
D0
PGOOD_INT_
MASK
Reserved
SYNC_CLK
_MASK
Reserved
TDIE_WARN
_MASK
Reserved
I_LOAD_
READY_MASK
Bits
Field
Type
Default
Description
7
PGOOD_INT
_MASK
R/W
X
Masking for Power-Good interrupt (PGOOD_INT in INT_TOP_1 register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect PGOOD_STAT status bit in TOP_STAT register.
6:5
Reserved
R/W
00
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Bits
Field
Type
Default
Description
4
SYNC_CLK
_MASK
R/W
X
Masking for external clock detection interrupt (SYNC_CLK_INT in INT_TOP_1
register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect SYNC_CLK_STAT status bit in TOP_STAT register.
3
2
Reserved
R/W
R/W
0
TDIE_WARN
_MASK
X
Masking for thermal warning interrupt (TDIE_WARN_INT in INT_TOP_1 register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect TDIE_WARN_STAT status bit in TOP_STAT register.
1
0
Reserved
R/W
R/W
0
I_MEAS
_MASK
X
Masking for load current measurement ready interrupt (MEAS_INT in INT_TOP_1
register).
0 - Interrupt generated
1 - Interrupt not generated.
7.6.1.34 TOP_MASK_2
Address: 0x21
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
RESET_REG
_MASK
Bits
7:1
0
Field
Type
R/W
R/W
Default
000 0000
X
Description
Reserved
RESET_REG
_MASK
Masking for register reset interrupt (RESET_REG_INT in INT_TOP_2 register):
0 - Interrupt generated
1 - Interrupt not generated.
This change of this bit by I2C writing has no effect because it will be read from OTP
memory during reset.
7.6.1.35 BUCK_MASK
Address: 0x22
D7
D6
D5
D4
D3
D2
D1
D0
BUCK1_PGF
_MASK
BUCK1_PGR
_MASK
Reserved
BUCK1_ILIM
_MASK
BUCK0_PGF
_MASK
BUCK0_PGR
_MASK
Reserved
BUCK0_ILIM
_MASK
Bits
Field
Type
Default
Description
7
BUCK1_PGF_MAS
K
R/W
X
Masking of Power Good invalid detection for Buck1 power good interrupt
(BUCK1_PG_INT in INT_BUCK register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK1_PG_STAT status bit in BUCK_STAT register.
6
BUCK1_PGR_MAS
K
R/W
X
Masking of Power Good valid detection for Buck1 Power Good interrupt
(BUCK1_PG_INT in INT_BUCK register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK1_PG_STAT status bit in BUCK_STAT register.
5
4
Reserved
R
0
BUCK1_ILIM
_MASK
R/W
X
Masking for Buck1 current limit detection interrupt (BUCK1_ILIM_INT in INT_BUCK
register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK1_ILIM_STAT status bit in BUCK_STAT register.
3
BUCK0_PGF_MAS
K
R/W
X
Masking of Power Good invalid detection for Buck0 power good interrupt
(BUCK0_PG_INT in INT_BUCK register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK0_PG_STAT status bit in BUCK_STAT register.
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Bits
Field
Type
Default
Description
2
BUCK0_PGR_MAS
K
R/W
X
Masking of Power Good valid detection for Buck0 power good interrupt
(BUCK0_PG_INT in INT_BUCK register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK0_PG_STAT status bit in BUCK_STAT register.
1
0
Reserved
R
0
BUCK0_ILIM
_MASK
R/W
X
Masking for Buck0 current limit detection interrupt (BUCK0_ILIM_INT in INT_BUCK
register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK0_ILIM_STAT status bit in BUCK_STAT register.
7.6.1.36 LDO_MASK
Address: 0x23
D7
D6
D5
D4
D3
D2
D1
D0
LDO1_PGF
_MASK
LDO1_PGR
_MASK
Reserved
LDO1_ILIM
_MASK
LDO0_PGF
_MASK
LDO0_PGR
_MASK
Reserved
LDO0_ILIM
_MASK
Bits
Field
Type
Default
Description
7
LDO1_PGF_MASK
LDO1_PGR_MASK
Reserved
R/W
X
Masking of Power Good invalid detection for LDO1 power good interrupt
(LDO1_PG_INT in INT_LDO register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect LDO1_PG_STAT status bit in LDO_STAT register.
6
R/W
X
Masking of Power Good valid detection for LDO1 power good interrupt
(LDO1_PG_INT in INT_LDO register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect LDO1_PG_STAT status bit in LDO_STAT register.
5
4
R
0
LDO1_ILIM
_MASK
R/W
X
Masking for LDO1 current limit detection interrupt (LDO1_ILIM_INT in INT_LDO
register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect LDO1_ILIM_STAT status bit in LDO_STAT register.
3
2
LDO0_PGF_MASK
LDO0_PGR_MASK
Reserved
R/W
R/W
X
X
Masking of Power Good invalid detection for LDO0 power good interrupt
(LDO0_PG_INT in INT_LDO register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect LDO0_PG_STAT status bit in LDO_STAT register.
Masking of Power Good valid detection for LDO0 power good interrupt
(LDO0_PG_INT in INT_LDO register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect LDO0_PG_STAT status bit in LDO_STAT register.
1
0
R
0
LDO0_ILIM
_MASK
R/W
X
Masking for LDO0 current limit detection interrupt (LDO0_ILIM_INT in INT_LDO
register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect LDO0_ILIM_STAT status bit in LDO_STAT register.
7.6.1.37 SEL_I_LOAD
Address: 0x24
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
LOAD_CURRE
NT_BUCK
_SELECT
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Bits
Field
Type
R/W
R/W
Default
000 0000
0
Description
7:1
Reserved
0
LOAD_CURRENT_
BUCK_SELECT
Start the current measurement on the selected regulator:
0 - Buck0
1 - Buck1
The measurement is started when register is written.
If the selected buck is master, the measurement result is a sum current of master and
slave buck.
If the selected buck is slave, the measurement result is a current of the selected slave
buck.
7.6.1.38 I_LOAD_2
Address: 0x25
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK_LOAD_
CURRENT[8]
Bits
7:1
0
Field
Type
R
Default
000 0000
0
Description
Reserved
BUCK_LOAD_
CURRENT[8]
R
This register describes the MSB bit of the average load current on selected regulator
with a resolution of 20 mA per LSB and maximum 10.22-A current.
7.6.1.39 I_LOAD_1
Address: 0x26
D7
D6
D5
D4
D3
D2
D1
D0
BUCK_LOAD_CURRENT[7:0]
Bits
Field
Type
Default
Description
7:0
BUCK_LOAD_
CURRENT[7:0]
R
0000 0000 This register describes 8 LSB bits of the average load current on selected regulator
with a resolution of 20 mA per LSB and maximum 10.22-A current.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LP8733xx-Q1 is a power management unit including two step-down regulators, two linear regulators, and
two general-purpose digital output signals.
8.2 Typical Applications
L0
VOUT_B0
VIN
VIN_B0
VIN_B1
SW_B0
FB_B0
CIN_BUCK0
CIN_BUCK1
COUT_BUCK0
LOAD
CPOL_BUCK0
VIN_LDO0
VIN_LDO1
L1
CIN_LDO0
CIN_LDO1
VOUT_B1
SW_B1
FB_B1
VANA
CANA
SDA
SCL
nINT
EN
COUT_BUCK1
LOAD
CPOL_BUCK1
VOUT_LDO0
VOUT_LDO0
VOUT_LDO1
CLKIN (GPO2)
GPO
VOUT_LDO1
PGOOD
GNDs
COUT_LDO0 COUT_LDO1
Copyright © 2017, Texas Instruments Incorporated
Figure 29. Two Single-phase Buck Outputs Configuration
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Typical Applications (continued)
L0
VOUT_B0
VIN
VIN_B0
SW_B0
FB_B0
VIN_B1
CIN_BUCK0
CIN_BUCK1
COUT_BUCK0
VIN_LDO0
L1
VIN_LDO1
CIN_LDO0
CIN_LDO1
LOAD
CPOL_BUCK
SW_B1
FB_B1
VANA
CANA
COUT_BUCK1
SDA
SCL
nINT
EN
VOUT_LDO0
VOUT_LDO0
VOUT_LDO1
CLKIN (GPO2)
GPO
VOUT_LDO1
PGOOD
GNDs
COUT_LDO0 COUT_LDO1
Copyright © 2017, Texas Instruments Incorporated
Figure 30. Single Dual-phase Buck Output Configuration
8.2.1 Design Requirements
8.2.1.1 Inductor Selection
The inductors L0 and L1 are shown in the Typical Applications. The inductance and DCR of the inductor affects
the control loop of the buck regulator. TI recommends using inductors similar to those listed in Table 8. Pay
attention to the saturation current and temperature rise current of the inductor. Check that the saturation current
is higher than the peak current limit and the temperature rise current is higher than the maximum expected rms
output current. Minimum effective inductance to ensure good performance is 0.22 μH at maximum peak output
current over the operating temperature range. DC resistance of the inductor must be less than 0.05 Ω for good
efficiency at high-current condition. The inductor AC loss also affects conversion efficiency. Higher Q factor at
switching frequency usually gives better efficiency at light load to middle load. Shielded inductors are preferred
as they radiate less noise.
Table 8. Recommended Inductors
RATED DC CURRENT
ISAT maximum (typical) /
ITEMP maximum (typical) (A)
DCR
MANUFACTURER
TOKO
PART NUMBER
VALUE
DIMENSIONS L × W × H (mm)
2.5 × 2 × 1.2
typical / maximum (mΩ)
DFE252012PD-
R47M
0.47 µH (20%)
5.2 (–) / 4 (–)(1)
— / 27
Tayo Yuden
MDMK2020TR47M 0.47 µH (20%)
MV
2 × 2 ×1.2
4.2 (4.8) / 2.3 (2.45)
40 / 46
(1) Operating temperature range is up to 125°C including self temperature rise.
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8.2.1.2 Buck Input Capacitor Selection
The input capacitors CIN_BUCK0 and CIN_BUCK1 are shown in the Typical Applications. A ceramic input bypass
capacitor of 10 μF is required for each phase of the regulator. Place the input capacitor as close as possible to
the VIN_Bx pin and PGND_Bx pin of the device. A larger value or higher voltage rating improves the input
voltage filtering. Use X7R type of capacitors, not Y5V or F. Also the DC bias characteristics capacitors must be
considered. Minimum effective input capacitance to ensure good performance is 1.9 μF per buck input at
maximum input voltage including tolerances, ambient temperature range and aging. This is assuming that there
are at least 22 μF of additional capacitance common for all the power input pins on the system power rail. See
Table 9.
The input filter capacitor supplies current to the high-side FET switch in the first half of each cycle and reduces
voltage ripple imposed on the input power source. A ceramic capacitor's low ESR provides the best noise filtering
of the input voltage spikes due to this rapidly changing current. Select an input filter capacitor with sufficient
ripple current rating. In addition ferrite can be used in front of the input capacitor to reduce the EMI.
Table 9. Recommended Buck Input Capacitor (X7R Dielectric)
DIMENSIONS L × W × H
(mm)
VOLTAGE
RATING
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
Murata
GCM21BR71A106KE22
10 µF (10%)
0805
2 × 1.25 × 1.25
10 V
8.2.1.3 Buck Output Capacitor Selection
The output capacitor COUT_BUCK0 and COUT_BUCK1 are shown in Typical Applications. A ceramic local output
capacitor of 22 μF is required per phase. Use ceramic capacitors, X7R type; do not use Y5V or F. DC bias
voltage characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out current
flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and
reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low
ESR and ESL to perform these functions. Minimum effective output capacitance to ensure good performance is
10 μF per phase including the DC voltage rolloff, tolerances, aging, and temperature effects.
The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its
RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for
selection process is at the switching frequency of the part. See Table 10.
POL capacitors CPOL_BUCKx can be used to improve load transient performance and to decrease the ripple
voltage. A higher output capacitance improves the load step behavior and reduces the output voltage ripple as
well as decreases the PFM switching frequency. However, output capacitance higher than 150 μF per phase is
not necessarily of any benefit. Note that the output capacitor may be the limiting factor in the output voltage
ramp, see Specifications for maximum output capacitance for different slew-rate settings. For large output
capacitors, the output voltage might be slower than the programmed ramp rate at voltage transitions, because of
the higher energy stored on the output capacitance. Also at start-up, the time required to charge the output
capacitor to target value might be longer. At shutdown the output voltage is discharged to 0.6 V level using
forced-PWM operation. This can increase the input voltage if the load current is small and the output capacitor is
large compared to input capacitor. Below 0.6 V level the output capacitor is discharged by the internal discharge
resistor and with large capacitor more time is required to settle VOUT down as a consequence of the increased
time constant.
Table 10. Recommended Buck Output Capacitors (X7R Dielectric)
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L × W × H
(mm)
VOLTAGE RATING
Murata
GCM31CR71A226KE02
22 µF (10%)
1206
3.2 × 1.6 × 1.6
10 V
8.2.1.4 LDO Input Capacitor Selection
The input capacitors CIN_LDO0 and CIN_LDO1 are shown in the . A ceramic input capacitor of 2.2 μF, 6.3 V is
sufficient for most applications. Place the input capacitor as close as possible to the VIN_LDOx pin and AGND
pin of the device. A larger value or higher voltage rating improves the input voltage filtering. Use X7R type of
capacitors, not Y5V or F. DC bias characteristics of capacitors must be considered, minimum effective input
capacitance to ensure good performance is 0.6 μF per LDO input at maximum input voltage including tolerances,
ambient temperature range and aging. See Table 11.
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Table 11. Recommended LDO Input Capacitors (X7R Dielectric)
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L × W × H
VOLTAGE RATING
(mm)
Murata
Murata
GCM188R70J225KE22
GCM21BR71C475KA73
2.2 µF (10%)
4.7 µF (10%)
0603
0805
1.6 × 0.8 × 0.8
2 × 1.25 × 1.25
6.3 V
16 V
8.2.1.5 LDO Output Capacitor Selection
The output capacitors COUT_LDO0 and COUT_LDO1 are shown in the Typical Applications. A ceramic output
capacitor of minimum 1.0 μF is required. Place the output capacitor as close to the VOUT_LDOx pin and AGND
pin of the device as possible. Use X7R type of capacitors, not Y5V or F. DC bias characteristics of capacitors
must be considered, minimum effective output capacitance to ensure good performance is 0.4 μF per LDO input
at maximum input voltage including tolerances, ambient temperature range and aging. See Table 12.
The output capacitance must be smaller than the input capacitance in order to ensure the stability of the LDO.
With a 1-μF output capacitor it is recommended to use at least 2.2-μF input capacitor; with a 2.2-μF output
capacitor at least 4.7-μF input capacitance.
The VANA input is used to supply analog and digital circuits in the device. See Table 13 for recommended
components from for VANA input supply filtering.
Table 12. Recommended LDO Output Capacitors (X7R Dielectric)
MANUFACTURER
Murata
PART NUMBER
VALUE
CASE SIZE
0603
DIMENSIONS L × W × H (mm)
1.6 × 0.8 × 0.8
VOLTAGE RATING
GCM188R71C105KA64
GCM188R70J225KE22
1 µF (10%)
2.2 µF (10%)
16 V
Murata
0603
1.6 × 0.8 × 0.8
6.3 V
Table 13. Recommended Supply Filtering Components
MANUFACTURER
Murata
PART NUMBER
VALUE
CASE SIZE
0402
DIMENSIONS L × W × H (mm)
1 × 0.5 × 0.5
VOLTAGE RATING
GCM155R71C104KA55
GCM188R71C104KA37
100 nF (10%)
100 nF (10%)
16 V
16 V
Murata
0603
1.6 × 0.8 × 0.8
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8.2.1.6 Current Limit vs. Maximum Output Current
The inductor current ripple can be calculated using Equation 1 and Equation 2:
VOUT
D =
V
ì h
IN(max)
(1)
(2)
(VIN(max) - VOUT ) ì D
fSW ì L
DIL =
Example using Equation 1 and Equation 2:
VIN(max) = 5.5 V
VOUT = 1 V
η = 0.75
fSW = 1.8 MHz
L = 0.38 µH
then D = 0.242 and ΔIL = 1.59 A
Peak current is half of the current ripple. If ILIM_FWD_SET_OTP is 3 A, the minimum forward current limit would be
2.85 A when taking the –5% tolerance into account. In this case the difference between set peak current and
maximum load current = 0.795 A + 0.15 A = 0.945 A.
Inductor current =
Forward current
ILIM_FWD_MAX (+20%)
ILIM_FWD_TYP (+7.5%)
ILIM_FWD_SET_OTP (1.5...4 A, 0.5-A step)
ILIM_FWD_MIN (-5%)
Minimum 1A guard band
to take current ripple,
inductor inductance
variation into account
IL_AVG = IOUT
1 / fSW
IOUT_MAX < ILIM_FWD_SET_OTP œ 1 A
Figure 31. Current Limit vs Maximum Output Current
8.2.2 Detailed Design Procedure
The performance of the LP8733xx-Q1 device depends greatly on the care taken in designing the printed circuit
board (PCB). The use of low-inductance and low serial-resistance ceramic capacitors is strongly recommended,
while proper grounding is crucial. Attention must be given to decoupling the power supplies. Decoupling
capacitors must be connected close to the device and between the power and ground pins to support high peak
currents being drawn from system power rail during turnon of the switching MOSFETs. Keep input and output
traces as short as possible, because trace inductance, resistance, and capacitance can easily become the
performance limiting items. The separate buck regulator power pins VIN_Bx are not connected together
internally. Connect the VIN_Bx power connections together outside the package using power plane construction.
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8.2.3 Application Curves
Measurements are done using typical application set up with connections shown in Typical Applications. Graphs
may not reflect the OTP default settings. Unless otherwise specified: V(VIN_Bx) = V(VIN_LDOx) = V(VANA) = 3.7 V,
VOUT_Bx = 1 V, VOUT_LDOx = 1 V, TA = 25°C, L = 0.47 µH (TOKO DFE252012PD-R47M), COUT_BUCK = 22 µF /
phase, and CPOL_BUCK = 22 µF, COUT_LDO = 1 µF.
100
90
80
70
60
50
40
100
90
80
70
60
50
40
Vin=5V, AUTO
Vin=3.3V, AUTO
Vin=5V, FPWM
Vin=3.3V, FPWM
Vin=5V, AUTO
Vin=3.3V, AUTO
Vin=5V, FPWM
Vin=3.3V, FPWM
0.001
0.01
0.1
1
3
Output Current (A)
0.001
0.01
0.1
1
6
D003
Output Current (A)
VOUT = 1.8 V
D005
VOUT = 1.8 V
Figure 32. Buck Efficiency in PFM/PWM and Forced PWM
Mode (Single-Phase Output)
Figure 33. Buck Efficiency in PFM/PWM and Forced PWM
Mode (Dual-Phase Output)
100
90
80
70
60
100
90
80
70
60
Vout=1V
Vout=1.8V
Vout=2.5V
50
Vout=1V
Vout=1.8V
Vout=2.5V
50
40
0.001
0.01
0.1
1
3
40
0.001
Output Current (A)
0.01
0.1
1
6
D007
Output Current (A)
VIN = 3.3 V
D009
VIN = 3.3 V
Figure 34. Buck Efficiency in Forced PWM Mode (Single-
Phase Output)
Figure 35. Buck Efficiency in Forced PWM Mode (Dual-
Phase Output)
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100
90
80
70
60
50
40
100
90
80
70
60
50
40
Vout=1V
Vout=1.8V
Vout=2.5V
Vout=1V
Vout=1.8V
Vout=2.5V
0.001
0.01
0.1
1
3
Output Current (A)
D011
0.001
0.01
0.1
1
6
VIN = 5 V
Output Current (A)
D013
VIN = 5 V
Figure 36. Buck Efficiency in Forced PWM Mode (Single-
Phase Output)
Figure 37. Buck Efficiency in Forced PWM Mode (Dual-
Phase Output)
1.02
1.016
1.012
1.008
1.004
1
1.02
1.016
1.012
1.008
1.004
1
0.996
0.992
0.988
0.996
0.992
0.988
0.984
0.98
Vin=3.3V, FPWM
0.984
Vin=5.0V, FPWM
Vin=3.3V, FPWM
Vin=5.0V, FPWM
0.98
0
0.5
1
1.5
2
2.5
3
Output Current (A)
D015
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
VOUT = 1 V
Output Current (A)
D017
VOUT = 1 V
Figure 38. Buck Output Voltage vs Load Current in Forced
PWM Mode (Single-Phase Output)
Figure 39. Buck Output Voltage vs Load Current in Forced
PWM Mode (Dual-Phase Output)
1.02
1.016
1.012
1.008
1.004
1
1.02
1.015
1.01
1.005
1
0.996
0.992
0.988
0.995
0.99
0.985
0.98
Vin=3.3V, AUTO
Vin=5.0V, AUTO
Vin=3.3V, AUTO
0.984
Vin=5.0V, AUTO
0.98
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Output Current (A)
1
0
0.2
0.4
0.6
0.8
1
Output Current (A)
D019
D020
VOUT = 1 V
VOUT = 1 V
Figure 40. Buck Output Voltage vs Load Current in
PFM/PWM Mode (Single-Phase Output)
Figure 41. Buck Output Voltage vs Load Current in
PFM/PWM Mode (Dual-Phase Output)
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1.02
1.016
1.012
1.008
1.004
1
1.016
1.012
1.008
1.004
1
0.996
0.992
0.988
0.984
0.98
0.996
0.992
0.988
0.984
0.98
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
Input Voltage (V)
D021
D022
VOUT = 1 V
Load = 1 A
VOUT = 1 V
Load = 1 A
Figure 42. Buck Output Voltage vs Input Voltage in PWM
Mode (Single-Phase Output)
Figure 43. Buck Output Voltage vs Input Voltage in PWM
Mode (Dual-Phase Output)
3
2
1
1.02
1.015
1.01
1.005
1
0.995
0.99
ADDING
SHEDDING
0.985
0.98
PFM
PWM
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
-40
-20
0
20
40
60
80
100 120 140
Output Current (A)
Temperature (èC)
D025
D023
VIN = 3.7 V
Load = 1 A (PWM) and 0.1 A (PFM)
Figure 44. Buck Output Voltage vs Temperature
Figure 45. Buck Phase Adding and Shedding vs Load
Current (Dual-Phase Output)
Slew-rate = 10 mV/µs
ILOAD = 0 A
VOUT = 1 V
Slew-rate = 10 mV/µs
ILOAD = 0 A
VOUT = 1 V
Figure 47. Buck Start-Up With EN1, Forced PWM Mode
(Dual-Phase Output)
Figure 46. Buck Start-Up With EN1, Forced PWM Mode
(Single-Phase Output)
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Slew-rate = 10 mV/µs
RLOAD = 1 Ω
VOUT = 1 V
Slew-rate = 10 mV/µs
RLOAD = 0.5 Ω
VOUT = 1 V
Figure 48. Buck Start-Up with EN1, Forced PWM Mode
(Single-Phase Output)
Figure 49. Buck Start-Up with EN1, Forced PWM Mode
(Dual-Phase Output)
Slew-rate = 10 mV/µs
RLOAD = 1 Ω
VOUT = 1 V
Slew-rate = 10 mV/µs
RLOAD = 0.5 Ω
VOUT = 1 V
Figure 50. Buck Shutdown With EN1, Forced PWM Mode
(Single-Phase Output)
Figure 51. Buck Shutdown With EN1, Forced PWM Mode
(Dual-Phase Output)
IOUT = 10 mA
IOUT = 10 mA
Figure 52. Buck Output Voltage Ripple, PFM Mode (Single-
Phase Output)
Figure 53. Buck Output Voltage Ripple, PFM Mode (Dual-
Phase Output)
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IOUT = 200 mA
IOUT = 200 mA
Figure 55. Buck Output Voltage Ripple,
Figure 54. Buck Output Voltage Ripple,
Forced PWM Mode (Single-Phase Output)
Forced PWM Mode (Dual-Phase Output)
Figure 56. Buck Transient From PFM-to-PWM Mode
(Single-Phase Output)
Figure 57. Buck Transient From PFM-to-PWM Mode (Dual-
Phase Output)
Figure 58. Buck Transient From PWM-to-PFM Mode
(Single-Phase Output)
Figure 59. Buck Transient From PWM-to-PFM Mode (Dual-
Phase Output)
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Figure 60. Buck Transient From 1-Phase to 2-Phase
Figure 61. Buck Transient From 2-Phase to 1-Phase
Operation (Dual-Phase Output)
Operation (Dual-Phase Output)
IOUT = 0.1 A → 2 A
→ 0.1 A
TR = TF = 400 ns
IOUT = 0.1 A → 4 A
→ 0.1 A
TR = TF = 400 ns
Figure 62. Buck Transient Load Step Response, AUTO
Mode (Single-Phase Output)
Figure 63. Buck Transient Load Step Response, AUTO
Mode (Dual-Phase Output)
IOUT = 0.1 A → 2 A
→ 0.1 A
TR = TF = 400 ns
IOUT = 0.1 A → 4 A
→ 0.1 A
TR = TF = 400 ns
Figure 64. Buck Transient Load Step Response, Forced
PWM Mode (Single-Phase Output)
Figure 65. Buck Transient Load Step Response, Forced
PWM Mode (Dual-Phase Output)
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VOUT(200mV/div)
VOUT(200mV/div)
Time (400 µs/div)
Time (400 µs/div)
Figure 66. Buck VOUT Transition from 0.6 V to 1.4 V With
Different Slew Rate Settings
Figure 67. Buck VOUT Transition from 1.4 V to 0.6 V With
Different Slew Rate Settings
Figure 68. Buck Start-up With Short on Output (Single-
Phase Output)
Figure 69. Buck Start-up With Short on Output (Dual-
Phase Output)
1.02
1.015
1.01
1.005
1
1.02
1.015
1.01
1.005
1
0.995
0.99
0.995
0.99
0.985
0.98
0.985
0.98
Vin=3.3V
Vin=5V
0
50
100
150
200
250
300
2.5
3
3.5
4
4.5
5
5.5
Output Current (mA)
Input Voltage (V)
D050
D051
VOUT = 1 V
Figure 70. LDO Output Voltage vs Load Current
VOUT = 1 V
Load = 200 mA
Figure 71. LDO Output Voltage vs Input Voltage
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1.02
1.015
1.01
1.005
1
0.995
0.99
0.985
0.98
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D052
ILOAD = 0 A
VOUT = 1 V
VOUT = 1 V
Load = 200 mA
Figure 73. LDO Start-Up
Figure 72. LDO Output Voltage vs Temperature
RLOAD = 3.3 Ω
VOUT = 1 V
ILOAD = 0 A
VOUT = 1 V
Figure 74. LDO Start-Up
Figure 75. LDO Shutdown
IOUT = 0 A → 0.3 A → 0 A
TR = TF = 1 µs
Figure 76. LDO Transient Load Step Response
Figure 77. LDO VOUT Transition from 1.8 V to 1.2 V
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Start-up
delay is 500
µs
Figure 78. LDO VOUT Transition from 1.2 V to 1.8 V
Figure 79. LDO Start-Up With Short on Output
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.8 V and 5.5 V. The VANA input
and VIN_Bx buck inputs must be connected together, and they must use the same input supply. This input
supply must be well regulated and able to withstand maximum input current and maintain stable voltage without
voltage drop even at load transition condition. The resistance of the input supply rail must be low enough that the
input current transient does not cause too high a drop in the LP8733xx-Q1 supply voltage that can cause false
UVLO fault triggering. If the input supply is located more than a few inches from the LP8733xx-Q1 additional bulk
capacitance may be required in addition to the ceramic bypass capacitors. The VIN_LDOx LDO input supply
voltage range is 2.5 V to 5.5 V and can be higher or lower than VANA supply voltage.
10 Layout
10.1 Layout Guidelines
The high frequency and large switching currents of the LP8733xx-Q1 make the choice of layout important. Good
power supply results only occur when care is given to proper design and layout. Layout affects noise pickup and
generation and can cause a good design to perform with less-than-expected results. With a range of output
currents from milliamps to several amps, good power supply layout is much more difficult than most general PCB
design. Use the following steps as a reference to ensure the device is stable and maintains proper voltage and
current regulation across its intended operating voltage and current range.
1. Place CIN as close as possible to the VIN_Bx pin and the PGND_Bx pin. Route the VIN trace wide and thick
to avoid IR drops. The trace between the positive node of the input capacitor and the VIN_Bx pin(s) of
LP8733xx-Q1, as well as the trace between the negative node of the input capacitor and power PGND_Bx
pin(s), must be kept as short as possible. The input capacitance provides a low-impedance voltage source
for the switching converter. The inductance of the connection is the most important parameter of a local
decoupling capacitor — parasitic inductance on these traces must be kept as small as possible for proper
device operation. The parasitic inductance can be reduced by using a ground plane as close as possible to
top layer by using thin dielectric layer between top layer and ground plane.
2. The output filter, consisting of L and COUT, converts the switching signal at SW_Bx to the noiseless output
voltage. It must be placed as close as possible to the device keeping the switch node small, for best EMI
behavior. Route the traces between the output capacitors of the LP8733xx-Q1 and the input capacitors of the
load direct and wide to avoid losses due to the IR drop.
3. Input for analog blocks (VANA and AGND) must be isolated from noisy signals. Connect VANA directly to a
quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling
capacitor as close as possible to the VANA pin.
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Layout Guidelines (continued)
4. If remote voltage sensing can be used for the load, connect the LP8733xx-Q1 feedback pins FB_Bx to the
respective sense pins on the load capacitor. The sense lines are susceptible to noise. They must be kept
away from noisy signals such as PGND_Bx, VIN_Bx, and SW_Bx, as well as high bandwidth signals such as
the I2C. Avoid both capacitive and inductive coupling by keeping the sense lines short and direct, and close
to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if
possible. If series resistors are used for load current measurement, place them after connection of the
voltage feedback.
5. PGND_Bx, VIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers
which are not able to withstand interference from noisy PGND_Bx, VIN_Bx and SW_Bx.
6. LDO performance (PSRR, noise and transient response) depend on the layout of the PCB. Best performance
is achieved by placing CIN and COUT as close to the LP8733xx-Q1 device as practical. The ground
connections for CIN and COUT must be back to the LP8733xx-Q1 AGND with as wide and as short of a
copper trace as is practical and with multiple vias if routing is done on other layer. Avoid connections using
long trace lengths, narrow trace widths, or connection through small via. These add parasitic inductances
and resistance that results in inferior performance especially during transient conditions.
Due to the small package of this converter and the overall small solution size, the thermal performance of the
PCB layout is important. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and
convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of
a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures.
Wide power traces come with the ability to sink dissipated heat. This can be improved further on multi-layer PCB
designs with vias to different planes. This results in reduced junction-to-ambient (RθJA) and junction-to-board
(RθJB) thermal resistances, thereby reducing the device junction temperature, TJ. TI strongly recommends
performance of a careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design
process by using a thermal modeling analysis software.
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10.2 Layout Example
VOUT0
VOUT1
COUT0
COUT1
GND
L1
L0
21 20 19
17
16
18
15
14
SW_B0
SW_B1
SW_B1
VIN_B1
22
23
13
12
SW_B0
VIN_B0
VIN_B0
CIN0
CIN1
29
AGND
24
VIN
25
VIN
GND
GND
11
VIN_B1
CLKIN
nINT
10
9
GPO
26
27
PGOOD
CIN2
CIN3
8
VIN_LDO0
28
VIN_LDO1
VIN
AGND
VIN
AGND
1
2
3
4
5
6
COUT3
AGND
COUT2
VIN
CANA
AGND
VOUT2
VOUT3
Figure 80. LP8733xx-Q1 Board Layout
In dual-phase buck configuration short VOUT0 and VOUT1 together.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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19-Nov-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
3000
250
(1)
(2)
(3)
(4/5)
(6)
LP873300RHDRQ1
LP873300RHDTQ1
LP873344RHDRQ1
LP873344RHDTQ1
ACTIVE
VQFN
VQFN
VQFN
VQFN
RHD
28
28
28
28
Green (RoHS
& no Sb/Br)
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
LP8733
00-Q1
ACTIVE
PREVIEW
PREVIEW
RHD
Green (RoHS
& no Sb/Br)
SN
SN
SN
LP8733
00-Q1
RHD
3000
250
Green (RoHS
& no Sb/Br)
LP8733
44-Q1
RHD
Green (RoHS
& no Sb/Br)
LP8733
44-Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Nov-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LP8733-Q1 :
Catalog: LP8733
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Sep-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP873300RHDRQ1
LP873300RHDTQ1
VQFN
VQFN
RHD
RHD
28
28
3000
250
330.0
180.0
12.4
12.4
5.25
5.25
5.25
5.25
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Sep-2018
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP873300RHDRQ1
LP873300RHDTQ1
VQFN
VQFN
RHD
RHD
28
28
3000
250
370.0
220.0
355.0
205.0
55.0
50.0
Pack Materials-Page 2
PACKAGE OUTLINE
RHD0028W
VQFN - 1 mm max height
S
C
A
L
E
2
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
5.1
4.9
0.1 MIN
(0.05)
A
-
A
2
5
.
0
0
0
SECTION A-A
TYPICAL
C
1 MAX
SEATING PLANE
0.08
0.05
0.00
3.4 0.1
(0.2) TYP
8
14
EXPOSED
THERMAL PAD
24X 0.5
7
15
A
SYMM
A
4X
3
1
21
0.3
28X
0.2
0.1
C A B
28
22
PIN 1 ID
(OPTIONAL)
SYMM
0.05
0.65
0.45
28X
4222120/B 02/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHD0028W
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.4)
SYMM
22
28
28X (0.75)
1
21
28X (0.25)
(1.45)
SYMM
(4.65)
(0.5) TYP
15
7
(R0.05) TYP
(
0.2) TYP
VIA
8
14
(1.45)
(4.65)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL EDGE
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222120/B 02/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RHD0028W
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(0.84) TYP
28
22
METAL
TYP
28X (0.75)
1
21
28X (0.25)
(0.84)
TYP
SYMM
(4.65)
24X (0.5)
7
15
(R0.05) TYP
8
14
4X ( 1.47)
(4.65)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
75% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4222120/B 02/2018
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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