LP8754 [TI]
多相位 6 核降压转换器;
| 型号： | LP8754 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 多相位 6 核降压转换器 转换器 |
| 文件： | 总53页 (文件大小：1898K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LP8754
ZHCSDB8A –FEBRUARY 2014–REVISED AUGUST 2014
LP8754 多相位六核降压转换器
1 特性
3 说明
1
•
6 个高效降压 DC-DC 转换器内核：
LP8754 旨在满足移动电话和类似便携式应用中最新应
用处理器的电源管理需求。 此器件包含 6 个降压 DC-
DC 转换器内核，一起捆绑在 6 相位降压转换器中，。
此器件由动态电压调节 (DVS) 接口或 I2C 兼容串行接
口完全控制。
–
–
–
–
–
最大输出电流为 10A
各内核捆绑到一个 6 相位转换器
负载电流报告
可编程过流保护 (OCP)
自动脉宽调制 (PWM)/脉冲频率调制 (PFM) 和
强制 PWM 操作以及自动低功耗模式设置
自动 PWM/PFM 操作搭配自动增相/切相功能，最大程
度提高了宽泛输出电流范围内的效率。 LP8754 支持
进行远程差分电压感测，以补偿稳压器输出与负载点之
间的 IR 下降，从而提高输出电压的精度。
–
–
–
–
自动增相/切相
远程差分反馈电压感测
输出电压斜升控制
保护特性包括短路保护、电流限制、输入
VOUT 范围为 0.6V 至 1.67V进行动态电压调节
OVP、UVLO、温度警告以及关断功能。 此器件还提
供多个错误标志，用于指示集成电路 (IC) 的状态信
息。 此外，I2C 回读信息包括总负载电流以及各降压内
核的负载电流：LP8754 无需添加电流感测电阻就能感
测到传递给负载的电流。在启动期间，器件会控制输出
电压转换率，以最大程度降低过冲和浪涌电流。
(DVS)
•
I2C 兼容接口，支持标准 (100kHz)、快速 (400kHz)
和高速 (3.4MHz) 三种模式
•
•
•
•
•
•
四个可选的 I2C 地址
具有可编程屏蔽的中断功能
输出短路和输入过压保护 (OVP)
扩展频谱与相位控制，用于降低电磁干扰 (EMI)
过温保护 (OTP)
器件信息(1)
器件型号
LP8754
封装
封装尺寸（最大值）
欠压闭锁 (UVLO)
DSBGA (49)
3.022mm x 2.882mm
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
2 应用
•
•
智能手机、电子书和平板电脑
效率与 负载电流间的关系
GSM、GPRS、EDGE、LTE、CDMA 和 WCDMA
手机
100
Low-Power PFM Mode
PFM Mode
•
游戏设备
PWM Mode
90
80
70
60
50
VIN = 3.7 V, VOUT = 1.1 V
1
10
100
1000
10000
OUTPUT CURRENT (mA)
C027
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SNVS861
LP8754
ZHCSDB8A –FEBRUARY 2014–REVISED AUGUST 2014
www.ti.com.cn
目录
7.3 Features Descriptions ............................................. 17
7.4 Device Functional Modes........................................ 25
7.5 Programming .......................................................... 27
7.6 Register Maps......................................................... 29
Application and Implementation ........................ 38
8.1 Application Information............................................ 38
8.2 Typical Application .................................................. 38
Power Supply Recommendations...................... 46
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ..................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions ...................... 5
6.4 Thermal Information.................................................. 6
6.5 General Electrical Characteristics............................. 7
6.6 6-Phase Buck Electrical Characteristics ................... 8
6.7 6-Phase Buck System Characteristics...................... 9
6.8 Protection Features Characteristics........................ 10
6.9 I2C Serial Bus Timing Parameters.......................... 12
6.10 Typical Characteristics.......................................... 14
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ....................................... 17
8
9
10 Layout................................................................... 46
10.1 Layout Guidelines ................................................. 46
10.2 Layout Example .................................................... 47
11 器件和文档支持 ..................................................... 48
11.1 器件支持................................................................ 48
11.2 文档支持 ............................................................... 48
11.3 商标....................................................................... 48
11.4 静电放电警告......................................................... 48
11.5 术语表 ................................................................... 48
12 机械封装和可订购信息 .......................................... 48
7
4 修订历史记录
日期
修订版本
注释
2014 年 8 月
版本 A
初始 Web 版本
2
Copyright © 2014, Texas Instruments Incorporated
LP8754
www.ti.com.cn
ZHCSDB8A –FEBRUARY 2014–REVISED AUGUST 2014
5 Pin Configuration and Functions
DSBGA (YFQ)
49 Pins
Top View
GND
GND
GND
B0
GND
B0
VIO
SYS
VLDO
GNDA
7
B3
B3
BUCK0
BUCK1
BUCK2
BUCK3
SW
B3
SW
B0
SW
B0
FB
B0+/B0
SW
B3
NSLP
INT
6
5
VIN
B3/B4
VIN
B0/B1
VIN
B0/B1
VIN
B0/B1
FB
B0-/B1
VIN
B3/B4
VIN
B3/B4
SW
B4
SW
B1
SW
B1
FB
B2
SW
B4
ADDR
NRST
BUCK4
BUCK5
4
3
2
1
GND
B4/B5
GND
B1/B2
GND
B1/B2
GND
B1/B2
FB
B3+/B3
GND
B4/B5
GND
B4/B5
SW
B5
SW
B2
SW
B2
SCL
SYS
FB
B3-/B4
SCL
SR
SW
B5
VIN
B5
VIN
B2
VIN
B2
SDA
SYS
FB
B5
SDA
SR
VDDA
5V
A
B
C
D
E
F
G
Pin Functions
PIN
TYPE
DESCRIPTION
NUMBER
NAME
Input for Buck 2. The separate power pins VINBXX are not connected together internally -
VINBXX pins must be connected together in the application and be locally bypassed.
A1, B1
VINB2
P
A2, B2
A3, B3, C3
A4, B4
SWB2
GNDB1/B2
SWB1
A
G
A
Buck 2 switch node
Power Ground for Buck 1 and Buck 2
Buck 1 switch node
Input for Buck 0 and Buck 1. The separate power pins VINBXX are not connected together
internally - VINBXX pins must be connected together in the application and be locally bypassed.
A5, B5, C5
VINB0/B1
P
A6, B6
A7, B7
C1
SWB0
GNDB0
SDASYS
SCLSYS
A
G
Buck 0 switch node
Power Ground for Buck 0
D/I/O
D/I
Serial interface data input and output for system access. Connect a pullup resistor.
Serial interface clock input for system access. Connect a pullup resistor.
C2
Serial bus address selection. Connect to GND (addr = 60h), VIOSYS (addr = 61h), SDASYS
(addr = 62h) or SCLSYS (addr = 63h).
C4
C6
ADDR
NSLP
D/I
D/I
Full Power to Low Power state transition control signal (By default active LOW for Low-Power
PFM mode)
Internal supply voltage capacitor pin. A ceramic low ESR 1-µF capacitor should be connected
from this pin to GNDA. The LDO voltage is generated internally, do NOT supply or load this pin
externally.
C7
VLDO
A
D1
D2
D3
D4
FBB5
FBB3−/B4
FBB3+/B3
FBB2
A
A
A
A
Not used for six-phase converter. Connect to GND.
Not used for six-phase converter. Connect to GND.
Not used for six-phase converter. Connect to GND.
Not used for six-phase converter. Connect to GND.
Copyright © 2014, Texas Instruments Incorporated
3
LP8754
ZHCSDB8A –FEBRUARY 2014–REVISED AUGUST 2014
www.ti.com.cn
Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NUMBER
NAME
Remote sensing (negative). Connect to the respective sense pin of the processor or to the
negative power supply trace of the processor as close as possible to the processor.
D5
FBB0−/B1
A
Remote sensing (positive). Connect to the respective sense pin of the processor or to the
positive power supply trace of the processor as close as possible to the processor.
D6
D7
E1
FBB0+/B0
GNDA
A
G
Ground
Serial Interface data input and output for Dynamic Voltage Scaling (DVS). Connect a pullup
resistor / connect to GND if not used.
SDASR
D/I/O
E2
E3, F3, G3
E4
SCLSR
GNDB4/B5
NRST
D/I
G
Serial Interface clock input for DVS. Connect a pullup resistor / connect to GND if not used.
Power Ground for Buck 4 and Buck 5
A
Voltage reference input for DVS interface. Setting NRST input HIGH triggers start-up sequence.
Input for Buck 3 and Buck 4.The separate power pins VINBXX are not connected together
internally - VINBXX pins must be connected together in the application and be locally bypassed.
E5, F5, G5
E6
VINB3/B4
INT
P
D/O
Open-drain interrupt output. Active LOW. Connect a pullup resistor to I/O supply.
This pin shall be tied to the system I/O-voltage. Bias supply voltage for the device. Enables the
I/O interface: All registers are accessible via serial bus interface when this pin is pulled high. An
internal power-on reset (POR) occurs when VIOSYS is toggled low/high. The I2C host should
allow at least 500 µs before sending data to the LP8754 after the rising edge of the VIOSYS line.
E7
VIOSYS
A
F1
VDDA5V
SWB5
P
A
A
A
G
Input for Analog blocks
Buck 5 switch node
Buck 4 switch node
Buck 3 switch node
Power Ground for Buck 3
F2, G2
F4, G4
F6, G6
F7, G7
SWB4
SWB3
GNDB3
Input for Buck 5. The separate power pins VINBXX are not connected together internally -
VINBXX pins must be connected together in the application and be locally bypassed.
G1
VINB5
P
A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin
4
Copyright © 2014, Texas Instruments Incorporated
LP8754
www.ti.com.cn
ZHCSDB8A –FEBRUARY 2014–REVISED AUGUST 2014
6 Specifications
6.1 Absolute Maximum Ratings
MIN
MAX
UNIT
INPUT VOLTAGE
Voltage on power connections (VIOSYS, VDDA5V, VINBXX)
−0.3
−0.3
6
6
V
Voltage on logic pins (input or output pins) (SCLSYS, SDASYS, NRST,
NSLP, ADDR, INT, SCLSR, SDASR)
Buck switch nodes (SWBXX)
−0.3
−0.3
−0.3
(VVINBXX + 0.2 V) with 6 V max
V
V
VLDO, FBB0+/B0, FBB0−/B1, FBB2, FBB3+/B3, FBB3−/B4, FBB5
All other analog pins
2
6
TEMPERATURE
Junction temperature (TJ-MAX
Maximum lead temperature (soldering, 10 s)(1)
)
150
260
150
°C
Storage temperature, Tstg
−65
(1) For detailed soldering specifications and information, please refer to Texas Instruments AN-1112: DSBGA Wafer-Level Chip-Scale
Package (SNVA009).
6.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
MAX
UNIT
INPUT VOLTAGE
Voltage on power connections (VDDA5V, VINBXX)
2.5
1.8
5
V
V
smaller of 3.3 V or
VVINBXX
Voltage on VIOSYS
SCLSYS, SDASYS, ADDR
SCLSR, SDASR, NSLP, INT
NRST
0
0
0
VVIOSYS
VNRST
1.8
V
V
V
TEMPERATURE
Junction temperature (TJ)
Ambient temperature (TA)
−40
−40
125
85
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground pin.
Copyright © 2014, Texas Instruments Incorporated
5
LP8754
ZHCSDB8A –FEBRUARY 2014–REVISED AUGUST 2014
www.ti.com.cn
6.4 Thermal Information
LP8754
YFQ
49 PINS
49.2
0.2
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJCtop
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
6.6
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.9
ψJB
6.5
RθJCbot
n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6
Copyright © 2014, Texas Instruments Incorporated
LP8754
www.ti.com.cn
ZHCSDB8A –FEBRUARY 2014–REVISED AUGUST 2014
6.5 General Electrical Characteristics
Minimum (MIN) and maximum (MAX) limits apply over the full ambient temperature range –40°C ≤ TA ≤ 85°C; typical (TYP)
values at TA = 25°C (unless otherwise noted). VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V (unless
otherwise noted).(1)(2)
PARAMETER
TEST CONDITIONS
VVIOSYS = 0 V, VNRST = 0 V
VVIOSYS = 1.8 V, VNRST = 0 V
MIN
TYP
0.1
50
MAX UNIT
CURRENTS
Shutdown supply current.
Total current into power
connections VDDA5V and
VINBXX
ISHDN
2
µA
Standby mode supply current.
Total current into power
connections VDDA5V and
VINBXX
ISTBY
Low-power PFM Mode, no load, one core
active
130
400
µA
µA
Active mode current
consumption. Total current
into power connections
VDDA5V and VINBXX
IActive
PFM Mode, no load, one core active
Forced PWM Mode, no load, one core
active
14.5
mA
LOGIC AND CONTROL INPUTS SCLSYS, SDASYS, ADDR
0.3 x
VVIOSYS
VIL
VIH
Vhys
Ci
Input low level
VVIOSYS = 1.8 V to 3.3 V
VVIOSYS = 1.8 V to 3.3 V
Input high level
0.7 x VVIOSYS
0.1 x VVIOSYS
V
Hysteresis of Schmitt trigger
inputs (SCLSYS, SDASYS)
Capacitance of pins
See(3)
4
pF
LOGIC AND CONTROL INPUTS SCLSR, SDASR, NSLP, NRST
VIL
VIH
Input low level
Input high level
VNRST = 1.8 V
VNRST = 1.8 V
0.3 x VNRST
0.7 x VNRST
0.1 x VNRST
V
Hysteresis of Schmitt trigger
inputs (SCLSR, SDASR)
Vhys
Capacitance of SCLSR and
SDASR pins
Ci
4
pF
RIN
Input resistance
NRST pulldown resistor to GND
1200
kΩ
VIL_NRST Input low level NRST
VIH_NRST Input high level NRST
LOGIC AND CONTROL OUTPUTS
0.54
V
1.3
Voltage on INT pin, ISINK = 3 mA,
VNRST = VVIOSYS = 1.8 V
0.4
VOL
Output low level
V
Voltage on SDASYS, SDASR, ISINK = 3
mA,
0.36
VNRST = VVIOSYS = 1.8 V
RP
External pullup resistor for INT To I/O Supply
10
kΩ
ALL LOGIC AND CONTROL INPUTS
All logic inputs over pin voltage range.
Note that NRST pin does have an 1.2-MΩ
internal pulldown resistor and current
through this resistor is not included into
ILEAK rating. TA = 25°C
ILEAK
Input current
−1
1
µA
(1) All voltage values are with respect to network ground pin.
(2) Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. Typical (Typ.) numbers are not ensured,
but do represent the most likely norm.
(3) Maximum capacitance of SCLSYS or SDASYS line is 8 pF, if ADDR pin is connected to line for serial bus address selection.
Copyright © 2014, Texas Instruments Incorporated
7
LP8754
ZHCSDB8A –FEBRUARY 2014–REVISED AUGUST 2014
www.ti.com.cn
6.6 6-Phase Buck Electrical Characteristics
Minimum (MIN) and maximum (MAX) limits apply over the full ambient temperature range –40°C ≤ TA ≤ 85°C; typical (TYP)
values at TA = 25°C (unless otherwise noted). VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V (unless
otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
PWM Mode, VOUTSET = 0.6 V to 1.67 V,
I
min
max(VOUTS
ET + 2.5%,
VOUTSET
OUT ≤ 10 A(2)
(VOUTSET
–
2.5%,
VOUTSET – 25
mV)
VOUTSET
+
25 mV)
PFM Mode, VOUTSET = 0.6 V to 1.67 V,
OUT ≤ 375 mA
min
(VOUTSET –
2.5%,
VOUTSET – 25
mV)
Differential feedback
voltage(1)
VFB0+/B0 - VFB0-/B1
max(VOUTS
ET + 2.5%,
VOUTSET +
I
VFB
V
VOUTSET
25 mV)
Low-Power PFM Mode, VOUTSET = 0.6 V
to 1.67 V,
min
max(VOUTS
ET + 3%,
VOUTSET +
(VOUTSET
–
–
VOUTSET
IOUT ≤ 30 mA
3%, VOUTSET
30 mV)
2050
650
30 mV)
3300
1050
1.67
ILIMITP
ILIMITN
High side switch current limit 2.5-A register setting
Low side switch current limit Reverse current
2600
900
1.1
10
mA
Range, programmable by register setting
0.6
V
VOUT
Output voltage
Step
mV
MHz
fSW
Switching frequency
Pin-pin resistance for PFET
2.5 V ≤ VVINBXX ≤ 5 V
Test current = 200 mA; Split FET
Test current = 200 mA; Full FET
2.7
3.0
120
60
3.4
RDSON_P
mΩ
RDSON_N
ILK_HS
Pin-pin resistance for NFET IOUT = –200 mA
50
High-side leakage current
Low-side leakage current
VSW = 0 V, Per Buck Core
2
2
µA
ILK_LS
VSW = 3.7 V = VVINBXX, per buck core
Enabled via control register, Active only
when converter disabled, Per Buck Core
RPD
Pull-down resistor
250
300
Ω
Differential feedback Input
resistance(3)
RIN_FB
TA = 25°C
200
400
kΩ
(1) Due to the nature of the converter operating in PFM Mode/Low-Power Mode, the feedback voltage accuracy specification is for the lower
point of the ripple. Thus the converter will position the average output voltage typically slightly above the nominal PWM-Mode output
voltage.
(2) The power switches in the LP8754 are designed to operate continuously with currents up to the switch current limit thresholds. However,
when continuously operating at high current levels there will be significant heat generated within the IC and thus sustained total DC
current which the device can support is typically limited by thermal constraints. Thermal issues will become extremely important when
designing PCB and the thermal environment of the LP8754. PCB with high thermal efficiency is required to ensure the junction
temperature is kept below 125°C. Completing thermal analyses in early stages of the product design process is highly recommended to
predict thermal performance at board level. Under high current load conditions the serial bus master device must monitor the
temperature of the converter using the Thermal warning feature, see Protection Features Characteristics. If the 2nd thermal warning is
triggered at 120°C, the application must quickly decrease the load current to keep the converter within its recommended operating
temperature.
(3) Datasheet min/max specification limits are specified by design.
8
Copyright © 2014, Texas Instruments Incorporated
LP8754
www.ti.com.cn
ZHCSDB8A –FEBRUARY 2014–REVISED AUGUST 2014
6.7 6-Phase Buck System Characteristics
Minimum (MIN) and maximum (MAX) limits apply over the full ambient temperature range –40°C ≤ TA ≤ 85°C; typical (TYP)
values at TA = 25°C (unless otherwise noted). VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V (unless
otherwise noted).
PARAMETER
TEST CONDITIONS
Programmable via control register(1)
RAMP_B0[2:0] = 000
MIN
TYP
MAX
UNIT
30
15
RAMP_B0[2:0] = 001
RAMP_B0[2:0] = 010
7.5
KRAMP
Ramp timer
RAMP_B0[2:0] = 011
3.8
mV/µs
RAMP_B0[2:0] = 100
1.9
RAMP_B0[2:0] = 101
0.94
0.47
0.23
25
RAMP_B0[2:0] = 110
RAMP_B0[2:0] = 111
TSTART
TRAMP
Start-up time
Time from NRST-HIGH to start of switching
Time to ramp from 5% to 95% of VOUT
Average output current, programmable via
µs
µs
VOUT rise time
20
(2)
control register, VOUT = 1.1 V.
PFM_EXIT_B0[2:0] = 011
175
225
275
325
375
PFM-to-PWM switch–over
current threshold
PFM_EXIT_B0[2:0] = 100
IPFM–PWM
mA
PFM_EXIT_B0[2:0] = 101
PFM_EXIT_B0[2:0] = 110
PFM_EXIT_B0[2:0] = 111
Average output current, Programmable via
(2)
control register, VOUT = 1.1 V
PFM_ENTRY_B0[2:0] = 000
PFM_ENTRY_B0[2:0] = 001
PFM_ENTRY_B0[2:0] = 010
PFM_ENTRY_B0[2:0] = 011
PFM_ENTRY_B0[2:0] = 100
ADD_PH_B0[2:0] = 010
ADD_PH_B0[2:0] = 011
ADD_PH_B0[2:0] = 100
ADD_PH_B0[2:0] = 101
ADD_PH_B0[2:0] = 110
ADD_PH_B0[2:0] = 111
SHED_PH_B0[2:0] = 000
SHED_PH_B0[2:0] = 001
SHED_PH_B0[2:0] = 010
SHED_PH_B0[2:0] = 011
SHED_PH_B0[2:0] = 100
SHED_PH_B0[2:0] = 101
100
125
150
175
225
500
600
700
800
900
1000
300
400
500
600
700
800
PWM-to-PFM switchover current
threshold
IPWM–PFM
mA
IADD
Phase adding level
mA
mA
ISHED
Phase shedding level
(1) In the real application, achievable output voltage ramp profiles are influenced by a number of factors, including the amount of output
capacitance, the load current level, the load characteristic (either resistive or constant-current), and the voltage ramp amplitude. Typical
values are measured with typical conditions. The falling edge ramp rate can be limited by the negative current limit ILIMITN
.
(2) The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependant on the output voltage, input voltage, and
the inductor current level. Typical values are measured with typical conditions.
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6-Phase Buck System Characteristics (continued)
Minimum (MIN) and maximum (MAX) limits apply over the full ambient temperature range –40°C ≤ TA ≤ 85°C; typical (TYP)
values at TA = 25°C (unless otherwise noted). VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V (unless
otherwise noted).
PARAMETER
TEST CONDITIONS
2.5 V ≤ VVINBXX ≤ 5 V
ILOAD = 1 A, forced PWM
MIN
TYP
MAX
UNIT
Line regulation
0.05
%/V
Load regulation in PWM mode of 100 mA ≤ ILOAD ≤ 10 A, Differential sensing
0.2
±30
±20
±60
%/A
mV
mV
mV
operation
enabled
AUTO (no Low-Power PFM) mode, IOUT 0.5
mA → 500 mA → 0.5 mA, 100 ns load step
ΔVOUT
PWM mode, IOUT 0.6 A → 2 A → 0.6 A, 400-ns
load step
Transient load step response
PWM mode, IOUT 1 A → 8 A → 1 A, 400-ns
load step
VVINBXX stepping 3.3 V <—> 3.8 V, tr = tf = 10
Transient line response
Output current
µs,
±15
mV
mA
µF
IOUT = 2000 mA DC
DC load each phase
Six phases combined(3)
1670
IOUT
10000
Effective capacitance during operation, VOUT
0.6 V to 1.67 V, Min value over TA –40°C to
85°C
=
COUT
Output capacitance(4)
30
50
10
Input capacitance on each input Effective capacitance during operation, 2.5 V ≤
CIN
2.5
µF
µH
voltage rail(4)(5)
VVINBXX ≤ 5 V
L
Output inductance
Effective inductance during operation
0.25
0.47
1
IBALANCE
Current balancing accuracy
IOUT ≥ 1000 mA
< 10%
COUT ESR = 10 mΩ
PWM mode, IOUT = 200 mA
Switching frequency = 3 MHz
Output voltage ripple PWM
mode, One phase active(6)
VRIPPLE_PWM
VRIPPLE_PFM
VRIPPLE_LP
7
8
8
mVPP
mVPP
mVPP
COUT ESR = 10 mΩ
PFM mode
IOUT = 100 µA
Output voltage ripple PFM
mode(6)
COUT ESR = 10 mΩ
Low-power PFM mode
IOUT = 100 µA
Output Voltage Ripple Low-
Power PFM mode(6)
(3) The power switches in the LP8754 are designed to operate continuously with currents up to the switch current limit thresholds. However,
when continuously operating at high current levels there will be significant heat generated within the IC and thus sustained total DC
current which the device can support is typically limited by thermal constraints. Thermal issues will become extremely important when
designing PCB and the thermal environment of the LP8754. PCB with high thermal efficiency is required to ensure the junction
temperature is kept below 125°C. Completing thermal analyses in early stages of the product design process is highly recommended to
predict thermal performance at board level. Under high current load conditions the serial bus master device must monitor the
temperature of the converter using the Thermal warning feature, see Protection Features Characteristics. If the 2nd thermal warning is
triggered at 120°C, the application must quickly decrease the load current to keep the converter within its recommended operating
temperature.
(4) Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. The performance of the LP8754 device
depends greatly on the care taken in designing the Printed Circuit Board (PCB). The use of low inductance and low serial resistance
ceramic capacitors is strongly recommended, while proper grounding is crucial. Attention should be given to decoupling the power
supplies. Decoupling capacitors must be connected close to the IC and between the power and ground pins to support high peak
currents being drawn from System Power Rail during turn-on of the switching MOSFETs. Keep input and output traces as short as
possible, because trace inductance, resistance and capacitance can easily become the performance limiting items.
(5) In addition to these capacitors, at least one higher value capacitor (for example, 22 µF) should be placed close to the power pins. Note
that cores B0-B1 and B3-B4 do have combined power input pins.
(6) Ripple voltage should be measured at COUT electrode on a well-designed PCB, using suggested inductors and capacitors and with a
high-quality scope probe.
6.8 Protection Features Characteristics
Minimum (MIN) and maximum (MAX) limits apply over the full ambient temperature range –40°C ≤ TA ≤ 85°C; typical (TYP) at
TA = 25°C (unless otherwise noted). VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V (unless otherwise
noted).
10
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Protection Features Characteristics (continued)
Minimum (MIN) and maximum (MAX) limits apply over the full ambient temperature range –40°C ≤ TA ≤ 85°C; typical (TYP) at
TA = 25°C (unless otherwise noted). VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V (unless otherwise
noted).
PARAMETER
VOLTAGE MONITORING
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power good threshold for voltage
decreasing, % of setting, VOUT = 1.1 V
VPG
Power good threshold voltage
90%
5.3
Input overvoltage protection trigger
point(1)(2)
VIN rising. Voltage monitored on VDDA5V
pin
VOVP
5.15
2.15
5.45
2.35
V
Input undervoltage lockout (UVLO)
turn-on threshold(1)
VIN falling. Voltage monitored on VDDA5V
pin
VUVLO
VSCP
2.25
400
400
400
Detected by sensing the voltage on
converter output with respect to GND.
Output short-circuit fault threshold
SCP masking time
mV
µs
Triggered by converter start-up, specified by
design
tMASKSCP
Triggered by converter start-up, specified by
design
µs
Triggered by VSET transition, specified by
design
Slew Rate setting mV/µs
30
50
100
15
tMASKPG
Power Good masking time
7.5
200
3.8
400
µs
1.9
800
0.94
0.47
0.23
1600
3200
6400
(1) Undervoltage lockout (UVLO) and overvoltage protection (OVP) circuits shut down the LP8754 when the system input voltage is outside
the desired operating range.
(2) Limits for OVP trigger points apply when VVIOSYS is high. False OVP alarm may occur, if the input voltage rises close to 5 V while
VVIOSYS is low.
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Protection Features Characteristics (continued)
Minimum (MIN) and maximum (MAX) limits apply over the full ambient temperature range –40°C ≤ TA ≤ 85°C; typical (TYP) at
TA = 25°C (unless otherwise noted). VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THERMAL SHUTDOWN AND MONITORING
TSHUT
Thermal shutdown (TSD)
Thermal warning
Threshold, Temperature rising
Hysteresis
Temperature rising, 1st warning, Interrupt
only
150
25
85
°C
Hysteresis
10
TWARN
Thermal warning prior to TSD
Temperature rising, 2nd warning, Interrupt
and flag set
120
Hysteresis
10
6.9 I2C Serial Bus Timing Parameters
Serial bus address is selected by the ADDR pin. Connect the pin to GND (addr = 60h), VIOSYS (addr = 61h), SDASYS (addr
= 62h), or SCLSYS (addr = 63h). Both of the serial buses share the same address; that is, if addr = 60h is selected for the
System bus, the Dynamic Voltage Scaling bus will respond to the same address. Start conditions are used to secure the I2C
slave address. During the I2C bus start condition, it is detected whether the ADDR is connected to SDASYS, SCLSYS, GND,
or VIOSYS. The I2C host should allow at least 500 µs before sending data to the LP8754 after the rising edge of the VIOSYS
line.
These specifications are ensured by design. Limits apply over the full ambient temperature range –40°C ≤ TA ≤ 85°C, VVDDA5V
= VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V (unless otherwise noted) (See Figure 1) .
MIN
NOM
MAX
UNIT
DIGITAL TIMING SPECIFICATIONS (SCL, SDA)(1)(2)(3)
Standard mode
100
400
3.4
kHz
kHz
Fast mode
fCLK
Serial clock frequency
High-speed mode, Cb = 100 pF (max)
High-speed mode, Cb = 400 pF (max)(4)
Standard mode
MHz
MHz
1.7
4.7
1.3
160
320
4
µs
ns
µs
ns
Fast mode
tLOW
SCL low time
High-speed mode, Cb = 100 pF (max)
High-speed mode, Cb = 400 pF (max)(4)
Standard mode
Fast mode
0.6
60
120
250
100
10
0
tHIGH
SCL high time
Data setup time
Data hold time
High-speed mode, Cb = 100 pF (max)
High-speed mode, Cb = 400 pF (max)(4)
Standard mode
tSU;DAT
Fast mode
ns
High-speed mode
Standard mode
3.45
0.9
µs
ns
Fast mode
0
tHD;DAT
High-speed mode, Cb = 100 pF (max)
High-speed mode, Cb = 400 pF (max)(4)
0
70
0
150
(1) Unless otherwise stated, 'SDA' in this paragraph refers to both of the SDASR and SDASYS signals, and respectively 'SCL' refers to
SCLSR and SCLSYS signals.
(2) Cb refers to the capacitance of one bus line. Cb is expressed in pF units. The specification table provided applies to both of the
interfaces; DVS and System interface.
(3) The power-on default setting for the system bus and the DVS bus is High-speed-enabled, there is no handshaking required to initiate
high speed.
(4) For bus line loads Cb between 100 pF and 400 pF the timing parameters must be linearly interpolated.
12
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I2C Serial Bus Timing Parameters (continued)
Serial bus address is selected by the ADDR pin. Connect the pin to GND (addr = 60h), VIOSYS (addr = 61h), SDASYS (addr
= 62h), or SCLSYS (addr = 63h). Both of the serial buses share the same address; that is, if addr = 60h is selected for the
System bus, the Dynamic Voltage Scaling bus will respond to the same address. Start conditions are used to secure the I2C
slave address. During the I2C bus start condition, it is detected whether the ADDR is connected to SDASYS, SCLSYS, GND,
or VIOSYS. The I2C host should allow at least 500 µs before sending data to the LP8754 after the rising edge of the VIOSYS
line.
These specifications are ensured by design. Limits apply over the full ambient temperature range –40°C ≤ TA ≤ 85°C, VVDDA5V
= VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V (unless otherwise noted) (See Figure 1) .
MIN
4.7
0.6
160
4.0
0.6
160
4.7
1.3
4.0
0.6
160
NOM
MAX
UNIT
Standard mode
µs
Set-up time for a repeated
start condition
tSU;STA
Fast mode
High-speed mode
ns
Standard mode
µs
Hold time for a start or a
repeated start condition
tHD;STA
Fast mode
High-speed mode
ns
Standard mode
Bus free time between a stop
and start condition
tBUF
µs
Fast mode
Standard mode
µs
Set-up time for a stop
condition
tSU;STO
Fast mode
High-speed mode
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Standard mode
1000
300
80
Fast mode
20
10
20
trDA
Rise time of SDA signal
Fall time of SDA signal
Rise time of SCL signal
High-speed mode, Cb = 100 pF (max)
High-speed mode, Cb = 400 pF (max)(4)
Standard mode
160
300
300
80
Fast Mode
6.5
10
20
tfDA
High-speed mode, Cb = 100 pF (max)
High-speed mode, Cb = 400 pF (max)(4)
Standard mode
160
1000
300
40
Fast mode
20
10
20
10
trCL
trCL1
tfCL
High-speed mode, Cb = 100 pF (max)
High-speed mode, Cb = 400 pF (max)(4)
High-speed mode, Cb = 100 pF (max)
80
Rise time of SCL signal after
a repeated start condition and
after acknowledge bit
80
High-speed mode, Cb = 400 pF (max)(4)
20
160
ns
Standard mode
300
300
40
ns
ns
ns
ns
Fast mode
6.5
10
20
Fall time of a SCL signal
High-speed mode, Cb = 100 pF (max)
High-speed mode, Cb = 400 pF (max)(4)
80
Capacitive load for each bus
line (SCL and SDA)
Cb
400
pF
ns
Fast mode
50
10
Pulse width of spike
suppressed(5)
tSP
High-speed mode
(5) Spike suppression filtering on SCLSYS, SCLSR, SDASYS and SDASR will suppress spikes that are less than the indicated width.
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t
BUF
SDA
t
t
HD;STA
t
fDA
t
rDA
rCL
t
t
LOW
fCL
t
SP
SCL
tHD;STA
t
t
SU;STA
SU;STO
t
HIGH
t
HD;DAT
t
SU;DAT
START
STOP START
REPEATED
START
Figure 1. I2C Timing
6.10 Typical Characteristics
Unless otherwise specified: VVDDA5V = VVINBXX = 3.7 V, VOUT = 1.1 V, TA = 25°C
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
500 mA
600 mA
700 mA
800 mA
900 mA
1000 mA
300 mA
400 mA
500 mA
600 mA
700 mA
800 mA
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
LOAD CURRENT (A)
LOAD CURRENT (A)
C017
C018
Figure 2. Phase Adding vs Load Current with
Different Level Settings
Figure 3. Phase Shedding vs Load Current with
Different Level Settings
55.0
54.0
53.0
52.0
51.0
50.0
49.0
48.0
47.0
140
138
136
134
132
130
128
126
124
122
120
2.5
3.0
3.5
4.0
4.5
5.0
2.5
3.0
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
C010
C001
VVIOSYS = 1.8 V
VNRST = 0 V
Low-Power Mode
No load
One core active
Figure 4. Standby Mode Current Consumption vs VIN
Figure 5. Low-Power PFM Mode Current Consumption vs
VIN
14
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Typical Characteristics (continued)
Unless otherwise specified: VVDDA5V = VVINBXX = 3.7 V, VOUT = 1.1 V, TA = 25°C
388.0
387.5
387.0
386.5
386.0
385.5
385.0
16.0
15.5
15.0
14.5
14.0
13.5
13.0
2.5
3.0
3.5
4.0
4.5
5.0
2.5
3.0
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
C002
C003
PFM Mode
No load
One core active
PWM Mode
No load
One core active
Figure 6. PFM Mode Current Consumption vs VIN
Figure 7. PWM Mode Current Consumption vs VIN
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7 Detailed Description
7.1 Overview
The LP8754 is a high-efficiency, high-performance power supply IC with six step-down DC-DC converter cores. It
delivers 0.6 V to 1.67 V regulated voltage rail from either a single Li-Ion or three cell NiMH/NiCd batteries to
portable devices such as cell phones and PDAs.
There are three modes of operation for the 6-phase converter, depending on the output current required: PWM
(Pulse Width Modulation), PFM (Pulse-Frequency Modulation), and Low-Power PFM. Converter operates in
PWM mode at high load currents of approximately 250 mA or higher, depending on register setting. Lighter
output current loads will cause the converter to automatically switch into PFM or Low-Power PFM mode for
reduced current consumption and a longer battery life. Forced PWM is also available for highest transient
performance.
Under no-load conditions the device can be set to Standby or Shutdown. Shutdown mode turns off the device,
offering the lowest current consumption (ISHDN = 0.1 µA typ.). Additional features include soft-start, undervoltage
lockout, input overvoltage protection, current overload protection, thermal warning, and thermal shutdown.
The modes and features can be programmed via control registers. All the registers can be accessed with both
I2C serial interfaces: System serial interface and Dynamic voltage scaling (DVS) interface. Using DVS interface
for dynamic voltage scaling prevents latencies if System serial interface is busy. Using DVS interface is optional;
System serial interface can also be used for dynamic voltage scaling.
7.1.1 Buck Information
The LP8754 has six integrated high-efficiency buck converter cores. The cores are designed for flexibility; most
of the functions are programmable, thus allowing optimization of the SMPS operation for each application. The
cores are bundled together to establish a multi-phase converter This is shown in Figure 24.
Operating Modes:
•
OFF: Output is isolated from the input voltage rail in this mode. Output has an optional pulldown resistor
which can be enabled with BUCK0_CTRL.RDIS_B0 bit.
•
•
PWM: Converter operates in buck configuration. Average switching frequency is constant.
PFM: Converter switches only when output voltage decreases below programmed threshold. Inductor current
is discontinuous.
•
Low-Power PFM: This mode is similar to PFM mode, but used with lower load conditions. In this mode some
of the internal blocks are turned off between the PFM pulses. Load transient response is compromised due to
the wake-up time.
Features:
•
•
•
•
•
•
•
•
•
•
•
•
DVS support
Automatic mode control based on the loading
Synchronous rectification
Current mode loop with PI compensator
Soft start
Power good flag with maskable interrupt
Overvoltage comparator
Phase control and spread spectrum techniques for reducing EMI
Average output current sensing (for PFM/PWM entry/exit, phase adding/shedding, and load current reporting)
Current balancing between the phases of the converter
Differential voltage sensing
Dynamic phase adding/shedding, each output being phase shifted
16
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Overview (continued)
Programmability (The following parameters can be programmed via registers):
•
•
•
•
•
•
Output voltage
Forced PWM operation
Switch current limits for high side FET
PWM/PFM mode entry and exit (based on average output current)
Phase adding and shedding levels
Output voltage slew rate
7.2 Functional Block Diagram
LP8754
VLDO
INTERNAL
LDO
FBB0+ / B0
FBB0- / B1
1
F
POWER
INPUTS
Configurable
Feedback
Amplifiers
FBB2
SYSTEM
POWER
FBB3+ / B3
FBB3- / B4
FBB5
Logic Control
(chip EN)
VIOSYS
SWB0
SWB1
SWB2
SWB3
SWB4
SWB5
Buck 0 /
Master 0
SCLSYS
SYS IO
Domain
EPROM
SDASYS
ADDR
Buck 1
Buck 2
Reference
Voltage
SCLSR
SDASR
Oscillator
INT
SR IO
Domain
Buck 3 /
Master 1
Thermal
Monitoring
NSLP
NRST
Buck 4
Buck 5
Voltage
Monitoring
Internal
Pull-down
1.1 M
POWER
GROUNDS
AGND
7.3 Features Descriptions
7.3.1 Multi-Phase DC-DC Converters
A multi-phase synchronous buck converter offers several advantages over a single power-stage converter. For
application processor power delivery, lower ripple on the input and output currents and faster transient response
to load steps are the most significant advantages. Also, since the load current is evenly shared among multiple
channels, the heat generated is greatly reduced for each channel due to the fact that power loss is proportional
to square of current. Physical size of the output inductor shrinks significantly for the similar reason.
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Features Descriptions (continued)
PMOS
CURRENT
SENSE
DIFFERENTIAL TO
SINGLE-ENDED
FBP
+
VIN
SW
POS
CURRENT
LIMIT
SLAVE
PHASE
CONTROL
-
FBN
RAMP
GENERATOR
V
OUT
-
GATE
CONTROL
ERROR
AMP
+
LOOP
COMP
VOLTAGE
NEG
CURRENT
LIMIT
POWER
GOOD
+
SETTING
SLEW RATE
CONTROL
VDAC
-
ZERO
CROSS
DETECT
NMOS
CURRENT
SENSE
MASTER
INTERFACE
PROGRAMMABLE
PARAMETERS
CONTROL
BLOCK
SLAVE
INTERFACE
IADC
GND
Figure 8. Detailed Block Diagram Showing One Buck Core
7.3.1.1 Multi-Phase Operation and Phase-Shedding
Under heavy load conditions, the switching phase of the bucks are interleaved. As a result, the 6-phase
converter has higher effective switching frequency than the switching frequency of any one phase.
The parallel operation decreases the efficiency at low load conditions. In order to overcome this operational
inefficiency, the LP8754 automatically changes the number of active phases to maximize the efficiency. This is
called phase-shedding and the concept is illustrated in Figure 9.
BEST EFFICIENCY OBTAINED WITH
N=1
N=2
N=3
N=6
N=4
N=5
LOAD CURRENT
(1)
Figure 9. Multi-phase Buck Converter Efficiency vs Number of Phases; All Converters in PWM Mode
(1) Graph is not to scale and is for illustrative purposes only.
18
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Features Descriptions (continued)
7.3.1.2 Transitions Between Low-Power PFM, PFM, and PWM Modes
Normal PWM-mode operation with phase-shedding can optimize efficiency at mid-to-full load, but this is usually
at the expense of light-load efficiency. The LP8754 converter operates in PWM mode at a load current of 100 to
375 mA or higher; this mode transition trip-point is set by register. Lighter load current causes the device to
automatically switch into PFM mode for reduced current consumption. By combining PFM and PWM modes in
the same regulator and providing automatic switching, high efficiency can be achieved over a wide output load
current range.
Efficiency is further enhanced when the converter enters Low-Power PFM mode. The LP8754 includes Low-
Power mode function for low-current consumption. In this mode most of the internal blocks are disabled between
the inductor current ramp up and ramp down phases to reduce the operating current. However, as a result, the
transient performance of the converter is compromised. The Low-Power mode can be enabled by control register
setting. Also, the application processor or the PMIC may provide an HW signal (NSLP) to the LP8754 input to
indicate when the processor has entered a low-power state. When the signal is asserted, the LP8754 Low-Power
PFM function will be enabled, and the LP8754 will run with a reduced input current. The right timing of the NSLP
signal from the system is important for best load-transient performance. The NSLP signal should be asserted
only when load current is stable and below 30 mA. Before the load current increases above 30 mA, the NSLP
signal should be de-asserted 100 µs (minimum) prior to a load step to prepare the converter for the higher load
current.
7.3.1.3 Buck Converter Load Current
The buck load current can be monitored via I2C registers. Current of different buck converter cores or the total
load current of the master can be selected from register 0x21 (see SEL_I_LOAD). A write to this selection
register starts a current measurement sequence. The measurement sequence is a minimum of 50 µs long. When
a measurement sequence starts, the FLAGS_1.I_LOAD_READY bit in register 0x0E is set to '0'. After the
measurement sequence is finished, the FLAGS_1.I_LOAD_READY bit is set to '1'. (Note that by default this bit is
'0'.) The measurement result can be read from registers 0x22 (LOAD_CURR.BUCK_LOAD_CURR[7:0]) and
0x21 (SEL_I_LOAD.BUCK_LOAD_CURR[10:8]). The measurement result [10:0] LSB is 10 mA, and the
maximum value of the measurement is 20 A. The LP8754 can be configured to give out an interrupt after the
load current measurement sequence is finished. Load current measurement interrupt can be masked with
INT_MASKS_2.MASK_I_LOAD_READY bit.
7.3.1.4 Spread Spectrum Mode
Systems with periodic switching signals may generate a large amount of switching noise in a set of narrowband
frequencies (the switching frequency and its harmonics). The usual solution to reduce noise coupling is to add
EMI-filters and shields to the boards. The LP8754's register-selectable spread spectrum mode minimizes the
need for output filters, ferrite beads, or chokes. In spread spectrum mode, the switching frequency varies
randomly around the center frequency, reducing the EMI emissions radiated by the converter, associated passive
components, and PCB traces. See Figure 10.
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Features Descriptions (continued)
FREQUENCY
Where a fixed-frequency converter exhibits large amounts of spectral energy at the switching frequency, the spread
spectrum architecture of the LP8754 spreads that energy over a large bandwidth.
Figure 10. Spread Spectrum Modulation
7.3.2 Power-Up and Output Voltage Sequencing
The power-up sequence for the LP8754 is as follows:
•
•
VVINBXX and VVDDA5V reach min recommended levels.
VVIOSYS set high. Enables the system I/O interface. For power-on-reset (POR), the I2C host should allow at
least 500 µs before sending data to the LP8754 after the rising edge of the VIOSYS line.
•
•
•
•
•
VLDO voltage is raising. The LDO voltage is generated internally. The internal POR signal is activated.
Internal POR deasserted, OTP read.
Device enters standby mode.
DC-DC enable, output voltage, voltage slew rate programmed over I2C as needed by the application.
NRST set high. The DC-DC converter can be enabled and disabled by VSET_B0.EN_DIS_B0 bit or using the
NRST signal.
VVDDA5V
t
0
VVIOSYS
LDO
(internal)
t
1
t2
NRST
LP8754 receiving/sending data across the system I2C bus.
t
I2CT
Figure 11. Timing Diagram for the Power-Up Sequence
20
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Features Descriptions (continued)
Table 1. Power-Up Sequence
PARAMETER
CONDITION(1)
MIN
TYP
MAX
UNIT
µs
t0
t1
VVDDA5V to VVIOSYS assertion
0
LDOON Delay Time
LDOON to NRST HIGH
CLDO = 1 µF
<100
150
µs
t2
0
µs
tI2CT
Device ready for I2C data transfer
500
µs
(1) These specification table entries are specified by design. The power input lines VVINBXX, VVDDA5V and VVIOSYS must be stable before the
NRST line goes High. Also, the VLDO line must be stable 1.8 V before the NRST line goes High.
7.3.3 Device Reset Scenarios
There are three reset methods implemented on the LP8754:
•
•
•
Software reset
Hardware reset
Power-on reset (POR)
An SW-reset occurs when the RESET.SW_RESET bit is written first with 1, followed by 0 right after that. This
event resets the control registers shown in Table 2 to the default values. The temperature, power good, and
other faults are persistent over the SW reset to allow for the system to identify to cause of the failure.
An internal power-on reset (POR) occurs when the supply voltage (VVDDA5V) transitions above the POR threshold
or VVIOSYS is toggled low/high. Each of the registers contain a factory-defined value upon POR, and this data
remains there until any of the following occurs:
•
•
Device sets a Flag bit, causing the Status register to be updated. The other registers remain untouched.
A different data word is written to a writable register.
The internal registers will lose their contents if the supply voltage (VVDDA5V) goes below 1 V (typ.).
An NRST high-to-low transition initiates the hardware reset. This event resets the control registers shown in
Table 2 to the default values.
Under OVP, UVLO, TSD, or VVIOSYS low (while NRST still high) conditions, a Fast Power-Down is launched.
Normal Power-Down Sequence Follows This Event
(Marked as '1')
Fast Power-Down Follows This Event
VVDDA5V
VVIOSYS
NRST
VVDDA5V
2
VVIOSYS
1
NRST
Figure 12. The External Power Control System De-
asserts NRST
Figure 13. NRST Stays HIGH While VVIOSYS
Transition from HIGH to LOW Happens (Marked as
'2')
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Inductor Current Dropping to Zero in ~2 µs (All
Converters, All Phases)
t
t
RST2
RST1
HW RST by NRST
OTP_MEM_READ
t
RST2
SW RST by I2C
OTP_MEM_READ
0
Time
~2 Ps
Figure 14. Fast Power-Down
Figure 15. Reset Timings
PARAMETER
LIMIT
tRST1
tRST2
NRST active low pulse width
NRST inactive or I2C reset
1 µs min + value on DELAY_BUCK0 register.
25 µs max
event to MEMORY READ end
Table 2. Hardware Reset, Power-On Reset (POR) and Software Reset: Registers After Reset
SOFTWARE RESET
I2C RESET
HARDWARE RESET
POWER-ON RESET
VVIOSYS LOW
(1)
HEX ADDRESS
0x00
REGISTER
VSET_B0
NRST LOW
All bits retained
All bits cleared
All bits cleared
All bits retained
All bits retained
All bits cleared
All bits cleared
N/A
All bits retained
All bits cleared
All bits cleared
All bits retained
All bits retained
All bits cleared
All bits cleared
All bits cleared
All bits cleared
Read Only
All bits cleared
All bits cleared
All bits cleared
All bits cleared
All bits cleared
All bits cleared
All bits cleared
All bits cleared
All bits cleared
0x06
FPWM
0x07 to 0x0C
0x0D
BUCK0_CTRL to BUCK5_CTRL
FLAGS_0
0x0E
FLAGS_1
0x0F
INT_MASK0
GENERAL
0x10
0x11
RESET
0x12
DELAY_BUCK0
CHIP_ID
All bits cleared
0x18
0x19
PFM_LEV_B0
PHASE_LEV_B0
SEL_I_LOAD
LOAD_CURR
INT_MASK_2
All bits cleared
All bits cleared
All bits retained
All bits cleared
All bits cleared
All bits retained
Read Only
All bits cleared
All bits cleared
All bits cleared
0x1F
0x21
0x22
0x2E
All bits cleared
All bits cleared
All bits cleared
(1) Reset is falling-edge sensitive and it will take effect upon complete of the power-down sequence. The registers can be updated by I2C
writing when NRST is low.
22
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7.3.4 Diagnosis and Protection Features
The LP8754 is capable of providing two levels of protection features: warnings for diagnosis and faults which are
causing the converters to shut down. When the device detects warning or fault conditions, the LP8754 sets the
flag bits indicating which fault or warning conditions have occurred; the INT pin will be pulled low. INT will be
released again after a clear of flags is complete. The flag bits are persistent over reset to allow for the system to
identify what was causing the interrupt and/or converter shutdown.
Also, the LP8754 has a soft-start circuit that limits in-rush current during start-up. The output voltage increase
rate is 30 mV/µs (default) during soft-start.
Table 3. Summary of Exceptions and Interrupt Signals
EVENT
REGISTER.BIT
INTERRUPT SIGNAL
PRODUCED?
INT MASK AVAILABLE?
SCP triggered
Not PowerGood
FLAGS_1.SCP
FLAGS_0.nPG_B0
FLAGS_0.TEMP[1:0]
Yes
Yes
Yes
Yes
Yes
TEMP status change
On any temperature change
except for the case when
TEMP[1:0] = 0b11
Thermal warning
Thermal shutdown
OVP triggered
FLAGS_1.T_WARNING
FLAGS_1.THSD
Yes
Yes
Yes
Yes
Yes
No
FLAGS_1.OVP
Yes
Yes
Load current measurement
ready
FLAGS_1.I_LOAD_READY
UVLO triggered
FLAGS_1.UVLO
Yes
Yes
7.3.4.1 Warnings for Diagnosis (No Power Down)
7.3.4.1.1 Short-Circuit Protection (SCP)
A short-circuit protection feature allows the LP8754 to protect itself and external components during overload
conditions. The output short-circuit fault threshold is 400 mV (typ.) .
7.3.4.1.2 Power Good Monitoring
When the converter's feedback-pin voltage falls lower than 90% (typ.) of the set voltage, the FLAGS_0.nPG_B0
flag is set. To prevent a false alarm, the power good circuit is masked during converter start-up and voltage
transitions. The duration of the power good mask is set to 400 µs for converter start-up. For voltage ramps the
masking time is extended by an internal logic circuit up to 6.4 ms. (See Protection Features Characteristics.)
tMASK, START
tMASK, RAMP
V
OUT
Time
Masking time for start-up is constant 400 µs (typ.). Masking time for voltage transitions depends on the selected ramp
rates.
Figure 16. Power Good Masking Principle
7.3.4.1.3 Thermal Warnings
Prior to the thermal shutdown, thermal warnings are set. The first warning is set at 85°C (INT pin low), and the
second at 120°C (INT pin pulled low and FLAGS_1.T_WARNING flag set). If the chip temperature crosses any of
the thresholds of 85°C, 120°C, or 150°C (see FLAGS_0 register) the INT pin will be triggered. INT will be cleared
upon read of FLAGS_0.TEMP[1:0] bits except if FLAGS_0.TEMP [1:0] = 0b11, which is a thermal fault event.
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7.3.4.2 Faults (Fault State and Fast Power Down)
7.3.4.2.1 Undervoltage Lockout (UVLO)
When the input voltage falls below VUVLO (typ. 2.25 V) at the VDDA5V pin, the LP8754 indicates a fault by
activating the FLAGS_1.UVLO flag. The buck converter shut down without a power-down sequence(Fast Power-
Down). The flag will remain active until the input voltage is raised above the UVLO threshold. If the flag is
cleared while the fault persists, the flag is immediately re-asserted, and interrupt remains active.
7.3.4.2.2 Overvoltage Protection (OVP)
When an input voltage greater than VOVP (typ. 5.3 V) is detected at the VDDA5V pin, the LP8754 indicates a fault
by activating the FLAGS_1.OVP flag. The buck converter is shut down immediately (Fast Power-Down). The flag
will remain active until the input voltage is below the OVP threshold. If the flag is cleared while the fault persists,
the flag is immediately re-asserted and interrupt remains active.
7.3.4.2.3 Thermal Shutdown (THSD)
The LP8754 has a thermal overload protection function that operates to protect itself from short-term misuse and
overload conditions. When the junction temperature exceeds around 150°C, the device enters shutdown via fault-
state. INT will be cleared upon write of the FLAGS_1.THSD flag even when thermal shutdown is active. This
allows automatic recovery when temperature decreases below thermal shutdown level. See Figure 17 for
LP8754 thermal diagnosis and protection features.
24
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Clear THSD
E\ꢀZULWLQJꢀ¶0'
Read FLAGS_0
INT Released
THSD De-asserted
Yes
TEMP[1:0] = 0b11
Power Outputs Disabled
INT Requested
THSD Asserted
No
Tj < 125°C
Tj > 150°C
Clear T_WARNING
Read FLAGS_0
E\ꢀZULWLQJꢀ¶0'
No
INT by T_WARNING
released
INT by change in
TEMP released
Yes
INT Requested
If THSD low then enable
power outputs
TEMP[1:0] = 0b10
Yes
INT Requested
T_WARNING Asserted
No
Tj < 110°C
Tj > 120°C
Read FLAGS_0
No
INT Released
Yes
INT Requested
TEMP[1:0] = 0b01
Yes
INT Requested
No
Tj < 75°C
Tj > 85°C
Read FLAGS_0
No
Yes
INT Requested
INT Released
TEMP[1:0] = 0b00
Note that INT is asserted whenever any of the thermal thresholds is crossed, if unmasked. Note also the 10°C
Hysteresis on the TJ Thresholds.
Figure 17. Thermal Warnings and Thermal Shutdown Flow
7.4 Device Functional Modes
SHUTDOWN: All switch, reference, control and bias circuitry of the LP8754 are turned off. The main battery
supply voltage is high enough to start the buck power-up sequence but VVIOSYS and NRST are
LOW.
STANDBY: Setting VVIOSYS HIGH enables standby-operation. All registers can be read or written by the system
master via the system serial interface. Recovery from UVLO, TSD, or OVP event also leads to
standby.
ACTIVE:
Regulated DC-DC converters are on or can be enabled with full current capability. In this mode, all
features and control registers are available via the system serial bus and via DVS interface.
LOW-POWER: At light loads (less than approximately 30 mA), and when the load does not require highest level
of transient performance, the device enters automatically Low-Power mode. In this mode the part
operates at low IQ. Conditions entering and exiting Low-Power mode are shown in Figure 18.
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Device Functional Modes (continued)
V
FROM ANY
STATE
VIOSYS
LOW
SHUTDOWN
V
VIOSYS
HIGH
READ
OTP
REG
RESET ***
STANDBY
THERMAL
SHUTDOWN
or
UVLO/OVP
RELEASED
and
NRST LOW
or
2
I C RESET
NRST HIGH
2
I C RESET
FLAG(s) CLEARED
ACTIVE
FAULT CONDITION
DETECTED
**
*
FROM ANY STATE
EXCEPT SHUTDOWN
ACTIVE
LOW POWER
*) HIGH LOAD CURRENT OR ANY OF
THE FOLLOWING CONDITIONS:
**) LOW LOAD CURRENT AND ALL
THE FOLLOWING CONDITIONS
NSLP (pin)
HIGH
µ0¶
µ0¶
NSLP (pin)
LOW
LP_B0 (bit)
LP_EN (bit)
FPWM_B0 (bit)
LP_B0 (bit)
LP_EN (bit)
FPWM_B0 (bit)
µ1¶
µ1¶
µ0¶
µ1¶
***) 6((ꢀ´5(6(7ꢀ6&(1$5,26´ꢀ)25ꢀ
DETAILS
Figure 18. Device Operation Modes
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7.5 Programming
7.5.1 I2C-Compatible Interface
The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on
the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected
to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). Every device
on the bus is assigned a unique address and acts as either a Master or a Slave depending on whether it
generates or receives the serial clock SCL. The SCL and SDA lines should each have a pullup resistor placed
somewhere on the line and remain HIGH even when the bus is idle. Note: CLK pin is not used for serial bus data
transfer. There are two buses implemented: the System I2C bus and the DVS bus. In the following paragraphs,
SCL refers to both SCLSYS and SCLSR, and SDA refers to SDASYS and SDASR. The LP8754 supports
standard mode (100 kHz), fast mode (400 kHz) and high-speed mode (3.4 MHz).
7.5.1.1 Data Validity
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of
the data line can only be changed when clock signal is LOW.
SCL
SDA
data
change
allowed
data
change
allowed
data
valid
data
change
allowed
data
valid
Figure 19. Data Validity Diagram
7.5.1.2 Start and Stop Conditions
The LP8754 is controlled via an I2C-compatible interface. START and STOP conditions classify the beginning
and end of the I2C session. A START condition is defined as SDA transitions from HIGH to LOW while SCL is
HIGH. A STOP condition is defined as SDA transition from LOW to HIGH while SCL is HIGH. The I2C master
always generates the START and STOP conditions.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 20. Start and Stop Sequences
The I2C bus is considered busy after a START condition and free after a STOP condition. During data
transmission the I2C master can generate repeated START conditions. A START and a repeated START
condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock
signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 1 shows the SDA
and SCL signal timing for the I2C-Compatible Bus. See the I2C Serial Bus Timing Parameters for timing values.
7.5.1.3 Transferring Data
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP8754 pulls
down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP8754 generates an
acknowledge after each byte has been received.
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Programming (continued)
There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must
indicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clocked
out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the
master), but the SDA line is not pulled down.
After the START condition, the bus master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a “0” indicates a WRITE and a “1”
indicates a READ. The second byte selects the register to which the data will be written. The third byte contains
data to write to the selected register.
ack from slave
ack from slave
ack from slave
start
MSB Chip Addr LSB
w
ack MSB Register Addr LSB ack
MSB Data LSB ack stop
SCL
SDA
start
id = 60h
w
ack
addr = 40h
ack
address 40h data
ack stop
Figure 21. Write Cycle (w = write; SDA = '0'), id = device address = 60Hex for LP8754.
ack from slave
ack from slave repeated start
ack from slave data from slave nack from master
start
MSB Chip Addr LSB
w
MSB Register Addr LSB
rs
MSB Chip Address LSB
r
MSB Data LSB
stop
SCL
SDA
start
id =60h
w
ack
address = 3Fh
ack rs
id = 60h
r
ack
address 3Fh data
nack stop
When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.
Figure 22. Read Cycle ( r = read; SDA = '1'), id = device address = 60Hex for LP8754.
7.5.1.4 I2C-Compatible Chip Address
The device address for the LP8754 is 0x60 (ADDR pin tied to the GND). After the START condition, the I2C
master sends the 7-bit address followed by an eighth bit, read or write (R/W). R/W = 0 indicates a WRITE and
R/W = 1 indicates a READ. The second byte following the device address selects the register address to which
the data will be written. The third byte contains the data for the selected register.
MSB
LSB
1
Bit 7
1
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
R/W
Bit 0
2
I C Slave Address (chip address)
Here device address is 1100000Bin = 60 Hex.
Figure 23. Device Address
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Programming (continued)
7.5.1.5 Auto-Increment Feature
The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8-
bit word is sent to the LP8754, the internal address index counter will be incremented by one, and the next
register will be written. Table 4 shows writing sequence to two consecutive registers. Note: the auto-increment
feature does not work for read.
Table 4. Auto-Increment Example
Master
Action
Start
Device
Address
= 60H
Write
Register
Address
Data
Data
Stop
LP8754
Action
ACK
ACK
ACK
ACK
7.6 Register Maps
7.6.1 Register Descriptions
The LP8754 is controlled by a set of registers through the system serial interface port or through the Dynamic
Voltage Scaling interface. Table 5 lists device registers, their addresses and their abbreviations. A more detailed
description is given in the sections VSET_B0 to INT_MASK_2.
Many registers contain bits, that are reserved for future use. When writing to a register, any reserved bits should
not be changed.
Table 5. Register Descriptions
Read /
Write
Addr
Register
D7
D6
D5
D4
D3
D2
D1
D0
EN_DIS_B
0
0x00
VSET_B0
R/W
VSET_B0[6:0]
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
FPWM
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
RDIS_B0
FPWM_B0
BUCK0_CTRL
BUCK1_CTRL
BUCK2_CTRL
BUCK3_CTRL
BUCK4_CTRL
BUCK5_CTRL
FLAGS_0
OC_LEV_B0[1:0]
OC_LEV_B1[1:0]
OC_LEV_B2[1:0]
OC_LEV_B3[1:0]
OC_LEV_B4[1:0]
OC_LEV_B5[1:0]
LP_B0
Reserved
RAMP_B0[2:0]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
nPG_B0
THSD
TEMP[1:0]
I_LOAD_REA
DY
T_WARNIN
G
0x0E
0x0F
FLAGS_1
R/W
R/W
Reserved
Reserved
UVLO
OVP
SCP
MASK_nPG
_B0
INT_MASK_0
Reserved
EN_SS
MASK_OVP MASK_SCP
0x10
0x11
0x12
0x18
0x19
0x1F
0x21
0x22
GENERAL
RESET
R/W
R/W
R/W
R
Reserved DIS_DIF_B0
Reserved
Reserved
SLP_POL
LP_EN
SW_RESET
DELAY_BUCK0
CHIP_ID
DELAY_B0[7:0]
OTP_REV[4:0]
DEVICE
Reserved
Reserved
Reserved
DIE_REV[1:0]
PFM_LEV_B0
PHASE_LEV_B0
SEL_I_LOAD
LOAD_CURR
R/W
R/W
R/W
R
PFM_ENTRY_B0[2:0]
ADD_PH_B0[2:0]
Reserved
Reserved
Reserved
PFM_EXIT_B0[2:0]
SHED_PH_B0[2:0]
BUCK_LOAD_CURR[10:8]
LOAD_CURRENT_SOURCE[2:0]
BUCK_LOAD_CURR[7:0]
MASK_ILOA MASK_UVL MASK_TWA MASK_TEM
0x2E
INT_MASK_2
R/W
Reserved
D_READY RNING
O
P
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7.6.2 VSET_B0
Address: 0x00
D7
D6
D5
D4
D3
D2
D1
D0
EN_DIS_B0
VSET_B0[6:0]
Bits
Field
Type
Default
Description
7
EN_DIS_B0
R/W
1
DC-DC converter Buck0 Enable/Disable. The Enable of the master Buck0 controls the
operation of the slave bucks.
0 = Converter disabled
1 = Converter enabled
Note: When a disable request is received the converter is disabled immediately.
6:0
VSET_B0[6:0]
R/W
011 1100 Sets the output voltage.
Defined by:
VOUT = 0.5 V + 10 mV * VSET_B0
VOUT range = 0.6 V to 1.67 V
NOTE: Do not use VSET_B0 values < 0001010 (10 dec) = 0.6 V.
NOTE: Register settings starting from 1110110 up to 1111111 are clamped to 1.67 V.
7.6.3 FPWM
Address: 0x06
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
FPWM_B0
Bits
7:1
0
Field
Type
R/W
R/W
Default
001 1111
1
Description
Reserved
FPWM_B0
Forced PWM mode of operation, Buck regulator 0 (Master). The setting of the master
controls the operation of the slave bucks.
0 = PWM, PFM or Low-Power PFM operation mode.
1 = This will force the master converter and the slaves to operate always in the PWM
mode.
7.6.4 BUCK0_CTRL
Address: 0x07
D7
D6
D5
D4
D3
D2
D1
D0
OC_LEV_B0[1:0]
LP_B0
RDIS_B0
Reserved
RAMP_B0[2:0]
Bits
Field
Type
Default
Description
7:6
OC_LEV_B0[1:0]
R/W
10
Inductor positive current limit on Buck 0. Note that OC_LEV_B0...B5 should have the
same value.
00 = 1.5 A
01 = 2.0 A
10 = 2.5 A
11 = 3.0 A
5
4
3
LP_B0
R/W
R/W
R/W
0
1
0
Allows converter to enter into Low-Power PFM mode.
1 = Entering to Low-Power PFM mode is allowed.
0 = Entering to Low-Power PFM more is not allowed.
RDIS_B0
Reserved
Enables the output discharge resistors when the VOUT supply has been disabled.
1 = Enable pull-down
0 = Disable pull-down
30
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Bits
ZHCSDB8A –FEBRUARY 2014–REVISED AUGUST 2014
Field
Type
Default
Description
2:0
RAMP_B0[2:0]
R/W
001
This set the output voltage change ramp as follows:
000 = 30 mV/µs
001 = 15 mV/µs
010 = 7.5 mV/µs
011 = 3.8 mV/µs
100 = 1.9 mV/µs
101 = 0.94 mV/µs
110 = 0.47 mV/µs
111 = 0.23 mV/µs
7.6.5 BUCK1_CTRL
Address: 0x08
D7
D6
D5
D4
D3
D2
D1
D0
OC_LEV_B1[1:0]
Reserved
Bits
Field
Type
Default
Description
7:6
OC_LEV_B1[1:0]
R/W
10
Inductor positive current limit on Buck 1. Note that OC_LEV_B0...B5 should have the
same value.
00 = 1.5 A
01 = 2.0 A
10 = 2.5 A
11 = 3.0 A
5:0
Reserved
R/W
01 0001
7.6.6 BUCK2_CTRL
Address: 0x09
D7
D6
D5
D4
D3
D2
D1
D0
OC_LEV_B2[1:0]
Reserved
Bits
Field
Type
Default
Description
7:6
OC_LEV_B2[1:0]
R/W
10
Inductor positive current limit on Buck 2. Note that OC_LEV_B0...B5 should have the
same value.
00 = 1.5 A
01 = 2.0 A
10 = 2.5 A
11 = 3.0 A
5:0
Reserved
R/W
01 0001
7.6.7 BUCK3_CTRL
Address: 0x0A
D7
D6
D5
D4
D3
D2
D1
D0
OC_LEV_B3[1:0]
Reserved
Bits
Field
Type
Default
Description
7:6
OC_LEV_B3[1:0]
R/W
10
Inductor positive current limit on Buck 3. Note that OC_LEV_B0...B5 should have the
same value.
00 = 1.5 A
01 = 2.0 A
10 = 2.5 A
11 = 3.0 A
5:0
Reserved
R/W
01 0001
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7.6.8 BUCK4_CTRL
Address: 0x0B
D7
D6
D5
D4
D3
D2
D1
D0
OC_LEV_B4[1:0]
Reserved
Bits
Field
Type
Default
Description
7:6
OC_LEV_B4[1:0]
R/W
10
Inductor positive current limit on Buck 4. Note that OC_LEV_B0...B5 should have the
same value.
00 = 1.5 A
01 = 2.0 A
10 = 2.5 A
11 = 3.0 A
5:0
Reserved
R/W
01 0001
7.6.9 BUCK5_CTRL
Address: 0x0C
D7
D6
D5
D4
D3
D2
D1
D0
OC_LEV_B5[1:0]
Reserved
Bits
Field
Type
Default
Description
7:6
OC_LEV_B5[1:0]
R/W
10
Inductor positive current limit on Buck 5. Note that OC_LEV_B0...B5 should have the
same value.
00 = 1.5 A
01 = 2.0 A
10 = 2.5 A
11 = 3.0 A
5:0
Reserved
R/W
01 0001
7.6.10 FLAGS_0
Address: 0x0D
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
nPG_B0
TEMP[1:0]
Bits
7:3
2
Field
Type
R/W
R/W
Default
X XXXX
0
Description
Reserved
nPG_B0
(1)
Flag Bit
Power good fault flag for VOUT rail
1 = Power fault detected
0 = Power good
1:0
TEMP[1:0]
R
00
indicates the die temperature as follows:
00: die temperature lower than 85ºC
01: 85ºC ≤ die temperature < 120ºC
10: 120ºC ≤ die temperature < 150ºC
11: die temperature 150ºC or higher
(1) The flag bit can be cleared only by writing a zero to the associated register bit or power cycling the device (VVIOSYS to LOW). Reading or
RESET does not clear the flag bits. After clearing, the nPG_B0 fault flag will be raised again '1' if the fault condition persists. Any
unmasked flag bit High will cause the interrupt to be asserted on the INT pin. The INT pin will be pulled Low until all the unmasked flags
are clear again.
7.6.11 FLAGS_1
Address: 0x0E
32
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D7
D6
D5
D4
D3
D2
D1
D0
Reserved
I_LOAD_READ
Y
UVLO
T_WARNING
THSD
OVP
SCP
Bits
7:6
5
Field
Type
Default
Description
Reserved
R/W
R/W
00
0
I_LOAD_READY
Flag Bit(1)
1 = Buck load current measurement data ready
0 = Buck load current measurement data not ready
(1)
4
3
UVLO
R/W
R/W
0
0
Flag Bit
1= Input undervoltage lockout (UVLO): Input voltage sagged below UVLO threshold.
0 = No UVLO
(1)
T_WARNING
Flag Bit
1= Thermal warning: The IC temperature exceeds 120°C, in advance of the thermal
shutdown protection.
0 = No thermal warning
(1)
2
1
0
THSD
OVP
SCP
R/W
R/W
R/W
0
0
0
Flag Bit
1 = Thermal shutdown event detected
0 = No thermal shutdown
(1)
Flag Bit
1= Indicates overvoltage protection (OVP) circuit activation.
0 = No OVP event. The OVP circuitry monitors VDDA5V power input.
(1)
Flag Bit
1= Indicates short-circuit protection (SCP) circuit activation. The bit is activated when a
short-circuit condition is detectedon output rail.
0 = No SCP event
(1) The flag bit(s) can be cleared only by writing a zero to the associated register bit(s) or power cycling the device (VVIOSYS to LOW).
Reading or RESET does not clear the flag bits. After clearing, the OVP, SCP fault flag(s) will be raised again '1' if the fault condition
persists. The THSD flag will remain '0' after clear, even though the fault condition persists. Any unmasked flag bit High will cause the
interrupt to be asserted on the INT pin. The INT pin will be pulled Low until all the unmasked flags are clear again.
7.6.12 INT_MASK_0
Address: 0x0F
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
MASK_nPG_B
0
MASK_OVP
MASK_SCP
Bits
7:3
2
Field
Type
R/W
R/W
Default
1 1111
0
Description
Reserved
MASK_nPG_B0
MASK_OVP
MASK_SCP
Interrupt mask for power good fault flag
1 = nPG_B0 does not set interrupt.
0 = nPG_B0 sets interrupt, when triggered.
1
0
R/W
R/W
0
0
Interrupt mask for Overvoltage Protection (OVP) fault flag
1 = OVP does not set interrupt.
0 = OVP sets interrupt, when triggered.
Interrupt mask for short-circuit protection SCP fault flag
1 = SCP does not set interrupt.
0 = SCP sets interrupt, when triggered.
7.6.13 GENERAL
Address: 0x10
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
EN_SS
Reserved
DIS_DIF_B0
Reserved
SLP_POL
LP_EN
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Bits
7:6
5
Field
Reserved
EN_SS
Type
R/W
R/W
Default
Description
00
0
Spread Spectrum
1 = Spread Spectrum enabled
0 = Spread Spectrum disabled
4
3
Reserved
R/W
R/W
0
0
DIS_DIF_B0
Disable Differential-to-single-ended amplifier
1 = Differential amplifier disabled
0 = Differential amplifier enabled
2
1
Reserved
SLP_POL
R/W
R/W
0
0
Sets the polarity of the NSLP pin
1 = NSLP is active high
0 = NSLP is active low
0
LP_EN
R/W
1
1 = allows Low-Power PFM mode. In order to reduce power consumption under low
load conditions, the unit will automatically switch off unused internal blocks.
0 = Low-Power mode not allowed
7.6.14 RESET
Address: 0x11
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
SW_RESET
Bits
7:1
0
Field
Type
R/W
R/W
Default
000 0000
0
Description
Reserved
SW_RESET
Writing this bit with '1' and '0', in this order, will reset the registers to the default values.
If NRST is still kept HIGH, the converter output(s) will be regulated to the programmed
register values. If a full POR reset is required VVIOSYS must be pulled low. The fault
flags are persistent over SW-reset.
7.6.15 DELAY_BUCK0
Address: 0x12
D7
D6
D5
D4
D3
D2
D1
D0
DELAY_B0
Bits
Field
Type
Default
Description
7:0
DELAY_B0
R/W
0000 0000 Master delay
Sets the delay time from when NRST is asserted to when the VOUT rail is enabled.
Sets the delay time from when NRST is de-asserted to when the VOUT rail is disabled.
DELAY = DELAY_B0 * 100 µs
(1)
If DELAY_B0 = FFh, supply is never enabled.
(1) If this register is set to FFh when the converter is already started, it will cause an immediate power down of the converter.
7.6.16 CHIP_ID
Address: 0x18
D7
D6
D5
D4
D3
D2
D1
D0
DEVICE
OTP_REV
DIE_REV
Bits
Field
Type
Default
Description
7
DEVICE
R
1
DEVICE
Contains Device ID
6:2
OTP_REV
R
0 0001
OTP_REV
Contains OTP Version ID
34
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Bits
ZHCSDB8A –FEBRUARY 2014–REVISED AUGUST 2014
Field
DIE_REV
Type
Default
Description
1:0
R
00
DIE_REV
Contains Revision ID
7.6.17 PFM_LEV_B0
Address: 0x19
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
PFM_ENTRY_B0[2:0]
Reserved
PFM_EXIT_B0[2:0]
Bits
Field
Type
Default
0
Description
7
Reserved
R/W
R/W
(1)
6:4
PFM_ENTRY_B0
011
PFM_ENTRY_B0
Sets the target PFM entry level for Buck 0. The final PWM-to-PFM switchover current
varies slightly and is dependant on the output voltage, input voltage and the inductor
current level.
000 = 100 mA
001 = 125 mA
010 = 150 mA
011 = 175 mA
100 = 225 mA
101 = Reserved
110 = Reserved
111 = Reserved
3
Reserved
R/W
R/W
0
(1)
2:0
PFM_EXIT_B0
110
PFM_EXIT_B0
Sets the target PFM exit level for Buck 0. The final PFM-to-PWM switchover current
varies slightly and is dependant on the output voltage, input voltage and the inductor
current level.
000 = Reserved
001 = Reserved
010 = Reserved
011 = 175 mA
100 = 225 mA
101 = 275 mA
110 = 325 mA
111 = 375 mA
(1) For proper operation, the PFM exit current level should be at least 150 mA higher than the PFM entry current level.
7.6.18 PHASE_LEV_B0
Address: 0x1F
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
ADD_PH_B0[2:0]
Reserved
SHED_PH_B0[2:0]
Bits
Field
Type
Default
0
Description
7
Reserved
R/W
R/W
6:4
ADD_PH_B0
100
ADD_PH_B0(1)
Sets the level on which a phase is added.
000 = Reserved
001 = Reserved
010 = 0.5 A * No. of Active Phases
011 = 0.6 A * No. of Active Phases
100 = 0.7 A * No. of Active Phases
101 = 0.8 A * No. of Active Phases
110 = 0.9 A * No. of Active Phases
111 = 1.0 A * No. of Active Phases
3
Reserved
R/W
0
(1) ADD_PH_B0 and SHED_PH_B0 values must be chosen so that the resulting hysteresis is a minimum of 100 mA and ADD_PH_B0 >
SHED_PH_B0.
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Bits
Field
Type
Default
Description
2:0
SHED_PH_B0
R/W
010
SHED_PH_B0(1)
Sets the level of phase shedding.
000 = 0.3 A * No. of Active Phases
001 = 0.4 A * No. of Active Phases
010 = 0.5 A * No. of Active Phases
011 = 0.6 A * No. of Active Phases
100 = 0.7 A * No. of Active Phases
101 = 0.8 A * No. of Active Phases
110 = Reserved
111 = Reserved
7.6.19 SEL_I_LOAD
Address: 0x21
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK_LOAD_CURR[10:8]
Reserved
LOAD_CURRENT_SOURCE[2:0]
Bits
Field
Type
R/W
R
Default
0
Description
7
Reserved
6:4
BUCK_LOAD_
CURR[10:8]
000
BUCK_LOAD_CURR
This register reports 3 MSB bits of the magnitude of the average load current of the
selected Buck Converter. See LOAD_CURR register.
3
Reserved
R/W
R/W
0
2:0 LOAD_CURRENT_
SOURCE[2:0]
000
LOAD_CURRENT_SOURCE
These bits are used for choosing the Buck Converter whose load current will be
measured.
000 = Converter 0 load current will be measured.
001 = Converter 1 load current will be measured.
010 = Converter 2 load current will be measured.
011 = Converter 3 load current will be measured.
100 = Converter 4 load current will be measured.
101 = Converter 5 load current will be measured.
110 = Master total load current will be measured.
111 = Reserved
7.6.20 LOAD_CURR
Address: 0x22
D7
D6
D5
D4
D3
D2
D1
D0
BUCK_LOAD_CURR[7:0]
Bits
Field
Type
Default
Description
7:0
BUCK_LOAD_
CURR[7:0]
R
0000 0000 BUCK_LOAD_CURR
This register reports 8 LSB bits of the magnitude of the average load current of the
selected Buck Converter. The value is reported with a resolution of 10 mA per LSB
and 20A max current. Three MSB bits are reported by
SEL_I_LOAD.BUCK_LOAD_CURR[10:8] bits, see SEL_I_LOAD.
The current reported is an average over the last 5 milliseconds. The host system has
read-only access to this register. This register is cleared to 0 on all resets.
000 0000 0000 Load current lower than 10 mA
000 0000 0001 10 mA ≤ Load current < 20 mA
...
111 1111 1110 20460 mA ≤ Load current < 20470 mA
111 1111 1111 Load current 20470 mA or higher.
Note: Not production tested. Typical values for reference only.
7.6.21 INT_MASK_2
Address: 0x2E
36
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ZHCSDB8A –FEBRUARY 2014–REVISED AUGUST 2014
D7
D6
D5
D4
D3
MASK_ILOAD_ MASK_UVLO MASK_TWARN MASK_TEMP
READY ING
D2
D1
D0
Reserved
Bits
Field
Reserved
Type
R/W
R/W
Default
0000
1
Description
7:4
3
MASK_ILOAD_
READY
Interrupt mask for load current measurement flag
1 = FLAGS_1.I_LOAD_READY does not set interrupt.
0 = FLAGS_1.I_LOAD_READY sets interrupt.
2
1
0
MASK_UVLO
R/W
R/W
R/W
0
1
1
Interrupt mask for undervoltage lock-out flag
1 = FLAGS_1.UVLO does not set interrupt.
0 = FLAGS_1.UVLO sets interrupt, when triggered.
MASK_
TWARNING
Interrupt mask for thermal warning flag
1 = FLAGS_1.T_WARNING does not set interrupt.
0 = FLAGS_1.T_WARNING sets interrupt, when triggered.
MASK_TEMP
Interrupt mask for die temperature flag bits
1 = FLAGS_0.TEMP[1:0] value change does not set interrupt.
0 = FLAGS_0.TEMP[1:0] value change sets interrupt.
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LP8754
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LP8754 is a multi-phase step-down converter with 6 switcher cores bundled together.
8.2 Typical Application
SYSTEM VOLTAGE
2.5 V - 5.0 V
LP8754: 6-PHASE
CONFIGURATION
OUTPUT
VOLTAGE
L0 0.47 PH
L1 0.47 PH
L2 0.47 PH
SWB0
VINB0/B1
CIN0
10 PF
APPLICATIONS
PROCESSOR
VINB2
SWB1
SWB2
CIN1
10 PF
COUT6PH
VINB3/B4
VINB5
CPU
LOAD
10A
4 x 22 PF
CIN2
10 PF
0.47 PH
L3
MAX
SWB3
CIN3
10 PF
L4 0.47 PH
L5 0.47 PH
SWB4
SWB5
VDDA5V
VIOSYS
CVDD
VIO1V8
1 PF
CVIOSYS
1 PF
SDASR
SCLSR
FBB0+/B0
FBB0-/B1
NSLP
OPTIONAL
VLDO
FBB2
CLDO
VIO1V8
1 PF
RP1
SDASYS
SCLSYS
FBB3+/B3
RP2
FBB3-/B4
FBB5
RP3
INT
CPU POWER REQUEST
NRST
Figure 24. 6-Phase Configuration Schematic
38
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ZHCSDB8A –FEBRUARY 2014–REVISED AUGUST 2014
Typical Application (continued)
8.2.1 Design Requirements
Table 6 shows requirements for 6-phase configuration.
Table 6. Design Parameters
DESIGN PARAMETER
Input voltage range
EXAMPLE VALUE
2.5 V to 5 V
1.1 V
Output voltage
Converter operation mode
Maximum load current
Inductor current limit
Forced PWM
10 A
2.5 A
8.2.2 Detailed Design Procedure
The performance of the LP8754 device depends greatly on the care taken in designing the Printed Circuit Board
(PCB). The use of low inductance and low serial resistance ceramic capacitors is strongly recommended, while
proper grounding is crucial. Attention should be given to decoupling the power supplies. Decoupling capacitors
must be connected close to the IC and between the power and ground pins to support high peak currents being
drawn from System Power Rail during turn-on of the switching MOSFETs. Keep input and output traces as short
as possible, because trace inductance, resistance and capacitance can easily become the performance limiting
items. The separate power pins VINBXX are not connected together internally. The VINBXX power connections
shall be connected together outside the package using power plane construction.
8.2.2.1 Inductor Selection
The DC bias current characteristics of inductors must be considered. Different manufacturers follow different
saturation current rating specifications, so attention must be given to details. (Please request DC bias curves
from the manufacturer as part of the inductor selection process.) Minimum effective value of inductance to
ensure good performance is 0.25 µH at 2.5 A (Default ILIMITP typical) bias current over the inductor's operating
temperature range. The inductor’s DC resistance should be less than 0.05 Ω for good efficiency at high-current
condition. The inductor AC loss (resistance) also affects conversion efficiency. Higher Q factor at switching
frequency usually gives better efficiency at light load to middle load. Table 7 lists suggested inductors and
suppliers. Shielded inductors radiate less noise and are preferable.
Table 7. Suggested Inductors
ITEM
MODEL
VENDOR
DIMENSIONS LxWxH (mm)
D.C.R (mΩ) MAX
L0 to L5; Step-down
converter inductor 0.47 µH
LQM21PNR47MGH
DFE252012 R47
DFE201612C R47N
Murata
TOKO
TOKO
2.0 x 1.2 x 1.0
2.5 x 2 x 1.2
2.0 x 1.6 x 1.2
40 (typ)
39
50
8.2.2.2 Input Capacitor Selection
A ceramic input capacitor of 10 µF, 10 V is sufficient for most applications. Place the input capacitor as close as
possible to the VINBXX pin and GND pin of the device. A larger value or higher voltage rating may be used to
improve input voltage filtering. Use X7R or X5R types, do not use Y5V. DC bias characteristics of ceramic
capacitors must be considered when selecting case sizes like 0402. Minimum effective input capacitance to
ensure good performance is 2.5 µF at maximum input voltage DC bias including tolerances and over ambient
temp range, assuming that there is at least 22 µF of additional capacitance common for all the power input pins
on the system power rail.
The input filter capacitor supplies current to the PFET (high-side) switch in the first half of each cycle and
reduces voltage ripple imposed on the input power source. A ceramic capacitor's low equivalent series resistance
(ESR) provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select an
input filter capacitor with sufficient ripple current rating.
For additional noise immunity, adding a high-frequency decoupling capacitor of 100 nF to 1 µF between VDDA5V
pin and GND is recommended.
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Table 8. Suggested Input Capacitors (X5R Dielectric)
MANUFACTURER
Murata
PART NUMBER
GRM188R60J106ME84
C1608X5R1A106KT
LMK107BJ106MALTD
CL10A226MP8NUNE
VALUE
CASE SIZE
0603
VOLTAGE RATING
10 µF (20%)
10 µF (10%)
10 µF (20%)
22 µF (20%)
6.3 V
10 V
10 V
10 V
TDK
0603
Taiyo Yuden
Samsung
0603
0603
8.2.2.3 Output Capacitor Selection
Use ceramic capacitor, X7R or X5R types; do not use Y5V. DC bias voltage characteristics of ceramic capacitors
must be considered. DC bias characteristics vary from manufacturer to manufacturer, and DC bias curves should
be requested from them as part of the capacitor selection process. The output filter capacitor smooths out current
flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and
reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low
ESR to perform these functions. Minimum effective output capacitance to ensure good performance in 6-phase
configuration is 30 µF at the output voltage DC bias including tolerances and over ambient temp range.
The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its
RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for
selection process is at the switching frequency of the part.
A higher output capacitance improves the load step behavior and reduces the output voltage ripple as well as
decreasing the PFM switching frequency. For most 6-phase applications 4 x 22-µF 0603 capacitors for COUT is
suitable. Although the converter's loop compensation can be programmed to adapt to virtually several hundreds
of microfarads COUT, an effective COUT less than 120 µF is preferred -- there is not necessarily any benefit to
having a COUT higher than 120 µF. Note that the output capacitor may be the limiting factor in the output voltage
ramp, especially for very large (> 100 µF) output capacitors. For large output capacitors, the output voltage might
be slower than the programmed ramp rate at voltage transitions, because of the higher energy stored on the
output capacitance. Also at start-up, the time required to charge the output capacitor to target value might be
longer. At shutdown, if the output capacitor is discharged by the internal discharge resistor, more time is required
to settle VOUT down as a consequence of the increased time constant.
Table 9. Suggested Output Capacitor
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
VOLTAGE RATING
Samsung
CL10A226MP8NUNE
22 µF (20%)
0603
10 V
8.2.2.4 LDO Capacitor Selection
A ceramic low ESR 1-μF capacitor should be connected between the VLDO and GNDA pins.
Table 10. Suggested LDO Capacitor
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
VOLTAGE RATING
Samsung
CL03A105MQ3CSNH
1 µF (20%)
0201
6.3 V
8.2.2.5 VIOSYS Capacitor Selection
Adding a ceramic low ESR 1-μF capacitor between the VIOSYS pin and GND is recommended. If VVIOSYS signal
is low noisy the capacitor is not required.
40
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ZHCSDB8A –FEBRUARY 2014–REVISED AUGUST 2014
8.2.3 Application Curves
Unless otherwise specified: VVDDA5V = VVINBXX = 3.7 V, VOUT = 1.1 V, TA = 25°C
100
90
80
70
60
50
100
90
80
70
60
50
1500 mV
1300 mV
1100 mV
900 mV
700 mV
1500 mV
1300 mV
1100 mV
900 mV
700 mV
0
2000
4000
6000
8000
10000
0
2000
4000
6000
8000
10000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
C028
C029
VIN = 3.7 V
Inductor: Murata LQM21PNR47MGH
VIN = 2.7 V
Inductor: Murata LQM21PNR47MGH
Figure 25. Efficiency vs Load Current in Forced PWM
Mode
Figure 26. Efficiency vs Load Current in Forced PWM
Mode
100
100
1500 mV
1300 mV
1100 mV
900 mV
90
80
70
60
50
40
30
700 mV
90
80
70
1300 mV LP PFM
1100 mV LP PFM
900 mV LP PFM
1300 mV PFM
1100 mV PFM
900 mV PFM
1300 mV PWM
1100 mV PWM
900 mV PWM
1
10
100
1000
10000
2500
3000
3500
4000
4500
5000
OUTPUT CURRENT (mA)
INPUT VOLTAGE (mV)
C033
C030
VOUTSET = 900, 1100 and 1300 mV
Inductor: Murata LQM21PNR47MGH
IOUT = 1 A
Inductor: Murata LQM21PNR47MGH
Figure 27. Efficiency vs Load Current in Low-Power PFM
Mode, PFM Mode, and Forced PWM Mode
Figure 28. Efficiency vs Input Voltage in PWM Mode
100
100
1500 mV
1300 mV
1100 mV
900 mV
700 mV
1500 mV
1300 mV
1100 mV
900 mV
700 mV
95
90
85
80
75
70
95
90
85
80
75
70
2500
3000
3500
4000
4500
5000
2500
3000
3500
4000
4500
5000
INPUT VOLTAGE (mV)
INPUT VOLTAGE (mV)
C031
C032
IOUT = 3 A
Inductor: Murata LQM21PNR47MGH
IOUT = 6 A
Inductor: Murata LQM21PNR47MGH
Figure 29. Efficiency vs Input Voltage in PWM Mode
Figure 30. Efficiency vs Input Voltage in PWM Mode
Copyright © 2014, Texas Instruments Incorporated
41
LP8754
ZHCSDB8A –FEBRUARY 2014–REVISED AUGUST 2014
www.ti.com.cn
1105
1104
1103
1102
1101
1100
1099
1098
1097
1096
1095
1110
1108
1106
1104
1102
1100
1098
1096
1094
1092
1090
VIN = 2.5 V
VIN = 3.7 V
VIN = 5 V
VIN = 2.5 V
VIN = 3.7 V
VIN = 5 V
0
1
2
3
4
5
6
7
8
9
10
0
100
200
300
400
500
LOAD CURRENT (A)
LOAD CURRENT (mA)
C019
C026
VOUTSET = 1.1 V
VOUTSET = 1.1 V
Figure 31. Output Voltage vs Load Current in Forced PWM
Mode
Figure 32. Output Voltage vs Load Current in PFM/PWM
Mode
1100.0
1110
1108
1106
1104
1102
1100
1098
1096
1099.5
1099.0
1098.5
1098.0
1094
PWM, ILOAD = 3 A
1092
PFM, ILOAD = 100 mA
1090
0
20
40
60
80
100
120
2500
3000
3500
4000
4500
5000
±40
±20
TEMPERATURE (C)
INPUT VOLTAGE (mV)
C042
C037
VOUTSET = 1.1 V
ILOAD = 1.0 A
VOUTSET = 1.1 V
Figure 33. Output Voltage vs Temperature
Figure 34. Line Regulation
2000
1800
1600
1400
1200
1000
800
10.0
2000
1800
1600
1400
1200
1000
800
10.0
Buck 0 Iout (mA)
Buck 1 Iout (mA)
Buck 2 Iout (mA)
Buck 3 Iout (mA)
Buck 4 Iout (mA)
Buck 5 Iout (mA)
Accuracy
Buck 0 Iout (mA)
Buck 1 Iout (mA)
Buck 2 Iout (mA)
Accuracy
8.0
6.0
4.0
2.0
0.0
8.0
6.0
4.0
2.0
0.0
600
600
400
400
200
200
0
0
0
2000
4000
6000
8000
10000
0
1000
2000
3000
4000
5000
TOTAL IOUT (mA)
TOTAL IOUT (mA)
C038
C040
Figure 35. Phase Currents and Current Balancing
Accuracy, 6 Phases Active (Currents measured by
LP8754)
Figure 36. Phase Currents and Current Balancing
Accuracy, 3 Phases Active (Currents measured by
LP8754)
42
Copyright © 2014, Texas Instruments Incorporated
LP8754
www.ti.com.cn
ZHCSDB8A –FEBRUARY 2014–REVISED AUGUST 2014
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
20.0
18.0
16.0
14.0
12.0
10.0
8.0
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
20.0
IOUT
IOUT
18.0
Accuracy
Accuracy
16.0
14.0
12.0
10.0
8.0
6.0
6.0
4.0
4.0
2.0
2.0
0
0
0.0
10000
0
0.0
5000
2000
4000
6000
8000
0
1000
2000
3000
4000
REAL IOUT (mA)
REAL IOUT (mA)
C039
C041
Figure 37. Load Current Measured by LP8754 vs Real Load
Current, 6 Phases Active
Figure 38. Load Current Measured by LP8754 vs Real Load
Current, 3 Phases Active
VOUT AC COUPLED
20 mV/DIV
VOUT AC COUPLED
20 mV/DIV
ILOAD 4 A/DIV
ILOAD 1 A/DIV
TIME 20 Ps/DIV
TIME 20 Ps/DIV
IOUT 1 A → 8 A → 1 A
tr = tf = 400 ns
IOUT 0.6 A → 2 A → 0.6 A
tr = tf = 400 ns
Figure 39. Transient Load Step Response, PWM Mode
Figure 40. Transient Load Step Response, PWM Mode
VIN 500 mV/DIV
VOUT AC COUPLED
20 mV/DIV
VOUT AC COUPLED
10 mV/DIV
ILOAD 200 mA/DIV
TIME 40 Ps/DIV
VIN 3.3 V → 3.8 V → 3.3 V
TIME 20 Ps/DIV
IOUT 0.5 mA → 0.5 A → 0.5 mA
tr = tf = 100 ns
tr = tf = 10 µs
IOUT = 2000 mA DC
Figure 42. Transient Line Response
Figure 41. Transient Load Step Response, AUTO Mode
Copyright © 2014, Texas Instruments Incorporated
43
LP8754
ZHCSDB8A –FEBRUARY 2014–REVISED AUGUST 2014
www.ti.com.cn
VOUT AC COUPLED 10 mV/DIV
VOUT AC COUPLED
10 mV/DIV
SW 1 V/DIV
SW 1 V/DIV
TIME 400 µs/DIV
TIME 200 ns/DIV
IOUT = 100 µA
IOUT = 200 mA
Figure 43. Output Voltage Ripple, PFM Mode
NRST 2 V/DIV
Figure 44. Output Voltage Ripple, PWM Mode, One Phase
Active
NRST 2 V/DIV
VOUT 200 mV/DIV
VOUT 200 mV/DIV
LOAD 1 A/DIV
SW 5 V/DIV
SW 5 V/DIV
TIME 20 Ps/DIV
TIME 20 Ps/DIV
No Load
3-A Load
Figure 45. Start-up with NRST, Forced PWM
Figure 46. Start-up with NRST, Forced PWM
NRST 2 V/DIV
VOUT 200 mV/DIV
TIME 400 µs/DIV
VOUT 200 mV/DIV
SW 5 V/DIV
TIME 10 ms/DIV
No Load
Figure 47. Shutdown with NRST, Forced PWM
Figure 48. VOUT Transition from 0.6 V to 1.4 V with
Different Ramp Settings
44
Copyright © 2014, Texas Instruments Incorporated
LP8754
www.ti.com.cn
ZHCSDB8A –FEBRUARY 2014–REVISED AUGUST 2014
VOUT AC COUPLED 10 mV/DIV
VOUT AC COUPLED 10 mV/DIV
IL_B0 200 mV/DIV
LOAD 1 A/DIV
TIME 100 ms/DIV
VSW 2 V/DIV
TIME 2 µs/DIV
IOUT 0 A → 5 A → 0 A
Figure 49. Load Ramp
Figure 50. Transient from PFM to PWM Mode
INT 500 mV/DIV
VOUT AC COUPLED 10 mV/DIV
VOUT 200 mV/DIV
LOAD 5 A/DIV
VSW 2 V/DIV
TIME 2 µs/DIV
TIME 400 Ps/DIV
Figure 52. Interrupt Line Going Low with Not Power Good
Activation
Figure 51. Transient from PWM to PFM Mode
SW 2 V/DIV
VOUT 200 mV/DIV
INT 500 mV/DIV
TIME 10 Ps/DIV
Figure 53. Metallic Short Applied at VOUT
Copyright © 2014, Texas Instruments Incorporated
45
LP8754
ZHCSDB8A –FEBRUARY 2014–REVISED AUGUST 2014
www.ti.com.cn
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.5 V and 5 V. This input supply
should be well regulated and able to withstand maximum input current and maintain stable voltage without
voltage drop even at load transition condition. The resistance of the input supply rail should be low enough that
the input current transient does not cause too high drop in the LP8754 supply voltage that can cause false UVLO
fault triggering. If the input supply is located more than a few inches from the LP8754 additional bulk capacitance
may be required in addition to the ceramic bypass capacitors.
10 Layout
10.1 Layout Guidelines
The high frequency and large switching currents of the LP8754 make the choice of layout important. Good power
supply results will only occur when care is given to proper design and layout. Bad layout will affect noise pickup
and generation and can cause a good design to perform with less-than-expected results. With a range of output
currents from milliamps to 10 A, good power-supply layout is more challenging than for most general PCB
design. The following steps should be used as a reference to ensure the device is stable and maintains proper
voltage and current regulation across its intended operating voltage and current range:
1. Place CIN as close as possible to the VINBXX pin and the GND pin. Route the VIN trace wide and thick to
avoid IR drops. The trace between the input capacitor's positive node and LP8754’s VINBXX pin(s) as well
as the trace between the input capacitor's negative node and power GND pin(s) must be kept as short as
possible. The input capacitance provides a low-impedance voltage source for the switching converter. The
parasitic inductance on these traces must be kept as tiny as possible for proper device operation.
2. The output filter for each buck, consisting of COUT and L, converts the switching signal at SW to the noiseless
output voltage. For optimal EMI behavior, it should be placed as close as possible to the device, keeping the
switch node small. Route the traces between the LP8754's output capacitors and the load's input capacitors
direct and wide to avoid losses due to the IR drop.
3. Input for analog blocks (VDDA5V and GNDA) should be isolated from noisy signals. Connect VDDA5V
directly to a quiet system voltage node and GNDA to a quiet ground point where no IR drop occurs. For
additional noise immunity, adding a high-frequency decoupling capacitor of 100 nF to 1 µF is recommended.
Place the decoupling capacitor as close to the VDDA5V pin as possible. VDDA5V trace is low current, so the
trace width does not need to be optimized.
4. If the processor load supports voltage remote sensing, connect the LP8754 feedback pins FBBXX to the
respective sense pins on the processor. The sense lines are susceptible to noise. They must be kept away
from noisy signals such as GNDBXX, VIN, and SW, as well as high bandwidth signals such as the I2C. Avoid
both capacitive as well as inductive coupling by keeping the sense lines short, direct, and close to each
other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible.
Running the signal as a differential pair is recommended.
5. GNDBXX, VIN, and SW should be routed on thick layers. They must not surround inner signal layers which
are not able to withstand interference from noisy GNDBXX, VIN, and SW. This can create noise coupling to
inner signal layers.
Due to the small package of this converter and the overall small solution size, the thermal performance of the
PCB layout is important. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and
convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of
a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures.
Wide power traces come with the ability to sink dissipated heat. This can be improved further on multi-layer PCB
designs with vias to different planes. This results in reduced junction-to-ambient (RθJA) and junction-to-board
(RθJB) thermal resistances, thereby reducing the device junction temperature, TJ. It's strongly recommended to
perform a careful system-level 2D or full 3D dynamic thermal analysis at the beginning of the product design
process, using a thermal modeling analysis software.
46
Copyright © 2014, Texas Instruments Incorporated
LP8754
www.ti.com.cn
ZHCSDB8A –FEBRUARY 2014–REVISED AUGUST 2014
10.2 Layout Example
Via to GND plane
Via to VIN plane
VOUT
COUT1
L1
L0
L2
COUT0
CIN1
CIN0
VIN
Input capacitors
GND
GND
VIN
GND
B1/
B2
VIN
B0/
B1
Pin A1
VIN
B2
SW
B2
SW
B1
SW
B0
GND
B0
VIN
CIN4
GND
CVIOSYS
GND
B1/
B2
VIN
B0/
B1
VIN
B2
SW
B2
SW
B1
SW
B0
GND
B0
CVLDO
GND
B1/
B2
VIN
B0/
B1
SDA
SYS
SCL
SYS
ADD
R
VLD
O
NSLP
FB
B3-/
B4
FB
B3+/
B3
FB
B0-/
B1
FB
B0+/
B0
FB
B5
FB
B2
GND
A
GND
B4/
B5
VIN
B3/
B4
SDA
SR
SCL
SR
NRS
T
VIO
SYS
INT
VIN
GND
B4/
B5
VIN
B3/
B4
VDD
A5V
SW
B5
SW
B4
SW
B3
GND
B3
CVDD
GND
B4/
B5
VIN
B3/
B4
VIN
B5
SW
B5
SW
B4
SW
B3
GND
B3
GND
GND
VIN
VIN
CIN2
CIN3
GND
Input capacitors
COUT2
L3
L4
L5
COUT3
Figure 54. LP8754 Board Layout
版权 © 2014, Texas Instruments Incorporated
47
LP8754
ZHCSDB8A –FEBRUARY 2014–REVISED AUGUST 2014
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.2 文档支持
11.2.1 相关文档ꢀ
相关文档如下：
德州仪器 (TI) 应用手册《DSBGA 晶圆级芯片规模封装》（文献编号：SNVA009）。
11.3 商标
All trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
12 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。
48
版权 © 2014, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP875484YFQR
ACTIVE
DSBGA
YFQ
49
1000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
754A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP875484YFQR
DSBGA
YFQ
49
1000
178.0
12.4
3.06
3.2
0.9
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
DSBGA YFQ 49
SPQ
Length (mm) Width (mm) Height (mm)
208.0 191.0 35.0
LP875484YFQR
1000
Pack Materials-Page 2
MECHANICAL DATA
YFQ0049x
D
0.600±0.075
E
TMD49XXX (Rev A)
D: Max = 3.022 mm, Min =2.962 mm
E: Max = 2.882 mm, Min =2.822 mm
4215087/A
12/12
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
www.ti.com
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