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LP8863-Q1

ZHCSGN5B –MARCH 2017–REVISED JULY 2018

LP8863-Q1 具有 6 个 150mA 通道的汽车显示 LED 背光驱动器

1 特性

2 应用

1

•

符合汽车类应用的要求

•

为以下应用提供背光：

•

具有符合 AEC-Q100 标准的下列特性：

–

汽车信息娱乐系统

汽车仪表盘

–

器件温度 1 级：-40℃ 至 +125℃ 的环境运行温

度范围

智能车镜

•

输入电压工作范围：3V 至 48V

抬头显示屏 (HUD)

中央信息显示屏 (CID)

音视频导航 (AVN)

六路高精度电流阱

–

电流匹配度为 1%（典型值）

使用 152Hz LED 输出 PWM 频率时，调光比为

32000:1

3 说明

–

使用 SPI、I2C 或 PWM 输入时，最高 16 位

LED 调光分辨率

LP8863-Q1 是带有升压控制器的汽车高效 LED 驱动

器。六路高精度电流阱支持相移，它可根据使用的通道

数自动调整。可通过 SPI 或 I2C 接口单独和全局控制

电流阱亮度；也可以通过 PWM 输入全局控制亮度。

自动检测使用过的 LED 灯串并调整 LED 通道

相移

每个通道的独立电流控制

升压控制器具有基于 LED 电流阱余量电压的自适应输

出电压控制。该特性可在所有条件下将电压调节到能够

满足需要的最低水平，从而更大限度降低功耗。凭借宽

范围可调频率，LP8863-Q1 能够避免 AM 无线电频带

的干扰。

•

混合 PWM 和电流调光功能

最高 47V 输出_电压升压或 SEPIC 直流/直流控制器

–

开关频率：300kHz 至 2.2MHz

升压扩频功能可降低 EMI

升压同步输入以从外部时钟设置升压开关频率

集成电荷泵支持低 V_IN条件，如冷启动

禁用升压时，输出电压自动放电

LP8863-Q1 支持内置混合 PWM 和电流调光，从而降

低了 EMI、延长了 LED 使用寿命并提高了总光学效

率。

•

详尽的故障诊断

器件信息⁽¹⁾

简化原理图

D1

器件编号

LP8863-Q1

封装

封装尺寸（标称值）

RISENSE

Q2

L1

VIN

V_OUT

HTSSOP (38)

9.70mm x 4.40mm

CIN

COUT

RSD

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

CPUMP

RFB1

RFB2

CPUMP

Q1

GD

ISNS

系统效率

C1N

C1P

PGND

C2x

RSENSE

PGND

95

ISNSGND

VDD

CVDD

FB

VDD

DISCHARGE

GND

VLDO

90

85

CLDO

LED0

LED1

LED2

LED3

LP8863-Q1

VDDIO

IFSEL

EN

INT

SDO_PWM

SDI_SDA

SCLK_SCL

LED4

LED5

ISET

80

75

V_OUT= 29 V

V_OUT= 36 V

V_OUT= 42 V

V_OUT= 46 V

SS_ADDRSEL

BST_SYNC

RISET

PWM_FSET

BST_FSET

RPWM_FSET

RBST_FSET

0

10

20

30

40

50

60

70

80

90 100

Brightness (%)

D007

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNVSAB6

LP8863-Q1

ZHCSGN5B –MARCH 2017–REVISED JULY 2018

www.ti.com.cn

7.16 Typical Characteristics.......................................... 13

Detailed Description ............................................ 14

8.1 Overview ................................................................. 14

8.2 Functional Block Diagram ....................................... 15

8.3 Feature Description................................................. 16

8.4 Device Functional Modes........................................ 38

8.5 Programming .......................................................... 42

8.6 Register Maps......................................................... 46

Application and Implementation ........................ 68

9.1 Application Information............................................ 68

9.2 Typical Applications ................................................ 68

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 4

Pin Configuration and Functions......................... 5

Specifications......................................................... 7

7.1 Absolute Maximum Ratings ...................................... 7

7.2 ESD Ratings.............................................................. 7

7.3 Recommended Operating Conditions....................... 7

7.4 Thermal Information.................................................. 8

7.5 Electrical Characteristics........................................... 8

7.6 Protection Electrical Characteristics ......................... 8

8

9

10 Power Supply Recommendations ..................... 81

11 Layout................................................................... 82

11.1 Layout Guidelines ................................................. 82

11.2 Layout Example .................................................... 83

12 器件和文档支持 ..................................................... 84

12.1 器件支持................................................................ 84

12.2 接收文档更新通知 ................................................. 84

12.3 社区资源................................................................ 84

12.4 商标....................................................................... 84

12.5 静电放电警告......................................................... 84

12.6 术语表 ................................................................... 84

13 机械、封装和可订购信息....................................... 84

7.7 LED Current Sink and LED PWM Electrical

Characteristics ........................................................... 9

7.8 Power-Line FET and R_ISENSEElectrical

Characteristics ........................................................... 9

7.9 Input PWM Electrical Characteristics...................... 10

7.10 Boost Converter Electrical Characteristics............ 10

7.11 Oscillator ............................................................... 11

7.12 Charge Pump........................................................ 11

7.13 Logic Interface Characteristics.............................. 11

7.14 Timing Requirements for SPI Interface................. 12

7.15 Timing Requirements for I²C Interface ................ 12

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision A (June 2017) to Revision B

Page

•

已添加 TI 参考设计顶部导航链接............................................................................................................................................ 1

Added note "When internal charge pump is disabled and CPUMP pin is used as an input, max rating is 5.5 V same

as VDD." ................................................................................................................................................................................ 7

•

Added note "When internal charge pump is disabled and CPUMP pin is used as an input, max rating is 5.5V same

as VDD." ................................................................................................................................................................................ 7

•

Deleted "ƒ_OSC" row ................................................................................................................................................................. 8

Deleted "led_driver_headroom = 01b" .................................................................................................................................. 9

Changed to "325" from "200" ................................................................................................................................................. 9

Changed to "450" from "400" ................................................................................................................................................. 9

Changed to "18.6" from "18.8" ............................................................................................................................................. 11

Changed to "21.4" from "21.2" ............................................................................................................................................. 11

Added VSDO_OLand VSDO_OHtwo rows................................................................................................................................ 11

已更改 Data hold time to rising edge of SCLK in SPI Timing Diagram ............................................................................... 12

已更改 to "VDD" from "EN" .................................................................................................................................................. 14

已更改 to "90%" from "88%" ................................................................................................................................................ 18

已更改 to "1.21 V" from "1.2 V" ........................................................................................................................................... 19

已更改 to "1.21 V" from "1.2 V" ........................................................................................................................................... 20

已更改 to "1.76 V" from "1.423 V" ....................................................................................................................................... 20

已更改 to "1.21 V" from "1.2 V" ........................................................................................................................................... 21

已更改 to "I_{SEL_MAX}" from "ISEL_MAX" ................................................................................................................................. 22

已更改 to "1.21 V and 2560" from "1.2 V and 2580" in 公式 11........................................................................................... 24

2

LP8863-Q1

www.ti.com.cn

ZHCSGN5B –MARCH 2017–REVISED JULY 2018

修订历史记录 (接下页)

•

已更改 to "DITHER_SELECT[2:0]" from "DITHER_SELECT[1:0]" ...................................................................................... 29

已更改 to "110 ms" from "1600 milliseconds" ...................................................................................................................... 34

已更改 to "overcurrent" from "undervoltage" ....................................................................................................................... 34

已更改 to "Boost does not start up. Fault is cleared by VDD cycling with correct resistor connection at FSET pin."

from "Device starts up using fail-safe values." .................................................................................................................... 36

•

已更改 to "400-ms" from "300-ms" ...................................................................................................................................... 39

已更改 to "VDD" from "EN" .................................................................................................................................................. 39

已添加 " For proper operation of discharge function, pull the EN pin before VDD pin. VIN and VDDIO can be set low

any time after EN low." ........................................................................................................................................................ 41

•

Changed to "8B0h' from "B0h" ............................................................................................................................................ 49

Changed to "R/W-2h' from 'R/W-0h" ................................................................................................................................... 49

Changed to "2h" from "0h" ................................................................................................................................................... 49

Changed to "100h" from "0h" ............................................................................................................................................... 57

Changed to "100h" from "0h" ............................................................................................................................................... 58

Changed to "000h - 0FFh = 0 °C to 255 °C, 100h - 1FFh = –256 °C to –1 °C" from "0h = –1 to –255 °C" ........................ 58

Changed to "000h - 0FFh = 0 °C to 255 °C, 100h - 1FFh = –256 °C to –1 °C" from "0h = –1 to –255 °C" ....................... 58

Changed to "1C0h" from "0h" .............................................................................................................................................. 63

Changed to "1C0h" from "0h" .............................................................................................................................................. 64

Changed to "2882h" from "882h" ......................................................................................................................................... 64

Changed to "2h" from "0h" ................................................................................................................................................... 64

Changed Description of FSM_LIVE_STATUS .................................................................................................................... 65

已更改 to "V_IN(min)× D / ( ƒ_SW× L )" from "V_IN(min)× D / ƒ_SW× L" ........................................................................................... 70

已更改 to "Current set resistor for 100 mA maximum" from "Maximum current set resistor" ............................................. 73

已更改 to "43.5 V" from "40 V" ............................................................................................................................................ 75

已更改 to "10-µF" from "10-µH" ........................................................................................................................................... 78

已更改 to "Current set resistor for 150 mA max" from "Maximum current set resistor" ...................................................... 80

Changes from Original (March 2017) to Revision A

Page

•

首次公开发布的完整产品说明书 ............................................................................................................................................. 1

3

LP8863-Q1

ZHCSGN5B –MARCH 2017–REVISED JULY 2018

www.ti.com.cn

5 Device Comparison Table

LP8863-Q1

LP8860-Q1

LP8862-Q1

LP8861-Q1

TPS61193-Q1

TPS61194-Q1

TPS61196-Q1

V_INrange

3 V to 48 V

4.5 V to 45 V

8 V to 30 V

Number of LED

channels

6

4

2

4

3

4

6

LED current /

channel

150 mA

160 mA

100 mA

200 mA

I2C/SPI support

SEPIC support

Yes

No

Yes

4

LP8863-Q1

www.ti.com.cn

ZHCSGN5B –MARCH 2017–REVISED JULY 2018

6 Pin Configuration and Functions

DCP Package

38-Pin HTSSOP

Top View

VDD

SD

1

2

3

4

5

6

7

8

9

38 GND

37

36 NC

VLDO

VSENSE_N

35

34

NC

VSENSE_P

C1N

PWM_FSET

33 BST_FSET

C1P

CPUMP

32

31

30

29

28

SS_ADDRSEL

SCLK_SCL

SDI_SDA

GD

SDO_PWM

BST_SYNC

GD 10

PGND 11

PGND 12

27 IFSEL

INT

ISNSGND 13

26

25

24

23

14

15

16

17

ISNS

FB

VDDIO

EN

DISCHARGE

LED5

ISET

22 LED0

21 LED1

20 LED2

Exposed Pad

(GND_LED)

LED4 18

LED3 19

5

LP8863-Q1

ZHCSGN5B –MARCH 2017–REVISED JULY 2018

www.ti.com.cn

Pin Functions

TYPE

DESCRIPTION

NO.

NAME

Power input for LDO, charge pump, and analog blocks - a 4.7–µF decoupling capacitor is

recommended.

1

VDD

Power

2

3

4

5

6

SD

VSENSE_N

VSENSE_P

C1N

Analog

Power line FET control. If unused, leave this pin floating.

Pin for input current sense. If input current sense is not used tie to VSENSE_P.

Pin for OVP/UVLO protection and input current sense.

Negative pin for charge pump flying capacitor. If feature not used, leave this pin floating.

Positive pin for charge pump flying capacitor. If feature not used, leave this pin floating.

C1P

Charge pump output pin. If charge pump is not used connect to VDD. TI recommends a

10–µF decoupling capacitor.

7

CPUMP

Power

8

CPUMP

GD

Power

Analog

Ground

Analog

Input

Charge pump output pin. If charge pump is not used connect to VDD.

Gate driver output for boost FET

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

GD

Gate driver output for boost FET

PGND

ISNSGND

ISNS

Power ground

Current sense resistor GND of boost controller

Boost current sense pin

FB

Boost feedback input

DISCHARGE

LED5

LED4

LED3

LED2

LED1

LED0

ISET

Boost output voltage discharge pin. Leave floating if unused.

LED current sink output. If unused tie to ground.

LED current setting input

EN

Enable input

VDDIO

Power

Supply input for digital IO pins - a 4.7–µF decoupling capacitor is recommended.

LP8863-Q1 device fault interrupt output, open drain. Requires an external pullup resistor to

VDDIO - a 10-kΩ pullup resistor is recommended.

26

27

28

INT

Output

Input

IFSEL

Serial control interface selection: low = SPI, high = I2C

Input for synchronizing boost. When synchronization is not used, connect this pin to ground

to disable spread spectrum or to VDDIO to enable spread spectrum.

BST_SYNC

Input

IFSEL=GND, slave data output for SPI. IFSEL=VDDIO, PWM input for brightness control. Tie

to GND if unused.

29

SDO_PWM

Input/Output

30

31

32

33

34

35

36

SDI_SDA

SCLK_SCL

SS_ADDRSEL

BST_FSET

PWM_FSET

NC

Input

Analog

N/A

IFSEL=GND, slave data input for SPI; IFSEL=VDDIO, serial data for I2C

IFSEL=GND, serial clock for SPI; IFSEL=VDDIO, serial clock for I2C

IFSEL=GND, slave select for SPI; IFSEL=VDDIO, I2C address selection

Resistor for setting boost FSW frequency. Do not leave floating.

Resistor for setting LED PWM frequency. Do not leave floating.

No connect — leave floating.

NC

N/A

No connect — leave floating.

Internal 1.8-V LDO output. Connect bypass capacitor to this pin - a 10–µF decoupling

capacitor is recommended.

37

VLDO

Power

38

GND

Ground

Ground for LDO — charge pump and analog blocks

LED ground connection

DAP

GND_LED

6

LP8863-Q1

www.ti.com.cn

ZHCSGN5B –MARCH 2017–REVISED JULY 2018

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

-0.3

MAX

50

UNIT

V_SENSE_P, VSENSE_N, SD, LED0 to LED5, FB, DISCHARGE

V

Voltage on pins

VDD, EN, ISNS

5.5

VDDIO, SCLK_SCL, SDI_SDA, SDO_PWM, SS_ADDRSEL, INT,

IFSEL, BST_FSET, PWM_FSET, ISET

-0.3

3.6

Voltage on pins

V

(2)

C1P, C1N, CPUMP , GD

-0.3

12

2

VLDO

Thermal

Continuous power dissipation

Internally

limited

Internally

limited

Ambient temperature

-40

125

150

260

150

°C

Junction temperature

Maximum lead temperature (soldering)

Storage temperature, Tstg

-65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) When internal charge pump is disabled and CPUMP pin is used as an input, maximum rating is 5.5 V same as VDD.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per AEC Q100-002,⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

Electrostatic

discharge

V_(ESD)

All pins

V

Corner pins

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted). All voltages are with respect to the potential at the GND

pins.

MIN

3

NOM

MAX

48

UNIT

V_SENSE_P, VSENSE_N, SD

Voltage on pins

EN, ISNS

12

V

0

48

0

5.5

VDD

2.7

3.3/5

Voltage on pins

VDDIO, SCLK_SCL, SDI_SDA, SDO_PWM, SS_ADDRSEL,

INT, IFSEL, BST_FSET, PWM_FSET, ISET

1.65

1.8/3.3

3.6

VLDO

0

1.8

2

11

(1)

C1P, C1N, CPUMP , GD

6.6/10

Thermal

Ambient temperature

-40

125

°C

(1) When internal charge pump is disabled and CPUMP pin is used as an input, maximum rating is 5.5 V same as VDD.

7

LP8863-Q1

ZHCSGN5B –MARCH 2017–REVISED JULY 2018

www.ti.com.cn

7.4 Thermal Information

LP8863

THERMAL METRIC⁽¹⁾

DCP (HTSSOP)

UNIT

38 PINS

32.4

19.5

8.8

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

ψ_JB

8.9

R_θJC(bot)

2.7

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

Limits apply over the full operating ambient temperature range -40°C ≤ T_A≤ +125°C, Unless otherwise specified, V_DD= 3.3V,

V_IN= 12V, V_DDIO= 1.8V

PARAMETER

TEST CONDITIONS

V_DD< V_POR, EN = L

MIN

TYP

0.3

75

MAX

2

UNIT

μA

Shutdown mode current, VDD pin

Standby mode current, VDD pin

V_DD> V_POR, EN = L

300

μA

LP8863-Q1 enabled, boost enabled

I_Q

(I_LED= 150mA), CP enabled, V_DD

3.3V, f_SW= 300kHz, Boost FET -

IPD25N06S4L-30

=

Active mode current , VDD pin

Power-on reset threshold

15

40⁽¹⁾

2.65

mA

V

V_POR

VDD pin voltage.

(1) Ensured by design.

7.6 Protection Electrical Characteristics

Limits apply over the full operating ambient temperature range –40°C ≤ T_A≤ +125°C, Unless otherwise specified, V_DD= 3.3 V,

V_IN= 12 V, V_DDIO= 1.8 V.

PARAMETER

TEST CONDITIONS

V_DDfalling

MIN

TYP

2.7

MAX

UNIT

V

VDD_UVLO

V_DDUVLO threshold

2.6

2.8

VDD_{UVLO_}V_DDUVLO hysteresis

0.1

V

H

VIN_UVLO

VIN_{UVLO_H}V_INUVLO hysteresis

VIN_OVPV_INOVP threshold

VIN_{OVP _H}V_INOVP hysteresis

V_INUVLO threshold

V_INfalling

2.7

40.8

155

2.8

0.35

43

2.9

45.2

175

V

V_INrising

V

2.5

V

T_TSD

Thermal shutdown threshold

Temperature rising

165

°C

Temperature falling from TSD

threshold

T_{TSD_H}

Thermal shutdown hysteresis

20

T_{TWR_H}

T_{TWR_L}

V_DDIO

Thermal high warning threshold

Thermal low warning threshold

V_DDIOsupply voltage

temperature_limit_high = 0x07D

temperature_limit_low = 0x069

115

95

125

105

135

115

3.6

°C

V

1.65

VDDIOI_Q

V_LDO

V_DDIOsupply current

1

μA

V

LDO output voltage

1.8

8

LP8863-Q1

www.ti.com.cn

ZHCSGN5B –MARCH 2017–REVISED JULY 2018

7.7 LED Current Sink and LED PWM Electrical Characteristics

Limits apply over the full operating ambient temperature range -40°C ≤ T_A≤ +125°C, Unless otherwise specified, V_DD= 3.3 V,

V_IN= 12 V, V_DDIO= 1.8 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

0.1

MAX UNIT

Outputs LED0 to LED5 = V_OUT

45 V, EN = Low

=

I_LEAKAGE

Leakage current

2.5

µA

I_MAX

Max LED sink current

LED0 to LED5

150

mA

I_ACC

LED sink current accuracy⁽¹⁾

LED sink current matching⁽¹⁾

I_OUT= 150 mA, PWM duty =100%

I_OUT= 150 mA

−4%

4%

3.5%

0.79

I_MATCH

V_SAT

1%

0.4

(2)

Saturation voltage

V

f_{PWM_OUT_MIN}

Minimum LED PWM output

frequency

0.152

kHz

f_{PWM_OUT_MAX}

DIM

Maximum LED PWM output

frequency

19.5

kHz

Dimming ratio

f_{PWM_OUT}= 152 Hz

32000:1

8000:1

f_{PWM_OUT}= 4.8 kHz with hybrid

dimming

f_{PWM_OUT}= 4.8 kHz

1000:1

0.55

0.5

V_HEADROOM

LED sink headroom

V

V_{HEADROOM_HYST}

LED sink headroom hysteresis

shorted_led_thresh = 000

shorted_led_thresh = 001

shorted_led_thresh = 010

shorted_led_thresh = 011

shorted_led_thresh = 100

shorted_led_thresh = 101

shorted_led_thresh = 110

shorted_led_thresh = 111

2.6

3.0

3.5

3.8

V_LEDSHORT

LED short detection threshold

LED output minimum pulse

V

4.1

4.6

5.2

5.9

t_{PWM_OUT}

200

ns

(1) Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current.

Matching is the maximum difference from the average. For the constant current sinks on the part (LED0 to LED5), the following are

determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG).

Matching number is calculated: (MAX-MIN)/AVG. The typical specification provided is the most likely norm of the matching figure for all

parts. LED current sinks were characterized with 1 V headroom voltage. Note that some manufacturers have different definitions in use.

(2) Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at 1 V.

7.8 Power-Line FET and R_ISENSEElectrical Characteristics

Limits apply over the full operating ambient temperature range -40°C ≤ T_A≤ +125°C, Unless otherwise specified, V_DD= 3.3 V,

V_IN= 12 V, V_DDIO= 1.8 V.

PARAMETER

TEST CONDITIONS

R_ISENSE= 20 mΩ

MIN

TYP

11

1

MAX UNIT

I_OCP

Input over current threshold

VSENSE_P pin leakage current

VSENSE_N pin leakage current

SD pin leakage current

Power line FET soft start

SD Pull-down current

9.35

12.65

A

I_{LEAK_VSENSE_P}

I_{LEAK_VSENSE_N}

I_{LEAK_SD}

V_{SENSE_P}= 48 V

V_{SENSE_N}= 48 V

V_SD= 48 V

µA

ms

µA

1

t_{SOFT_START}

I_SD

When R_ISENSEis used

R_SD= 20 kΩ

50

325

450

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LP8863-Q1

ZHCSGN5B –MARCH 2017–REVISED JULY 2018

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7.9 Input PWM Electrical Characteristics

Limits apply over the full operating ambient temperature range -40°C ≤ T_A≤ +125°C, Unless otherwise specified, V_DD= 3.3V,

V_IN= 12V, V_DDIO= 1.8V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

f_{PWM_IN}

PWM input frequency

PWM input minimum on time

PWM input resolution

100

20 000

Hz

ns

bit

t_{PWM_MIN_ON}

INPWM_RES

200

16

f_{PWM_IN}= 100 Hz

f_{PWM_IN}= 20 kHz

10

7.10 Boost Converter Electrical Characteristics

Limits apply over the full operating ambient temperature range -40°C ≤ T_A≤ +125°C, Unless otherwise specified, V_DD= 3.3V,

V_IN= 12V, V_DDIO= 1.8V

PARAMETER

Input voltage

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN

3

48

V

Boost mode (R_FBTOP= 910 kΩ, R_FBBOT

100 kΩ)

=

20

6

47

24

V_OUT

Output voltage

V

SEPIC mode (R_FBTOP= 560 kΩ, R_FBBOT

170 kΩ)

=

ƒ_SW

Switching frequency

BST_FSET = 3.93 kΩ

303

400

kHz

BST_FSET = 4.75 kΩ

BST_FSET = 5.76 kΩ

606

BST_FSET = 7.87 kΩ

800

BST_FSET = 11 kΩ

1000

1250

1667

2200

BST_FSET = 17.8 kΩ

BST_FSET = 42.2 kΩ

BST_FSET = 140 kΩ

Boost mode, I_OUT= 6 x 150 mA

Boost mode, I_OUT= 6 x 85 mA

SEPIC mode

5.5⁽¹⁾

10⁽¹⁾

5⁽¹⁾

11

V_OUT/V_IN

Max conversion ratio

0.2

9

I_MAX

Boost switching current limit

External FET gate drive voltage

R_SENSE= 20 mΩ

10

5

A

V

VDD = 5 V +/-10%, CP Disabled

VDD = 3.3 V +/-10%, CP Enabled

VDD = 5 V +/-10%, CP Enabled

4.5

6

5.5

V_GD

6.6

10

7.2

9

11

Source, V_GD/(GDR_DSON+ Total resistance

to gate input of SW FET) must not be

higher than 2.5A

R_DSONof internal high side FET to

drive gate of external FET

GDR_DSONH

GDR_DSONL

1.4

Ω

R_DSONof internal low side FET to

drive gate of external FET

Sink, V_GD/(GDR_DSON+ Total resistance to

gate input of SW FET) must not be higher

than 2.5A

0.75

Delay from beginning of boost soft start to

when LED drivers can begin

t_START-UP

Start-up time

50

ms

T_ON

Minimum switch on time

Minimum switch off time

120

70

ns

T_OFF

BOOST_OVP low threshold at FB

V_{BST_OVPL}

V_{BST_OVPH}

1.423

1.76

V

BOOST_OVP high threshold at FB

(1) Ensured by design

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7.11 Oscillator

Limits apply over the full operating ambient temperature range -40°C ≤ T_A≤ +125°C, Unless otherwise specified, V_DD= 3.3V,

V_IN= 12V, V_DDIO= 1.8V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f_OSC

Oscillator frequency

18.6

20

21.4

MHz

7.12 Charge Pump

Limits apply over the full operating ambient temperature range -40°C ≤ T_A≤ +125°C, Unless otherwise specified, V_DD= 3.3V,

V_IN= 12V, V_DDIO= 1.8V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f_CP

Charge pump switching frequency

387

417

447

kHz

7.13 Logic Interface Characteristics

Limits apply over the full operating ambient temperature range -40°C ≤ T_A≤ +125°C, Unless otherwise specified, V_DD= 3.3V,

V_IN= 12V, V_DDIO= 1.8V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

0.4

UNIT

LOGIC INPUT EN

VEN_IL

VEN_IH

IENI

Input low level

Input high level

Input current

V

1.2

5

30

µA

EN pin internal pull-down

resistance

R_PDEN

MΩ

LOGIC INPUT SCLK_SCL, SDI_SDA, SS_ADDRSEL, PWM, IF_SEL, BST_SYNC

0.2 x

VDDIO

V_IL

V_IH

Input low level

Input high level

V

0.8 x

VDDIO

I_I

Input current

5

µA

V

VSDO_OL

Output low level

I_OUT= 3 mA

0.3

0.5

0.7 x

VDDIO VDDIO

0.9 x

VSDO_OH

Output high level

I_OUT= –2 mA

V

LOGIC OUTPUT SDA

VSDA_OL

Output low level

I = 3 mA

0.3

0.5

1

V

ISDA_LEAKAGEOutput leakage current

LOGIC OUTPUT INT

V = 5.5 V

μA

VINT_OL

Output low level

I_OUT= 3 mA

0.3

0.5

1

V

IINT_LEAK

Output leakage current

μA

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7.14 Timing Requirements for SPI Interface

MIN

100

50

NOM

MAX

UNIT

ns

1

Cycle time

2

Enable lead time

Enable lag time

Clock low time

Clock high time

Data setup time

Data hold time

Disable time

ns

3

50

ns

4

45

ns

5

45

ns

6

20

ns

7

20

ns

8

30

35

ns

9

Data valid

ns

10

C_b

SS inactive time

Bus capacitance

50

5

ns

40

pF

7.15 Timing Requirements for I²C Interface

MIN

NOM

MAX

UNIT

kHz

µs

ƒ_SCLK

Clock frequency

400

1

2

3

4

5

6

7

8

9

10

Hold time (repeated) START Condition

Clock low time

0.6

1.3

µs

Clock high time

600

50

ns

Set-up time for a repeated START condition

Data hold time

ns

Data setup time

100

ns

Rise Time of SDA and SCL

Fall Time of SDA and SCL

Set-up time for STOP condition

Bus free time between a STOP and a START Condition

300

ns

600

1.3

ns

µs

SS

t10t

t2t

t1t

7

4

5

3

SCLK

SDI

6

MSB IN

BIT 30

BIT 16

R/W

BIT 15

BIT 1

LSB IN

9

8

High

Impedance

9

SDO

MSBOUT

LSB OUT

Address

Data

图 1. SPI Timing Diagram

SDA

SCL

10

8

7

6

1

7

9

2

8

4

1

5

3

图 2. I2C Timing Diagram

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7.16 Typical Characteristics

Unless otherwise specified: C_IN= C_OUT= 2 × 10-μF ceramic and 2 × 33-μF electrolytic, V_DD= 3.3 V, charge pump enabled,

T_A= 25°C

100

95

90

85

80

75

100

95

90

85

80

75

70

65

60

V_IN= 9 V

V_IN= 12 V

V_IN= 16 V

V_IN= 24 V

V_IN= 12 V

V_IN= 16 V

V_IN= 24 V

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

Brightness (%)

8 LEDs/string

6 strings

Brightness (%)

8 LEDs/string

6 strings

D001

D002

ƒ_SW= 303 kHz

L1 = 22 µH

150 mA/string

ƒ_SW= 2.2 MHz

L1 = 10 µH

150 mA/string

图 3. Boost Efficiency

图 4. Boost Efficiency

90

85

80

75

70

65

60

55

85

80

75

70

65

60

55

50

V_IN= 6 V

V_IN= 12 V

V_IN= 17 V

V_IN= 6 V

V_IN= 12 V

V_IN= 17 V

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

Brightness (%)

D003

D004

ƒ_SW= 303 kHz

2 LEDs/string

150 mA/string

6 strings

ƒ_SW= 2.2 MHz

2 LEDs/string

150 mA/string

6 strings

L1 = 10 µH, L2 = 15 µH

L1 = L2 = 4.7 µH

图 5. SEPIC Efficiency

图 6. SEPIC Efficiency

150

2.5

2.0

1.5

1.0

0.5

0.0

15 mA

25 mA

50 mA

80 mA

120 mA

120

150 mA

90

60

30

0

8192 16384 24576 32768 40960 49152 57344 65536

0

8192 16384 24576 32768 40960 49152 57344 65536

Brightness Code

D005

D006

图 7. Current Linearity

图 8. Current Matching

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ZHCSGN5B –MARCH 2017–REVISED JULY 2018

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8 Detailed Description

8.1 Overview

The LP8863-Q1 device is a high-voltage LED driver for automotive infotainment, clusters, and other automotive

display LED backlight applications. It supports conventional LED backlight applications and cluster-mode

applications requiring independent duty and current control of each channel.

The LP8863-Q1 device uses the PWM input for brightness control by default. Alternatively, the brightness can

also be controlled by I2C or SPI. When two LP8863-Q1 devices are used in the system, individual I2C addresses

can be selected independently with the SS_ADDRSEL pin. In cluster-mode applications each of the six LED

brightness levels can be individually controlled via the I2C or SPI interface.

The boost frequency, LED PWM frequency, and LED string current are configured with external resistors through

the BST_FSET, PWM_FSET, and ISET pins. The INT pin is used to report faults to the system. Fault interrupt

status can be cleared with the I2C, SPI interface, or is cleared on the falling edge of the VDD pin.

The LP8863-Q1 supports pure PWM dimming and hybrid dimming; that is, combined PWM and current

brightness control. By default PWM dimming mode is enabled, but can be changed using the I2C or SPI

interface.

The six LED current drivers provide up to 150 mA per output and can be tied together to support higher current

LEDs. The maximum output current of the LED drivers is set with the ISET resistor and can be optionally scaled

by the LEDx_CURRENT[11:0] register bits with I2C or SPI interfaces. The LED output PWM frequency is set with

a PWM_FSET resistor. The number of connected LED strings is automatically detected, and the device

automatically selects the correct phase shift. For example, if four strings are connected, the LED outputs are

phase shifted by 90 degrees (= 360 / 4); if 6 strings are connected, the LED outputs are phase shifted by 60

degrees (= 360 / 6). Outputs that are not used must be connected to GND. Unused outputs are disabled and

excluded from adaptive voltage and do not generate open/short LED faults. When I2C is available, LED outputs

can be re-configured in cluster mode to support up to 6 individually controlled channels or, alternatively, 3 to 5

channels for a display and 3 to 1 individual channels for indicator lights. In this mode all strings can be connected

to the boost of LP8863-Q1 or an external boost can be used for indicator channels.

A resistor divider connected from V_OUTto the FB pin sets the maximum voltage of the boost. For best efficiency

the boost voltage is adapted automatically to the minimum necessary level needed to drive the LED strings by

monitoring all the LED output voltage drops in real time. The switching frequency of the boost regulator can be

set between 300 kHz and 2.2 MHz by the BST_FSET resistor. The boost has a start-up feature that reduces the

peak current from the power-line during start-up. The LP8863-Q1 also can control a power-line FET to reduce

battery leakage when disabled and provide isolation and protection in the event of a fault.

Fault detection features of LP8863-Q1 include:

•

Open-string and shorted LED detection

LED fault detection prevents system overheating in case of open or short in some of the LED strings

–

•

Boost overcurrent

Boost overvoltage

Device undervoltage protection

–

Threshold sensing from VDD pin

V_INinput overvoltage protection (OVP)

Threshold sensing from VSENSE_P pin

V_INinput undervoltage protection

Threshold sensing from VSENSE_P pin

V_INinput overcurrent protection (OCP)

Threshold sensing across R_ISENSEresistor

•

–

•

Thermal shutdown in case of die overtemperature

Die temperature read-out and programmable thermal window detector

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8.2 Functional Block Diagram

VSENSE_P

VSENSE_N SD

VDDIO

CPUMP

GD

Powerline FET

Control

GD

PGND

C1N

C1P

VDD

Charge

Pump

ISNS

+

-

Boost

Controller

ISNSGND

Analog

FB

VLDO

LDO

Discharge

DISCHARGE

Digital

OSC

20 MHz

PWM_FSET

BST_FSET

EEPROM

LED0

LED1

LED2

LED3

LED4

LED5

ISET

6 x LED

Current

Sinks

ADC

EN

INT

Digital Blocks

(FSM, Adaptive

Voltage Control,

Fault Logic, etc.)

BST_SYNC

IFSEL

SS_ADDRSEL

SDO_PWM

SDI_SDA

SCLK_SCL

LED

Current

Setting

SPI / I2C

TEMP

Sensor

Analog Blocks

(VREF, TSD, etc.)

ADC

GND

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8.3 Feature Description

8.3.1 Control Interface

Device control interface includes:

•

EN is the enable input for the LP8863-Q1 device.

INT is an open-drain fault output (indicating fault condition detection or thermal threshold crossing).

IFSEL is used for selecting between I2C and SPI.

–

SPI is a 4-wire interface using SCL, SDI, SDO, and SS pins.

When SPI is selected the brightness must be controlled using the DISP_BRT and BRT_MODE registers.

I2C is a 2-wire interface using SCL and SDA pins.

When I2C is selected, the ADDRSEL pin is used to select between two alternate slave addresses.

When I2C is selected, the BRT_MODE register setting is used to select whether the brightness is

controlled by the DISP_BRT register or PWM input pin. The PWM pin is selected by default so that an I2C

interface is not required.

•

BST_SYNC is used to input an external clock for the boost switching frequency and control the internal boost

clock mode.

–

The external clock is auto detected at start-up and, if missing, the internal clock is used.

Optionally, the BST_SYNC can be tied to VDDIO to enable the boost spread spectrum function or tied to

GND to disable it.

•

ISET pin to set the maximum LED current level per string.

BST_FSET pin to set the boost switching frequency.

PWM_FSET pin to set the LED output PWM dimming frequency.

Control interface is selected with IF_SEL pin according to 表 1.

表 1. Control Interface Selection, SPI or I2C

IF_SEL

VDDIO (1)

GND (0)

SERIAL INTERFACE

I2C

SPI

In I2C mode the ADDRSEL is used to select between two unique slave addresses, and the PWM input may be

used to control the brightness.

8.3.2 Boost Controller

The LP8863-Q1 current-mode-controlled boost DC/DC controller generates the bias voltage for the LEDs. The

boost is a current-mode-controlled topology with an 8-A cycle by cycle current limit. The boost converter senses

the switch current and across the external sense resistor connected between ISNS and ISNSGND. A 25-mΩ

sense resistor results in an 8-A cycle by cycle current limit.. Maximum boost voltage is configured with external

FB-pin resistor divider connected between V_OUTand FB. The FB-divider equation is described in Boost Adaptive

Voltage Control.

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D1

L1

VIN

VBOOST

CIN

COUT

OCP

ADAPTIVE

VOLTAGE

CONTROL

LIGHT

LOAD

CPUMP

GD

OVP

R

RFB1

FB

R

-

GM

Q1

RFB2

+

S

GATE

DRIVER

PGND

BOOST OSCILLATOR

BST_FSET

ADC

RBST_FSET

ISNS

OFF/BLANK TIME

PULSE GENERATOR

CURRENT RAMP

GENERATOR

BST_SYNC

RISENSE

MUX

GM

G

ISNS_GND

图 9. Boost Controller Block Diagram

The boost switching frequency is adjustable from 300 kHz to 2.2 MHz via an external resistor at BST_FSET (see

表 2).

表 2. Boost Frequency Selection

R_BST_FSET (kΩ)

BOOST FREQUENCY (kHz)

3.92

4.75

5.76

7.87

11

303

400

606

800

1000

1250

1667

2200

17.8

42.2

140

8.3.2.1 Boost Adaptive Voltage Control

The LP8863-Q1 boost DC/DC converter generates the bias voltage for the LEDs. During normal operation, boost

output voltage is adjusted automatically based on the LED current sink headroom voltages. This is called

adaptive boost control. The number of used LED outputs is auto detected and only the active LED outputs are

monitored to control the adaptive boost voltage. Any LED strings with open or short faults are also removed from

the adaptive voltage control loop. The LED driver pin voltages are periodically monitored by the control loop and

the boost voltage is raised if any of the LED outputs falls below the low headroom threshold. The boost voltage is

lowered if all the LED outputs are above the high headroom threshold. See 图 10 for how the low and high

headroom thresholds automatically scale based on the LED string current and V_SATlevel being used.

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LED0-5 PIN

VOLTAGE

Adaptive Control

makes no change

Adaptive Control

makes no change

Adaptive Control

steps voltage down

Adaptive Control

steps voltage up

SHORTED_LED_THRESHOLD

Only one output (LED0)

above threshold

All LED0-5 outputs above

threshold

One output (LED5) below

threshold

LED_DRV_HEADROOM

+0.5v

LED_DRV_HEADROOM

图 10. Adaptive Boost Voltage Control Loop Function

The external resistive divider (R_FB1, R_FB2) defines both the minimum and maximum adaptive boost voltage levels.

The FB circuit operates the same in boost and SEPIC topologies. Choose maximum boost voltage based on the

maximum LED string voltage specification. Before the LED drivers are active the boost starts up to the initial

boost level. The initial boost voltage is approximately 90% of maximum boost voltage. Once the LED driver

channels are active, the boost output voltage is adjusted automatically based on LED current sink headroom

voltage. The FB pin resistor divider also scales the boost OVP and undervoltage levels.

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8.3.2.1.1 FB Divider Using Two-Resistor Method

A typical FB-pin circuit uses a two-resistor divider circuit between the boost output voltage and ground.

V_IN

VBOOST

+

BSTOVPH

BSTOVPL

BSTOCP

VOVPH

VOVPL

VUVP

-

+

-

+

RFB1

FB

-

COMP

+

RFB2

+

ISEL[10:0]

VBG

-

图 11. Two-Resistor FB Divider Circuit

Maximum boost voltage can be calculated with 公式 1. The maximum boost voltage can be reached during

OPEN string detection or if all LED strings are left disconnected.

V_BG

V_MAXBOOST= ((

) + I_{SEL_MAX})) ì R_FB1+ V_BG

R_FB2

where

•

V_BG= 1.21 V

I_{SEL_MAX}= 38.7 µA

R_FB2recommended value is 100 kΩ for boost operation and 170 kΩ for SEPIC operation.

(1)

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50

45

40

35

30

25

20

15

10

5

100

150

200

250

300

350

400

450

500

550

600

650

700

750

800

850

900

950

R_FB1 (kOhm)

R_FB2= 100 kΩ

图 12. Maximum Boost Output Voltage vs. RFB1 Resistor Value

The minimum boost voltage must be less than the minimum LED string voltage. Minimum boost voltage is

calculated with 公式 2:

V_BG

V_MINBOOST= (

) ì R_FB1+ V_BG

R_FB2

where

•

V_BG= 1.21 V

(2)

When the boost OVP_LOW level is reached the boost controller stops switching the boost FET and the

BSTOVPL_STATUS bit is set. The LED drivers are still active during this condition, and the boost resumes

normal switching operation once the boost output level falls. The boost OVP low voltage threshold is calculated

with 公式 3:

V

V_{BOOST _OVP_LOW}= (( ^OVPL) + I_{SEL_MAX}) ì R_FB1+ V_OVPL

R_FB2

where

•

V_OVPL= 1.423 V

I_{SEL_MAX}= 38.7 µA

(3)

When the boost OVP_HIGH level is reached the boost controller enters fault recovery mode, and the

BSTOVPH_STATUS bit is set. The boost OVP high-voltage threshold is calculated with 公式 4:

V

V_{BOOST _OVP_HIGH}= (( ^OVPH) + I_{SEL_MAX}) ì R_FB1+ V_OVPH

R_FB2

where

•

V_OVPH= 1.76 V

I_{SEL_MAX}= 38.7 µA

(4)

When the boost UVP level is reached the boost controller starts a 100-ms OCP counter. The LP8863-Q1 device

enters the fault recovery mode and sets the BSTOCP_STATUS bit if the boost voltage does not rise above the

UVP threshold before the timer expires. The boost UVP voltage when adaptive voltage control is at the maximum

output voltage is calculated with 公式 5:

V

V_{BOOST _UVP}= (( ^UVP) + I_{SEL_MAX}) ì R_FB1+ V_UVP

R_FB2

where

•

V_UVP= 0.886 V

I_{SEL_MAX}= 38.7 µA

(5)

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ZHCSGN5B –MARCH 2017–REVISED JULY 2018

8.3.2.1.2 FB Divider Using Three-Resistor Method

A FB-pin circuit using a three-resistor divider circuit can be used for applications where less than 200-kΩ

resistors are required.

V_IN

VBOOST

+

BSTOVPH

BSTOVPL

BSTOCP

VOVPH

VOVPL

VUVP

-

+

-

+

RFB1

RFB3

FB

-

COMP

+

RFB2

+

ISEL[10:0]

VBG

-

图 13. Three-Resistor FB Divider Circuit

Maximum boost voltage can be calculated with 公式 6. The maximum boost voltage can be reached during

OPEN string detection or if all LED strings are left disconnected.

»

…

ÿ

»

…

ÿ

»

…

ÿ

Ÿ

⁄

1

V_MAXBOOST

=

((I

ì R_FB3) + V_BG) ì (

)

+ I

ì R_FB1+ (I_{SEL_MAX}ì R_FB3)+ V_BG

Ÿ

_{SEL_MAX}Ÿ

SEL_MAX

R_FB2

……

Ÿ

⁄

Ÿ

⁄

where

•

V_BG= 1.21 V

I_{SEL_MAX}= 38.7 µA

R_FB2recommended value is 6 kΩ for boost operation and 10 kΩ for SEPIC operation

R_FB3recommended value is 27 kΩ for boost operation and 30 kΩ for SEPIC operation

(6)

The minimum boost voltage must be less than the minimum LED string voltage. Minimum boost voltage is

calculated with 公式 7:

R

V_MINBOOST= (V_BGì ( ^FB1)) + V_BG

R_FB2

(7)

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When the boost OVP_LOW level is reached the boost controller stops switching the boost FET, and the

BSTOVPL_STATUS bit is set. The LED drivers are still active during this condition, and the boost resumes

normal switching operation once the boost output level falls. The boost OVP low voltage threshold is calculated

with 公式 8:

»

…

ÿ

»

…

ÿ

»

ÿ

Ÿ

⁄

1

V_{BOOST_OVP_LOW}

=

((I

ì R_FB3) + V_OVPL) ì (

)

+ I

ì R_FB1+ (I_{SEL_MAX}ì R_FB3)+ V_OVPL

Ÿ

_{SEL_MAX}Ÿ

…

SEL_MAX

R_FB2

……

Ÿ

⁄

Ÿ

⁄

where

•

V_OVPL= 1.423 V

I_{SEL_MAX}= 38.7 µA

(8)

When the boost OVP_LOW level is reached the boost controller enters fault recovery mode, and the

BSTOVPH_STATUS bit is set. The boost OVP high-voltage threshold is calculated with 公式 9:

»

…

ÿ

»

…

ÿ

»

…

ÿ

Ÿ

⁄

1

V_{BOOST _OVP_HIGH}

=

((I

ì R_FB3) + V_OVPH) ì (

)

+ I

ì R_FB1+ (I_{SEL_MAX}ì R_FB3)+ V_OVPH

Ÿ

_{SEL_MAX}Ÿ

SEL_MAX

R_FB2

……

Ÿ

⁄

Ÿ

⁄

where

•

V_OVPH= 1.76 V

I_{SEL_MAX}= 38.7 µA

(9)

When the boost UVP level is reached the boost controller starts a 100-ms OCP counter. The LP8863-Q1 device

enters the fault recovery mode and sets the BSTOCP_STATUS bit if the boost voltage does not rise above the

UVP threshold before the timer expires. The boost UVP voltage is calculated with 公式 10:

»

…

ÿ

»

…

ÿ

»

…

ÿ

Ÿ

⁄

1

V_{BOOST_UVP}

=

((I

ì R_FB3) + V_UVP) ì (

)

+ I

ì R_FB1+ (I_{SEL_MAX}ì R_FB3)+ V_UVP

Ÿ

_{SEL_MAX}Ÿ

SEL_MAX

R_FB2

……

Ÿ

⁄

Ÿ

⁄

where

•

V_UVP= 0.886 V

I_{SEL_MAX}= 38.7 µA

(10)

8.3.2.2 Boost Sync and Spread Spectrum

The boost controller can be clocked by an external BST_SYNC signal. If the external synchronization clock

disappears the boost continues operation at the frequency defined by RBST_FSET resistor. If the external sync

clock disappears while the SYNC pin level is low the boost continues operation without spread spectrum. If the

external sync clock disappears, and BST_SYNC pin remains high the boost initially stops switching for

approximately 256 μs and then begins switching with spread spectrum enabled.

If using the external BST_SYNC input, the external frequency must be between 1.2 and 1.5 times higher than the

frequency defined by the R_{BST_SET}resistor.

The boost converter has also an internal spread spectrum function that reduces EMI noise around the switching

frequency and its harmonic frequencies. The internal spread spectrum function modulates the boost frequency

±3% from the central frequency with a 1.875-kHz modulation frequency. The spread-spectrum function cannot be

used when an external synchronization clock is used.

表 3. Boost Synchronization Mode

BST_SYNC PIN LEVEL

Low (GND)

BOOST CLOCK MODE

Spread spectrum disabled

High (VDDIO)

Spread spectrum enabled

300-kHz to 2200-kHz clock frequency

Spread spectrum disabled, external synchronization mode

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8.3.2.3 Boost Output Discharge

When the boost is disabled, the discharge pin typically sinks 30-mA current in order to discharge the boost

output voltage. The boost voltage discharge time depends on output capacitance. The discharge function is

enabled for a maximum of 400 ms or until the output voltage falls below 3.3 V. The discharge state is entered

when the EN pin goes low. If VDD falls below the power-on reset (POR) level, the LP8863-Q1 device exits the

discharge state early and immediately enters the shutdown state. If the discharge feature is unused, leave the

DISCHARGE pin floating.

8.3.3 2X Charge Pump

An integrated 2X charge pump can be used to supply the gate drive for the external FET of the boost controller.

The charge pump is enabled or disabled by automatically detecting the presence of the external C_2Xcapacitor. If

V_DDis < 4.5 V then use the charge pump to generate a high-enough gate voltage to drive the external boost

switching FET. To use the charge pump, a 2.2-µF cap is placed between C1N and C1P. If the charge pump is

not required, C1N and C1P must be left unconnected and CPUMP pins tied to VDD. A 10-µF C_PUMPcapacitor is

used to store energy for the gate driver. The C_PUMPcapacitor is required to be used in both charge pump

enabled and disabled conditions and must be placed as close as possible to the CPUMP pins. 图 14 and 图 15

show required connections for both use cases.

D1

L1

R_ISENSE

Q2

V_IN

R_SD

C_IN

C_OUT

C_PUMP

CPUMP

Q1

GD

R_FB1

R_FB2

GD

ISNS

C1N

R_SENSE

PGND

C_2X

PGND

LP8863-Q1

ISNSGND

C1P

VDD

C_VDD

FB

图 14. Charge Pump Enabled Circuit

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D

1

R_ISENSE

L1

Q2

V_IN

R_SD

C_IN

C_OUT

C_PUMP

CPUMP

Q1

GD

R_FB1

R_FB2

GD

ISNS

C1N

R_SENSE

PGND

LP8863-Q1

ISNSGND

C1P

VDD

C_VDD

FB

图 15. Charge Pump Disabled Circuit

The C2X_STAT status bit shows whether a C_2Xcapacitor was detected. The C2X_INT bit shows status of any

charge pump faults and generates a INT signal. The C2X_INT bit can be used to prevent the charge-pump fault

from causing an interrupt on the INT pin signal.

8.3.4 1.8-V LDO

The internal LDO regulator converts the input voltage at VDD to a 1.8-V output voltage at VLDO pin. The LDO

regulator supplies internal circuitry. Bypass LDO with a ceramic capacitor of at least 4.7-µF capacitance to

ground. Place capacitor as close as possible to the VLDO pin.

8.3.5 LED Current Sinks

8.3.5.1 LED Output Current Setting

The maximum output LED current is set by an external resistor value. The LEDx_CURRENT[11:0] registers can

also be used to individually adjust each string’s current down from this maximum. The default value for all the

LEDx_CURRENT[11:0] registers is the maximum (4095). 公式 11 is used to calculate the current setting of an

individual string:

1.21V

R_ISET

LEDx _CURRENT[11: 0]

4095

ILEDx =

ì2560ì

(11)

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LED0 Current Sink

LED0

LATCH

DIN

LED0_DAC

LED0_CURRENT[11:0]

DOUT

EXTERNAL

CURRENT

SETTING

ISET

RISET

LATCH

DIN

LED1_DAC

LED2_DAC

LED3_DAC

LED4_DAC

LED5_DAC

LED1 Current Sink

LED2 Current Sink

LED3 Current Sink

LED4 Current Sink

LED5 Current Sink

LED1

LED2

LED3

LED4

LED5

LED1_CURRENT[11:0]

LED2_CURRENT[11:0]

LED3_CURRENT[11:0]

LED4_CURRENT[11:0]

LED5_CURRENT[11:0]

DOUT

LATCH

DIN

LATCH

DIN

LATCH

DIN

LATCH

DIN

LOAD_BRT

图 16. LED Driver Current Setting Circuit

The LEDx_CURRENT[11:0] registers updates are also latched by the LOAD_BRT_DB register similar to the

individual brightness registers. This is done so all LED currents can be updated simultaneously. The default

value for all the LEDx_CURRENT[11:0] registers is FFFh.

8.3.5.2 LED Output PWM Clock Generation

The LED PWM frequency is asynchronous from the input PWM frequency. The LED PWM frequency is

generated from the internal 20-MHz oscillator and can be set to eight discrete frequencies from 152 Hz to 19.531

kHz. The PWM dimming resolution is highest when the lowest PWM frequency is used. The PWM_FSET resistor

determines the LED PWM frequency based on 表 4. PWM resolution in 表 4 is with PWM dither disabled.

表 4. LED PWM Frequency Selection

R_PWM_FSET (kΩ)

LED PWM FREQUENCY (Hz)

PWM DIMMING RESOLUTION (bits)

3.92

4.75

5.76

7.87

11

152

305

16 (maximum)

16

15

14

13

12

11

10

610

1221

2441

4883

9766

19 531

17.8

42.2

140

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8.3.5.3 LED Output String Configuration

The six LED driver channels of the LP8863-Q1 device can automatically support applications using six, five, four,

three, and two LED strings. The driver channels can also be tied together in groups of two, three, or six

channels. This allows the LP8863-Q1 device to drive three 300-mA LED strings, two 450-mA LED strings, or one

900-mA LED string. The LED strings are always appropriately phase shifted for their string configuration. This

reduces the ripple seen at the boost output, which allows smaller output capacitors and reduces audible ringing

in the capacitors. Phase shift increases the load frequency, which can move potential capacitor noise above the

audible band while still keeping PWM frequency low to support a higher dimming ratio.

When the LP8863-Q1 device is first powered on the string configuration is automatically detected and the phases

of each channel configured. The LED string configuration must not be changed unless the LP8863-Q1 is

powered off in shutdown state. The string configurations in 表 5 are valid configurations for auto detection. Any

other detected configuration defaults to 6 channel / 60 degree mode. The detected string configuration can be

read from the LED_STRING_CONF[2:0] register. Tie unused LEDx pins to ground.

表 5. LED Output String Configuration

AUTOMATIC

PHASE SHIFT

CONFIGURATION

LED0

LED1

LED2

LED3

LED4

LED5

6 channels

5 channels

4 channels

3 channels

2 channels

150 mA

60°

72°

(Tied to GND)

150 mA

(Tied to GND)

90°

150 mA

(Tied to GND) (Tied to GND)

120°

180°

(Tied to GND)

3 channels, 300 mA

/channel

300 mA

120°

(tie LED pins together)

2 channels, 450 mA

/channel

450 mA

180°

(tie LED pins together)

1 channel, 900 mA

(tied LED pins together)

900 mA

None

8.3.5.3.1 Independent Cluster Brightness Control Mode

The LP8863-Q1 supports a cluster mode like that found in the LP8860-Q1 LED driver. This mode allows the

brightness of each of the six driver channels to be controlled independently using the I2C or SPI interface. This is

done by using the six CLUSTER_BRTx[15:0] registers, the six LEDx_GROUP registers and the

LED_EXT_SUPPLY[5:0] register.

The LEDx_GROUP registers select which CLUSTER_BRTx or DISP_BRT register is used for each of the six

LED driver channels. The LED_EXT_SUPPLY[5:0] register selects which channels are used by the adaptive

boost voltage control loop. This allows the LP8863-Q1 to drive LED strings that powered with either the

integrated boost controller or external supply. If a LED driver channel is driving a string powered from the boost

then its corresponding LED_EXT_SUPPLY bit should be set to zero. By default all LED_EXT_SUPPLY bits are

0, and all LEDx_GROUP bits are 000.

An example of how the registers would be configured if the application calls for a display backlight with 4 strings

and uses the remaining 2 current sinks to drive indicator LEDs where anodes are supplied externally (not from

the boost of the LP8863-Q1 device) follows:

LED_EXT_SUPPLY[5:0] = 11000b

LED0_GROUP = 000b

LED1_GROUP = 000b

LED2_GROUP = 000b

LED3_GROUP = 000b

LED4_GROUP = 100b

LED5_GROUP = 101b

(LED5 and LED4 use external supply )

(LED0 uses DISP_BRT register)

(LED1 uses DISP_BRT register)

(LED2 uses DISP_BRT register)

(LED3 uses DISP_BRT register)

(LED4 uses CLUSTER_BRT4 register)

(LED5 uses CLUSTER_BRT5 register)

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8.3.6 Brightness Control

The LP8863-Q1 supports global or individual brightness control for each LED string through individual PWM duty

cycle control of the LED0 to LED5 driver channels via I2C/SPI registers. An internal 20-MHz clock is used for

generating PWM outputs.

8.3.6.1 Brightness Control Signal Path

One display brightness path and five individual brightness paths can be used to control the LED driver channel

brightness. The LEDx_GROUP registers select whether the display brightness path or the cluster 1 to 5

brightness paths control each LED output. The BRT_MODE register selects whether the input to the display

brightness path is the PWM input pin or DISP_BRT register. The brightness control signal path diagram is shown

in 图 17.

The display brightness path has sloper and hybrid dimming functions that can be enabled. By default the sloper

function is enabled and hybrid dimming function disabled. Both functions can be controlled using the I2C or SPI

interface. The sloper function is described in Sloper and hybrid dimming is described in Hybrid Dimming.

By default the LP8863-Q1 operates with LED0 to LED5 channels controlled by the display brightness path. To

enable individual LED string brightness control the LEDx_GROUP registers must be reconfigured with the

SPI/I2C interface.

图 17. LP8863-Q1 Brightness Path Diagram

8.3.6.2 Hybrid Dimming

In addition to pure PWM dimming, LP8863-Q1 supports a hybrid-dimming mode. Hybrid dimming combines PWM

and current modes for brightness control for the display brightness path. In hybrid mode PWM dimming is used

for the low range of brightness, and current dimming is used for high brightness levels as shown in 图 18.

Current dimming control enables improved optical efficiency due to increased LED efficiency at lower currents.

PWM dimming control at low brightness levels ensures linear and accurate control.

Hybrid mode can be enabled with the DIMMING_MODE bit in USER_CONFIG1 register. The PWM and current

modes transition threshold can be set at 12.5% or at 0% brightness with the DIMMING_MODE bits. The latter

selection allows for pure current dimming control mode.

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图 18. 12.5% PWM and Current Hybrid Dimming Diagram

8.3.6.3 Sloper

An optional sloper function makes the transition from one brightness value to another optically smooth. By default

the advanced sloper is enabled with a 200-ms linear sloper duration. Transition time between two brightness

values is programmed with the SLOPE_SELECT[2:0] bits (when 000, sloper is disabled). With advanced sloper

enabled the brightness changes are further smoothed to be more pleasing to the human eye. Advanced slope is

enabled with ADV_SLOPE_ENABLE register bit.

Brightness

Sloper Input

Time

Brightness

Sloper Output

Advanced Slope

Linear Slope

Slope Time

Time

图 19. Brightness Sloper

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8.3.6.4 Dither

The number of brightness steps when using LED output PWM dimming is equal to the 20-MHz oscillator

frequency divided by the LED PWM frequency (set by PWM FSET resistor). The PWM duty cycle dither is a

function the LP8863-Q1 uses to increase the number of brightness dimming steps beyond this oscillator clock

limitation. The dither function modulates the LED driver output duty cycle over time to create more possible

average brightness levels. The DITHER_SELECT[2:0] register bits control the level of dither, disabled, 1, 2, or up

to 5 bits using the I2C or SPI interface. By default the dither has 3 bits enabled (default 011b).

When the 1-bit dither is selected, the width of every second PWM pulse is increased by one LSB (one 20-MHz

clock period). When the 3-bit dither is selected, within a sequence of 8 PWM periods the number of pulses with

increased length varies: dither value 000 - all 8 pulses at default length; 001 - one of the 8 pulses is longer; 010 -

two of the 8 pulses are longer, etc., until at 111 seven of the 8 pulses have increased length. 图 20 shows one

example of PWM output dither.

50.003%

100 Hz

Input PWM

1.2 kHz LED

PWM

Without Dither

50%

1.2 kHz LED

PWM

50.006%

50%

With 2bit Dither

图 20. PWM Dither Example

The dither block also has an additional mode at low brightness levels when LED PWM duty cycle is less than the

minimum pulse width (that is, less than the LED driver rise time). In this mode the dither block skips full PWM

pulses to reduce the brightness further enabling very high dimming modes. The end result is the LED PWM

frequency is reduced as more and more minimum pulses are skipped or dithered out. This function can be

enabled using the I2C or SPI interface by programming the EN_MIN_PWM_LIMIT bit to 1. 图 21 shows how the

2-bit minimum brightness dithering works.

100 Hz

Input PWM

300 ns = 0.003%

200 ns

No

Pulse

200 ns

No

Pulse

305 Hz LED PWM

With Minimum Pulse

Dither

3.2 ms

Average Brightness = 0.003%

图 21. Minimum Brightness Dither Example

8.3.7 Die Temperature Read-Out and Thermal Window Detector

The LP8863-Q1 has two internal thermal sensors: one for protection purposes (device thermal shutdown) and

one for die temperature monitoring. The die temperature monitor block includes a 9-bit ADC to convert the

analog thermal-sensor output to a temperature reading available in the register JUNCTION_TEMPERATURE.

First temperature result is available 2 ms after the activation of the block and conversion rate is 10 Hz. When the

temperature monitor block is disabled register JUNCTION_TEMPERATURE content is –256°C.

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The die temperature monitor also includes a thermal window detector. The TEMPERATURE_LIMIT_HIGH and

TEMPERATURE_LIMIT_LOW bits set the high and low limits for the thermal window. These thresholds have

±1°C hysteresis: TEMPERATURE _LIMIT_HIGH + 1°C for increasing and TEMPERATURE_LIMIT_HIGH – 1°C

for decreasing, for example. If the die temperature increases above the high limit or reduces below the low limit,

a fault interrupt is generated. Die temperature monitor (ADC, thermal sensor, and window detector) can be

disabled to minimize power dissipation in STANDBY mode. The thermal sensor for TSD is always active.

TSD_STATUS

TSD Thermal Sensor

INT

Interrupts

INT

Temperature Monitor

Window Detector

TEMPHIGH_STATUS

TEMPLOW_STATUS

TEMPERATURE_LIMIT_HIGH

TEMPERATURE_LIMIT_LOW

Thermal Sensor

I2C/SPI

JUNCTION_TEMPERATURE

TEMP_MON_EN

ADC

图 22. Thermal Shutdown and Sensor Block Diagram

图 23, 图 24, and 图 25 show the INT pin and status behaviors of the TSD, temperature high, and temperature

low limits.

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Enters Standby Mode

TTSD Thermal Shutdown

Returns to Normal Mode

TTSD_H hysteresis

TEMPERATURE_LIMIT_HIGH

TEMPERATURE_LIMIT_LOW

Host clears INT Status

TEMP_MON_EN

INT

TEMPHIGH_STATUS

TEMPLOW_STATUS

TSD_STATUS

图 23. Thermal Shutdown and Sensor Example 1

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T_TSDThermal Shutdown

TTSD_H hysteresis

TEMPERATURE_LIMIT_HIGH

TEMPERATURE_LIMIT_LOW

Host clears INT Status

TEMP_MON_EN

INT

TEMPHIGH_STATUS

TEMPLOW_STATUS

TSD_STATUS

图 24. Thermal Shutdown and Sensor Example 2

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TTSD Thermal Shutdown

TTSD_H hysteresis

TEMPERATURE_LIMIT_HIGH

TEMPERATURE_LIMIT_LOW

Host clears INT Status

TEMP_MON_EN

INT

TEMPHIGH_STATUS

TEMPLOW_STATUS

TSD_STATUS

图 25. Thermal Shutdown and Sensor Example 3

8.3.8 Protection and Fault Detections

The LP8863-Q1 device includes fault detections for LED open and short conditions, boost input undervoltage,

overvoltage and overcurrent, boost output overvoltage and overcurrent, VDD undervoltage and die

overtemperature. Host can monitor the status of the faults in INTERRUPT_STATUS_1 and

INTERRUPT_STATUS_2 registers.

8.3.8.1 LED Faults

During normal boost operation, boost voltage is raised if any of the LED outputs falls below the low headroom

threshold level. Open LED fault is detected if boost output voltage has reached the maximum and at least one

LED output is still below the threshold. The open string is then disconnected from the boost adaptive control loop

and its output is disabled. Any LED fault sets the status bit LED_STATUS and an interrupt is generated unless

LED interrupt is disabled. Reason for the open LED faults can be read from bits OPEN_LED and LEDx_FAULT

(x = 0...5, indicating the faulty LED) in INTERRUPT_STATUS_2 register. These bits maintain their value until

device power-down while the LED_STATUS bit is cleared by the interrupt clearing procedure. If a new LED fault

is detected, LED_STATUS is set and an interrupt generated again.

Shorted LED fault is detected if one or more LED outputs are above the SHORTED_LED_THRESHOLD setting

and at least one LED output is inside the normal operation widow (see 图 26). Shorted string is disconnected

from the boost adaptive control loop and the LED PWM output is disabled. LED_STATUS status bit is set and an

interrupt generated similarly as in open LED case. Shorted LED fault reason can be read from bits SHORT_LED

and LEDx_FAULT (x = 0...5, indicating the faulty LED) in INTERRUPT_STATUS_2 register.

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图 26. LED Open and Short Detection Logic

8.3.8.2 Boost Faults

Boost overvoltage is detected if the FB pin voltage exceeds the V_OVPLthreshold. When boost overvoltage is

detected, BSTOVPL_STATUS bit is set in the INTERRUPT_STATUS_1 register. The boost FET stops switching,

and the output voltage is automatically limited. If the BSTOVPL_STATUS bit is continually set (that is, reappears

after clearing), it may indicate an issue in the application. Boost overvoltage low is monitored during device

normal operation (ACTIVE mode).

A second boost overvoltage high fault is detected if the FB pin voltage exceeds the V_OVPHthreshold. The

LP8863-Q1 device enters the fault recovery state to protect against excessive thermal dissipation caused by high

headroom on the LED drivers. When boost overvoltage is detected, BSTOVPH_STATUS bit is set in the

INTERRUPT_STATUS_1 register. A fault interrupt is also generated. If the BSTOVPH_STATUS bit is continually

set (that is, reappears after clearing), it may indicate an issue in the application. Boost overvoltage high is

monitored during device normal operation (ACTIVE mode).

Boost overcurrent is detected if the FB pin voltage drops below the V_UVPthreshold. A boost OCP fault is detected

if the undervoltage condition persists for longer than 110 ms. If the boost overcurrent timer expires before the

output voltage recovers, the BSTOCP_STATUS bit is set in the INTERRUPT_STATUS_1 register. The fault

recovery state is entered, and a fault interrupt is generated. If the BSTOCP_STATUS bit is permanently set, it

may indicate an issue in the application. Boost overcurrent is monitored from the boost start, and fault may

trigger during boost start-up.

8.3.8.3 Power-Line Faults

If during operation of the LP8863-Q1 device the V_IN(VSENSE_P pin) voltage falls below the VINUVLO falling

level, the boost, LED outputs, and power-line FET are turned off, and the device enters STANDBY mode. The

VINUVLO_STATUS bit is also set, and the INT pin is triggered. When the VINUVLO voltage rises above the

rising threshold level the LP8863-Q1 device exits STANDBY and begins the start-up sequence.

If during LP8863-Q1 device operation V_IN(VSENSE_P pin) voltage rises above the VINOVP rising level, boost,

LED outputs, and power-line FET are turned off, and the device enters STANDBY mode. The VINOVP_STATUS

bit is also set, and the INT pin is triggered. When the VINOVP voltage falls below the falling threshold level the

LP8863-Q1 exits STANDBY and begins the start-up sequence.

The VIN OCP protection detects overcurrent by measuring voltage of the R_ISENSEresistor connected between

VSENSE_P and VSENSE_N pins. VIN OCP sensing begins once the LP8863-Q1 enters the PL FET soft-start

state. Fault is detected if overcurrent condition duration lasts for at least 10 μs, minimum. The VINOCP_STATUS

bit is also set, and the INT pin is triggered. To trip at a lower current limit a larger sense resistor can be used to

create a 220-mV voltage difference across the sense resistor.

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8.3.8.4 VDD Undervoltage Fault

If during LP8863-Q1 device operation VDD falls below VDDUVLO falling level, boost, PL FET, and LED outputs

are turned off, and the device enters STANDBY mode. The VDDUVLO_STATUS fault bit is set, and the INT pin

is triggered. The LP8863-Q1 recovers automatically to ACTIVE mode when VDD rises above VDDUVLO rising

threshold.

If VDD falls below VPOR the LP8863-Q1 device enters SHUTDOWN mode.

8.3.8.5 Thermal Shutdown

If the die temperature of LP8863-Q1 reaches the thermal shutdown threshold T_TSD, the boost, PL FET, and LED

outputs on LP8863-Q1 device shut down to protect the device from damage. Fault status bit TSD_STATUS bit is

set, and the INT pin is triggered. The device restarts the PL FET, the boost, and LED outputs when temperature

drops by T_{TSD_H}amount.

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8.4 Device Functional Modes

8.4.1 State Diagram

From Any State

VDD < POR

SHUTDOWN

VDD > POR

DEVICE INIT

STANDBY

EN=1

PL FET

SOFTSTART

FAULT RECOVERY

200 ms and

PL_PRECHARGE_READY

50 ms and

PL_PRECHARGE_COMPLETE

BOOST STARTUP

50 ms and

BOOST_OK=0

50 ms and

BOOST_OK=1

FAULT

NORMAL

LATCH FAULT

All LED channels have been

disabled due to open or short faults.

EN=0

DISCHARGE_DONE and

EN=0

DISCHARGE

图 27. State Machine Diagram

8.4.2 Shutdown

When VDD is below POR threshold device is in shutdown state.

8.4.3 Device Initialization

After POR is released device initialization begins. During this state the LDO is started up, EEPROM default and

trim configurations are loaded, BOOST_FSET and PWM_FSET resistors are detected, and the LED string

configuration is detected.

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Device Functional Modes (接下页)

8.4.4 Standby Mode

In standby the LP8863-Q1 device can be accessed with I2C or SPI to change any configuration registers. Analog

blocks are disabled to save power.

8.4.5 Power-line FET Soft Start

Power-line FET is enabled, and boost input and output capacitors are charged to V_INlevel. V_INfaults for OCP,

OVP, and UVP are enabled.

8.4.6 Boost Start-Up

Boost voltage is ramped to maximum voltage level with reduced current limit. Start-up exits when boost reaches

initial target voltage. All boost faults are now enabled.

8.4.7 Normal Mode

LED drivers are enabled when brightness is greater than zero. All LED faults are active.

8.4.8 Discharge Mode

When EN goes low from normal mode the boost output voltage is discharged. This state exits when boost

voltage falls below 3.3 V or when the 400-ms timer expires.

8.4.9 Fault Recovery

Non-LED faults can trigger fault recover state. LED drivers, boost converter, and power-line FET are disabled for

200 ms, and the device attempts to restart from standby mode if EN is still high.

8.4.10 Latch Fault

If all LED strings are disabled due to faults then the LP8863-Q1 enters the latch fault mode. This state can be

exited by toggling the VDD pin.

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Device Functional Modes (接下页)

8.4.11 Start-Up Sequence

DEVICE

INIT

PL FET

PRECHARGE

BOOST

SOFTSTART

STATE

VIN

SHUTDOWN

STANDBY

NORMAL

VDD

VDDIO

EN

PWM

Input Pin

VINIT

VADAPT

Boost VOUT

VIN

50 ms

LEDx

图 28. Start-Up Sequence Diagram

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Device Functional Modes (接下页)

8.4.12 Shutdown Sequence

STATE

VIN

NORMAL

DISCHARGE

SHUTDOWN

VDD

VDDIO

EN

PWM Input

Boost

VOUT

3.3 V

0 V

LEDx

< 400 ms

图 29. Shutdown Sequence Diagram

For proper operation of discharge function, pull the EN pin before VDD pin. VIN and VDDIO can be set low any

time after EN low.

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8.5 Programming

8.5.1 Serial Interface Selection

The serial interface type is selected by connecting the IFSEL pin to VDDIO or GND. The LP8863-Q1 device

checks the IFSEL pin state as part of device startup. Device start-up occurs after VDD and VDDIO POR levels

are reached. 表 6 shows how to connect the IFSEL pin to select between the SPI and I2C-compatible interfaces.

表 6. Serial Control Interface Selection

PIN NAME

SS_ADDRSEL

SCLK_SCL

SDI_SDA

IFSEL PIN = VDDIO

IFSEL PIN = GND

ADDRSEL

SCL

SS

SCLK

SDI

SDA

SDO_PWM

PWM

SDO

8.5.2 SPI Interface

In SPI mode host can address as many unique LP8863-Q1 devices as there are slave select pins on host. The

complete 10-bit register space in LP8863-Q1 device can be accessed using SPI interface.

The LP8863-Q1 device is compatible with SPI serial-bus specification and operates as a slave device. The

transmission consists of 32-bit write and read cycles. One cycle consists of a 15-bit register address (10 bits

used), 1 read/write (R/W) bit and 16-bit data to maintain compatibility with 16-bit SPI.

The R/W bit high state defines a write cycle and low defines a read cycle. The SDO output is normally in a high-

impedance state. When the slave-select pin SS for the device is active (that is, low) the SDO output is pulled

low. During write cycle SDO stays in high-impedance state. The address and data bits are transmitted MSB first.

The slave-select signal SS must be low during the cycle transmission. SS resets the interface when high, and it

has to be taken high between successive cycles, except when using auto- increment mode. Data is clocked in on

the rising edge of the SCLK clock signal, while data is clocked out on the falling edge of SCLK.

图 30. SPI Write

图 31. SPI Read

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8.5.3 I2C-Compatible Interface

Two LP8863-Q1 slave devices may share the same I2C bus. The SS_ADDRSEL pin selects between the two

possible base slave addresses.

表 7. I2C Address Selection

SS_ADDRSEL PIN

GND

7-BIT I2C BASE SLAVE ADDRESS

0x2C

0x3C

VDDIO

The LP8863-Q1 uses a 10-bit register address space. The 10-bit register address space is accessed as four

separate 8-bit address spaces. Four different slave addresses are used to access each of the four 8-bit address

register spaces.

表 8. I2C Address Registers Selection

SS_ADDRSEL PIN

7-BIT BASE ADDRESS

7-BIT SLAVE ADDRESS

ACCESSIBLE 10-BIT REGISTERS

0x000 to 0x0FF

0x2C

0x2D

0x2E

0x2F

0x3C

0x3D

0x3E

0x3F

0x100 to 0x1FF

GND

0x2C

0x200 to 0x2FF

0x300 to 0x3FF

0x000 to 0x0FF

0x100 to 0x1FF

VDDIO

0x3C

0x200 to 0x2FF

0x300 to 0x3FF

Write I2C transactions are made up of 4 bytes. The first byte includes the 7-bit slave address and Write bit. The

7-bit slave address selects the LP8863-Q1 slave device and one of four 8-bit register address sections. The

second byte includes eight LSB bits of the 10-bit register address. The last two bytes are the 16-bit register

value.

Read I2C transactions are made up of five bytes. The first byte includes the 7-bit slave address and Write bit.

The 7-bit slave address selects the LP8863-Q1 slave device and one of four 8-bit register address sections. The

second byte includes eight LSB bits of the 10-bit register address. The third byte includes the 7-bit slave address

and Read bit. The last two bytes are the 16-bit register value returned from the slave.

图 32. I2C Write

图 33. I2C Read

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8.5.4 Programming Examples

8.5.4.1 General Configuration Registers

The LP8863-Q1 does not require any serial interface configuration. It can be simply controlled with the EN pin

and PWM pin. Most of the device configuration is accomplished using external resistor values or automatic

detection. If a serial interface is available then extended configuration is possible. The configuration registers can

be written in standby state as shown in 表 9.

表 9. Configuration Registers

REGISTER NAME

BRT_MODE

FUNCTION

Selects PWM pin or DISPLAY_BRT register for brightness control.

Selects voltage level for shorted LED Fault.

SHORTED_LED_THRESHOLD

DITHER_SELECT

Selects up to 3 bits of PWM dither for added dimming resolution.

Enables 200-ns PWM pulse limit and frequency dither to reach lower minimum brightness

levels.

EN_MIN_PWM_LIMIT

SLOPE_SELECT

Selects duration for linear brightness sloper.

ADV_SLOPE_ENABLE

DIMMING_MODE

Enables advance sloper S-shape smoothing function.

Select between PWM, hybrid or current LED ouput dimming types.

Enables temperature window monitor function.

TEMP_MON_EN

TEMPERATURE_LIMIT_HIGH

TEMPERATURE_LIMIT_LOW

Sets HIGH threshold level for temperature window function.

Sets LOW threshold level for temperature window function.

8.5.4.2 Clearing Fault Interrupts

The LP8863-Q1 has an INT pin to alert the host when a fault occurs. If a serial interface is available, the Interrupt

Fault Status registers can be read back to learn which fault(s) have been detected. These status bits are located

in the INTERRUPT_STATUS_1, INTERRUPT_STATUS_2, and INTERRUPT_STATUS_3 registers. Each

interrupt status has a STATUS bit and a CLEAR bit. If a fault interrupt has been detected, a 1 is read back from

its STATUS bit. To clear a fault interrupt status a 1 must be written to both the STATUS bit and CLEAR bit at the

same time.

8.5.4.3 Disabling Fault Interrupts

By default most of the LP8863-Q1 faults trigger the INT pin. Each fault has two INT_EN bits. These bits are

located in the INTERRUPT_ENABLE_1, INTERRUPT_ENABLE_2, and INTERRUPT_ENABLE_3 registers. If the

INT_EN bit is read and returns a 1, the INT pin is triggered when that fault occurs. The fault interrupt can be

disabled by writing 01 to its INT_EN bits, or it can be enabled by writing 11 to its INT_EN bits. There is also a

GLOBAL fault interrupt that can be disabled to prevent any faults from triggering the INT pin.

8.5.4.4 Diagnostic Registers

The LP8863-Q1 contains several diagnostic registers than can be read with the serial interface for debugging or

additional device information. 表 10 is a summary of the available registers.

表 10. Diagnostic Registers

REGISTER NAME

JUNCTION_TEMPERATURE

FUNCTION

9-bit die junction temperature in 2s complement form — 1°C per LSB

Current state of the functional state machine

FSM_LIVE_STATUS

PWM_INPUT_STATUS

LED_PWM_STATUS

LED_CURRENT_STATUS

Measured 6-bit duty cycle of the PWM pin input

16-bit LED0 PWM duty cycle from state machine

12-bit LED0 current DAC value from state machine

10-bit value for adaptive boost voltage target — value is linear between

VBOOST_MIN and VBOOST_MAX calculations

VBOOST_STATUS

AUTO_PWM_FREQ_SEL

AUTO_BOOST_FREQ_SEL

AUTO_LED_STRING_CFG

LED PWM frequency value from PWM_FSET detection

Boost switching frequency value from PWM_FSET detection

LED string phase configuration detected from LED pin configuration

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8.5.4.5 Cluster Mode Configuration and Control Registers

The LP8863-Q1 device supports a cluster mode where the duty cycles and LED current of the six LED current

drivers can be controlled independently. This mode can also select which LED current driver’s headroom levels

are used by the adaptive boost voltage control loop. If the anode of an LED string is supplied by an external

supply and not the integrated boost controller then its LED_EXT_SUPPLY bit is set to 1. The cluster mode

configuration registers are summarized in 表 11. More details can be found in Register Maps.

表 11. Cluster Mode Configuration Registers

REGISTER NAME

FUNCTION

LED0_GROUP...LED5_GROUP

Selects which of the five CLUSTERx_BRT or DISPLAY_BRT registers control each

LED current driver.

CLUSTER1_BRT…CLUSTER5_BRT

LED0_CURRENT…LED5_CURRENT

LOAD_BRT_DB

Five 16-bit brightness values that can be used in addition to the DISPLAY_BRT

register.

Six 12-bit current registers allow LED current to be independently scaled from

maximum level for LED current driver.

Load BRT bit is written to 1 in order to update the CLUSTERx_BRT and

LEDx_CURRENT registers at the same time.

LED_EXT_SUPPLY

Six bits to select which LED current driver is powered from an external supply and not

the boost converter.

LED0_SHORT_DISABLE…

LED5_SHORT_DISABLE

Six bits to individually disable LED short detection for each LED current driver. Used if

LED current value is set to lower value than other strings.

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8.6 Register Maps

8.6.1 FullMap Registers

Table 12 lists the memory-mapped registers for the FullMap registers. All register offset addresses not listed in

Table 12 should be considered as reserved locations and the register contents should not be modified.

Table 12. FULLMAP Registers

Offset

20h

Acronym

Register Name

Section

Go

BL_MODE

Brightness Mode

28h

DISP_BRT

Display Brightness

30h

GROUPING1

Brightness Grouping 1

Brightness Grouping 2

User Config 1

32h

GROUPING2

40h

USER_CONFIG1

42h

USER_CONFIG2

User Config 2

4Eh

INTERRUPT_ENABLE_3

INTERRUPT_ENABLE_1

INTERRUPT_ENABLE_2

INTERRUPT_STATUS_1

INTERRUPT_STATUS_2

INTERRUPT_STATUS_3

JUNCTION_TEMPERATURE

TEMPERATURE_LIMIT_HIGH

TEMPERATURE_LIMIT_LOW

CLUSTER1_BRT

Fault Interrupt Enable 3

Fault Interrupt Enable 1

Fault Interrupt Enable 2

Fault Interrupt Status 1

Fault Interrupt Status 2

Fault Interrupt Status 3

Die Junction Temperature

Temperature High Limit

Temperature Low Limit

Cluster 1 Brightness

Cluster 2 Brightness

Cluster 3 Brightness

Cluster 4 Brightness

Cluster 5 Brightness

Cluster Brightness and Current Load Bit

LED0 Current

50h

52h

54h

56h

58h

E8h

ECh

EEh

13Ch

148h

154h

160h

16Ch

178h

1C2h

1C4h

1C6h

1C8h

1CAh

1CCh

288h

28Ah

2A4h

2A6h

2A8h

2AAh

2ACh

2AEh

CLUSTER2_BRT

CLUSTER3_BRT

CLUSTER4_BRT

CLUSTER5_BRT

BRT_DB_CONTROL

LED0_CURRENT

LED1_CURRENT

LED1 Current

LED2_CURRENT

LED2 Current

LED3_CURRENT

LED3 Current

LED4_CURRENT

LED4 Current

LED5_CURRENT

LED5 Current

BOOST_CONTROL

SHORT_THRESH

Boost Control

Shorted LED Threshold

Device State Diagnostics

PWM Input Diagnostics

PWM Output Diagnostics

LED Current Diagnostics

Adaptive Boost Diagnostics

Auto Detect Diagnstics

FSM_DIAGNOSTICS

PWM_INPUT_DIAGNOSTICS

PWM_OUTPUT_DIAGNOSTICS

LED_CURR_DIAGNOSTICS

ADAPT_BOOST_DIAGNOSTICS

AUTO_DETECT_DIAGNOSTICS

Complex bit access types are encoded to fit into small table cells. Table 13 shows the codes that are used for

access types in this section.

Table 13. FullMap Access Type Codes

Access Type

Read Type

R

Code

Description

R

Read

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Table 13. FullMap Access Type Codes (continued)

Access Type

Write Type

W

Code

Description

W

Write

Reset or Default Value

-n

Value after reset or the default

value

8.6.1.1 BL_MODE Register (Offset = 20h) [reset = 300h]

BL_MODE is shown in Figure 34 and described in Table 14.

Return to Summary Table.

Figure 34. BL_MODE Register

15

7

14

6

13

5

12

4

11

10

2

9

1

8

0

RESERVED

R/W-C0h

3

RESERVED

R/W-C0h

brightness_mode

R/W-0h

Table 14. BL_MODE Register Field Descriptions

Bit

Field

Type

Reset

Description

15-2

1-0

RESERVED

R/W

C0h

These bits are reserved.

brightness_mode

R/W

0h

0h = Brightness controlled by PWM Input

1h = Reserved

2h = Brightness controlled by DISPLAY_BRT Register

3h = Reserved

8.6.1.2 DISP_BRT Register (Offset = 28h) [reset = 0h]

DISP_BRT is shown in Figure 35 and described in Table 15.

Return to Summary Table.

Figure 35. DISP_BRT Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DISPLAY_BRT

R/W-0h

Table 15. DISP_BRT Register Field Descriptions

Bit

15-0

Field

DISPLAY_BRT

Type

Reset

Description

R/W

0h

Display Brightness Register

8.6.1.3 GROUPING1 Register (Offset = 30h) [reset = 0h]

GROUPING1 is shown in Figure 36 and described in Table 16.

Return to Summary Table.

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Figure 36. GROUPING1 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

LED3_GROUP

R/W-0h

LED2_GROUP

R/W-0h

4

3

LED1_GROUP

R/W-0h

LED0_GROUP

R/W-0h

Table 16. GROUPING1 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

11-8

7-4

LED3_GROUP

LED2_GROUP

LED1_GROUP

LED0_GROUP

R/W

0h

LED Output 3 Brightness Control Mapping

0h = DISP_BRT/PWM

1h = CLUSTER1_BRT

2h = CLUSTER3_BRT

3h = CLUSTER3_BRT

4h = CLUSTER4_BRT

5h = CLUSTER5_BRT

R/W

0h

LED Output 2 Brightness Control Mapping

0h = DISP_BRT/PWM

1h = CLUSTER1_BRT

2h = CLUSTER3_BRT

3h = CLUSTER3_BRT

4h = CLUSTER4_BRT

5h = CLUSTER5_BRT

LED Output 1 Brightness Control Mapping

0h = DISP_BRT/PWM

1h = CLUSTER1_BRT

2h = CLUSTER3_BRT

3h = CLUSTER3_BRT

4h = CLUSTER4_BRT

5h = CLUSTER5_BRT

3-0

LED Output 0 Brightness Control Mapping

0h = DISP_BRT/PWM

1h = CLUSTER1_BRT

2h = CLUSTER3_BRT

3h = CLUSTER3_BRT

4h = CLUSTER4_BRT

5h = CLUSTER5_BRT

8.6.1.4 GROUPING2 Register (Offset = 32h) [reset = 0h]

GROUPING2 is shown in Figure 37 and described in Table 17.

Return to Summary Table.

Figure 37. GROUPING2 Register

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

RESERVED

R/W-0h

LED5_GROUP

R/W-0h

LED4_GROUP

R/W-0h

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Table 17. GROUPING2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-8

RESERVED

R/W

0h

These bits are reserved.

7-4

LED5_GROUP

R/W

0h

LED Output 5 Brightness Control Mapping

0h = DISP_BRT/PWM

1h = CLUSTER1_BRT

2h = CLUSTER3_BRT

3h = CLUSTER3_BRT

4h = CLUSTER4_BRT

5h = CLUSTER5_BRT

3-0

LED4_GROUP

R/W

0h

LED Output 4 Brightness Control Mapping

0h = DISP_BRT/PWM

1h = CLUSTER1_BRT

2h = CLUSTER3_BRT

3h = CLUSTER3_BRT

4h = CLUSTER4_BRT

5h = CLUSTER5_BRT

8.6.1.5 USER_CONFIG1 Register (Offset = 40h) [reset = 8B0h]

USER_CONFIG1 is shown in Figure 38 and described in Table 18.

Return to Summary Table.

Figure 38. USER_CONFIG1 Register

15

7

14

13

5

12

11

10

2

9

8

DITHER_SELECT

RESERVED

TEMP_MON_E

N

RESERVED

R/W-0h

R/W-2h

3

R/W-0h

1

R/W-0h

0

6

4

SLOPE_SELECT

ADV_SLOPE_

ENABLE

RESERVED

DIMMING_MODE

R/W-5h

R/W-1h

R/W-0h

Table 18. USER_CONFIG1 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-13

DITHER_SELECT

R/W

0h

0h = Dither Disabled

1h = 1-bit Dither

2h = 2-bit Dither

3h = 3-bit Dither

4h = 4-bit Dither

5h = 5-bit Dither

6h = Unused

7h = Unused

12-10

9

RESERVED

R/W

2h

0h

These bits are reserved.

TEMP_MON_EN

0h = Temperature Monitor Disabled

1h = Temperature Monitor Enabled

8

RESERVED

R/W

0h

This bit is reserved.

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Table 18. USER_CONFIG1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

7-5

SLOPE_SELECT

R/W

5h

0h = 0ms

1h = 1ms

2h = 2ms

3h = 50ms

4h = 100ms

5h = 200ms

6h = 300ms

7h = 500ms Times are for linear slope mode. Advanced sloper will

increase durations while adding additional smoothing to brightness

transitions. 1ms and 2ms sloper times are intended to be used only

in linear mode. 50ms to 500ms sloper durations may be used with or

without advanced sloper function.

4

ADV_SLOPE_ENABLE

R/W

1h

0h = Linear Sloping

1h = Advanced Sloping

3-2

1-0

RESERVED

R/W

0h

These bits are reserved.

DIMMING_MODE

LED Output Dimming Mode

0h = PWM Mode

1h = 12.5% Hybrid Mode

2h = Unused

3h = 12-bit Constant Current Mode

8.6.1.6 USER_CONFIG2 Register (Offset = 42h) [reset = 0h]

USER_CONFIG2 is shown in Figure 39 and described in Table 19.

Return to Summary Table.

Figure 39. USER_CONFIG2 Register

15

14

6

13

5

12

11

10

2

9

1

8

0

EN_MIN_PWM

_LIMIT

RESERVED

R/W-0h

7

R/W-0h

3

4

RESERVED

R/W-0h

Table 19. USER_CONFIG2 Register Field Descriptions

Bit

Field

EN_MIN_PWM_LIMIT

Type

Reset

Description

15

R/W

0h

Allows PWM pulses to be dithered to reduce lower minimum

brightness.

When enabled brightness levels that map to less than 200ns pulse

width will cause pulses to be skipped.

0h = Disabled

1h = Enabled

14-0

RESERVED

R/W

0h

These bits are reserved.

8.6.1.7 INTERRUPT_ENABLE_3 Register (Offset = 4Eh) [reset = 200Ah]

INTERRUPT_ENABLE_3 is shown in Figure 40 and described in Table 20.

Return to Summary Table.

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Figure 40. INTERRUPT_ENABLE_3 Register

15

14

13

VINOCP_INT_EN

R/W-2h

12

11

CPCAP_INT_EN

R/W-0h

10

9

1

8

0

BSTSYNC_INT_EN

R/W-0h

CP_INT_EN

R/W-0h

7

6

5

4

3

2

FSET_INT_EN

R/W-0h

INVSTRING_INT_EN

R/W-0h

VINOVP_INT_EN

R/W-2h

VINUVP_INT_EN

R/W-2h

Table 20. INTERRUPT_ENABLE_3 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-14

13-12

11-10

9-8

BSTSYNC_INT_EN

VINOCP_INT_EN

CPCAP_INT_EN

CP_INT_EN

R/W

0h

Missing Boost Sync Interrupt Enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable Interrupt

3h = Enable Interrupt

R/W

2h

0h

VIN Over-Current Interrupt Enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable Interrupt

3h = Enable Interrupt

Charge Pump Cap Missing Interrupt Enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable Interrupt

3h = Enable Interrupt

Charge Pump Interrupt Enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable Interrupt

3h = Enable Interrupt

7-6

FSET_INT_EN

Missing FSET Resistor Interrupt Enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable Interrupt

3h = Enable Interrupt

5-4

INVSTRING_INT_EN

Invalid LED String Configuration Interrupt Enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable Interrupt

3h = Enable Interrupt

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Table 20. INTERRUPT_ENABLE_3 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3-2

VINOVP_INT_EN

R/W

2h

VIN Over-Voltage Interrupt Enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable Interrupt

3h = Enable Interrupt

1-0

VINUVP_INT_EN

R/W

2h

VIN Under-Voltage Interrupt Enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable Interrupt

3h = Enable Interrupt

8.6.1.8 INTERRUPT_ENABLE_1 Register (Offset = 50h) [reset = A02Ah]

INTERRUPT_ENABLE_1 is shown in Figure 41 and described in Table 21.

Return to Summary Table.

Figure 41. INTERRUPT_ENABLE_1 Register

15

GLOBAL_INT_EN

R/W-2h

14

13

12

11

TEMP_INT_EN

R/W-0h

10

9

1

8

BSTOVPH_INT_EN

R/W-2h

RESERVED

R/W-0h

7

6

5

4

3

2

0

BSTOVPL_INT_EN

R/W-0h

BSTOCP_INT_EN

R/W-2h

VDDUVLO_INT_EN

R/W-2h

TSD_INT_EN

R/W-2h

Table 21. INTERRUPT_ENABLE_1 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-14

13-12

11-10

9-8

GLOBAL_INT_EN

R/W

2h

Global Interrupt Enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable Interrupt

3h = Enable Interrupt

BSTOVPH_INT_EN

TEMP_INT_EN

RESERVED

R/W

2h

0h

Boost OVP High Interrupt Enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable Interrupt

3h = Enable Interrupt

Temperature Interrupt Enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable Interrupt

3h = Enable Interrupt

These bits are reserved.

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Table 21. INTERRUPT_ENABLE_1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

7-6

BSTOVPL_INT_EN

R/W

0h

Boost OVP Low Interrupt Enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable Interrupt

3h = Enable Interrupt

5-4

3-2

1-0

BSTOCP_INT_EN

VDDUVLO_INT_EN

TSD_INT_EN

R/W

2h

Boost Over-Current Interrupt Enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable Interrupt

3h = Enable Interrupt

VDD UVLO Interrupt Enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable Interrupt

3h = Enable Interrupt

Thermal Shutdown Interrupt Enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable Interrupt

3h = Enable Interrupt

8.6.1.9 INTERRUPT_ENABLE_2 Register (Offset = 52h) [reset = 80h]

INTERRUPT_ENABLE_2 is shown in Figure 42 and described in Table 22.

Return to Summary Table.

Figure 42. INTERRUPT_ENABLE_2 Register

15

7

14

6

13

5

12

4

11

3

10

9

1

8

0

RESERVED

R/W-0h

2

LED_INT_EN

R/W-2h

RESERVED

R/W-0h

Table 22. INTERRUPT_ENABLE_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-8

7-6

RESERVED

R/W

0h

These bits are reserved.

LED_INT_EN

R/W

2h

LED Open / Short Interrupt Enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable Interrupt

3h = Enable Interrupt

5-0

RESERVED

R/W

0h

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8.6.1.10 INTERRUPT_STATUS_1 Register (Offset = 54h) [reset = 0h]

INTERRUPT_STATUS_1 is shown in Figure 43 and described in Table 23.

Return to Summary Table.

Figure 43. INTERRUPT_STATUS_1 Register

15

14

13

12

11

10

9

1

8

BSTOVPH_ST BSTOVPH_CL TEMPHIGH_ST TEMPHIGH_CL TEMPLOW_ST TEMPLOW_CL

RESERVED

R/W-0h

ATUS

EAR

ATUS

EAR

ATUS

EAR

R/W-0h

7

6

5

4

3

2

0

BSTOVPL_STA BSTOVPL_CLE BSTOCP_STA BSTOCP_CLE VDDUVLO_ST VDDUVLO_CL TSD_STATUS

TSD_CLEAR

TUS

AR

TUS

AR

ATUS

EAR

R/W-0h

Table 23. INTERRUPT_STATUS_1 Register Field Descriptions

Bit

Field

Type

Reset

Description

15

BSTOVPH_STATUS

R/W

0h

Boost OVP High Status

0h = No Fault

1h = Fault

14

13

BSTOVPH_CLEAR

R/W

0h

Boost OVP High Fault Clear

Write "1" to both Status bit and Clear bit at same time to clear

interrupt register status and interrupt pin status.

TEMPHIGH_STATUS

Temperature High Status

0h = No Fault

1h = Fault

12

11

TEMPHIGH_CLEAR

TEMPLOW_STATUS

R/W

0h

Temperature High Fault Clear

Write "1" to both Status bit and Clear bit at same time to clear

interrupt register status and interrupt pin status.

Temperature Low Status

0h = No Fault

1h = Fault

10

TEMPLOW_CLEAR

R/W

0h

Temperature Low Fault Clear

Write "1" to both Status bit and Clear bit at same time to clear

interrupt register status and interrupt pin status.

9-8

7

RESERVED

R/W

0h

These bits are reserved.

BSTOVPL_STATUS

Boost OVP Low Status

0h = No Fault

1h = Fault

6

5

BSTOVPL_CLEAR

BSTOCP_STATUS

R/W

0h

Boost OVP Low Fault Clear

Write "1" to both Status bit and Clear bit at same time to clear

interrupt register status and interrupt pin status.

Boost Over-Current Status

0h = No Fault

1h = Fault

4

3

BSTOCP_CLEAR

R/W

0h

Boost Over-Current Fault Clear

Write "1" to both Status bit and Clear bit at same time to clear

interrupt register status and interrupt pin status.

VDDUVLO_STATUS

VDD UVLO Status

0h = No Fault

1h = Fault

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Table 23. INTERRUPT_STATUS_1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

2

VDDUVLO_CLEAR

R/W

0h

VDD UVLO Fault Clear

Write "1" to both Status bit and Clear bit at same time to clear

interrupt register status and interrupt pin status.

1

0

TSD_STATUS

TSD_CLEAR

R/W

0h

Thermal Shutdown Status

0h = No Fault

1h = Fault

Thermal Shutdown Fault Clear

Write "1" to both Status bit and Clear bit at same time to clear

interrupt register status and interrupt pin status.

8.6.1.11 INTERRUPT_STATUS_2 Register (Offset = 56h) [reset = 0h]

INTERRUPT_STATUS_2 is shown in Figure 44 and described in Table 24.

Return to Summary Table.

Figure 44. INTERRUPT_STATUS_2 Register

15

14

13

12

11

10

9

8

LED5_FAULT

R/W-0h

LED4_FAULT

R/W-0h

LED3_FAULT

R/W-0h

LED2_FAULT

R/W-0h

LED1_FAULT

R/W-0h

LED0_FAULT

R/W-0h

OPEN_LED

R/W-0h

SHORT_LED

R/W-0h

7

6

5

4

3

2

1

0

LED_STATUS

R/W-0h

LED_CLEAR

R/W-0h

RESERVED

R/W-0h

Table 24. INTERRUPT_STATUS_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15

LED5_FAULT

LED4_FAULT

LED3_FAULT

LED2_FAULT

LED1_FAULT

LED0_FAULT

R/W

0h

LED5 Status

0h = No Fault

1h = Fault

Status is cleared with LED_STATUS bit

14

13

12

11

10

R/W

0h

LED4 Status

0h = No Fault

1h = Fault

Status is cleared with LED_STATUS bit

LED3 Status

0h = No Fault

1h = Fault

Status is cleared with LED_STATUS bit

LED2 Status

0h = No Fault

1h = Fault

Status is cleared with LED_STATUS bit

LED1 Status

0h = No Fault

1h = Fault

Status is cleared with LED_STATUS bit

LED0 Status

0h = No Fault

1h = Fault

Status is cleared with LED_STATUS bit

55

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Table 24. INTERRUPT_STATUS_2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

9

OPEN_LED

R/W

0h

LED Open Status

0h = No Fault

1h = Fault

Status is cleared with LED_STATUS bit

8

7

SHORT_LED

LED_STATUS

R/W

0h

LED Short Status

0h = No Fault

1h = Fault

Status is cleared with LED_STATUS bit

LED Open / Short Fault Status

0h = No Fault

1h = Fault

6

LED_CLEAR

RESERVED

R/W

0h

LED Open / Short Fault Clear

Write "1" to both Status bit and Clear bit at same time to clear

interrupt register status and interrupt pin status.

5-0

These bits are reserved.

8.6.1.12 INTERRUPT_STATUS_3 Register (Offset = 58h) [reset = 0h]

INTERRUPT_STATUS_3 is shown in Figure 45 and described in Table 25.

Return to Summary Table.

Figure 45. INTERRUPT_STATUS_3 Register

15

14

13

12

11

10

9

8

BSTSYNC_ST BSTSYNC_CL VINOCP_STAT VINOCP_CLEA CPCAP_STAT CPCAP_CLEA

CP_STATUS

CP_CLEAR

ATUS

EAR

US

R

US

R

R/W-0h

1

R/W-0h

0

7

6

5

4

3

2

FSET_STATUS FSET_CLEAR INVSTRING_S INVSTRING_C VINOVP_STAT VINOVP_CLEA VINUVP_STAT VINUVP_CLEA

TATUS

LEAR

US

R

US

R

R/W-0h

Table 25. INTERRUPT_STATUS_3 Register Field Descriptions

Bit

Field

Type

Reset

Description

15

BSTSYNC_STATUS

R/W

0h

Missing Boost Sync Fault Status

0h = No Fault

1h = Fault

14

13

BSTSYNC_CLEAR

VINOCP_STATUS

R/W

0h

Missing Boost Sync Fault Clear

Write "1" to both Status bit and Clear bit at same time to clear

interrupt register status and interrupt pin status.

VIN Over-Current Fault Status

0h = No Fault

1h = Fault

12

11

VINOCP_CLEAR

CPCAP_STATUS

R/W

0h

VIN Over-Current Fault Clear

Write "1" to both Status bit and Clear bit at same time to clear

interrupt register status and interrupt pin status.

Missing Charge Pump Capacitor Fault Status

0h = No Fault

1h = Fault

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Table 25. INTERRUPT_STATUS_3 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

10

CPCAP_CLEAR

R/W

0h

Missing Charge Pump Capacitor Fault Clear

Write "1" to both Status bit and Clear bit at same time to clear

interrupt register status and interrupt pin status.

9

CP_STATUS

R/W

0h

Charge Pump Fault Status

0h = No Fault

1h = Fault

8

7

CP_CLEAR

R/W

0h

Charge Pump Fault Fault Clear

Write "1" to both Status bit and Clear bit at same time to clear

interrupt register status and interrupt pin status.

FSET_STATUS

Missing Boost / PWM FSET Resistor Fault Status

0h = No Fault

1h = Fault

6

5

FSET_CLEAR

R/W

0h

Missing Boost / PWM FSET Resistor Fault Clear

Write "1" to both Status bit and Clear bit at same time to clear

interrupt register status and interrupt pin status.

INVSTRING_STATUS

Invalid LED String Configuration Fault Status

0h = No Fault

1h = Fault

4

3

INVSTRING_CLEAR

VINOVP_STATUS

R/W

0h

Invalid LED String Configuration Fault Clear

Write "1" to both Status bit and Clear bit at same time to clear

interrupt register status and interrupt pin status.

VIN Over-Voltage Fault Status

0h = No Fault

1h = Fault

2

1

VINOVP_CLEAR

VINUVP_STATUS

R/W

0h

VIN Over-Voltage Fault Clear

Write "1" to both Status bit and Clear bit at same time to clear

interrupt register status and interrupt pin status.

VIN Under-Voltage Fault Status

0h = No Fault

1h = Fault

0

VINUVP_CLEAR

R/W

0h

VIN Under-Voltage Fault Clear

Write "1" to both Status bit and Clear bit at same time to clear

interrupt register status and interrupt pin status.

8.6.1.13 JUNCTION_TEMPERATURE Register (Offset = E8h) [reset = 100h]

JUNCTION_TEMPERATURE is shown in Figure 46 and described in Table 26.

Return to Summary Table.

Figure 46. JUNCTION_TEMPERATURE Register

15

7

14

6

13

12

11

10

9

1

8

RESERVED

JUNCTION_TE

MPERATURE

R-0h

4

R-100h

0

5

3

2

JUNCTION_TEMPERATURE

R-100h

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Table 26. JUNCTION_TEMPERATURE Register Field Descriptions

Bit

Field

Type

Reset

Description

15-9

RESERVED

R

0h

These bits are reserved.

8-0

JUNCTION_TEMPERATU

RE

R

100h

Junction Temperature ADC Measurement

2's complement number.

000h - 0FFh = 0 °C to 255 °C

100h - 1FFh = –256 °C to –1 °C

8.6.1.14 TEMPERATURE_LIMIT_HIGH Register (Offset = ECh) [reset = 7Dh]

TEMPERATURE_LIMIT_HIGH is shown in Figure 47 and described in Table 27.

Return to Summary Table.

Figure 47. TEMPERATURE_LIMIT_HIGH Register

15

7

14

6

13

12

11

10

9

1

8

RESERVED

TEMPERATUR

E_LIMIT_HIGH

R-0h

4

R/W-7Dh

0

5

3

2

TEMPERATURE_LIMIT_HIGH

R/W-7Dh

Table 27. TEMPERATURE_LIMIT_HIGH Register Field Descriptions

Bit

Field

Type

Reset

Description

15-9

8-0

RESERVED

R

0h

These bits are reserved.

TEMPERATURE_LIMIT_ R/W

HIGH

7Dh

High Limit for Junction Temperature Monitor

2's complement number.

000h - 0FFh = 0 °C to 255 °C

100h - 1FFh = –256 °C to –1 °C

8.6.1.15 TEMPERATURE_LIMIT_LOW Register (Offset = EEh) [reset = 69h]

TEMPERATURE_LIMIT_LOW is shown in Figure 48 and described in Table 28.

Return to Summary Table.

Figure 48. TEMPERATURE_LIMIT_LOW Register

15

7

14

6

13

12

11

10

9

1

8

RESERVED

TEMPERATUR

E_LIMIT_LOW

R-0h

4

R/W-69h

0

5

3

2

TEMPERATURE_LIMIT_LOW

R/W-69h

Table 28. TEMPERATURE_LIMIT_LOW Register Field Descriptions

Bit

Field

Type

Reset

Description

15-9

8-0

RESERVED

R

0h

These bits are reserved.

TEMPERATURE_LIMIT_L R/W

OW

69h

Low Limit for Junction Temperature Monitor

2's complement number.

000h - 0FFh = 0 °C to 255 °C

100h - 1FFh = –256 °C to –1 °C

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8.6.1.16 CLUSTER1_BRT Register (Offset = 13Ch) [reset = FFFFh]

CLUSTER1_BRT is shown in Figure 49 and described in Table 29.

Return to Summary Table.

Figure 49. CLUSTER1_BRT Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CLUSTER1_BRT

R/W-FFFFh

Table 29. CLUSTER1_BRT Register Field Descriptions

Bit

15-0

Field

CLUSTER1_BRT

Type

Reset

Description

R/W

FFFFh

CLUSTER1 Brightness Control.

This register controls LED output duty cycle for the LED outputs

assigned to LED GROUP 1.

This register is buffered, write LOAD_BRT_DB bit to update.

8.6.1.17 CLUSTER2_BRT Register (Offset = 148h) [reset = FFFFh]

CLUSTER2_BRT is shown in Figure 50 and described in Table 30.

Return to Summary Table.

Figure 50. CLUSTER2_BRT Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CLUSTER2_BRT

R/W-FFFFh

Table 30. CLUSTER2_BRT Register Field Descriptions

Bit

15-0

Field

CLUSTER2_BRT

Type

Reset

Description

R/W

FFFFh

CLUSTER2 Brightness Control.

This register controls LED output duty cycle for the LED outputs

assigned to LED GROUP 2.

This register is buffered, write LOAD_BRT_DB bit to update.

8.6.1.18 CLUSTER3_BRT Register (Offset = 154h) [reset = FFFFh]

CLUSTER3_BRT is shown in Figure 51 and described in Table 31.

Return to Summary Table.

Figure 51. CLUSTER3_BRT Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CLUSTER3_BRT

R/W-FFFFh

Table 31. CLUSTER3_BRT Register Field Descriptions

Bit

15-0

Field

CLUSTER3_BRT

Type

Reset

Description

R/W

FFFFh

CLUSTER3 Brightness Control.

This register controls LED output duty cycle for the LED outputs

assigned to LED GROUP 3.

This register is buffered, write LOAD_BRT_DB bit to update.

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8.6.1.19 CLUSTER4_BRT Register (Offset = 160h) [reset = FFFFh]

CLUSTER4_BRT is shown in Figure 52 and described in Table 32.

Return to Summary Table.

Figure 52. CLUSTER4_BRT Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CLUSTER4_BRT

R/W-FFFFh

Table 32. CLUSTER4_BRT Register Field Descriptions

Bit

15-0

Field

CLUSTER4_BRT

Type

Reset

Description

R/W

FFFFh

CLUSTER4 Brightness Control.

This register controls LED output duty cycle for the LED outputs

assigned to LED GROUP 4.

This register is buffered, write LOAD_BRT_DB bit to update.

8.6.1.20 CLUSTER5_BRT Register (Offset = 16Ch) [reset = FFFFh]

CLUSTER5_BRT is shown in Figure 53 and described in Table 33.

Return to Summary Table.

Figure 53. CLUSTER5_BRT Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CLUSTER5_BRT

R/W-FFFFh

Table 33. CLUSTER5_BRT Register Field Descriptions

Bit

15-0

Field

CLUSTER5_BRT

Type

Reset

Description

R/W

FFFFh

CLUSTER5 Brightness Control.

This register controls LED output duty cycle for the LED outputs

assigned to LED GROUP 5.

This register is buffered, write LOAD_BRT_DB bit to update.

8.6.1.21 BRT_DB_CONTROL Register (Offset = 178h) [reset = 0h]

BRT_DB_CONTROL is shown in Figure 54 and described in Table 34.

Return to Summary Table.

Figure 54. BRT_DB_CONTROL Register

15

7

14

6

13

5

12

11

3

10

9

1

8

0

RESERVED

R/W-0h

4

2

RESERVED

R/W-0h

LOAD_BRT_D

B

R/W-0h

Table 34. BRT_DB_CONTROL Register Field Descriptions

Bit

Field

Type

Reset

Description

15-1

0

RESERVED

R/W

0h

These bits are reserved.

LOAD_BRT_DB

R/W

0h

Write this bit to "1" to update CLUSTERx_BRT registers and

LEDx_CURRENT registers (those registers are buffered).

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8.6.1.22 LED0_CURRENT Register (Offset = 1C2h) [reset = FFFh]

LED0_CURRENT is shown in Figure 55 and described in Table 35.

Return to Summary Table.

Figure 55. LED0_CURRENT Register

15

14

6

13

12

11

10

9

8

0

LED0_SHORT_

DISABLE

RESERVED

LED0_CURRENT

R/W-0h

7

R/W-0h

5

R/W-FFFh

4

3

2

1

LED0_CURRENT

R/W-FFFh

Table 35. LED0_CURRENT Register Field Descriptions

Bit

Field

Type

Reset

Description

15

LED0_SHORT_DISABLE R/W

0h

Short Fault Disable for LED0

0h = Short LED Faults are detected for LED0 output

1h = Short LED Faults are not detected for LED0 output

14-12

11-0

RESERVED

R/W

0h

LED0_CURRENT

FFFh

Individual LED Current control for LED0 Output

8.6.1.23 LED1_CURRENT Register (Offset = 1C4h) [reset = FFFh]

LED1_CURRENT is shown in Figure 56 and described in Table 36.

Return to Summary Table.

Figure 56. LED1_CURRENT Register

15

14

6

13

12

11

10

9

8

0

LED1_SHORT_

DISABLE

RESERVED

LED1_CURRENT

R/W-0h

7

R/W-0h

5

R/W-FFFh

4

3

2

1

LED1_CURRENT

R/W-FFFh

Table 36. LED1_CURRENT Register Field Descriptions

Bit

Field

Type

Reset

Description

15

LED1_SHORT_DISABLE R/W

0h

Short Fault Disable for LED1

0h = Short LED Faults are detected for LED1 output

1h = Short LED Faults are not detected for LED1 output

14-12

11-0

RESERVED

R/W

0h

LED1_CURRENT

FFFh

Individual LED Current control for LED1 Output

8.6.1.24 LED2_CURRENT Register (Offset = 1C6h) [reset = FFFh]

LED2_CURRENT is shown in Figure 57 and described in Table 37.

Return to Summary Table.

61

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Figure 57. LED2_CURRENT Register

15

14

6

13

12

11

10

9

8

LED2_SHORT_

DISABLE

RESERVED

LED2_CURRENT

R/W-0h

7

R/W-0h

5

R/W-FFFh

4

3

2

1

0

LED2_CURRENT

R/W-FFFh

Table 37. LED2_CURRENT Register Field Descriptions

Bit

Field

Type

Reset

Description

15

LED2_SHORT_DISABLE R/W

0h

Short Fault Disable for LED2

0h = Short LED Faults are detected for LED2 output

1h = Short LED Faults are not detected for LED2 output

14-12

11-0

RESERVED

R/W

0h

LED2_CURRENT

FFFh

Individual LED Current control for LED2 Output

8.6.1.25 LED3_CURRENT Register (Offset = 1C8h) [reset = FFFh]

LED3_CURRENT is shown in Figure 58 and described in Table 38.

Return to Summary Table.

Figure 58. LED3_CURRENT Register

15

14

6

13

12

11

10

9

8

0

LED3_SHORT_

DISABLE

RESERVED

LED3_CURRENT

R/W-0h

7

R/W-0h

5

R/W-FFFh

4

3

2

1

LED3_CURRENT

R/W-FFFh

Table 38. LED3_CURRENT Register Field Descriptions

Bit

Field

Type

Reset

Description

15

LED3_SHORT_DISABLE R/W

0h

Short Fault Disable for LED3

0h = Short LED Faults are detected for LED3 output

1h = Short LED Faults are not detected for LED3 output

14-12

11-0

RESERVED

R/W

0h

LED3_CURRENT

FFFh

Individual LED Current control for LED3 Output

8.6.1.26 LED4_CURRENT Register (Offset = 1CAh) [reset = FFFh]

LED4_CURRENT is shown in Figure 59 and described in Table 39.

Return to Summary Table.

Figure 59. LED4_CURRENT Register

15

14

6

13

12

11

10

9

8

0

LED4_SHORT_

DISABLE

RESERVED

LED4_CURRENT

R/W-0h

7

R/W-0h

5

R/W-FFFh

4

3

2

1

LED4_CURRENT

R/W-FFFh

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Table 39. LED4_CURRENT Register Field Descriptions

Bit

Field

Type

Reset

Description

15

LED4_SHORT_DISABLE R/W

0h

Short Fault Disable for LED4

0h = Short LED Faults are detected for LED4 output

1h = Short LED Faults are not detected for LED4 output

14-12

11-0

RESERVED

R/W

0h

LED4_CURRENT

FFFh

Individual LED Current control for LED4 Output

8.6.1.27 LED5_CURRENT Register (Offset = 1CCh) [reset = FFFh]

LED5_CURRENT is shown in Figure 60 and described in Table 40.

Return to Summary Table.

Figure 60. LED5_CURRENT Register

15

14

6

13

12

11

10

9

8

0

LED5_SHORT_

DISABLE

RESERVED

LED5_CURRENT

R/W-0h

7

R/W-0h

5

R/W-FFFh

4

3

2

1

LED5_CURRENT

R/W-FFFh

Table 40. LED5_CURRENT Register Field Descriptions

Bit

Field

Type

Reset

Description

15

LED5_SHORT_DISABLE R/W

0h

Short Fault Disable for LED5

0h = Short LED Faults are detected for LED5 output

1h = Short LED Faults are not detected for LED5 output

14-12

11-0

RESERVED

R/W

0h

LED5_CURRENT

FFFh

Individual LED Current control for LED5 Output

8.6.1.28 BOOST_CONTROL Register (Offset = 288h) [reset = 1C0h]

BOOST_CONTROL is shown in Figure 61 and described in Table 41.

Return to Summary Table.

Figure 61. BOOST_CONTROL Register

15

7

14

6

13

12

11

3

10

9

1

8

0

LED_EXT_SUPPLY

R/W-0h

RESERVED

R/W-1C0h

5

4

2

RESERVED

R/W-1C0h

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Table 41. BOOST_CONTROL Register Field Descriptions

Bit

Field

Type

Reset

Description

15-10

LED_EXT_SUPPLY

R/W

0h

Selects whether external LED voltage supply is used for a LED

output.

Bit 15 = LED5

Bit 14 = LED4

Bit 13 = LED3

Bit 12 = LED2

Bit 11 = LED1

Bit 10 = LED0

0h = LP8863 Boost Converter Supply is used

1h = External Supply is used.

9-0

RESERVED

R/W

1C0h

These bits are reserved.

8.6.1.29 SHORT_THRESH Register (Offset = 28Ah) [reset = 2882h]

SHORT_THRESH is shown in Figure 62 and described in Table 42.

Return to Summary Table.

Figure 62. SHORT_THRESH Register

15

7

14

6

13

5

12

4

11

3

10

SHORTED_LED_THRESHOLD

R/W-4h

9

1

8

RESERVED

R/W-2h

RESERVED

R/W-82h

2

0

RESERVED

R/W-82h

Table 42. SHORT_THRESH Register Field Descriptions

Bit

Field

RESERVED

Type

Reset

Description

15-12

11-9

R/W

2h

This bit is reserved.

SHORTED_LED_THRES R/W

HOLD

4h

Threshold for detecting Shorted LED Fault on LED outputs.

Fault is detected when LEDx pin voltage (referenced to ground)

exceeds selected threshold when LED driver is enabled.

0h = 2.6V

1h = 3.0V

2h = 3.4V

3h = 3.8V

4h = 4.2V

5h = 4.8V

6h = 5.2V

7h = 6.0V

8-0

RESERVED

R/W

82h

These bits are reserved.

8.6.1.30 FSM_DIAGNOSTICS Register (Offset = 2A4h) [reset = 0h]

FSM_DIAGNOSTICS is shown in Figure 63 and described in Table 43.

Return to Summary Table.

Figure 63. FSM_DIAGNOSTICS Register

15

14

13

12

11

10

9

8

RESERVED

R-0h

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7

6

5

4

3

2

1

0

RESERVED

R-0h

FSM_LIVE_STATUS

R-0h

Table 43. FSM_DIAGNOSTICS Register Field Descriptions

Bit

Field

Type

Reset

Description

15-5

RESERVED

R

0h

These bits are reserved.

4-0

FSM_LIVE_STATUS

R

0h

Current status of Device state machine.

1h = LDO_STARTUP

2h = EEPROM_READ

3h = STANDBY

4h - Ch = BOOST_START

Dh = NORMAL

Eh = DISCHARGE

Fh = SHUTDOWN

10h = FAULT_RECOVERY

11h = ALL_LED_FAULT

8.6.1.31 PWM_INPUT_DIAGNOSTICS Register (Offset = 2A6h) [reset = 0h]

PWM_INPUT_DIAGNOSTICS is shown in Figure 64 and described in Table 44.

Return to Summary Table.

Figure 64. PWM_INPUT_DIAGNOSTICS Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PWM_INPUT_STATUS

R-0h

Table 44. PWM_INPUT_DIAGNOSTICS Register Field Descriptions

Bit

15-0

Field

PWM_INPUT_STATUS

Type

Reset

Description

16bit value for detected duty cycle of PWM input signal.

R

0h

8.6.1.32 PWM_OUTPUT_DIAGNOSTICS Register (Offset = 2A8h) [reset = 0h]

PWM_OUTPUT_DIAGNOSTICS is shown in Figure 65 and described in Table 45.

Return to Summary Table.

Figure 65. PWM_OUTPUT_DIAGNOSTICS Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

LED_PWM_STATUS

R-0h

Table 45. PWM_OUTPUT_DIAGNOSTICS Register Field Descriptions

Bit

15-0

Field

LED_PWM_STATUS

Type

Reset

Description

R

0h

16-bit PWM Duty Code that Brightness path is driving to LED0

output.

8.6.1.33 LED_CURR_DIAGNOSTICS Register (Offset = 2AAh) [reset = 0h]

LED_CURR_DIAGNOSTICS is shown in Figure 66 and described in Table 46.

Return to Summary Table.

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Figure 66. LED_CURR_DIAGNOSTICS Register

15

7

14

6

13

12

11

10

9

8

0

RESERVED

R-0h

LED_CURRENT_STATUS

R-0h

5

4

3

2

1

LED_CURRENT_STATUS

R-0h

Table 46. LED_CURR_DIAGNOSTICS Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

11-0

RESERVED

R

0h

These bits are reserved.

LED_CURRENT_STATU

S

R

0h

12-bit Current DAC Code that Brightness path is driving to LED0

output.

8.6.1.34 ADAPT_BOOST_DIAGNOSTICS Register (Offset = 2ACh) [reset = 0h]

ADAPT_BOOST_DIAGNOSTICS is shown in Figure 67 and described in Table 47.

Return to Summary Table.

Figure 67. ADAPT_BOOST_DIAGNOSTICS Register

15

7

14

6

13

12

11

10

2

9

8

0

RESERVED

R-0h

VBOOST_STATUS

R-0h

5

4

3

1

VBOOST_STATUS

R-0h

Table 47. ADAPT_BOOST_DIAGNOSTICS Register Field Descriptions

Bit

Field

Type

Reset

Description

15-11

10-0

RESERVED

R

0h

These bits are reserved.

VBOOST_STATUS

R

0h

11-bit Boost Voltage Code that Adaptive Voltage Control Loop is

sending to Analog Boost Block.

Boost Output Voltage =

((R_FB1/R_FB2)*1.2)+(R_FB1*18.75nA*VBOOST_STATUS)

8.6.1.35 AUTO_DETECT_DIAGNOSTICS Register (Offset = 2AEh) [reset = 0h]

AUTO_DETECT_DIAGNOSTICS is shown in Figure 68 and described in Table 48.

Return to Summary Table.

Figure 68. AUTO_DETECT_DIAGNOSTICS Register

15

14

13

12

11

10

9

1

8

RESERVED

AUTO_PWM_F

REQ_SEL

R-0h

0

7

6

5

4

AUTO_BOOST_FREQ_SEL

R-0h

3

2

AUTO_PWM_FREQ_SEL

R-0h

AUTO_LED_STRING_CFG

R-0h

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Table 48. AUTO_DETECT_DIAGNOSTICS Register Field Descriptions

Bit

Field

Type

Reset

Description

15-9

RESERVED

R

0h

These bits are reserved.

8-6

5-3

2-0

AUTO_PWM_FREQ_SEL

R

0h

PWM Frequency Setting based on PWM_FSET resistor detection.

0h = 152Hz

1h = 305Hz

2h = 610 Hz

3h = 1.22kHz

4h = 2.44kHz

5h = 4.88kHz

6h = 9.77kHz

7h = 19.53kHz

AUTO_BOOST_FREQ_S

EL

Boost Frequency Setting based on BST_FSET resistor detection.

0h = 303kHz

1h = 400kHz

2h = 606kHz

3h = 800kHz

4h = 1MHz

5h = 1.25 MHz

6h = 1.67MHz

7h = 2.2MHz

AUTO_LED_STRING_CF

G

Detected LED string configuration.

0h = 6 separate strings

1h = 5 separate strings

2h = 4 separate strings

3h = 3 separate strings

4h = 2 separate strings

5h = outputs connected in groups of 2 to drive 3 strings

6h = outputs connected in groups of 3 to drive 2 strings

7h = all outputs connected together to drive one string

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9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LP8863-Q1 device is designed for automotive applications, and an input voltage V_INis intended to be

connected to the vehicle battery. Depending on the input voltage, the device may be used in either boost mode

or SEPIC mode. The device is internally powered from the VDD pin, and voltage must be in 2.7-V to 5.5-V range.

The device has flexible configurability through external components or by an SPI or I2C interface. If the VDD

voltage is not high enough to drive an external nMOSFET gate, an internal charge pump must be used to power

the gate driver (GD pin).

注

For applications where V_INvoltage is below the output voltage, use a boost converter

topology. Maximum operating voltage for V_INis 48 V, and the boost converter can achieve

output voltage up to 47 V. Conversion ratio of 5.5 (full load) or 10 (half load) must be

taken into account. If V_INvoltage is expected to be below or above output voltage, a

SEPIC converter can be implemented. The SEPIC converter can achieve maximum output

voltage up to 24 V, and maximum conversion ratio for SEPIC mode is 5.

9.2 Typical Applications

9.2.1 Full Feature Application for Display Backlight

图 69 shows a full application for the LP8863-Q1 device in a boost topology. It supports 6 LED strings in display

mode, each at 100 mA, with an automatic 60° phase shift. Brightness control register is used for LED dimming

method through I2C communication. The charge pump is enabled for a 400-kHz boost switching frequency with

spread spectrum.

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Typical Applications (接下页)

D1

Q2

L1

RISENSE

VIN

VOUT

COUT

RSD

CIN

CPUMP

RFB1

RFB2

CPUMP

Q1

GD

ISNS

C1N

PGND

RSENSE

C2x

PGND

ISNSGND

C1P

VDD

FB

VDD

DISCHARGE

GND

CVDD

CLDO

VLDO

LED0

LED1

LED2

LED3

LP8863-Q1

VDDIO

IFSEL

HOST

EN

INT

SDO_PWM

SDI_SDA

SCLK_SCL

LED4

LED5

ISET

I2C

SS_ADDRSEL

BST_SYNC

RISET

PWM_FSET

BST_FSET

RPWM

VDDIO

RBST

图 69. Full Feature Application for Display Backlight

9.2.1.1 Design Requirements

This typical LED-driver application is designed to meet the parameters listed in 表 49:

表 49. LP8863-Q1 Full-Feature Design Parameters

DESIGN PARAMETER

VIN voltage range

VALUE

3 V to 20 V

VDD voltage

3.3 V

LED strings configuration

Charge pump

6 strings, 7 LEDs in series

Enabled

I2C

Brightness control

Output configuration

LED string current

Boost frequency

Inductor

LED0 to LED5 are in display mode (phase shift 60°)

100 mA

400 kHz

22 µH at 12-A saturation current

R_ISENSE

20 mΩ

Power-line FET

R_SENSE

Enabled

20 mΩ

Input/Output capacitors

Spread spectrum

Discharge function

C_INand C_OUT: 2 × 33-µF electrolytic + 2 × 10-µF ceramic

Enabled

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9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Inductor Selection

There are a few things to consider when choosing an inductor: inductance, current rating, and DC resistance

(DCR). 表 50 shows recommended inductor values for each operating frequency. The LP8863-Q1 device

automatically sets internal boost compensation controls depending on the selected switching frequency.

表 50. Inductance Values for Boost Switching Frequencies

SW FREQUENCY (kHz)

INDUCTANCE (µH)

300

400

22

15

10

600

800

1000

1250

1667

2200

The current rating of inductor must be at least 25% higher than maximum boost switching current I_SW(max), which

can be calculated with 公式 12. TI recommends a current rating of 12 A for most applications; use an inductor

with low DCR to achieve good efficiency. Efficiency varies with load condition, switching frequency, and

components, but 80% can be use as safe estimation. Power Stage Designer™ Tools can be used for the boost

calculation: http://www.ti.com/tool/powerstage-designer

I_OUT(max)

DI_L

2

I_SW(max)

=

+

1- D

where

•

ΔI_L= V_IN(min)× D / ( ƒ_SW× L )

D = 1 – V_IN(min)× η / V_OUT

I_SW(max): Maximum switching current

ΔI_L: Inductor ripple current

I_OUT(max): Maximum output current

D: Boost duty cycle

V_IN(min): Minimum input voltage

ƒ_SW: Minimum switching frequency of the converter

L: Inductance

V_OUT: Output voltage

η: Efficiency of boost converter

(12)

9.2.1.2.2 Output Capacitor Selection

Recommended voltage rating for output capacitors is 50% higher than maximum output voltage level — 100-V

voltage rating is recommended. Capacitance value determines voltage ripple and boost stability. The DC-bias

effect can reduce the effective capacitance significantly, by up to 80%, a consideration for capacitance value

selection. Effective capacitance must be at least 50 µF for full load/maximum conversion ratio applications and

must be used to achieve good phase and gain margin levels. TI recommends using two 33-µF Al-polymer

electrolytic capacitors and two 10-µF ceramic capacitors in parallel to reduce ripple, increase stability, and

reduce ESR effect.

9.2.1.2.3 Input Capacitor Selection

Recommended input capacitance is the same as output capacitance although input capacitors are not as critical

to boost operation. Input capacitance can be reduced but must ensure enough filtering for input power.

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9.2.1.2.4 Charge Pump Output Capacitor

TI recommends a ceramic capacitor with at least 16-V voltage rating for the output capacitor of the charge pump.

A 10-μF capacitor can be used for most applications.

9.2.1.2.5 Charge Pump Flying Capacitor

TI recommends a ceramic capacitor with at least 16-V voltage rating for the flying capacitor of the charge pump.

One 2.2-μF capacitor connecting C1P and C1N pins can be used for most applications.

9.2.1.2.6 Output Diode

A Schottky diode must be used for the boost output diode. Current rating must be at least 25% higher than the

maximum output current; TI recommends a 12-A current rating for most applications. Schottky diodes with a low

forward drop and fast switching speeds are ideal for increasing efficiency. At maximum current, the forward

voltage must be as low as possible; less than 0.5 V is recommended. Reverse breakdown voltage of the

Schottky diode must be significantly larger than the output voltage, 25% higher voltage rating is recommended.

Do not use ordinary rectifier diodes, because slow switching speeds and long recovery times cause efficiency

and load regulation to suffer.

9.2.1.2.7 Switching FET

Gate-drive voltage for the FET is V_DDwith charge pump bypassed, or about double V_DD, if the charge pump is

enabled. Switching FET is a critical component for determining power efficiency of the boost converter. Several

aspects need to be considered when selecting switching FET such as voltage and current rating, R_DSON, power

dissipation, thermal resistance and rise/fall times. An N type MOSFET with at least 25% higher voltage rating

than maximum output voltage must be used. Current rating of switching FET should be same or higher than

inductor rating. R_DSONmust be as low as possible, less than 20 mΩ is recommended. Thermal resistance (R_θJA

)

must also be low to dissipate heat from power loss on switching FET. TI recommends typical rise/fall time values

less than 10 ns.

9.2.1.2.8 Boost Sense Resistor

The R_SENSEresistor determines the boost overcurrent limit and is sensed every boost switching cycle. A high-

power 20-mΩ resistor can be used for sensing the boost SW current and setting maximum current limit at 10 A

(typical). R_SENSEcan be increased to lower this limit and can be calculated with 公式 13, but this should be done

carefully because it may also affect stability. Boost overcurrent limit must not be set below 4 A, therefore R_SENSE

must not exceed 50 mΩ. Power rating can be calculated from the inductor current and sense resistor resistance

value.

200 mV

R_SENSE

=

I_{BOOST _OCP}

where

•

R_SENSE: boost sense resistor (mΩ)

I_{BOOST_OCP}: boost overcurrent limit

(13)

9.2.1.2.9 Power-Line FET

A power line FET can be used to disconnect input power from boost input to protect the LP8863-Q1 device and

boost components in case an overcurrent event occurs. A P type MOSFET is used for the power-line FET.

Voltage rating must be at least 25% higher than maximum input voltage level. Low R_DSONis important to reduce

power loss on the FET — less than 20 mΩ is recommended. Current rating for the FET must be at least 25%

higher than input peak current. Gate-to-source voltage (V_GS) for open transistor must be less than minimum input

voltage; use a 20-kΩ resistor between the pFET gate and source.

9.2.1.2.10 Input Current Sense Resistor

A high-power resistor can be used for sensing the boost input current. Overcurrent condition is detected when

the voltage across R_ISENSEreaches 220 mV. Typical 20 mΩ sense resistor is used to set 11-A input current limit.

Sense resistor value can be increased to lower overcurrent limit for application as needed. Power rating can be

calculated from the input current and resistance value.

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9.2.1.2.11 Feedback Resistor Divider

Feedback resistors R_FB1and R_FB2determine the maximum boost output level. Output voltage can be calculated

as in 公式 14:

≈

∆

«

’

V_BG

V_{OUT_MAX}

=

+ I_{SEL_MAX}ì R_FB1+ V_BG

÷

R_FB2

◊

where

•

V_BG= 1.21 V

I_{SEL_MAX}= 38.7 µA

R_FB2= 100 kΩ (recommended for boost mode)

(14)

9.2.1.2.12 Critical Components for Design

图 70 shows the critical part of circuitry: boost components, the LP8863-Q1 internal charge pump for gate-driver

powering, and powering/grounding of LP8863-Q1. Schematic example is shown in 图 70.

D1

Q2

L1

RISENSE

VIN

VOUT

COUT

RSD

CIN

CPUMP

RFB1

CPUMP

Q1

GD

ISNS

C1N

PGND

RSENSE

RFB2

C2x

PGND

ISNSGND

C1P

VDD

FB

VDD

DISCHARGE

GND

CVDD

VLDO

LED0

LED1

LED2

LED3

CLDO

LP8863-Q1

VDDIO

IFSEL

HOST

EN

INT

SDO_PWM

SDI_SDA

SCLK_SCL

LED4

LED5

ISET

I2C

SS_ADDRSEL

BST_SYNC

RISET

PWM_FSET

BST_FSET

RPWM

VDDIO

RBST

图 70. Critical Components for Full Feature Design

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表 51. Recommended Component Values for Full Feature Design Example

REFERENCE

DESCRIPTION

NOTE

DESIGNATOR

R_ISENSE

R_SD

20 mΩ, 3 W

20 kΩ, 0.1 W

Input current sensing resistor

Power-line FET gate pullup resistor

Boost current sensing resistor

Bottom feedback divider resistor

Top feedback divider resistor

Boost frequency set resistor

Current set resistor for 100 mA maximum

Output PWM frequency set resistor

Charge-pump output capacitor

Flying capacitor

R_SENSE

R_FB2

20 mΩ, 3 W

100 kΩ, 0.1 W

R_FB1

910 kΩ, 0.1 W

R_BST

R_ISET

R_PWM

C_PUMP

C_2X

4.77 kΩ, 0.1 W

31.2 kΩ, 0.1 W

42.2 kΩ, 0.1 W

10-µF, 16-V ceramic

2.2-µF, 25-V ceramic

C_VDD

C_LDO

C_IN

4.7-µF + 0.1-µF, 10-V ceramic

2 × 33-µF, 63-V electrolytic + 2 × 10-µF, 100-V ceramic

22-μH saturation current 23 A

100 V, 10-A Schottky diode

60-V, 25-A nMOSFET

VDD bypass capacitor

VLDO bypass capacitor

Boost input capacitor

C_OUT

L1

Boost output capacitor

Boost inductor

D1

Boost Schottky diode

Q1

Boost nMOSFET

Q2

60-V, 30-A pMOSFET

Power-line FET

9.2.1.3 Application Curves

F_{LED_PWM}= 300 Hz

Phase Shift 60°

6 Strings

ƒ_SW= 400 kHz

100 mA/String

C_IN= C_OUT= 2 × 33 μF (electrolytic) + 2 × 10 μF (ceramic)

图 71. LED String Currents Showing Phase Shift PWM

图 72. Typical Start-Up

Operation

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9.2.2 Application With Basic/Minimal Operation

The LP8863-Q1 needs only a few external components for basic functionality if material cost and PCB area for a

solution need to be minimized. In this example LP8863-Q1 is configured with external components and no I2C or

SPI communication. The power-line FET is removed, as is input current sensing. Internal charge pump is not

used, and all external synchronization functions and special features are disabled. Only 5 LED strings are

enabled.

D1

L1

VIN

VOUT

COUT

CIN

CPUMP

RFB1

CPUMP

Q1

GD

ISNS

C1N

PGND

RSENSE

RFB2

PGND

ISNSGND

C1P

RFB3

VDD

FB

VDD

DISCHARGE

CVDD

GND

VLDO

LED0

LED1

LED2

LED3

LED4

CLDO

LP8863-Q1

VDDIO

IFSEL

EN

INT

SDO_PWM

SDI_SDA

SCLK_SCL

LED5

ISET

SS_ADDRSEL

BST_SYNC

RISET

PWM_FSET

BST_FSET

RPWM

RBST

图 73. Minimal Solution/Minimum Components Application

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9.2.2.1 Design Requirements

This typical LED-driver application is designed to meet the parameters listed in 表 52:

表 52. LP8863-Q1 Minimal Solution Design Parameters

DESIGN PARAMETER

V_INvoltage range

VALUE

5 V to 30 V

V_DDvoltage

5 V (note: 5 V required when charge pump disabled.)

5 strings, 10 LEDs in series

LED strings configuration

R_FB1= 100 kΩ, R_FB2= 6 kΩ , R_FB3= 27 kΩ (maximum output

voltage set to 43.5 V)

3-resistor feedback network

Charge pump

Disabled

Brightness control

PWM input

LED0 to LED4 are in display mode (phase shift 72°); LED5 is

not used (GND)

Output configuration

LED string current

Boost frequency

Inductor

150 mA

300 kHz

22 µH at 12-A saturation current

Power-line FET

R_SENSE

Disabled

20 mΩ

Power-line FET

R_SENSE

Enabled

20 mΩ

Input/Output capacitors

Spread spectrum

Discharge function

C_INand C_OUT: 2 × 33-µF electrolytic + 2 × 10-µF ceramic

Disabled

9.2.2.2 Detailed Design Procedure

See Detailed Design Procedure

9.2.2.3 Application Curves

See Application Curves

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9.2.3 SEPIC Mode Application

When LED string voltage can be above and below the input voltage level, use the SEPIC configuration. In SEPIC

mode, the SW pin detects a maximum voltage equal to the sum of the input and output voltages, a consideration

when selecting components. This fact limits the maximum output voltage to 24 V. External frequency can be

used to synchronize boost or SEPIC switching frequency through the BST_SYNC pin.

CS2

RS

D1

Q2

L1

RISENSE

VIN

VOUT

COUT

RFB1

RSD

CIN

CS1

L2

CPUMP

Q1

GD

ISNS

C1N

PGND

RSENSE

RFB2

C2x

PGND

ISNSGND

C1P

VDD

FB

VDD

DISCHARGE

GND

CVDD

VLDO

LED0

LED1

LED2

LED3

CLDO

LP8863-Q1

VDDIO

IFSEL

HOST

EN

INT

SDO_PWM

SDI_SDA

LED4

LED5

ISET

SCLK_SCL

SPI

SS_ADDRSEL

RISET

PWM_FSET

BST_FSET

BST_SYNC

RPWM

RBST

图 74. SEPIC Mode with Three LEDs in Series

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9.2.3.1 Design Requirements

This typical LED-driver application is designed to meet the parameters listed in 表 53:

表 53. LP8863-Q1 SEPIC Mode Design Parameters

DESIGN PARAMETER

V_INvoltage range

VALUE

3 V to 48 V

V_DDvoltage

3.3 V

LED strings configuration

Charge pump

6 strings, 3 LEDs in series

Enabled

SPI

Brightness control

Output configuration

LED string current

LED0 to LED5 are in display mode (phase shift 60°)

150 mA

2.2 MHz (Note: BST_SYNC frequency must be 0.2 to 0.5%

higher than frequency set by BST_FSET resistor.)

BST_SYNC external signal frequency

BST_FSET resistor

Inductor

42.2 kΩ (sets boost frequency to 1.6 MHz)

10 µH at 12-A saturation current

R_ISENSE

20 mΩ

Power-line FET

R_SENSE

Enabled

20 mΩ

Input/Output capacitors

Spread spectrum

Discharge function

Boost synchronization

C_INand C_OUT: 2 × 33-µF electrolytic + 2 × 10-µF ceramic

Disabled

Enabled

.

9.2.3.2 Detailed Design Procedure

9.2.3.2.1 Inductor Selection

Inductance for both inductors can be selected from 表 54, depending on operating frequency for the application.

Current rating is recommended to be at least 25% higher than maximum inductor peak current. Peak-to-peak

ripple current can be estimated to be approximately 40% of the maximum input current and and inductor peak

current can be calculated with 公式 15, 公式 16, and 公式 17:

表 54. Inductance Values for SEPIC Switching

Frequencies

SW FREQUENCY (kHz)

INDUCTANCE (µH)

300

400

15

600

10

800

10

1000

1250

1667

2200

6.8

4.7

77

LP8863-Q1

ZHCSGN5B –MARCH 2017–REVISED JULY 2018

www.ti.com.cn

V_OUT+ V_D

40%

2

≈

’

I_L1(peak)= I_OUT

ì

1+

∆

«

÷

◊

V

IN(min)

where

•

I_L1(peak): Peak current for inductor 1

I_OUT: Maximum output current

V_OUT: Output voltage

V_D: Diode forward voltage drop

V_IN(min): Minimum input voltage

(15)

(16)

40%

2

≈

’

I_L2(peak)= I_OUT

ì

1+

∆

«

÷

◊

where

•

I_L2(peak): Peak current for inductor 2

I_OUT: Maximum output current

V_OUT

DI_L= I ì 40% = I_OUT

ì

ì 40%

IN

V

IN(min)

where

•

ΔI_L: Inductor ripple current

I_IN: Input current

V_OUT: Output voltage

V_IN(min): Minimum input voltage

(17)

9.2.3.2.2 Coupling Capacitor Selection

The coupling capacitors Cs isolate the input from the output and provide protection against a shorted load. The

selection of SEPIC capacitors, Cs, depends mostly on the RMS current, which can be calculated with 公式 18.

The capacitors must be rated for a large RMS current relative to the output power; TI recommends at least 25%

higher rating for I_RMS. When using uncoupled inductors, use one 10-µF ceramic capacitor in parallel with one 33-

µF electrolytic capacitor and series 2-Ω resistor. If coupled inductors are used, then use only one 10-µF ceramic

capacitor.

V_OUT+ V_D

I_Cs(rms)= I_OUT

ì

V

IN(min)

where

•

I_Cs(rms): RMS current of Cs capacitor

I_OUT: Output current

V_OUT: Output voltage

V_D: Diode forward voltage drop

V_IN(min): Minimum input voltage

(18)

9.2.3.2.3 Output Capacitor Selection

See Detailed Design Procedure

9.2.3.2.4 Input Capacitor Selection

See Detailed Design Procedure

9.2.3.2.5 Charge Pump Output Capacitor

See Detailed Design Procedure

9.2.3.2.6 Charge Pump Flying Capacitor

See Detailed Design Procedure

78

LP8863-Q1

www.ti.com.cn

ZHCSGN5B –MARCH 2017–REVISED JULY 2018

9.2.3.2.7 Switching FET

Gate-drive voltage for the FET is V_DDor about 2 × V_DD, if the charge pump is enabled. Use an N-type MOSFET

for the switching FET. The switching FET for SEPIC mode sees a maximum voltage of V_IN(max)+ V_OUT, 25%

higher rating is recommended. Current rating is also recommended to be 25% higher than peak current, which

can be calculated with 公式 19. R_DSONmust be as low as possible — less than 20 mΩ is recommended. Thermal

resistance (R_θJA) must also be low to dissipate heat from power loss on switching FET. Typical rise/fall time

values recommended are less than 10 ns.

I_Q1(peak)= I_L1(peak)+ I_L2(peak)

where

•

I_Q1(peak): Peak current for switching FET

I_L1(peak): Peak current for inductor 1

I_IL2(peak):: Peak current for inductor 2 BOOST_OCP

(19)

9.2.3.2.8 Output Diode

A Schottky diode must be used for the SEPIC output diode. Current rating must be at least 25% higher than the

maximum current, which is the same as switch peak current. Schottky diodes with a low forward drop and fast

switching speeds are ideal for increasing efficiency. At maximum current, the forward voltage must be as low as

possible; TI recommends less than 0.5 V. Reverse breakdown voltage of the Schottky diode must be able to

withstand V_IN(max)+ V_OUT(max); at least 25% higher voltage rating is recommended. Do not use ordinary rectifier

diodes, because slow switching speeds and long recovery times cause efficiency and load regulation to suffer.

9.2.3.2.9 Switching Sense Resistor

See Detailed Design Procedure

9.2.3.2.10 Power-Line FET

See Detailed Design Procedure

9.2.3.2.11 Input Current Sense Resistor

See Detailed Design Procedure

9.2.3.2.12 Feedback Resistor Divider

Feedback resistors R_FB1and R_FB2determine the maximum boost output level. Output voltage can be calculated

as follows:

≈

∆

«

’

V_BG

V_{OUT _MAX}

=

+ I_{SEL_MAX}ì R_FB1+ V_BG

÷

R_FB2

◊

where

•

V_BG= 1.21 V

I_{SEL_MAX}= 38.7 µA

R_FB2= 170 kΩ (recommended for SEPIC Mode)

(20)

9.2.3.2.13 Critical Components for Design

图 75 shows the critical part of circuitry: SEPIC components, the LP8863-Q1 internal charge pump for gate-driver

powering, and powering/grounding of LP8863-Q1. Schematic example is shown in 图 70.

79

LP8863-Q1

ZHCSGN5B –MARCH 2017–REVISED JULY 2018

www.ti.com.cn

CS2

RS

D1

Q2

L1

RISENSE

VIN

VOUT

COUT

RFB1

RSD

CIN

CS1

L2

CPUMP

Q1

GD

ISNS

C1N

PGND

RSENSE

RFB2

C2x

PGND

ISNSGND

C1P

VDD

FB

VDD

DISCHARGE

GND

CVDD

VLDO

LED0

LED1

LED2

LED3

CLDO

LP8863-Q1

VDDIO

IFSEL

HOST

EN

INT

SDO_PWM

SDI_SDA

LED4

LED5

ISET

SCLK_SCL

SPI

SS_ADDRSEL

RISET

PWM_FSET

BST_FSET

BST_SYNC

RPWM

RBST

图 75. Critical Components for SEPIC Mode Design

表 55. Recommended Components for SEPIC Design Example

REFERENCE DESIGNATOR

DESCRIPTION

20 mΩ, 3 W

NOTE

R_ISENSE

R_SD

Input current sensing resistor

20 kΩ, 0.1 W

Power-line FET gate pullup resistor

SEPIC current sensing resistor

Bottom feedback divider resistor

Top feedback divider resistor

SEPIC frequency set resistor

Current set resistor for 150 mA max

Output PWM frequency set resistor

Charge pump output capacitor

Flying capacitor

R_SENSE

R_FB2

R_FB1

R_BST

R_ISET

R_PWM

C_PUMP

C2x

20 mΩ, 3 W

170 kΩ, 0.1 W

560 kΩ, 0.1 W

140 kΩ, 0.1 W

20.5 kΩ, 0.1 W

140 kΩ, 0.1 W

10-µF, 16-V ceramic

2.2-µF, 25-V ceramic

4.7-µF + 0.1-µF, 10-V ceramic

10-µF + 0.1-µF, 10-V ceramic

2 × 33-µF, 63-V electrolytic

10-µF, 100-V ceramic

33-µF, 63-V electrolytic

2 Ω, 0.125 W

C_VDD

C_LDO

C_IN

V_DDbypass capacitor

VLDO bypass capacitor

SEPIC input capacitor

C_OUT

C_S1

SEPIC output capacitor

SEPIC coupling capacitor

SEPIC resistor

C_S2

RS

L1

10-µH saturation current 15.5 A

100-V 10-A Schottky diode

60-V, 25-A nMOSFET

60-V, 30-A pMOSFET

SEPIC inductor

L2

SEPIC inductor

D1

SEPIC Schottky diode

Q1

SEPIC nMOSFET

Q2

Power-line FET

80

LP8863-Q1

www.ti.com.cn

ZHCSGN5B –MARCH 2017–REVISED JULY 2018

9.2.3.3 Application Curves

See Application Curves

10 Power Supply Recommendations

The LP8863-Q1 is designed to operate from a car battery. The V_INinput must be protected from reverse voltage

and voltage dump condition over 48 V. The impedance of the input supply rail must be low enough that the input

current transient does not cause drop below VIN UVLO level. If the input supply is connected with long wires,

additional bulk capacitance may be required in addition to normal input capacitor.

The voltage range for V_DDis 3 V to 5.5 V. A ceramic capacitor must be placed as close as possible to the VDD

pin. The boost gate driver is powered from the CPUMP pins. A ceramic capacitor must be placed as close to the

CPUMP pins as possible.

81

LP8863-Q1

ZHCSGN5B –MARCH 2017–REVISED JULY 2018

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

图 76 shows a layout recommendation for the LP8863-Q1 used to illustrate the principles of good layout. This

layout can be adapted to the actual application layout if and where possible. It is important that all boost

components are close to each other and to the chip; the high-current traces must be wide enough. VDD must be

as noise-free as possible. Place a V_DDbypass capacitor near the VDD and GND pins and ground it to a low-

noise ground. A charge-pump capacitor, boost input capacitors, and boost output capacitors must be connected

to PGND. Place the charge-pump capacitors close to the device. The main points to guide the PCB layout

design:

•

Current loops need to be minimized:

–

For low frequency the minimal current loop can be achieved by placing the boost components as close as

possible to each other. Input and output capacitor grounds need to be close to each other to minimize

current loop size.

–

Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact

under the current traces. High frequency return currents follow the route with minimum impedance, which

is the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when

return current flows just under the positive current route in the ground plane, if the ground plane is intact

under the route.

–

For high frequency the copper area capacitance must be taken into account. For example, the copper

area for the drain of boost nMOSFET is a tradeoff between capacitance and the cooling capacity of the

components.

•

GND plane must be intact under the high-current-boost traces to provide shortest possible return path and

smallest possible current loops for high frequencies.

Current loops when the boost switch is conducting and not conducting must be in the same direction in

optimal case.

Inductors must be placed so that the current flows in the same direction as in the current loops. Rotating the

inductor 180° changes current direction.

Use separate power and noise-free grounds. PGND is used for boost converter return current. Use a low-

noise ground for more sensitive signals, like VDD bypass capacitor grounding as well as grounding the GND

pins of the LP8863-Q1 device itself.

•

Route boost output voltage (V_OUT) to LEDs from output capacitors not straight from the diode cathode.

A small bypass capacitor (TI recommends a 39-pF capacitor) must be placed close to the FB pin to suppress

high frequency noise

•

VDD line must be separated from the high current supply path to the boost converter to prevent high

frequency ripple affecting the chip behavior. A separate 1-µF bypass capacitor is used for the VDD pin, and it

is grounded to noise-free ground.

Capacitor connected to charge pump output CPUMP must have 10-µF capacitance, grounded by the shortest

way to boost a switch-current-sensing resistor. This capacitor must be as close as possible to CPUMP pin.

This capacitor provides a greater peak current for gate driver and must be used even if the charge pump is

disabled. If the charge pump is disabled, the VDD and CPUMP pins must be tied together.

•

Input and output capacitors need low-impedence grounding (wide traces with many vias to PGND plane).

If two or more output capacitors are used, symmetrical layout must be used to get all capacitors working

ideally.

•

Input/output ceramic capacitors have DC-bias effect. If the output capacitance is too low, it can cause boost

to become unstable under certain load conditions. DC bias characteristics should be obtained from the

component manufacturer; DC bias is not taken into account on component tolerance. TI recommends

X5R/X7R capacitors.

82

LP8863-Q1

www.ti.com.cn

ZHCSGN5B –MARCH 2017–REVISED JULY 2018

11.2 Layout Example

图 76. LP8863-Q1 Layout Guidelines

83

LP8863-Q1

ZHCSGN5B –MARCH 2017–REVISED JULY 2018

www.ti.com.cn

12 器件和文档支持

12.1 器件支持

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

12.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.6 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。

84

PACKAGE MATERIALS INFORMATION

www.ti.com

18-Mar-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LP8863ADCPRQ1

HTSSOP DCP

38

2000

330.0

16.4

6.9

10.2

1.8

12.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

18-Mar-2019

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTSSOP DCP 38

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 43.0

LP8863ADCPRQ1

2000

Pack Materials-Page 2

GENERIC PACKAGE VIEW

DCP 38

4.4 x 9.7, 0.5 mm pitch

PowerPAD TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224560/B

www.ti.com

PACKAGE OUTLINE

DCP0038A

PowerPAD^TMTSSOP - 1.2 mm max height

S

C

A

L

E

2

.

0

SMALL OUTLINE PACKAGE

C

6.6

6.2

TYP

A

0.1 C

PIN 1 INDEX

AREA

SEATING

PLANE

36X 0.5

38

1

2X

9

9.8

9.6

NOTE 3

19

20

0.27

0.17

0.08

38X

4.5

4.3

B

C A B

SEE DETAIL A

(0.15) TYP

2X 0.95 MAX

NOTE 5

19

20

2X 0.95 MAX

NOTE 5

0.25

GAGE PLANE

1.2 MAX

39

4.70

3.94

THERMAL

PAD

0.15

0.05

0.75

0.50

0 -8

A

20

DETAIL A

TYPICAL

1

38

2.90

2.43

4218816/A 10/2018

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may differ or may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

DCP0038A

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

(3.4)

NOTE 9

METAL COVERED

BY SOLDER MASK

(2.9)

SYMM

38X (1.5)

38X (0.3)

SEE DETAILS

38

1

(R0.05) TYP

36X (0.5)

3X (1.2)

SYMM

39

(4.7)

(9.7)

NOTE 9

(0.6) TYP

SOLDER MASK

DEFINED PAD

(

0.2) TYP

VIA

20

19

(1.2)

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 8X

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

SOLDER MASK DETAILS

4218816/A 10/2018

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged

or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DCP0038A

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

(2.9)

BASED ON

0.125 THICK

STENCIL

38X (1.5)

38X (0.3)

METAL COVERED

BY SOLDER MASK

1

38

(R0.05) TYP

36X (0.5)

(4.7)

SYMM

39

BASED ON

0.125 THICK

STENCIL

19

20

SYMM

(5.8)

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 8X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

3.24 X 5.25

2.90 X 4.70 (SHOWN)

2.65 X 4.29

0.125

0.15

0.175

2.45 X 3.97

4218816/A 10/2018

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

www.ti.com

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TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

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型号：	LP8863-Q1
厂家：	TEXAS INSTRUMENTS
描述：	具有 6 个 150mA 通道的 LP8863-Q1 汽车显示屏 LED 背光驱动器驱动驱动器
文件：	总92页 (文件大小：3815K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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