LPC660IMX/NOPB [TI]
四路、15V、350kHz 运算放大器 | D | 14 | -40 to 85;
| 型号： | LPC660IMX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 四路、15V、350kHz 运算放大器 | D | 14 | -40 to 85 放大器 光电二极管 运算放大器 |
| 文件： | 总26页 (文件大小：951K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LPC660
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SNOS554D –MAY 1998–REVISED MARCH 2013
LPC660 Low Power CMOS Quad Operational Amplifier
Check for Samples: LPC660
1
FEATURES
DESCRIPTION
The LPC660 CMOS Quad operational amplifier is
ideal for operation from a single supply. It features a
wide range of operating voltages from +5V to +15V
and features rail-to-rail output swing in addition to an
input common-mode range that includes ground.
Performance limitations that have plagued CMOS
amplifiers in the past are not a problem with this
design. Input VOS, drift, and broadband noise as well
as voltage gain (into 100 kΩ and 5 kΩ) are all equal
to or better than widely accepted bipolar equivalents,
while the power supply requirement is typically less
than 1 mW.
2
•
•
•
•
•
•
•
•
•
•
•
•
Rail-to-rail output swing
Micropower operation: (1 mW)
Specified for 100 kΩ and 5 kΩ loads
High voltage gain: 120 dB
Low input offset voltage: 3 mV
Low offset voltage drift: 1.3 μV/°C
Ultra low input bias current: 2 fA
Input common-mode includes V−
Operation range from +5V to +15V
Low distortion: 0.01% at 1 kHz
Slew rate: 0.11 V/μs
This chip is built with National's advanced Double-
Poly Silicon-Gate CMOS process.
Full military temp. range available
See the LPC662 datasheet for a Dual CMOS
operational amplifier and LPC661 datasheet for a
single CMOS operational amplifier with these same
features.
APPLICATIONS
•
•
•
•
•
•
•
High-impedance buffer
Precision current-to-voltage converter
Long-term integrator
High-impedance preamplifier
Active filter
Sample-and-Hold circuit
Peak detector
Application Circuit
Oscillator frequency is determined by R1, R2, C1, and C2:
fOSC = 1/2πRC
where R = R1 = R2 and C = C1 = C2.
Figure 1. Sine-Wave Oscillator
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2013, Texas Instruments Incorporated
LPC660
SNOS554D –MAY 1998–REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)
Absolute Maximum Ratings
Differential Input Voltage
Supply Voltage (V+ − V−)
Output Short Circuit to V+
Output Short Circuit to V−
Lead Temperature
±Supply Voltage
16V
(2)
(3)
(Soldering, 10 sec.)
260°C
−65°C to +150°C
150°C
Storage Temp. Range
(4)
Junction Temperature
ESD Rating
(C = 100 pF, R = 1.5 kΩ)
Power Dissipation
1000V
(4)
Current at Input Pin
±5 mA
±18 mA
(V+) + 0.3V, (V−) − 0.3V
Current at Output Pin
Voltage at Input/Output Pin
Current at Power Supply Pin
35 mA
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test
conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed.
(2) Do not connect output to V+when V+ is greater than 13V or reliability may be adversely affected.
(3) Applies to both single supply and split supply operation. Continuous short circuit operation at elevated ambient temperature and/or
multiple Op Amp shorts can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30
mA over long term may adversely affect reliability.
(4) The maximum power dissipation is a function of TJ(max), θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(max)–TA)θJA
.
(1)
Operating Ratings
Temperature Range
LPC660AM
−55°C ≤ TJ ≤ +125°C
−40°C ≤ TJ ≤ +85°C
−40°C ≤ TJ ≤ +85°C
LPC660AI
LPC660I
Supply Range
Power Dissipation
4.75V to 15.5V
(2)
(3)
Thermal Resistance (θJA),
14-Pin Ceramic DIP
14-Pin Molded DIP
90°C/W
85°C/W
115°C/W
90°C/W
14-Pin SOIC
14-Pin Side Brazed Ceramic DIP
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test
conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed.
(2) For operating at elevated temperatures, the device must be derated based on the thermal resistance θJA with PD = (TJ–TA)/θJA
.
(3) All numbers apply for packages soldered directly into a PC board.
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DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V,
V− = 0V, VCM = 1.5V, VO = 2.5V, and RL > 1M unless otherwise specified.
LPC660AM
LPC660AI
LPC660I
Parameter
Conditions
Typ
LPC660AMJ/883
Units
(1) (2)
(1)
(1)
Limit
Limit
Limit
Input Offset Voltage
1
3
3
6
mV
3.5
3.3
6.3
max
Input Offset Voltage
Average Drift
1.3
μV/°C
Input Bias Current
Input Offset Current
Input Resistance
0.002
20
100
20
pA
max
pA
4
2
4
2
0.001
100
max
Tera Ω
dB
>1
83
Common Mode Rejection
Ratio
0V ≤ VCM ≤ 12.0V
V+ = 15V
5V ≤ V+ ≤ 15V
70
68
70
68
63
61
min
dB
Positive Power Supply
Rejection Ratio
83
94
70
70
63
68
68
61
min
dB
Negative Power Supply
Rejection Ratio
0V ≤ V− ≤ −10V
84
84
74
82
83
73
min
V
Input Common Mode
Voltage Range
V+ = 5V & 15V
−0.4
V+ − 1.9
1000
500
−0.1
0
−0.1
0
−0.1
0
For CMRR > 50 dB
max
V
V+ − 2.3
V+ − 2.6
400
250
180
70
V+ − 2.3
V+ − 2.5
400
300
180
120
200
160
100
60
V+ − 2.3
V+ − 2.5
300
200
90
min
V/mV
min
V/mV
min
V/mV
min
V/mV
min
(3)
Large Signal
Voltage Gain
RL = 100 kΩ
Sourcing
Sinking
70
(3)
RL = 5 kΩ
1000
250
200
150
100
35
100
80
Sourcing
Sinking
50
40
(1) Limits are guaranteed by testing or correlation.
(2) A military RETS electrical test specification is available on request. At the time of printing, the LPC660AMJ/883 RETS specification
complied fully with the boldface limits in this column. The LPC660AMJ/883 may also be procured to a Standard Military Drawing
specification.
(3) V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 2.5V ≤ VO ≤ 7.5V.
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DC Electrical Characteristics (continued)
Unless otherwise specified, all limits guaranteed for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V,
V− = 0V, VCM = 1.5V, VO = 2.5V, and RL > 1M unless otherwise specified.
LPC660AM
LPC660AI
LPC660I
Parameter
Conditions
Typ
4.987
0.004
4.940
0.040
14.970
0.007
14.840
0.110
22
LPC660AMJ/883
Units
(1) (2)
(1)
(1)
Limit
Limit
Limit
Output Swing
V+ = 5V
4.970
4.950
0.030
0.050
4.850
4.750
0.150
0.250
14.920
14.880
0.030
0.050
14.680
14.600
0.220
0.300
16
4.970
4.950
0.030
0.050
4.850
4.750
0.150
0.250
14.920
14.880
0.030
0.050
14.680
14.600
0.220
0.300
16
4.940
4.910
0.060
0.090
4.750
4.650
0.250
0.350
14.880
14.820
0.060
0.090
14.580
14.480
0.320
0.400
13
V
min
V
RL = 100 kΩ to V+/2
max
V
V+ = 5V
RL = 5 kΩ to V+/2
min
V
max
V
V+ = 15V
RL = 100 kΩ to V+/2
min
V
max
V
V+ = 15V
RL = 5 kΩ to V+/2
min
V
max
mA
min
mA
min
mA
min
mA
min
μA
Output Current
V+ = 5V
Sourcing, VO = 0V
Sinking, VO = 5V
Sourcing, VO = 0V
12
14
11
21
16
16
13
12
14
11
Output Current
V+ = 15V
40
19
28
23
19
25
20
Sinking, VO = 13V
39
19
28
23
(4)
19
24
19
Supply Current
All Four Amplifiers
VO = 1.5V
160
200
200
240
250
230
270
max
(4) Do not connect output to V+when V+ is greater than 13V or reliability may be adversely affected.
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AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V,
V− = 0V, VCM = 1.5V, VO = 2.5, and RL > 1M unless otherwise specified.
LPC660AM
LPC660AI LPC660I
Parameter
Conditions
Typ
LPC660AMJ/883
Units
(1) (2)
(1)
(1)
Limit
Limit
0.07
0.05
Limit
0.05
0.03
(3)
Slew Rate
0.11
0.07
V/μs
min
0.04
Gain-Bandwidth Product
Phase Margin
0.35
50
MHz
Deg
dB
Gain Margin
17
(4)
Amp-to-Amp Isolation
Input Referred Voltage Noise
Input Referred Current Noise
Total Harmonic Distortion
130
42
dB
F = 1 kHz
F = 1 kHz
nV/√Hz
pA/√Hz
%
0.0002
0.01
F = 1 kHz, AV = −10
RL = 100 kΩ, VO = 8 VPP
(1) Limits are guaranteed by testing or correlation.
(2) A military RETS electrical test specification is available on request. At the time of printing, the LPC660AMJ/883 RETS specification
complied fully with the boldface limits in this column. The LPC660AMJ/883 may also be procured to a Standard Military Drawing
specification.
(3) V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates.
(4) Input referred. V+ = 15V and RL = 100 kΩ connected to V+/2. Each amp excited in turn with 1 kHz to produce VO = 13 VPP
.
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Typical Performance Characteristics
VS = ±7.5V, TA = 25°C unless otherwise specified
Supply Current
vs.
Supply Voltage
Input Bias Current
vs.
Temperature
Figure 2.
Figure 3.
Common-Mode Voltage Range
vs.
Temperature
Output Characteristics Current Sinking
Figure 4.
Figure 5.
Input Voltage Noise
vs.
Output Characteristics Current Sourcing
Frequency
Figure 6.
Figure 7.
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Typical Performance Characteristics (continued)
VS = ±7.5V, TA = 25°C unless otherwise specified
Crosstalk Rejection
CMRR
vs.
Frequency
vs.
Frequency
Figure 8.
Figure 9.
CMRR
vs.
Temperature
Power Supply Rejection Ratio
vs.
Frequency
Figure 10.
Figure 11.
Open-Loop Voltage Gain
vs.
Temperature
Open-Loop Frequency Response
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
VS = ±7.5V, TA = 25°C unless otherwise specified
Gain and Phase Responses
Gain and Phase Responses
vs.
vs.
Load Capacitance
Temperature
Figure 14.
Figure 15.
Non-Inverting Slew Rate
vs.
Gain Error (VOSvs. VOUT
)
Temperature
Figure 16.
Figure 17.
Inverting Slew Rate
vs.
Large-Signal Pulse Non-Inverting Response
(AV = +1)
Temperature
Figure 18.
Figure 19.
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Typical Performance Characteristics (continued)
VS = ±7.5V, TA = 25°C unless otherwise specified
Non-Inverting Small Signal Pulse Response
(AV = +1)
Inverting Large-Signal Pulse Response
Figure 20.
Figure 21.
Inverting Small-Signal Pulse Response
Stability vs. Capacitive Load
Note: Avoid resistive loads of less than 500Ω, as they may cause
instability.
Figure 22.
Figure 23.
Stability vs. Capacitive Load
Figure 24.
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Application Hints
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AMPLIFIER TOPOLOGY
The topology chosen for the LPC660 is unconventional (compared to general-purpose op amps) in that the
traditional unity-gain buffer output stage is not used; instead, the output is taken directly from the output of the
integrator, to allow rail-to-rail output swing. Since the buffer traditionally delivers the power to the load, while
maintaining high op amp gain and stability, and must withstand shorts to either rail, these tasks now fall to the
integrator.
As a result of these demands, the integrator is a compound affair with an embedded gain stage that is doubly fed
forward (via Cf and Cff) by a dedicated unity-gain compensation driver. In addition, the output portion of the
integrator is a push-pull configuration for delivering heavy loads. While sinking current the whole amplifier path
consists of three gain stages with one stage fed forward, whereas while sourcing the path contains four gain
stages with two fed forward.
Figure 25. LPC660 Circuit Topology (Each Amplifier)
The large signal voltage gain while sourcing is comparable to traditional bipolar op amps, for load resistance of at
least 5 kΩ. The gain while sinking is higher than most CMOS op amps, due to the additional gain stage;
however, when driving load resistance of 5 kΩ or less, the gain will be reduced as indicated in the Electrical
Characteristics. The op amp can drive load resistance as low as 500Ω without instability.
COMPENSATING INPUT CAPACITANCE
Refer to the LMC660 or LMC662 datasheets to determine whether or not a feedback capacitor will be necessary
for compensation and what the value of that capacitor would be.
CAPACITIVE LOAD TOLERANCE
Like many other op amps, the LPC660 may oscillate when its applied load appears capacitive. The threshold of
oscillation varies both with load and circuit gain. The configuration most sensitive to oscillation is a unity-gain
follower. See the Typical Performance Characteristics.
The load capacitance interacts with the op amp's output resistance to create an additional pole. If this pole
frequency is sufficiently low, it will degrade the op amp's phase margin so that the amplifier is no longer stable at
low gains. The addition of a small resistor (50Ω to 100Ω) in series with the op amp's output, and a capacitor (5
pF to 10 pF) from inverting input to output pins, returns the phase margin to a safe value without interfering with
lower-frequency circuit operation. Thus, larger values of capacitance can be tolerated without oscillation. Note
that in all cases, the output will ring heavily when the load capacitance is near the threshold for oscillation.
Figure 26. Rx, Cx Improve Capacitive Load Tolerance
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Capacitive load driving capability is enhanced by using a pull up resistor to V+ (Figure 27). Typically a pull up
resistor conducting 50 μA or more will significantly improve capacitive load responses. The value of the pull up
resistor must be determined based on the current sinking capability of the amplifier with respect to the desired
output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical
Characteristics).
Figure 27. Compensating for LargeCapacitive Loads with A Pull Up Resistor
PRINTED-CIRCUIT-BOARD LAYOUT
FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires
special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the LPC660,
typically less than 0.04 pA, it is essential to have an excellent layout. Fortunately, the techniques for obtaining
low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though
it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination,
the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LPC660's inputs
and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp's
inputs. See Figure 28. To have a significant effect, guard rings should be placed on both the top and bottom of
the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier
inputs, since no leakage current can flow between two points at the same potential. For example, a PC board
trace-to-pad resistance of 1012 ohms, which is normally considered a very large resistance, could leak 5 pA if the
trace were a 5V bus adjacent to the pad of an input. This would cause a 100 times degradation from the
LPC660's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a resistance
of 1011 ohms would cause only 0.05 pA of leakage current, or perhaps a minor (2:1) degradation of the
amplifier's performance. See Figure 29a, Figure 30b, Figure 31c for typical connections of guard rings for
standard op-amp configurations. If both inputs are active and at high impedance, the guard can be tied to ground
and still provide some protection; see Figure 32d.
Figure 28. Example of Guard Ring in P.C. Board Layout using the LPC660
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Figure 29. (a) Inverting Amplifier
Figure 30. (b) Non-Inverting Amplifier
Figure 31. (c) Follower
Figure 32. (d) Howland Current Pump
The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few
circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the
amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an
excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but
the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 33.
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(Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.)
Figure 33. Air Wiring
BIAS CURRENT TESTING
The test method of Figure 34 is appropriate for bench-testing bias current with reasonable accuracy. To
understand its operation, first close switch S2 momentarily. When S2 is opened, then
(1)
Figure 34. Simple Input Bias Current Test Circuit
A suitable capacitor for C2 would be a 5 pF or 10 pF silver mica, NPO ceramic, or air-dielectric. When
determining the magnitude of I−, the leakage of the capacitor and socket must be taken into account. Switch S2
should be left shorted most of the time, or else the dielectric absorption of the capacitor C2 could cause errors.
Similarly, if S1 is shorted momentarily (while leaving S2 shorted)
(2)
where Cx is the stray capacitance at the + input.
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Typical Single-Supply Applications — (V+ = 5.0 VDC)
Figure 35. Photodiode Current-to-Voltage Converter
Note: A 5V bias on the photodiode can cut its capacitance by a factor of 2 or 3, leading to improved response and
lower noise. However, this bias on the photodiode will cause photodiode leakage (also known as its dark current).
Figure 36. Micropower Current Source
Note: (Upper limit of output range dictated by input common-mode range; lower limit dictated by minimum current
requirement of LM385.)
Figure 37. Low-Leakage Sample-and-Hold
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Figure 38. Instrumentation Amplifier
For good CMRR over temperature, low drift resistors should be used. Matching of R3 to R6 and R4 to R7 affects
CMRR. Gain may be adjusted through R2. CMRR may be adjusted through R7.
Figure 39. Sine-Wave Oscillator
Oscillator frequency is determined by R1, R2, C1, and C2:
fOSC = 1/2πRC
where R = R1 = R2 and C = C1 = C2.
Figure 40. 1 Hz Square-Wave Oscillator
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This circuit, as shown, oscillates at 2.0 kHz with a peak-to-peak output swing of 4.5V
Figure 41. Power Amplifier
Figure 42. 10 Hz Bandpass Filter
fO = 10 Hz
Q = 2.1
Gain = −8.8
Figure 43. 10 Hz High-Pass Filter (2 dB Dip)
fc = 10 Hz
d = 0.895
Gain = 1
Figure 44. 1 Hz Low-Pass Filter (Maximally Flat, Dual Supply Only)
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Figure 45. High Gain Amplifier with Offset Voltage Reduction
Gain = −46.8
Output offset voltage reduced to the level of the input offset voltage of the bottom amplifier (typically 1 mV), referred
to VBIAS
.
Connection Diagram
Top View
Figure 46. 14-Pin SOIC Package
See Package Number D0014A
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REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 17
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LPC660AIM/NOPB
LPC660AIMX/NOPB
LPC660IM/NOPB
LPC660IMX/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
D
D
14
14
14
14
55
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
LPC660AIM
2500 RoHS & Green
55 RoHS & Green
2500 RoHS & Green
SN
SN
SN
LPC660AIM
LPC660IM
LPC660IM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LPC660AIMX/NOPB
LPC660IMX/NOPB
SOIC
SOIC
D
D
14
14
2500
2500
330.0
330.0
16.4
16.4
6.5
6.5
9.35
9.35
2.3
2.3
8.0
8.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LPC660AIMX/NOPB
LPC660IMX/NOPB
SOIC
SOIC
D
D
14
14
2500
2500
356.0
367.0
356.0
367.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LPC660AIM/NOPB
LPC660AIM/NOPB
LPC660IM/NOPB
LPC660IM/NOPB
D
D
D
D
SOIC
SOIC
SOIC
SOIC
14
14
14
14
55
55
55
55
495
495
495
495
8
8
8
8
4064
4064
4064
4064
3.05
3.05
3.05
3.05
Pack Materials-Page 3
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相关型号：
LPC661AIMX
IC OP-AMP, 3300 uV OFFSET-MAX, 0.35 MHz BAND WIDTH, PDSO8, PLASTIC, SOP-8, Operational Amplifier
NSC
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