LPC662IM/NOPB [TI]
双路、15V、350kHz 运算放大器 | D | 8 | -40 to 85;
| 型号： | LPC662IM/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路、15V、350kHz 运算放大器 | D | 8 | -40 to 85 放大器 光电二极管 运算放大器 |
| 文件： | 总22页 (文件大小：679K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Texas Instruments.
Search http://www.ti.com/ for the latest technical
information and details on our current products and services.
August 2000
LPC662
Low Power CMOS Dual Operational Amplifier
n Long-term integrator
General Description
n High-impedance preamplifier
The LPC662 CMOS Dual operational amplifier is ideal for
n Active filter
operation from a single supply. It features a wide range of
operating voltage from +5V to +15V, rail-to-rail output swing
in addition to an input common-mode range that includes
n Sample-and-Hold circuit
n Peak detector
ground. Performance limitations that have plagued CMOS
amplifiers in the past are not a problem with this design.
Input VOS, drift, and broadband noise as well as voltage gain
(into 100 kΩ and 5 kΩ) are all equal to or better than widely
accepted bipolar equivalents, while the power supply
requirement is typically less than 0.5 mW.
Features
n Rail-to-rail output swing
<
n Micropower operation ( 0.5 mW)
n Specified for 100 kΩ and 5 kΩ loads
n High voltage gain
n Low input offset voltage
n Low offset voltage drift
n Ultra low input bias current
n Input common-mode includes GND
n Operating range from +5V to +15V
n Low distortion
120 dB
3 mV
1.3 µV/˚C
2 fA
This chip is built with National’s advanced Double-Poly
Silicon-Gate CMOS process.
See the LPC660 datasheet for a Quad CMOS operational
amplifier and LPC661 for
a single CMOS operational
amplifier with these same features.
0.01% at 1 kHz
0.11 V/µs
Applications
n High-impedance buffer
n Precision current-to-voltage converter
n Slew rate
n Full military temperature range available
Application Circuit
Howland Current Pump
DS010548-23
© 2001 National Semiconductor Corporation
DS010548
www.national.com
Absolute Maximum Ratings (Note 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Current at Power Supply Pin
Voltage at Input/Output Pin
35 mA
(V+) + 0.3V, (V−) −0.3V
Operating Ratings (Note 3)
±
Differential Input Voltage
Supply Voltage (V+ − V−)
Output Short Circuit to V+
Output Short Circuit to V−
Lead Temperature
Supply Voltage
16V
Temperature Range
LPC662AMJ/883
LPC662AM
−55˚C ≤ TJ ≤ +125˚C
−55˚C ≤ TJ ≤ +125˚C
−40˚C ≤ TJ ≤ +85˚C
−40˚C ≤ TJ ≤ +85˚C
4.75V to 15.5V
(Note 11)
(Note 1)
LPC662AI
LPC662I
(Soldering, 10 sec.)
Storage Temp. Range
Junction Temperature
ESD Rating
260˚C
Supply Range
−65˚C to +150˚C
150˚C
Power Dissipation
Thermal Resistance (θJA) (Note 10)
8-Pin Ceramic DIP
8-Pin Molded DIP
8-Pin SO
(Note 9)
100˚C/W
101˚C/W
165˚C/W
100˚C/W
(C = 100 pF, R = 1.5 kΩ)
Power Dissipation
1000V
(Note 2)
±
Current at Input Pin
Current at Output Pin
5 mA
8-Pin Side Brazed Ceramic DIP
±
18 mA
DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25˚C. Boldface limits apply at the temperature extremes. V+ = 5V, V−
>
= 0V, VCM = 1.5V, VO = 2.5V and RL 1M unless otherwise specified.
LPC662AM
LPC662AI
Limit
LPC662I
Limit
Parameter
Conditions
Typ
LPC662AMJ/883
Units
Limit
(Note 4)
(Note 4)
(Notes 4, 8)
Input Offset Voltage
1
3
3
6
mV
max
3.5
3.3
6.3
Input Offset Voltage
Average Drift
1.3
µV/˚C
Input Bias Current
0.002
0.001
20
100
20
pA
max
pA
4
2
4
2
Input Offset Current
100
max
Tera Ω
dB
>
Input Resistance
Common Mode
1
0V ≤ VCM ≤ 12.0V
V+ = 15V
5V ≤ V+ ≤ 15V
83
70
68
70
68
63
61
Rejection Ratio
min
dB
Positive Power Supply
Rejection Ratio
83
70
70
63
VO = 2.5V
0V ≤ V− ≤ −10V
68
68
61
min
dB
Negative Power Supply
Rejection Ratio
94
84
84
74
82
83
73
min
V
Input Common-Mode
Voltage Range
V+ = 5V and 15V
−0.4
V+ − 1.9
1000
500
−0.1
0
−0.1
0
−0.1
0
For CMRR ≥ 50 dB
max
V
V+ − 2.3
V+ − 2.6
400
250
180
70
V+ − 2.3
V+ − 2.5
400
300
180
120
200
160
100
60
V+ − 2.3
V+ − 2.5
300
200
90
min
V/mV
min
V/mV
min
V/mV
min
V/mV
min
Large Signal
Voltage Gain
RL = 100 kΩ (Note 5)
Sourcing
Sinking
70
RL = 5 kΩ (Note 5)
Sourcing
1000
250
200
150
100
35
100
80
Sinking
50
40
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2
DC Electrical Characteristics (Continued)
Unless otherwise specified, all limits guaranteed for TJ = 25˚C. Boldface limits apply at the temperature extremes. V+ = 5V, V−
>
= 0V, VCM = 1.5V, VO = 2.5V and RL 1M unless otherwise specified.
LPC662AM
LPC662AMJ/883
Limit
(Notes 4, 8)
4.970
4.950
0.030
0.050
4.850
4.750
0.150
0.250
14.920
14.880
0.030
0.050
14.680
14.600
0.220
0.300
16
LPC662AI
Limit
LPC662I
Limit
Parameter
Conditions
Typ
Units
(Note 4)
(Note 4)
Output Swing
V+ = 5V
RL = 100 kΩ to V+/2
4.987
0.004
4.940
0.040
14.970
0.007
14.840
0.110
22
4.970
4.950
0.030
0.050
4.850
4.750
0.150
0.250
14.920
14.880
0.030
0.050
14.680
14.600
0.220
0.300
16
4.940
4.910
0.060
0.090
4.750
4.650
0.250
0.350
14.880
14.820
0.060
0.090
14.580
14.480
0.320
0.400
13
V
min
V
max
V
V+ = 5V
RL = 5 kΩ to V+/2
min
V
max
V
V+ = 15V
RL = 100 kΩ to V+/2
min
V
max
V
V+ = 15V
RL = 5 kΩ to V+/2
min
V
max
mA
min
mA
min
mA
min
mA
min
µA
Output Current
V+ = 5V
Sourcing, VO = 0V
Sinking, VO = 5V
Sourcing, VO = 0V
12
14
11
21
16
16
13
12
14
11
Output Current
V+ = 15V
40
19
28
23
19
25
20
Sinking, VO = 13V
(Note 11)
39
19
28
23
19
24
19
Supply Current
Both Amplifiers
VO = 1.5V
86
120
120
140
145
140
160
max
3
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AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25˚C. Boldface limits apply at the temperature extremes. V+ = 5V, V−
>
= 0V, VCM = 1.5V, VO = 2.5V and RL 1M unless otherwise specified.
LPC662AM
LPC662AMJ/883
Limit
LPC662AI LPC662I
Parameter
Conditions
Typ
Limit
Limit
Units
(Note 4)
(Note 4)
(Notes 4, 8)
0.07
Slew Rate
(Note 6)
0.11
0.07
0.05
V/µs
min
MHz
Deg
dB
0.04
0.05
0.03
Gain-Bandwidth Product
Phase Margin
0.35
50
Gain Margin
17
Amp-to-Amp Isolation
(Note 7)
130
42
dB
Input Referred Voltage Noise F = 1 kHz
Input Referred Current Noise F = 1 kHz
0.0002
0.01
Total Harmonic Distortion
F = 1 kHz, AV = −10, V+ = 15V
%
RL = 100 kΩ, VO = 8 VPP
Note 1: Applies to both single supply and split supply operation. Continuous short circuit operation at elevated ambient temperature and/or multiple Op Amp shorts
±
can result in exceeding the maximum allowed junction temperature of 150˚C. Output currents in excess of 30 mA over long term may adversely affect reliability.
Note 2: The maximum power dissipation is a function of T , θ , and T . The maximum allowable power dissipation of any ambient temperature is P = (T
J(max)
J(max) JA
A
D
− T )/θ
A
.
JA
Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed.
Note 4: Limits are guaranteed by testing or correlation.
+
Note 5: V = 15V, V
= 7.5V and R connected to 7.5V. For Sourcing tests, 7.5V ≤ V ≤ 11.5V. For Sinking tests, 2.5V ≤ V ≤ 7.5V.
L O O
CM
+
Note 6: V = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates.
+
+
Note 7: Input referred. V = 15V and R = 100 kΩ connected to V /2. Each amp excited in turn with 1 kHz to produce V = 13 V .
PP
L
O
Note 8: A military RETS electrical test specification is available on request. At the time of printing, the LPC662AMJ/883 RETS specification complied fully with the
boldface limits in this column. The LPC662AMJ/883 may also be procured to a Standard Military Drawing specification.
Note 9: For operating at elevated temperatures the device must be derated based on the thermal resistance θ with P = (T − T )/θ .
JA
JA
D
J
A
Note 10: All numbers apply for packages soldered directly into a PC board.
+
+
Note 11: Do not connect output to V when V is greater than 13V or reliability may be adversely affected.
www.national.com
4
±
7.5V, TA = 25˚C unless otherwise specified
Typical Performance Characteristics VS
=
Supply Current vs
Supply Voltage
Input Bias Current
vs Temperature
DS010548-28
DS010548-29
Input Common-Mode
Voltage Range vs
Temperature
Output Characteristics
Current Sinking
DS010548-30
DS010548-31
Output Characteristics
Current Sourcing
Input Voltage Noise
vs Frequency
DS010548-32
DS010548-33
5
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±
7.5V, TA = 25˚C unless otherwise specified (Continued)
Typical Performance Characteristics VS
=
Crosstalk Rejection
vs Frequency
CMRR vs Frequency
DS010548-35
DS010548-34
CMRR vs Temperature
Open-Loop Voltage Gain
vs Temperature
DS010548-36
DS010548-38
Open-Loop
Frequency Response
Gain and Phase Responses
vs Load Capacitance
DS010548-39
DS010548-40
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6
±
7.5V, TA = 25˚C unless otherwise specified (Continued)
Typical Performance Characteristics VS
=
Gain and Phase Responses
vs Temperature
Gain Error
(VOSvs VOUT
)
DS010548-41
DS010548-42
Non-Inverting Slew Rate
vs Temperature
Inverting Slew Rate
vs Temperature
DS010548-43
DS010548-44
Large-Signal Pulse
Non-Inverting Response
(AV = +1)
Non-Inverting Small
Signal Pulse Response
(AV = +1)
DS010548-45
DS010548-46
7
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±
7.5V, TA = 25˚C unless otherwise specified (Continued)
Typical Performance Characteristics VS
=
Inverting Large-Signal
Pulse Response
Inverting Small-Signal
Pulse Response
DS010548-47
DS010548-48
Power Supply Rejection
Ratio vs Frequency
DS010548-37
Stability vs Capacitive Load
Stability vs Capacitive Load
DS010548-4
DS010548-5
Note: Avoid resistive loads of less than 500Ω, as they may cause
instability.
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8
Application Hints
AMPLIFIER TOPOLOGY
tolerated without oscillation. Note that in all cases, the output
will ring heavily when the load capacitance is near the
threshold for oscillation.
The topology chosen for the LPC662 is unconventional
(compared to general-purpose op amps) in that the
traditional unity-gain buffer output stage is not used; instead,
the output is taken directly from the output of the integrator,
to allow rail-to-rail output swing. Since the buffer traditionally
delivers the power to the load, while maintaining high op
amp gain and stability, and must withstand shorts to either
rail, these tasks now fall to the integrator.
As a result of these demands, the integrator is a compound
affair with an embedded gain stage that is doubly fed forward
(via Cf and Cff) by a dedicated unity-gain compensation
driver. In addition, the output portion of the integrator is a
push-pull configuration for delivering heavy loads. While
sinking current the whole amplifier path consists of three
gain stages with one stage fed forward, whereas while
sourcing the path contains four gain stages with two fed
forward.
DS010548-7
FIGURE 2. Rx, Cx Improve Capacitive Load Tolerance
Capacitive load driving capability is enhanced by using a
pull up resistor to V+ Figure 3. Typically a pull up resistor
conducting 50 µA or more will significantly improve
capacitive load responses. The value of the pull up resistor
must be determined based on the current sinking capability
of the amplifier with respect to the desired output swing.
Open loop gain of the amplifier can also be affected by the
pull up resistor (see Electrical Characteristics).
DS010548-6
FIGURE 1. LPC662 Circuit Topology (Each Amplifier)
The large signal voltage gain while sourcing is comparable
to traditional bipolar op amps for load resistance of at least
5 kΩ. The gain while sinking is higher than most CMOS op
amps, due to the additional gain stage; however, when
driving load resistance of 5 kΩ or less, the gain will be
reduced as indicated in the Electrical Characteristics. The op
amp can drive load resistance as low as 500Ω without
instability.
DS010548-26
FIGURE 3. Compensating for Large
Capacitive Loads with A Pull Up Resistor
PRINTED-CIRCUIT-BOARD LAYOUT
FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate
with less than 1000 pA of leakage current requires special
layout of the PC board. When one wishes to take advantage
of the ultra-low bias current of the LPC662, typically less
than 0.04 pA, it is essential to have an excellent layout.
Fortunately, the techniques for obtaining low leakages are
quite simple. First, the user must not ignore the surface
leakage of the PC board, even though it may sometimes
appear acceptably low, because under conditions of high
humidity or dust or contamination, the surface leakage will
be appreciable.
COMPENSATING INPUT CAPACITANCE
Refer to the LMC660 or LMC662 datasheets to determine
whether or not a feedback capacitor will be necessary for
compensation and what the value of that capacitor would be.
CAPACITIVE LOAD TOLERANCE
Like many other op amps, the LPC662 may oscillate when
its applied load appears capacitive. The threshold of
oscillation varies both with load and circuit gain. The
configuration most sensitive to oscillation is a unity-gain
follower. See the Typical Performance Characteristics.
To minimize the effect of any surface leakage, lay out a ring
of foil completely surrounding the LPC662’s inputs and the
terminals of capacitors, diodes, conductors, resistors, relay
terminals, etc. connected to the op-amp’s inputs. See Figure
4. To have a significant effect, guard rings should be placed
on both the top and bottom of the PC board. This PC foil
must then be connected to a voltage which is at the same
voltage as the amplifier inputs, since no leakage current can
flow between two points at the same potential. For example,
a PC board trace-to-pad resistance of 1012 ohms, which is
normally considered a very large resistance, could leak 5 pA
if the trace were a 5V bus adjacent to the pad of an input.
The load capacitance interacts with the op amp’s output
resistance to create an additional pole. If this pole frequency
is sufficiently low, it will degrade the op amp’s phase margin
so that the amplifier is no longer stable at low gains. The
addition of a small resistor (50Ω to 100Ω) in series with the
op amp’s output, and a capacitor (5 pF to 10 pF) from
inverting input to output pins, returns the phase margin to a
safe value without interfering with lower-frequency circuit
operation. Thus, larger values of capacitance can be
9
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performance. See Figure 5a, Figure 5b, Figure 5c for typical
connections of guard rings for standard op-amp
configurations. If both inputs are active and at high
impedance, the guard can be tied to ground and still provide
some protection; see Figure 5d.
Application Hints (Continued)
This would cause
a 100 times degradation from the
LPC662’s actual performance. However, if a guard ring is
held within 5 mV of the inputs, then even a resistance of
1011 ohms would cause only 0.05 pA of leakage current, or
perhaps
a minor (2:1) degradation of the amplifier’s
DS010548-19
FIGURE 4. Example of Guard Ring in P.C. Board Layout, using the LPC660
DS010548-22
(c) Follower
DS010548-20
(a) Inverting Amplifier
DS010548-21
(b) Non-Inverting Amplifier
DS010548-23
(d) Howland Current Pump
FIGURE 5. Guard Ring Connections
The designer should be aware that when it is inappropriate
to lay out a PC board for the sake of just a few circuits, there
is another technique which is even better than a guard ring
on a PC board: Don’t insert the amplifier’s input pin into the
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10
Application Hints (Continued)
board at all, but bend it up in the air and use only air as an
insulator. Air is an excellent insulator. In this case you may
have to forego some of the advantages of PC board
construction, but the advantages are sometimes well worth
the effort of using point-to-point up-in-the-air wiring.
See Figure 6.
DS010548-25
FIGURE 7. Simple Input Bias Current Test Circuit
DS010548-24
A suitable capacitor for C2 would be a 5 pF or 10 pF silver
mica, NPO ceramic, or air-dielectric. When determining the
magnitude of I−, the leakage of the capacitor and socket
must be taken into account. Switch S2 should be left shorted
most of the time, or else the dielectric absorption of the
capacitor C2 could cause errors.
(Input pins are lifted out of PC board and soldered directly to components.
All other pins connected to PC board.)
FIGURE 6. Air Wiring
BIAS CURRENT TESTING
The test method of Figure 7 is appropriate for bench-testing
bias current with reasonable accuracy. To understand its
operation, first close switch S2 momentarily. When S2 is
opened, then
Similarly, if S1 is shorted momentarily (while leaving S2
shorted)
where Cx is the stray capacitance at the + input.
Typical Single-Supply Applications (V+ = 5.0 VDC
)
Photodiode Current-to-Voltage Converter
Micropower Current Source
DS010548-18
DS010548-17
Note: (Upper limit of output range dictated by input common-mode range;
lower limit dictated by minimum current requirement of LM385.)
Note: A 5V bias on the photodiode can cut its capacitance by a factor of 2
or 3, leading to improved response and lower noise. However, this bias on
the photodiode will cause photodiode leakage (also known as its dark
current).
11
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Typical Single-Supply Applications (V+ = 5.0 VDC) (Continued)
Low-Leakage Sample-and-Hold
DS010548-8
Instrumentation Amplifier
DS010548-9
For good CMRR over temperature, low drift resistors should be used. Matching of R3 to R6 and R4 to R7 affects CMRR. Gain may be adjusted through R2.
CMRR may be adjusted through R7.
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12
Typical Single-Supply Applications (V+ = 5.0 VDC) (Continued)
Sine-Wave Oscillator
DS010548-10
Oscillator frequency is determined by R1, R2, C1, and C2:
fOSC = 1/2πRC
where R = R1 = R2 and C = C1 = C2.
This circuit, as shown, oscillates at 2.0 kHz with a peak-to-peak output swing of 4.5V
1 Hz Square-Wave Oscillator
Power Amplifier
DS010548-12
DS010548-11
13
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Typical Single-Supply Applications (V+ = 5.0 VDC) (Continued)
10 Hz Bandpass Filter
10 Hz High-Pass Filter (2 dB Dip)
DS010548-14
f
= 10 Hz
c
DS010548-13
d = 0.895
Gain = 1
f
= 10 Hz
O
Q = 2.1
Gain = −8.8
1 Hz Low-Pass Filter
(Maximally Flat, Dual Supply Only)
High Gain Amplifier with Offset Voltage Reduction
DS010548-15
DS010548-16
Gain = −46.8
Output offset voltage reduced to the level of the input offset voltage of the
bottom amplifier (typically 1 mV), referred to V
.
BIAS
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14
Connection Diagram
8-Pin DIP/SO
DS010548-1
Top View
Ordering Information
Package
Temperature Range
NSC
Transport
Media
Drawing
Military
Industrial
8-Pin
Side Brazed
Ceramic DIP
8-Pin
LPC662AMD
D08C
Rail
LPC662AIM
or LPC662IM
LPC662AIN
or LPC662IN
M08A
N08E
J08A
Rail
Tape and Reel
Rail
Small Outline
8-Pin
Molded DIP
8-Pin
LPC662AMJ/883
Rail
Ceramic DIP
15
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Physical Dimensions inches (millimeters) unless otherwise noted
8-Pin Cavity Dual-In-Line Package (D)
Order Number LPC662AMD
NS Package Number D08C
Ceramic Dual-In-Line Package (J)
Order Number LPC662AMJ/883
NS Package Number J08A
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16
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
8-Pin Small Outline Molded Package (M)
Order Number LPC662AIM or LPC662IM
NS Package Number M08A
8-Pin Molded Dual-In-Line Package (N)
Order Number LPC662AIN or LPC662IN
NS Package Number N08E
17
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Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
National Semiconductor
Europe
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
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Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
Fax: +49 (0) 180-530 85 86
Email: europe.support@nsc.com
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Email: ap.support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
See Audio Products
Products > Analog - Amplifiers > Operational Amplifiers > Low Power > LPC662
LPC662 Product Folder
Low Power CMOS Dual Operational Amplifier
Generic P/N 662
General
Description
Package
& Models
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& Pricing
Design
Tools
Application
Notes
Features
Datasheet
Parametric Table
Channels (Channels)
Input Output Type
Bandwidth, typ (MHz)
Parametric Table
2
Maximum Supply Voltage (Volt)
Offset Voltage, Max (mV)
Input Bias Current, Temp Max (nA)
Output Current, typ (mA)
Voltage Noise, typ (nV/Hz)
Shut down
15
Vcm to V-, R-R Out
3, 6
.0040
21
.35
.11
Slew Rate, typ (Volts/usec)
Supply Current per Channel, typ (mA) .0430
42
Minimum Supply Voltage (Volt)
5
No
Special Features
-
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Std
Pack
Size
Package
Marking
Part Number
Status
$US
each
IBIS
Qty
24 Hour
rail [logo]¢2¢T
SOIC
NARROW
Full
production
MSL
LPC662A.MOD
N/A
LPC662AIM
8
1K+ $1.2500
of
LPC66
2AIM
Buy Now
95
24 Hour
rail [logo]¢2¢T
SOIC
NARROW
Full
production
MSL
LPC662IM
8
N/A
N/A
1K+ $0.8100
of
LPC66
2IM
Buy Now
95
reel [logo]¢2¢T
SOIC
NARROW
Full
production
MSL
MSL
LPC662A.MOD
LPC662AIMX
LPC662IMX
8
8
N/A
N/A
N/A
N/A
1K+ $1.2500
1K+ $0.8100
of
2500
LPC66
2AIM
Buy Now
reel [logo]¢2¢T
SOIC
NARROW
Full
production
N/A
of
2500
LPC66
2IM
tray
of
N/A
LPC662AI
MDC
Full
production
Samples
Samples
Die
LPC662A.MOD
-
-
tray
of
Full
production
Die
LPC662I MDC
N/A
N/A
wafer
jar
of
LPC662AI
MWC
Full
production
Wafer
Wafer
LPC662A.MOD
N/A
N/A
-
-
N/A
wafer
jar
of
Full
production
LPC662I MWC
N/A
N/A
General Description
The LPC662 CMOS Dual operational amplifier is ideal for operation from a single supply. It features a wide
range of operating voltage from +5V to +15V, rail-to-rail output swing in addition to an input common-mode
range that includes ground. Performance limitations that have plagued CMOS amplifiers in the past are not a
problem with this design. Input VOS, drift, and broadband noise as well as voltage gain (into 100 k and 5
k
) are all equal to or better than widely accepted bipolar equivalents, while the power supply requirement
is typically less than 0.5 mW.
This chip is built with National's advanced Double-Poly Silicon-Gate CMOS process.
See the LPC660 datasheet for a Quad CMOS operational amplifier and LPC661 for a single CMOS operational
amplifier with these same features.
Features
Rail-to-rail output swing
Micropower operation (<0.5 mW)
Specified for 100 k and 5 k loads
High voltage gain
120 dB
3 mV
Low input offset voltage
Low offset voltage drift
Ultra low input bias current
1.3 µV/°C
2 fA
Input common-mode includes GND
Operating range from +5V to +15V
Low distortion
0.01% at 1 kHz
0.11 V/µs
Slew rate
Full military temperature range available
Applications
●
●
●
●
●
●
●
High-impedance buffer
Precision current-to-voltage converter
Long-term integrator
High-impedance preamplifier
Active filter
Sample-and-Hold circuit
Peak detector
Design Tools
Title
Size in Kbytes Date
Receive via Email
Download
View Online
Amplifiers Selection Guide
software for Windows
View
12-Jun-2002
7 Kbytes
If you have trouble printing or viewing PDF file(s), see Printing Problems.
Application Notes
Title
Size in Kbytes Date
Receive via Email
Download
View Online
View Online Download Receive via Email
5-Aug-95
AN-856: A SPICE Compatible
Macromodel for CMOS Operational 105 Kbytes
Amplifiers
If you have trouble printing or viewing PDF file(s), see Printing Problems.
[Information as of 5-Aug-2002]
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