LQH44PN2R2MP0 [TI]
1.2A High Efficient Step Down Converter in 2x2mm SON Package; 1.2A高效降压转换器采用2x2mm SON封装
| 型号： | LQH44PN2R2MP0 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1.2A High Efficient Step Down Converter in 2x2mm SON Package |
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TLV62080
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SLVSAK9A –OCTOBER 2011–REVISED NOVEMBER 2011
1.2A High Efficient Step Down Converter in 2x2mm SON Package
Check for Samples: TLV62080
1
FEATURES
DESCRIPTION
DCS-ControlTM Architecture for Fast Transient
Regulation
The TLV62080 device is a synchronous step down
converter with an input voltage range of 2.5V to 5.5V.
The TLV62080 focuses on high efficient step down
conversion over a wide output current range. At
medium to heavy loads, the converter operates in
PWM mode and automatically enters Power Save
Mode operation at light load currents to maintain high
efficiency over the entire load current range.
•
•
•
•
•
•
•
•
•
2.5V to 5.5V Input Voltage Range
100% Duty Cycle for Lowest Dropout
Power Save Mode for Light Load Efficiency
Output Discharge Function
Power Good Output
To address the requirements of system power rails,
the internal compensation circuit allows a large
selection of external output capacitor values ranging
from 10µF up to 100uF effective capacitance. With its
DCS-ControlTM architecture excellent load transient
performance and output voltage regulation accuracy
is achieved. The device is available in 2mm x 2mm
SON package with Thermal PAD.
Thermal Shutdown
Available in 2x2mm 8-Pin SON Package
For Improved Features Set, See TPS62080
APPLICATIONS
•
•
•
Battery Powered Portable Devices
Point of Load Regulators
System Power Rail Voltage Conversion
POWER GOOD
180k
TLV62080
2.5V...5.5V
VIN
VIN
EN
PG
1mH
VOUT
SW
10µF
22µF
R1
GND
GND
VOS
FB
R2
Figure 1. Typical Application of TLV62080
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TLV62080
SLVSAK9A –OCTOBER 2011–REVISED NOVEMBER 2011
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Table 1. ORDERING INFORMATION
TA
PACKAGE MARKING
PACKAGE
PART NUMBER(1)
TLV62080DSG
–40°C to 85°C
RAU
8-Pin QFN
(1) For detailed ordering information please check the PACKAGE OPTION ADDENDUM section at the end of this datasheet.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE
UNIT
V
Voltage range at VIN, PG, VOS(2)
Voltage range at SW(2)(3)
Voltage range at FB(2)
–0.3 to 7
–0.3 to (VIN + 0.3V)
–0.3 to 3.6
–0.3 to (VIN + 0.3V)
2
V
V
Voltage range at EN(2)
V
ESD rating, Human Body Model
ESD rating, Charged Device Model
Continuous total power dissipation
Operating junction temperature range, TJ
Operating ambient temperature range, TA
Storage temperature range, Tstg
kV
V
500
See Dissipation Rating Table
–40 to 125
–40 to 85
–65 to 150
°C
°C
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) During operation, device switching
THERMAL INFORMATION
TLV62080
THERMAL METRIC(1)
UNITS
DSG (8 PINS)
65.1
θJA
Junction-to-ambient thermal resistance
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
100.7
135.7
2.3
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
45.1
θJCbot
8.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS(1)
MIN TYP
2.5
MAX UNIT
VIN
VOUT
TA
Input voltage range
5.5
4.0
85
V
V
Output voltage range
0.5
Operating ambient temperature
Operating junction temperature
–40
°C
°C
TJ
–40
125
(1) Refer to the APPLICATION INFORMATION section for further information.
2
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ELECTRICAL CHARACTERISTICS
Over recommended free-air temperature range, TA = -40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted),
VIN=3.6V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY
VIN
Input voltage range
2.5
5.5
V
uA
µA
V
IQ
Quiescent current into VIN
Shutdown current into VIN
Under voltage lock out
IOUT = 0mA, Device not switching
EN = LOW
30
ISD
1
Input voltage falling
1.8
120
150
20
2.0
VUVLO
TJSD
Under voltage lock out hysteresis
Thermal shut down
Rising above VUVLO
mV
°C
°C
Temperature rising
Thermal shutdown hysteresis
Temperature falling below TJSD
LOGIC INTERFACE (EN)
VIH
VIL
High level input voltage
2.5V ≤ VIN ≤ 5.5V
2.5V ≤ VIN ≤ 5.5V
1
V
V
Low level input voltage
Input leakage current
0.4
0.5
ILKG
0.01
µA
POWER GOOD
VPG Power good threshold
VOUT falling referenced to VOUT nominal
–15
–10
–5
%
%
V
Power good hysteresis
Low level voltage
5
VIL
Isink = 500 µA
0.3
0.1
IPG,LKG PG Leakage current
VPG = 5.0 V
0.01
µA
OUTPUT
VOUT
VFB
IFB
Output voltage range TLV62080
0.5
4.0
V
V
Feedback regulation voltage
Feedback input bias current
Output discharge resistor
V
IN ≥ 2.5V and VIN ≥ VOUT + 1V
0.438
0.45 0.462
VFB = 0.45 V
10
1
100
nA
kΩ
mΩ
mΩ
A
RDIS
EN = LOW, VOUT = 1.8 V
ISW = 500 mA
High side FET on-resistance
Low side FET on-resistance
High side FET switch current limit
120
90
RDS(on)
ILIM
ISW = 500 mA
Rising inductor current
1.6
2.8
4
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DEVICE INFORMATION
QFN
8 PIN 2X2 mm
EN
GND
GND
FB
1
2
3
4
8
7
6
5
VIN
SW
PG
VOS
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
VIN
NO.
8
PWR Power Supply Voltage Input.
IN Device Enable Logic Input.
Logic HIGH enables the device, logic LOW disables the device and turns it into shutdown.
PWR Power and Signal Ground.
IN Output Voltage Sense Pin for the internal control loop. Must be connected to output.
EN
1
GND
VOS
SW
2,3
5
7
PWR Switch Pin connected to the internal MOSFET switches and inductor terminal.
Connect the inductor of the output filter here.
FB
4
6
IN
Feedback Pin for the internal control loop.
Connect this pin to the external feedback divider to program the output voltage.
PG
OUT
Power Good open drain output.
This pin is pulled to low if the output voltage is below regulation limits. Can be left floating if not used.
Thermal Pad
Connect it to GND.
FUNCTIONAL BLOCK DIAGRAMS
VIN
SW
High Side
N-MOS
Power
Good
PG
Gate
Driver
Control
Logic
Low Side
N-MOS
Active
Output
Discharge
Thermal
Shutdown
GND
VOS
ramp
Softstart
EN
direct control
&
compensation
comparator
Under
Voltage
Shutdown
FB
error
amplifier
minimum
on-timer
REF
DSC-CONTROLTM
Figure 2. Functional Block Diagram
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SLVSAK9A –OCTOBER 2011–REVISED NOVEMBER 2011
TYPICAL CHARACTERISTICS
PARAMETER MEASUREMENT INFORMATION
POWER GOOD
R3
TLV62080
VIN
VIN
PG
L1
VOUT
EN
SW
C3
C1
C2
GND
GND
VOS
FB
R1
R2
Table 2. List of Components
REFERENCE
DESCRIPTION
MANUFACTURER
C1
10uF, Ceramic Capacitor, 6.3V, X5R, size 0603
Std
22uF, Ceramic Capacitor, 6.3V, X5R, size 0805,
GRM21BR60J226ME39L
C2
C3
Murata
Kemet
47uF, Tantalum Capacitor, 8V, 35mΩ, size 3528,
T520B476M008ATE035
L1
R1
R2
R3
1.0µH, Power Inductor, 2.2A, size 3x3x1.2mm, XFL3012-102MEB
Depending on the output voltage of TLV62080, 1%;
39.2k, Chip Resistor, 1/16W, 1%, size 0603
Coilcraft
Std
Std
178k, Chip Resistor, 1/16W, 1%, size 0603
TABLE OF GRAPHS
Figure
Load Current, VOUT = 0.9V
Load Current, VOUT = 1.2V
Load Current, VOUT = 2.5V
Input Voltage, VOUT = 0.9V
Input Voltage, VOUT = 2.5V
Load Current, VOUT = 0.9V
Load Current, VOUT = 2.5V
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Efficiency
Output Voltage
Accuracy
Switching Frequency Load Current, VOUT = 2.5V,
VIN = 3.3V, VOUT = 1.2V, Load Current = 500mA, PWM Mode
Typical Operation
VIN = 3.3V, VOUT = 1.2V, Load Current = 10mA, PFM Mode
VIN = 3.3V, VOUT = 1.2V, Load Current = 50mA to 1A
VIN = 3.3V to 4.2V, VOUT = 1.2V, Load = 2.2Ω
VIN = 3.3V, VOUT = 1.2V, Load = 2.2Ω
Load Transient
Line Transient
Startup
VIN = 3.3V, VOUT = 1.2V, No Load
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EFFICIENCY
EFFICIENCY
vs
LOAD CURRENT
vs
LOAD CURRENT
100
100
90
80
70
60
50
40
30
20
10
0
VOUT = 0.9 V
VOUT = 1.2 V
90
80
70
60
50
40
30
20
10
0
VIN = 2.8 V
VIN = 3.6 V
VIN = 4.2 V
VIN = 2.8 V
VIN = 3.6 V
VIN = 4.2 V
10u
100u
1m
10m
100m
1
3
10u
100u
1m
10m
100m
1
3
Output Current (A)
Output Current (A)
G001
G002
Figure 3.
Figure 4.
EFFICIENCY
vs
OUTPUT VOLTAGE
vs
LOAD CURRENT
INPUT VOLTAGE
100
0.910
0.905
0.900
0.895
0.890
0.885
0.880
VOUT = 2.5 V
VOUT = 0.9 V
90
80
70
60
50
40
30
20
10
0
IOUT = 1A, TA = 25°C
IOUT = 1A, TA = −40°C
IOUT = 1A, TA = 85°C
IOUT = 10mA, TA = 25°C
IOUT = 10mA, TA = −40°C
IOUT = 10mA, TA = 85°C
VIN = 3.6 V
VIN = 4.2 V
VIN = 5.0 V
10u
100u
1m
10m
100m
1
3
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
Output Current (A)
G003
G004
Figure 5.
Figure 6.
OUTPUT VOLTAGE
vs
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
LOAD CURRENT
2.54
2.52
2.50
2.48
2.46
2.44
2.42
0.910
0.906
0.902
0.898
0.894
0.890
VOUT = 2.5 V
VIN = 3.6 V
IOUT = 1A, TA = 25°C
IOUT = 1A, TA = −40°C
IOUT = 1A, TA = 85°C
IOUT = 10mA, TA = 25°C
IOUT = 10mA, TA = −40°C
IOUT = 10mA, TA = 85°C
TA = 25°C
TA = −40°C
TA = 85°C
2.5
3
3.5
4
4.5
5
5.5
10u
100u
1m
10m
100m
1
3
Input Voltage (V)
Output Current (A)
G005
G006
Figure 7.
Figure 8.
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OUTPUT VOLTAGE
vs
SWITCHING FREQUENCY
vs
LOAD CURRENT
LOAD CURRENT
2.54
5M
4M
3M
2M
1M
0
VIN = 3.6 V
VOUT = 2.5V
VIN = 2.5V
VIN = 3.3V
VIN = 4.2V
VIN = 5.0V
2.52
2.50
2.48
2.46
TA = 25°C
TA = −40°C
TA = 85°C
10u
100u
1m
10m
100m
1
3
0
200m 400m 600m 800m
1
1.2
1.4
Output Current (A)
Output Current (A)
G007
G008
Figure 9.
Figure 10.
TYPICAL APPLICATION (PWM MODE)
TYPICAL APPLICATION (PFM MODE)
SW
SW
2V/div
2V/div
VOUT
VOUT
20mV/div
20mV/div
LCOIL
LCOIL
0.2A/div
0.5A/div
t - 2µs/div
t - 200ns/div
Figure 11.
Figure 12.
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LOAD TRANSIENT
LINE TRANSIENT
1A
4.2V
LOAD
50mA
1A/div
VIN
3.3V
1V/div
VOUT
20mV/div
VOUT
50mV/div
LCOIL
1A/div
t - 50µs/div
t - 100µs/div
Figure 13.
Figure 14.
START UP
START UP (WITHOUT LOAD)
EN
EN
5V/div
5V/div
PG
PG
1V/div
1V/div
VOUT
VOUT
1V/div
1V/div
LCOIL
LCOIL
0.5A/div
0.2A/div
t - 20µs/div
t - 20µs/div
Figure 15.
Figure 16.
8
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DETAILED DESCRIPTION
DEVICE OPERATION
The TLV62080 synchronous switched mode converter is based on DCS™ Control (Direct Control with Seamless
transition into Power Save Mode). This is an advanced regulation topology that combines the advantages of
hysteretic and voltage mode control.
The DCS™ Control topology operates in PWM (Pulse Width Modulation) mode for medium to heavy load
conditions and in Power Save Mode at light load currents. In PWM the converter operates with its nominal
switching frequency of 2MHz having a controlled frequency variation over the input voltage range. As the load
current decreases the converter enters Power Save Mode, reducing the switching frequency and minimizing the
IC quiescent current to achieve high efficiency over the entire load current range. DCS™ Control supports both
operation modes (PWM and PFM) using a single building block having a seamless transition from PWM to Power
Save Mode without effects on the output voltage. The TLV62080 offers both excellent DC voltage and superior
load transient regulation, combined with very low output voltage ripple, minimizing interference with RF circuits.
POWER SAVE MODE
As the load current decreases the TLV62080 enters the Power Save Mode operation. During Power Save Mode
the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current
maintaining high efficiency. The power save mode occurs when the inductor current becomes discontinuous. It is
based on a fixed on time architecture. The typical on time is given by ton=210ns·(VIN / VOUT). The switching
frequency over the whole load current range is shown in Figure 10.
100% DUTY CYCLE LOW DROPOUT OPERATION
The device offers low input to output voltage difference by entering 100% duty cycle mode. In this mode the high
side MOSFET switch is constantly turned on and the low side MOSFET is switched off. This is particularly useful
in battery powered applications to achieve longest operation time by taking full advantage of the whole battery
voltage range. The minimum input voltage to maintain switching regulation, depending on the load current and
output voltage can be calculated as:
V
= VOUT + IOUT,MAX ´(RDS(on) + RL )
IN,MIN
(1)
With:
VIN,MIN = Minimum input voltage
IOUT,MAX = Maximum output current
RDS(on) = High side FET on-resistance
RL = Inductor ohmic resistance
ENABLING / DISABLING THE DEVICE
The device is enabled by setting the EN input to a logic HIGH. Accordingly, a logic LOW disables the device. If
the device is enabled, the internal power stage will start switching and regulate the output voltage to the
programmed threshold. The EN input must be terminated with a resistance less than 1MΩ pulled to VIN or GND.
OUTPUT DISCHARGE
The output gets discharged by the SW pin with a typical discharge resistor of RDIS whenever the device shuts
down. This is the case when the device gets disabled by enable, thermal shutdown trigger, and undervoltage
lockout trigger.
SOFT START
After enabling the device, an internal soft-start circuitry monotonically ramps up the output voltage and reaches
the nominal output voltage during a soft start time (100µs, typical). This avoids excessive inrush current and
creates a smooth output voltage rise slope. It also prevents excessive voltage drops of primary cells and
rechargeable batteries with high internal impedance.
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If the output voltage is not reached within the soft start time, such as in the case of heavy load, the converter will
enter regular operation. Consequently, the inductor current limit will operate as described below. The TLV62080
is able to start into a pre-biased output capacitor. The converter starts with the applied bias voltage and ramps
the output voltage to its nominal value.
POWER GOOD
The TLV62080 has a power good output going low when the output voltage is below its nominal value. The
power good keeps high impedance once the output is above 95% of the regulated voltage, and is driven to low
once the output voltage falls below typically 90% of the regulated voltage. The PG pin is a open drain output and
is specified to sink typically up to 0.5mA. The power good output requires a pull up resistor that is recommended
connecting to the device output. When the device is off due to disable, UVLO or thermal shutdown, the PG pin is
at high impedance.
The PG signal can be used for sequencing of multiple rails by connecting to the EN pin of other converters.
Leave the PG pin unconnected when not used.
UNDER VOLTAGE LOCKOUT
To avoid mis-operation of the device at low input voltages, an under voltage lockout is implemented, that shuts
down the device at voltages lower than VUVLO with a VHYS_UVLO hysteresis.
THERMAL SHUTDOWN
The device goes into thermal shutdown once the junction temperature exceeds typically TJSD. Once the device
temperature falls below the threshold the device returns to normal operation automatically.
INDUCTOR CURRENT LIMIT
The Inductor Current Limit prevents the device from high inductor current and drawing excessive current from the
battery or input voltage rail. Excessive current might occur with a shorted/saturated inductor or a heavy
load/shorted output circuit condition.
The incorporated inductor peak current limit measures the current during the high side and low side power
MOSFET on-phase in PWM mode. Once the high side switch current limit is tripped, the high side MOSFET is
turned off and the low side MOSFET is turned on to reduce the inductor current. Until the inductor current drops
down to low side switch current limit, the low side MOSFET is turned off and the high side switch is turned on
again. This operation repeats until the inductor current does not reach the high side switch current limit. Due to
the internal propagation delay, the real current limit value can exceed the static current limit in the electrical
characteristics table.
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APPLICATION INFORMATION
Output Filter Design
The inductor and the output capacitor together provide a low pass frequency filter. To simplify this process
Table 3 outlines possible inductor and capacitor value combinations for the most application.
Table 3. Matrix of Output Capacitor / Inductor Combinations
COUT [µF](1)
L [µH](1)
10
22
47
100
150
0.47
1
(2)(3)
+
+
+
+
+
+
+
2.2
4.7
+
(1) Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary
by+20% and -50%. Inductor tolerance and current de-rating is anticipated. The effective inductance
can vary by +20% and -30%.
(2) Plus mark indicates recommended filter combinations.
(3) Filter combination in typical application.
Inductor Selection
Main parameter for the inductor selection is the inductor value and then the saturation current of the inductor. To
calculate the maximum inductor current under static load conditions, Equation 2 is given.
DIL
IL,MAX = IOUT,MAX
+
2
VOUT
1-
V
IN
DIL = VOUT
Where
´
L ´ fSW
(2)
IOUT,MAX = Maximum output current
ΔIL = Inductor current ripple
fSW = Switching frequency
L = Inductor value
It's recommended to choose the saturation current for the inductor 20%~30% higher than the IL,MAX, out of
Equation 2. A higher inductor value is also useful to lower ripple current, but will increase the transient response
time as well. The following inductors are recommended to be used in designs.
Table 4. List of Recommended Inductors
INDUCTANCE
CURRENT RATING
[mA]
DIMENSIONS
DC RESISTANCE
TYPE
MANUFACTURER
[µH]
L x W x H [mm3]
[mΩ typ]
1.0
1.0
2.2
2.2
2500
1650
2500
1600
3 x 3 x 1.2
3 x 3 x 1.2
35
40
49
81
XFL3012-102ME
LQH3NPN1R0NJ0
LQH44PN2R2MP0
XFL3012-222ME
Coilcraft
Murata
Murata
Coilcraft
4 x 3.7 x 1.65
3 x 3 x 1.2
Capacitor Selection
The input capacitor is the low impedance energy source for the converter which helps to provide stable
operation. A low ESR multilayer ceramic capacitor is recommended for best filtering and should be placed
between VIN and GND as close as possible to that pins. For most applications 10μF will be sufficient, a larger
value reduces input current ripple.
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The architecture of the TLV62080 allows to use tiny ceramic-type output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its
resistance up to high frequencies and to get narrow capacitance variation with temperature, it's recommended to
use X7R or X5R dielectric. The TLV62080 is designed to operate with an output capacitance of 10µF to 100µF,
as outlined in Table 3.
Table 5. List of Recommended Capacitors
CAPACITANCE
DIMENSIONS
TYPE
MANUFACTURER
[µF]
L x W x H [mm3]
10
22
22
GRM188R60J106M
GRM188R60G226M
GRM21BR60J226M
0603: 1.6 x 0.8 x 0.8
0603: 1.6 x 0.8 x 0.8
0805: 2.0 x 1.2 x 1.25
Murata
Murata
Murata
Setting the Output Voltage
By selecting R1 and R2, the output voltage is programmed to the desired value. The following equation can be
used to calculate R1 and R2.
POWER GOOD
TLV62080
2.5V...5.5V
180k
VIN
VIN
PG
1mH
VOUT
EN
SW
10µF
22µF
GND
GND
VOS
FB
R1
R2
Figure 17. Typical Application Circuit
R1
R2
R1
æ
ö
÷
ø
æ
ö
÷
ø
VOUT = VFB ´ 1+
= 0.45V ´ 1+
ç
ç
R2
è
è
(3)
For best accuracy, R2 should be kept smaller than 40kΩ to ensure that the current flowing through R2 is at least
100 times larger than IFB. Changing the sum towards a lower value increases the robustness against noise
injection. Changing the sum towards higher values reduces the quiescent current.
PCB Layout
The PCB layout is an important step to maintain the high performance of the TLV62080 device.
The input/output capacitors and the inductor should be placed as close as possible to the IC. This keeps the
traces short. Routing these traces direct and wide results in low trace resistance and low parasitic inductance. A
common power GND should be used. The low side of the input and output capacitors must be connected
properly to the power GND to avoid a GND potential shift.
The sense traces connected to FB and VOS pins are signal traces. Special care should be taken to avoid noise
being induced. By a direct routing, parasitic inductance can be kept small. GND layers might be used for
shielding. Keep these traces away from SW nodes.
12
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Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): TLV62080
TLV62080
www.ti.com
SLVSAK9A –OCTOBER 2011–REVISED NOVEMBER 2011
Figure 18. PCB Layout Suggestion
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the
power-dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
•
•
•
Improving the power dissipation capability of the PCB design
Improving the thermal coupling of the component to the PCB by soldering the ThermalPAD™
Introducing airflow in the system
For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics
Application Notes SZZA017 and SPRA953.
APPLICATION EXAMPLES
POWER GOOD
TLV62080
2.5V .. 5.5V
180k
VIN
VIN
PG
1mH
1.2V
VOUT
EN
SW
10µF
22µF
GND
GND
VOS
FB
65.3k
39.2k
Figure 19. 1.2V Output Voltage Application
Copyright © 2011, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Link(s): TLV62080
TLV62080
SLVSAK9A –OCTOBER 2011–REVISED NOVEMBER 2011
www.ti.com
POWER GOOD
TLV62080
3.0V .. 5.5V
180k
VIN
VIN
EN
PG
1mH
2.5V
VOUT
SW
10µF
22µF
GND
GND
VOS
FB
178.6k
39.2k
Figure 20. 2.5V Output Voltage Application
14
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Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): TLV62080
TLV62080
www.ti.com
SLVSAK9A –OCTOBER 2011–REVISED NOVEMBER 2011
Changes from Original (October 2011) to Revision A
Page
•
•
Changed pin VSNS to VOS in Figure 1 ................................................................................................................................ 1
Changed pin VSNS to VOS in Figure 17 ............................................................................................................................ 12
Copyright © 2011, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Link(s): TLV62080
PACKAGE OPTION ADDENDUM
www.ti.com
9-Mar-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TLV62080DSGR
TLV62080DSGT
ACTIVE
ACTIVE
WSON
WSON
DSG
DSG
8
8
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Mar-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV62080DSGR
TLV62080DSGT
WSON
WSON
DSG
DSG
8
8
3000
250
179.0
179.0
8.4
8.4
2.2
2.2
2.2
2.2
1.2
1.2
4.0
4.0
8.0
8.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Mar-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV62080DSGR
TLV62080DSGT
WSON
WSON
DSG
DSG
8
8
3000
250
195.0
195.0
200.0
200.0
45.0
45.0
Pack Materials-Page 2
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