LSF0102-Q1 [TI]
汽车类双通道双向多电压电平转换器;
| 型号： | LSF0102-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类双通道双向多电压电平转换器 转换器 电平转换器 |
| 文件： | 总25页 (文件大小：1252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LSF0102-Q1
ZHCSI50B –MAY 2018 –REVISED MAY 2023
LSF0102-Q1 汽车类2 通道自动双向多电压电平转换器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准
LSF0102-Q1 器件是一款自动双向电压转换器，无需方
向引脚即可在广泛的电源范围内进行转换。当容性负载
≤ 30pF 时，LSF0102-Q1 支持最高 100MHz 的升压
转换和高于 100MHz 的降压转换。此外，当容性负载
为 50pF 时，LSF0102-Q1 支持最高 40MHz 的上行和
下行转换，因此，LSF0102-Q1 器件可支持汽车中各种
常见的标准接口，如I2C、SPI、GPIO、SDIO、UART
和MDIO。
– 温度等级1：–40°C ≤TA ≤125°C
– 器件HBM ESD 分类等级2
– CDM ESD 分类等级C6
• 在无方向引脚的情况下提供双向电压转换
• 支持开漏和推挽应用，如I2C、SPI、UART、
MDIO、SDIO 和GPIO
• 在不超过30pF 的容性负载条件下支持最高达
100MHz 的上行转换和超过100MHz 的下行转换，
在50pF 的容性负载条件下支持高达40MHz 的上
行/下行转换
LSF0102-Q1 器件具有 5V 耐受数据输入。因此该器件
可兼容 TTL 电压电平。此外，LSF0102-Q1 还支持混
合模式电压转换，可在各个通道上升压和降压转换至不
同的电源电平。
• 可实现以下电压之间的双向电压电平转换
– 0.95V ↔ 1.8/2.5/3.3/5 V
– 1.2V ↔ 1.8/2.5/3.3/5V
– 1.8V ↔ 2.5/3.3/5V
– 2.5V ↔ 3.3/5V
封装信息(1)
封装尺寸（标称值）
器件型号
LSF0102-Q1
封装
DCU（VSSOP，8） 2.30mm × 2.00mm
– 3.3V ↔ 5V
• 低待机电流
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 5V 耐受I/O 端口，可支持TTL
电压电平
Vref_A
2
Vref_B
7
LSF0102-Q1
• 低导通电阻，可减少信号失真
• EN = 低电平时为高阻抗I/O 引脚
• 采用直通引脚排列以简化PCB 布线
• 闩锁性能超过100mA，符合JESD 78 II 类规范
8
EN
B1
6
5
SW
SW
3
4
A1
A2
2 应用
B2
• 信息娱乐系统音响主机
• 图形群集
• ADAS 融合
1
• ADAS 前置摄像头
• HEV 电池管理系统
GND
功能方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SDLS969
LSF0102-Q1
ZHCSI50B –MAY 2018 –REVISED MAY 2023
www.ti.com.cn
Table of Contents
7 Parameter Measurement Information............................8
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
8.2 Functional Block Diagram...........................................9
8.3 Feature Description.....................................................9
9 Application and Implementation..................................12
9.1 Application Information............................................. 12
9.2 Typical Application.................................................... 12
9.3 Power Supply Recommendations.............................17
9.4 Layout....................................................................... 18
10 Device and Documentation Support..........................19
10.1 Documentation Support.......................................... 19
10.2 接收文档更新通知................................................... 19
10.3 支持资源..................................................................19
10.4 Trademarks.............................................................19
10.5 静电放电警告.......................................................... 19
10.6 术语表..................................................................... 19
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics (Translating Down):
VCCB = 3.3 V..................................................................6
6.7 Switching Characteristics (Translating Down):
VCCB = 2.5 V..................................................................6
6.8 Switching Characteristics Translating Up): VCCB
= 3.3 V...........................................................................6
6.9 Switching Characteristics (Translating Up): VCCB
= 2.5 V...........................................................................6
6.10 Typical Characteristics..............................................7
Information.................................................................... 19
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (April 2021) to Revision B (May 2023)
Page
• Updated the Recommended Operating Conditions table to reflect maximum of 5.5 V...................................... 4
• Updated the Thermal Information table.............................................................................................................. 4
• Changed all Switching Characteristic Test Conditions........................................................................................6
• Added the Output Enable section.......................................................................................................................9
• Added the Up and Down Translation sections.................................................................................................. 11
• Changed pull up resistor to bias resistor in Enable, Disable, and Reference Voltage Guidelines section....... 12
• Added the Bias Circuitry section.......................................................................................................................13
• Updated the current values in the table titled Pull-up Resistor Values ............................................................ 13
• Added image to the Mixed-Mode Voltage Translation section..........................................................................14
• Added the Single Supply Translation section................................................................................................... 15
• Added section Voltage Translation for Vref_B < Vref_A + 0.8 V ......................................................................17
Changes from Revision * (May 2018) to Revision A (April 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Updated the Bidirectional Translation section to include inclusive terminology................................................13
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SDLS969
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5 Pin Configuration and Functions
图5-1. LSF0102-Q1 DCU Package, 8-Pin VSSOP (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
3
A1
A2
B1
B2
I/O
I/O
I/O
I/O
Input/Output A port for Channel 1
Input/Output A port for Channel 2
Input/Output B port for Channel 1
Input/Output B port for Channel 2
4
6
5
I/O enable input; see 图9-1 for typical setup. Should be tied directly to Vref_B to be enabled
or pulled LOW to disable all I/O pins.
EN
8
I
GND
1
2
Ground
—
—
Vref_A
A side reference supply voltage; see 节9 for setup and supply voltage range.
B side reference supply voltage. Must be connected to supply through 200 kΩ; see 节9 for
setup and supply voltage range.
Vref_B
7
—
(1) I = input, O = output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)(1)
MIN
–0.5
–0.5
MAX
7
UNIT
V
Input voltage(2), VI
Input/output voltage(2), VI/O
Continuous channel current
Input clamp current, IIK
7
V
128
–50
150
150
mA
mA
°C
VI < 0
Storage temperature range, Tstg
Operating junction temperature, TJ
–65
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are observed.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
5.5
UNIT
V
VI/O
Input/output voltage
Vref_A/B/EN
IPASS
TA
Reference voltage
5.5
V
Pass transistor current
Operating free-air temperature
64
mA
°C
125
–40
6.4 Thermal Information
LSF0102-Q1
THERMAL METRIC(1)
DCU (US8)
8 PINS
279.7
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
129.9
Junction-to-board thermal resistance
191.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
66.3
190.1
ψJB
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
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English Data Sheet: SDLS969
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX UNIT
VIK
IIH
Input clamp voltage
V
II = –18 mA, VEN = 0
–1.2
I/O input high
leakage
VI = 5 V, VEN = 0
5.0
µA
Vref_B to Vref_A
leakage
ICCBA
Vref_B = VEN = 5.5 V, Vref_A = 4.5 V, IO = 0, VI = VCC or GND
1
11
µA
pF
pF
CI(ref_A/B/EN)
Cio(off)
Input capacitance VI = 3 V or 0
I/O pin off-state
VO = 3 V or 0, VEN = 0
4.0
6.0
capacitance
I/O Pin on-state
capacitance
Cio(on)
VO = 3 V or 0, VEN = 3 V
VI = 0, IO = 64 mA
10.5 12.5
pF
Vref_A = 3.3 V; Vref_B = VEN = 5 V
Vref_A = 1.8 V; Vref_B = VEN = 5 V
Vref_A = 1.0 V; Vref_B = VEN = 5 V
Vref_A = 1.8 V; Vref_B = VEN = 5 V
Vref_A = 2.5 V; Vref_B = VEN = 5 V
Vref_A = 3.3 V; Vref_B = VEN = 5 V
Vref_A = 1.8 V; Vref_B = VEN = 3.3 V
Vref_A = 1.0 V; Vref_B = VEN = 3.3 V
Vref_A = 1.0 V; Vref_B = VEN = 1.8 V
8.0
9.0
10
10
15
9.0
18
20
30
Ω
VI = 0, IO = 32 mA
Ω
(2)
ron
On-state resistance
VI = 1.8 V, IO = 15 mA
VI = 1.0 V, IO = 10 mA
VI = 0 V, IO = 10 mA
VI = 0 V, IO = 10 mA
Ω
Ω
Ω
Ω
(1) All typical values are at TA = 25°C.
(2) Measured by the voltage drop between the A and B pins at the indicated current through the switch. On-state resistance is determined
by the lowest voltage of the two (A or B) pins.
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6.6 Switching Characteristics (Translating Down): VCCB = 3.3 V
over recommended operating free-air temperature range, VCCB = 3.3 V, VCCB = VIH = Vref_A + 1, VIL = 0, and VM = 0.5Vref_A
(unless otherwise noted) (see Parameter Measurement Information)
CL = 50 pF
CL = 30 pF
MIN TYP MAX
CL = 15 pF
MIN TYP MAX
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
Propagation delay
time, low-to-high
output
From (input) A or B
to (output) B or A
tPLH
1.1
0.7
0.8
0.3
0.4
ns
Propagation delay
time, high-to-low
output
From (input) A or B
to (output) B or A
tPHL
1.2
6.7 Switching Characteristics (Translating Down): VCCB = 2.5 V
over recommended operating free-air temperature range, VCCB = 2.5 V, VCCB = VIH = Vref_A + 1, VIL = 0, and VM = 0.5Vref_A
(unless otherwise noted) (see Parameter Measurement Information)
CL = 50 pF
CL = 30 pF
MIN TYP MAX
CL = 15 pF
MIN TYP MAX
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
Propagation delay
time, low-to-high
output
From (input) A or B
to (output) B or A
tPLH
1.2
0.8
1
0.35
0.5
ns
Propagation delay
time, high-to-low
output
From (input) A or B to
(output) B or A
tPHL
1.3
6.8 Switching Characteristics Translating Up): VCCB = 3.3 V
over recommended operating free-air temperature range, VCCB = 3.3 V, VCCB = VT = Vref_A + 1, Vref_A = VIH, VIL = 0, VM
=
0.5Vref_A and RL = 300 (unless otherwise noted) (see Parameter Measurement Information)
CL = 50 pF
CL = 30 pF
CL = 15 pF
MIN TYP MAX
PARAMETER
TEST CONDITIONS
UNIT
MIN TYP MAX
MIN
TYP
MAX
Propagation delay
time, low-to-high
output
From (input) A or B
to (output) B or A
tPLH
1
1
0.8
0.4
0.4
ns
Propagation delay
time, high-to-low
output
From (input) A or B
to (output) B or A
tPHL
0.9
6.9 Switching Characteristics (Translating Up): VCCB = 2.5 V
over recommended operating free-air temperature range, VCCB = 2.5 V, VCCB = VT = Vref_A + 1, Vref_A = VIH, VIL = 0, VM
=
0.5Vref_A and RL = 300 (unless otherwise noted) (see Parameter Measurement Information)
CL = 50 pF
CL = 30 pF
CL = 15 pF
TYP MAX
PARAMETER
TEST CONDITIONS
UNIT
MIN TYP MAX
MIN TYP MAX MIN
Propagation delay
time, low-to-high
output
From (input) A or B
to (output) B or A
tPLH
1.1
1.3
0.9
1.1
0.45
0.6
ns
Propagation delay
time, high-to-low
output
From (input) A or B
to (output) B or A
tPHL
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English Data Sheet: SDLS969
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6.10 Typical Characteristics
图6-1. Signal Integrity (1.8 to 3.3 V Translation Up at 50 MHz)
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7 Parameter Measurement Information
The outputs are measured one at a time, with one transition per measurement. All input pulses are supplied by
generators that have the following characteristics:
• PRR ≤10 MHz
• ZO = 50 Ω
• tr ≤2 ns
• tf ≤2 ns
VT
RL
S1
From Output
Under Test
S2
(1)
CL
A. CL includes probe and jig capacitance.
图7-1. Load Circuit
USAGE
SWITCH
Translating Up
Translating Down
S1
S2
图7-2. Translating Up and Down Table
3.3 V
VIL
VM
VM
Input
5 V
VOL
VM
VM
Output
图7-3. Translating Up
5 V
VIL
VM
VM
Input
2 V
VOL
VM
VM
Output
图7-4. Translating Down
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8 Detailed Description
8.1 Overview
The LSF0102-Q1 device can be used in level translation applications for interfacing devices or systems
operating at different interface voltages. The LSF0102-Q1 device is ideal for use in applications where an open-
drain driver is connected to the data I/Os. With appropriate pull-up resistors and layout, the LSF0102-Q1 device
can achieve 100 MHz. The LSF0102-Q1 can also be used in applications where a push-pull driver is connected
to the data I/Os.
8.2 Functional Block Diagram
Vref_A
2
Vref_B
7
LSF0102-Q1
8
EN
B1
6
5
SW
SW
3
4
A1
A2
B2
1
GND
8.3 Feature Description
8.3.1 Auto Bidirectional Voltage Translation
The LSF0102-Q1 device is an auto bidirectional voltage level translator that operates from 0.95 to 5.5 V on
Vref_A and 1.8 to 5.5 V on Vref_B. This allows bidirectional voltage translation between 0.95 V and 5.5 V without
the need for a direction pin in open-drain or push-pull applications. The LSF0102-Q1 device supports level
translation applications with transmission speeds greater than 100 Mbps for open-drain systems using a 250-Ω
pull-up resistor with a 30-pF capacitive load.
8.3.2 Output Enable
To enable the I/O pins, the EN input should be tied directly to Vref_B during operation and both pins must be
pulled up to the HIGH side (VCCB) through a bias resistor (typically 200 kΩ). To ensure the high impedance state
during power-up, power-down, or during operation, the EN pin must be LOW. The EN pin should always be tied
directly to the Vref_B pin and is recommended to be disabled by an open-drain driver without a pullup resistor.
This allows Vref_B to regulate the EN input and bias the channels for proper translation. A filter capacitor on Vref_B
is recommended for a stable supply at the device.
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3.3 V
VCCB
1.8 V
200 k
Vref_B
EN
Vref_A
0.1 ꢀF
B1
A1
图8-1. EN Pin Tied to Vref_B Directly and to VCCB Through a Pull-Up Resistor
The supply voltage of open drain I/O devices can be completely different from the supplies used for the LSF and
has no impact on the operation. For additional details on how to use the enable pin, see the Using the Enable
Pin with the LSF Family video.
表8-1. EN Pin Function Table
INPUT EN(1) PIN
Tied directly to Vref_B
L
Data Port State
An = Bn
Hi-Z
(1) EN is controlled by Vref_B logic levels.
8.3.3 Device Functional Modes
For each channel (n), when either the An or Bn port is LOW, the switch provides a low impedance path between
the An and Bn ports; the corresponding Bn or An port will be pulled LOW. The low RON of the switch allows
connections to be made with minimal propagation delay and signal distortion.
表 8-1 provides a summary of device operation. For additional details on the functional operation of the LSF
family of devices, see the Down Translation with the LSF Family and Up Translation with the LSF Family videos.
表8-2. Device Functionality
Switch State
Signal Direction(1)
Input State
Functionality
ON
A-side voltage is pulled low through the switch to the B-side voltage
B = LOW
(Low Impedance)
B to A (Down Translation)
(2)
OFF
(High Impedance)
A-side voltage is clamped at Vref_A
B = HIGH
A = LOW
A = HIGH
ON
B-side voltage is pulled low through the switch to the A-side voltage
(Low Impedance)
A to B (Up Translation)
OFF
(High Impedance)
B-side voltage is clamped at Vref_A and then pulled up to the VPU
supply voltage
(1) The downstream channel should not be actively driven through a low impedance driver, or else bus contention may occur.
(2) The A-side can have a pullup to Vref_A for additional current drive capability or may also be pulled above Vref_A with a pullup resistor.
Specifications in the Recommended Operating Conditions section should always be followed.
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8.3.3.1 Up and Down Translation
8.3.3.1.1 Up Translation
When the signal is being driven from A to B and the An port is HIGH, the switch will be OFF and the Bn port will
then be driven to a voltage higher than Vref_A by the pull-up resistor that is connected to the pull-up supply
voltage (VPU). This functionality allows seamless translation between higher and lower voltages selected by the
user, without the need for directional control. Pull-up resistors are always required on the high side, and pull-ups
are only required on the low side, if the low side of the device's output is open drain or its input has a leakage
greater than 1 µA.
3.3 V
VCCB
1.8 V
VCCA
LSF010x-Q1
200 k
Vref_B
EN
Vref_A
0.1 μF
RB1
B1
B2
A1
A2
3.3 V
Device
1.8 V
Device
GND
图8-2. Up Translation Example Schematic with Push-Pull and Open Drain Configuration
Up translation with the LSF requires attention to two important factors: maximum data rate and sink current.
Maximum data rate is directly related to the rising edge of the output signal. Sink current depends on supply
values and the chosen pull-up resistor values. 方程式 1 shows the maximum data rate formula and 方程式 2
shows the maximum sink current formula, both of which are estimations. A low RC value is needed to reach high
speeds, which also require strong drivers. Please see the Up Translation with the LSF Family video for estimated
data rate and sink current calculations based on circuit components.
1
1
bits
second
=
+
(1)
(2)
3 × 2R
C
6R
C
B1 B1
B1 B1
V
V
R
CCA
CCB
I
≅
A
OL
R
A1
B1
8.3.3.1.2 Down Translation
When the signal is being driven HIGH from the Bn port to An port, the switch will be OFF, clamping the voltage
on the An port to the voltage set by Vref_A. A pull-up resistor can be added on either side of the device. There are
special circumstances that allow the removal of one or both of the pull-up resistors. If the signal is always going
to be down translated from a push-pull transmitter, then the resistor on the B-side can be removed. If the leakage
current into the receiver on the A-side is less than 1 µA, then the resistor on the A-side can also be removed.
This arrangement with no external pull-up resistors can be used when down translating from a push-pull output
to a low-leakage input. For an open drain transmitter, the pull-up resistor on the B-side is necessary because an
open drain output can't drive high by itself. For a summary of device operation, refer to 节 8.3.3. For additional
details on the functional operation of the LSF family of devices, see the Up Translation with the LSF Family and
Down Translation with the LSF Family videos.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The LSF0102-Q1 device is able to perform voltage translation for open-drain or push-pull interfaces such as I2C,
SPI, UART, MDIO, SDIO, and GPIO.
9.2 Typical Application
9.2.1 Bidirectional Translation
VB_Pullup = 3.3 V
Vref_A = 1.2 V
200 kΩ
Vpu1 = 3.3 V
Vref_A
2
Vref_B
7
Rpu
LSF0102-Q1
Rpu
EN
8
Rpu
Vpu3 = 2.5 V
VCC
GPIO3
VCC
GPIO1
B1
6
A1
3
SW
SW
B2
5
GPIO2
VCC
A2
4
GPIO3
GND
1
GND
GND
图9-1. Bidirectional Translation to Multiple Voltage Levels
9.2.1.1 Design Requirements
9.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines
The LSF0102-Q1 device has an EN input that is used to disable the device by setting EN LOW, which places all
I/Os in the high-impedance state. Since LSF family is switch-type voltage translator, the power consumption is
very low. It is recommended to always enable LSF0102-Q1 device for bidirectional applications by connecting
the EN pin to the Vref_B pin, as shown in 图 9-1. For additional details on setting up the Vref_A, Vref_B, and EN
pins, see the Understanding the Bias Circuit for the LSF Family video.
表9-1. Application Operating Condition
PARAMETER
MIN
TYP
MAX
5.5
UNIT
(1)
Vref_A
Vref_B
VI(EN)
VPU
reference voltage (A)
0.95
V
V
V
V
reference voltage (B)
input voltage on EN pin
pull-up supply voltage
Vref_A + 0.8
Vref_A + 0.8
0
5.5
Vref_B
5.5
Vref_B
(1) Vref_A is required to be the lowest voltage level across all inputs and outputs.
The 200 kΩ, bias resistor is required to allow Vref_B to regulate the EN input. A filter capacitor on Vref_B is
recommended. Also Vref_B and VI(EN) are recommended to be 1.0 V higher than Vref_A for best signal integrity.
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9.2.1.1.2 Bias Circuitry
For proper operation, VCCA must always be at least 0.8 V less than VCCB (VCCA + 0.8 ≦ VCCB). The 200 kΩ bias
resistor is required to allow Vref_B to regulate the EN input and properly bias the device for translation. A 0.1 µF
capacitor is recommended for providing a path from Vref_B to ground for high frequency noise. Vref_B and VI(EN)
are recommended to be 1.0 V higher than Vref_A for best signal integrity.
Attempting to drive the EN pin directly with a push-pull output device is a very common design error with the
LSF0102-Q1 series of devices. It is also very important to note that current does flow into the A-side voltage
supply during normal operation. Not all voltage sources can sink current, so be sure that applicable designs can
handle this current. For more design details, see the Understanding the Bias Circuit for the LSF Family video.
3.3 V
VCCB
1.8 V
200 kΩ
Vref_B
EN
Vref_A
0.1 µF
B1
A1
图9-2. Bias Circuitry Inside the LSF010x-Q1 Device
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Bidirectional Translation
For the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage),
the EN input must be connected to Vref_B and both pins pulled to HIGH side VCCB through a bias resistor
(typically 200 kΩ), as shown in 图 9-1. This allows Vref_B to regulate the EN input. A filter capacitor on Vref_B is
recommended. The controller output driver can be push-pull or open-drain (pull-up resistors may be required)
and the peripheral device output can be push-pull or open-drain (pull-up resistors are required to pull the Bn
outputs to Vpu).
If either output is push-pull, data must be unidirectional or the outputs must be tri-state and be controlled by
some direction-control mechanism to prevent HIGH-to-LOW contention in either direction. If both outputs are
open-drain, no direction control is needed.
In 图 9-1, the reference supply voltage Vref_A is connected to the processor core power supply voltage. Vref_B is
connected through a 200 kΩ resistor to a 3.3 V VB_Pullup power supply and Vref_A is set to 1.2 V. The output of A1
has a maximum output voltage equal to Vref_A, and the bidirectional interface on channel 2 has a maximum
output voltage equal to VPU1
.
9.2.1.2.2 Pull-Up Resistor Sizing
To maintain an appropriate output low voltage, the pull-up resistor value should limit the current through the pass
transistor when it is in the ON state to less than 15 mA. This ensures a pass voltage of 260 mV to 350 mV. To
set the current through each pass transistor at 15 mA, the pull-up resistor value can be calculated using the
following equation:
V
− 0.35 V
pu
0.015 A
R
=
(3)
pu
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The appropriate pull up resistor will depend on the current requirements of the application. 表 9-2 provides
resistor values, reference voltages, and currents at 15 mA, 10 mA, and 3 mA. The resistor value shown in the
+10% column (or a larger value) should be used to ensure that the pass voltage of the transistor is 350 mV or
less. The external driver must be able to sink the total current from the resistors on both sides of the LSF0102-
Q1 device at 0.175 V, although the 15 mA applies only to current flowing through the LSF0102-Q1.
表9-2. Pull-up Resistor Values
8 mA
5 mA
3 mA
VPU
NOMINAL (Ω)
+10%(1) (Ω)
NOMINAL (Ω)
+10%(1) (Ω)
NOMINAL (Ω)
+10%(1) (Ω)
5 V
581
639
930
1023
1550
1705
3.3 V
2.5 V
1.8 V
1.5 V
1.2 V
369
269
181
144
106
406
296
199
158
117
590
430
290
230
170
649
473
319
253
187
983
717
483
383
283
1082
788
532
422
312
(1) +10% to compensate for VDD range and resistor tolerance
9.2.1.2.3 Application Curve
图9-3. Captured Waveform From Above I2C Set-Up (1.8 V to 3.3 V at 2.5 MHz)
9.2.1.2.4 Mixed-Mode Voltage Translation
The supply voltage (VPU) for each channel can be individually set with a pull-up resistor. 图 9-4 shows an
example of this mixed-mode multi-voltage translation. For additional details on multi-voltage translation, see the
Multi-voltage Translation with the LSF Family video.
With the Vref_B pulled up to 5 V and Vref_A connected to 1.8 V, all channels will be clamped to 1.8 V at which
point a pullup can be used to define the high level voltage for a given channel.
• Push-Pull Down Translation (5 V to 1.8 V): Channel 1 is an example of this setup. When B1 is 5 V, A1 is
clamped to 1.8 V, and when B1 is LOW, A1 is driven LOW through the switch.
• Push-Pull Up Translation (1.8 V to 5 V): Channel 2 is an example of this setup. When A2 is 1.8 V, the
switch is high impedance and the B2 channel is pulled up to 5 V. When A2 is LOW, B2 is driven LOW through
the switch.
• Push-Pull Down Translation (3.3 V to 1.8 V): Channels 3 and 4 are examples of this setup. When either B3
or B4 are driven to 3.3 V, A3 or A4 are clamped to 1.8 V, and when either B3 or B4 are LOW, A3 or A4 are
driven LOW through the switch.
• Open-Drain Bidirectional Translation (3.3 V ↔ 1.8 V): Channels 5 through 8 are examples of this setup.
These channels are for bidirectional operation for I2C and MDIO to translate between 1.8 V and 3.3 V with
open-drain drivers.
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Vpu = 5.0 V
Vref(A) = 1.8 V
200 k
Vref_B
Vref_A
LSF010x-Q1
EN
Rpu
1.8 V
Vcc
Vcc
A1
A2
A3
A4
B1
B2
B3
B4
B5
B6
GPIO
GPIO
GPIO
SW
SW
SW
SW
Vpu
=
3.3 V
GPIO
GPIO
GPIO
Vcc
GPIO
GPIO
Rpu
Rpu
A5
A6
SW
SW
SW
SW
SCL
SDA
SCL
SDA
Rpu
Rpu
MDIO
MDIO
MDC
MDC
图9-4. Multi-Voltage Translation with the LSF010x-Q1
9.2.1.2.5 Single Supply Translation
Sometimes, an external device will have an unknown voltage that could be above or below the desired
translation voltage, preventing a normal connection of the LSF. Resistors are added on the A side in place of the
second supply in this case –this is an example of when LSF single supply operation is utilized, shown in Figure
9-5. In the following figure, a single 3.3 V supply is used to translate between a 3.3 V device and a device that
can change between 1.8 V and 5.0 V. R1 and R2 are added in place of the second supply. Note that due to
some current coming out of the Vref_A pin, this cannot be treated as a simple voltage divider.
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3.3 V
VCCB
LSF010x-Q1
200 k
R1
Vref_B
EN
Vref_A
R2
1.8 V – 5 V
0.1 µF
RB1
RB2
RA1
RA2
B1
B2
A1
A2
5
1.8 V – V
Device
3.3 V
Device
GND
图9-5. Single Supply Translation with 3.3 V Supply
The steps to select the resistor values for R1 and R2 are as follows:
1. Select a value for R1. Typically, 1 MΩ is used to reduce current consumption.
2. Plug in values for your system into the following equation. Note that Vref_A is the lowest voltage in the
system. VCCB is the primary supply and R1 is the selected value from step 1.
3
200 10 × R × V
1
REFA
− 0.85 × R
1
R
=
(4)
2
3
200 10 + R
V
− V
1
CCB
REFA
The single supply used must be at least 0.8 V larger than the lowest desired translation voltage. The voltage at
Vref_A must be selected as the lowest voltage to be used in the system. The LSF evaluation module (LSF-EVM)
contains unpopulated pads to place R1 and R2 for single supply operation testing. For an example single supply
translation schematic and details, see the Single Supply Translation with the LSF Family video.
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9.2.1.2.6 Voltage Translation for Vref_B < Vref_A + 0.8 V
As described in the Enable, Disable, and Reference Voltage Guidelines section, it is generally recommended
that Vref_B > Vref_A + 0.8 V; however, the device can still operate in the condition where Vref_B < Vref_A + 0.8 V as
long as additional considerations are made for the design.
Typical Operation (Vref_B > Vref_A + 0.8 V): in this scenario, pullup resistors are not required on the A-side for
proper down-translation as is shown for channels 1 and 2 of 图 9-4. The typical operating mode of the device
ensures that when down translating from B to A, the A-side I/O ports will clamp at Vref_A to provide proper
voltage translation. For further explanation of device operation, see the Down Translation with the LSF Family
video.
Requirements for Vref_B < Vref_A + 0.8 V Operation: in this scenario, there is not a large enough voltage
difference between Vref_A and Vref_B to ensure that the A side I/O ports will be clamped at Vref_A, but rather at a
voltage approximately equal to Vref_B – 0.8 V. For example, if Vref_B = 1.8 V and Vref_A = 1.2 V, the A-side I/Os
will clamp to a voltage around 1.0 V. Therefore, to operate in such a condition, the following additional design
considerations must be met:
• Vref_B must be greater than VRef_A during operation (Vref_B > Vref_A
)
• Pullup resistors should be populated on A-side I/O ports to ensure the line will be fully pulled up to the
desired voltage.
图 9-6 shows an example of this setup, where 1.2 V ↔ 1.8 V translation is achieved with the LSF0102-Q1. This
type of setup also applies for other voltage nodes such as 1.8 V ↔ 2.5 V, 1.05 V ↔ 1.5 V, and others as long as
the Recommended Operating Conditions table is followed.
1.8 V
1.2 V
200 kΩ
Vref_B
Vref_A
EN
RPU(A2)
RPU(A1)
RPU(B1)
RPU(B2)
0.1 μF
A1
A2
B1
B2
SW
SW
1.2 V Device
1.8 V Device
图9-6. 1.2 V to 1.8 V Level Translation with LSF010x
9.3 Power Supply Recommendations
There are no power sequence requirements for the LSF family. 表 9-3 provides the recommended operating
voltages for all supply and input pins.
表9-3. Recommended Operating Voltages
PARAMETER
MIN
TYP
MAX
5.5
UNIT
(1)
Vref_A
Vref_B
VI(EN)
reference voltage (A)
0.95
V
V
V
reference voltage (B)
Vref_A + 0.8
Vref_A + 0.8
5.5
input voltage on EN pin
5.5
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表9-3. Recommended Operating Voltages (continued)
PARAMETER
MIN
TYP
MAX
UNIT
VPU
pull-up supply voltage
0
Vref_B
V
9.4 Layout
9.4.1 Layout Guidelines
Because the LSF0102-Q1 device is a switch-type level translator, the signal integrity is dependent upon the pull-
up resistor value and PCB board parasitics. Consider the following recommendations when designing with the
LSF0102-Q1.
• Minimize the signal trace length to reduce capacitance
• Avoid using stubs in the signal path to reduce parasitics.
• Place the LSF0102-Q1 device near the high voltage side.
• Select the appropriate pull-up resistor that applies to translation levels and driving capability of transmitter.
9.4.2 Layout Example
LSF0102-Q1
EN
GND
1
2
3
4
8
7
6
5
Short Signal Trace as possible
Vref_B
Vref_A
A1
A2
B1
B2
Minimize Stub as possible
图9-7. Short Trace Layout
TP1
SDIO Connector
(3.3V IO)
SD Controller
(1.8V IO)
LSF0102-Q1
SDIO level translator
Device PCB
TP2
图9-8. Device Placement
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10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TI Logic Minute: Introduction –Voltage Level Translation with the LSF Family video
• Texas Instruments, Voltage-Level Translation with the LSF Family application report
10.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LSF0102QDCURQ1
ACTIVE
VSSOP
DCU
8
3000 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
NG2SQ
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LSF0102-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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28-Feb-2023
Catalog : LSF0102
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE OUTLINE
DCU0008A
VSSOP - 0.9 mm max height
S
C
A
L
E
6
.
0
0
0
SMALL OUTLINE PACKAGE
3.2
3.0
TYP
C
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
6X 0.5
8
1
2X
2.1
1.9
1.5
NOTE 3
4
5
0.25
0.17
8X
2.4
2.2
B
0.08
C A B
NOTE 3
SEE DETAIL A
0.9
0.6
0.12
GAGE PLANE
0.1
0.0
0.35
0.20
0 -6
(0.13) TYP
A
30
DETAIL A
TYPICAL
4225266/A 09/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-187 variation CA.
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EXAMPLE BOARD LAYOUT
DCU0008A
VSSOP - 0.9 mm max height
SMALL OUTLINE PACKAGE
SEE SOLDER MASK
DETAILS
SYMM
8X (0.85)
(R0.05) TYP
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(3.1)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
OPENING
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4225266/A 09/2014
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DCU0008A
VSSOP - 0.9 mm max height
SMALL OUTLINE PACKAGE
8X (0.85)
SYMM
(R0.05) TYP
8
1
8X (0.3)
SYMM
6X (0.5)
4
5
(3.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 25X
4225266/A 09/2014
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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