LV2862XLVDDCR [TI]

采用超小型 SOT23 封装的 4.5V 至 60V 600mA 降压转换器 | DDC | 6 | -40 to 125;


型号：	LV2862XLVDDCR
厂家：	TEXAS INSTRUMENTS
描述：	采用超小型 SOT23 封装的 4.5V 至 60V 600mA 降压转换器 \| DDC \| 6 \| -40 to 125 转换器
文件：	总25页 (文件大小：1597K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LV2862

ZHCSS74B –JANUARY 2015 –REVISED JUNE 2023

LV2862 60V、600mA、高效、宽输入电压范围降压转换器

电源调节的各种工业和汽车应用。1µA 的超低关断电

流可进一步延长电池使用寿命。工作频率固定在

770kHz（X 版本）和2.1MHz（Y 版本）上，可在保证

低输出纹波电压的同时，支持使用小型外部元件。软启

动和补偿电路在内部实现，从而最大限度地减少了器件

所用的外部元件。

1 特性

• 输入范围为4V 至60V，可承受65V 瞬态

• 770kHz（X 版本）或2.1MHz（Y 版本）开关频率

• 凭借Eco-mode，可以在轻负载下实现超高的效率

• 低压降运行

• 高达600mA 的输出电流

• 高电压精密使能输入

• 过流保护

LV2862 针对高达 600mA 的负载电流进行了优化。该

器件具有0.765V 的标称反馈电压。

• 过热保护

• 内部补偿

• 内部软启动

• 小型总体解决方案尺寸（SOT-6L 封装）

该器件内置多种保护特性，例如逐脉冲电流限制、热感

应和应对功耗过大的热关断。LV2862 采用扁平

SOT-6L 封装。

封装信息

封装⁽¹⁾

封装尺寸⁽²⁾

2 应用

器件型号

LV2862

DDC（SOT，6） 2.90 mm × 2.8 mm

• 电网基础设施

• 电器

• 电机驱动器

• 通用宽输入电压电源

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

(2) 封装尺寸（长x 宽）为标称值，并包括引脚（如适用）。

3 说明

LV2862 是一款PWM 直流/直流降压稳压器。该器件具

有 4V 至 60V 的宽输入范围，适用于从非稳压源进行

100

VIN

Up to 60 V

VIN

Cboot

Cin

SHDN

GND

Cout

LV2862

简化原理图

Vin = 12 V

1000

100

Output Current (mA)

D001

效率与输出电流间的关系

(f_sw= 0.7MHz, V_OUT= 3.3V)

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVSA49

LV2862

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ZHCSS74B –JANUARY 2015 –REVISED JUNE 2023

Table of Contents

7.4 Device Functional Modes............................................9

8 Application and Implementation..................................10

8.1 Application Information............................................. 10

8.2 Typical Application.................................................... 10

8.3 Power Supply Recommendations.............................15

8.4 Layout....................................................................... 15

9 Device and Documentation Support............................17

9.1 Documentation Support............................................ 17

9.2 接收文档更新通知..................................................... 17

9.3 支持资源....................................................................17

9.4 Trademarks...............................................................17

9.5 静电放电警告............................................................ 17

9.6 术语表....................................................................... 17

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................4

6.5 Electrical Characteristics.............................................5

6.6 Typical Characteristics................................................6

7 Detailed Description........................................................7

7.1 Overview.....................................................................7

7.2 Functional Block Diagram...........................................7

7.3 Feature Description.....................................................7

Information.................................................................... 17

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (June 2020) to Revision B (June 2023)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• 更新了封装信息表格式...................................................................................................................................... 1

• Moved storage temperature row from the Handling Ratings table to the Absolute Maximum Ratings table......4

• Updated the Handling Ratings table to ESD Ratings table.................................................................................4

• Corrected part number typo in the Power Supply Recommendations section ................................................ 15

Changes from Revision * (December 2014) to Revision A (June 2020)

Page

• 首次公开发布......................................................................................................................................................1

English Data Sheet: SNVSA49

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5 Pin Configuration and Functions

LV2862

GND

V_IN

PIN 1 ID

SHDN

TSOT-6L (Top View)

图5-1. SOT (DDC) 6 Pins Top View

表5-1. Pin Functions

DESCRIPTION

NAME

NO.

Switch FET gate bias voltage. Connect C_bootcap between CB and SW.

Ground connection

GND

Set feedback voltage divider ratio with V_OUT= V_FB(1 + (R1 / R2))

Enable and disable input (high voltage tolerant). Internal pullup current source. Pull below 1.25 V to

disable. Float to enable. Establish the input undervoltage lockout with a two-resistor divider.

SHDN

V_IN

Power input voltage pin. Input for internal supply and drain node input for internal high-side MOSFET.

Switch node. Connect to inductor, diode, and C_bootcap.

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6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

–0.3

–1

MAX

UNIT

V_INto GND

SHDN to GND

Input voltages

FB to GND

CB to SW

SW to GND

Output voltages

SW to GND less than 30-ns transients

–2

T_Joperating junction temperature

T_stgstorage temperature range

150

165

°C

–40

–55

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

6.2 ESD Ratings

MIN

MAX

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

pins⁽¹⁾

2000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins⁽²⁾

500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

VIN

CB to SW

Buck Regulator

–0.3

–1

Control

SHDN

125

Temperature

Operating junction temperature, T_J

°C

–40

6.4 Thermal Information

LV2862

TSOT

6 PINS

102

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

36.9

°C/W

Junction-to-board characterization parameter

28.4

(1) All numbers apply for packages soldered directly onto a 3" x 3" PC board with 2 oz. copper on 4 layers in still air in accordance to

JEDEC standards. Thermal resistance varies greatly with layout, copper thickness, number of layers in PCB, power distribution,

English Data Sheet: SNVSA49

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number of thermal vias, board size, ambient temperature, and air flow. For more information about traditional and new thermal metrics,

see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

V_IN= 12 V, SHDN = V_IN. T_J= 25°C unless otherwise noted.

PARAMETER

VIN (Input Power Supply)

Operating input voltage

Shutdown supply current

CONDITION

MIN

TYP

MAX

UNIT

µA

EN = 0 V

Rising

Undervoltage lockout thresholds

Falling

I_Q

Eco-mode, no load, V_IN= 12 V, not switching

µA

SHDN and UVLO

Rising SHDN Threshold Voltage

1.05

1.25

–4.2

–1

1.38

SHDN = 2.3 V

SHDN = 0.9 V

µA

SHDN PIN current

Hysteresis current

HIGH-SIDE MOSFET

On-resistance

-3

V_IN= 12 V, CB to SW = 5.8 V

f_SW= 2.1 MHz

900

mΩ

t_ON-min

D_MAX: Maximum duty cycle

V_FB: Feedback voltage

CURRENT LIMIT

96%

0.765

0.74

0.79

Peak Current limit threshold

1200

770

LV2862X

LV2862Y

560

980

f_SWSwitching frequency

kHz

1785

2100

2415

THERMAL PERFORMANCE

T_SHUTDOWNThermal shutdown trip

point

170

ºC

T_hys

Hysteresis

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6.6 Typical Characteristics

Unless otherwise specified the following conditions apply: V_IN= 12 V, SHDN = V_IN, T_A= 25°C

100

Vin = 15 V

Vin = 18 V

Vin = 12 V

Vin = 15 V

100

1000

100

1000

Output Current (mA)

D002

D003

V_OUT= 12 V

L1 = 22 µH

f_SW= 770 kHz

C_OUT= 10 µF

V_OUT= 5 V

L1 = 22 µH

f_SW= 770 kHz

C_OUT= 10 µF

图6-1. Efficiency versus Load Current

图6-2. Efficiency versus Load Current

100

Vin = 15 V

Vin = 18 V

Vin = 12 V

Vin = 15 V

100

1000

100

1000

Output Current (mA)

D004

D005

V_OUT= 12 V

L1 = 10 µH

f_SW= 2.1 MHz

C_OUT= 10 µF

V_OUT= 5 V

L1 = 10 µH

f_SW= 2.1 MHz

C_OUT= 10 µF

图6-3. Efficiency versus Load Current

图6-4. Efficiency versus Load Current

English Data Sheet: SNVSA49

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7 Detailed Description

7.1 Overview

The LV2862 device is a 60-V, 600-mA, step-down (buck) regulator. The buck regulator has a very low quiescent

current during light load to prolong the battery life.

The LV2862 improves performance during line and load transients by implementing a constant frequency,

current mode control which reduces output capacitance and simplifies frequency compensation design. The

LV2862 reduces the external component count by integrating the boot recharge diode. The bias voltage for the

integrated high-side MOSFET is supplied by a capacitor on the CB to SW pin. The boot capacitor voltage is

monitored by a UVLO circuit and turns the high-side MOSFET off when the boot voltage falls below a preset

threshold. The LV2862 can operate at high duty cycles because of the boot UVLO and refresh the wimp FET.

The output voltage can be stepped down to as low as the 0.8 V. Internal soft start is featured to minimize inrush

currents.

7.2 Functional Block Diagram

VIN

Current Sense

Leading Edge

Blanking

Bootstrap

Regulator

Logic and

PWM Latch

Driver

Wimp FET

CB Refresh

–

Frequency

Shift

–

0.765 V

COMP

Main OSC

Bandgap

Reference

Slope

Compensation

SHDN

GND

7.3 Feature Description

7.3.1 Continuous Conduction Mode

The LV2862 steps the input voltage down to a lower output voltage. In continuous conduction mode (when the

inductor current never reaches zero at CCM), the buck regulator operates in two cycles. The power switch is

connected between V_INand SW. In the first cycle of operation, the transistor is closed and the diode is reverse

biased. Energy is collected in the inductor and the load current is supplied by Cout and the rising current through

the inductor. During the second cycle, the transistor is open and the diode is forward biased due to the fact that

the inductor current cannot instantaneously change direction. The energy stored in the inductor is transferred to

the load and output capacitor. The ratio of these two cycles determines the output voltage. The output voltage is

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defined approximately as: D = V_OUT/ V_INand D' = (1 - D) where D is the duty cycle of the switch. D and D' are

required for design calculations.

7.3.2 Fixed Frequency PWM Control

The LV2862 has two fixed frequency options and implements peak current mode control. The output voltage is

compared through external resistors on the FB pin to an internal voltage reference by an error amplifier that

drives the internal COMP node. An internal oscillator initiates the turnon of the high-side power switch. The error

amplifier output is compared to the high-side power switch current. When the power switch current reaches the

level set by the internal COMP voltage, the power switch is turned off. The internal COMP node voltage

increases and decreases as the output current increases and decreases. The device implements a current limit

by clamping the COMP node voltage to a maximum level.

7.3.3 Eco-mode

The LV2862 operates in Eco-mode at light load currents to improve efficiency by reducing switching and gate

drive losses. For Eco-mode operation, the LV2862 senses peak current, not average or load current, so the load

current where the device enters Eco-mode is dependent on V_IN, V_OUT, and the output inductor value. When the

load current is low and the output voltage is within regulation, the device enters ECO mode (see 图 8-10) and

draws only 28-µA input quiescent current.

7.3.4 Bootstrap Voltage (CB)

The LV2862 has an integrated boot regulator, and requires a small ceramic capacitor between the CB and SW

pins to provide the gate drive voltage for the high-side MOSFET. The CB capacitor is refreshed when the high-

side MOSFET is off and the low-side diode conducts.

To improve dropout, the LV2862 is designed to operate at 96% duty cycle as long as the CB to SW pin voltage is

greater than 3 V. When the voltage from CB to SW drops below 3 V, the high-side MOSFET is turned off using

an UVLO circuit which allows the low-side diode to conduct and refresh the charge on the CB capacitor.

Because the supply current sourced from the CB capacitor is low, the high-side MOSFET can remain on for

more switching cycles than is required to refresh the capacitor, thus the effective duty cycle of the switching

regulator is high.

Attention must be taken in maximum duty cycle applications with light load. To ensure SW can be pulled to

ground to refresh the CB capacitor, an internal circuit charges the CB capacitor when the load is light or the

device is working in dropout condition.

7.3.5 Enable (SHDN) and VIN Undervoltage Lockout (UVLO)

The LV2862 SHDN pin is a high-voltage tolerant input with an internal pullup circuit. The device can be enabled

even if the SHDN pin is floating. The regulator can also be turned on using 1.25 V or higher logic signals. It can

be used if the use of a higher voltage is desired due to system or other constraints. A 100-kΩ or larger resistor is

recommended between the applied voltage and the SHDN pin to protect the device. When SHDN is pulled down

to 0 V, the chip is turned off and enters the lowest shutdown current mode. In shutdown mode, the supply current

is decreased to approximately 1 µA. If the shutdown function is not to be used, the SHDN pin can be tied to V_IN

through a 100-kΩ resistor. The maximum voltage to the SHDN pin must not exceed 60 V. The LV2862 has an

internal UVLO circuit to shut down the output if the input voltage falls below an internally fixed UVLO threshold

level. This ensures that the regulator is not latched into an unknown state during low input voltage conditions.

The regulator powers up when the input voltage exceeds the voltage level. If there is a requirement for a higher

UVLO voltage, the SHDN pin can be used to adjust the input voltage UVLO by using external resistors.

7.3.6 Setting the Output Voltage

The output voltage is set using the feedback pin and a resistor divider connected to the output as shown on the

front page schematic. The feedback pin voltage is 0.765 V, so the ratio of the feedback resistors sets the output

voltage according to 方程式1:

V_OUT= 0.765 V (1 + (R1 / R2))

(1)

English Data Sheet: SNVSA49

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Typically, R2 is given as 1 kΩ–100 kΩ for a starting value. To solve for R1 given R2 and V_OUT, use R1 = R2

((V_OUT/ 0.765 V) –1).

7.3.7 Current Limit

The LV2862 implements current mode control which uses the internal COMP voltage to turn off the high-side

MOSFET on a cycle-by-cycle basis. Each cycle, the switch current and internal COMP voltage are compared.

When the peak switch current intersects the COMP voltage, the high-side switch is turned off. During overcurrent

conditions that pull the output voltage low, the error amplifier responds by driving the COMP node high,

increasing the switch current. The error amplifier output is clamped internally, which functions as a switch current

limit.

7.3.8 Thermal Shutdown

The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 170°C

(typ). The thermal shutdown forces the device to stop switching when the junction temperature exceeds the

thermal trip threshold. After the junction temperature decreases below 160°C (typ), the device reinitiates the

power-up sequence.

7.4 Device Functional Modes

This device does not have any device functional modes.

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The LV2862 is a PWM DC/DC buck (step-down) regulator. With a wide input range from 4 V to 60 V, it is suitable

for a wide range of applications from, industrial to automotive, for power conditioning from unregulated source.

Soft start and compensation circuits are implemented internally, which allow the device to be used with

minimized external components.

8.2 Typical Application

VIN

Cin

2.2 µF

VIN

100 k

Cboot

100 nF

22 µH

5 V, 0.6 A

SHDN

LV2862

Cout

10 µF

54.9 k

GND

10 k

图8-1. Application Circuit, 5-V Output

8.2.1 Design Requirements

8.2.1.1 Design Guide –Step By Step Design Procedure

表 8-1 details the design of a high frequency switching regulator using ceramic output capacitors. A few

parameters must be known to start the design process. These parameters are typically determined at the system

level:

表8-1. Design Parameters

Input Voltage, V_IN

9 V to 16 V, Typical 12 V

Output Voltage, V_OUT

5.0 V ± 3%

Maximum Output Current Example I_{O_max}

Minimum Output Current Example I_{O_min}

Transient Response 0.03 A to 0.6 A

Output Voltage Ripple

0.6 A

0.03 A

Switching Frequency f_SW

770 kHz

Overvoltage Peak Value

Undervoltage Value

106% of Output Voltage

91% of Output Voltage

Target during Load Transient

8.2.2 Detailed Design Procedure

8.2.2.1 Selecting the Switching Frequency

The first step is to decide on a switching frequency for the regulator. Typically, choose the highest switching

frequency possible because this switching frequency produces the smallest solution size. The high switching

frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that

English Data Sheet: SNVSA49

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switches at a lower frequency. The switching frequency that can be selected is limited by the minimum on-time of

the internal power switch, the input voltage and the output voltage, and the frequency shift limitation. For this

example, the output voltage is 5 V, the maximum input voltage is 16 V, and a switching frequency of 770 kHz is

used.

8.2.2.2 Output Inductor Selection

The most critical parameters for the inductor are the inductance, peak current, and the DC resistance. The

inductance is related to the peak-to-peak inductor ripple current, the input, and the output voltages. Because the

ripple current increases with the input voltage, the maximum input voltage is always used to determine the

inductance. To calculate the minimum value of the output inductor, use 方程式 1. A reasonable value for the

ripple current is 40% (K_IND) of the DC output current. For this design example, the minimum inductor value is

calculated to be 20.4 µH, and a nearest standard value was chosen: 22 µH. For the output filter inductor, it is

important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor

current can be found in 方程式 3 and 方程式 4. The inductor ripple current is 0.22 A, and the RMS current is 0.6

A. As the equation set demonstrates, lower ripple currents reduce the output voltage ripple of the regulator but

require a larger value of inductance. A good starting point for most applications is 22 μH with a 1.6-A current

rating. Using a rating near 1.6 A enables the LV2862 to current limit without saturating the inductor. This is

preferable to the LV2862 going into thermal shutdown mode and the possibility of damaging the inductor if the

output is shorted to ground or other long-term overload.

V_{in max}-V_out

I_oì K_IND

V_out

L_{o min}

I_ripple

I_L-RMS

V_{in max}ì f_sw

(2)

(3)

V_outì(V_{in max}-V_out

V_{in max}ì L_oì f_sw

)

I_o

I_ripple

(4)

(5)

I_ripple

I_{L- peak}= I_o+

8.2.2.3 Output Capacitor Selection

The selection of C_OUTis mainly driven by three primary considerations. The output capacitor determines the

modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The

output capacitance needs to be selected based on the most stringent of these three criteria.

The first criterion is the desired response to a large change in the load current. The regulator usually needs two

or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty

cycle to react to the change. The output capacitance must be large enough to supply the difference in current for

two clock cycles while only allowing a tolerable amount of droop in the output voltage. 方程式 5 shows the

minimum output capacitance necessary to accomplish this. The transient load response is specified as a 3%

change in V_OUTfor a load step from 0.03 A to 0.6 A (full load), ΔI_OUT= 0.6 - 0.03 = 0.57 A and ΔV_OUT= 0.03 ×

5 = 0.15 V. Using these numbers gives a minimum capacitance of 10.8 µF. For ceramic capacitors, the ESR is

usually small enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higher

ESR that must be taken into account.

The stored energy in the inductor produces an output voltage overshoot when the load current rapidly

decreases. The output capacitor must also be sized to absorb energy stored in the inductor when transitioning

from a high load current to a lower load current. 方程式 6 is used to calculate the minimum capacitance to keep

the output voltage overshoot to a desired value. Where L is the value of the inductor, I_OH, is the output current

under heavy load, I_OLis the output under light load, V_fis the final peak output voltage, and V_iis the initial

capacitor voltage. For this example, the worst case load step is from 0.6 A to 0.03 A. The output voltage

increases during this load transition and the stated maximum in our specification is 3% of the output voltage.

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This makes V_{o_overshoot}= 1.03 × 5 = 5.15 V. V_iis the initial capacitor voltage which is the nominal output voltage

of 5 V. Using these numbers in 方程式6 yields a minimum capacitance of 5.2 µF.

方程式 7 calculates the minimum output capacitance needed to meet the output voltage ripple specification

where f_SWis the switching frequency, V_{o_ripple}is the maximum allowable output voltage ripple, and I_{L_ripple}is the

inductor ripple current. 方程式 7 yields 0.26 µF. 方程式 8 calculates the maximum ESR an output capacitor can

have to meet the output voltage ripple specification. indicates the ESR must be less than 680 mΩ.

Additional capacitance de-ratings for aging, temperature, and dc bias must be factored in which increases this

minimum value. For this example, 10-µF ceramic capacitors are used. Capacitors in the range of 10 µF–100 µF

are a good starting point with an ESR of 0.7 Ω or less.

2ì DI_out

fswì DV_out

C_out

(6)

(7)

(Ioh²- Iol²)

(Vf ²-Vi²)

C_out> L_oì

C_out

V_{o _ ripple}

8ì fsw

I_{L _ ripple}

(8)

(9)

V_{o _ ripple}

R_ESR

I_{L _ ripple}

8.2.2.4 Schottky Diode Selection

The breakdown voltage rating of the diode is preferred to be 25% higher than the maximum input voltage. In the

target application, the current rating for the diode must be equal to the maximum output current for best reliability

in most applications. In cases where the input voltage is not much greater than the output voltage, the average

diode current is lower. In this case, it is possible to use a diode with a lower average current rating,

approximately (1 - D) × I_OUT. However, the peak current rating must be higher than the maximum load current. A

0.5-A to 1-A rated diode is a good starting point.

8.2.2.5 Input Capacitor Selection

A low ESR ceramic capacitor is needed between the VIN pin and ground pin. This capacitor prevents large

voltage transients from appearing at the input. Use a 2.2 µF–10 µF value with X5R or X7R dielectric.

Depending on construction, the value of a ceramic capacitor can decrease up to 50% of its nominal value when

rated voltage is applied. Consult with the capacitor manufacturer's data sheet for information on capacitor

derating over voltage and temperature. The capacitor must also have a ripple current rating greater than the

maximum input current ripple of the LV2862. The input ripple current can be calculated using 方程式10 and 方程

式11.

For this example design, one 4.7-µF, 50-V capacitor is selected. The input capacitance value determines the

input ripple voltage of the regulator. The input voltage ripple can be calculated using 方程式10. Using the design

example values, I_outmax= 0.6 A, C_in= 2.2 µF, and f_sw= 770 kHz yields an input voltage ripple of 97 mV and an

RMS input ripple current of 0.3 A.

(V_{in min}-V_out

)

V_out

I_cirms= I_out

V_{in min}

in min

(10)

I_{out max}ì 0.25

C_inì fsw

DV_in

(11)

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English Data Sheet: SNVSA49

LV2862

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ZHCSS74B –JANUARY 2015 –REVISED JUNE 2023

8.2.2.5.1 Bootstrap Capacitor Selection

A 0.1-μF ceramic capacitor or larger is recommended for the bootstrap capacitor (C_BOOT). For applications

where the input voltage is close to output voltage, a larger capacitor is recommended, generally 0.1 µF to 1 µF to

ensure plenty of gate drive for the internal switches and a consistently low R_DSON. A ceramic capacitor with an

X7R or X5R grade dielectric with a voltage rating of 10 V or higher is recommended because of the stable

characteristics over temperature and voltage.

表8-2. Output Voltage Inductor and Capacitor Combinations

P/N

V_OUT(V)

L (µH)

C_OUT(µF)

R1 (kΩ)

54.9 (1%)

64.9 (1%)

147 (1%)

R2 (kΩ)

10 (1%)

LV2862X

5.7

8.2.2.5.1.1 Typical Application Circuits

VIN

Cin

2.2 µF

VIN

100 k

22 µH

Cboot

100 nF

5.7 V, 0.6 A

SHDN

LV2862

Cout

64.9 k

10 µF

GND

10 k

图8-2. Application Circuit, 5.7-V Output

VIN

Cin

2.2 µF

22 µH

Cboot

100 nF

100 k

12 V, 0.6 A

SHDN

LV2862

Cout

10 µF

147 k

GND

10 k

图8-3. Application Circuit, 12-V Output

表 8-2 lists the recommended typical output voltage inductor/capacitor combinations for optimized total solution

size.

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English Data Sheet: SNVSA49

LV2862

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ZHCSS74B –JANUARY 2015 –REVISED JUNE 2023

8.2.3 Application Curves

Unless otherwise specified the following conditions apply: V_IN= 12 V, f_SW= 770 kHz, L = 22 µH, C_OUT= 10 µF,

T_A= 25°C

V_OUT(50 mV/DIV, AC coupled)

V_OUT(10 mV/DIV, AC coupled)

V_SW(5 V/DIV)

I_INDUCTOR(0.5 A/DIV)

Time (1 µs/DIV)

Time (800 µs/DIV)

V_OUT= 5 V

I_OUT= 600 mA

V_OUT= 5 V

图8-4. Switching Node and Output Voltage

图8-5. Load Transient Between 0.1 A and 0.6 A

Waveform

V_SHDN(5 V/DIV)

V_OUT(5 V/DIV)

V_SHDN(5 V/DIV)

V_OUT(5 V/DIV)

I_Inductor(1 A/DIV)

Time (800 µs/DIV)

Time (200 µs/DIV)

V_IN= 15 V

V_OUT= 12 V / 600 mA

V_IN= 15 V

V_OUT= 12 V / 600 mA

图8-6. Start-up Waveform

图8-7. Shutdown Waveform

V_SHDN(5 V/DIV)

V_OUT(5 V/DIV)

V_SHDN(5 V/DIV)

V_OUT(5 V/DIV)

I_Inductor(0.5 A/DIV)

Time (2 ms/DIV)

Time (200 µs/DIV)

V_IN= 12 V

V_OUT= 5 V / 600 mA

V_IN= 12 V

V_OUT= 5 V / 600 mA

图8-8. Start-up Waveform

图8-9. Shutdown Waveform

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LV2862

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ZHCSS74B –JANUARY 2015 –REVISED JUNE 2023

V_OUT(20 mV/DIV, AC coupled)

I_INDUCTOR(100 mA/DIV)

V_SW(5 V/DIV)

Time (200 µs/DIV)

V_IN= 12 V

V_OUT= 5 V / No Load

图8-10. Eco-mode Operation

8.3 Power Supply Recommendations

The LV2862 is designed to operate from an input voltage supply range between 4 V and 60 V. This input supply

must be able to withstand the maximum input current and maintain a voltage above 4 V. The resistance of the

input supply rail must be low enough that an input current transient does not cause a high enough drop at the

LV2862 supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply is

located more than a few inches from the LV2862, additional bulk capacitance can be required in addition to the

ceramic input capacitors.

8.4 Layout

8.4.1 Layout Guidelines

Layout is a critical portion of good power supply design. The following guidelines helps users design a PCB with

the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.

1. The feedback network, resistors R1 and R2, must be kept close to the FB pin and away from the inductor to

minimize coupling noise into the feedback pin.

2. The input capacitor C_INmust be placed close to the V_INpin. This reduces copper trace inductance which

affects input voltage ripple of the IC.

3. The inductor L1 must be placed close to the SW pin to reduce magnetic and electrostatic noise.

4. The output capacitor C_OUTmust be placed close to the junction of L1 and the diode D1. The L1, D1, and

C_OUTtrace must be as short as possible to reduce conducted and radiated noise.

5. The ground connection for the diode, C_INand C_OUTmust be tied to the system ground plane in only one spot

(preferably at the C_OUTground point) to minimize conducted noise in the system ground plane.

6. For more detail on switching power supply layout considerations, see Application Note AN-1149, Layout

Guidelines for Switching Power Supplies.

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English Data Sheet: SNVSA49

LV2862

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ZHCSS74B –JANUARY 2015 –REVISED JUNE 2023

8.4.2 Layout Example

图8-11. Layout Example

English Data Sheet: SNVSA49

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LV2862

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ZHCSS74B –JANUARY 2015 –REVISED JUNE 2023

9 Device and Documentation Support

9.1 Documentation Support

9.1.1 Related Documentation

Texas Instruments, Layout Guidelines for Switching Power Supplies application report

9.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

9.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

9.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

9.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

9.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: LV2862

English Data Sheet: SNVSA49

PACKAGE OPTION ADDENDUM

www.ti.com

22-May-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LV2862XLVDDCR

LV2862XLVDDCT

LV2862YDDCR

LV2862YDDCT

ACTIVE SOT-23-THIN

DDC

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

C02X

C02Y

Samples

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

22-May-2023

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Jul-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LV2862XLVDDCR

LV2862XLVDDCT

LV2862YDDCR

LV2862YDDCT

SOT-23-

THIN

DDC

3000

250

178.0

180.0

178.0

8.4

3.2

3.1

3.2

1.4

1.1

1.4

4.0

8.0

SOT-23-

THIN

3.2

SOT-23-

THIN

250

3.05

3.2

SOT-23-

THIN

3000

250

SOT-23-

THIN

3.2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Jul-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LV2862XLVDDCR

LV2862XLVDDCT

LV2862YDDCR

LV2862YDDCT

SOT-23-THIN

DDC

3000

250

208.0

183.0

208.0

191.0

183.0

191.0

35.0

20.0

35.0

250

3000

250

Pack Materials-Page 2

PACKAGE OUTLINE

DDC0006A

SOT-23 - 1.1 max height

SMALL OUTLINE TRANSISTOR

3.05

2.55

1.1

0.7

1.75

1.45

0.1 C

PIN 1

INDEX AREA

4X 0.95

1.9

3.05

2.75

0.5

0.3

0.1

TYP

0.0

0.2

C A B

0 -8 TYP

0.25

GAGE PLANE

SEATING PLANE

0.20

0.12

TYP

0.6

0.3

TYP

4214841/C 04/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Reference JEDEC MO-193.

www.ti.com

EXAMPLE BOARD LAYOUT

DDC0006A

SOT-23 - 1.1 max height

SMALL OUTLINE TRANSISTOR

SYMM

6X (1.1)

6X (0.6)

SYMM

4X (0.95)

(R0.05) TYP

(2.7)

LAND PATTERN EXAMPLE

EXPLOSED METAL SHOWN

SCALE:15X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

SOLDERMASK DETAILS

4214841/C 04/2022

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DDC0006A

SOT-23 - 1.1 max height

SMALL OUTLINE TRANSISTOR

SYMM

6X (1.1)

6X (0.6)

SYMM

4X(0.95)

(R0.05) TYP

(2.7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL

SCALE:15X

4214841/C 04/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LV2862XLVDDCR [TI]

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