LVCR162245 [TI]
16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS; 具有三态输出的16位总线收发器型号: | LVCR162245 |
厂家: | TEXAS INSTRUMENTS |
描述: | 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS |
文件: | 总12页 (文件大小:308K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN74LVCR162245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES047E–AUGUST 1995–REVISED MARCH 2005
FEATURES
DGG OR DL PACKAGE
(TOP VIEW)
•
Member of the Texas Instruments Widebus™
Family
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
1OE
1A1
1A2
GND
1A3
1A4
•
•
•
•
Operates From 2.7 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 8.5 ns at 3.3 V
2
3
4
Typical VOLP (Output Ground Bounce) < 0.8 V
5
at VCC = 3.3 V, TA = 25°C
6
7
V
CC
V
CC
•
•
•
Typical VOHV (Output VOH Undershoot) > 2 V at
VCC = 3.3 V, TA = 25°C
8
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
9
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
All Outputs Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
•
•
Latch-Up Performance Exceeds 250 mA Per
JEDEC Standard JESD-17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
V
CC
V
CC
2B5
2B6
GND
2B7
2B8
2DIR
2A5
2A6
GND
2A7
2A8
2OE
DESCRIPTION/ORDERING INFORMATION
This 16-bit (dual-octal) noninverting bus transceiver is
designed for 2.7-V to 3.6-V VCC operation.
The SN74LVCR162245 is designed for asynchronous
communication
between
data
buses.
The
control-function implementation minimizes external
timing requirements.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the
A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR)
input. The output-enable (OE) input can be used to disable the device so that the buses effectively are isolated.
All outputs, which are designed to sink up to 12 mA, include 26-Ω resistors to reduce overshoot and undershoot.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input
circuit and is not disabled by OE or DIR.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74LVCR162245DL
TOP-SIDE MARKING
LVCR162245
Tube
SSOP – DL
Tape and reel
Tape and reel
SN74LVCR162245DLR
SN74LVCR162245DGGR
SN74LVCR162245KR
–40°C to 85°C
TSSOP – DGG
LVCR162245
LEP245
VFBGA – GQL
Tape and reel
VFBGA – ZQL (Pb-free)
74LVCR162245ZQLR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVCR162245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES047E–AUGUST 1995–REVISED MARCH 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
GQL OR ZQL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
TERMINAL ASSIGNMENTS(1)
1
2
3
4
5
6
A
B
C
D
E
F
1DIR
1B2
1B4
1B6
1B8
2B1
2B3
2B5
2B7
2DIR
NC
NC
NC
NC
1OE
1A2
1A4
1A6
1A8
2A1
2A3
2A5
2A7
2OE
1B1
1B3
1B5
1B7
2B2
2B4
2B6
2B8
NC
GND
VCC
GND
GND
VCC
GND
1A1
1A3
1A5
1A7
2A2
2A4
2A6
2A8
NC
G
H
J
GND
VCC
GND
NC
GND
VCC
GND
NC
K
(1) NC - No internal connection
FUNCTION TABLE
(EACH 8-BIT SECTION)
INPUTS
OPERATION
OE
DIR
L
L
L
B data to A bus
A data to B bus
Isolation
H
H
X
2
SN74LVCR162245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES047E–AUGUST 1995–REVISED MARCH 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
1
1DIR
1A1
48
1OE
47
2
1B1
To Seven Other Channels
24
2DIR
2A1
25
2OE
2B1
36
13
Pin numbers shown are for the DGG and DL packages.
3
SN74LVCR162245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES047E–AUGUST 1995–REVISED MARCH 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
–0.5
MAX
UNIT
VCC
VI
Supply voltage range
Input voltage range
4.6
VCC + 4.6
VCC + 0.5
VCC + 0.5
–50
V
Except I/O ports(2)
I/O ports(2)(3)
V
VO
IIK
Output voltage range(2)(3)
Input clamp current
V
VI < 0
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0 or VO > VCC
VO = 0 to VCC
±50
Continuous output current
Continuous current through VCC or GND
±50
±100
DGG package
DL package
70
θJA
Package thermal impedance(4)
63
°C/W
°C
GQL/ZQL package
42
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This value is limited to 4.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
2.7
2
MAX UNIT
VCC
VIH
VIL
VI
Supply voltage
3.6
V
V
V
V
V
High-level input voltage
Low-level input voltage
Input voltage
VCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
0.8
VCC
VCC
–8
0
0
VO
Output voltage
VCC = 2.7 V
VCC = 3 V
VCC = 2.7 V
VCC = 3 V
IOH
High-level output current
Low-level output current
mA
mA
–12
8
IOL
12
∆t/∆V
Input transition rise or fall rate
Operating free-air temperature
10
ns/V
TA
–40
85
°C
(1) All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI
application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
SN74LVCR162245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES047E–AUGUST 1995–REVISED MARCH 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
VCC
MIN TYP(2)
VCC – 0.2
MAX UNIT
IOH = –100 µA
IOH = –4 mA,
IOH = –8 mA,
IOH = –6 mA,
IOH = –12 mA,
IOL = 100 µA
IOL = 4 mA,
MIN to MAX
VIH = 2 V
VIH = 2 V
VIH = 2 V
VIH = 2 V
2.2
2
2.7 V
VOH
V
2.4
2
3 V
MIN to MAX
2.7 V
0.2
0.4
VIL = 0.8 V
VIL = 0.8 V
VIL = 0.8 V
VIL = 0.8 V
VOL
IOL = 8 mA,
0.6
0.55
0.8
V
IOL = 6 mA,
3 V
3.6 V
3 V
IOL = 12 mA,
VI = VCC or GND
VI = 0.8 V
Il
±5
µA
µA
75
Il(hold)
VI = 2 V
–75
VI = 0 to 3.6 V
3.6 V
3.6 V
±500
±10
20
µA
µA
(3)
IOZ
VO = 0 V or (VCC to 5.5 V)
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V(4)
ICC
IO = 0
3.6 V
µA
20
∆ICC
Ci
One input at VCC – 0.6 V, Other inputs at VCC or GND
VI = VCC or GND
2.7 V to 3.6 V
3.3 V
500
µA
pF
pF
Control inputs
A or B ports
2.5
3.5
Cio
VO = VCC or GND
3.3 V
(1) For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
(2) All typical values are at VCC = 3.3 V, TA = 25°C.
(3) For the total leakage current in an I/O port, please consult the II(hold) specification for the input voltage condition 0 V < VI < VCC, and the
IOZ specification for the input voltage conditions VI = 0 V or VI = VCC to 5.5 V. The bus-hold current, at input voltage greater than VCC, is
negligible.
(4) This applies in the disabled state only.
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see
Figure 1)
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX
MIN
1.5
1.5
1.5
MAX
tpd
ten
tdis
A or B
OE
B or A
A or B
A or B
1.5
1.5
1.5
7.5
9
8.5
10
ns
ns
ns
OE
7.5
8.5
Operating Characteristics
VCC = 3.3 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Outputs enabled
Outputs disabled
20
2
Cpd
Power dissipation capacitance per transceiver
CL = 50 pF, f = 10 MHz
pF
5
SN74LVCR162245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES047E–AUGUST 1995–REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION
6 V
Open
TEST
S1
t
/t
Open
6 V
GND
S1
500 Ω
PLH PHL
From Output
Under Test
t
t
/t
PLZ PZL
GND
/t
PHZ PZH
C = 50 pF
L
500 Ω
(see Note A)
2.7 V
LOAD CIRCUIT FOR OUTPUTS
1.5 V
Timing Input
Data Input
0 V
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Input
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
t
t
t
PLZ
PZL
t
t
t
PHL
PLH
Output
Waveform 1
S1 at 6 V
3 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
− 0.3 V
OH
1.5 V
1.5 V
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
PACKAGE OPTION ADDENDUM
www.ti.com
24-Feb-2006
PACKAGING INFORMATION
Orderable Device
74LVCR162245DGGRE4
74LVCR162245DGGRG4
74LVCR162245DLG4
74LVCR162245DLRG4
74LVCR162245ZQLR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
48
48
48
48
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
SSOP
SSOP
DGG
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
ZQL
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
SN74LVCR162245DGGR
SN74LVCR162245DL
SN74LVCR162245DLR
SN74LVCR162245KR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
SSOP
SSOP
DGG
DL
48
48
48
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
GQL
1000
TBD
SNPB
Level-1-240C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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