M3851010304BGA [TI]

Voltage Comparator;


型号：	M3851010304BGA
厂家：	TEXAS INSTRUMENTS
描述：	Voltage Comparator
文件：	总22页 (文件大小：802K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM111JAN

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SNOSAM9B –JULY 2008–REVISED MARCH 2013

LM111JAN Voltage Comparator

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FEATURES

DESCRIPTION

The LM111 is a voltage comparator that has input

currents nearly a thousand times lower than devices

such as the LM106 or LM710. It is also designed to

operate over a wider range of supply voltages: from

standard ±15V op amp supplies down to the single

5V supply used for IC logic. The output is compatible

with RTL, DTL and TTL as well as MOS circuits.

Further, it can drive lamps or relays, switching

voltages up to 50V at currents as high as 50 mA.

•

Operates from Single 5V Supply

Input Current: 200 nA max. Over Temperature

Offset Current: 20 nA max. Over Temperature

Differential Input Voltage Range: ±30V

Power Consumption: 135 mW at ±15V

Power Supply Voltage, single 5V to ±15V

Offset Voltage Null Capability

Strobe Capability

Both the inputs and the outputs of the LM111 can be

isolated from system ground, and the output can

drive loads referred to ground, the positive supply or

the negative supply. Offset balancing and strobe

capability are provided and outputs can be wire

OR'ed. Although slower than the LM106 and LM710

(200 ns response time vs 40 ns) the device is also

much less prone to spurious oscillations. The LM111

has the same pin configuration as the LM106 and

LM710.

Connection Diagrams

Note: Pin 4 connected to case

Figure 1. Metal Can Package

Top View

See Package Number LMC0008C

Figure 2. Dual-In-Line Package

Top View

See Package Number NAB0008A

Figure 3. Dual-In-Line Package

Top View

See Package Number J0014A

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LM111JAN

SNOSAM9B –JULY 2008–REVISED MARCH 2013

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Figure 4. See Package Number NAD0010A, NAC0010A

Schematic Diagram

Note: Pin connections shown on schematic diagram are for LMC0008C package.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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Absolute Maximum Ratings⁽¹⁾

Positive Supply Voltage

Negative Supply Voltage

Total Supply Voltage

+30.0V

-30.0V

36V

Output to Negative Supply Voltage

GND to Negative Supply Voltage

Differential Input Voltage

Sink Current

50V

30V

±30V

50mA

Input Voltage⁽²⁾

±15V

Power Dissipation⁽³⁾

8 LD CERDIP

400mW @ 25°C

330mW @ 25°C

400mW @ 25°C

10 seconds

10mA

8 LD Metal Can

10 LD CERPACK

10 LD Ceramic SOIC

14 LD CERDIP

Output Short Circuit Duration

Maximum Strobe Current

Operating Temperature Range

-55°C ≤ T_A≤ 125°C

120°C/W

Thermal Resistance

θ_JA

8 LD CERDIP (Still Air @ 0.5W)

8 LD CERDIP (500LF/Min Air flow @ 0.5W)

8 LD Metal Can (Still Air @ 0.5W)

8 LD Metal Can (500LF/Min Air flow @ 0.5W)

10 Ceramic SOIC (Still Air @ 0.5W)

10 Ceramic SOIC (500LF/Min Air flow @ 0.5W)

10 CERPACK (Still Air @ 0.5W)

10 CERPACK (500LF/Min Air flow @ 0.5W)

14 LD CERDIP (Still Air @ 0.5W)

14 LD CERDIP (500LF/Min Air flow @ 0.5W)

8 LD CERDIP

76°C/W

150°C/W

92°C/W

231°C/W

153°C/W

231°C/W

153°C/W

120°C/W

65°C/W

35°C/W

40°C/W

60°C/W

35°C/W

-65°C ≤ T_A≤ 150°C

175°C

θ_JC

8 LD Metal Can Pkg

10 LD Ceramic SOIC

10 LD CERPACK

14 LD CERDIP

Storage Temperature Range

Maximum Junction Temperature

Lead Temperature (Soldering, 60 seconds)

Voltage at Strobe Pin

300°C

V⁺-5V

Package Weight (Typical)

8 LD Metal Can

8 LD CERDIP

965mg

1100mg

250mg

10 LD CERPACK

10 LD Ceramic SOIC

14 LD CERDIP

225mg

TBD

ESD Rating⁽⁴⁾

300V

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(2) This rating applies for ±15V supplies. The positive input voltage limit is 30 V above the negative supply. The negative input voltage limit

is equal to the negative supply voltage or 30V below the positive supply, whichever is less.

(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by T_Jmax(maximum junction temperature),

θ_JA(package junction to ambient thermal resistance), and T_A(ambient temperature). The maximum allowable power dissipation at any

temperature is P_Dmax= (T_Jmax- T_A)/θ_JAor the number given in the Absolute Maximum Ratings, whichever is lower.

(4) Human body model, 1.5 kΩ in series with 100 pF.

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Recommended Operating Conditions

Supply Voltage

V_CC= ±15V_DC

Operating Temperature Range

-55°C ≤ T_A≤ 125°C

Quality Conformance Inspection

Mil-Std-883, Method 5005 — Group A

Subgroup

Description

Static tests at

Temperature (°C)

+25

+125

-55

Static tests at

Dynamic tests at

Functional tests at

Switching tests at

+25

+125

-55

+25

+125

-55

+25

+125

-55

LM111 JAN Electrical Characteristics DC Parameters

The following conditions apply, unless otherwise specified.

DC:

V_CC= ±15V, V_CM= 0

Sub-

groups

Symbol

Parameter

Conditions

V_I= 0V, R_S= 50Ω

Notes

Min

Max Unit

V_IO

Input Offset Voltage

-3.0

-4.0

-3.0

+3.0 mV

+4.0 mV

+3.0 mV

2, 3

+V_CC= 29.5V, -V_CC= -0.5V,

V_I= 0V, V_CM= -14.5V,

R_S= 50Ω

-4.0

-3.0

-4.0

+4.0 mV

+3.0 mV

+4.0 mV

2, 3

+V_CC= 2V, -V_CC= -28V,

V_I= 0V, V_CM= +13V,

R_S= 50Ω

2, 3

+V_CC= +2.5V, -V_CC= -2.5V,

V_I= 0V, R_S= 50Ω

-3.0

-4.0

-3.0

-4.5

-3.0

+3.0 mV

+4.0 mV

+3.0 mV

+4.5 mV

+3.0 mV

2, 3

V_IO

Raised Input Offset Voltage

V_I= 0V, R_S= 50Ω

See⁽¹⁾

2, 3

+V_CC= 29.5V, -V_CC= -0.5V,

V_I= 0V, V_CM= -14.5V,

R_S= 50Ω

-4.5

-3.0

-4.5

+4.5 mV

+3.0 mV

+4.5 mV

2, 3

+V_CC= 2V, -V_CC= -28V,

V_I= 0V, V_CM= +13V,

R_S= 50Ω

See⁽¹⁾

2, 3

I_IO

Input Offset Current

V_I= 0V, R_S= 50KΩ

-10

-20

-10

+10

+20

+10

1, 2

+V_CC= 29.5V, -V_CC= -0.5V,

V_I= 0V, V_CM= -14.5V,

R_S= 50KΩ

1, 2

-20

-10

-20

+20

+10

+20

+V_CC= 2V, -V_CC= -28V,

V_I= 0V, V_CM= +13V,

R_S= 50KΩ

1, 2

(1) Subscript (R) indicates tests which are performed with input stage current raised by connecting BAL and BAL/STB terminals to +V_CC

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LM111 JAN Electrical Characteristics DC Parameters (continued)

The following conditions apply, unless otherwise specified.

DC:

V_CC= ±15V, V_CM= 0

Sub-

Symbol

I_IO

Parameter

Conditions

V_I= 0V, R_S= 50KΩ

Notes

Min

Max Unit

groups

1, 2

Raised Input Offset Current

Input Bias Current

-25

-50

+25

+50

See⁽¹⁾

±I_IB

V_I= 0V, R_S= 50KΩ

-100 0.1

-150 0.1

1, 2

+V_CC= 29.5V, -V_CC= -0.5V,

V_I= 0V, V_CM= -14.5V,

R_S= 50KΩ

1, 2

-200 0.1

-150 0.1

-200 0.1

+V_CC= 2V, -V_CC= -28V,

V_I= 0V, V_CM= +13V,

R_S= 50KΩ

1, 2

V_OSt

Collector Output Voltage (Strobe) +V_I= Gnd, -V_I= 15V,

See⁽²⁾

1, 2, 3

I_St= -3mA, R_S= 50Ω

CMRR

Common Mode Rejection

Low Level Output Voltage

-28V ≤ -V_CC≤ -0.5V, R_S=50Ω, 2V ≤

+V_CC≤ 29.5V, R_S= 50Ω, -14.5V ≤

_CM≤ 13V,R_S= 50Ω

V_OL

+V_CC= 4.5V, -V_CC= Gnd,

I_O= 8mA, ±V_I= 0.5V,

V_ID= -6mV

See⁽³⁾

0.4

1, 2, 3

+V_CC= 4.5V, -V_CC= Gnd,

I_O= 8mA, ±V_I= 3V,

V_ID= -6mV

I_O= 50mA, ±VI = 13V,

V_ID= -5mV

See⁽³⁾

1.5

1, 2, 3

I_O= 50mA, ±VI = -14V,

V_ID= -5mV

I_CEX

Output Leakage Current

Input Leakage Current

+V_CC= 18V, -V_CC= -18V,

V_O= 32V

-1.0

500

I_IL

+V_CC= 18V, -V_CC= -18V,

+V_I= +12V, -V_I= -17V

-5.0

500

1, 2, 3

+V_CC= 18V, -V_CC= -18V,

+V_I= -17V, -V_I= +12V

+I_CC

Power Supply Current

6.0

7.0

1, 2

-I_CC

-5.0

-6.0

-25

1, 2

Δ V_IO/ Δ T

Δ I_IO/ Δ T

I_OS

Temperature Coefficient Input

Offset Voltage

25°C ≤ T ≤ 125°C

-55°C ≤ T ≤ 25°C

25°C ≤ T ≤ 125°C

-55°C ≤ T ≤ 25°C

See⁽⁴⁾

uV/°C

pA/°C

Temperature Coefficient Input

Offset Current

-100 100

-200 200

200

Short Circuit Current

V_O= 5V, t ≤ 10mS, -V_I= 0.1V,

+V_I= 0V

150

250

+V_IOadj.

-V_IOadj.

±A_VE

Input Offset Voltage (Adjustment) V_O= 0V, V_I= 0V, R_S= 50Ω

5.0

-5.0 mV

Voltage Gain (Emitter)

R_L= 600Ω

See⁽⁵⁾

V/mV

8.0

5, 6

(2) I_ST= −2mA at −55°C

(3) V_IDis voltage difference between inputs.

(4) Calculated parameter.

(5) Datalog reading in K=V/mV.

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LM111 JAN Electrical Characteristics AC Parameters

The following conditions apply, unless otherwise specified.

AC:

V_CC= ±15V, V_CM= 0

Sub-

groups

Symbol

Parameter

Conditions

Notes

Min Max

Unit

tR_LHC

tR_HLC

Response Time (Collector Output) V_OD(Overdrive) = -5mV,

C_L= 50pF, V_I= -100mV

300

640

300

500

7, 8B

Response Time (Collector Output) V_OD(Overdrive) = 5mV,

C_L= 50pF, V_I= 100mV

7, 8B

LM111 JAN Electrical Characteristics DC Drift Parameters

The following conditions apply, unless otherwise specified.

DC:

V_CC= ±15V, V_CM= 0

Delta calculations performed on JANS devices at group B , subgroup 5.

Sub-

groups

Symbol

V_IO

Parameter

Conditions

V_I= 0V, R_S= 50Ω

Notes

Min Max

Unit

Input Offset Voltage

-0.5

0.5

+V_CC= 29.5V, -V_CC= -0.5V,

V_I= 0V, V_CM= -14.5V,

R_S= 50Ω

+V_CC= 2V, -V_CC= -28V,

V_I= 0V, V_CM= +13V,

R_S= 50Ω

-0.5

0.5

±I_IB

Input Bias Current

V_I= 0V, R_S= 50KΩ

-12.5 12.5

+V_CC= 29.5V, -V_CC= -0.5V,

V_I= 0V, V_CM= -14.5V,

R_S= 50KΩ

+V_CC= 2V, -V_CC= -28V,

V_I= 0V, V_CM= +13V,

R_S= 50KΩ

-12.5 12.5

I_CEX

Output Leakage Current

+V_CC= 18V, -V_CC= -18V,

V_O= 32V

-5.0

5.0

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LM111 Typical Performance Characteristics

Input Bias Current

Figure 5.

Figure 6.

Input Bias Current

Figure 7.

Figure 8.

Input Bias Current

Figure 9.

Figure 10.

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LM111 Typical Performance Characteristics (continued)

Input Bias Current

Input Overdrives

Input Bias Current

Input Overdrives

Figure 11.

Figure 12.

Response Time for Various

Input Overdrives

Input Bias Current

Figure 13.

Figure 14.

Response Time for Various

Input Overdrives

Output Limiting Characteristics

Figure 15.

Figure 16.

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LM111 Typical Performance Characteristics (continued)

Supply Current

Figure 17.

Figure 18.

Leakage Currents

Figure 19.

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APPLICATION HINTS

CIRCUIT TECHNIQUES FOR AVOIDING

OSCILLATIONS IN COMPARATOR APPLICATIONS

When a high-speed comparator such as the LM111 is used with fast input signals and low source impedances,

the output response will normally be fast and stable, assuming that the power supplies have been bypassed (with

0.1 μF disc capacitors), and that the output signal is routed well away from the inputs (pins 2 and 3) and also

away from pins 5 and 6.

However, when the input signal is a voltage ramp or a slow sine wave, or if the signal source impedance is high

(1 kΩ to 100 kΩ), the comparator may burst into oscillation near the crossing-point. This is due to the high gain

and wide bandwidth of comparators such as the LM111. To avoid oscillation or instability in such a usage,

several precautions are recommended, as shown in Figure 20 below.

1. The trim pins (pins 5 and 6) act as unwanted auxiliary inputs. If these pins are not connected to a trim-pot,

they should be shorted together. If they are connected to a trim-pot, a 0.01 μF capacitor C1 between pins 5

and 6 will minimize the susceptibility to AC coupling. A smaller capacitor is used if pin 5 is used for positive

feedback as in Figure 20.

2. Certain sources will produce a cleaner comparator output waveform if a 100 pF to 1000 pF capacitor C2 is

connected directly across the input pins.

3. When the signal source is applied through a resistive network, R_S, it is usually advantageous to choose an

R_S′ of substantially the same value, both for DC and for dynamic (AC) considerations. Carbon, tin-oxide, and

metal-film resistors have all been used successfully in comparator input circuitry. Inductive wire wound

resistors are not suitable.

4. When comparator circuits use input resistors (e.g. summing resistors), their value and placement are

particularly important. In all cases the body of the resistor should be close to the device or socket. In other

words there should be very little lead length or printed-circuit foil run between comparator and resistor to

radiate or pick up signals. The same applies to capacitors, pots, etc. For example, if R_S=10 kΩ, as little as 5

inches of lead between the resistors and the input pins can result in oscillations that are very hard to damp.

Twisting these input leads tightly is the only (second best) alternative to placing resistors close to the

comparator.

5. Since feedback to almost any pin of a comparator can result in oscillation, the printed-circuit layout should be

engineered thoughtfully. Preferably there should be a ground plane under the LM111 circuitry, for example,

one side of a double-layer circuit card. Ground foil (or, positive supply or negative supply foil) should extend

between the output and the inputs, to act as a guard. The foil connections for the inputs should be as small

and compact as possible, and should be essentially surrounded by ground foil on all sides, to guard against

capacitive coupling from any high-level signals (such as the output). If pins 5 and 6 are not used, they should

be shorted together. If they are connected to a trim-pot, the trim-pot should be located, at most, a few inches

away from the LM111, and the 0.01 μF capacitor should be installed. If this capacitor cannot be used, a

shielding printed-circuit foil may be advisable between pins 6 and 7. The power supply bypass capacitors

should be located within a couple inches of the LM111. (Some other comparators require the power-supply

bypass to be located immediately adjacent to the comparator.)

6. It is a standard procedure to use hysteresis (positive feedback) around a comparator, to prevent oscillation,

and to avoid excessive noise on the output because the comparator is a good amplifier for its own noise. In

the circuit of Figure 21, the feedback from the output to the positive input will cause about 3 mV of

hysteresis. However, if R_Sis larger than 100Ω, such as 50 kΩ, it would not be reasonable to simply increase

the value of the positive feedback resistor above 510 kΩ. The circuit of Figure 22 could be used, but it is

rather awkward. See the notes in paragraph 7 below.

7. When both inputs of the LM111 are connected to active signals, or if a high-impedance signal is driving the

positive input of the LM111 so that positive feedback would be disruptive, the circuit of Figure 20 is ideal.

The positive feedback is to pin 5 (one of the offset adjustment pins). It is sufficient to cause 1 to 2 mV

hysteresis and sharp transitions with input triangle waves from a few Hz to hundreds of kHz. The positive-

feedback signal across the 82Ω resistor swings 240 mV below the positive supply. This signal is centered

around the nominal voltage at pin 5, so this feedback does not add to the V_OSof the comparator. As much as

8 mV of V_OScan be trimmed out, using the 5 kΩ pot and 3 kΩ resistor as shown.

8. These application notes apply specifically to the LM111 and LF111 families of comparators, and are

applicable to all high-speed comparators in general, (with the exception that not all comparators have trim

pins).

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Pin connections shown are for LM111H in the LMC0008C hermetic package

Figure 20. Improved Positive Feedback

Pin connections shown are for LM111H in the LMC0008C hermetic package

Figure 21. Conventional Positive Feedback

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Figure 22. Positive Feedback with High Source Resistance

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Typical Applications

Pin connections shown on schematic diagram and typical applications are for LMC0008C metal can package.

Offset Balancing

Strobing

Note: Do Not Ground Strobe Pin. Output is turned off when current

is pulled from Strobe Pin.

Figure 23.

Figure 24.

Increasing Input Stage Current

Detector for Magnetic Transducer

Note: Increases typical common mode slew from 7.0V/μs to 18V/μs.

Figure 25.

Figure 26.

Digital Transmission Isolator

Relay Driver with Strobe

*Absorbs inductive kickback of relay and protects IC from severe

voltage transients on V⁺⁺line.

Note: Do Not Ground Strobe Pin.

Figure 27.

Figure 28.

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Strobing off Both Input and Output Stages

Note:Typical input current is 50 pA with inputs strobed off.

Positive Peak Detector

Figure 29.

Zero Crossing Detector Driving MOS Logic

*Solid tantalum

Figure 30.

Figure 31.

Typical Applications

(Pin numbers refer to LMC0008C package)

Zero Crossing Detector Driving MOS Switch

100 kHz Free Running Multivibrator

*TTL or DTL fanout of two

Figure 32.

Figure 33.

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10 Hz to 10 kHz Voltage Controlled Oscillator

*Adjust for symmetrical square wave time when V_IN= 5 mV

†Minimum capacitance 20 pF Maximum frequency 50 kHz

Figure 34.

Driving Ground-Referred Load

Using Clamp Diodes to Improve Response

*Input polarity is reversed when using pin 1 as output.

Figure 35.

Figure 36.

TTL Interface with High Level Logic

*Values shown are for a 0 to 30V logic swing and a 15V threshold.

†May be added to control speed and reduce susceptibility to noise spikes.

Figure 37.

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Crystal Oscillator

Comparator and Solenoid Driver

Figure 38.

Figure 39.

Precision Squarer

Low Voltage Adjustable Reference Supply

*Solid tantalum

†Adjust to set clamp level

*Solid tantalum

Figure 40.

Figure 41.

Positive Peak Detector

Zero Crossing Detector Driving MOS Logic

*Solid tantalum

Figure 42.

Figure 43.

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Negative Peak Detector

Precision Photodiode Comparator

*Solid tantalum

*R2 sets the comparison level. At comparison, the photodiode has

less than 5 mV across it, decreasing leakages by an order of

magnitude.

Figure 44.

Figure 45.

Switching Power Amplifier

Figure 46.

Figure 47.

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REVISION HISTORY SECTION

Released

05/09/05

Revision

Section

Originator

Changes

New Release, Corporate

format

L. Lytle

1 MDS data sheets converted into one Corp.

data sheet format. MJLM111–X Rev 0D3 will

be archived.

03/26/2013

All Sections

Changed layout of National Data Sheet to TI

format

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PACKAGE OPTION ADDENDUM

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11-Apr-2013

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

JL111BGA

ACTIVE

TO-99

LMC

TBD

Call TI

-55 to 125

JL111BGA

JM38510/10304BGA Q

ACO

JM38510/10304BGA Q

JM38510/10304BGA

M38510/10304BGA

ACTIVE

LMC

-55 to 125

JL111BGA

JM38510/10304BGA Q

ACO

JM38510/10304BGA Q

JL111BGA

JM38510/10304BGA Q

ACO

JM38510/10304BGA Q

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LM111JAN, LM111JAN-SP :

Military: LM111JAN

•

Space: LM111JAN-SP

•

NOTE: Qualified Version Definitions:

Military - QML certified for Military and Defense Applications

•

Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

•

Addendum-Page 2

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