M4FR5969SRGZT-MLS [TI]
耐辐射加固保障混合信号微控制器 | RGZ | 48 | -55 to 105;
| 型号： | M4FR5969SRGZT-MLS |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 耐辐射加固保障混合信号微控制器 | RGZ | 48 | -55 to 105 时钟 控制器 微控制器 外围集成电路 装置 |
| 文件： | 总132页 (文件大小：2692K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MSP430FR5969-SP
ZHCSH89A –DECEMBER 2017–REVISED MARCH 2018
MSP430FR5969-SP 抗辐射加固混合信号微控制器
1 器件概述
1.1 特性
1
– 16 位循环冗余校验器 (CRC)
• 高性能模拟
• 抗辐射加固
(1)
– 扩展工作温度（-55°C 至 105°C）
– 16 通道模拟比较器
– 单粒子闩锁 (SEL) 在 125°C 下的抗扰度可达 72
MeV.cm2/mg
– 12 位模数转换器 (ADC)
具有内部基准和采样保持
和高达 16 个外部输入通道
– 辐射批次验收测试结果为 50krad
– 48 引脚 VQFN 塑料封装
– 单受控基线
• 多功能输入/输出端口
– 可每位、每字节和每字访问（成对访问）
– 所有端口上，从 LPM 中的边沿可选唤醒
– 所有端口上可编程上拉和下拉
• 代码安全性和加密
– 128 位或 256 位 AES 安全加密和解密协处理器
（只适用于 MSP430FR59xx）
– 针对随机数生成算法的随机数种子
• 增强型串行通信
– 延长了产品变更通知周期
– 产品可追溯性
– 延长了产品生命周期
• 嵌入式微控制器
– 时钟频率高达 16MHz 的 16 位精简指令集计算机
(RISC) 架构
– 宽电源电压范围
(2)
（1.8V 至 3.6V）
– eUSCI_A0 和 eUSCI_A1 支持
• 优化的超低功率模式
– 支持自动波特率侦测的通用异步收发器
– 工作模式：大约 100µA/MHz
– 待机（具有低功率低频内部时钟源 (VLO) 的
LPM3）：0.4µA（典型值）
(UART)
– IrDA 编码和解码
– SPI
(3)
– 实时时钟 (LPM3.5)：0.25µA（典型值）
– eUSCI_B0 支持
– 支持多个从器件寻址的 I2C
– SPI
– 关断 (LPM4.5)：0.02µA（典型值）
• 超低功耗铁电 RAM (FRAM)
– 高达 64KB 的非易失性存储器
– 超低功耗写入
– 硬件 UART
• 灵活时钟系统
– 125ns 每个字的快速写入（4ms 内写入 64KB）
– 具有 10 个可选厂家调整频率的定频数控振荡器
– 统一标准存储器 = 单个空间内的程序 + 数据 + 存
储
(DCO)
– 1015 写入周期持久性
– 抗辐射和非磁性
– 低功率低频内部时钟源 (VLO)
– 32kHz 晶振 (LFXT)
– 高频晶振 (HFXT)
• 智能数字外设
• 开发工具和软件
– 32 位硬件乘法器 (MPY)
– 3 通道内部 DMA
– 具有日历和报警功能的实时时钟 (RTC)
– 自由的专业开发环境 具有 EnergyTrace++™技术
– 开发套件 (MSP-TS430RGZ48C)
• 要获得完整的模块说明，请参见
《
– 5 个 16 位定时器，每个定时器具有多达 7 个捕
捉/比较寄存器
(1) 请参阅规格 部分中的 MSP430FR5969-SP EM 寿命降额表。
(2) 最小电源电压受 SVS 电平限制。
MSP430FR58xx，MSP430FR59xx，MSP430FR6
8xx 和 MSP430FR69xx 系列用户指南》
(3) 实时时钟 (RTC) 由 3.7pF 晶振计时。
1.2 应用
•
•
航天器分布式遥测和维护
传感器管理
•
数据日志
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLASEK0
MSP430FR5969-SP
ZHCSH89A –DECEMBER 2017–REVISED MARCH 2018
www.ti.com.cn
1.3 说明
MSP430™超低功耗 (ULP) FRAM 平台将独特的嵌入式 FRAM 和整体超低功耗系统架构组合在一起，从而
使得创新人员能够以较少的能源预算增加性能。FRAM 技术以低很多的功耗将 SRAM 的速度、灵活性和耐
久性与闪存的稳定性和可靠性组合在一起。
MSP430FR5969-SP 的超低功耗架构可提供七种低功耗模式，这七种模式均经过优化，能够在低功耗的情况
下对系统进行分布式遥测和维护。
MSP430FR5969-SP 的集成式混合信号 特性 使其非常适合用于下一代航天器的分布式遥测 应用 。对单粒
子闩锁的强大抗干扰性和电离辐射总剂量使得该器件得以应用于多种空间和辐射环境中。
器件信息(1)
等级
器件型号
封装(2)
48 引脚 VQFN
7.00mm × 7.00mm
M4FR5969SRGZT-MLS
MLS
HTQFP (48)
7.00mm × 7.00mm
M4FR5969SPHPT-MLS
MLS
(1) 要获得所有可用器件的最新部件、封装和订购信息，请参见封装选项附录（节 8）或浏览 TI 网站
www.ti.com.cn。
(2) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参见机械数据（节 8）。
1.4 功能框图
图 1-1 显示了器件的功能方框图。
PJ.x
P1.x, P2.x P3.x, P4.x
2x8 2x8
1x8
LFXIN,
HFXIN
LFXOUT,
HFXOUT
ADC12_B
I/O Ports
P1, P2
2x8 I/Os
I/O Ports
P3, P4
2x8 I/Os
I/O Port
PJ
1x8 I/Os
REF_A
MCLK
ACLK
Comp_E
(up to 16
standard
inputs,
up to 8
differential
inputs)
Clock
System
(up to 16
inputs)
Voltage
Reference
SMCLK
PA
1x16 I/Os
PB
1x16 I/Os
DMA
Controller
Channel
3
MAB
MDB
Bus
Control
Logic
CPUXV2
incl. 16
Registers
MPU
IP Encap
TA2
TA3
AES256
Power
Mgmt
FRAM
RAM
Security
Encryption,
Decryption
(128, 256)
Watchdog
Timer_A
2 CC
Registers
(int. only)
CRC16
MPY32
LDO
SVS
Brownout
64KB
48KB
32KB
2KB
1KB
EEM
(S: 3 + 1)
EnergyTrace++
MDB
MAB
JTAG
Interface
Spy-Bi-Wire
TB0
TA0
TA1
eUSCI_A0
eUSCI_A1
eUSCI_B0
Timer_B
7 CC
Timer_A
3 CC
Timer_A
3 CC
(I2C,
SPI)
RTC_B
(UART,
IrDA,
SPI)
Registers
(int, ext)
Registers
(int, ext)
Registers
(int, ext)
LPM3.5 Domain
Copyright © 2017, Texas Instruments Incorporated
图 1-1. 功能方框图
2
器件概述
版权 © 2017–2018, Texas Instruments Incorporated
MSP430FR5969-SP
www.ti.com.cn
ZHCSH89A –DECEMBER 2017–REVISED MARCH 2018
内容
1
器件概述.................................................... 1
5.2 CPU ................................................. 46
5.3 Operating Modes .................................... 47
5.4 Interrupt Vector Table and Signatures .............. 50
5.5 Memory Organization ............................... 53
5.6 Bootloader (BSL).................................... 53
5.7 JTAG Operation ..................................... 54
5.8 FRAM................................................ 55
1.1 特性 ................................................... 1
1.2 应用 ................................................... 1
1.3 说明 ................................................... 2
1.4 功能框图 .............................................. 2
修订历史记录............................................... 4
Terminal Configuration and Functions.............. 5
3.1 Pin Diagrams ......................................... 5
3.2 Signal Descriptions ................................... 6
3.3 Pin Multiplexing ..................................... 10
3.4 Connection of Unused Pins ......................... 10
Specifications ........................................... 11
4.1 Absolute Maximum Ratings......................... 11
4.2 ESD Ratings ........................................ 11
4.3 Recommended Operating Conditions............... 11
2
3
5.9
Memory Protection Unit Including IP Encapsulation 55
5.10 Peripherals .......................................... 56
5.11 Input and Output Diagrams ......................... 77
5.12 Device Descriptor (TLV) ........................... 104
5.13 Identification........................................ 106
Applications, Implementation, and Layout ...... 107
4
6
7
6.1
Software Best Practices for Radiation Effects
Mitigation........................................... 107
6.2
6.3
Device Connection and Layout Fundamentals .... 107
4.4
4.5
4.6
4.7
4.8
4.9
Active Mode Supply Current Into VCC Excluding
External Current .................................... 12
Typical Characteristics – Active Mode Supply
Currents ............................................. 13
Low-Power Mode (LPM0, LPM1) Supply Currents
Into VCC Excluding External Current ................ 13
Low-Power Mode (LPM2, LPM3, LPM4) Supply
Currents (Into VCC) Excluding External Current .... 14
Low-Power Mode (LPM3.5, LPM4.5) Supply
Peripheral- and Interface-Specific Design
Information ......................................... 111
器件和文档支持......................................... 113
7.1 入门和后续步骤 .................................... 113
7.2 工具和软件 ......................................... 114
7.3 文档支持 ........................................... 116
7.4 辐射信息 ........................................... 117
7.5 相关链接 ........................................... 117
7.6 社区资源 ........................................... 118
7.7 商标 ................................................ 118
7.8 静电放电警告....................................... 118
7.9 出口管制提示....................................... 118
7.10 术语表.............................................. 118
机械、封装和可订购信息 .............................. 119
Currents (Into VCC) Excluding External Current .... 15
Typical Characteristics, Current Consumption per
Module .............................................. 16
4.10 Thermal Resistance Characteristics ................ 16
4.11 Timing and Switching Characteristics............... 17
4.12 Emulation and Debug ............................... 45
Detailed Description ................................... 46
5.1 Overview ............................................ 46
5
8
版权 © 2017–2018, Texas Instruments Incorporated
内容
3
MSP430FR5969-SP
ZHCSH89A –DECEMBER 2017–REVISED MARCH 2018
www.ti.com.cn
2 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (December 2017) to Revision A
Page
•
已添加 添加了 PHP 封装选项 ....................................................................................................... 2
4
修订历史记录
Copyright © 2017–2018, Texas Instruments Incorporated
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Product Folder Links: MSP430FR5969-SP
MSP430FR5969-SP
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ZHCSH89A –DECEMBER 2017–REVISED MARCH 2018
3 Terminal Configuration and Functions
3.1 Pin Diagrams
Figure 3-1 shows the 48-pin RGZ package for the MSP430FR5969-SP MCU.
48 47 46 45 44 43 42 41 40 39 38 37
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P3.0/A12/C12
1
2
36 DVSS
35 P4.6
3
34 P4.5
4
33 P4.4/TB0.5
P3.1/A13/C13
5
32 P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
31 P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
30 P3.7/TB0.6
P3.2/A14/C14
6
P3.3/A15/C15
7
P4.7
8
29 P3.6/TB0.5
P1.3/TA1.2/UCB0STE/A3/C3
P1.4/TB0.1/UCA0STE/A4/C4
P1.5/TB0.2/UCA0CLK/A5/C5
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6
9
28 P3.5/TB0.4/COUT
27 P3.4/TB0.3/SMCLK
26 P2.2/TB0.2/UCB0CLK
25 P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
NOTE: TI recommends connecting the QFN package pad to VSS
.
NOTE: On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX.
NOTE: On devices with I2C BSL: P1.6: BSLSDA; P1.7: BSLSCL.
Figure 3-1. 48-Pin RGZ/PHP Package (Top View) – MSP430FR5969-SP
Copyright © 2017–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
5
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3.2 Signal Descriptions
describes the signals for all device variants and package options.
Signal Descriptions
TERMINAL
NO.(2)
I/O(1)
DESCRIPTION
NAME
RGZ and PHP
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TA0 CCR1 capture: CCI1A input, compare: Out1
External DMA trigger
P1.0/TA0.1/DMAE0/
RTCCLK/A0/C0/VREF-/
VeREF-
RTC clock calibration output (not available on MSP430FR5x5x devices)
Analog input A0 for ADC
1
I/O
Comparator input C0
Output of negative reference voltage
Input for an external negative reference voltage to the ADC
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TA0 CCR2 capture: CCI2A input, compare: Out2
TA1 input clock
P1.1/TA0.2/TA1CLK/
COUT/A1/C1/VREF+/
VeREF+
Comparator output
2
I/O
Analog input A1 for ADC
Comparator input C1
Output of positive reference voltage
Input for an external positive reference voltage to the ADC
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TA1 CCR1 capture: CCI1A input, compare: Out1
TA0 input clock
P1.2/TA1.1/TA0CLK/
COUT/A2/C2
3
I/O
Comparator output
Analog input A2 for ADC
Comparator input C2
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.0/A12/C12
P3.1/A13/C13
P3.2/A14/C14
4
5
6
I/O Analog input A12 for ADC
Comparator input C12
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
I/O Analog input A13 for ADC
Comparator input C13
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
I/O Analog input A14 for ADC
Comparator input C14
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
I/O Analog input A15 for ADC
P3.3/A15/C15
P4.7
7
8
Comparator input C15
I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TA1 CCR2 capture: CCI2A input, compare: Out2
I/O Slave transmit enable – eUSCI_B0 SPI mode
Analog input A3 for ADC
P1.3/TA1.2/UCB0STE/
A3/C3
9
Comparator input C3
(1) I = input, O = output
(2) N/A = not available
6
Terminal Configuration and Functions
Copyright © 2017–2018, Texas Instruments Incorporated
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ZHCSH89A –DECEMBER 2017–REVISED MARCH 2018
Signal Descriptions (continued)
TERMINAL
NO.(2)
I/O(1)
DESCRIPTION
NAME
RGZ and PHP
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR1 capture: CCI1A input, compare: Out1
I/O Slave transmit enable – eUSCI_A0 SPI mode
Analog input A4 for ADC
P1.4/TB0.1/UCA0STE/
A4/C4
10
11
Comparator input C4
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR2 capture: CCI2A input, compare: Out2
P1.5/TB0.2/UCA0CLK/
A5/C5
Clock signal input – eUSCI_A0 SPI slave mode,
I/O
Clock signal output – eUSCI_A0 SPI master mode
Analog input A5 for ADC
Comparator input C5
General-purpose digital I/O
Test data output port
Switch all PWM outputs high impedance input – TB0
PJ.0/TDO/TB0OUTH/
SMCLK/SRSCG1/C6
12
13
I/O
SMCLK output
Low-Power Debug: CPU Status Register Bit SCG1
Comparator input C6
General-purpose digital I/O
Test data input or test clock input
I/O MCLK output
PJ.1/TDI/TCLK/MCLK/
SRSCG0/C7
Low-Power Debug: CPU Status Register Bit SCG0
Comparator input C7
General-purpose digital I/O
Test mode select
PJ.2/TMS/ACLK/
SROSCOFF/C8
14
15
I/O ACLK output
Low-Power Debug: CPU Status Register Bit OSCOFF
Comparator input C8
General-purpose digital I/O
Test clock
PJ.3/TCK/
SRCPUOFF/C9
I/O
Low-Power Debug: CPU Status Register Bit CPUOFF
Comparator input C9
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.0/A8
P4.1/A9
P4.2/A10
P4.3/A11
16
17
18
19
I/O
Analog input A8 for ADC
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
I/O
Analog input A9 for ADC
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
I/O
Analog input A10 for ADC
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
I/O
Analog input A11 for ADC
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR0 capture: CCI0B input, compare: Out0
P2.5/TB0.0/UCA1TXD/
UCA1SIMO
20
I/O
Transmit data – eUSCI_A1 UART mode
Slave in, master out – eUSCI_A1 SPI mode
Copyright © 2017–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
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7
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Signal Descriptions (continued)
TERMINAL
NO.(2)
I/O(1)
DESCRIPTION
NAME
RGZ and PHP
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR1 compare: Out1
P2.6/TB0.1/UCA1RXD/
UCA1SOMI
21
I/O
I
Receive data – eUSCI_A1 UART mode
Slave out, master in – eUSCI_A1 SPI mode
Test mode pin – select digital I/O on JTAG pins
Spy-Bi-Wire input clock
TEST/SBWTCK
22
23
Reset input active low
RST/NMI/SBWTDIO
I/O Nonmaskable interrupt input
Spy-Bi-Wire data input/output
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR6 capture: CCI6B input, compare: Out6
Transmit data – eUSCI_A0 UART mode
I/O BSL Transmit (UART BSL)
P2.0/TB0.6/UCA0TXD/
UCA0SIMO/TB0CLK/
ACLK
24
Slave in, master out – eUSCI_A0 SPI mode
TB0 clock input
ACLK output
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR0 capture: CCI0A input, compare: Out0
Receive data – eUSCI_A0 UART mode
P2.1/TB0.0/UCA0RXD/
UCA0SOMI/TB0.0
25
26
I/O
BSL receive (UART BSL)
Slave out, master in – eUSCI_A0 SPI mode
TB0 CCR0 capture: CCI0A input, compare: Out0
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR2 compare: Out2
P2.2/TB0.2/UCB0CLK
I/O
Clock signal input – eUSCI_B0 SPI slave mode
Clock signal output – eUSCI_B0 SPI master mode
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
I/O TB0 CCR3 capture: CCI3A input, compare: Out3
SMCLK output
P3.4/TB0.3/SMCLK
P3.5/TB0.4/COUT
27
28
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
I/O TB0 CCR4 capture: CCI4A input, compare: Out4
Comparator output
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.6/TB0.5
P3.7/TB0.6
29
30
I/O
TB0 CCR5 capture: CCI5A input, compare: Out5
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
I/O
TB0 CCR6 capture: CCI6A input, compare: Out6
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR3 capture: CCI3B input, compare: Out3
Slave in, master out – eUSCI_B0 SPI mode
I2C data – eUSCI_B0 I2C mode
P1.6/TB0.3/UCB0SIMO/
UCB0SDA/TA0.0
31
I/O
BSL Data (I2C BSL)
TA0 CCR0 capture: CCI0A input, compare: Out0
8
Terminal Configuration and Functions
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Signal Descriptions (continued)
TERMINAL
NO.(2)
I/O(1)
DESCRIPTION
NAME
RGZ and PHP
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR4 capture: CCI4B input, compare: Out4
Slave out, master in – eUSCI_B0 SPI mode
I2C clock – eUSCI_B0 I2C mode
P1.7/TB0.4/UCB0SOMI/
UCB0SCL/TA1.0
32
I/O
I/O
BSL clock (I2C BSL)
TA1 CCR0 capture: CCI0A input, compare: Out0
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0CCR5 capture: CCI5B input, compare: Out5
P4.4/TB0.5
33
P4.5
34
35
36
37
38
I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
Digital ground supply
P4.6
DVSS
DVCC
P2.7
Digital power supply
I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TA0 CCR0 capture: CCI0B input, compare: Out0
I/O Slave transmit enable – eUSCI_A1 SPI mode
Analog input A6 for ADC
P2.3/TA0.0/UCA1STE/
A6/C10
39
Comparator input C10
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TA1 CCR0 capture: CCI0B input, compare: Out0
Clock signal input – eUSCI_A1 SPI slave mode
I/O
P2.4/TA1.0/UCA1CLK/
A7/C11
40
Clock signal output – eUSCI_A1 SPI master mode
Analog input A7 for ADC
Comparator input C11
Analog ground supply
General-purpose digital I/O
AVSS
41
42
PJ.6/HFXIN
I/O
I/O
Input for high-frequency crystal oscillator HFXT (in RHA and DA packages:
MSP430FR595x devices only)
General-purpose digital I/O
PJ.7/HFXOUT
AVSS
43
44
45
Output for high-frequency crystal oscillator HFXT (in RHA and DA packages:
MSP430FR595x devices only)
Analog ground supply
General-purpose digital I/O
PJ.4/LFXIN
I/O
I/O
Input for low-frequency crystal oscillator LFXT (in RHA and DA packages:
MSP430FR594x devices only)
General-purpose digital I/O
PJ.5/LFXOUT
46
Output of low-frequency crystal oscillator LFXT (in RHA and DA packages:
MSP430FR594x devices only)
AVSS
47
48
Analog ground supply
Analog power supply
AVCC
QFN Pad
Pad
QFN package exposed thermal pad. TI recommends connection to VSS.
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Terminal Configuration and Functions
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3.3 Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and diagrams of the
multiplexed ports, see 节 5.11.
3.4 Connection of Unused Pins
Table 3-1 lists the correct termination of all unused pins.
Table 3-1. Connection of Unused Pins(1)
PIN
AVCC
POTENTIAL
DVCC
COMMENT
AVSS
DVSS
Px.0 to Px.7
RST/NMI
Open
Set to port function, output direction (PxDIR.n = 1)
DVCC or VCC 47-kΩ pullup or internal pullup selected with 2.2-nF (10-nF(2)) pulldown
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK
The JTAG pins are shared with general-purpose I/O function (PJ.x). If not
used as JTAG pins, these pins should be switched to port function, output
direction. When used as JTAG pins, these pins should remain open.
Open
Open
TEST
This pin always has an internal pulldown enabled.
(1) Any unused pin with a secondary function that is shared with general-purpose I/O should follow the
Px.0 to Px.7 unused pin connection guidelines.
(2) The pulldown capacitor should not exceed 2.2 nF when using devices in Spy-Bi-Wire mode or in 4-
wire JTAG mode with TI tools like FET interfaces or GANG programmers. If JTAG or Spy-Bi-Wire
access is not needed, up to a 10-nF pulldown capacitor may be used.
10
Terminal Configuration and Functions
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4 Specifications
4.1 Absolute Maximum Ratings(1)
over operating temperature range (unless otherwise noted)
MIN
MAX
4.1
UNIT
V
Voltage applied at DVCC and AVCC pins to VSS
Voltage difference between DVCC and AVCC pins(2)
–0.3
±0.3
V
VCC + 0.3 V
(4.1 Max)
(3)
Voltage applied to any pin
–0.3
–55
V
Diode current at any device pin
±2
mA
°C
(4)
Storage temperature, Tstg
125
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltage differences between DVCC and AVCC exceeding the specified limits may cause malfunction of the device including erroneous
writes to RAM and FRAM.
(3) All voltages referenced to VSS
.
(4) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
4.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD) Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
4.3 Recommended Operating Conditions
Typical data are based on VCC = 3.0 V, TA = 25°C (unless otherwise noted)
MIN NOM
MAX UNIT
Supply voltage range applied at all DVCC and AVCC
pins(1) (2) (3)
VCC
1.8(4)
3.6
V
VSS
TJ
Supply voltage applied at all DVSS and AVSS pins
Operating junction temperature
Capacitor value at DVCC(5)
0
V
–55
105
°C
µF
CDVCC
1–20%
No FRAM wait states
(NWAITSx = 0)
0
0
8(7)
fSYSTEM
Processor frequency (maximum MCLK frequency)(6)
MHz
With FRAM wait states
(NWAITSx = 1)(8)
16(9)
fACLK
Maximum ACLK frequency
Maximum SMCLK frequency
50 kHz
16(9) MHz
fSMCLK
(1) TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up, power down, and device
operation, the voltage difference between AVCC and DVCC must not exceed the limits specified in Absolute Maximum Ratings.
Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
(2) See Table 4-1 for additional important information.
(3) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
(4) The minimum supply voltage is defined by the supervisor SVS levels. See Table 4-2 for the exact values.
(5) Connect a low-ESR capacitor with at least the value specified and a maximum tolerance of 20% as close as possible to the DVCC pin.
(6) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(7) DCO settings and HF crystals with a typical value less or equal the specified MAX value are permitted.
(8) Wait states only occur on actual FRAM accesses; that is, on FRAM cache misses. RAM and peripheral accesses are always executed
without wait states.
(9) DCO settings and HF crystals with a typical value less or equal the specified MAX value are permitted. If a clock sources with a larger
typical value is used, the clock must be divided in the clock system.
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100
10
1
Electromigration Fail Mode
0.1
80
85
90
95
100
105
110
115
120
125
130
135
140
145
150
Continuous Junction Temperature (èC)
D012
(1) See data sheet for absolute maximum and minimum recommended operating conditions.
(2) The predicted operating lifetime vs junction temperature is based on reliability modeling using electromigration as the dominant
failure mechanism affecting device wear-out for the specific device process and design characteristics.
Figure 4-1. MSP430FR5969-SP EM Lifetime Derating Chart
4.4 Active Mode Supply Current Into VCC Excluding External Current
(2)
over recommended operating temperature (unless otherwise noted)(1)
FREQUENCY (fMCLK = fSMCLK
)
1 MHz
0 wait states
(NWAITSx = 0)
4 MHz
0 wait states
(NWAITSx = 0)
8 MHz
0 wait states
(NWAITSx = 0)
12 MHz
1 wait states
(NWAITSx = 1)
16 MHz
1 wait states
(NWAITSx = 1)
EXECUTION
MEMORY
PARAMETER
VCC
UNIT
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
IAM, FRAM_UNI
FRAM
3.0 V
3.0 V
210
640
1220
1475
1845
µA
µA
(Unified memory)(3)
FRAM
0% cache hit
ratio
(4) (5)
IAM, FRAM (0%)
370
240
200
170
1280
745
560
480
2510
1440
1070
890
2080
1575
1300
1155
2650
1990
1620
1420
FRAM
50% cache hit
ratio
(4) (5)
IAM, FRAM (50%)
3.0 V
3.0 V
3.0 V
µA
µA
µA
FRAM
66% cache hit
ratio
(4) (5)
IAM, FRAM (66%)
FRAM
75% cache hit
ratio
(4) (5)
IAM, FRAM (75%)
255
1085
1310
1620
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Characterized with program executing typical data processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency, except for 12 MHz. For 12 MHz, fDCO= 24 MHz and
fMCLK = fSMCLK = fDCO/2.
At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency
(fMCLK,eff) decreases. The effective MCLK frequency also depends on the cache hit ratio. SMCLK is not affected by the number of wait
states or the cache hit ratio.
The following equation can be used to compute fMCLK,eff
:
fMCLK,eff = fMCLK / [wait states × (1 – cache hit ratio) + 1]
For example, with 1 wait state and 75% cache hit ratio, fMCKL,eff = fMCLK / [1 × (1 – 0.75) + 1] = fMCLK / 1.25.
(3) Represents typical program execution. Program and data reside entirely in FRAM. All execution is from FRAM.
(4) Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit
ratio represents number cache accesses divided by the total number of FRAM accesses. For example, a 75% ratio implies three of
every four accesses is from cache, and the remaining are FRAM accesses.
(5) See Figure 4-2 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best
linear fit using the typical data from Section 4.4.
12
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Active Mode Supply Current Into VCC Excluding External Current (continued)
over recommended operating temperature (unless otherwise noted)(1) (2)
FREQUENCY (fMCLK = fSMCLK
)
1 MHz
0 wait states
(NWAITSx = 0)
4 MHz
0 wait states
(NWAITSx = 0)
8 MHz
0 wait states
(NWAITSx = 0)
12 MHz
1 wait states
(NWAITSx = 1)
16 MHz
1 wait states
(NWAITSx = 1)
EXECUTION
MEMORY
PARAMETER
VCC
UNIT
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
FRAM
100% cache hit
ratio
(4) (5)
IAM, FRAM (100%)
3.0 V
110
235
420
640
730
µA
(6)
IAM, RAM
IAM, RAM only
RAM
RAM
3.0 V
3.0 V
130
100
320
290
585
555
890
860
1070
1040
µA
µA
(7) (5)
180
1300
(6) Program and data reside entirely in RAM. All execution is from RAM.
(7) Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
4.5 Typical Characteristics – Active Mode Supply Currents
3000
I(AM,0%)
I(AM,50%)
2500
I(AM,66%)
I(AM,75%)
2000
1500
1000
500
0
I(AM,100%)
I(AM,75%) [µA] = 103 × f [MHz] + 68
I(AM,RAMonly)
0
1
2
3
4
5
6
7
8
9
MCLK Frequency (MHz)
C001
NOTE: I(AM, cache hit ratio): Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with
cache hit-to-miss ratio as specified. Cache hit ratio represents number cache accesses divided by the total number of
FRAM accesses. For example, a 75% ratio implies three of every four accesses is from cache, and the remaining are
FRAM accesses.
NOTE: I(AM, RAMonly): Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
Figure 4-2. Typical Active Mode Supply Currents vs MCLK Frequency, No Wait States
4.6 Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
(2)
over recommended operating temperature (unless otherwise noted)(1)
FREQUENCY (fSMCLK
8 MHz
)
PARAMETER
VCC
1 MHz
TYP
4 MHz
TYP
12 MHz
TYP
16 MHz
TYP
UNIT
MAX
115
60
MAX
TYP
150
160
115
115
MAX
MAX
MAX
260
2.2 V
3.0 V
2.2 V
3.0 V
70
80
35
35
95
105
60
250
260
215
215
215
225
180
180
ILPM0
µA
µA
ILPM1
60
205
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Current for watchdog timer clocked by SMCLK included.
fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO at specified frequency, except for 12 MHz. For 12 MHz, fDCO = 24 MHz and fSMCLK
fDCO / 2.
=
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4.7 Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External
Current
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)(1)
PARAMETER
VCC
2.2 V
3 V
MIN
TYP
0.9
0.9
0.9
0.9
0.7
0.7
0.6
0.6
0.5
MAX
UNIT
ILPM2,XT12
ILPM2,XT3.7
ILPM2,VLO
ILPM3,XT12
Low-power mode 2, 12-pF crystal(2) (3) (4)
μA
17
2.2 V
3 V
Low-power mode 2, 3.7-pF crystal(2) (5) (4)
Low-power mode 2, VLO, includes SVS(6)
μA
μA
μA
2.2 V
3 V
16.7
4.9
2.2 V
3 V
Low-power mode 3, 12-pF crystal, excludes
SVS(2) (3) (7)
Low-power mode 3, 3.7-pF crystal, excludes
2.2 V
ILPM3,XT3.7
SVS(2) (5) (8)
(also see )
μA
3 V
0.5
2.2 V
3 V
0.4
0.4
0.5
0.5
0.3
0.3
ILPM3,VLO
ILPM4,SVS
ILPM4
Low-power mode 3, VLO, excludes SVS(9)
μA
μA
μA
4.7
4.8
Low-power mode 4, includes SVS(10)
(also see )
2.2 V
3 V
2.2 V
3 V
Low-power mode 4, excludes SVS(11)
4.6
1.3
Additional idle current if one or more modules
from Group A (see 表 5-3) are activated in
LPM3 or LPM4.
IIDLE,GroupA
3 V
0.02
μA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Not applicable for devices with HF crystal oscillator only.
(3) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5-pF load.
(4) Low-power mode 2, crystal oscillator test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 are included. Current for brownout and SVS are included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(5) Characterized with a SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are chosen
to closely match the required 3.7-pF load.
(6) Low-power mode 2, VLO test conditions:
Current for watchdog timer clocked by ACLK is included. RTC disabled (RTCHOLD = 1). Current for brownout and SVS are included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
(7) Low-power mode 3, 12-pF crystal, excludes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 are included. Current for brownout is included. SVS disabled
(SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(8) Low-power mode 3, 3.7-pF crystal, excludes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 are included. Current for brownout is included. SVS disabled
(SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(9) Low-power mode 3, VLO, excludes SVS test conditions:
Current for watchdog timer clocked by ACLK is included. RTC disabled (RTCHOLD = 1). Current for brownout is included. SVS is
disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
(10) Low-power mode 4, includes SVS test conditions:
Current for brownout and SVS are included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
(11) Low-power mode 4, excludes SVS test conditions:
Current for brownout is included. SVS is disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
14
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Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External
Current (continued)
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)(1)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
Additional idle current if one or more modules
from Group B (see 表 5-3) are activated in
LPM3 or LPM4
IIDLE,GroupB
3 V
0.015
1
μA
4.8 Low-Power Mode (LPM3.5, LPM4.5) Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)(1)
PARAMETER
VCC
MIN
TYP
0.45
0.45
0.25
MAX
UNIT
2.2 V
3.0 V
2.2 V
Low-power mode 3.5, 12-pF crystal, includes
SVS(2)(3)(4)
ILPM3.5,XT12
μA
2
Low-power mode 3.5, 3.7-pF cyrstal,
excludes SVS(2)(5)(6)
(also see )
ILPM3.5,XT3.7
μA
3.0 V
0.25
Low-power mode 4.5, includes SVS(7)
(also see )
2.2 V
3.0 V
2.2 V
3.0 V
0.2
0.2
0.2
0.2
ILPM4.5,SVS
μA
μA
1.5
1
Low-power mode 4.5, excludes SVS(8)
(also see )
ILPM4.5
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Not applicable for devices with HF crystal oscillator only.
(3) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5-pF load.
(4) Low-power mode 3.5, 12-pF crystal, includes SVS test conditions:
Current for RTC clocked by XT1 is included. Current for brownout and SVS are included (SVSHE = 1). Core regulator is disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(5) Characterized with a SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are chosen
to closely match the required 3.7-pF load.
(6) Low-power mode 3.5, 3.7-pF crystal, excludes SVS test conditions:
Current for RTC clocked by XT1 is included. Current for brownout is included. SVS is disabled (SVSHE = 0). Core regulator isdisabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(7) Low-power mode 4.5, includes SVS test conditions:
Current for brownout and SVS are included (SVSHE = 1). Core regulator is disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
(8) Low-power mode 4.5, excludes SVS test conditions:
Current for brownout is included. SVS is disabled (SVSHE = 0). Core regulator is disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
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4.9 Typical Characteristics, Current Consumption per Module(1)
MODULE
Timer_A
TEST CONDITIONS
REFERENCE CLOCK
Module input clock
MIN
TYP
3
MAX
UNIT
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
nA
Timer_B
eUSCI_A
eUSCI_A
eUSCI_B
eUSCI_B
RTC_B
MPY
Module input clock
Module input clock
Module input clock
Module input clock
Module input clock
32 kHz
5
UART mode
5.5
3.5
3.5
3.5
100
25
SPI mode
SPI mode
I2C mode, 100 kbaud
Only from start to end of operation
Only from start to end of operation
Only from start to end of operation
MCLK
μA/MHz
μA/MHz
μA/MHz
AES
MCLK
21
CRC
MCLK
2.5
(1) For other module currents not listed here, see the module specific parameter sections.
4.10 Thermal Resistance Characteristics
THERMAL METRIC
Junction-to-ambient thermal resistance(1)
Junction-to-case (top) thermal resistance(2)
Junction-to-board thermal resistance(3)
PACKAGE
VALUE
30.6
17.2
7.2
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJA
θJC(TOP)
θJB
QFN-48 (RGZ)
ΨJB
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
Junction-to-case (bottom) thermal resistance(4)
Junction-to-ambient thermal resistance, still air(1)
Junction-to-case (top) thermal resistance(2)
Junction-to-board thermal resistance(3)
7.2
ΨJT
0.2
θJC(BOTTOM)
θJA
θJC(TOP)
θJB
1.2
26.9
16.4
7.6
\
QFP-48 (PHP)
ΨJB
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
Junction-to-case (bottom) thermal resistance(4)
7.6
ΨJT
0.2
θJC(BOTTOM)
1.5
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
16
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4.11 Timing and Switching Characteristics
4.11.1 Power Supply Sequencing
TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up,
power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the
limits specified in Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the
device including erroneous writes to RAM and FRAM.
At power up, the device does not start executing code before the supply voltage reaches VSVSH+ if the
supply rises monotonically to this level.
Table 4-1 lists the reset power ramp requirements.
Table 4-1. Brownout and Device Reset Power Ramp Requirements
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
| dDVCC/dt | < 3 V/s(3)
| dDVCC/dt | > 300 V/s(3)
| dDVCC/dt | < 3 V/s(4)
MIN
0.7
0
TYP
MAX UNIT
1.68
V
V
V
VVCC_BOR–
VVCC_BOR+
Brownout power-down level(1)(2)
Brownout power-up level(2)
0.79
1.74
(1) In case of a supply voltage brownout, the device supply voltages need to ramp down to the specified brownout power-down level
VVCC_BOR- before the voltage is ramped up again to ensure a reliable device start-up and performance according to the data sheet
including the correct operation of the on-chip SVS module.
(2) Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR
resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation for
capacitor CDVCC should limit the slopes accordingly.
(3) The brownout levels are measured with a slowly changing supply. With faster slopes the MIN level required to reset the device properly
can decrease to 0 V. Use the graph in Figure 4-3 to estimate the VVCC_BOR- level based on the down slope of the supply voltage. After
removing VCC the down slope can be estimated based on the current consumption and the capacitance on DVCC: dV/dt = I/C with
dV/dt: slope, I: current, C: capacitance.
(4) The brownout levels are measured with a slowly changing supply.
2
1.5
1
0.5
0
1
10
100
1000
10000
100000
Supply Voltage Power-Down Slope (V/s)
Figure 4-3. Brownout Power-Down Level vs Supply Voltage Down Slope
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Table 4-2 lists the characteristics of the SVS.
Table 4-2. SVS
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
170
MAX UNIT
ISVSH,LPM
VSVSH-
SVSH current consumption, low power modes
SVSH power-down level
300
1.85
1.99
120
10
nA
V
1.73
1.75
40
1.80
1.88
VSVSH+
SVSH power-up level
V
VSVSH_hys
tPD,SVSH, AM
SVSH hysteresis
mV
µs
SVSH propagation delay, active mode
dVVcc/dt = –10 mV/µs
4.11.2 Reset Timing
Table 4-3 lists the required reset input timing.
Table 4-3. Reset Input
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
VCC
MIN
MAX UNIT
t(RST)
(1) Not applicable if RST/NMI pin configured as NMI.
External reset pulse duration on RST(1)
2.2 V, 3.0 V
2
µs
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4.11.3 Clock Specifications
Table 4-4 lists the characteristics of the LFXT.
Table 4-4. Low-Frequency Crystal Oscillator, LFXT(1)
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
3.0 V
180
TA = 25°C, CL,eff = 3.7 pF, ESR ≈ 44 kΩ
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {1},
TA = 25°C, CL,eff = 6 pF, ESR ≈ 40 kΩ
3.0 V
3.0 V
3.0 V
185
225
IVCC.LFXT
Current consumption
nA
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {2},
TA = 25°C, CL,eff = 9 pF, ESR ≈ 40 kΩ
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF, ESR ≈ 40 kΩ
330
fLFXT
LFXT oscillator crystal frequency LFXTBYPASS = 0
32768
Hz
Measured at ACLK,
LFXT oscillator duty cycle
DCLFXT
30%
70%
fLFXT = 32768 Hz
LFXT oscillator logic-level
LFXTBYPASS = 1(2) (3)
fLFXT,SW
10.5 32.768
50 kHz
70%
square-wave input frequency
LFXT oscillator logic-level
LFXTBYPASS = 1
DCLFXT, SW
30%
210
300
2
square-wave input duty cycle
LFXTBYPASS = 0, LFXTDRIVE = {1},
fLFXT = 32768 Hz, CL,eff = 6 pF
Oscillation allowance for
LF crystals(4)
OALFXT
kΩ
LFXTBYPASS = 0, LFXTDRIVE = {3},
fLFXT = 32768 Hz, CL,eff = 12.5 pF
Integrated load capacitance at
LFXIN terminal(5) (6)
CLFXIN
pF
pF
Integrated load capacitance at
LFXOUT terminal(5) (6)
CLFXOUT
2
(1) To improve EMI on the LFXT oscillator, observe the following guidelines.
•
•
•
•
•
•
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins LFXIN and LFXOUT.
Avoid running PCB traces underneath or adjacent to the LFXIN and LFXOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator LFXIN and LFXOUT pins.
If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW
.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
•
•
•
•
For LFXTDRIVE = {0}, CL,eff = 3.7 pF.
For LFXTDRIVE = {1}, CL,eff = 6 pF
For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 9 pF
For LFXTDRIVE = {3}, 9 pF ≤ CL,eff ≤ 12.5 pF
(5) This represents all the parasitic capacitance present at the LFXIN and LFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN × COUT / (CIN + COUT), where CIN and COUT are the
total capacitance at the LFXIN and LFXOUT terminals, respectively.
(6) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF. The PCB adds
additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance
of the selected crystal is met.
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Table 4-4. Low-Frequency Crystal Oscillator, LFXT(1) (continued)
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
TA = 25°C, CL,eff = 3.7 pF
3.0 V
800
tSTART,LFXT
Start-up time(7)
ms
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF
3.0 V
1000
fFault,LFXT
Oscillator fault frequency(8) (9)
0
3500
Hz
(7) Includes start-up counter of 1024 clock cycles.
(8) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specification may set the
flag. A static condition or stuck at fault condition sets the flag.
(9) Measured with logic-level input frequency but also applies to operation with crystals.
Table 4-5 lists the characteristics of the HFXT.
Table 4-5. High-Frequency Crystal Oscillator, HFXT(1)
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0, HFFREQ = 1(2)
TA = 25°C, CL,eff = 18 pF, Typical ESR, Cshunt
75
fOSC = 8 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 1,
TA = 25°C, CL,eff = 18 pF, Typical ESR, Cshunt
120
190
250
HFXT oscillator
crystal current HF
mode at typical
ESR
IDVCC.HFXT
3.0 V
μA
fOSC = 16 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 2, HFFREQ = 2,
TA = 25°C, CL,eff = 18 pF, Typical ESR, Cshunt
fOSC = 24 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 3, HFFREQ = 3,
TA = 25°C, CL,eff = 18 pF, Typical ESR, Cshunt
HFXTBYPASS = 0, HFFREQ = 1(2)(3)
crystal frequency, HFXTBYPASS = 0, HFFREQ = 2(3)
4
8.01
8
HFXT oscillator
fHFXT
16
24
MHz
MHz
crystal mode
HFXTBYPASS = 0, HFFREQ = 3(3)
16.01
HFXT oscillator
DCHFXT
Measured at SMCLK, fHFXT = 16 MHz
duty cycle
40%
50%
60%
HFXTBYPASS = 1, HFFREQ = 0(4)(3)
0.9
4.01
4
8
HFXT oscillator
HFXTBYPASS = 1, HFFREQ = 1(4)(3)
logic-level square-
fHFXT,SW
wave input
HFXTBYPASS = 1, HFFREQ = 2(4)(3)
8.01
16
24
frequency, bypass
HFXTBYPASS = 1, HFFREQ = 3(4)(3)
mode
16.01
HFXT oscillator
logic-level square-
HFXTBYPASS = 1
wave input duty
DCHFXT, SW
40%
60%
cycle
(1) To improve EMI on the HFXT oscillator, observe the following guidelines.
•
•
•
•
•
•
Keep the traces between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins HFXIN and HFXOUT.
Avoid running PCB traces underneath or adjacent to the HFXIN and HFXOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator HFXIN and HFXOUT pins.
If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) HFFREQ = {0} is not supported for HFXT crystal mode of operation.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) When HFXTBYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCHFXT, SW
.
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Table 4-5. High-Frequency Crystal Oscillator, HFXT(1) (continued)
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0, HFFREQ = 1,
TA = 25°C, CL,eff = 16 pF
3.0 V
1.6
tSTART,HFXT
Start-up time(5)
ms
fOSC = 24 MHz ,
HFXTBYPASS = 0, HFXTDRIVE = 3, HFFREQ = 3,
TA = 25°C, CL,eff = 16 pF
3.0 V
0.6
2
Integrated load
capacitance at
CHFXIN
pF
pF
HFXIN terminaI(6)
(7)
Integrated load
capacitance at
HFXOUT
CHFXOUT
2
terminaI(6) (7)
Oscillator fault
frequency(8) (9)
fFault,HFXT
0
800
kHz
(5) Includes start-up counter of 1024 clock cycles.
(6) This represents all the parasitic capacitance present at the HFXIN and HFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN × COUT / (CIN + COUT), where CIN and COUT are the
total capacitance at the HFXIN and HFXOUT terminals, respectively.
(7) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF. The PCB adds
additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance
of the selected crystal is met.
(8) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX might set the flag. A static
condition or stuck at fault condition set the flag.
(9) Measured with logic-level input frequency but also applies to operation with crystals.
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Table 4-6 lists the characteristics of the DCO.
Table 4-6. DCO
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 0,
DCORSEL = 1, DCOFSEL = 0
DCO frequency range
1 MHz, trimmed
fDCO1
1
±3.8%
MHz
DCO frequency range
2.7 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 1
fDCO2.7
fDCO3.5
fDCO4
2.667
3.5
4
±3.8%
±3.8%
±3.8%
MHz
MHz
MHz
DCO frequency range
3.5 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 2
DCO frequency range
4 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 3
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 4,
DCORSEL = 1, DCOFSEL = 1
DCO frequency range
5.3 MHz, trimmed
fDCO5.3
fDCO7
fDCO8
5.333
±3.8%
±3.8%
±3.8%
MHz
MHz
MHz
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 5,
DCORSEL = 1, DCOFSEL = 2
DCO frequency range
7 MHz, trimmed
7
8
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 6,
DCORSEL = 1, DCOFSEL = 3
DCO frequency range
8 MHz, trimmed
DCO frequency range
16 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 1, DCOFSEL = 4
fDCO16
fDCO21
fDCO24
16
21
24
±3.8%(1)
±3.8%(1)
±3.8%(1)
MHz
MHz
MHz
DCO frequency range
21 MHz, trimmed
Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 5
DCO frequency range
24 MHz, trimmed
Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 6
Measured at SMCLK, divide by 1,
no external divide, all
fDCO,DC
Duty cycle
DCORSEL/DCOFSEL settings except
DCORSEL = 1, DCOFSEL = 5 and
DCORSEL = 1, DCOFSEL = 6
48%
50%
52%
Based on fsignal = 10 kHz and DCO used
for 12-bit SAR ADC sampling source.
This achieves >74 dB SNR due to jitter
(that is, it is limited by ADC
tDCO, JITTER DCO jitter
2
3
ns
performance).
dfDCO/dT
DCO temperature drift(2)
3.0 V
0.01
%/°C
(1) After a wakeup from LPM1, LPM2, LPM3, or LPM4, the DCO frequency fDCO might exceed the specified frequency range for a few clock
cycles by up to 5% before settling into the specified steady-state frequency range.
(2) Calculated using the box method: (MAX(–55°C to 105°C) – MIN(–55°C to 105°C)) / MIN(–55°C to 105°C) / (105°C – (–55°C))
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Table 4-7 lists the characteristics of the VLO.
Table 4-7. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
Current consumption
VLO frequency
TEST CONDITIONS
MIN
TYP
100
9.9
MAX UNIT
IVLO
nA
fVLO
Measured at ACLK
3.3
16
kHz
%/°C
%/V
dfVLO/dT
dfVLO/dVCC
fVLO,DC
VLO frequency temperature drift
VLO frequency supply voltage drift
Duty cycle
Measured at ACLK(1)
Measured at ACLK(2)
Measured at ACLK
0.2
0.7
40%
50%
60%
(1) Calculated using the box method: (MAX(–55°C to 105°C) – MIN(–55°C to 105°C)) / MIN(–55°C to 105°C) / (105°C – (–55°C))
(2) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)
Table 4-8 lists the characteristics of the MODOSC.
Table 4-8. Module Oscillator (MODOSC)
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
25
MAX UNIT
IMODOSC
Current consumption
Enabled
μA
fMODOSC
MODOSC frequency
3.75
4.8
5.5
MHz
fMODOSC/dT
MODOSC frequency temperature drift(1)
0.08
%/℃
MODOSC frequency supply voltage
drift(2)
fMODOSC/dVCC
DCMODOSC
1.4
%/V
Duty cycle
Measured at SMCLK, divide by 1
40%
50%
60%
(1) Calculated using the box method: (MAX(–55°C to 105°C) – MIN(–55°C to 105°C)) / MIN(–55°C to 105°C) / (105°C – (–55°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
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4.11.4 Wake-up Characteristics
Table 4-9 list the device wake-up times.
Table 4-9. Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX UNIT
(Additional) wake-up time to activate the FRAM
in AM if previously disabled by the FRAM
controller or from an LPM if immediate
activation is selected for wakeup
tWAKE-UP FRAM
6
10
μs
400 +
1.5 / fDCO
tWAKE-UP LPM0
Wake-up time from LPM0 to active mode(1)
2.2 V, 3.0 V
ns
tWAKE-UP LPM1
tWAKE-UP LPM2
tWAKE-UP LPM3
tWAKE-UP LPM4
Wake-up time from LPM1 to active mode(1)
Wake-up time from LPM2 to active mode(1)
Wake-up time from LPM3 to active mode(1)
Wake-up time from LPM4 to active mode(1)
2.2 V, 3.0 V
2.2 V, 3.0 V
2.2 V, 3.0 V
2.2 V, 3.0 V
2.2 V, 3.0 V
2.2 V, 3.0 V
2.2 V, 3.0 V
6
6
μs
μs
μs
μs
μs
μs
ms
7
10
10
7
tWAKE-UP LPM3.5 Wake-up time from LPM3.5 to active mode(2)
250
250
1
350
350
1.5
SVSHE = 1
SVSHE = 0
tWAKE-UP LPM4.5 Wake-up time from LPM4.5 to active mode(2)
Wake-up time from a RST pin triggered reset to
tWAKE-UP-RST
2.2 V, 3.0 V
2.2 V, 3.0 V
250
1
350
1.5
μs
active mode(2)
(2)
tWAKE-UP-BOR
Wake-up time from power-up to active mode
ms
(1) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first
externally observable MCLK clock edge. MCLK is sourced by the DCO and the MCLK divider is set to divide-by-1 (DIVMx = 000b,
fMCLK = fDCO). This time includes the activation of the FRAM during wakeup.
(2) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
Table 4-10 list the typical wake-up charges.
Table 4-10. Typical Wake-up Charge(1)
also see Figure 4-4 and
PARAMETER
TEST CONDITIONS MIN
TYP
MAX UNIT
Charge used for activating the FRAM in AM or during wakeup
from LPM0 if previously disabled by the FRAM controller.
QWAKE-UP FRAM
QWAKE-UP LPM0
QWAKE-UP LPM1
QWAKE-UP LPM2
QWAKE-UP LPM3
QWAKE-UP LPM4
15.1
nAs
Charge used for wakeup from LPM0 to active mode (with FRAM
active)
4.4
nAs
nAs
nAs
nAs
nAs
Charge used for wakeup from LPM1 to active mode (with FRAM
active)
15.1
15.3
16.5
16.5
Charge used for wakeup from LPM2 to active mode (with FRAM
active)
Charge used for wakeup from LPM3 to active mode (with FRAM
active)
Charge used for wakeup from LPM4 to active mode (with FRAM
active)
QWAKE-UP LPM3.5 Charge used for wakeup from LPM3.5 to active mode(2)
QWAKE-UP LPM4.5 Charge used for wakeup from LPM4.5 to active mode(2)
QWAKE-UP-RESET Charge used for reset from RST or BOR event to active mode(2)
76
77
nAs
nAs
nAs
nAs
SVSHE = 1
SVSHE = 0
77.5
75
(1) Charge used during the wake-up time from a given low-power mode to active mode. This does not include the energy required in active
mode (for example, for an interrupt service routine).
(2) Charge required until start of user code. This does not include the energy required to reconfigure the device.
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4.11.4.1 Typical Characteristics, Average LPM Currents vs Wake-up Frequency
10000.00
LPM0
LPM1
LPM2,XT12
1000.00
LPM3,XT12
LPM3.5,XT12
100.00
10.00
1.00
0.10
0.001
0.01
0.1
1
10
100
1000
10000
100000
Wake-up Frequency (Hz)
NOTE: The average wakeup current does not include the energy required in active mode; for example, for an interrupt
service routine or to reconfigure the device.
Figure 4-4. Average LPM Currents vs Wake-up Frequency at 25°C
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4.11.5 Digital I/Os
Table 4-11 lists the characteristics of the digital inputs.
Table 4-11. Digital Inputs
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
1.2
TYP
MAX UNIT
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
1.65
V
VIT+
VIT–
Vhys
Positive-going input threshold voltage
1.65
0.55
0.75
0.44
0.60
2.25
1.00
V
Negative-going input threshold voltage
1.35
0.98
V
Input voltage hysteresis (VIT+ – VIT–
Pullup or pulldown resistor
)
1.30
For pullup: VIN = VSS
For pulldown: VIN = VCC
RPull
CI,dig
CI,ana
20
35
3
50
kΩ
pF
pF
Input capacitance, digital only port pins
VIN = VSS or VCC
Input capacitance, port pins with shared analog
functions(1)
VIN = VSS or VCC
5
2.2 V,
3.0 V
(2)(3)
Ilkg(Px.y)
t(int)
High-impedance input leakage current
See
–20
22
+20
nA
ns
µs
External interrupt timing (external trigger pulse Ports with interrupt capability
2.2 V,
3.0 V
duration to set interrupt flag)(4)
(see 节 1.4 and Section 3.2)
2.2 V,
3.0 V
t(RST)
External reset pulse duration on RST(5)
2.2
(1) If the port pins PJ.4/LFXIN and PJ.5/LFXOUT are used as digital I/Os, they are connected by a 4-pF capacitor and a 35-MΩ resistor in
series. At frequencies of approximately 1 kHz and lower, the 4-pF capacitor can add to the pin capacitance of PJ.4/LFXIN and/or
PJ.5/LFXOUT.
(2) The input leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
(3) The input leakage of the digital port pins is measured individually. The port pin is selected for input, and the pullup or pulldown resistor is
disabled.
(4) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int)
.
(5) Not applicable if RST/NMI pin configured as NMI.
26
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Table 4-12 lists the characteristics of the digital outputs.
Table 4-12. Digital Outputs
over recommended ranges of supply voltage and operating temperature (unless otherwise noted) (also see Figure 4-5,
Figure 4-6, Figure 4-7, and Figure 4-8)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA(1)
I(OHmax) = –3 mA(2)
I(OHmax) = –2 mA(1)
I(OHmax) = –6 mA(2)
I(OLmax) = 1 mA(1)
I(OLmax) = 3 mA(2)
I(OLmax) = 2 mA(1)
I(OLmax) = 6 mA(2)
VCC
MIN
VCC – 0.25
VCC – 0.60
VCC – 0.25
VCC – 0.60
VSS
TYP
MAX UNIT
VCC
2.2 V
VCC
VOH
High-level output voltage
V
VCC
3.0 V
2.2 V
3.0 V
VCC
VSS + 0.25
VSS
VSS + 0.60
VSS + 0.25
VSS + 0.60
VOL
Low-level output voltage
V
VSS
VSS
2.2 V
3.0 V
2.2 V
16
(4) (5)
fPx.y
Port output frequency (with load)(3)
Clock output frequency(3)
CL = 20 pF, RL
MHz
MHz
16
ACLK, MCLK, or SMCLK at
configured output port,
CL = 20 pF(5)
16
fPort_CLK
3.0 V
16
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
4
3
4
3
6
4
6
4
15
15
15
15
15
15
15
15
Port output rise time, digital only port
pins
trise,dig
CL = 20 pF
CL = 20 pF
CL = 20 pF
CL = 20 pF
ns
ns
ns
ns
Port output fall time, digital only port
pins
tfall,dig
Port output rise time, port pins with
shared analog functions
trise,ana
Port output fall time, port pins with
shared analog functions
tfall,ana
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
(3) The port can output frequencies at least up to the specified limit, and the port might support higher frequencies.
(4) A resistive divider with 2 × R1 and R1 = 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the
divider. CL = 20 pF is connected from the output to VSS
.
(5) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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4.11.5.1 Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
0.016
0.014
0.012
0.01
0.03
0.025
0.02
0.015
0.01
0.005
0
25èC
105èC
25èC
105èC
0.008
0.006
0.004
0.002
0
0
0.5
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
3
Low-Level Output Voltage (V)
Low-Level Output Voltage (V)
D005
D006
VCC = 2.2 V
VCC = 3.0 V
Figure 4-5. Typical Low-Level Output Current vs
Low-Level Output Voltage
Figure 4-6. Typical Low-Level Output Current vs
Low-Level Output Voltage
0
0
25èC
105èC
25èC
105èC
-0.005
-0.01
-0.01
-0.02
-0.03
-0.015
0
0.5
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
3
High-Level Output Voltage (V)
High-Level Output Voltage (V)
D007
D008
VCC = 2.2 V
VCC = 3.0 V
Figure 4-8. Typical High-Level Output Current vs
Figure 4-7. Typical High-Level Output Current vs
High-Level Output Voltage
High-Level Output Voltage
28
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Table 4-13 lists the frequencies of the pin oscillator.
Table 4-13. Pin-Oscillator Frequency, Ports Px
over recommended ranges of supply voltage and operating temperature (unless otherwise noted) (see Figure 4-9 and
Figure 4-10)
PARAMETER
TEST CONDITIONS
Px.y, CL = 10 pF(1)
Px.y, CL = 20 pF(1)
VCC
MIN
TYP
1640
870
MAX UNIT
foPx.y
Pin-oscillator frequency
3.0 V
kHz
(1) CL is the external load capacitance connected from the output to VSS and includes all parasitic effects such as PCB traces.
4.11.5.2 Typical Characteristics, Pin-Oscillator Frequency
1000
1000
25èC
105èC
25èC
105èC
100
10
100
10
100
100
External Load Capacitance (pF)
External Load Capacitance (pF)
D009
D010
VCC = 2.2 V
One output active at a time.
VCC = 3.0 V
One output active at a time.
Figure 4-9. Typical Oscillation Frequency vs Load Capacitance Figure 4-10. Typical Oscillation Frequency vs Load Capacitance
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4.11.6 Timer_A and Timer_B
Table 4-14 lists the characteristics of the Timer_A.
Table 4-14. Timer_A
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK or ACLK,
External: TACLK,
Duty cycle = 50% ±10%
2.2 V,
3.0 V
fTA
Timer_A input clock frequency
16 MHz
All capture inputs, minimum pulse
duration required for capture
2.2 V,
3.0 V
tTA,cap
Timer_A capture timing
20
ns
Table 4-15 lists the characteristics of the Timer_B.
Table 4-15. Timer_B
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK or ACLK,
External: TBCLK,
Duty cycle = 50% ±10%
2.2 V,
3.0 V
fTB
Timer_B input clock frequency
16 MHz
All capture inputs, minimum pulse
duration required for capture
2.2 V,
3.0 V
tTB,cap
Timer_B capture timing
20
ns
30
Specifications
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4.11.7 eUSCI
Table 4-16 lists the supported clock frequencies of the eUSCI in UART mode.
Table 4-16. eUSCI (UART Mode) Clock Frequency
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
Internal: SMCLK or ACLK,
feUSCI
eUSCI input clock frequency
External: UCLK,
Duty cycle = 50% ±10%
16
4
MHz
MHz
BITCLK clock frequency
(equals baud rate in MBaud)
fBITCLK
Table 4-17 lists the deglitch times of the eUSCI in UART mode.
Table 4-17. eUSCI (UART Mode)
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UCGLITx = 0
VCC
MIN
5
TYP
MAX UNIT
30
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
20
35
50
90
ns
tt
UART receive deglitch time(1)
2.2 V, 3.0 V
160
220
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. Thus the selected deglitch
time can limit the maximum usable baud rate. To ensure that pulses are correctly recognized, their duration should exceed the
maximum specification of the deglitch time.
Table 4-18 lists the supported clock frequencies of the eUSCI in SPI master mode.
Table 4-18. eUSCI (SPI Master Mode) Clock Frequency
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
16 MHz
Internal: SMCLK or ACLK,
Duty cycle = 50% ±10%
feUSCI
eUSCI input clock frequency
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Table 4-19 lists the characteristics of the eUSCI in SPI master mode.
Table 4-19. eUSCI (SPI Master Mode)
(1)
over recommended ranges of supply voltage and operating temperature (unless otherwise noted) (see note
)
PARAMETER
TEST CONDITIONS
VCC
MIN
1
MAX
UNIT
tSTE,LEAD
tSTE,LAG
STE lead time, STE active to clock
UCSTEM = 1, UCMODEx = 01 or 10
UCxCLK
cycles
STE lag time, last clock to STE inactive UCSTEM = 1, UCMODEx = 01 or 10
1
STE access time, STE active to SIMO
UCSTEM = 0, UCMODEx = 01 or 10
data out
tSTE,ACC
tSTE,DIS
2.2 V, 3.0 V
2.2 V, 3.0 V
60
60
ns
ns
STE disable time, STE inactive to
UCSTEM = 0, UCMODEx = 01 or 10
SOMI high impedance
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
35
35
0
tSU,MI
SOMI input data setup time
SOMI input data hold time
ns
ns
ns
ns
tHD,MI
0
10
10
tVALID,MO
SIMO output data valid time(2)
SIMO output data hold time(3)
UCLK edge to SIMO valid, CL = 20 pF
CL = 20 pF
0
0
tHD,MO
(1) fUCxCLK = 1 / 2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)
)
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 4-11 and Figure 4-12.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 4-
11 and Figure 4-12.
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UCMODEx = 01
UCMODEx = 10
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
SIMO
tHD,MO
tVALID,MO
tSTE,ACC
tSTE,DIS
Figure 4-11. SPI Master Mode, CKPH = 0
UCMODEx = 01
STE
tSTE,LEAD
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,MI
tSU,MI
SOMI
SIMO
tHD,MO
tVALID,MO
tSTE,DIS
tSTE,ACC
Figure 4-12. SPI Master Mode, CKPH = 1
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Table 4-20 lists the characteristics of the eUSCI in SPI slave mode.
Table 4-20. eUSCI (SPI Slave Mode)
(1)
over recommended ranges of supply voltage and operating temperature (unless otherwise noted) (see Note
)
PARAMETER
TEST CONDITIONS
VCC
MIN
45
40
0
MAX UNIT
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
tSU,SI
STE lead time, STE active to clock
ns
STE lag time, last clock to STE inactive
ns
0
45
ns
40
STE access time, STE active to SOMI data out
40
ns
35
STE disable time, STE inactive to SOMI high
impedance
4
4
7
7
SIMO input data setup time
SIMO input data hold time
SOMI output data valid time(2)
SOMI output data hold time(3)
ns
ns
tHD,SI
35
ns
35
UCLK edge to SOMI valid,
CL = 20 pF
tVALID,SO
0
0
tHD,SO
CL = 20 pF
ns
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)
)
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 4-13 and Figure 4-14.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 4-13
and Figure 4-14.
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UCMODEx = 01
UCMODEx = 10
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tSU,SI
tLOW/HIGH
tLOW/HIGH
tHD,SI
SIMO
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 4-13. SPI Slave Mode, CKPH = 0
UCMODEx = 01
UCMODEx = 10
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 4-14. SPI Slave Mode, CKPH = 1
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Table 4-21 lists the characteristics of the eUSCI in I2C mode.
Table 4-21. eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating temperature (unless otherwise noted) (see Figure 4-15)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK or ACLK,
External: UCLK,
feUSCI
eUSCI input clock frequency
16 MHz
Duty cycle = 50% ±10%
fSCL
SCL clock frequency
2.2 V, 3.0 V
2.2 V, 3.0 V
0
4.0
0.6
4.7
0.6
0
400 kHz
µs
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
2.2 V, 3.0 V
µs
tHD,DAT
tSU,DAT
Data hold time
Data setup time
2.2 V, 3.0 V
2.2 V, 3.0 V
ns
ns
100
4.0
0.6
4.7
1.3
50
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
UCGLITx = 0
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
UCCLTOx = 1
UCCLTOx = 2
UCCLTOx = 3
tSU,STO
Setup time for STOP
2.2 V, 3.0 V
µs
Bus free time between a STOP and
START condition
tBUF
µs
250
25
125
ns
Pulse duration of spikes suppressed by
input filter
tSP
2.2 V, 3.0 V
12.5
6.3
62.5
31.5
27
30
33
tTIMEOUT
Clock low time-out
2.2 V, 3.0 V
ms
tHD,STA
tSU,STA
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 4-15. I2C Mode Timing
36
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4.11.8 ADC
Table 4-22 lists the input requirements of the ADC.
Table 4-22. 12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN NOM
MAX UNIT
V(Ax)
Analog input voltage range(1)
All ADC12 analog input pins Ax
0
AVCC
190
V
fADC12CLK = MODCLK, ADC12ON = 1,
ADC12PWRMD = 0, ADC12DIF = 0,
REFON = 0, ADC12SHTx = 0,
ADC12DIV = 0
3.0 V
2.2 V
3.0 V
2.2 V
145
I(ADC12_B)
single-
ended mode
Operating supply current into
µA
AVCC plus DVCC terminals(2) (3)
140
175
170
185
235
230
fADC12CLK = MODCLK, ADC12ON = 1,
ADC12PWRMD = 0, ADC12DIF = 1,
REFON = 0, ADC12SHTx= 0,
ADC12DIV = 0
I(ADC12_B)
differential
mode
Operating supply current into
µA
pF
AVCC plus DVCC terminals(2) (3)
Only one terminal Ax can be selected
at one time
CI
RI
Input capacitance
2.2 V
10
15
>2 V
<2 V
0.5
1
4
kΩ
kΩ
Input MUX ON resistance
0 V ≤ V(Ax) ≤ AVCC
10
(1) The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion results.
(2) The internal reference supply current is not included in current consumption parameter I(ADC12_B)
.
(3) Approximately 60% (typical) of the total current into the AVCC and DVCC terminals is from AVCC.
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Table 4-23 lists the timing parameters of the ADC.
Table 4-23. 12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
For specified performance of ADC12 linearity parameters
Frequency for specified with ADC12PWRMD = 0.
fADC12CLK
0.45
5.4
MHz
performance
If ADC12PWRMD = 1, the maximum is 1/4 of the value
shown here.
Frequency for reduced
performance
Internal oscillator(1)
fADC12CLK
fADC12OSC
Linearity parameters have reduced performance
ADC12DIV = 0, fADC12CLK = fADC12OSC from MODCLK
32.768
4.8
kHz
4
5.4
3.5
MHz
REFON = 0, Internal oscillator,
fADC12CLK = fADC12OSC from MODCLK, ADC12WINC = 0
2.6
tCONVERT
Conversion time
µs
External fADC12CLK from ACLK, MCLK, or SMCLK,
ADC12SSEL ≠ 0
(2)
See
Turnon settling time of
the ADC
(3)
tADC12ON
See
100
ns
ns
Time ADC must be off
before it can be turned
on again
tADC12OFF must be met to make sure that tADC12ON time
holds.
tADC12OFF
100
All pulse sample mode
(ADC12SHP = 1) and
extended sample mode
(ADC12SHP = 0) with
buffered reference
1
µs
µs
(ADC12VRSEL = 0x1, 0x3,
0x5, 0x7, 0x9, 0xB, 0xD,
RS = 400 Ω, RI = 4 kΩ,
tSample
Sampling time
CI = 15 pF, Cpext= 8 pF(4)
0xF)
Extended sample mode
(ADC12SHP = 0) with
unbuffered reference
(ADC12VRSEL= 0x0, 0x2,
0x4, 0x6, 0xC, 0xE)
(5)
See
(1) The ADC12OSC is sourced directly from MODOSC inside the UCS.
(2) 14 × 1 / fADC12CLK. If ADC12WINC = 1, then 15 × 1 / fADC12CLK
(3) The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
(4) Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB: tsample = ln(2n+2) × (RS + RI) × (CI + Cpext), RS < 10 kΩ,
where n = ADC resolution = 12, RS= external source resistance, Cpext = external parasitic capacitance.
(5) 6 × 1 / fADC12CLK
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Table 4-24 lists the linearity parameters of the ADC when using an external reference.
Table 4-24. 12-Bit ADC, Linearity Parameters With External Reference(1)
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Number of no missing code
output-code bits
Resolution
EI
12
bits
Integral linearity error (INL) for
differential input
1.2 V ≤ VR+ – VR– ≤ AVCC
±1.8
LSB
Integral linearity error (INL) for
single ended inputs
EI
1.2 V ≤ VR+ – VR– ≤ AVCC
±2.2
+1.0
LSB
LSB
ED
Differential linearity error (DNL)
–0.99
ADC12VRSEL = 0x2 or 0x4 without TLV calibration,
TLV calibration data can be used to improve the
parameter(4)
EO
Offset error(2) (3)
±0.5
±0.8
±1
±1.5
±2.5
±20
mV
With external voltage reference without internal
buffer (ADC12VRSEL = 0x2 or 0x4) without TLV
calibration,
TLV calibration data can be used to improve the
parameter(4)
,
EG,ext
Gain error
LSB
VR+ = 2.5 V, VR– = AVSS
With external voltage reference with internal buffer
(ADC12VRSEL = 0x3),
VR+ = 2.5 V, VR– = AVSS
With external voltage reference without internal
buffer (ADC12VRSEL = 0x2 or 0x4) without TLV
calibration,
±1.4
±3.5
TLV calibration data can be used to improve the
parameter(4)
,
ET,ext
Total unadjusted error
LSB
VR+ = 2.5 V, VR– = AVSS
With external voltage reference with internal buffer
(ADC12VRSEL = 0x3),
±1.4
±21.0
VR+ = 2.5 V, VR– = AVSS
(1) See Table 4-26 and Table 4-32 for more information on internal reference performance, and see Designing With the MSP430FR59xx
and MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal or external
reference.
(2) Offset is measured as the input voltage (at which ADC output transitions from 0 to 1) minus 0.5 LSB.
(3) Offset increases as IR drop increases when VR– is AVSS.
(4) For details, see the device descriptor in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's
Guide.
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Table 4-25 lists the dynamic performance characteristics of the ADC with differential inputs and an
external reference.
Table 4-25. 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference(1)
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
Signal-to-noise
Effective number of bits(2)
TEST CONDITIONS
VR+ = 2.5 V, VR– = AVSS
VR+ = 2.5 V, VR– = AVSS
MIN
TYP
71
MAX UNIT
SNR
dB
ENOB
11.2
bits
(1) See Table 4-26 and Table 4-32 for more information on internal reference performance, and see Designing With the MSP430FR59xx
and MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal or external
reference.
(2) ENOB = (SINAD – 1.76) / 6.02
Table 4-26 lists the dynamic performance characteristics of the ADC with differential inputs and an internal
reference.
Table 4-26. 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference(1)
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
Effective number of bits(2)
TEST CONDITIONS
VR+ = 2.5 V, VR– = AVSS
MIN
TYP
MAX
UNIT
ENOB
10.7
Bits
(1) See Table 4-32 for more information on internal reference performance, and see Designing With the MSP430FR59xx and
MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal or external reference.
(2) ENOB = (SINAD – 1.76) / 6.02
Table 4-27 lists the dynamic performance characteristics of the ADC with single-ended inputs and an
external reference.
Table 4-27. 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference(1)
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
Signal-to-noise
Effective number of bits(2)
TEST CONDITIONS
VR+ = 2.5 V, VR– = AVSS
VR+ = 2.5 V, VR– = AVSS
MIN
TYP
68
MAX
UNIT
dB
SNR
ENOB
10.7
bits
(1) See Table 4-28 and Table 4-32 for more information on internal reference performance, and see Designing With the MSP430FR59xx
and MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal or external
reference.
(2) ENOB = (SINAD – 1.76) / 6.02
Table 4-28 lists the dynamic performance characteristics of the ADC with single-ended inputs and an
internal reference.
Table 4-28. 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference(1)
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
Effective number of bits(2)
TEST CONDITIONS
VR+ = 2.5 V, VR– = AVSS
MIN
TYP
MAX
UNIT
ENOB
10.4
bits
(1) See Table 4-32 for more information on internal reference performance, and see Designing With the MSP430FR59xx and
MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal or external reference.
(2) ENOB = (SINAD – 1.76) / 6.02
Table 4-29 lists the dynamic performance characteristics of the ADC using a 32.678-kHz clock.
Table 4-29. 12-Bit ADC, Dynamic Performance With 32.768-kHz Clock
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP UNIT
10 bits
Reduced performance with fADC12CLK from ACLK LFXT 32.768 kHz,
VR+ = 2.5 V, VR– = AVSS
ENOB
Effective number of bits(1)
(1) ENOB = (SINAD – 1.76) / 6.02
40
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Table 4-30 lists the characteristics of the temperature sensor and built-in V1/2 of the ADC.
Table 4-30. 12-Bit ADC, Temperature Sensor and Built-In V1/2
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
700
2.5
MAX UNIT
mV
ADC12ON = 1, ADC12TCMAP = 1,
TA = 0°C
VSENSOR
See (1) (2) (also see Figure 4-16)
(2)
TCSENSOR
tSENSOR(sample)
See
ADC12ON = 1, ADC12TCMAP = 1
mV/°C
µs
Sample time required if ADCTCMAP = 1 and
channel (MAX – 1) is selected(3)
ADC12ON = 1, ADC12TCMAP = 1,
Error of conversion result ≤ 1 LSB
30
AVCC voltage divider for ADC12BATMAP = 1
on MAX input channel
V1/2
ADC12ON = 1, ADC12BATMAP = 1
47.5%
50% 52.5%
38 63
IV 1/2
Current for battery monitor during sample time ADC12ON = 1, ADC12BATMAP = 1
µA
µs
Sample time required if ADC12BATMAP = 1
ADC12ON = 1, ADC12BATMAP = 1
and channel MAX is selected(4)
tV 1/2 (sample)
1.7
(1) The temperature sensor offset can be as much as ±30°C. TI recommends a single-point calibration to minimize the offset error of the
built-in temperature sensor.
(2) The device descriptor structure contains calibration values for 30°C ±3°C and 105°C ±3°C for each available reference voltage level.
The sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature, °C) + VSENSOR, where TCSENSOR and VSENSOR can be
computed from the calibration values for higher accuracy.
(3) The typical equivalent impedance of the sensor is 250 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
.
(4) The on-time tV1/2(on) is included in the sampling time tV1/2(sample); no additional on time is needed.
1000
900
800
700
600
500
400
300
200
100
0
-55
-30
-5
20
45
70
95
Temperature (°C)
D011
Figure 4-16. Typical Temperature Sensor Voltage
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Table 4-31 lists the external reference requirements for the ADC.
Table 4-31. 12-Bit ADC, External Reference(1)
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Positive external reference voltage input
VeREF+ or VeREF- based on ADC12VRSEL bit
VR+
VR+ > VR–
1.2
AVCC
V
Negative external reference voltage input
VeREF+ or VeREF- based on ADC12VRSEL bit
VR–
VR+ > VR–
VR+ > VR–
0
1.2
V
V
VR+ – VR–
Differential external reference voltage input
Static input current, singled-ended input mode
1.2
AVCC
1.2 V ≤ VeREF+ ≤ VAVCC, VeREF– = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 1h,
ADC12DIF = 0, ADC12PWRMD = 0
±10
±2.5
±20
±5
IVeREF+
IVeREF-
,
µA
µA
1.2 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 8h,
ADC12DIF = 0, ADC12PWRMD = 01
1.2 V ≤ VeREF+ ≤ VAVCC, VeREF– = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 1h,
ADC12DIF = 1, ADC12PWRMD = 0
IVeREF+
IVeREF-
,
Static input current, differential input mode
1.2 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 8h,
ADC12DIF = 1, ADC12PWRMD = 1
IVeREF+
IVeREF+
CVeREF+/-
Peak input current with single-ended input
Peak input current with differential input
Capacitance at VeREF+ or VeREF- terminal
0 V ≤ VeREF+ ≤ VAVCC, ADC12DIF = 0
0 V ≤ VeREF+ ≤ VAVCC, ADC12DIF = 1
1.5
3
mA
mA
µF
(2)
See
10
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
(2) Connect two decoupling capacitors, 10 µF and 470 nF, to VeREF to decouple the dynamic current required for an external reference
source if it is used for the ADC12_B. Also see the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family
User's Guide.
42
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4.11.9 Reference
Table 4-32 lists the characteristics of the built-in voltage reference.
Table 4-32. REF, Built-In Reference
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
2.5 ±1.5%
2.0 ±1.5%
MAX UNIT
REFVSEL = {2} for 2.5 V, REFON = 1
REFVSEL = {1} for 2.0 V, REFON = 1
REFVSEL = {0} for 1.2 V, REFON = 1
From 0.1 Hz to 10 Hz, REFVSEL = {0}
2.7 V
2.2 V
1.8 V
Positive built-in reference
voltage output
VREF+
V
1.2 ±1.8%
110
Noise
RMS noise at VREF(1)
µV
VREF ADC BUF_INT buffer TA = 25°C , ADC ON, REFVSEL = {0},
VOS_BUF_INT
–12
–12
12
12
mV
offset(2)
REFON = 1, REFOUT = 0
VREF ADC BUF_EXT
buffer offset(2)
TA = 25°C, REFVSEL = {0} , REFOUT = 1,
REFON = 1 or ADC ON
VOS_BUF_EXT
AVCC(min)
IREF+
mV
V
REFVSEL = {0} for 1.2 V
REFVSEL = {1} for 2.0 V
REFVSEL = {2} for 2.5 V
1.8
2.2
2.7
AVCC minimum voltage,
Positive built-in reference
active
Operating supply current
into AVCC terminal(3)
REFON = 1
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
8
225
15
355
µA
ADC ON, REFOUT = 0, REFVSEL = {0, 1, 2},
ADC12PWRMD = 0,
ADC ON, REFOUT = 1, REFVSEL = {0, 1, 2},
ADC12PWRMD = 0
1030
120
1680
240
Operating supply current
into AVCC terminal(3)
ADC ON, REFOUT = 0, REFVSEL = {0, 1, 2},
ADC12PWRMD = 1
IREF+_ADC_BUF
µA
µA
ADC ON, REFOUT = 1, REFVSEL = {0, 1, 2},
ADC12PWRMD = 1
545
895
ADC OFF, REFON = 1, REFOUT = 1,
REFVSEL = {0, 1, 2}
1085
1780
REFVSEL = {0, 1, 2}, AVCC = AVCC(min) for
each reference level,
REFON = REFOUT = 1
VREF maximum load
current, VREF+ terminal
IO(VREF+)
–1000
10
REFVSEL = {0, 1, 2},
ΔVout/ΔIo
(VREF+)
Load-current regulation,
VREF+ terminal
IO(VREF+) = +10 µA or –1000 µA,
AVCC = AVCC(min) for each reference level,
REFON = REFOUT = 1
2500 µV/mA
Capacitance at VREF+ and
VREF- terminals
CVREF+/-
TCREF+
REFON = REFOUT = 1
0
100
pF
Temperature coefficient of
built-in reference
REFVSEL = {0, 1, 2}, REFON = REFOUT = 1,
TA = –55°C to 105°C(4)
18
120
3.0
75
50 ppm/K
400 µV/V
mV/V
Power supply rejection ratio AVCC = AVCC(min) to AVCC(max), TA = 25°C,
(DC)
PSRR_DC
PSRR_AC
tSETTLE
REFVSEL = {0, 1, 2}, REFON = REFOUT = 1
Power supply rejection ratio
(AC)
dAVCC= 0.1 V at 1 kHz
Settling time of reference
voltage(5)
AVCC = AVCC (min) to AVCC(max)
REFVSEL = {0, 1, 2}, REFON = 0 → 1
,
80
µs
(1) Internal reference noise affects ADC performance when ADC uses internal reference. See Designing With the MSP430FR59xx and
MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal versus external
reference.
(2) Buffer offset affects ADC gain error and thus total unadjusted error.
(3) The internal reference current is supplied through terminal AVCC.
(4) Calculated using the box method: (MAX(–55°C to 105°C) – MIN(–55°C to 105°C)) / MIN(–55°C to 105°C)/(105°C – (–55°C)).
(5) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
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4.11.10 Comparator
Table 4-33 lists the characteristics of the comparator.
Table 4-33. Comparator_E
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
CEPWRMD = 00, CEON = 1,
CERSx = 00 (fast)
11
20
CEPWRMD = 01, CEON = 1,
CERSx = 00 (medium)
9
17
µA
0.5
Comparator operating supply
current into AVCC, excludes
reference resistor ladder
2.2 V,
3.0 V
IAVCC_COMP
CEPWRMD = 10, CEON = 1,
CERSx = 00 (slow), TA = 30°C
CEPWRMD = 10, CEON = 1,
CERSx = 00 (slow), TA = 85°C
1.3
CEREFLx = 01, CERSx = 10, REFON = 0,
CEON = 0, CEREFACC = 0
12
5
15
µA
7
Quiescent current of resistor
ladder into AVCC, including
REF module current
2.2 V,
3.0 V
IAVCC_REF
CEREFLx = 01, CERSx = 10, REFON = 0,
CEON = 0, CEREFACC = 1
CERSx = 11, CEREFLx = 01, CEREFACC = 0
CERSx = 11, CEREFLx = 10, CEREFACC = 0
CERSx = 11, CEREFLx = 11, CEREFACC = 0
CERSx = 11, CEREFLx = 01, CEREFACC = 1
CERSx = 11, CEREFLx = 10, CEREFACC = 1
CERSx = 11, CEREFLx = 11, CEREFACC = 1
1.8 V
2.2 V
2.7 V
1.8 V
2.2 V
2.7 V
1.17
1.92
2.40
1.10
1.90
2.35
0
1.2
2.0
2.5
1.2
2.0
2.5
1.23
2.08
2.60
V
1.245
VREF
Reference voltage level
2.08
2.60
VIC
Common-mode input range
Input offset voltage
VCC-1
32
V
CEPWRMD = 00
–32
–32
–30
VOFFSET
CEPWRMD = 01
32
mV
CEPWRMD = 10
30
CEPWRMD = 00 or CEPWRMD = 01
CEPWRMD = 10
9
9
1
CIN
Input capacitance
pF
On (switch closed)
3
kΩ
RSIN
Series input resistance
Off (switch open)
50
MΩ
CEPWRMD = 00, CEF = 0, Overdrive ≥ 20 mV
CEPWRMD = 01, CEF = 0, Overdrive ≥ 20 mV
CEPWRMD = 10, CEF = 0, Overdrive ≥ 20 mV
260
350
400
530
16
ns
Propagation delay, response
time
tPD
µs
ns
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 00
700
1.0
2.0
4.0
0.9
0.9
15
1200
2.0
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 01
Propagation delay with filter
active
tPD,filter
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 10
3.7
µs
µs
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 11
7.2
CEON = 0 → 1, VIN+, VIN- from pins,
Overdrive ≥ 20 mV, CEPWRMD = 00
2.0
CEON = 0 → 1, VIN+, VIN- from pins,
Overdrive ≥ 20 mV, CEPWRMD = 01
tEN_CMP
Comparator enable time
Comparator and reference
2.0
CEON = 0 → 1, VIN+, VIN- from pins,
Overdrive ≥ 20 mV, CEPWRMD = 10
100
CEON = 0 → 1, CEREFLX = 10, CERSx = 10 or 11,
tEN_CMP_VREF
ladder and reference voltage CEREF0 = CEREF1 = 0x0F,
350
1500
µs
V
enable time
Overdrive ≥ 20 mV
VIN ×
VIN ×
(n + 0.5) (n + 1)
/ 32 / 32
VIN ×
(n + 1.5)
/ 32
Reference voltage for a
given tap
VIN = reference into resistor ladder,
n = 0 to 31
VCE_REF
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4.11.11 FRAM
Table 4-34 lists the characteristics of the FRAM.
Table 4-34. FRAM
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
1014
100
40
TYP
MAX UNIT
Read and write endurance
cycles
TJ = 25°C
tRetention
Data retention duration
TJ = 70°C
years
TJ = 105°C
2.5
(1)
IWRITE
IERASE
tWRITE
Current to write into FRAM
Erase current
IREAD
nA
nA
ns
n/a(2)
(3)
Write time
tREAD
(4)
(4)
NWAITSx = 0
NWAITSx = 1
1 / fSYSTEM
2 / fSYSTEM
tREAD
Read time
ns
(1) Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read
current IREAD is included in the active mode current consumption numbers IAM,FRAM
.
(2) FRAM does not require a special erase sequence.
(3) Writing into FRAM is as fast as reading.
(4) The maximum read (and write) speed is specified by fSYSTEM using the appropriate wait state settings (NWAITSx).
4.12 Emulation and Debug
Table 4-35 lists the characteristics of the JTAG and Spy-Bi-Wire interface.
Table 4-35. JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
TEST
PARAMETER
MIN
TYP
MAX UNIT
CONDITIONS
2.2 V, 3.0 V
2.2 V, 3.0 V
2.2 V, 3.0 V
IJTAG
Supply current adder when JTAG active (but not clocked)
Spy-Bi-Wire input frequency
40
100
μA
fSBW
0
10 MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
0.04
15
110
100
μs
μs
μs
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge)(1)
tSBW, En
tSBW,Rst
2.2 V, 3.0 V
Spy-Bi-Wire return to normal operation time
TCK input frequency, 4-wire JTAG(2)
15
0
2.2 V
3.0 V
16 MHz
16 MHz
fTCK
0
Rinternal
Internal pulldown resistance on TEST
2.2 V, 3.0 V
20
35
50
kΩ
TCLK/MCLK frequency during JTAG access, no FRAM access
fTCLK
16 MHz
(limited by fSYSTEM
)
tTCLK,Low/High
fTCLK,FRAM
TCLK low or high clock pulse duration, no FRAM access
25
4
ns
MHz
ns
TCLK/MCLK frequency during JTAG access, including FRAM access
(limited by fSYSTEM with no FRAM wait states)
tTCLK,FRAM,Low/High TCLK low or high clock pulse duration, including FRAM accesses
100
(1) Tools that access the Spy-Bi-Wire and BSL interfaces must wait for the tSBW,En time after the first transition of the TEST/SBWTCK pin
(low to high), before the second transition of the pin (high to low) during the entry sequence.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
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5 Detailed Description
5.1 Overview
The Texas Instruments MSP430FR5969-SP ultra-low-power microcontroller includes several different sets
of peripherals. The architecture, combined with seven low-power modes is optimized for distributed
telemetry applications. The devices features a powerful 16-bit RISC CPU, 16-bit registers, and constant
generators that contribute to maximum code efficiency.
The MSP430FR5969-SP microcontroller comprises up to five 16-bit timers, Comparator, universal serial
communication interfaces (eUSCI) supporting UART, SPI, and I2C, hardware multiplier, AES accelerator,
DMA, real-time clock module with alarm capabilities, up to 40 I/O pins, and an high-performance 12-bit
analog-to-digital converter (ADC).
5.2 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-
register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data.
46
Detailed Description
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5.3 Operating Modes
The MSP430FR5969-SP MCU has one active mode and seven software-selectable low-power modes of operation (see 表 5-1). An interrupt event
can wake up the device from a low-power mode (LPM0 to LPM4), service the request, and restore back to the low-power mode on return from the
interrupt program. Low-power modes LPM3.5 and LPM4.5 disable the core supply to minimize power consumption.
表 5-1. Operating Modes
MODE
AM
LPM0
LPM1
LPM2
LPM3
LPM4
OFF
LPM3.5
LPM4.5
ACTIVE,
FRAM
SHUTDOWN
SHUTDOWN
ACTIVE
16 MHz
103 µA/MHz 65 µA/MHz
N/A
CPU Off(2)
CPU OFF
STANDBY
STANDBY
RTC ONLY
WITH SVS
WITHOUT SVS
OFF(1)
Maximum system clock
16 MHz
70 µA at 1 MHz
instant
16 MHz
35 µA at 1 MHz
6 µs
50 kHz
0.7 µA
6 µs
50 kHz
0.4 µA
7 µs
0(3)
0.3 µA
7 µs
50 kHz
0.25 µA
250 µs
0(3)
Typical current consumption,
TA = 25°C
0.2 µA
250 µs
0.02 µA
1000 µs
Typical wake-up time
LF
I/O
Comp
LF
I/O
Comp
I/O
Comp
RTC
I/O
Wake-up events
N/A
all
all
I/O
CPU
on
off
off
off
off
off
off
off
off
off
reset
off
reset
off
standby
FRAM
on
off(1)
(or off(1)
)
Peripherals in high-frequency
state(4)
yes
yes
yes
yes
yes
yes
no
yes
yes
off
no
no
no
reset
RTC
reset
off
reset
reset
reset
off
Peripherals in low-frequency
state(4)
yes
yes
off
yes(5)
yes(5)
off
Peripherals in unclocked
state(4)
yes
on
(16 MHzMAX
optional(6)
yes(5)
off
MCLK
SMCLK
ACLK
off
)
optional(6)
(16 MHzMAX
optional(6)
(16 MHzMAX
off
off
off
off
off
(16 MHzMAX
)
)
)
)
)
on
on
on
on
on
off
off
off
(50 kHzMAX
)
(50 kHzMAX
)
(50 kHzMAX
)
(50 kHzMAX
)
(50 kHzMAX)
optional
(16 MHzMAX
optional
(16 MHzMAX
optional
(16 MHzMAX
optional
(50 kHzMAX
optional
(50 kHzMAX
optional
(50 kHzMAX)
External clock
Full retention
off
no
off
no
)
)
)
yes
yes
yes
yes
yes
yes
(1) FRAM disabled in FRAM controller
(2) Disabling the FRAM through the FRAM controller allows the application to lower the LPM current consumption but the wake-up time increases as soon as FRAM is accessed (for example,
to fetch an interrupt vector). For a wakeup that does not involve the FRAM (for example, DMA transfer to RAM), the wakeup is not delayed.
(3) All clocks disabled
(4) See 表 5-2 for a detailed description of peripherals in high-frequency, low-frequency, or unclocked state.
(5) See 节 5.3.1, which describes the use of peripherals in LPM3 and LPM4.
(6) Controlled by SMCLKOFF.
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表 5-1. Operating Modes (continued)
MODE
AM
LPM0
LPM1
LPM2
LPM3
LPM4
OFF
LPM3.5
LPM4.5
ACTIVE,
FRAM
SHUTDOWN
WITH SVS
SHUTDOWN
WITHOUT SVS
ACTIVE
CPU Off(2)
CPU OFF
STANDBY
STANDBY
RTC ONLY
OFF(1)
SVS
always
always
always
optional(7)
optional(7)
optional(7)
optional(7)
on(8)
off(9)
Brownout
always
always
always
always
always
always
always
always
(7) Activated SVS (SVSHE = 1) results in higher current consumption. SVS is not included in typical current consumption.
(8) SVSHE = 1
(9) SVSHE = 0
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5.3.1 Peripherals in Low-Power Modes
Peripherals can be in different states that impact the achievable power modes of the device. The states
depend on the operational modes of the peripherals. The states are:
•
•
•
A peripheral is in a "high frequency state" if it requires or uses a clock with a "high" frequency of more
than 50 kHz.
A peripheral is in a "low frequency state" if it requires or uses a clock with a "low" frequency of 50 kHz
or less.
A peripheral is in an "unclocked state" if it does not require nor use an internal clock.
If the CPU requests a power mode that does not support the current state of all active peripherals, the
device cannot enter the requested power mode but does enter a power mode that still supports the current
state of the peripherals, unless an external clock is used. If an external clock is used, the application must
ensure the correct frequency range for the requested power mode.
表 5-2. Peripheral States
PERIPHERAL
WDT
DMA(4)
IN HIGH-FREQUENCY STATE(1)
Clocked by SMCLK
Not applicable
IN LOW-FREQUENCY STATE(2)
Clocked by ACLK
IN UNCLOCKED STATE(3)
Not applicable
Not applicable
Waiting for a trigger
Not applicable
RTC_B
Not applicable
Clocked by LFXT
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
Timer_A, TAx
Timer_B, TBx
Clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
Waiting for first edge of START bit
Not applicable
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
eUSCI_Ax in
UART mode
Clocked by SMCLK
Clocked by ACLK
eUSCI_Ax in SPI
master mode
Clocked by SMCLK
Clocked by ACLK
eUSCI_Ax in SPI
slave mode
eUSCI_Bx in I2C Clocked by SMCLK or
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
Not applicable
Clocked by ACLK or
clocked by external clock ≤50 kHz
master mode
clocked by external clock >50 kHz
eUSCI_Bx in I2C
slave mode
Waiting for START condition or
clocked by external clock ≤50 kHz
Clocked by external clock >50 kHz
Clocked by SMCLK
Clocked by external clock ≤50 kHz
Clocked by ACLK
eUSCI_Bx in SPI
master mode
Not applicable
eUSCI_Bx in SPI
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
ADC12_B
REF_A
COMP_E
CRC(5)
MPY(5)
AES(5)
Clocked by SMCLK or by MODOSC
Not applicable
Clocked by ACLK
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Waiting for a trigger
Always
Not applicable
Always
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
(1) Peripherals are in a state that requires or uses a clock with a "high" frequency of more than 50 kHz.
(2) Peripherals are in a state that requires or uses a clock with a "low" frequency of 50 kHz or less.
(3) Peripherals are in a state that does not require or does not use an internal clock.
(4) The DMA always transfers data in active mode but can wait for a trigger in any low power mode. A DMA trigger during a low power
mode will cause a temporary transition into active mode for the time of the transfer.
(5) Operates only during active mode and will eventually delay the transition into a low power mode until its operation is completed.
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5.3.1.1 Idle Currents of Peripherals in LPM3 and LPM4
Most peripherals can be activated to be operational in LPM3 if clocked by ACLK. Some modules are
operational in LPM4, because they do not require a clock to operate (for example, the comparator).
Activating a peripheral in LPM3 or LPM4 increases the current consumption due to its active supply
current contribution but also due to an additional idle current. To limit the idle current adder, certain
peripherals are grouped together. To achieve optimal current consumption, use modules within one group
and limit the number of groups with active modules. 表 5-3 lists the grouping of the peripherals. Modules
not listed in this table are either already included in the standard LPM3 current consumption or cannot be
used in LPM3 or LPM4.
The idle current adder is very small at room temperature (25°C) but increases at high temperatures
(85°C), See the IIDLE current parameters in Section 4.7 for details.
表 5-3. Peripheral Groups
Group A
Timer TA1
Timer TA2
Timer TB0
eUSCI_A0
eUSCI_A1
eUSCI_B0
Group B
Timer TA0
Timer TA3
Comparator
ADC12_B
REF_A
5.4 Interrupt Vector Table and Signatures
The interrupt vectors, the power-up start address and signatures are in the address range 0FFFFh to
0FF80h. 图 5-1 summarizes the content of this address range.
0FFFFh
Reset Vector
BSL Password
Interrupt
Vectors
0FFE0h
JTAG Password
Reserved
0FF88h
0FF80h
Signatures
图 5-1. Interrupt Vectors, Signatures and Passwords
The power-up start address or reset vector is at 0FFFFh to 0FFFEh. It contains a 16-bit address that
points to the start address of the application program.
The interrupt vectors start at 0FFFDh and extend to lower addresses. Each vector contains the 16-bit
address of the appropriate interrupt-handler instruction sequence. 表 5-4 lists the device specific interrupt
vector locations.
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The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as BSL password (if
enabled by the corresponding signature).
The signatures are located at 0FF80h extending to higher addresses. Signatures are evaluated during
device start-up. 表 5-5 lists the device specific signature locations.
A JTAG password can be programmed starting from address 0FF88h and extending to higher addresses.
The password can extend into the interrupt vector locations using the interrupt vector addresses as
additional bits for the password. The length of the JTAG password depends on the JTAG signature.
See the System Resets, Interrupts, and Operating Modes, System Control Module (SYS) chapter in the
MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide for details.
表 5-4. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
System Reset
Power up, Brownout, Supply Supervisor
External Reset RST
Watchdog Time-out (Watchdog mode)
WDT, FRCTL MPU, CS, PMM Password
Violation
SVSHIFG
PMMRSTIFG
WDTIFG
WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW
UBDIFG
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
Reset
0FFFEh
highest
FRAM uncorrectable bit error detection
MPU segment violation
ACCTEIFG
FRAM access time error
Software POR, BOR
PMMPORIFG, PMMBORIFG
(SYSRSTIV)(1)
(2)
System NMI
Vacant Memory Access
JTAG Mailbox
VMAIFG
JMBNIFG, JMBOUTIFG
CBDIFG, UBDIFG
(Non)maskable
(Non)maskable
0FFFCh
0FFFAh
FRAM bit error detection
MPU segment violation
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
(3)
(SYSSNIV)(1)
User NMI
External NMI
Oscillator Fault
NMIIFG, OFIFG
(3)
(SYSUNIV)(1)
CEIFG, CEIIFG
(CEIV)(1)
Comparator_E
TB0
Maskable
Maskable
0FFF8h
0FFF6h
TB0CCR0.CCIFG
TB0CCR1.CCIFG ... TB0CCR6.CCIFG,
TB0CTL.TBIFG
TB0
Maskable
Maskable
0FFF4h
0FFF2h
(TB0IV)(1)
Watchdog Timer (Interval Timer Mode)
WDTIFG
UCA0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA0IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
eUSCI_A0 Receive or Transmit
eUSCI_B0 Receive or Transmit
ADC12_B
Maskable
Maskable
Maskable
0FFF0h
0FFEEh
0FFECh
(UCA0IV)(1)
UCB0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB0IFG: UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1,
UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3,
UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB0IV)(1)
ADC12IFG0 to ADC12IFG31
ADC12LOIFG, ADC12INIFG, ADC12HIIFG,
ADC12RDYIFG, ADC21OVIFG, ADC12TOVIFG
(ADC12IV)(1)
TA0
TA0
TA0CCR0.CCIFG
Maskable
Maskable
0FFEAh
0FFE8h
TA0CCR1.CCIFG, TA0CCR2.CCIFG,
TA0CTL.TAIFG
(TA0IV)(1)
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space
(3) (Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot disable it.
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PRIORITY
表 5-4. Interrupt Sources, Flags, and Vectors (continued)
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
UCA1IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA1IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
eUSCI_A1 Receive or Transmit
Maskable
0FFE6h
(UCA1IV)(1)
DMA0CTL.DMAIFG, DMA1CTL.DMAIFG,
DMA2CTL.DMAIFG
DMA
TA1
TA1
Maskable
Maskable
Maskable
0FFE4h
0FFE2h
0FFE0h
(DMAIV)(1)
TA1CCR0.CCIFG
TA1CCR1.CCIFG, TA1CCR2.CCIFG,
TA1CTL.TAIFG
(TA1IV)(1)
P1IFG.0 to P1IFG.7
(P1IV)(1)
I/O Port P1
TA2
Maskable
Maskable
0FFDEh
0FFDCh
TA2CCR0.CCIFG
TA2CCR1.CCIFG
TA2CTL.TAIFG
(TA2IV)(1)
TA2
Maskable
0FFDAh
P2IFG.0 to P2IFG.7
(P2IV)(1)
I/O Port P2
TA3
Maskable
Maskable
0FFD8h
0FFD6h
TA3CCR0.CCIFG
TA3CCR1.CCIFG
TA3CTL.TAIFG
(TA3IV)(1)
TA3
Maskable
0FFD4h
P3IFG.0 to P3IFG.7
(P3IV)(1)
I/O Port P3
I/O Port P4
Maskable
Maskable
0FFD2h
0FFD0h
P4IFG.0 to P4IFG.2
(P4IV)(1)
RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG,
RT1PSIFG, RTCOFIFG
RTC_B
AES
Maskable
Maskable
0FFCEh
0FFCCh
(RTCIV)(1)
AESRDYIFG
lowest
表 5-5. Signatures
SIGNATURE
IP Encapsulation Signature 2
IP Encapsulation Signature 1(1)
BSL Signature 2
WORD ADDRESS
0FF8Ah
0FF88h
0FF86h
0FF84h
0FF82h
0FF80h
BSL Signature 1
JTAG Signature 2
JTAG Signature 1
(1) Must not contain 0AAAAh if used as JTAG password and IP encapsulation functionality is not desired.
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5.5 Memory Organization
表 5-6 summarizes the memory map for all device variants.
表 5-6. Memory Organization(1)
MSP430FR5969-SP
Memory (FRAM)
63KB
Main: interrupt vectors and signatures
Main: code memory
Total Size
00FFFFh–00FF80h
013FFFh–004400h
2KB
RAM
0023FFh–001C00h
256 B
001AFFh–001A00h
Device Descriptor Info (TLV) (FRAM)
128 B
0019FFh–001980h
Info A
Info B
Info C
Info D
BSL 3
BSL 2
BSL 1
BSL 0
Size
128 B
00197Fh–001900h
Information memory (FRAM)
128 B
0018FFh–001880h
128 B
00187Fh–001800h
512 B
0017FFh–001600h
512 B
0015FFh–001400h
Bootloader (BSL) memory (ROM)
512 B
0013FFh–001200h
512 B
0011FFh–001000h
4KB
000FFFh–0h
Peripherals
(1) All address space not listed is considered vacant memory.
5.6 Bootloader (BSL)
The BSL enables users to program the FRAM or RAM using a UART serial interface (FRxxxx devices).
Access to the device memory through the BSL is protected by an user-defined password. 表 5-7 list the
BSL pins requirements. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and
TEST/SBWTCK pins. For a complete description of the features of the BSL and its implementation, see
the MSP430 Programming With the Bootloader (BSL).
表 5-7. BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
Entry sequence signal
RST/NMI/SBWTDIO
TEST/SBWTCK
Entry sequence signal
P2.0
P2.1
VCC
VSS
Devices with UART BSL (FRxxxx): Data transmit
Devices with UART BSL (FRxxxx): Data receive
Power supply
Ground supply
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5.7 JTAG Operation
5.7.1 JTAG Standard Interface
The MSP430 supports the standard JTAG interface which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable
the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430 development tools and device programmers. 表 5-8 lists the JTAG pin requirements. For further
details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools
User's Guide. For a complete description of the features of the JTAG interface and its implementation, see
MSP430 Programming With the JTAG Interface.
表 5-8. JTAG Pin Requirements and Functions
DEVICE SIGNAL
PJ.3/TCK
DIRECTION
FUNCTION
JTAG clock input
JTAG state control
JTAG data input, TCLK input
JTAG data output
Enable JTAG pins
External reset
IN
IN
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
IN
OUT
IN
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
IN
Power supply
VSS
Ground supply
5.7.2 Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 supports the 2-wire Spy-Bi-Wire interface. Spy-Bi-
Wire can be used to interface with MSP430 development tools and device programmers. 表 5-9 lists the
Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and device
programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the features
of the JTAG interface and its implementation, see MSP430 Programming With the JTAG Interface.
表 5-9. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
DIRECTION
IN
FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input and output
Power supply
IN, OUT
VSS
Ground supply
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5.8 FRAM
The FRAM can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. Features of the FRAM include:
•
•
•
•
Ultra-low-power ultra-fast-write nonvolatile memory
Byte and word access capability
Programmable wait state generation
Error correction coding (ECC)
注
Wait States
For MCLK frequencies > 8 MHz, wait states must be configured following the flow described
in the Wait State Control section of the FRAM Controller (FRCTRL) chapter in the
MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide.
For important software design information regarding FRAM including but not limited to partitioning the
memory layout according to application-specific code, constant, and data space requirements, the use of
FRAM to optimize application energy consumption, and the use of the Memory Protection Unit (MPU) to
maximize application robustness by protecting the program code against unintended write accesses, see
MSP430™ FRAM Technology – How To and Best Practices.
5.9 Memory Protection Unit Including IP Encapsulation
The FRAM can be protected from inadvertent CPU execution, read access, or write access by the MPU.
Features of the MPU include:
•
IP encapsulation with programmable boundaries in steps of 1KB (prevents reads from "outside"; for
example, JTAG or non-IP software).
•
•
•
Main memory partitioning is programmable up to three segments in steps of 1KB.
Each segment's access rights can be individually selected (main and information memory).
Access violation flags with interrupt capability for easy servicing of access violations.
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5.10 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
handled using all instructions. For complete module descriptions, see the MSP430FR58xx,
MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide.
5.10.1 Digital I/O
Up to four 8-bit I/O ports are implemented:
•
•
•
•
•
•
•
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Programmable pullup or pulldown on all ports.
Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for all ports.
Read and write access to port control registers is supported by all instructions.
Ports can be accessed byte-wise or word-wise in pairs.
No cross-currents during start-up.
注
Configuration of Digital I/Os After BOR Reset
To prevent any cross currents during start-up of the device, all port pins are high-impedance
with Schmitt triggers, and their module functions disabled. To enable the I/O functionality
after a BOR reset, the ports must be configured first and then the LOCKLPM5 bit must be
cleared. For details, see the Configuration After Reset section of the Digital I/O chapter in the
MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide.
5.10.2 Oscillator and Clock System (CS)
The clock system includes support for a 32-kHz watch-crystal oscillator (XT1), an internal very-low-power
low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a high-
frequency crystal oscillator XT2. The clock system module is designed to meet the requirements of both
low system cost and low power consumption. A fail-safe mechanism exists for all crystal sources. The
clock system module provides the following clock signals:
•
Auxiliary clock (ACLK). ACLK can be sourced from a 32-kHz watch crystal (LFXT1), the internal low-
frequency oscillator (VLO), or a digital external low-frequency (<50 kHz) clock source.
•
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced from a high-frequency
crystal (HFXT2), the internal digitally controlled oscillator DCO, a 32-kHz watch crystal (LFXT1), the
internal low-frequency oscillator (VLO), or a digital external clock source.
•
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by same sources made available to MCLK.
5.10.3 Power-Management Module (PMM)
The primary functions of the PMM are:
•
•
•
Supply regulated voltages to the core logic
Supervise voltages that are connected to the device (at DVCC pins)
Give reset signals to the device during power on and power off
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5.10.4 Hardware Multiplier (MPY)
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed multiplication, unsigned
multiplication, signed multiply-and-accumulate, and unsigned multiply-and-accumulate operations.
5.10.5 Real-Time Clock (RTC_B) (Only MSP430FR596x and MSP430FR594x)
The RTC_B module contains an integrated real-time clock (RTC). The RTC integrates an internal calendar
that compensates for months with less than 31 days and includes leap year correction. The RTC_B also
supports flexible alarm functions and offset-calibration hardware. RTC operation is available in LPM3.5
modes to minimize power consumption.
5.10.6 Watchdog Timer (WDT_A)
The primary function of the WDT_A module is to perform a controlled system restart if a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not
needed in an application, the module can be configured as an interval timer and can generate interrupts at
selected time intervals. 表 5-10 lists the clock sources for the WDT_A module.
表 5-10. WDT_A Clocks
NORMAL OPERATION
WDTSSEL
(WATCHDOG AND INTERVAL TIMER MODE)
00
01
10
11
SMCLK
ACLK
VLOCLK
LFMODCLK
5.10.7 System Module (SYS)
The SYS module manages many of the system functions within the device. These system functions
include power on reset (POR) and power up clear (PUC) handling, NMI source selection and
management, reset interrupt vector generators, bootloader (BSL) entry mechanisms, and configuration
management (device descriptors). The SYS module also includes a data exchange mechanism through
JTAG called a JTAG mailbox that can be used in the application. 表 5-11 lists the SYS module interrupt
vector registers.
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表 5-11. System Module Interrupt Vector Registers
INTERRUPT VECTOR
REGISTER
ADDRESS
INTERRUPT EVENT
VALUE
PRIORITY
No interrupt pending
Brownout (BOR)
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
Highest
RSTIFG RST/NMI (BOR)
PMMSWBOR software BOR (BOR)
LPMx.5 wakeup (BOR)
Security violation (BOR)
Reserved
SVSHIFG SVSH event (BOR)
Reserved
Reserved
PMMSWPOR software POR (POR)
WDTIFG watchdog time-out (PUC)
WDTPW password violation (PUC)
FRCTLPW password violation (PUC)
Uncorrectable FRAM bit error detection (PUC)
Peripheral area fetch (PUC)
PMMPW PMM password violation (PUC)
MPUPW MPU password violation (PUC)
CSPW CS password violation (PUC)
SYSRSTIV, System Reset
019Eh
MPUSEGPIFG encapsulated IP memory segment violation
(PUC)
26h
MPUSEGIIFG information memory segment violation (PUC)
MPUSEG1IFG segment 1 memory violation (PUC)
MPUSEG2IFG segment 2 memory violation (PUC)
MPUSEG3IFG segment 3 memory violation (PUC)
28h
2Ah
2Ch
2Eh
(1)
ACCTEIFG access time error (PUC)
30h
Reserved
No interrupt pending
32h to 3Eh
00h
Lowest
Highest
Reserved
02h
Uncorrectable FRAM bit error detection
Reserved
04h
06h
MPUSEGPIFG encapsulated IP memory segment violation
MPUSEGIIFG information memory segment violation
MPUSEG1IFG segment 1 memory violation
MPUSEG2IFG segment 2 memory violation
MPUSEG3IFG segment 3 memory violation
VMAIFG vacant memory access
JMBINIFG JTAG mailbox input
08h
0Ah
0Ch
0Eh
SYSSNIV, System NMI
019Ch
10h
12h
14h
JMBOUTIFG JTAG mailbox output
Correctable FRAM bit error detection
16h
18h
1Ah to
1Eh
Reserved
Lowest
(1) Indicates incorrect wait state settings.
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表 5-11. System Module Interrupt Vector Registers (continued)
INTERRUPT VECTOR
ADDRESS
INTERRUPT EVENT
VALUE
PRIORITY
REGISTER
No interrupt pending
NMIIFG NMI pin
OFIFG oscillator fault
Reserved
00h
02h
04h
06h
08h
Highest
SYSUNIV, User NMI
019Ah
Reserved
0Ah to
1Eh
Reserved
Lowest
5.10.8 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC12_B conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to wake to move data to or from a peripheral. 表 5-12 lists the available triggers for the DMA.
表 5-12. DMA Trigger Assignments(1)
TRIGGER
CHANNEL 0
DMAREQ
CHANNEL 1
DMAREQ
CHANNEL 2
DMAREQ
0
1
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA3CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA3CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA3CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
Reserved
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Reserved
Reserved
Reserved
AES Trigger 0
AES Trigger 1
AES Trigger 2
UCA0RXIFG
AES Trigger 0
AES Trigger 1
AES Trigger 2
UCA0RXIFG
AES Trigger 0
AES Trigger 1
AES Trigger 2
UCA0RXIFG
UCA0TXIFG
UCA0TXIFG
UCA0TXIFG
UCA1RXIFG
UCA1RXIFG
UCA1RXIFG
UCA1TXIFG
UCA1TXIFG
UCA1TXIFG
UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)
UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)
UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)
18
19
UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)
UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)
UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)
20
21
22
23
24
25
26
27
UCB0RXIFG1 (I2C)
UCB0TXIFG1 (I2C)
UCB0RXIFG2 (I2C)
UCB0TXIFG2 (I2C)
UCB0RXIFG3 (I2C)
UCB0TXIFG3 (I2C)
ADC12 end of conversion
Reserved
UCB0RXIFG1 (I2C)
UCB0TXIFG1 (I2C)
UCB0RXIFG2 (I2C)
UCB0TXIFG2 (I2C)
UCB0RXIFG3 (I2C)
UCB0TXIFG3 (I2C)
ADC12 end of conversion
Reserved
UCB0RXIFG1 (I2C)
UCB0TXIFG1 (I2C)
UCB0RXIFG2 (I2C)
UCB0TXIFG2 (I2C)
UCB0RXIFG3 (I2C)
UCB0TXIFG3 (I2C)
ADC12 end of conversion
Reserved
(1) If a reserved trigger source is selected, no trigger is generated.
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表 5-12. DMA Trigger Assignments(1) (continued)
TRIGGER
CHANNEL 0
Reserved
MPY ready
DMA2IFG
DMAE0
CHANNEL 1
Reserved
MPY ready
DMA0IFG
DMAE0
CHANNEL 2
28
29
30
31
Reserved
MPY ready
DMA1IFG
DMAE0
5.10.9 Enhanced Universal Serial Communication Interface (eUSCI)
The eUSCI modules are used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols
such as UART, enhanced UART with automatic baudrate detection, and IrDA.
The eUSCI_An module provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.
The eUSCI_Bn module provides support for SPI (3 or 4 pin) and I2C.
Two eUSCI_A modules and one eUSCI_B module are implemented.
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5.10.10 TA0, TA1
TA0 and TA1 are 16-bit timers and counters (Timer_A type) with three capture/compare registers each.
TA0 and TA can support multiple captures or compares, PWM outputs, and interval timing (see 表 5-13
and 表 5-14). TA0 and TA have extensive interrupt capabilities. Interrupts may be generated from the
counter on overflow conditions and from each of the capture/compare registers.
表 5-13. TA0 Signal Connections
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
MODULE
BLOCK
INPUT PORT PIN
OUTPUT PORT PIN
P1.2
TA0CLK
ACLK (internal)
SMCLK (internal)
TA0CLK
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
CCR0
N/A
TA0
N/A
P1.2
P1.6
P2.3
TA0.0
P1.6
P2.3
TA0.0
TA0.0
DVSS
DVCC
VCC
P1.0
P1.1
TA0.1
CCI1A
P1.0
ADC12(internal)
ADC12SHSx = {1}
COUT (internal)
CCI1B
CCR1
CCR2
TA1
TA2
TA0.1
TA0.2
DVSS
DVCC
GND
VCC
TA0.2
CCI2A
CCI2B
GND
VCC
P1.1
ACLK (internal)
DVSS
DVCC
表 5-14. TA1 Signal Connections
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
DEVICE INPUT
SIGNAL
MODULE INPUT
MODULE
BLOCK
INPUT PORT PIN
OUTPUT PORT PIN
SIGNAL
P1.1
TA1CLK
ACLK (internal)
SMCLK (internal)
TA1CLK
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
CCR0
N/A
TA0
N/A
P1.1
P1.7
P2.4
TA1.0
P1.7
P2.4
TA1.0
TA1.0
DVSS
DVCC
VCC
P1.2
P1.3
TA1.1
CCI1A
P1.2
ADC12(internal)
ADC12SHSx = {4}
COUT (internal)
CCI1B
CCR1
CCR2
TA1
TA2
TA1.1
TA1.2
DVSS
DVCC
GND
VCC
TA1.2
CCI2A
CCI2B
GND
VCC
P1.3
ACLK (internal)
DVSS
DVCC
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5.10.11 TA2, TA3
TA2 and TA3 are 16-bit timers and counters (Timer_A type) with two capture/compare registers each and
with internal connections only. TA2 and TA3 can support multiple captures or compares, PWM outputs,
and interval timing (see 表 5-15 and 表 5-16). TA2 and TA3 have extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
表 5-15. TA2 Signal Connections
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
DEVICE INPUT SIGNAL
MODULE INPUT NAME
MODULE BLOCK
COUT (internal)
ACLK (internal)
SMCLK (internal)
TACLK
ACLK
Timer
N/A
TA0
TA1
SMCLK
TA3 CCR0 output
(internal)
CCI0A
TA3 CCI0A input
ACLK (internal)
DVSS
CCI0B
GND
VCC
CCR0
CCR1
DVCC
COUT (internal)
DVSS
CCI1B
GND
VCC
DVCC
表 5-16. TA3 Signal Connections
MODULE OUTPUT
DEVICE OUTPUT
SIGNAL
DEVICE INPUT SIGNAL
MODULE INPUT NAME
MODULE BLOCK
SIGNAL
COUT (internal)
ACLK (internal)
SMCLK (internal)
TACLK
ACLK
Timer
N/A
SMCLK
TA2 CCR0 output
(internal)
CCI0A
TA2 CCI0A input
ACLK (internal)
DVSS
CCI0B
GND
VCC
CCR0
CCR1
TA0
TA1
DVCC
COUT (internal)
DVSS
CCI1B
GND
VCC
DVCC
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5.10.12 TB0
TB0 is a 16-bit timer and counter (Timer_B type) with seven capture/compare registers. TB0 can support
multiple captures or compares, PWM outputs, and interval timing (see 表 5-17). TB0 has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers.
表 5-17. TB0 Signal Connections
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
MODULE
BLOCK
INPUT PORT PIN
OUTPUT PORT PIN
P2.0
TB0CLK
ACLK (internal)
SMCLK (internal)
TB0CLK
TBCLK
ACLK
Timer
CCR0
N/A
N/A
SMCLK
INCLK
CCI0A
CCI0B
P2.0
P2.1
P2.5
TB0.0
P2.1
P2.5
TB0.0
TB0
TB0.0
ADC12 (internal)
ADC12SHSx = {2}
DVSS
GND
DVCC
TB0.1
VCC
P1.4
P1.5
CCI1A
CCI1B
P1.4
P2.6
COUT (internal)
CCR1
TB1
TB0.1
ADC12 (internal)
ADC12SHSx = {3}
DVSS
GND
DVCC
TB0.2
VCC
CCI2A
CCI2B
GND
P1.5
P2.2
ACLK (internal)
DVSS
CCR2
CCR3
CCR4
CCR5
CCR6
TB2
TB3
TB4
TB5
TB6
TB0.2
TB0.3
TB0.4
TB0.5
TB0.6
DVCC
TB0.3
VCC
P3.4
P1.6
CCI3A
CCI3B
GND
P3.4
P1.6
TB0.3
DVSS
DVCC
TB0.4
VCC
P3.5
P1.7
CCI4A
CCI4B
GND
P3.5
P1.7
TB0.4
DVSS
DVCC
TB0.5
VCC
P3.6
P4.4
CCI5A
CCI5B
GND
P3.6
P4.4
TB0.5
DVSS
DVCC
TB0.6
VCC
P3.7
P2.0
CCI6A
CCI6B
GND
P3.7
P2.0
TB0.6
DVSS
DVCC
VCC
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5.10.13 ADC12_B
The ADC12_B module supports fast 12-bit analog-to-digital conversions with differential and single-ended
inputs. The module implements a 12-bit SAR core, sample select control, reference generator, and a
conversion result buffer. A window comparator with lower and upper limits allows CPU-independent result
monitoring with three window comparator interrupt flags.
表 5-18 lists the external trigger sources.
表 5-18. ADC12_B Trigger Signal Connections
ADC12SHSx
CONNECTED TRIGGER
SOURCE
BINARY
DECIMAL
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
Software (ADC12SC)
TA0 CCR1 output
TB0 CCR0 output
TB0 CCR1 output
TA1 CCR1 output
TA2 CCR1 output
TA3 CCR1 output
Reserved (DVSS)
表 5-19 lists the available multiplexing between internal and external analog inputs.
表 5-19. ADC12_B External and Internal Signal Mapping
CONTROL BIT IN ADC12CTL3
REGISTER
EXTERNAL ADC INPUT
(CONTROL BIT = 0)
INTERNAL ADC INPUT
(CONTROL BIT = 1)
ADC12BATMAP
ADC12TCMAP
ADC12CH0MAP
ADC12CH1MAP
ADC12CH2MAP
ADC12CH3MAP
A31
A30
A29
A28
A27
A26
Battery monitor
Temperature sensor
N/A(1)
N/A(1)
N/A(1)
N/A(1)
(1) N/A = No internal signal is available on this device.
5.10.14 Comparator_E
The primary function of the Comparator_E module is to support precision slope analog-to-digital
conversions, battery voltage supervision, and monitoring of external analog signals.
5.10.15 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking. The CRC16 module signature is based on the CRC-CCITT standard.
5.10.16 AES256 Accelerator
The AES accelerator module performs encryption and decryption of 128-bit data with 128-, 192-, or 256-
bit keys according to the Advanced Encryption Standard (AES) (FIPS PUB 197) in hardware.
5.10.17 True Random Seed
The Device Descriptor (TLV) (see 节 5.12) contains a 128-bit true random seed that can be used to
implement a deterministic random number generator.
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5.10.18 Shared Reference (REF)
The REF module generates all of the critical reference voltages that can be used by the various analog
peripherals in the device.
5.10.19 Embedded Emulation
5.10.19.1 Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The S version of the EEM has the following features:
•
•
•
•
•
Three hardware triggers or breakpoints on memory access
One hardware trigger or breakpoint on CPU register write access
Up to four hardware triggers that can be combined to form complex triggers or breakpoints
One cycle counter
Clock control on module level
5.10.19.2 EnergyTrace++ Technology
The devices implement circuitry to support EnergyTrace++ technology. The EnergyTrace++ technology
allows you to observe information about the internal states of the microcontroller. These states include the
CPU Program Counter (PC), the ON or OFF status of the peripherals and the system clocks (regardless of
the clock source), and the low-power mode currently in use. These states can always be read by a debug
tool, even when the microcontroller sleeps in LPMx.5 modes.
The activity of the following modules can be observed:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MPY is calculating.
WDT is counting.
RTC is counting.
ADC: a sequence, sample, or conversion is active.
REF: REFBG or REFGEN active and BG in static mode.
COMP is on.
AES is encrypting or decrypting.
eUSCI_A0 is transferring (receiving or transmitting) data.
eUSCI_A1 is transferring (receiving or transmitting) data.
eUSCI_B0 is transferring (receiving or transmitting) data.
TB0 is counting.
TA0 is counting.
TA1 is counting.
TA2 is counting.
TA3 is counting.
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5.10.20 Peripheral File Map
表 5-20 lists the base address for each peripheral. For complete module register descriptions, see the
MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide.
表 5-20. Peripherals
OFFSET ADDRESS
MODULE NAME
BASE ADDRESS
RANGE
Special Functions (see 表 5-21)
PMM (see 表 5-22)
0100h
0120h
0140h
0150h
015Ch
0160h
0180h
01B0h
0200h
0220h
0320h
0340h
0380h
03C0h
0400h
0440h
04A0h
04C0h
0500h
0510h
0520h
0530h
05A0h
05C0h
05E0h
0640h
0800h
08C0h
09C0h
000h–01Fh
000h–01Fh
000h–00Fh
000h–007h
000h–001h
000h–00Fh
000h–01Fh
000h–001h
000h–01Fh
000h–01Fh
000h–01Fh
000h–02Fh
000h–02Fh
000h–02Fh
000h–02Fh
000h–02Fh
000h–01Fh
000h–02Fh
000h–00Fh
000h–00Fh
000h–00Fh
000h–00Fh
000h–00Fh
000h–01Fh
000h–01Fh
000h–02Fh
000h–09Fh
000h–00Fh
000h–00Fh
FRAM Control (see 表 5-23)
CRC16 (see 表 5-24)
Watchdog (see 表 5-25)
CS (see 表 5-26)
SYS (see 表 5-27)
Shared Reference (see 表 5-28)
Port P1, P2 (see 表 5-29)
Port P3, P4 (see 表 5-30)
Port PJ (see 表 5-31)
TA0 (see 表 5-32)
TA1 (see 表 5-33)
TB0 (see 表 5-34)
TA2 (see 表 5-35)
TA3 (see 表 5-36)
Real-Time Clock (RTC_B) (see 表 5-37)
32-Bit Hardware Multiplier (see 表 5-38)
DMA General Control (see 表 5-39)
DMA Channel 0 (see 表 5-39)
DMA Channel 1 (see 表 5-39)
DMA Channel 2 (see 表 5-39)
MPU Control (see 表 5-40)
eUSCI_A0 (see 表 5-41)
eUSCI_A1 (see 表 5-42)
eUSCI_B0 (see 表 5-43)
ADC12_B (see 表 5-44)
Comparator_E (see 表 5-45)
AES (see 表 5-46)
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表 5-21. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
SFRIE1
OFFSET
OFFSET
OFFSET
OFFSET
SFR interrupt enable
SFR interrupt flag
00h
02h
04h
SFRIFG1
SFR reset pin control
SFRRPCR
表 5-22. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
PMM control 0
PMM interrupt flags
PM5 control 0
PMMCTL0
PMMIFG
00h
0Ah
10h
PM5CTL0
表 5-23. FRAM Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
FRCTL0
FRAM control 0
General control 0
General control 1
00h
04h
06h
GCCTL0
GCCTL1
表 5-24. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
CRC16DI
CRC data input
00h
02h
04h
06h
CRC data input reverse byte
CRC initialization and result
CRC result reverse byte
CRCDIRB
CRCINIRES
CRCRESR
表 5-25. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
REGISTER
WDTCTL
OFFSET
OFFSET
Watchdog timer control
00h
表 5-26. CS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
CS control 0
CS control 1
CS control 2
CS control 3
CS control 4
CS control 5
CS control 6
CSCTL0
CSCTL1
CSCTL2
CSCTL3
CSCTL4
CSCTL5
CSCTL6
00h
02h
04h
06h
08h
0Ah
0Ch
表 5-27. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
06h
08h
0Ah
0Ch
0Eh
JTAG mailbox control
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
JTAG mailbox output 1
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
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表 5-27. SYS Registers (Base Address: 0180h) (continued)
REGISTER DESCRIPTION
REGISTER
SYSUNIV
OFFSET
User NMI vector generator
1Ah
1Ch
1Eh
System NMI vector generator
Reset vector generator
SYSSNIV
SYSRSTIV
表 5-28. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
REGISTER
REFCTL
OFFSET
OFFSET
Shared reference control
00h
表 5-29. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
Port P1 input
P1IN
00h
02h
04h
06h
0Ah
0Ch
0Eh
16h
18h
1Ah
1Ch
01h
03h
05h
07h
0Bh
0Dh
17h
1Eh
19h
1Bh
1Dh
Port P1 output
P1OUT
P1DIR
P1REN
Port P1 direction
Port P1 resistor enable
Port P1 selection 0
Port P1 selection 1
Port P1 interrupt vector word
P1SEL0
P1SEL1
P1IV
Port P1 complement selection
Port P1 interrupt edge select
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
P1SELC
P1IES
P1IE
P1IFG
P2IN
Port P2 output
P2OUT
P2DIR
P2REN
P2SEL0
P2SEL1
P2SELC
P2IV
Port P2 direction
Port P2 resistor enable
Port P2 selection 0
Port P2 selection 1
Port P2 complement selection
Port P2 interrupt vector word
Port P2 interrupt edge select
Port P2 interrupt enable
Port P2 interrupt flag
P2IES
P2IE
P2IFG
表 5-30. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
02h
04h
06h
0Ah
0Ch
0Eh
16h
18h
1Ah
1Ch
Port P3 output
P3OUT
P3DIR
P3REN
Port P3 direction
Port P3 resistor enable
Port P3 selection 0
P3SEL0
P3SEL1
P3IV
Port P3 selection 1
Port P3 interrupt vector word
Port P3 complement selection
Port P3 interrupt edge select
Port P3 interrupt enable
Port P3 interrupt flag
P3SELC
P3IES
P3IE
P3IFG
68
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表 5-30. Port P3, P4 Registers (Base Address: 0220h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P4 input
P4IN
01h
03h
05h
07h
0Bh
0Dh
17h
1Eh
19h
1Bh
1Dh
Port P4 output
P4OUT
P4DIR
P4REN
Port P4 direction
Port P4 resistor enable
Port P4 selection 0
Port P4 selection 1
P4SEL0
P4SEL1
P4SELC
P4IV
Port P4 complement selection
Port P4 interrupt vector word
Port P4 interrupt edge select
Port P4 interrupt enable
P4IES
P4IE
Port P4 interrupt flag
P4IFG
表 5-31. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
02h
04h
06h
0Ah
0Ch
16h
Port PJ output
PJOUT
PJDIR
PJREN
Port PJ direction
Port PJ resistor enable
Port PJ selection 0
Port PJ selection 1
Port PJ complement selection
PJSEL0
PJSEL1
PJSELC
表 5-32. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA0 control
TA0CTL
00h
02h
04h
06h
08h
0Ah
10h
12h
14h
16h
18h
1Ah
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
Capture/compare control 3
Capture/compare control 4
TA0 counter
TA0CCTL0
TA0CCTL1
TA0CCTL2
TA0CCTL3
TA0CCTL4
TA0R
Capture/compare 0
Capture/compare 1
Capture/compare 2
Capture/compare 3
Capture/compare 4
TA0 expansion 0
TA0CCR0
TA0CCR1
TA0CCR2
TA0CCR3
TA0CCR4
TA0EX0
TA0 interrupt vector
TA0IV
表 5-33. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA1 control
TA1CTL
00h
02h
04h
06h
10h
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA1 counter
TA1CCTL0
TA1CCTL1
TA1CCTL2
TA1R
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表 5-33. TA1 Registers (Base Address: 0380h) (continued)
REGISTER DESCRIPTION
REGISTER
TA1CCR0
OFFSET
Capture/compare 0
Capture/compare 1
Capture/compare 2
TA1 expansion 0
12h
14h
16h
20h
2Eh
TA1CCR1
TA1CCR2
TA1EX0
TA1IV
TA1 interrupt vector
表 5-34. TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TB0 control
TB0CTL
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
Capture/compare control 3
Capture/compare control 4
Capture/compare control 5
Capture/compare control 6
TB0 counter
TB0CCTL0
TB0CCTL1
TB0CCTL2
TB0CCTL3
TB0CCTL4
TB0CCTL5
TB0CCTL6
TB0R
Capture/compare 0
TB0CCR0
TB0CCR1
TB0CCR2
TB0CCR3
TB0CCR4
TB0CCR5
TB0CCR6
TB0EX0
Capture/compare 1
Capture/compare 2
Capture/compare 3
Capture/compare 4
Capture/compare 5
Capture/compare 6
TB0 expansion 0
TB0 interrupt vector
TB0IV
表 5-35. TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA2 control
TA2CTL
TA2CCTL0
TA2CCTL1
TA2R
00h
02h
04h
10h
12h
14h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
TA2 counter
Capture/compare 0
Capture/compare 1
TA2 expansion 0
TA2CCR0
TA2CCR1
TA2EX0
TA2IV
TA2 interrupt vector
表 5-36. TA3 Registers (Base Address: 0440h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA3 control
TA3CTL
00h
02h
04h
10h
12h
14h
Capture/compare control 0
Capture/compare control 1
TA3 counter
TA3CCTL0
TA3CCTL1
TA3R
Capture/compare 0
Capture/compare 1
TA3CCR0
TA3CCR1
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表 5-36. TA3 Registers (Base Address: 0440h) (continued)
REGISTER DESCRIPTION
REGISTER
TA3EX0
TA3IV
OFFSET
OFFSET
TA3 expansion 0
20h
2Eh
TA3 interrupt vector
表 5-37. RTC_B Real-Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
RTCCTL0
RTC control 0
00h
01h
02h
03h
08h
0Ah
0Ch
0Dh
0Eh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Eh
RTC control 1
RTCCTL1
RTC control 2
RTCCTL2
RTC control 3
RTCCTL3
RTC prescaler 0 control
RTC prescaler 1 control
RTC prescaler 0
RTC prescaler 1
RTC interrupt vector word
RTC seconds
RTCPS0CTL
RTCPS1CTL
RTCPS0
RTCPS1
RTCIV
RTCSEC/RTCNT1
RTCMIN/RTCNT2
RTCHOUR/RTCNT3
RTCDOW/RTCNT4
RTCDAY
RTC minutes
RTC hours
RTC day of week
RTC days
RTC month
RTCMON
RTC year low
RTCYEARL
RTCYEARH
RTCAMIN
RTC year high
RTC alarm minutes
RTC alarm hours
RTC alarm day of week
RTC alarm days
Binary-to-BCD conversion
BCD-to-binary conversion
RTCAHOUR
RTCADOW
RTCADAY
BIN2BCD
BCD2BIN
表 5-38. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
16-bit operand 1 – signed multiply
MPYS
MAC
16-bit operand 1 – multiply accumulate
16-bit operand 1 – signed multiply accumulate
16-bit operand 2
MACS
OP2
16 × 16 result low word
RESLO
RESHI
16 × 16 result high word
16 × 16 sum extension
SUMEXT
MPY32L
32-bit operand 1 – multiply low word
32-bit operand 1 – multiply high word
32-bit operand 1 – signed multiply low word
32-bit operand 1 – signed multiply high word
32-bit operand 1 – multiply accumulate low word
32-bit operand 1 – multiply accumulate high word
32-bit operand 1 – signed multiply accumulate low word
32-bit operand 1 – signed multiply accumulate high word
MPY32H
MPYS32L
MPYS32H
MAC32L
MAC32H
MACS32L
MACS32H
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表 5-38. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
32-bit operand 2 – low word
32-bit operand 2 – high word
OP2L
OP2H
RES0
RES1
RES2
RES3
20h
22h
24h
26h
28h
2Ah
2Ch
32 × 32 result 0 – least significant word
32 × 32 result 1
32 × 32 result 2
32 × 32 result 3 – most significant word
MPY32 control 0
MPY32CTL0
表 5-39. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)
REGISTER DESCRIPTION
REGISTER
DMA0CTL
OFFSET
DMA channel 0 control
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Eh
DMA channel 0 source address low
DMA channel 0 source address high
DMA channel 0 destination address low
DMA channel 0 destination address high
DMA channel 0 transfer size
DMA0SAL
DMA0SAH
DMA0DAL
DMA0DAH
DMA0SZ
DMA channel 1 control
DMA1CTL
DMA1SAL
DMA1SAH
DMA1DAL
DMA1DAH
DMA1SZ
DMA channel 1 source address low
DMA channel 1 source address high
DMA channel 1 destination address low
DMA channel 1 destination address high
DMA channel 1 transfer size
DMA channel 2 control
DMA2CTL
DMA2SAL
DMA2SAH
DMA2DAL
DMA2DAH
DMA2SZ
DMA channel 2 source address low
DMA channel 2 source address high
DMA channel 2 destination address low
DMA channel 2 destination address high
DMA channel 2 transfer size
DMA module control 0
DMACTL0
DMACTL1
DMACTL2
DMACTL3
DMACTL4
DMAIV
DMA module control 1
DMA module control 2
DMA module control 3
DMA module control 4
DMA interrupt vector
表 5-40. MPU Control Registers (Base Address: 05A0h)
REGISTER DESCRIPTION
REGISTER
MPUCTL0
OFFSET
MPU control 0
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
MPU control 1
MPUCTL1
MPU segmentation border 2
MPU segmentation border 1
MPU access management
MPU IP control 0
MPUSEGB2
MPUSEGB1
MPUSAM
MPUIPC0
MPU IP encapsulation segment border 2
MPU IP encapsulation segment border 1
MPUIPSEGB2
MPUIPSEGB1
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表 5-41. eUSCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
OFFSET
OFFSET
eUSCI_A control word 0
eUSCI _A control word 1
eUSCI_A baud rate 0
UCA0CTLW0
UCA0CTLW1
UCA0BR0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ah
1Ch
1Eh
eUSCI_A baud rate 1
UCA0BR1
eUSCI_A modulation control
eUSCI_A status word
UCA0MCTLW
UCA0STATW
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL
UCA0IRTCTL
UCA0IRRCTL
UCA0IE
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
UCA0IFG
UCA0IV
表 5-42. eUSCI_A1 Registers (Base Address:05E0h)
REGISTER DESCRIPTION
REGISTER
UCA1CTLW0
eUSCI_A control word 0
eUSCI _A control word 1
eUSCI_A baud rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ah
1Ch
1Eh
UCA1CTLW1
UCA1BR0
eUSCI_A baud rate 1
UCA1BR1
eUSCI_A modulation control
eUSCI_A status word
UCA1MCTLW
UCA1STATW
UCA1RXBUF
UCA1TXBUF
UCA1ABCTL
UCA1IRTCTL
UCA1IRRCTL
UCA1IE
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
UCA1IFG
UCA1IV
表 5-43. eUSCI_B0 Registers (Base Address: 0640h)
REGISTER DESCRIPTION
REGISTER
UCB0CTLW0
eUSCI_B control word 0
eUSCI_B control word 1
eUSCI_B bit rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
14h
16h
18h
1Ah
1Ch
UCB0CTLW1
UCB0BR0
eUSCI_B bit rate 1
UCB0BR1
eUSCI_B status word
UCB0STATW
UCB0TBCNT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA0
UCB0I2COA1
UCB0I2COA2
UCB0I2COA3
UCB0ADDRX
eUSCI_B byte counter threshold
eUSCI_B receive buffer
eUSCI_B transmit buffer
eUSCI_B I2C own address 0
eUSCI_B I2C own address 1
eUSCI_B I2C own address 2
eUSCI_B I2C own address 3
eUSCI_B received address
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表 5-43. eUSCI_B0 Registers (Base Address: 0640h) (continued)
REGISTER DESCRIPTION
REGISTER
UCB0ADDMASK
UCB0I2CSA
UCB0IE
OFFSET
eUSCI_B address mask
eUSCI I2C slave address
eUSCI interrupt enable
eUSCI interrupt flags
1Eh
20h
2Ah
2Ch
2Eh
UCB0IFG
eUSCI interrupt vector word
UCB0IV
表 5-44. ADC12_B Registers (Base Address: 0800h)
REGISTER DESCRIPTION
REGISTER
ADC12CTL0
OFFSET
ADC12_B control 0
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
36h
38h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
4Eh
50h
52h
ADC12_B control 1
ADC12CTL1
ADC12_B control 2
ADC12CTL2
ADC12_B control 3
ADC12CTL3
ADC12_B window comparator low threshold
ADC12_B window comparator high threshold
ADC12_B interrupt flag 0
ADC12LO
ADC12HI
ADC12IFGR0
ADC12IFGR1
ADC12IFGR2
ADC12IER0
ADC12_B interrupt flag 1
ADC12_B interrupt flag 2
ADC12_B interrupt enable 0
ADC12_B interrupt enable 1
ADC12_B interrupt enable 2
ADC12_B interrupt vector
ADC12IER1
ADC12IER2
ADC12IV
ADC12_B memory control 0
ADC12_B memory control 1
ADC12_B memory control 2
ADC12_B memory control 3
ADC12_B memory control 4
ADC12_B memory control 5
ADC12_B memory control 6
ADC12_B memory control 7
ADC12_B memory control 8
ADC12_B memory control 9
ADC12_B memory control 10
ADC12_B memory control 11
ADC12_B memory control 12
ADC12_B memory control 13
ADC12_B memory control 14
ADC12_B memory control 15
ADC12_B memory control 16
ADC12_B memory control 17
ADC12_B memory control 18
ADC12_B memory control 19
ADC12_B memory control 20
ADC12_B memory control 21
ADC12_B memory control 22
ADC12_B memory control 23
ADC12_B memory control 24
ADC12_B memory control 25
ADC12MCTL0
ADC12MCTL1
ADC12MCTL2
ADC12MCTL3
ADC12MCTL4
ADC12MCTL5
ADC12MCTL6
ADC12MCTL7
ADC12MCTL8
ADC12MCTL9
ADC12MCTL10
ADC12MCTL11
ADC12MCTL12
ADC12MCTL13
ADC12MCTL14
ADC12MCTL15
ADC12MCTL16
ADC12MCTL17
ADC12MCTL18
ADC12MCTL19
ADC12MCTL20
ADC12MCTL21
ADC12MCTL22
ADC12MCTL23
ADC12MCTL24
ADC12MCTL25
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表 5-44. ADC12_B Registers (Base Address: 0800h) (continued)
REGISTER DESCRIPTION
REGISTER
ADC12MCTL26
OFFSET
ADC12_B memory control 26
ADC12_B memory control 27
ADC12_B memory control 28
ADC12_B memory control 29
ADC12_B memory control 30
ADC12_B memory control 31
ADC12_B memory 0
54h
56h
58h
5Ah
5Ch
5Eh
60h
62h
64h
66h
68h
6Ah
6Ch
6Eh
70h
72h
74h
76h
78h
7Ah
7Ch
7Eh
80h
82h
84h
86h
88h
8Ah
8Ch
8Eh
90h
92h
94h
96h
98h
9Ah
9Ch
9Eh
ADC12MCTL27
ADC12MCTL28
ADC12MCTL29
ADC12MCTL30
ADC12MCTL31
ADC12MEM0
ADC12MEM1
ADC12MEM2
ADC12MEM3
ADC12MEM4
ADC12MEM5
ADC12MEM6
ADC12MEM7
ADC12MEM8
ADC12MEM9
ADC12MEM10
ADC12MEM11
ADC12MEM12
ADC12MEM13
ADC12MEM14
ADC12MEM15
ADC12MEM16
ADC12MEM17
ADC12MEM18
ADC12MEM19
ADC12MEM20
ADC12MEM21
ADC12MEM22
ADC12MEM23
ADC12MEM24
ADC12MEM25
ADC12MEM26
ADC12MEM27
ADC12MEM28
ADC12MEM29
ADC12MEM30
ADC12MEM31
ADC12_B memory 1
ADC12_B memory 2
ADC12_B memory 3
ADC12_B memory 4
ADC12_B memory 5
ADC12_B memory 6
ADC12_B memory 7
ADC12_B memory 8
ADC12_B memory 9
ADC12_B memory 10
ADC12_B memory 11
ADC12_B memory 12
ADC12_B memory 13
ADC12_B memory 14
ADC12_B memory 15
ADC12_B memory 16
ADC12_B memory 17
ADC12_B memory 18
ADC12_B memory 19
ADC12_B memory 20
ADC12_B memory 21
ADC12_B memory 22
ADC12_B memory 23
ADC12_B memory 24
ADC12_B memory 25
ADC12_B memory 26
ADC12_B memory 27
ADC12_B memory 28
ADC12_B memory 29
ADC12_B memory 30
ADC12_B memory 31
表 5-45. Comparator_E Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
REGISTER
CECTL0
OFFSET
Comparator_E control 0
Comparator_E control 1
Comparator_E control 2
Comparator_E control 3
Comparator_E interrupt
Comparator_E interrupt vector word
00h
02h
04h
06h
0Ch
0Eh
CECTL1
CECTL2
CECTL3
CEINT
CEIV
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表 5-46. AES Accelerator Registers (Base Address: 09C0h)
REGISTER DESCRIPTION
REGISTER
AESACTL0
OFFSET
AES accelerator control 0
AES accelerator control 1
AES accelerator status
AES accelerator key
00h
AESACTL1
AESASTAT
AESAKEY
AESADIN
02h
04h
06h
AES accelerator data in
AES accelerator data out
008h
00Ah
00Ch
00Eh
AESADOUT
AESAXDIN
AESAXIN
AES accelerator XORed data in
AES accelerator XORed data in (no trigger)
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ZHCSH89A –DECEMBER 2017–REVISED MARCH 2018
5.11 Input and Output Diagrams
5.11.1 Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
图 5-2 shows the port diagram. 表 5-47 summarizes the selection of the pin function.
Pad Logic
(ADC) Reference
(P1.0, P1.1)
To ADC
From ADC
To Comparator
From Comparator
CEPDx
P1REN.x
0 0
0 1
1 0
1 1
P1DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P1OUT.x
From module 1
From module 2
DVSS
P1.0/TA0.1/DMAE0/RTCCLK/
A0/C0/VREF-/VeREF-
P1.1/TA0.2/TA1CLK/COUT/
A1/C1VREF+/VeREF+
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P1SEL1.x
P1SEL0.x
P1IN.x
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 5-2. Port P1 (P1.0 to P1.2) Diagram
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表 5-47. Port P1 (P1.0 to P1.2) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
P1.0 (I/O)
TA0.CCI1A
TA0.1
I: 0; O: 1
0
0
0
0
1
1
0
1
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/
VREF-/VeREF-
0
DMAE0
RTCCLK(2)(3)
0
1
A0, C0, VREF-, VeREF-(4)(5)
X
1
0
1
0
P1.1 (I/O)
I: 0; O: 1
TA0.CCI2A
TA0.2
0
0
1
1
0
1
P1.1/TA0.2/TA1CLK/COUT/A1/C1/
VREF+/VeREF+
1
2
TA1CLK
COUT(6)
A1, C1, VREF+, VeREF+(4)(5)
0
1
X
1
0
1
0
P1.2 (I/O)
I: 0; O: 1
TA1.CCI1A
TA1.1
0
1
0
1
X
0
1
P1.2/TA1.1/TA0CLK/COUT/A2/C2
(1) X = Don't care
TA0CLK
COUT(7)
A2, C2(4)(5)
1
1
0
1
(2) Not available on MSP430FR5x5x devices
(3) Do not use this pin as RTCCLK output if the DMAE0 functionality is used on any other pin. Select an alternative RTCCLK output pin.
(4) Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
(5) Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module
automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.
(6) Do not use this pin as COUT output if the TA1CLK functionality is used on any other pin. Select an alternative COUT output pin.
(7) Do not use this pin as COUT output if the TA0CLK functionality is used on any other pin. Select an alternative COUT output pin.
78
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5.11.2 Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
图 5-3 shows the port diagram. 表 5-48 summarizes the selection of the pin function.
Pad Logic
To ADC
From ADC
To Comparator
From Comparator
CEPDx
P1REN.x
0 0
0 1
1 0
1 1
P1DIR.x
DVSS
DVCC
0
1
From module 2
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P1OUT.x
From module 1
From module 2
DVSS
P1.3/TA1.2/UCB0STE/A3/C3
P1.4/TB0.1/UCA0STE/A4/C4
P1.5/TB0.2/UCA0CLK/A5/C5
P1SEL1.x
P1SEL0.x
P1IN.x
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 5-3. Port P1 (P1.3 to P1.5) Diagram
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表 5-48. Port P1 (P1.3 to P1.5) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
P1.3 (I/O)
TA1.CCI2A
TA1.2
I: 0; O: 1
0
0
0
0
1
P1.3/TA1.2/UCB0STE/A3/C3
3
1
UCB0STE
A3, C3(3)(4)
P1.4 (I/O)
TB0.CCI1A
TB0.1
X(2)
1
1
0
0
1
0
X
I: 0; O: 1
0
0
1
P1.4/TB0.1/UCA0STE/A4/C4
4
5
1
X(5)
UCA0STE
A4, C4(3)(4)
P1.5(I/O)
TB0.CCI2A
TB0.2
1
1
0
0
1
0
X
I: 0; O: 1
0
0
1
P1.5/TB0.2/UCA0CLK/A5/C5
(1) X = Don't care
1
UCA0CLK
A5, C5(3)(4)
X(5)
X
1
1
0
1
(2) Direction controlled by eUSCI_B0 module.
(3) Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
(4) Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module
automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.
(5) Direction controlled by eUSCI_A0 module.
80
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5.11.3 Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
图 5-4 shows the port diagram. 表 5-49 summarizes the selection of the pin function.
Pad Logic
P1REN.x
0 0
0 1
1 0
1 1
P1DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
From module 2
1
0 0
0 1
1 0
1 1
P1OUT.x
From module 1
From module 2
From module 3
P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
P1SEL1.x
P1SEL0.x
P1IN.x
EN
D
To modules
NOTE: Functional representation only.
图 5-4. Port P1 (P1.6 and P1.7) Diagram
表 5-49. Port P1 (P1.6 and P1.7) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
P1.6 (I/O)
TB0.CCI3B
TB0.3
I: 0; O: 1
0
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1
X(2)
P1.6/TB0.3/UCB0SIMO/UCB0SDA/ TA0.0
6
UCB0SIMO/UCB0SDA
TA0.CCI0A
TA0.0
0
1
P1.7 (I/O)
I: 0; O: 1
TB0.CCI4B
TB0.4
0
1
X(3)
P1.7/TB0.4/UCB0SOMI/UCB0SCL/ TA1.0
(1) X = Don't care
7
UCB0SOMI/UCB0SCL
TA1.CCI0A
TA1.0
0
1
(2) Direction controlled by eUSCI_B0 module.
(3) Direction controlled by eUSCI_A0 module.
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5.11.4 Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
图 5-5 shows the port diagram. 表 5-50 summarizes the selection of the pin function.
Pad Logic
P2REN.x
0 0
0 1
1 0
1 1
P2DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
From module 2
1
0 0
0 1
1 0
1 1
P2OUT.x
From module 1
From module 2
From module 3
P2.0/TB0.6/UCA0TXD/UCA0SIMO/
TB0CLK/ACLK
P2.1/TB0.0/UCA0RXD/UCA0SOMI/
TB0.0
P2.2/TB0.2/UCB0CLK
P2SEL1.x
P2SEL0.x
P2IN.x
EN
D
To modules
NOTE: Functional representation only.
图 5-5. Port P2 (P2.0 to P2.2) Diagram
表 5-50. Port P2 (P2.0 to P2.2) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL1.x
P2SEL0.x
P2.0 (I/O)
TB0.CCI6B
TB0.6
I: 0; O: 1
0
0
0
0
1
1
0
X
1
1
0
1
0
1
0
1
X(2)
P2.0/TB0.6/UCA0TXD/UCA0SIMO/
TB0CLK/ACLK
0
UCA0TXD/UCA0SIMO
TB0CLK
ACLK(3)
0
1
P2.1 (I/O)
I: 0; O: 1
TB0.CCI0A
0
1
X(2)
P2.1/TB0.0/UCA0RXD/UCA0SOMI/
TB0.0
1
TB0.0
UCA0RXD/UCA0SOMI
(1) X = Don't care
(2) Direction controlled by eUSCI_A0 module.
(3) Do not use this pin as ACLK output if the TB0CLK functionality is used on any other pin. Select an alternative ACLK output pin.
82 Detailed Description
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表 5-50. Port P2 (P2.0 to P2.2) Pin Functions (continued)
CONTROL BITS AND SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL1.x
P2SEL0.x
P2.2 (I/O)
N/A
I: 0; O: 1
0
0
1
0
1
0
0
1
1
TB0.2
1
P2.2/TB0.2/UCB0CLK
2
(4)
UCB0CLK
N/A
X
0
1
Internally tied to DVSS
(4) Direction controlled by eUSCI_B0 module.
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5.11.5 Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
Pad Logic
To ADC
From ADC
To Comparator
From Comparator
CEPDx
P2REN.x
0 0
0 1
1 0
1 1
P2DIR.x
DVSS
DVCC
0
1
From module 2
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P2OUT.x
From module 1
From module 2
DVSS
P2.3/TA0.0/UCA1STE/A6/C10
P2.4/TA1.0/UCA1CLK/A7/C11
P2SEL1.x
P2SEL0.x
P2IN.x
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 5-6. Port P2 (P2.3 and P2.4) Diagram
84
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表 5-51. Port P2 (P2.3 and P2.4) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL1.x
P2SEL0.x
P2.3 (I/O)
TA0.CCI0B
TA0.0
I: 0; O: 1
0
0
0
0
1
P2.3/TA0.0/UCA1STE/A6/C10
3
1
(2)
UCA1STE
A6, C10(3)(4)
P2.4 (I/O)
TA1.CCI0B
TA1.0
X
1
1
0
0
1
0
X
I: 0; O: 1
0
0
1
P2.4/TA1.0/UCA1CLK/A7/C11
(1) X = Don't care
4
1
(2)
UCA1CLK
A7, C11(3)(4)
X
1
1
0
1
X
(2) Direction controlled by eUSCI_A1 module.
(3) Setting P2SEL1.x and P2SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
(4) Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module
automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.
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5.11.6 Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
图 5-7 shows the port diagram. 表 5-52 summarizes the selection of the pin function.
Pad Logic
P2REN.x
0 0
0 1
1 0
1 1
P2DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
From module 2
1
0 0
0 1
1 0
1 1
P2OUT.x
From module 1
From module 2
DVSS
P2.5/TB0.0/UCA1TXD/UCA1SIMO
P2.6/TB0.1/UCA1RXD/UCA1SOMI
P2SEL1.x
P2SEL0.x
P2IN.x
EN
D
To modules
NOTE: Functional representation only.
图 5-7. Port P2 (P2.5 and P2.6) Diagram
表 5-52. Port P2 (P2.5 and P2.6) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL1.x
P2SEL0.x
P2.5(I/O)
TB0.CCI0B
TB0.0
I: 0; O: 1
0
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1
X(2)
P2.5/TB0.0/UCA1TXD/UCA1SIMO
5
UCA1TXD/UCA1SIMO
N/A
0
Internally tied to DVSS
1
P2.6(I/O)
I: 0; O: 1
N/A
0
1
X(2)
TB0.1
P2.6/TB0.1/UCA1RXD/UCA1SOMI
(1) X = Don't care
6
UCA1RXD/UCA1SOMI
N/A
0
Internally tied to DVSS
1
(2) Direction controlled by eUSCI_A1 module.
86
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5.11.7 Port P2 (P2.7) Input/Output With Schmitt Trigger
图 5-8 shows the port diagram. 表 5-53 summarizes the selection of the pin function.
Pad Logic
P2REN.x
0 0
0 1
1 0
1 1
P2DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P2OUT.x
DVSS
DVSS
P2.7
DVSS
P2SEL1.x
P2SEL0.x
P2IN.x
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 5-8. Port P2 (P2.7) Diagram
表 5-53. Port P2 (P2.7) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL1.x
P2SEL0.x
P2.7(I/O)
N/A
I: 0; O: 1
0
0
0
1
0
1
0
1
1
P2.7
7
Internally tied to DVSS
N/A
X
Internally tied to DVSS
(1) X = Don't care
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5.11.8 Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
图 5-9 shows the port diagram. 表 5-54 summarizes the selection of the pin function.
Pad Logic
To ADC
From ADC
To Comparator
From Comparator
CEPDx
P3REN.x
0 0
0 1
1 0
1 1
P3DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P3OUT.x
DVSS
DVSS
DVSS
P3.0/A12/C12
P3.1/A13/C13
P3.2/A14/C14
P3.3/A15/C15
P3SEL1.x
P3SEL0.x
P3IN.x
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 5-9. Port P3 (P3.0 to P3.3) Diagram
88
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表 5-54. Port P3 (P3.0 to P3.3) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P3.x)
x
FUNCTION
P3DIR.x
P3SEL1.x
P3SEL0.x
P3.0 (I/O)
N/A
I: 0; O: 1
0
0
0
0
1
1
Internally tied to DVSS
N/A
1
P3.0/A12/C12
P3.1/A13/C13
P3.2/A14/C14
0
0
0
Internally tied to DVSS
A12/C12(2)(3)
P3.1 (I/O)
1
X
1
0
1
0
I: 0; O: 1
N/A
0
0
1
1
0
Internally tied to DVSS
N/A
1
1
2
3
0
Internally tied to DVSS
A13/C13(2)(3)
P3.2 (I/O)
1
X
1
0
1
0
I: 0; O: 1
N/A
0
0
1
1
0
Internally tied to DVSS
N/A
1
0
Internally tied to DVSS
A14/C14(2)(3)
P3.3 (I/O)
1
X
1
0
1
0
I: 0; O: 1
N/A
0
1
0
1
X
0
1
Internally tied to DVSS
N/A
P3.3/A15/C15
1
1
0
1
Internally tied to DVSS
A15/C15(2)(3)
(1) X = Don't care
(2) Setting P3SEL1.x and P3SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
(3) Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module
automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.
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5.11.9 Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger
图 5-10 shows the port diagram. 表 5-55 summarizes the selection of the pin function.
Pad Logic
P3REN.x
0 0
0 1
1 0
1 1
P3DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P3OUT.x
From module 1
From module 2
From module 3
P3.4/TB0.3/SMCLK
P3.5/TB0.4/CBOUT
P3.6/TB0.5
P3.7/TB0.6
P3SEL1.x
P3SEL0.x
P3IN.x
EN
D
To modules
NOTE: Functional representation only.
图 5-10. Port P3 (P3.4 to P3.7) Diagram
90
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表 5-55. Port P3 (P3.4 to P3.7) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P3.x)
x
FUNCTION
P3DIR.x
P3SEL1.x
P3SEL0.x
P3.4 (I/O)
TB0.CCI3A
TB0.3
I: 0; O: 1
0
0
0
0
1
P3.4/TB0.3/SMCLK
P3.5/TB0.4/COUT
P3.6/TB0.5
4
1
N/A
0
1
0
0
X
0
1
SMCLK
P3.5 (I/O)
TB0.CCI4A
TB0.4
1
I: 0; O: 1
0
5
6
7
1
N/A
0
1
0
0
X
0
1
COUT
1
P3.6 (I/O)
TB0.CCI5A
TB0.5
I: 0; O: 1
0
1
N/A
0
1
0
0
X
0
1
Internally tied to DVSS
P3.7 (I/O)
1
I: 0; O: 1
TB0.CCI6A
0
1
0
1
P3.7/TB0.6
TB0.6
N/A
1
X
Internally tied to DVSS
(1) X = Don't care
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5.11.10 Port P4 (P4.0 to P4.3) Input/Output With Schmitt Trigger
图 5-11 shows the port diagram. 表 5-56 summarizes the selection of the pin function.
Pad Logic
To ADC
From ADC
P4REN.x
0 0
0 1
1 0
1 1
P4DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P4OUT.x
DVSS
DVSS
P4.0/A8
P4.1/A9
P4.2/A10
P4.3/A11
DVSS
P4SEL1.x
P4SEL0.x
P4IN.x
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 5-11. Port P4 (P4.0 to P4.3) Diagram
92
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表 5-56. Port P4 (P4.0 to P4.3) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x
P4SEL1.x
P4SEL0.x
P4.0 (I/O)
N/A
I: 0; O: 1
0
0
0
0
1
1
Internally tied to DVSS
1
P4.0/A8
P4.1/A9
P4.2/A10
0
N/A
0
0
Internally tied to DVSS
1
A8(2)
X
1
0
1
0
P4.1 (I/O)
I: 0; O: 1
N/A
0
0
1
1
0
Internally tied to DVSS
1
1
2
3
N/A
0
Internally tied to DVSS
A9(2)
1
X
1
0
1
0
P4.2 (I/O)
I: 0; O: 1
N/A
0
0
1
1
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
A10(2)
1
X
1
0
1
0
P4.3 (I/O)
I: 0; O: 1
N/A
0
1
0
1
X
0
1
Internally tied to DVSS
N/A
P4.3/A11
1
1
0
1
Internally tied to DVSS
A11(2)
(1) X = Don't care
(2) Setting P4SEL1.x and P4SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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5.11.11 Port P4 (P4.4 to P4.7) Input/Output With Schmitt Trigger
图 5-12 shows the port diagram. 表 5-57 summarizes the selection of the pin function.
Pad Logic
P4REN.x
0 0
0 1
1 0
1 1
P4DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P4OUT.x
From module 1
DVSS
DVSS
P4.4/TB0.5
P4.5
P4.6
P4SEL1.x
P4.7
P4SEL0.x
P4IN.x
EN
D
To modules
NOTE: Functional representation only.
图 5-12. Port P4 (P4.4 to P4.7) Diagram
94
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表 5-57. Port P4 (P4.4 to P4.7) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x
P4SEL1.x
P4SEL0.x
P4.4 (I/O)
TB0.CCI5B
TB0.5
I: 0; O: 1
0
0
0
0
1
P4.4/TB0.5
4
1
N/A
0
1
0
0
X
0
1
Internally tied to DVSS
1
P4.5 (I/O)
I: 0; O: 1
N/A
0
P4.5
5
6
7
Internally tied to DVSS
1
N/A
0
1
0
0
X
0
1
Internally tied to DVSS
P4.6 (I/O)
1
I: 0; O: 1
N/A
0
P4.6
Internally tied to DVSS
N/A
1
0
1
0
0
X
0
1
Internally tied to DVSS
P4.7 (I/O)
1
I: 0; O: 1
N/A
0
1
0
1
P4.7
Internally tied to DVSS
N/A
1
X
Internally tied to DVSS
(1) X = Don't care
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5.11.12 Port PJ, PJ.4 and PJ.5 Input/Output With Schmitt Trigger
图 5-13 and 图 5-14 show the port diagrams. 表 5-58 summarizes the selection of the pin function.
Pad Logic
To LFXT XIN
PJREN.4
0 0
0 1
1 0
1 1
PJDIR.4
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
PJOUT.4
DVSS
DVSS
DVSS
PJ.4/LFXIN
PJSEL1.4
PJSEL0.4
PJIN.4
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 5-13. Port PJ (PJ.4) Diagram
96
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Pad Logic
To LFXT XOUT
PJSEL0.4
PJSEL1.4
LFXTBYPASS
PJREN.5
0 0
0 1
1 0
1 1
PJDIR.5
DVSS
DVCC
0
Direction
0: Input
1: Output
1
1
0 0
0 1
1 0
1 1
PJOUT.5
DVSS
DVSS
PJ.5/LFXOUT
DVSS
PJSEL1.5
PJSEL0.5
PJIN.5
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 5-14. Port PJ (PJ.5) Diagram
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表 5-58. Port PJ (PJ.4 and PJ.5) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (PJ.x)
x
FUNCTION
PJ.4 (I/O)
LFXT
BYPASS
PJDIR.x
PJSEL1.5
PJSEL0.5
PJSEL1.4
PJSEL0.4
I: 0; O: 1
X
X
0
0
X
N/A
0
1
X
X
1
X
X
PJ.4/LFXIN
4
Internally tied to DVSS
LFXIN crystal mode(2)
LFXIN bypass mode(2)
X
X
X
X
X
X
0
0
0
1
X
0
1
X
0
1
X
0
1
1
0
1
0
0
1(3)
0
PJ.5 (I/O)
N/A
I: 0; O: 1
0
0
X
X
0
0
see(4)
see(4)
X
X
0
PJ.5/LFXOUT
5
1(3)
0
Internally tied to DVSS
LFXOUT crystal mode(2)
1
see(4)
X
see(4)
X
X
X
1
1(3)
0
X
(1) X = Don't care
(2) If PJSEL1.4 = 0 and PJSEL0.4 = 1, the general-purpose I/O is disabled. When LFXTBYPASS = 0, PJ.4 and PJ.5 are configured for
crystal operation and PJSEL1.5 and PJSEL0.5 are don't care. When LFXTBYPASS = 1, PJ.4 is configured for bypass operation and
PJ.5 is configured as general-purpose I/O.
(3) When PJ.4 is configured in bypass mode, PJ.5 is configured as general-purpose I/O.
(4) If PJSEL0.5 = 1 or PJSEL1.5 = 1, the general-purpose I/O functionality is disabled. No input function is available. Configured as output,
the pin is actively pulled to zero.
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5.11.13 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
图 5-15 and 图 5-16 show the port diagrams. 表 5-59 summarizes the selection of the pin function.
Pad Logic
To HFXT XIN
PJREN.6
0 0
0 1
1 0
1 1
PJDIR.6
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
PJOUT.6
DVSS
DVSS
DVSS
PJ.6/HFXIN
PJSEL1.6
PJSEL0.6
PJIN.6
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 5-15. Port PJ (PJ.6) Diagram
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Pad Logic
To HFXT XOUT
PJSEL0.6
PJSEL1.6
HFXTBYPASS
PJREN.7
0 0
0 1
1 0
1 1
PJDIR.7
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
PJOUT.7
DVSS
DVSS
DVSS
PJ.7/HFXOUT
PJSEL1.7
PJSEL0.7
PJIN.7
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 5-16. Port PJ (PJ.7) Diagram
100
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表 5-59. Port PJ (PJ.6 and PJ.7) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (PJ.x)
x
FUNCTION
PJ.6 (I/O)
HFXT
BYPASS
PJDIR.x
PJSEL1.7
PJSEL0.7
PJSEL1.6
PJSEL0.6
I: 0; O: 1
X
X
0
0
X
N/A
0
1
X
X
1
X
X
PJ.6/HFXIN
6
Internally tied to DVSS
HFXIN crystal mode(2)
HFXIN bypass mode(2)
X
X
X
X
X
X
0
0
0
1
X
0
1
X
0
1
X
0
1
1
0
1
0
0
1(4)
0
PJ.7 (I/O)(3)
I: 0; O: 1
0
0
X
X
0
(3)
(3)
N/A
0
see
see
X
X
0
PJ.7/HFXOUT
7
1(4)
0
(3)
(3)
Internally tied to DVSS
HFXOUT crystal mode(2)
1
see
see
X
X
1
1(4)
0
X
X
X
(1) X = Don't care
(2) Setting PJSEL1.6 = 0 and PJSEL0.6 = 1 causes the general-purpose I/O to be disabled. When HFXTBYPASS = 0, PJ.6 and PJ.7 are
configured for crystal operation and PJSEL1.6 and PJSEL0.7 are do not care. When HFXTBYPASS = 1, PJ.6 is configured for bypass
operation, and PJ.7 is configured as general-purpose I/O.
(3) With PJSEL0.7 = 1 or PJSEL1.7 = 1 the general-purpose I/O functionality is disabled. No input function is available. When configured as
output, the pin is actively pulled to zero.
(4) When PJ.6 is configured in bypass mode, PJ.7 is configured as general-purpose I/O.
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5.11.14 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With
Schmitt Trigger
图 5-17 shows the port diagram. 表 5-60 summarizes the selection of the pin function.
To Comparator
From Comparator
Pad Logic
CEPDx
JTAG enable
From JTAG
From JTAG
PJREN.x
0 0
0 1
1 0
1 1
PJDIR.x
1
0
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
PJOUT.x
From module 1
1
0
From Status Register (SR)
DVSS
PJ.0/TDO/TB0OUTH/SMCLK/
SRSCG1/C6
PJ.1/TDI/TCLK/MCLK/
SRSCG0/C7
PJ.2/TMS/ACLK/
SROSCOFF/C8
PJ.3/TCK/
PJSEL1.x
PJSEL0.x
PJIN.x
Bus
Keeper
EN
D
SRCPUOFF/C9
To modules
and JTAG
NOTE: Functional representation only.
图 5-17. Port PJ (PJ.0 to PJ.3) Diagram
102
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表 5-60. Port PJ (PJ.0 to PJ.3) Pin Functions
CONTROL BITS/ SIGNALS(1)
PIN NAME (PJ.x)
x
FUNCTION
PJDIR.x
PJSEL1.x
PJSEL0.x
CEPDx (Cx)
PJ.0 (I/O)(2)
TDO(3)
I: 0; O: 1
0
0
0
0
X
X
X
TB0OUTH
SMCLK(4)
N/A
0
0
1
1
1
0
1
0
0
0
1
PJ.0/TDO/TB0OUTH/
SMCLK/SRSCG1/C6
0
0
CPU Status Register Bit SCG1
1
N/A
0
Internally tied to DVSS
1
C6(5)
PJ.1 (I/O)(2)
TDI/TCLK(3) (6)
X
X
0
X
0
1
0
0
I: 0; O: 1
X
X
X
N/A
0
0
1
1
1
0
1
0
0
0
MCLK
1
PJ.1/TDI/TCLK/MCLK/
SRSCG0/C7
1
2
3
N/A
0
CPU Status Register Bit SCG0
1
N/A
0
Internally tied to DVSS
1
C7(5)
PJ.2 (I/O)(2)
TMS(3) (6)
X
X
0
X
0
1
0
0
I: 0; O: 1
X
X
X
N/A
0
0
1
1
1
0
1
0
0
0
ACLK
1
PJ.2/TMS/ACLK/
SROSCOFF/C8
N/A
0
CPU Status Register Bit OSCOFF
1
N/A
0
Internally tied to DVSS
1
C8(5)
PJ.3 (I/O)(2)
TCK(3) (6)
X
X
0
X
0
1
0
0
I: 0; O: 1
X
0
1
0
1
0
1
X
X
X
N/A
0
1
1
0
0
0
Internally tied to DVSS
PJ.3/TCK/SRCPUOFF/C9
N/A
CPU Status Register Bit CPUOFF
N/A
1
1
0
1
Internally tied to DVSS
C9(5)
X
X
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module. JTAG mode selection is made via the SYS module or by the Spy-Bi-Wire four-wire
entry sequence. Neither PJSEL1.x and PJSEL0.x nor CEPDx bits have an effect in these cases.
(4) Do not use this pin as SMCLK output if the TB0OUTH functionality is used on any other pin. Select an alternative SMCLK output pin.
(5) Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module
automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.
(6) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.
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5.12 Device Descriptor (TLV)
表 5-61 lists the Device ID for the MSP430FR5969-SP device. 表 5-62 lists the contents of the device
descriptor tag-length-value (TLV) structure for MSP430FR5969-SP.
表 5-61. Device IDs
DEVICE ID
DEVICE
MSP430FR5969-SP
01A05h
01A04h
081h
069h
表 5-62. Device Descriptor(1)
MSP430FR59xx (UART BSL)
DESCRIPTION
ADDRESS
VALUE
06h
Info length
01A00h
01A01h
01A02h
01A03h
01A04h
01A05h
01A06h
01A07h
01A08h
01A09h
01A0Ah
01A0Bh
01A0Ch
01A0Dh
01A0Eh
01A0Fh
01A10h
01A11h
01A12h
01A13h
CRC length
06h
Per unit
Per unit
CRC value
Device ID
nfo Block
See 表 5-61.
Hardware revision
Firmware revision
Die record tag
Per unit
Per unit
08h
Die record length
0Ah
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Lot/Wafer ID
Die Record
Die X position
Die Y position
Test results
(1) NA = Not applicable, Per unit = content can differ from device to device
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表 5-62. Device Descriptor(1) (continued)
MSP430FR59xx (UART BSL)
DESCRIPTION
ADDRESS
VALUE
11h
ADC12 calibration tag
01A14h
01A15h
01A16h
01A17h
01A18h
01A19h
01A1Ah
01A1Bh
01A1Ch
01A1Dh
01A1Eh
01A1Fh
01A20h
01A21h
01A22h
01A23h
01A24h
01A25h
01A26h
01A27h
01A28h
01A29h
01A2Ah
01A2Bh
01A2Ch
01A2Dh
ADC12 calibration length
ADC gain factor(2)
10h
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
12h
ADC offset(3)
ADC 1.2-V reference
Temperature sensor 30°C
ADC 1.2-V reference
Temperature sensor 85°C
ADC12 Calibration
ADC 2.0-V reference
Temperature sensor 30°C
ADC 2.0-V reference
Temperature sensor 85°C
ADC 2.5-V reference
Temperature sensor 30°C
ADC 2.5-V reference
Temperature sensor 85°C
REF calibration tag
REF calibration length
06h
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
REF 1.2-V reference
REF 2.0-V reference
REF 2.5-V reference
REF Calibration
(2) ADC gain: the gain correction factor is measured at room temperature using a 2.5-V external voltage reference without internal buffer
(ADC12VRSEL=0x2, 0x4, or 0xE). Other settings (for example, using internal reference) can result in different correction factors.
(3) ADC offset: the offset correction factor is measured at room temperature using ADC12VRSEL= 0x2 or 0x4, an external reference,
VR+ = external 2.5 V, VR- = AVSS.
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表 5-62. Device Descriptor(1) (continued)
MSP430FR59xx (UART BSL)
ADDRESS VALUE
DESCRIPTION
128-bit random number tag
Random number length
01A2Eh
01A2Fh
01A30h
01A31h
01A32h
01A33h
01A34h
01A35h
01A36h
01A37h
01A38h
01A39h
01A3Ah
01A3Bh
01A3Ch
01A3Dh
01A3Eh
01A3Fh
01A40h
01A41h
01A42h
01A43h
15h
10h
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
1Ch
Random Number
128-bit random number(4)
BSL tag
BSL length
02h
BSL Configuration
BSL Interface
00h
BSL interface configuration
00h
(4) 128-bit random number: The random number is generated during production test using the CryptGenRandom() function from Microsoft®.
5.13 Identification
5.13.1 Revision Identification
The device revision information is shown as part of the top-side marking on the device package. The
device-specific errata sheet describes these markings. For links to the errata sheets for the devices in this
data sheet, see 节 7.3.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Hardware Revision" entries in 节 5.12.
5.13.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific
errata sheet describes these markings. For links to the errata sheets for the devices in this data sheet, see
节 7.3.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Device ID" entries in 节 5.12.
5.13.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in
detail in the MSP430 Programming With the JTAG Interface.
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6 Applications, Implementation, and Layout
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1 Software Best Practices for Radiation Effects Mitigation
Use of any MCU in a radiation environment introduces challenges for understanding radiation effects. The
most common approach for characterizing single events effects (SEE) is using a system approach. The
system requirements are modeled and implemented in hardware capable of being exposed to heavy ions
or protons. The effects on actual system behavior are then characterized, rather than utilizing specific
cross sections for the various hardware blocks. It is recommended that this approach be used to fully
understand the SEE performance of the MCU in a given end application.
Following are important recommendations that system designers can adopt to mitigate radiation effects:
•
The FRAM array is known to be very robust to corruption due to SEE. Accessing the FRAM (read or
write) creates possibility of corruption of data due to FRAM controller sensitivity. The probability of SEE
can be lowered by minimizing FRAM accesses and operating at lower frequency. A boot time
mitigation technique could implement a software code health check. Any detected corruption in critical
FRAM could be repaired by utilizing redundant code stored in unused area FRAM.
•
•
Creating error handlers for all critical interrupts is essential for device self-recovery from events.
Using the MPU to protect code space, look-up tables and interrupt vector tables (IVT) lowers
probability of corruption of critical data.
•
•
•
SRAM will have higher cross section than FRAM. It is recommended to use FRAM in place of SRAM
for volatile data.
Avoid pointer indexing and incrementing near memory space with critical data, such as code and IVT.
An event could offset the index resulting in reading/writing to unexpected locations.
The probability of SEE will be lowered when operating at a higher VCC
.
6.2 Device Connection and Layout Fundamentals
This section describes the recommended guidelines when designing with the MSP430. These guidelines
ensure that the device has proper connections for powering, programming, debugging, and optimum
analog performance.
6.2.1 Power Supply Decoupling and Bulk Capacitors
TI recommends connecting a combination of a 1-µF capacitor and a 100-nF low-ESR ceramic decoupling
capacitor to each AVCC and DVCC pin. Higher-value capacitors may be used but can affect supply rail
ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple
(within a few millimeters). Additionally, TI recommends separated grounds with a single-point connection
for better noise isolation from digital to analog circuits on the board and to achieve high analog accuracy.
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DVCC
Digital
Power Supply
Decoupling
+
+
1 µF
100 nF
100 nF
DVSS
AVCC
Analog
Power Supply
Decoupling
1 µF
AVSS
图 6-1. Power Supply Decoupling
6.2.2 External Oscillator
The device can support a low-frequency crystal (32 kHz) on the LFXT pins, a high-frequency crystal on
the HFXT pins, or both. External bypass capacitors for the crystal oscillator pins are required.
It is also possible to apply digital clock signals to the LFXIN and HFXIN input pins that meet the
specifications of the respective oscillator if the appropriate LFXTBYPASS or HFXTBYPASS mode is
selected. In this case, the associated LFXOUT and HFXOUT pins can be used for other purposes. If the
LFXIN and HFXIN are left unused, they must be terminated according to Section 3.4.
图 6-2 shows a typical connection diagram.
LFXIN
or
LFXOUT
or
HFXIN
HFXOUT
CL1
CL2
图 6-2. Typical Crystal Connection
See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal
oscillator with the MSP430 devices.
6.2.3 JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or
MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the
connections also support the MSP-GANG production programmers, thus providing an easy way to
program prototype boards, if desired. 图 6-3 shows the connections between the 14-pin JTAG connector
and the target device required to support in-system programming and debugging for 4-wire JTAG
communication. 图 6-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are
identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSP-
FET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an
alternate connection (pin 4 instead of pin 2). The VCC-sense feature senses the local VCC present on the
target board (that is, a battery or other local power supply) and adjusts the output signals accordingly. 图
6-3 and 图 6-4 show a jumper block that supports both scenarios of supplying VCC to the target board. If
this flexibility is not required, the desired VCC connections may be hard-wired to eliminate the jumper
block. Pins 2 and 4 must not be connected at the same time.
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For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User’s
Guide.
VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
AVCC/DVCC
J2 (see Note A)
R1
47 kW
JTAG
RST/NMI/SBWTDIO
VCC TOOL
TDO/TDI
TDI
TDO/TDI
TDI
2
1
3
VCC TARGET
4
TMS
TMS
6
5
TEST
TCK
8
7
TCK
GND
RST
10
12
14
9
11
13
TEST/SBWTCK
AVSS/DVSS
C1
2.2 nF
(see Note B)
Copyright © 2016, Texas Instruments Incorporated
A. If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,
make connection J2.
B. The upper limit for C1 is 2.2 nF when using current TI tools.
图 6-3. Signal Connections for 4-Wire JTAG Communication
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VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
J2 (see Note A)
AVCC/DVCC
R1
47 kΩ
(See Note B)
JTAG
VCC TOOL
TDO/TDI
2
1
3
5
7
9
RST/NMI/SBWTDIO
VCC TARGET
4
6
TCK
8
GND
10
12
14
11
13
TEST/SBWTCK
AVSS/DVSS
C1
2.2 nF
(See Note B)
Copyright © 2016, Texas Instruments Incorporated
A. Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the
debug or programming adapter.
B. The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with
the device. The upper limit for C1 is 2.2 nF when using current TI tools.
图 6-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
6.2.4 Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function
Register (SFR), SFRRPCR.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing
specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is
edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the
external NMI. When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either
pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.
If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an
external 47-kΩ pullup resistor to the RST/NMI pin with a 2.2-nF pulldown capacitor. The pulldown
capacitor should not exceed 2.2 nF when using devices in Spy-Bi-Wire mode or in 4-wire JTAG mode with
TI tools like FET interfaces or GANG programmers. If JTAG or Spy-Bi-Wire access is not needed, up to a
10-nF pulldown capacitor may be used.
See the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide for
more information on the referenced control registers and bits.
6.2.5 Unused Pins
For details on the connection of unused pins, see Section 3.4.
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6.2.6 General Layout Recommendations
•
Proper grounding and short traces for external crystal to reduce parasitic capacitance. See MSP430
32-kHz Crystal Oscillators for recommended layout guidelines.
•
•
Proper bypass capacitors on DVCC, AVCC, and reference pins if used.
Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital
switching signals such as PWM or JTAG signals away from the oscillator circuit.
•
•
See Circuit Board Layout Techniques for a detailed description of PCB layout considerations. This
document is written primarily about op amps, but the guidelines are generally applicable for all mixed-
signal applications.
Proper ESD level protection should be considered to protect the device from unintended high-voltage
electrostatic discharge. See MSP430 System-Level ESD Considerations for guidelines.
6.2.7 Do's and Don'ts
TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up,
power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the
limits specified in Section 4.1. Exceeding the specified limits may cause malfunction of the device
including erroneous writes to RAM and FRAM.
6.3 Peripheral- and Interface-Specific Design Information
6.3.1 ADC12_B Peripheral
6.3.1.1 Partial Schematic
图 6-5 shows the recommended decoupling circuit when an external voltage reference is used.
AVSS
VREF+/VEREF+
Using an
External
Positive
Reference
+
4.7 µF
10 µF
VEREF-
Using an
External
+
Negative
Reference
10 µF
4.7 µF
图 6-5. ADC12_B Grounding and Noise Considerations
6.3.1.2 Design Requirements
As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should
be followed to eliminate ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with
other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset
voltages that can add to or subtract from the reference or input voltages of the ADC. The general
guidelines in 节 6.2.1 combined with the connections in 节 6.3.1.1 prevent this.
In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital
switching or switching power supplies can corrupt the conversion result. TI recommends a noise-free
design using separate analog and digital ground planes with a single-point connection to achieve high
accuracy.
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图 6-5 shows the recommended decoupling circuit when an external voltage reference is used. The
internal reference module has a maximum drive current as specified in the Reference module's IO(VREF+)
specification.
The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are
selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage
enters the device. In this case, the 10-µF capacitor is used to buffer the reference pin and filter any low-
frequency ripple. A bypass capacitor of 4.7 µF is used to filter out any high-frequency noise.
6.3.1.3 Detailed Design Procedure
For additional design information, see Designing With the MSP430FR58xx, FR59xx, FR68xx, and FR69xx
ADC.
6.3.1.4 Layout Guidelines
Component that are shown in the partial schematic (see 图 6-5) should be placed as close as possible to
the respective device pins. Avoid long traces, because they add additional parasitic capacitance,
inductance, and resistance on the signal.
Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),
because the high-frequency switching can be coupled into the analog signal.
If differential mode is used for the ADC12_B, the analog differential input signals must be routed closely
together to minimize the effect of noise on the resulting signal.
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7 器件和文档支持
7.1 入门和后续步骤
有关 MSP430 系列器件以及有助于开发的工具和库的更多信息，请访问入门页面。
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7.2 工具和软件
表 7-1 列出 了 MSP430FR59xx 微控制器支持的调试特性。关于可用特性的详细信息，请参见《适用于
MSP430 的 Code Composer Studio 用户指南 》。
表 7-1. 硬件 功能
断点
(N)
状态序列发生
器
LPMx.5 调试支 EnergyTrace++ 技
MSP430 架构
4 线 JTAG 2 线 JTAG
范围断点
有
时钟控制
是
跟踪缓冲器
否
持
术
MSP430Xv2
有
有
3
否
有
有
EnergyTrace™技术可用于 Code Composer Studio 6.0 及更高版本。EnergyTrace 技术需要专用的调试器
电路，该电路受新一代板载 eZ-FET 闪存仿真工具和新一代独立 MSP-FET JTAG 仿真器的支持。有关更多
信息，请参阅《使用 Code Composer Studio 版本
6 与增强型仿真模块 (EEM) 进行高级调试》和
《MSP430™ 高级功耗优化：ULP Advisor™ 和 EnergyTrace™ 技术》。
设计套件与评估模块
MSP430FR5969 LaunchPad™ 开发套件
MSP-EXP430FR5969
LaunchPad
开发套件是适用于
MSP430FR5969 MCU 的易用型微控制器开发板。它包含了在 MSP430FRxx FRAM 平台上快
速开始开发所需要的全部资源，包括用于编程、调试和能量测量的板载仿真。
适用于 MSP430FRxx FRAM MCU 的 48 引脚目标开发板和 MSP-FET 编程器包 MSP-FET430U48C 是一
款强大的设计套件，可在 MSP 微控制器上快速进行应用开发。它包含 USB 调试接口，用于
通过 JTAG 接口或节省引脚的 Spy-Bi-Wire（2 线 JTAG）协议对系统内的 MSP MCU 进行编
程和调试。只需使用几次按键即可在数秒钟内擦除 FRAM 并对其进行编程；而且由于 MSP
FRAM 的功耗极低，因此无需外部电源。
MSP-TS430RGZ48C - 适用于 MSP430FRxx FRAM MCU 的 48 引脚目标开发板 MSP-TS430RGZ48C 是
一款独立的 48 引脚 ZIF 插座目标板，用于通过 JTAG 接口或 Spy-Bi-Wire（2 线 JTAG）协议
对系统内的 MSP430 MCU 进行编程和调试。
软件
MSP430Ware™ 软件 MSP430Ware 软件集合了所有 MSP430 器件的代码示例、数据表以及其他设计资
源，打包提供给用户。除了提供已有 MSP430 MCU 设计资源的完整集合外，MSP430Ware
软件还包含名为 MSP 驱动程序库的高级 API。借助该库可以轻松地对 MSP430 硬件进行编
程。MSP430Ware 软件以 CCS 组件或独立软件包两种形式提供。
MSP430FR59xx、MSP430FR58xx 代码示例 根据不同应用需求配置各集成外设的每个 MSP 器件均具备
相应的 C 代码示例。
适用于 MSP 超低功耗微控制器的 FRAM 嵌入式软件实用程序 TI FRAM 实用程序软件旨在用作不断扩充的
嵌入式软件实用程序集合，其中的实用程序充分利用了 FRAM 的超低功耗和近乎无限次的写
入寿命。这些实用程序适用于 MSP430FRxx FRAM 微控制器，并提供示例代码来协助应用程
序开发。
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MSP 驱动程序库 MSP 驱动程序库的抽象 API 提供易用的函数调用，无需直接操纵 MSP430 硬件的位与字
节。完整的文档通过具有帮助意义的 API 指南交付，其中包括有关每个函数调用和经过验证的
参数的详细信息。开发人员可以使用驱动程序库功能，以最低开销编写完整项目。
MSP EnergyTrace™ 技术 适用于 MSP430 微控制器的 EnergyTrace 技术是基于电能的代码分析工具，适
用于测量和显示应用的电能系统配置并帮助优化应用以实现超低功耗。
ULP（超低功耗）Advisor ULP Advisor™软件是一款辅助工具，旨在指导开发人员编写更为高效的代码，
从而充分利用 MSP 和 MSP432 微控制器独特的 超低功耗 功能。ULP Advisor 的目标人群是
微控制器的资深开发者和开发新手，可以根据详尽的 ULP 检验表检查代码，以便最大限度地
减少应用程序的能耗。在编译时，ULP Advisor 会提供通知和备注以突出显示代码中可以进一
步优化的区域，进而实现更低功耗。
IEC60730 软件包 IEC60730 MSP430 软件包经过专门开发，用于协助客户达到 IEC 60730-1:2010（家用
及类似用途的自动化电气控制 - 第 1 部分：一般要求）B 类产品的要求。其中涵盖家用电器、
电弧检测器、电源转换器、电动工具、电动自行车及其他诸多产品。IEC60730 MSP430 软件
包可以嵌入在 MSP430 MCU 中 运行的客户应用， 从而帮助客户简化其消费类器件在功能安
全方面遵循 IEC 60730-1:2010 B 类规范的认证工作。
适用于 MSP 的定点数学运算库 MSP IQmath 和 Qmath 库是一套经过高度优化的高精度数学运算函数集
合，适用于 C 语言开发者，能够将浮点算法无缝嵌入 MSP430 和 MSP432 器件的定点代码
中。这些例程通常用于计算密集的实时 应用， 而优化的执行速度、高精度以及超低能耗通常
是影响这些实时应用的关键因素。与使用浮点数学算法编写的同等代码相比，使用 IQmath 和
Qmath 库可以大幅提高执行速度并显著降低能耗。
适用于 MSP430 的浮点数学运算库
TI
在低功耗和低成本微控制器领域锐意创新，为您提供
MSPMATHLIB。此标量函数的浮点数学运算库，能够充分利用器件的智能外设，使速度最高
达到标准 MSP430 数学函数的 26 倍。Mathlib 能够轻松集成到您的设计中。该运算库免费使
用并集成在 Code Composer Studio IDE 和 IAR Embedded Workbench IDE 中。
开发工具
适用于 MSP 微控制器的 Code Composer Studio™ 集成开发环境 Code Composer Studio (CCS) 是一种
集成开发环境 (IDE)，支持所有 MSP 微控制器器件。CCS 包含一整套用于开发和调试嵌入式
应用。CCS 包含了优化的 C/C++ 编译器、源代码编辑器、项目构建环境、调试器、描述器以
及其他众多 功能。
命令行编程器 MSP Flasher 是一款基于 shell 的开源接口，可使用 JTAG 或 Spy-Bi-Wire (SBW) 通信通过
FET 编程器或 eZ430 对 MSP 微控制器进行编程。MSP Flasher 可用于将二进制文件（.txt 或
.hex 文件）直接下载到 MSP 微控制器，而无需使用 IDE。
MSP MCU 编程器和调试器 MSP-FET 是一款强大的仿真开发工具（通常称为调试探针），可帮助用户在
MSP 低功耗微控制器 (MCU) 中快速开发应用。创建 MCU 软件通常需要将生成的二进制程序
下载到 MSP 器件中，从而进行验证和调试。
MSP-GANG 生产编程器 MSP Gang 编程器是一款 MSP430 或 MSP432 器件编程器，可同时对多达八个
完全相同的 MSP430 或 MSP432 闪存或 FRAM 器件进行编程。MSP Gang 编程器可使用标
准的 RS-232 或 USB 连接与主机 PC 相连并提供灵活的编程选项，允许用户完全自定义流
程。
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7.3 文档支持
以下文档对 MSP430FR59xx MCU 进行了介绍。www.ti.com.cn 网站上提供了这些文档的副本。
接收文档更新通知
要接收文档更新通知（包括芯片勘误表），请转至 ti.com.cn 上您的器件对应的产品文件夹（关于产品文件
夹的链接，请参见节 7.5）。请单击右上角的“通知我”按钮。点击后，您将每周定期收到已更改的产品信息
（如果有的话）。有关更改的详细信息，请查阅已修订文档的修订历史记录。
用户指南
《MSP430FR58xx、MSP430FR59xx、MSP430FR68xx 和 MSP430FR69xx 系列用户指南》该器件系列
提供的所有模块和外设的详细 说明 。
MSP430FR57xx、MSP430FR58xx、MSP430FR59xx、MSP430FR68xx 和 MSP430FR69xx 引导加载程
序 (BSL) 引导加载程序（BSL，之前称为自举加载程序）可在 MSP430 MCU 项目的开发和更
新过程中对存储器进行编程。该程序可由使用串行协议发送命令的工具激活。BSL 支持用户控
制 MSP430 的活动，可与个人计算机或其他设备进行数据交换。
《通过 JTAG 接口对 MSP430 进行编程》 本文档介绍了使用 JTAG 通信端口擦除、编程和验证基于
MSP430 闪存和 FRAM 的微控制器系列的存储器模块所需的功能。此外，该文档还描述了如
何设定所有 MSP430 器件提供的 JTAG 访问安全熔丝。本文档介绍了使用标准 4 线 JTAG 接
口和 2 线 JTAG 接口（也称为 Spy-Bi-Wire (SBW)）访问 MCU。
《MSP430 硬件工具用户指南》 本手册介绍了 TI MSP-FET430 闪存仿真工具 (FET) 的硬件。FET 是针对
MSP430 超低功耗微控制器的程序开发工具。对提供的接口类型，即并行端口接口和 USB 接
口进行了说明。
116
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MSP430FR5969-SP
www.ti.com.cn
ZHCSH89A –DECEMBER 2017–REVISED MARCH 2018
应用报告
MSP430 FRAM 技术 – 操作方法和最佳实践 FRAM 采用非易失性存储器技术，行为与 SRAM 类似，支持
大量新 应用的同时，还改变了固件的设计方式。该应用程序报告从嵌入式软件开发方面概述了
FRAM 技术在 MSP430 中的使用方法和最佳实践。其中介绍了如何按照应用程序特定的代
码、常量、数据空间要求实施存储器布局以及如何使用 FRAM 优化应用程序的能耗。
MSP430 32kHz 晶体振荡器 对于稳定的晶体振荡器，选择合适的晶振、正确的负载电路和适当的电路板布
局布线至关重要。该应用报告总结了晶体振荡器的功能，介绍了为实现 MSP430 超低功耗运
行而选择正确晶体的参数。此外，还给出了正确电路板布局布线的提示和示例。本文档还包含
与可能振荡器测试相关的详细信息以确保大批量生产中的稳定振荡器运行。
《MSP430 系统级 ESD 注意事项》 系统级 ESD 对于低电压下的硅晶技术以及经济高效型和超低功耗组件
的需求日益增加。该应用报告提出了三项不同的 ESD 主题，旨在帮助电路板设计人员和 OEM
理解并设计出稳健耐用的系统级设计。
7.4 辐射信息
有关辐射信息详情，请访问 ti.com/radiation。
7.5 相关链接
表 7-2 列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件以及申请样片或购买产品的
快速访问链接。
表 7-2. 相关链接
器件
产品文件夹
请单击此处
立即订购
技术文档
工具和软件
请单击此处
支持和社区
请单击此处
MSP430FR5969
请单击此处
请单击此处
版权 © 2017–2018, Texas Instruments Incorporated
器件和文档支持
117
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产品主页链接: MSP430FR5969-SP
MSP430FR5969-SP
ZHCSH89A –DECEMBER 2017–REVISED MARCH 2018
www.ti.com.cn
7.6 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术
规范，并且不一定反映 TI 的观点；请参见 TI 的 《使用条款》。
TI E2E™ 社区
TI 的工程师交流 (E2E) 社区. 此社区的创建目的是为了促进工程师之间协作。在 e2e.ti.com 中，您可以提
问、共享知识、拓展思路，在同领域工程师的帮助下解决问题。
TI 嵌入式处理器维基网页
德州仪器 (TI) 嵌入式处理器维基网页。此网站的建立是为了帮助开发人员熟悉德州仪器 (TI) 的嵌入式处理
器，并且也为了促进与这些器件相关的硬件和软件的总体知识的创新和增长。
7.7 商标
EnergyTrace++, MSP430, EnergyTrace, LaunchPad, MSP430Ware, ULP Advisor, 适用于 MSP 微控制器
的 Code Composer Studio, E2E are trademarks of Texas Instruments.
Microsoft is a registered trademark of Microsoft Corporation.
All other trademarks are the property of their respective owners.
7.8 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
7.9 出口管制提示
接收方同意：如果美国或其他适用法律限制或禁止将通过非披露义务的披露方获得的任何产品或技术数据
（其中包括软件）（见美国、欧盟和其他出口管理条例之定义）、或者其他适用国家条例限制的任何受管制
产品或此项技术的任何直接产品出口或再出口至任何目的地，那么在没有事先获得美国商务部和其他相关政
府机构授权的情况下，接收方不得在知情的情况下，以直接或间接的方式将其出口。
7.10 术语表
TI 术语表
这份术语表列出并解释术语、缩写和定义。
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MSP430FR5969-SP
www.ti.com.cn
ZHCSH89A –DECEMBER 2017–REVISED MARCH 2018
8 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通
知，也不会对此文档进行修订。如需获取此数据表的浏览器版本，请参阅左侧的导航栏。
版权 © 2017–2018, Texas Instruments Incorporated
机械、封装和可订购信息
119
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
M4FR5969SPHPT-MLS
M4FR5969SRGZT-MLS
ACTIVE
ACTIVE
HTQFP
VQFN
PHP
RGZ
48
48
10
1
RoHS & Green
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-55 to 105
-55 to 105
FR5969-MLS
FR5969-MLS
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2022
OTHER QUALIFIED VERSIONS OF MSP430FR5969-SP :
Catalog : MSP430FR5969
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
M4FR5969SRGZT-MLS
VQFN
RGZ
48
1
180.0
16.4
7.3
7.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Feb-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RGZ 48
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
M4FR5969SRGZT-MLS
1
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGZ 48
7 x 7, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
RGZ0048B
VQFN - 1 mm max height
S
C
A
L
E
2
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
7.15
6.85
A
B
PIN 1 INDEX AREA
7.15
6.85
1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
2X 5.5
4.1 0.1
(0.2) TYP
EXPOSED
THERMAL PAD
13
24
44X 0.5
12
25
49
SYMM
2X
5.5
0.30
0.18
36
48X
1
0.1
0.05
C B A
48
37
SYMM
PIN 1 ID
(OPTIONAL)
0.5
0.3
48X
4218795/B 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGZ0048B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.1)
(1.115) TYP
(0.685)
TYP
37
48
48X (0.6)
1
36
48X (0.24)
(1.115)
TYP
44X (0.5)
(0.685)
TYP
SYMM
49
(
0.2) TYP
VIA
(6.8)
(R0.05)
TYP
12
25
13
24
SYMM
(6.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218795/B 02/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGZ0048B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.37)
TYP
37
48
48X (0.6)
1
36
48X (0.24)
44X (0.5)
(1.37)
TYP
SYMM
49
(R0.05) TYP
(6.8)
9X
METAL
TYP
(
1.17)
12
25
13
24
SYMM
(6.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 49
73% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:12X
4218795/B 02/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
GENERIC PACKAGE VIEW
PHP 48
7 x 7, 0.5 mm pitch
TQFP - 1.2 mm max height
QUAD FLATPACK
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226443/A
www.ti.com
PACKAGE OUTLINE
TM
PHP0048C
PowerPAD TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
7.2
6.8
B
NOTE 3
37
48
PIN 1 ID
1
36
7.2
6.8
9.2
TYP
8.8
NOTE 3
12
25
13
24
A
0.27
48X
44X 0.5
0.17
0.08
C A B
4X 5.5
1.2 MAX
C
SEATING PLANE
SEE DETAIL A
0.08
(0.13)
TYP
13
24
12
25
0.25
(1)
GAGE PLANE
4.6
3.6
49
0.75
0.45
0.15
0.05
0 -7
A
16
36
DETAIL A
TYPICAL
1
48
37
4X (0.115)NOTE5
4.6
3.6
4226381/A 11/2020
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MS-026.
5. Feature may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
PHP0048C
PowerPAD TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
(
6.5)
NOTE 10
(4.6)
SYMM
48
37
SOLDER MASK
DEFINED PAD
48X (1.6)
1
36
48X (0.3)
SYMM
49
(4.6)
(1.1 TYP)
(8.5)
44X (0.5)
12
25
(R0.05) TYP
(
0.2) TYP
VIA
METAL COVERED
BY SOLDER MASK
13
24
(1.1 TYP)
SEE DETAILS
(8.5)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4226381/A 11/2020
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,
Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
10. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
PHP0048C
PowerPAD TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
(4.6)
BASED ON
0.125 THICK STENCIL
SEE TABLE FOR
SYMM
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
48
37
48X (1.6)
1
36
48X (0.3)
(8.5)
(4.6)
SYMM
49
BASED ON
0.125 THICK
STENCIL
44X (0.5)
12
25
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
24
13
(8.5)
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
5.14 X 5.14
4.6 X 4.6 (SHOWN)
4.2 X 4.2
0.125
0.150
0.175
3.89 X 3.89
4226381/A 11/2020
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
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TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
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