MCF8316A_V01_技术文档

MCF8316A

SLLSFI0A – AUGUST 2021 – REVISED DECEMBER 2021

MCF8316A Sensorless Field Oriented Control (FOC) Integrated FET BLDC Driver

1 Features

3 Description

•

Three-phase BLDC motor driver with integrated

sensorless motor control algorithm

The MCF8316A provides a single-chip, code-free

sensorless FOC solution for customers driving speed-

controlled 12- to 24-V brushless-DC motors (BLDC)

or Permanent Magnet Synchronous motor (PMSM) up

to 8-A peak current. The MCF8316A integrates three

1/2-H bridges with 40-V absolute maximum capability

and a very low R_DS(ON)of 95 mΩ(high-side + low-

side). Power management features of an adjustable

buck regulator and LDO generate the 3.3-V or 5.0-V

voltage rails for the device and can be used to power

external circuits.

– Code-free Field Oriented Control (FOC)

– Offline motor parameters measurement with

Motor Parameter Extraction Tool (MPET)

– 5-point configurable speed profile support

– Windmilling support through forward

resynchronization and reverse drive

– Analog, PWM, freq. or I²C based speed input

– Configurable motor startup and stop options

– Anti-voltage surge protections prevents

overvoltage

– Improved acoustic performance with automatic

dead time compensation

4.5- to 35-V operating voltage (40-V abs max)

High output current capability: 8-A peak

Low MOSFET on-state resistance

– 95-mΩ R_DS(ON)(HS + LS) at T_A= 25°C

Low power sleep mode

– 3-µA (maximum) at V_VM= 24-V, T_A= 25°C

Speed loop accuracy: 3% with internal clock and

1% with external clock reference

Customer-configurable non-volatile memory

(EEPROM) to store device configuration

Supports up to 75-kHz PWM frequency for low

inductance motor support

Does not require external current sense resistors,

built-in current sensing

The algorithm configuration can be stored in non-

volatile EEPROM, which allows the device to operate

stand-alone once it has been configured. The device

receives a speed command through a PWM input,

analog voltage, variable frequency square wave or

I²C command. There are a large number of protection

features integrated into the MCF8316A, intended to

protect the device, motor, and system against fault

events.

•

Device Information⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE (NOM)

MCF8316A1V

VQFN (40)

7.00 mm × 5.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Documentation for reference:

•

Refer E2E FAQ for clarification.

Refer MCF8316A tuning guide

Refer to the MCF8316A EVM GUI

•

Built-in 3.3-V ±5%, 20-mA LDO regulator

Built-in 3.3-V/5-V, 170-mA buck regulator

Dedicated DRVOFF pin to disable (Hi-Z) outputs

Spread spectrum and slew rate for EMI mitigation

Suite of Integrated protection features

LDO out

3.3-V, up to 20-mA

4.5 to 35-V (40-V abs max)

Buck out

3.3 or 5.0-V, up to 170-mA

– Supply undervoltage lockout (UVLO)

– Motor lock detection (5 different types)

– Overcurrent protection (OCP)

– Thermal warning and shutdown (OTW/TSD)

– Fault condition indication pin (nFAULT)

– Optional fault diagnostics over I²C interface

SPEED

PWM, analog, frequency or

commanded over I²C

MCF8316A

A

B

C

DIRECTION

BRAKE

Sensorless

FOC

FG

Speed feecback

EEPROM

nFAULT

I²C

Op onal during opera on;

I²C speed, diagnos cs, or

on-the- y con gura on

Buck/LDO Regulator

Integrated Current Sensing

2 Applications

8-A peak output current,

typically 12 to 24-V

•

Brushless-DC (BLDC) Motor Modules

Residential and Living Fans

Air Purifiers and Humidifier Fans

Washer and Dishwashers Pumps

Automotive Fan and Blowers

Medical CPAP Blowers

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

MCF8316A

SLLSFI0A – AUGUST 2021 – REVISED DECEMBER 2021

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................6

6.5 Electrical Characteristics.............................................6

6.6 Characteristics of the SDA and SCL bus for

Standard and Fast mode.............................................12

6.7 Typical Characteristics..............................................14

7 Detailed Description......................................................15

7.1 Overview...................................................................15

7.2 Functional Block Diagram.........................................16

7.3 Feature Description...................................................17

7.4 Device Functional Modes..........................................68

7.5 External Interface......................................................68

7.6 EEPROM access and I²C interface.......................... 70

7.7 EEPROM (Non-Volatile) Register Map..................... 76

7.8 RAM (Volatile) Register Map...................................132

8 Application and Implementation................................158

8.1 Application Information........................................... 158

8.2 Typical Applications................................................ 158

9 Power Supply Recommendations..............................165

9.1 Bulk Capacitance....................................................165

10 Layout.........................................................................166

10.1 Layout Guidelines................................................. 166

10.2 Layout Example.................................................... 167

10.3 Thermal Considerations........................................168

11 Device and Documentation Support........................169

11.1 Support Resources............................................... 169

11.2 Trademarks........................................................... 169

11.3 Electrostatic Discharge Caution............................169

11.4 Glossary................................................................169

12 Mechanical, Packaging, and Orderable

Information.................................................................. 169

4 Revision History

Changes from Revision * (August 2021) to Revision A (December 2021)

Page

•

Updated device status to Production Data......................................................................................................... 1

2

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5 Pin Configuration and Functions

DVDD

DGND

FB_BK

1

2

32

31

30

29

28

27

26

25

24

23

22

21

EXT_WD

SCL

SDA

FG

3

4

GND_BK

SW_BK

CPL

SPEED/WAKE

5

AVDD

AGND

6

MCF8316A

(Thermal Pad)

CPH

7

CP

NC

8

9

VM

10

11

12

VM

PGND

DRVOFF

Figure 5-1. MCF8316A 40-Pin VQFN With Exposed Thermal Pad Top View

Table 5-1. Pin Functions

40-pin Package

MCF8316A

26

TYPE⁽¹⁾

DESCRIPTION

NAME

AGND

GND

Device analog ground. Refer Layout Guidelines for connections recommendation.

3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor

between the AVDD1 and AGND pins. This regulator can source up to 20 mA externally.

AVDD

BRAKE

CP

27

35

8

PWR O

High → Brake the motor when High

Low → normal operation

Connect to PGND via 10-kΩ resistor, if not used

I

Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the

CP and VM pins.

PWR

CPH

7

6

2

PWR

GND

Charge pump switching node. Connect a X5R or X7R, 47-nF, ceramic capacitor between

the CPH and CPL pins. TI recommends a capacitor voltage rating at least twice the

normal operating voltage of the device.

CPL

DGND

Device digital ground. Refer Layout Guidelines for connections recommendation.

Direction of motor spinning;

When low, phase driving sequence is OUT A → OUT C → OUT B

When high, phase driving sequence is OUT A → OUT B → OUT C

DIR

34

I

Connect to AVDD via 10-kΩ resistor, if not used

DRVOFF

DVDD

21

1

I

Coast (Hi-Z) all six MOSFETs when DRVOFF is high.

1.5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor

between the DVDD and DGND pins.

PWR

EXT_CLK

EXT_WD

33

32

I

External clock reference input in external clock reference mode.

External watchdog input.

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Table 5-1. Pin Functions (continued)

40-pin Package

MCF8316A

TYPE⁽¹⁾

DESCRIPTION

NAME

Feedback for buck regulator output control. Connect to buck regulator output after the

inductor/resistor.

FB_BK

3

PWR I/O

Motor speed indicator output. Open-drain output requires an external pull-up resistor to

1.8 to 5-V.

FG

29

4

O

GND

-

GND_BK

NC

Buck regulator ground. Refer Layout Guidelines for connections recommendation.

No connection, open

22, 23, 24, 25, 36,

37, 39

Fault indicator. Pulled logic-low with fault condition; Open-drain output requires an

external pull-up resistor to 1.8V to 5.0V.

nFAULT

40

O

OUTA

OUTB

OUTC

PGND

SCL

13, 14

16, 17

19, 20

12, 15, 18

31

PWR O

GND

I

Half bridge output A

Half bridge output B

Half bridge output C

Device power ground. Refer Layout Guidelines for connections recommendation.

I²C clock input

I²C data line

SDA

30

I/O

SPEED/

WAKE

Device speed input; supports analog, PWM or frequency based speed input. The speed

pin input can be configured through SPEED_MODE.

28

I

CSA output from one of the three phases depending on configuration - SOA, SOB or

SOC.

SOX

38

5

O

SW_BK

PWR

Buck switch node. Connect this pin to an inductor or resistor.

Device and motor power supply. Connect to motor supply voltage; bypass to GND with

one 0.1-µF capacitor plus one bulk capacitor. TI recommends a capacitor voltage rating at

least twice the normal operating voltage of the device.

VM

9, 10, 11

PWR I

GND

Thermal pad

Must be connected to ground.

(1) I = input, O = output, GND = groung pin, PWR = power, NC = no connect

4

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6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX UNIT

Power supply pin voltage (VM)

–0.3

40

4

V

V/µs

V

Power supply voltage ramp (VM)

Voltage difference between ground pins (GND_BK,DGND, PGND, AGND)

Charge pump voltage (CPH, CP)

–0.3

–1

0.3

V_VM+ 6

V_VM+0.3

5.75

V_VM+0.3

4

V

Charge pump negative switching pin voltage (CPL)

Switching regulator pin voltage (FB_BK)

Switching node pin voltage (SW_BK)

V

Analog regulators pin voltage (AVDD)

V

Analog regulators pin voltage (DVDD)

1.7

V

Logic pin input voltage (BRAKE, DRVOFF, DIR, EXT_CLK, EXT_WD, SCL, SDA, SPEED)

Open drain pin output voltage (nFAULT, FG)

Output pin voltage (OUTA, OUTB, OUTC)

Ambient temperature, T_A

6

V

6

V

V_VM+ 1

125

V

–40

–65

°C

Junction temperature, T_J

150

Storage tempertaure, T_stg

150

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.

If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime

6.2 ESD Ratings

VALUE

±2000

±750

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged device model (CDM), per JEDEC specification JS-002⁽²⁾

Electrostatic

discharge

V_(ESD)

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

NOM

MAX UNIT

V_VM

Power supply voltage

V_VM

4.5

24

35

8

V

A

(1)

I_OUT

Peak output winding current

OUTA, OUTB, OUTC

BRAKE, DRVOFF, DIR, EXT_CLK,

EXT_WD, SPEED, SDA, SCL

V_{IN_LOGIC}

Logic input voltage

–0.1

5.5

V

V_OD

I_OD

T_A

Open drain pullup voltage

nFAULT, FG

5.5

5

V

Open drain output current capability

Operating ambient temperature

Operating Junction temperature

mA

°C

–40

125

150

T_J

(1) Power dissipation and thermal limits must be observed

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UNIT

SLLSFI0A – AUGUST 2021 – REVISED DECEMBER 2021

6.4 Thermal Information

MCF8316A

RGF (VQFN)

40 Pins

25.7

THERMAL METRIC⁽¹⁾

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

15.2

7.3

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

Ψ_JB

7.2

R_θJC(bot)

2.0

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

at T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

POWER SUPPLIES

V_VM> 6 V, V_SPEED= 0, T_A= 25 °C

V_SPEED= 0, T_A= 125 °C

3

5

7

µA

I_VMQ

VM sleep mode current

3.5

V_VM> 6 V, V_SPEED> V_{EN_SB,}DRVOFF =

High, T_A= 25 °C, L_BK= 47 uH, C_BK= 22

µF

8

15

mA

V_VM> 6 V, V_SPEED> V_{EN_SB,}DRVOFF =

High, R_BK= 22 Ω, C_BK= 22 µF

25

8

28

15

28

mA

I_VMS

VM standby mode current

V_VM> 6 V, V_SPEED> V_{EN_SB,}DRVOFF =

High, L_BK= 47 uH, C_BK= 22 µF

V_VM> 6 V, V_SPEED> V_{EN_SB,}DRVOFF =

High, R_BK= 22 Ω, C_BK= 22 µF

25

V_VM> 6 V, V_SPEED> V_{EX_SL}

,

PWM_FREQ_OUT = 0011b (25 kHz),

T_J= 25 °C, L_BK= 47 uH, C_BK= 22 µF,

No Motor Connected

11

27

11

18

30

17

30

mA

V_VM> 6 V, V_SPEED> V_{EX_SL}

,

PWM_FREQ_OUT = 0011b (25 kHz),

T_J= 25 °C, R_BK= 22 Ω, C_BK= 22 µF,

No Motor Connected

I_VM

VM operating mode current

V_VM> 6 V, V_SPEED> V_{EX_SL}

,

PWM_FREQ_OUT = 0011b (25 kHz),

L_BK= 47 uH, C_BK= 22 µF, No Motor

Connected

V_VM> 6 V, V_SPEED> V_{EX_SL}

,

PWM_FREQ_OUT = 0011b (25 kHz),

R_BK= 22 Ω, C_BK= 22 µF, No Motor

Connected

28

V_AVDD

I_AVDD

V_DVDD

V_VCP

f_CP

Analog regulator voltage

0 mA ≤ I_AVDD≤ 30 mA

3.125

3.3

3.465

20

V

mA

V

External analog regulator load

Digital regulator voltage

1.4

4.0

1.55

4.7

1.65

5.5

Charge pump regulator voltage

Charge pump switching frequency

VCP with respect to VM

V

400

kHz

6

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at T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

BUCK REGULATOR

V_VM> 6 V, 0 mA ≤ I_BK≤ 170 mA,

BUCK_SEL = 00b

3.1

4.6

3.7

5.2

3.3

5.0

4.0

5.7

3.5

5.4

4.3

6.2

V

V_VM> 6 V, 0 mA ≤ I_BK≤ 170 mA,

BUCK_SEL = 01b

Buck regulator average voltage

(L_BK= 47 µH, C_BK= 22 µF)

V_VM> 6 V, 0 mA ≤ I_BK≤ 170 mA,

BUCK_SEL = 10b

V_BK

V_VM> 6.7 V, 0 mA ≤ I_BK≤ 170 mA,

BUCK_SEL = 11b

V_VM< 6.0 V (BUCK_SEL = 00b, 01b,

10b) or V_VM< 6.0 V (BUCK_SEL = 11b),

0 mA ≤ I_BK≤ 170 mA

V_VM–

I_BK*(R_LBK

V

+2) ⁽¹⁾

V_VM> 6 V, 0 mA ≤ I_BK≤ 20 mA,

BUCK_SEL = 00b

3.1

4.6

3.7

5.2

3.3

5.0

4.0

5.7

3.5

5.4

4.3

6.2

V

V_VM> 6 V, 0 mA ≤ I_BK≤ 20 mA,

BUCK_SEL = 01b

Buck regulator average voltage

(L_BK= 22 µH, C_BK= 22 µF)

V_VM> 6 V, 0 mA ≤ I_BK≤ 20 mA,

BUCK_SEL = 10b

V_BK

V_VM> 6.7 V, 0 mA ≤ I_BK≤ 20 mA,

BUCK_SEL = 11b

V_VM< 6.0 V (BUCK_SEL = 00b, 01b,

10b) or V_VM< 6.0 V (BUCK_SEL = 11b),

0 mA ≤ I_BK≤ 20 mA

V_VM–

I_BK*(R_LBK

V

+2)⁽¹⁾

V_VM> 6 V, 0 mA ≤ I_BK≤ 10 mA,

BUCK_SEL = 00b

3.1

4.6

3.7

5.2

3.3

5.0

4.0

5.7

3.5

5.4

4.3

6.2

V

V_VM> 6 V, 0 mA ≤ I_BK≤ 10 mA,

BUCK_SEL = 01b

Buck regulator average voltage

(R_BK= 22 Ω, C_BK= 22 µF)

V_VM> 6 V, 0 mA ≤ I_BK≤ 10 mA,

BUCK_SEL = 10b

V_BK

V_VM> 6.7 V, 0 mA ≤ I_BK≤ 10 mA,

BUCK_SEL = 11b

V_VM< 6.0 V (BUCK_SEL = 00b, 01b,

10b) or V_VM< 6.0 V (BUCK_SEL = 11b),

0 mA ≤ I_BK≤ 10 mA

V_VM–

I_BK*(R_BK

+2)

V

V_VM> 6 V, 0 mA ≤ I_BK≤ 170 mA, Buck

regulator with inductor, L_BK= 47 uH, C_BK

= 22 µF

–100

100

mV

V_VM> 6 V, 0 mA ≤ I_BK≤ 20 mA, Buck

regulator with inductor, L_BK= 22 uH, C_BK

= 22 µF

V_{BK_RIP}

Buck regulator ripple voltage

V_VM> 6 V, 0 mA ≤ I_BK≤ 10 mA, Buck

regulator with resistor; R_BK= 22 Ω, C_BK

= 22 µF

100

170

L_BK= 47 uH, C_BK= 22 µF,

BUCK_PS_DIS = 1b

mA

L_BK= 47 uH, C_BK= 22 µF,

BUCK_PS_DIS = 0b

170 –

I_AVDD

L_BK= 22 uH, C_BK= 22 µF,

BUCK_PS_DIS = 1b

20

I_BK

External buck regulator load

L_BK= 22 uH, C_BK= 22 µF,

BUCK_PS_DIS = 0b

20 –

I_AVDD

R_BK= 22 Ω, C_BK= 22 µF,

BUCK_PS_DIS = 1b

10

R_BK= 22 Ω, C_BK= 22 µF,

BUCK_PS_DIS = 0b

10 –

I_AVDD

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at T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Regulation Mode

20

535

2.95

2.7

kHz

V

f_{SW_BK}

Buck regulator switching frequency

Linear Mode

20

V_BKrising, BUCK_SEL = 00b

V_BKfalling, BUCK_SEL = 00b

V_BKrising, BUCK_SEL = 01b

V_BKfalling, BUCK_SEL = 01b

V_BKrising, BUCK_SEL = 10b

V_BKfalling, BUCK_SEL = 10b

V_BKrising, BUCK_SEL = 11b

V_BKfalling, BUCK_SEL = 11b

2.7

2.5

4.3

4.1

2.7

2.5

4.3

4.1

2.8

2.6

4.4

4.2

2.8

2.6

4.4

4.2

V

4.55

4.35

2.95

2.7

V

Buck regulator undervoltage lockout

V_{BK_UV}

V

4.55

4.35

V

Buck regulator undervoltage lockout

hysteresis

V_{BK_UV_HYS}

Rising to falling threshold

90

200

400

mV

BUCK_CL = 0b

BUCK_CL = 1b

360

80

600

150

910

250

mA

Buck regulator Current limit threshold

I_{BK_CL}

Buck regulator Overcurrent protection

trip point

I_{BK_OCP}

2

3

1

4

A

t_{BK_RETRY}

Overcurrent protection retry time

0.7

1.3

ms

DRIVER OUTPUTS

V_VM> 6 V, I_OUT= 1 A, T_A= 25°C

V_VM< 6 V, I_OUT= 1 A, T_A= 25°C

V_VM> 6 V, I_OUT= 1 A, T_J= 150 °C

V_VM< 6 V, I_OUT= 1 A, T_J= 150 °C

V_VM= 24 V, SLEW_RATE = 00b

V_VM= 24 V, SLEW_RATE = 01b

V_VM= 24 V, SLEW_RATE = 10b

V_VM= 24 V, SLEW_RATE = 11b

V_VM= 24 V, SLEW_RATE = 00b

V_VM= 24 V, SLEW_RATE = 01b

V_VM= 24 V, SLEW_RATE = 10b

V_VM= 24 V, SLEW_RATE = 11b

V_VM= 24 V, SR = 25 V/µs

95

105

140

145

25

125

130

185

190

45

mΩ

V/us

ns

Total MOSFET on resistance (High-side

+ Low-side)

R_DS(ON)

13

30

50

80

Phase pin slew rate switching low to high

(Rising from 20 % to 80 %)

SR

80

125

200

25

185

280

45

130

14

30

50

80

Phase pin slew rate switching high to low

(Falling from 80 % to 20 %

SR

80

125

200

1800

1100

650

500

185

280

3400

1550

1000

750

110

V_VM= 24 V, SR = 50 V/µs

ns

Output dead time (high to low / low to

high)

t_DEAD

V_VM= 24 V, SR = 125 V/µs

ns

V_VM= 24 V, SR = 200 V/µs

ns

8

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at T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SPEED INPUT - PWM MODE

ƒ_PWM

PWM input frequency

PWM input resolution

0.01

11

12

11

13

12

11

10

8

95

13

14

12

14

13

12

11

10

kHz

bits

f_PWM= 0.01 to 0.35 kHz

12

13

f_PWM= 0.35 to 2 kHz

f_PWM= 2 to 3.5 kHz

f_PWM= 3.5 to 7 kHz

f_PWM= 7 to 14 kHz

f_PWM= 14 to 29.2 kHz

f_PWM= 29.3 to 60 kHz

f_PWM= 60 to 95 kHz

11.5

13.5

12.5

11.5

10.5

9

Res_PWM

SPEED INPUT - ANALOG MODE

V_{ANA_FS}

Analog full-speed voltage

Analog voltage resolution

2.95

3

3.05

V

V_{ANA_RES}

732

μV

SPEED INPUT - FREQUENCY MODE

ƒ_{PWM_FREQ}PWM input frequency range

SLEEP MODE

Duty cycle = 50%

32767

40

Hz

V_{EN_SL}

V_{EX_SL}

Analog voltage to enter sleep mode

Analog voltage to exit sleep mode

SPEED_MODE = 00b (analog mode)

mV

V

2.2

0.5

Time needed to detect wake up signal on SPEED_MODE = 00b (analog mode)

SPEED pin

t_{DET_ANA}

1

3

1.5

5

μs

V_SPEED> V_{EX_SL}

V_SPEED> V_{EX_SL}to DVDD voltage

available, SPEED_MODE = 01b (PWM

mode)

t_WAKE

Wakeup time from sleep mode

ms

t_{EX_SL_DR_A}Time taken to drive motor after exiting

SPEED_MODE = 00b (analog mode)

V_SPEED> V_{EN_SL}, ISD detection disabled

20

ms

μs

from sleep mode

NA

Time needed to detect wake up signal on SPEED_MODE = 01b (PWM mode)

SPEED pin

t_{DET_PWM}

0.5

1

3

1.5

V_SPEED> V_{DIG_IH}

V_SPEED> V_{DIG_IH}to DVDD voltage

available and release nFault,

t_{WAKE_PWM}Wakeup time from sleep mode

5

ms

SPEED_MODE = 01b (PWM mode)

t_{EX_SL_DR_P}Time taken to drive motor after wakeup SPEED_MODE = 01b (PWM mode)

20

2

ms

from sleep state

V_SPEED> V_{DIG_IH}, ISD detection disabled

WM

SPEED_MODE = 00b (analog mode)

V_SPEED< V_{EN_SL}

t_{DET_SL_ANA}Time needed to detect sleep command

0.5

1

SPEED_MODE = 01b (PWM mode)

V_SPEED< V_{DIG_IL}, SLEEP_ENTRY_TIME

= 00b

0.035

0.05

0.065

0.26

26

ms

SPEED_MODE = 01b (PWM mode)

V_SPEED< V_{DIG_IL}, SLEEP_ENTRY_TIME

= 01b

0.14

14

0.2

20

t_{DET_SL_PWM}Time needed to detect sleep command

SPEED_MODE = 01b (PWM mode)

V_SPEED< V_{DIG_IL}

,

SLEEP_ENTRY_TIME = 10b

SPEED_MODE = 01b (PWM mode)

V_SPEED< V_{DIG_IL}, SLEEP_ENTRY_TIME

= 11b

140

200

260

t_{DET_SL_FRE}

SPEED_MODE = 11b (Frequency mode)

V_SPEED< V_{DIG_IL}

Time needed to detect sleep command

4000

1

ms

Q

Time needed to stop driving motor after V_SPEED< V_{EN_SL}(analog

t_{EN_SL}

2

detecting sleep command

mode) or V_SPEED< V_{DIG_IL}(PWM mode)

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at T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

STANDBY MODE

V_{EN_SB}

V_{EX_SB}

Analog voltage to enter standby mode

Analog voltage to exit standby mode

SPEED_MODE = 00b (analog mode)

40

mV

170

t_{EX_SB_DR_A}Time taken to drive motor after exiting

SPEED_MODE = 00b (analog mode)

V_SPEED> V_{EN_SB}, ISD detection disabled

6

2

ms

standby mode

NA

t_{EX_SB_DR_P}Time taken to drive motor after exiting

SPEED_MODE = 01b (PWM mode)

V_SPEED> V_{DIG_IH}, ISD detection disabled

standby mode

WM

SPEED_MODE = 00b (analog mode)

V_SPEED< V_{EN_SB}

t_{DET_SB_ANA}Time needed to detect standby mode

0.5

1

SPEED_MODE = 01b (PWM mode)

V_SPEED< V_{DIG_IL}, SLEEP_ENTRY_TIME

= 00b

0.035

0.05

0.065

0.26

26

ms

SPEED_MODE = 01b (PWM mode)

V_SPEED< V_{DIG_IL}, SLEEP_ENTRY_TIME

= 01b

0.14

14

0.2

20

Time needed to detect standby

t_{EN_SB_PWM}

command

SPEED_MODE = 01b (PWM mode)

V_SPEED< V_{DIG_IL}

,

SLEEP_ENTRY_TIME = 10b

SPEED_MODE = 01b (PWM mode)

V_SPEED< V_{DIG_IL}

,

140

200

260

SLEEP_ENTRY_TIME = 11b

SPEED_MODE = 11b (Frequency

mode), V_SPEED< V_{DIG_IL}

t_{EN_SB_FREQ}Time needed to detect standby mode

4000

1

ms

SPEED_MODE = 10b (I2C

mode), SPEED_CMD = 0

t_{EN_SB_DIG}

Time needed to detect standby mode

2

V_SPEED< V_{EN_SL}(analog

mode) or V_SPEED< V_{DIG_IL}(PWM mode)

or SPEED_CMD = 0 (I2C mode)

Time needed to stop driving motor after

detecting standby command

t_{EN_SB}

1

ms

LOGIC-LEVEL INPUTS (BRAKE, DIR, EXT_CLK, EXT_WD, SCL, SDA, SPEED)

0.25*AV

DD

V_IL

V_IH

Input logic low voltage

Input logic high voltage

AVDD = 3 to 3.6 V

V

0.65*AV

DD

V_HYS

I_IL

Input hysteresis

50

-0.15

-0.3

0.6

500

800

0.15

0

mV

µA

Input logic low current

Input logic high current

AVDD = 3 to 3.6 V

SPEED pin To GND

To GND

I_IH

µA

R_{PD_SPEED}Input pulldown resistance

R_PDInput pulldown resistance

OPEN-DRAIN OUTPUTS (nFAULT, FG)

1

1.4

110

MΩ

kΩ

90

100

V_OL

Output logic low voltage

I_OD=-5 mA

V_OD= 3.3 V

0.4

0.5

V

I_OZ

Output logic high current

0

µA

I²C Serial Interface

0.3*AVD

D

V_{I2C_L}

LOW-level input voltage

-0.5

V

0.7*AVD

D

V_{I2C_H}

HIGH-level input voltage

Hysterisis

5.5

0.05*AV

DD

V_{I2C_HYS}

V_{I2C_OL}

I_{I2C_OL}

I_{I2C_IL}

C_i

LOW-level output voltage

LOW-level output current

open-drain at 2mA sink current

V_{I2C_OL}= 0.6V

0

0.4

6

V

mA

µA

pF

Input current on SDA and SCL

Capacitance for SDA and SCL

-10⁽²⁾

10⁽²⁾

10

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at T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Standard Mode

250⁽³⁾

ns

Output fall time from V_{I2C_H}(min) to

V_{I2C_L}(max)

t_of

Fast Mode

Pulse width of spikes that must be

suppressed by the input filter

t_SP

0

50⁽⁴⁾

ns

OSCILLATOR

EXT_CLK_CONFIG = 000b

EXT_CLK_CONFIG = 001b

EXT_CLK_CONFIG = 010b

EXT_CLK_CONFIG = 011b

EXT_CLK_CONFIG = 100b

EXT_CLK_CONFIG = 101b

EXT_CLK_CONFIG = 110b

EXT_CLK_CONFIG = 111b

8

16

kHz

32

64

f_OSCREF

External clock reference

128

256

512

1024

EEPROM

EE_Prog

Programing voltage

Retention

1.35

1.5

1.65

V

T_A= 25 ℃

100

Years

Cycles

EE_RET

EE_END

T_J= -40 to 150 ℃

T_J= -40 to 85 ℃

10

1000

Endurance

20000

PROTECTION CIRCUITS

V_UVLOSupply undervoltage lockout (UVLO)

VM rising

VM falling

4.3

4.1

140

3

4.4

4.2

200

5

4.5

4.3

350

7

V

V_{UVLO_HYS}Supply undervoltage lockout hysteresis Rising to falling threshold

mV

µs

t_UVLO

Supply undervoltage deglitch time

Supply rising, OVP_EN = 1, OVP_SEL =

0

32.5

31.8

20

34

33

22

21

35

34.3

23

V

Supply falling, OVP_EN = 1, OVP_SEL

= 0

V_OVP

Supply overvoltage protection (OVP)

Supply rising, OVP_EN = 1, OVP_SEL =

1

Supply falling, OVP_EN = 1, OVP_SEL

= 1

19

22

Rising to falling threshold, OVP_SEL = 1

Rising to falling threshold, OVP_SEL = 0

0.9

0.7

2.5

2.25

2.2

65

1

0.8

5

1.1

0.9

7

V

V_{OVP_HYS}

t_OVP

Supply overvoltage protection (OVP)

Supply overvoltage deglitch time

µs

V

Supply rising

2.5

2.4

100

2.85

2.65

2.75

2.6

150

3

Charge pump undervoltage lockout

(above VM)

V_CPUV

Supply falling

V

V_{CPUV_HYS}Charge pump UVLO hysteresis

Rising to falling threshold

Supply rising

mV

V

2.7

2.5

V_{AVDD_UV}

Analog regulator undervoltage lockout

Supply falling

2.8

V

V_{AVDD_}

Analog regulator undervoltage lockout

hysteresis

Rising to falling threshold

180

200

240

mV

UV_HYS

OCP_LVL = 0b

OCP_LVL = 1b

10

15

16

24

20

28

A

I_OCP

Overcurrent protection trip point

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at T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

MIN

0.1

0.2

0.6

1

TYP

0.3

0.6

1.25

1.6

5

MAX UNIT

OCP_DEG = 00b

0.7

1.2

1.8

2.5

6

µs

ms

°C

OCP_DEG = 01b

t_OCP

Overcurrent protection deglitch time

OCP_DEG = 10b

OCP_DEG = 11b

OCP_RETRY = 0

OCP_RETRY = 1

Die temperature (T_J)

4

t_RETRY

Overcurrent protection retry time

425

160

25

500

170

30

575

180

35

T_OTW

Thermal warning temperature

Thermal warning hysteresis

T_{OTW_HYS}

T_TSD

T_{TSD_HYS}

T_TSD

Thermal shutdown temperature

Thermal shutdown hysteresis

Thermal shutdown temperature (FET)

Thermal shutdown hysteresis (FET)

175

25

185

30

195

35

170

20

180

25

190

30

T_{TSD_HYS}

(1) R_LBKis resistance of inductor L_BK

(2) If AVDD is switched off, I/O pins must not obstruct the SDA and SCL lines.

(3) The maximum tf for the SDA and SCL bus lines (300 ns) is longer than the specified maximum tof for the output stages (250 ns). This

allows series protection resistors (Rs) to be connected between the SDA/SCL pins and the SDA/SCL bus lines without exceeding the

maximum specified tf.

(4) Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns

6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

Standard-mode

f_SCL

SCL clock frequency

0

4

100

kHz

µs

After this period, the first clock pulse is

generated

t_{HD_STA}

Hold time (repeated) START condition

t_LOW

t_HIGH

LOW period of the SCL clock

HIGH period of the SCL clock

4.7

4

µs

Set-up time for a repeated START

condition

t_{SU_STA}

4.7

µs

(4)

t_{HD_DAT}

t_{SU_DAT}

t_r

Data hold time ⁽²⁾

I2C bus devices

0 ⁽³⁾

250

µs

ns

Data set-up time

Rise time for both SDA and SCL signals

1000

300

Fall time of both SDA and SCL signals ⁽³⁾

t_f

ns

µs

(6) (7) (8)

t_{SU_STO}

t_BUF

Set-up time for STOP condition

4

Bus free time between STOP and START

condition

4.7

C_b

Capacitive load for each bus line ⁽⁹⁾

Data valid time ⁽¹⁰⁾

400

3.45 ⁽⁴⁾

pF

µs

t_{VD_DAT}

t_{VD_ACK}

Data valid acknowledge time ⁽¹¹⁾

For each connected device (including

hysteresis)

0.1*AVD

D

V_nL

V_nh

Noise margin at the LOW level

Noise margin at the HIGHlevel

V

For each connected device (including

hysteresis)

0.2*AVD

D

Fast-mode

f_SCL

SCL clock frequency

Hold time (repeated) START condition

0

400

KHz

µs

After this period, the first clock pulse is

generated

t_{HD_STA}

0.6

12

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over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

1.3

NOM

MAX

UNIT

µs

t_LOW

t_HIGH

LOW period of the SCL clock

HIGH period of the SCL clock

0.6

µs

Set-up time for a repeated START

condition

t_{SU_STA}

0.6

µs

(4)

t_{HD_DAT}

t_{SU_DAT}

t_r

Data hold time ⁽²⁾

0 ⁽³⁾

100 ⁽⁵⁾

20

µs

ns

Data set-up time

Rise time for both SDA and SCL signals

300

20 x

(AVDD/

5.5V)

Fall time of both SDA and SCL signals ⁽³⁾

t_f

ns

(6) (7) (8)

t_{SU_STO}

t_BUF

Set-up time for STOP condition

0.6

1.3

µs

Bus free time between STOP and START

condition

C_b

Capacitive load for each bus line ⁽⁹⁾

Data valid time ⁽¹⁰⁾

400

0.9 ⁽⁴⁾

pF

µs

t_{VD_DAT}

t_{VD_ACK}

Data valid acknowledge time ⁽¹¹⁾

For each connected device (including

hysteresis)

0.1*AVD

D

V_nL

V_nh

Noise margin at the LOW level

Noise margin at the HIGHlevel

V

For each connected device (including

hysteresis)

0.2*AVD

D

(1) All values referred to V_IH(min)(0.3V_DD) and V_IL(max)levels (see Table 9).

(2) t_{HD_DAT}is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.

(3) A device must internally provice a hold time of at least 300 ns for the SDA signal (with respect to the V_IH(min)of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

(4) The maximum t_{HD_DAT}could be 3.45 us and .9 us for Standard-mode and Fast-mode, but must be less than the maximum of t_{VD_DAT}or

t_{VD_ACK}by a transistion time. This maximum must only be met if the device does not stretch the LOW period (t_LOW) of the SCL signal. If

the clock stretched the SCL, the data must be valid by the set-up time before it releases the clock.

(5) A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement t_{SU_DAT}250 ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the

LOW period if the SCL signal, it must output the next data bit to the SDA line t_r(max)+ t_{SU_DAT}= 1000 + 250 = 1250 ns (according to the

Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

(6) If mixed with Hs-mode devices, faster fall times according to Table 10 are allowed.

(7) The maximum t_ffor the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t_fis specified

at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines

without exceeding the maximum specified t_f.

(8) In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should

allow for this when considering bus timing.

(9) The maximum bus capacitance allowable may vary from the value depending on the actual operating voltage and frequency of the

application.

(10) t_{VD_DAT}= time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

(11) t_{VD_ACK}= time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, dependging on which one is worse).

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6.7 Typical Characteristics

30

28.5

27

25.5

24

160

150

140

130

120

110

100

90

22.5

Buck with Inductor (25C)

21

19.5

18

16.5

15

Buck with Inductor (150C)

Buck with Resistor (25C)

Buck with Resistor (150C)

13.5

12

80

70

10.5

9

60

-40 -20

10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35

Supply Voltage (V)

0

20

40

60

80 100 120 140

Junction Temperature (C)

Figure 6-1. Supply current over supply voltage

Figure 6-2. R_DS(ON)(high and low side combined)

for MOSFETs over temperature

100

5.75

5.5

T_J= -40 C

97.5

T_J= 25 C

T_J= -150 C

5.25

5

95

92.5

90

4.75

BUCK_SEL = 00b

BUCK_SEL = 01b

BUCK_SEL = 10b

BUCK_SEL = 11b

4.5

87.5

85

4.25

4

82.5

80

3.75

3.5

3.25

3

77.5

75

0

0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2

Buck Output Load Current (A)

4

8

12

16

20

24

28

32

36

Supply Voltage (V)

Figure 6-4. Buck regulator output voltage over load

current

Figure 6-3. Buck regulator efficiency over supply

voltage

14

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7 Detailed Description

7.1 Overview

The MCF8316A provides a single-chip, code-free sensorless FOC solution for customers driving speed-

controlled 12- to 24-V brushless-DC motors requiring up to 8-A peak phase currents.

The MCF8316A integrates three 1/2-H bridges with 40-V absolute maximum capability and a very low R_DS(ON)

of 95-mΩ (high-side + low-side) to enable high power drive capability. Current is sensed using an integrated

current sensing circuit which eliminates the need for external sense resistors. Power management features of an

adjustable buck regulator and LDO generate the necessary voltage rails for the device and can be used to power

external circuits.

MCF8316A implements Sensorless FOC, and so an external microcontroller is not required to spin the

brushless-DC motor. The algorithm is implemented in a fixed-function state machine, so no coding is needed.

The algorithm is highly configurable through register settings ranging from motor start-up behavior to closed

loop operation. Register settings can be stored in non-volatile EEPROM, which allows the device to operate

stand-alone once it has been configured. The device receives a speed command through a PWM input, analog

voltage, frequency input or I²C command.

In-built protection features include power-supply undervoltage lockout (UVLO), charge-pump undervoltage

lockout (CPUV), overcurrent protection (OCP), AVDD undervoltage lockout (AVDD_UV), buck regulator UVLO,

motor lock detection and overtemperature warning and shutdown (OTW and TSD). Fault events are indicated by

the nFAULT pin with detailed fault information available in the registers.

The MCF8316A device is available in a 0.5-mm pin pitch, VQFN surface-mount package. The VQFN package

size is 7 mm × 5 mm with a height of 1 mm.

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7.2 Functional Block Diagram

C_AVDD1µF

C_FLY47nF

VM

L_BK

AVDD

Out

Buck

Out

- or -

R_BK

SW_BK

AVDD AGND

CPL

CPH

CP

C_CP

1µF

C_BK

VM

GND_BK

Buck/LDO

Regulator

AVDD LDO

Regulator

Charge Pump

Input VM or

Buck/LDO

FB_BK

DVDD

C_VM1

+

C_VM2

0.1µF

>10µF

DVDD

LDO

Regulator

Protection

VCP

C_DVDD

1µF

DRVOFF

VM

DGND

EEPROM

OUTA

SPEED/WAKE

BRAKE

PWM, Freq or

Analog Input

Sensorless

Control

VGLS

Integrated

current

sensing

AVDD

DIR

PGND

IO Interafce

ISENA

PGND

VM

Protection

PGND

A

Protection

VCP

DRVOFF

FG

nFAULT

AVDD

OUTB

VGLS

Speed profiles

Speed loop

SCL

Integrated

current

sensing

AVDD

I²C

SDA

PGND

2

ISENB

Motor Parameter Extraction

PGND

VM

Protection

PGND

Optional external

clock reference

EXT_WD

EXT_CLK

Protection

VCP

DRVOFF

Built-in 60-MHz

Oscillator

12-bit

ADC

OUTC

Op onal external

clock reference

VGLS

Integrated

current

sensing

ISENx output

on SOX pin

VM

ISENA

OUTA

PGND

SOX

ISENB

ISENC

OUTB

PGND

ISENC

PGND

OUTC

Protection

Figure 7-1. MCF8316A Functional Block Diagram

16

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7.3 Feature Description

7.3.1 Output Stage

The MCF8316A consists of an integrated 95-mΩ (combined high-side and low-side FETs' on-state resistance)

NMOS FETs connected in a three-phase bridge configuration. A doubler charge pump provides the proper

gate-bias voltage to the high-side NMOS FETs across a wide operating-voltage range in addition to providing

100% duty-cycle support. An internal linear regulator provides the gate-bias voltage for the low-side MOSFETs.

7.3.2 Device Interface Modes

The MCF8316A supports I²C interface to provide end application design with adequate flexibility. MCF8316A

allows controlling the motor operation and system through BRAKE, DRVOFF, DIR, EXT_CLK, EXT_WD

and SPEED/WAKE. MCF8316A also provides different signals for monitoring speed, fault and phase current

feedback through FG, nFAULT and SOX .

7.3.2.1 Interface - Control and Monitoring

Motor Control Signals

•

When BRAKE pin is driven 'High', MCF8316A enters brake state. Brake state can be configured to either

low side braking (see Low-Side Braking) or align brake (see Align Braking) through BRAKE_PIN_MODE.

MCF8316A decreases output speed to value defined by BRAKE_SPEED_THRESHOLD before entering

brake state. As long as BRAKE is driven 'High', MCF8316A stays in brake state. Brake pin input can be

overwritten by configuring BRAKE_INPUT over the I²C interface.

•

The DIR pin decides the direction of motor spin; when driven 'High', the sequence is OUT A → OUT B →

OUT C, and when driven 'Low' the sequence is OUT A → OUT C → OUT B. DIR pin input can be overwritten

by configuring DIR_INPUT over the I²C interface.

When DRVOFF pin is driven 'High', MCF8316A stops driving the motor by turning OFF all MOSFETs (coast

state). When DRVOFF is driven 'Low', MCF8316A returns to normal state of operation, as if it was restarting

the motor (see DRVOFF Functionality). DRVOFF does not cause the device to go to sleep or standby mode;

the digital core is still active. Entry and exit from sleep or standby condition is controlled by SPEED pin.

SPEED/WAKE pin is used to control motor speed and wake up MCF8316A from sleep mode. SPEED pin can

be configured to accept PWM, frequency or analog input signals. It is used to enter and exit from sleep and

standby mode (see Table 7-6).

•

External Oscillator and Watchdog Signals (Optional)

•

EXT_CLK pin may be used to provide an external clock reference (see External Clock Source ).

EXT_WD pin may be used to provide an external watchdog signal (see External Watchdog).

Output Signals

•

FG pin provides pulses which are proportional to motor speed (see FG Configuration).

nFAULT pin provides fault status in device or motor operation.

SOX pin provides the output of one of the current sense amplifiers.

7.3.2.2 I²C Interface

The MCF8316A supports an I²C serial communication interface that allows an external controller to send and

receive data. This I²C interface lets the external controller configure the EEPROM and read detailed fault and

motor state information. The I²C bus is a two-wire interface using the SCL and SDA pins which are described as

follows:

•

The SCL pin is the clock signal input.

The SDA pin is the data input and output.

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7.3.3 Step-Down Mixed-Mode Buck Regulator

The MCF8316A has an integrated mixed-mode buck regulator in conjunction with AVDD to supply regulated

3.3 V or 5 V power for an external controller or system voltage rail. Additionally, the buck output can also be

configured to 4 V or 5.7 V for supporting the extra headroom for external LDO for generating a 3.3 V or 5 V

supplies. The output voltage of the buck is set by BUCK_SEL.

The buck regulator has a low quiescent current of ~1-2 mA during light loads to prolong battery life. The device

improves performance during line and load transients by implementing a pulse-frequency current-mode control

scheme which requires less output capacitance and simplifies frequency compensation design.

Table 7-1. Recommended settings for Buck Regulator

Buck Mode

Buck output voltage Max output

Max output current Buck current limit

AVDD power

sequencing

current from AVDD from Buck (I_{BK_MAX}

)

(I_{AVDD_MAX}

)

Inductor - 47 μH

Inductor - 22 μH

Resistor - 22 Ω

3.3 V or 4 V

5 V or 5.7 V

3.3 V or 4 V

5 V or 5.7 V

3.3 V or 4 V

20 mA

170 mA - I_AVDD

20 mA - I_AVDD

10 mA - I_AVDD

600 mA (BUCK_CL = Not supported

0b)

(BUCK_PS_DIS = 1b)

20 mA

600 mA (BUCK_CL = Supported

0b)

(BUCK_PS_DIS = 0b)

150 mA (BUCK_CL = Not supported

1b)

(BUCK_PS_DIS = 1b)

150 mA (BUCK_CL = Supported

1b)

(BUCK_PS_DIS = 0b)

150 mA (BUCK_CL = Not supported

1b)

(BUCK_PS_DIS = 1b)

150 mA (BUCK_CL = Supported

1b)

(BUCK_PS_DIS = 0b)

7.3.3.1 Buck in Inductor Mode

The buck regulator in MCF8316A is primarily designed to support low inductance of 47-µH and 22-µH. A 47-µH

inductor allows the buck regulator to operate up to 170-mA load current support, whereas applications requiring

current up to 20-mA can use a 22-µH inductor which saves component size.

Figure 7-2 shows the connection of buck regulator in inductor mode.

VM

SW_BK

Ext. Load

V_BK

Control

L_BK

C_BK

GND_BK

FB_BK

Figure 7-2. Buck (Inductor Mode)

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7.3.3.2 Buck in Resistor mode

If the external load requirement is less than 10-mA, the inductor can be replaced with a resistor. In resistor mode

the power is dissipated across the external resistor and the efficiency is lower than buck in inductor mode.

Figure 7-3 shows the connection of buck in resistor mode.

VM

SW_BK

Ext. Load

V_BK

Control

R_BK

C_BK

GND_BK

FB_BK

Figure 7-3. Buck (Resistor Mode)

7.3.3.3 Buck Regulator with External LDO

The buck regulator also supports the voltage requirement to supply an external LDO to generate standard 3.3-V

or 5-V output rail with higher accuracies. The buck output voltage should be configured to 4-V or 5.7-V to provide

extra headroom to support the external LDO for generating 3.3-V or 5-V rail as shown in Figure 7-4. This allows

for a lower-voltage LDO design to save cost and better thermal management due to low drop-out voltage.

VM

V_LDO

(3.3V / 5V)

V_BK

SW_BK

(4V / 5.7V)

V_IN

V_LDO

Ext. Load

C_LDO

Control

L_BK

3.3V / 5V

LDO

C_BK

GND_BK

FB_BK

GND

External LDO

GND

Figure 7-4. Buck Regulator with External LDO

7.3.3.4 AVDD Power Sequencing from Buck Regulator

The AVDD LDO has an option of using the power supply from mixed mode buck regulator to reduce the

device power dissipation. The power sequencing mode allows on-the-fly changeover of AVDD LDO input from

DC mains (VM) to buck output (V_BK) as shown in Figure 7-5. This sequencing can be configured through the

BUCK_PS_DIS bit . Power sequencing is supported only when buck output voltage is set to 5-V or 5.7-V.

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VM

SW_BK

L_BK

Ext. Load

V_BK

Control

C_BK

GND_BK

FB_BK

BUCK_PS_DIS

V_BK

VM

AVDD LDO

REF

+

–

AVDD

AGND

External Load

C_AVDD

Figure 7-5. AVDD Power Sequencing from Mixed Mode Buck Regulator

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7.3.3.5 Mixed Mode Buck Operation and Control

The buck regulator implements a pulse frequency modulation (PFM) architecture with peak current mode control.

The output voltage of the buck regulator is compared with the internal reference voltage (V_{BK_REF}) which is

internally generated depending on the buck-output voltage setting (BUCK_SEL) which constitutes an outer

voltage control loop. Depending on the comparator output going high (V_BK< V_{BK_REF}) or low (V_BK> V_{BK_REF}),

the high-side power FET of the buck turns on and off respectively. An independent current control loop monitors

the current in high-side power FET (I_BK) and turns off the high-side FET when the current becomes higher than

the buck current limit (I_{BK_CL}). This implements a current limit control for the buck regulator. Figure 7-6 shows the

architecture of the buck and various control/protection loops.

SW_BK

I_BK

Ext. Load

V_BK

VM

L_BK

PWM Control

and Driver

C_BK

GND_BK

I_BK

+

Current Limit

OC Protection

UV Protection

_

I_{BK_CL}

I_BK

+

_

I_{BK_OCP}

FB_BK

V_BK

+

_

V_{BK_UVLO}

VM

V_BK

+

_

Voltage Control

V_{BK_REF}

Buck

Reference

Voltage

BUCK_SEL

Buck Control

Generator

Figure 7-6. Buck Operation and Control Loops

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7.3.3.6 Buck Undervoltage Protection

If at any time the voltage on the FB_BK pin (buck regulator output) falls lower than the V_{BK_UVLO}threshold,

both the high-side and low-side MOSFETs of the buck regulator are disabled . MCF8316A goes into reset state

whenever buck UV event occurs, since the internal circuitry in MCF8316A is powered from the buck regulator

output.

7.3.3.7 Buck Overcurrent Protection

The buck overcurrent event is sensed by monitoring the current flowing through high-side MOSFET of the buck

regulator. If the current through the high-side MOSFET exceeds the I_{BK_OCP}threshold for a time longer than the

deglitch time (t_{OCP_DEG}), a buck OCP event is recognized. MCF8316A goes into reset state whenever buck OCP

event occurs, since the internal circuitry in MCF8316A is powered from the buck regulator output.

7.3.4 AVDD Linear Voltage Regulator

A 3.3-V, linear regulator is integrated into the MCF8316A and is available for use by external circuitry. The AVDD

LDO regulator is used for powering up the internal circuitry of the device and additionally, this regulator can also

provide the supply voltage for a low-power MCU or other circuitry supporting low current (up to 20-mA). The

output of the AVDD regulator should be bypassed near the AVDD pin with a X5R or X7R, 1-µF, 6.3-V ceramic

capacitor routed directly back to the adjacent AGND ground pin.

The AVDD nominal, no-load output voltage is 3.3-V.

FB_BK

BUCK_PS_DIS

V_BK

VM

REF

+

–

AVDD

AGND

External Load

C_AVDD

Figure 7-7. AVDD Linear Regulator Block Diagram

Use Equation 1 to calculate the power dissipated in the device by the AVDD linear regulator with VM as supply

(BUCK_PS_DIS = 1b)

2 = (8_8/F 8_#8&&) × +_#8&&

(1)

For example, at a V_VMof 24-V, drawing 20-mA out of AVDD results in a power dissipation as shown in Equation

2.

P = 24 V - 3.3 V ì 20 mA = 414 mW

(

)

(2)

Use Equation 3 to calculate the power dissipated in the device by the AVDD linear regulator with buck output as

supply (BUCK_PS_DIS = 0b)

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P =

V

− V

× I

(3)

FB_BK

AVDD AVDD

7.3.5 Charge Pump

Since the output stages use N-channel FETs, the device requires a gate-drive voltage higher than the VM power

supply to turn-on the high-side FETs. The MCF8316A integrates a charge-pump circuit that generates a voltage

above the VM supply for this purpose.

The charge pump requires two external capacitors(C_CP, C_FLY) for operation. See the block diagram and pin

descriptions for details on these capacitors (value, connection, and so forth).

VM

C_CP

CP

CPH

VM

Charge

Pump

Control

C_FLY

CPL

Figure 7-8. Charge Pump

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7.3.6 Slew Rate Control

An adjustable gate-drive current control for the MOSFETs in the output stage is provided to achieve configurable

slew rate for EMI mitigation. The MOSFET VDS slew rate is a critical factor for optimizing radiated emissions,

total energy and duration of diode recovery spikes and switching voltage transients related to parasitic elements

of the PCB. This slew rate is predominantly determined by the control of the internal MOSFET gate current as

shown in Figure 7-9.

VM

VCP (Internal)

Slew Rate

Control

OUTx

VCP (Internal)

Slew Rate

Control

GND

Figure 7-9. Slew Rate Circuit Implementation

The slew rate of each half-bridge can be adjusted through SLEW_RATE settings. Slew rate can be configured as

25-V/µs, 50-V/µs, 125-V/µs or 200-V/µs. The slew rate is calculated by the rise-time and fall-time of the voltage

on OUTx pin as shown in Figure 7-10.

V_OUTx

VM

80%

20%

0

Time

t_fall

t_rise

Figure 7-10. Slew Rate Timings

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7.3.7 Cross Conduction (Dead Time)

The device is fully protected against any cross conduction of the MOSFETs. The high-side and low-side

MOSFETs are carefully controlled to avoid any shoot-through events by inserting a dead time (t_dead). This is

implemented by sensing the gate-source voltage (VGS) of the high-side and low-side MOSFETs and ensuring

that the VGS of high-side MOSFET has reached below turn-off levels before switching on the low-side MOSFET

of same half-bridge as shown in Figure 7-11 and Figure 7-12 and vice versa.

VM

Gate

Control

+

VGS

VGS_HS

VGS_LS

–

OUTx

t_DEAD

Gate

Control

+

GND

VGS

–

Figure 7-11. Cross Conduction Protection

OUTx HS

OUTx

Gate

(VGS_HS)

10%

t_DEAD

OUTx

Gate

(VHS_LS)

10%

OUTx LS

Time

Figure 7-12. Dead Time

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7.3.8 SPEED Control

The MCF8316A offers four methods of directly controlling the speed of the motor. The speed control method is

configured by SPEED_MODE. The speed command can be controlled in one of the following four ways.

•

PWM input on SPEED pin by varying duty cycle of input signal

Frequency input on SPEED pin by varying frequency of input signal

Analog input on SPEED pin by varying amplitude of input signal

Over I²C by configuring DIGITAL_SPEED_CTRL register

The speed can also be indirectly controlled by varying the supply voltage (V_M).

Freq based

Freq

Duty

PWM

PWM Duty

ADC

SPEED Pin

Speed

Profiles

Close Loop

FOC

DUTY

CMD

SPEED

REF

Analog

DUTY

OUT

FETs

PWM

I²C

Figure 7-13. Multiplexing the Speed Command

The signal path from SPEED pin input (or I²C based speed input) to output duty cycle (DUTY OUT) applied to

FETs is shown in Figure 7-13.

Note

1. Any duty command (DUTY CMD from SPEED pin or I²C) or speed reference (SPEED REF from

speed profiles) value set to < 1% will result in speed reference (SPEED REF) being clamped to

zero and motor to be in stopped state.

2. If MAX_SPEED is set to 0, SPEED REF is clamped to zero (irrespective of DUTY CMD) and

motor is in stopped state.

7.3.8.1 Analog-Mode Speed Control

Analog input based speed control can be configured by setting SPEED_MODE to 00b. In this mode, the duty

command (DUTY CMD) varies with the analog voltage input on the SPEED pin(V_SPEED). When 0 < V_SPEED

<

V_{EN_SB}, DUTY CMD is set to zero and the motor is stopped. When V_{EN_SB}< V_SPEED< V_{ANA_FS}, DUTY CMD

varies linearly with V_SPEEDas shown in Figure 7-14 . When V_SPEED> V_{ANA_FS}, DUTY CMD is clamped to 100%.

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DUTY CMD

100%

Analog Speed Input

V_{EN_SB}

V_{ANA_FS}

0

Figure 7-14. Analog-Mode Speed Control

7.3.8.2 PWM-Mode Speed Control

PWM based speed control can be configured by setting SPEED_MODE to 01b. In this mode, the PWM duty

cycle applied to the SPEED pin can be varied from 0 to 100% and duty command (DUTY CMD) varies

linearly with the applied PWM duty cycle. DUTY CMD is set to zero and the motor is stopped when the

PWM signal at SPEED pin stays < V_{DIG_IL}for longer than t_{EN_SB_PWM}. The frequency of the PWM input signal

applied to the SPEED pin is defined as f_PWMand the range for this frequency can be configured through

SPEED_RANGE_SEL.

Note

f_PWMis the frequency of the PWM signal the device can accept at SPEED pin to control motor speed.

It does not correspond to the PWM output frequency that is applied to the motor phases. The PWM

output frequency can be configured through PWM_FREQ_OUT (see Section 7.3.15).

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DUTY CMD

100%

PWM Duty Input

100%

0

Figure 7-15. PWM-Mode Speed Control

7.3.8.3 I²C based Speed Control

I²C based serial interface can be used for speed control by setting SPEED_MODE to 10b. In this mode,

the duty command can be written directly into DIGITAL_SPEED_CTRL register and the SPEED pin can

be independently used to control the sleep entry and exit. If SPEED pin input is < V_{EN_SL}for a time

longer than SLEEP_ENTRY_TIME, MCF8316A enters sleep state irrespective of the I²C duty command in

DIGITAL_SPEED_CTRL register. When SPEED pin > V_{EX_SL}, MCF8316A exits sleep state and speed is

controlled through DIGITAL_SPEED_CTRL register. If DIGITAL_SPEED_CTRL register is set to 0 and SPEED

pin > V_{EX_SL}, MCF8316A is in standby state.

7.3.8.4 Frequency-Mode Speed Control

Frequency based speed control is configured by setting SPEED_MODE to 11b. In this mode, duty command

varies linearly as a function of the frequency of the square wave input at SPEED pin as given in Equation 4.

Input frequency greater than INPUT_MAXIMUM_FREQ clamps the duty command to 100%. The duty command

is set to zero and the motor is stopped when the frequency signal at SPEED pin stays < V_{DIG_IL}for longer than

t_{EN_SB_FREQ}

.

Duty command = Frequency at SPEED pin / INPUT_MAXIMUM_FREQ * 100

(4)

7.3.8.5 Speed Profiles

MCF8316A supports three different kinds of speed profiles(linear, step, forward-reverse) to enable a variety

of end-user applications. The different speed profiles can be configured through SPEED_PROFILE_CONFIG.

When SPEED_PROFILE_CONFIG is set to 00b, the speed reference is the same as the duty command.

7.3.8.5.1 Linear Speed Profiles

Note

For all types of speed profiles, duty command = 0 stops the motor irrespective of the speed profile

register settings.

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SPEED_REF

SPEED_CLAMP2

SPEED_E

SPEED_D

SPEED_C

SPEED_B

SPEED_A

SPEED_CLAMP1

SPEED_OFF1

SPEED_OFF2

DUTY_CMD

DUTY_A

DUTY_E DUTY_CLAMP2 DUTY_ON2

DUTY_OFF2

DUTY_OFF1 DUTY_ON1 DUTY_CLAMP1

DUTY_B

DUTY_C DUTY_D

Figure 7-16. Linear Speed Profiles

Linear speed profiles can be configured by setting SPEED_PROFILE_CONFIG to 01b. Linear speed profiles

feature speed references which change linearly between SPEED_CLAMP1 and SPEED_CLAMP2 with different

slopes which can be set by configuring DUTY_x and SPEED_x combination.

•

DUTY_ON1 configures the duty command above which MCF8316A starts driving the motor (to speed

reference set by SPEED_CLAMP1) when the current speed reference is zero. When current speed reference

is zero and duty command is below DUTY_ON1, MCF8316A continues to be in off state and motor is

stationary.

•

DUTY_OFF1 configures the duty command below which the speed reference changes to SPEED_OFF1,

if SPEED_OFF1 > SPEED_CLAMP1. If SPEED_OFF1 < SPEED_CLAMP1, speed reference is set to

SPEED_CLAMP1.

•

DUTY_CLAMP1 configures the duty command till which speed reference will be constant. SPEED_CLAMP1

configures this constant speed reference between between DUTY_OFF1 and DUTY_CLAMP1.

DUTY_A configures the duty command for speed reference SPEED_A. The speed reference changes

linearly between DUTY_CLAMP1 and DUTY_A.

DUTY_B configures the duty command for speed reference SPEED_B. The speed reference changes

linearly between DUTY_A and DUTY_B.

DUTY_C configures the duty command for speed reference SPEED_C. The speed reference changes

linearly between DUTY_B and DUTY_C.

DUTY_D configures the duty command for speed reference SPEED_D. The speed reference changes

linearly between DUTY_C and DUTY_D.

DUTY_E configures the duty command for speed reference SPEED_E. The speed reference changes

linearly between DUTY_D and DUTY_E.

DUTY_CLAMP2 configures the duty command above which the speed reference will be constant at

SPEED_CLAMP2. SPEED_CLAMP2 configures this constant speed reference between DUTY_CLAMP2 and

DUTY_OFF2 . The speed reference changes linearly between DUTY_E and DUTY_CLAMP2.

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•

DUTY_ON2 configures the duty command below which MCF8316A starts driving the motor (to speed

reference set by SPEED_CLAMP2) when the current speed reference is zero. When current speed reference

is zero and duty command is above DUTY_ON1, MCF8316A continues to be in off state and motor is

stationary.

•

DUTY_OFF2 configures the duty command above which the speed reference will change from

SPEED_CLAMP2 to SPEED_OFF2.

7.3.8.5.2 Staircase Speed Profiles

SPEED_REF

SPEED_CLAMP2

SPEED_E

SPEED_D

SPEED_C

SPEED_B

SPEED_A

SPEED_CLAMP1

SPEED_OFF2

DUTY_CMD

SPEED_OFF1

DUTY_A

DUTY_E

DUTY_CLAMP2 DUTY_ON2 DUTY_OFF2

DUTY_OFF1 DUTY_ON1 DUTY_CLAMP1

DUTY_B

DUTY_C DUTY_D

Figure 7-17. Staircase Speed Profiles

Staircase speed profiles can be configured by setting SPEED_PROFILE_CONFIG to b10. Staircase speed

profiles feature speed changes in steps between SPEED_CLAMP1 and SPEED_CLAMP2. DUTY_x and

SPEED_x configures the speed and duty command at which the step is increased

•

DUTY_ON1 configures the duty command above which MCF8316A starts driving the motor (to speed

reference set by SPEED_CLAMP1) when the current speed reference is zero. When current speed reference

is zero and duty command is below DUTY_ON1, MCF8316A continues to be in off state and motor is

stationary.

•

DUTY_OFF1 configures the duty command below which the speed reference changes from

SPEED_CLAMP1 to SPEED_OFF1, if SPEED_OFF1 > SPEED_CLAMP1. If SPEED_OFF1 <

SPEED_CLAMP1, speed reference is set to SPEED_CLAMP1.

•

DUTY_CLAMP1 configures the duty command till which speed reference will be constant. SPEED_CLAMP1

configures this constant speed reference between DUTY_OFF1 and DUTY_CLAMP1.

DUTY_A configures the duty command for speed reference SPEED_A. There is a step change in speed

reference from SPEED_CLAMP1 to SPEED_A at DUTY_CLAMP1.

DUTY_B configures the duty command for speed reference SPEED_B. There is a step change in speed

reference from SPEED_A to SPEED_B at DUTY_A.

DUTY_C configures the duty command for speed reference SPEED_C. There is a step change in speed

reference from SPEED_B to SPEED_C at DUTY_B.

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•

DUTY_D configures the duty command for speed reference SPEED_D. There is a step change in speed

reference from SPEED_C to SPEED_D at DUTY_C.

DUTY_E configures the duty command for speed reference SPEED_E. There is a step change in speed

reference from SPEED_D to SPEED_E at DUTY_D.

DUTY_CLAMP2 configures the duty command above which the speed reference will be constant at

SPEED_CLAMP2. SPEED_CLAMP2 configures this constant speed reference between DUTY_CLAMP2 and

DUTY_OFF2. There is a step change in speed reference from SPEED_E to SPEED_CLAMP2 at DUTY_E.

DUTY_ON2 configures the duty command below which MCF8316A starts driving the motor (to speed

reference set by SPEED_CLAMP2) when the current speed reference is zero. When current speed reference

is zero and duty command is above DUTY_ON1, MCF8316A continues to be in off state and motor is

stationary.

•

DUTY_OFF2 configures the duty command above which the speed reference will change from

SPEED_CLAMP2 to SPEED_OFF2.

7.3.8.5.3 Forward-Reverse Speed Profiles

SPEED_REF

Forward Direction

Reverse Direction

OUT C OUT B

OUT A

OUT B

OUT C

OUT A

SPEED_CLAMP2

SPEED_A

SPEED_D

SPEED_CLAMP1

SPEED_OFF2

DUTY_CMD

SPEED_OFF1

DUTY_C

DUTY_E

DUTY_CLAMP2 DUTY_ON2 DUTY_OFF2

DUTY_OFF1 DUTY_ON1 DUTY_CLAMP1

DUTY_A DUTY_B

DUTY_D

Figure 7-18. Forward Reverse Speed Profiles

Forward-Reverse speed profiles can be configured by setting SPEED_PROFILE_CONFIG to b11. Forward-

Reverse speed profiles feature direction change through adjusting the duty command. DUTY_C configures duty

command at which the direction will be changed. The Forward-Reverse speed profile can be used to eliminate

the separate signal used to control the motor direction.

•

DUTY_ON1 configures the duty command above which MCF8316A starts driving the motor in the forward

direction (to speed reference set by SPEED_CLAMP1) when the current speed reference is zero. When

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current speed reference is zero and duty command is below DUTY_ON1, MCF8316A continues to be in off

state and motor is stationary.

•

DUTY_OFF1 configures the duty command below which the speed reference changes in the forward

direction from SPEED_CLAMP1 to SPEED_OFF1, if SPEED_OFF1 > SPEED_CLAMP1. If SPEED_OFF1

< SPEED_CLAMP1, speed reference is set to SPEED_CLAMP1.

DUTY_CLAMP1 configures the duty command at which speed reference will be the constant in

forward direction. SPEED_CLAMP1 configures constant speed reference between DUTY_CLAMP1 and

DUTY_OFF1.

•

DUTY_A configures the duty command for speed reference SPEED_A. The speed reference changes

linearly between DUTY_CLAMP1 and DUTY_A.

DUTY_B configures the duty command above which MCF8316A will be in off state. The speed reference

remains constant at SPEED_A between DUTY_A and DUTY_B.

•

DUTY_C configures the duty command at which the direction is changed

DUTY_D configures the duty command above which the MCF8316A will be in running state in the reverse

direction. SPEED_D configures constant speed reference between DUTY_D and DUTY_E.

DUTY_CLAMP2 configures the duty command above which speed reference will be constant at

SPEED_CLAMP2 in reverse direction. The speed reference changes linearly between DUTY_E and

DUTY_CLAMP2.

DUTY_ON2 configures the duty command below which MCF8316A starts driving the motor in the reverse

direction (to speed reference set by SPEED_CLAMP2) when the current speed reference is zero. When

current speed reference is zero and duty command is above DUTY_ON1, MCF8316A continues to be in off

state and motor is stationary.

•

DUTY_OFF2 configures the duty command above which the speed reference changes in the reverse

direction from SPEED_CLAMP2 to SPEED_OFF2.

7.3.9 Starting the Motor Under Different Initial Conditions

The motor can be in one of three states when MCF8316A begins the start-up process. The motor may be

stationary, spinning in the forward direction, or spinning in the reverse direction. The MCF8316A includes a

number of features to allow for reliable motor start-up under all of these conditions. Figure 7-19 shows the motor

start-up flow for each of the three initial motor states.

Brake

Align

Double Align

Sta onary

IPD

Slow rst cycle

Open Loop

Spinning in forward

direc on

Closed Loop

Coast (Hi-Z)

Brake

Spinning in reverse

direc on

Reverse Drive

Figure 7-19. Starting the motor under different initial conditions

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Note

"Forward" means "spinning in the same direction as the commanded direction", and "Reverse" means

"spinning in the opposite direction as the commanded direction".

7.3.9.1 Case 1 – Motor is Stationary

If the motor is stationary, the commutation must be initialized to be in phase with the position of the motor. The

MCF8316A provides various options to initialize the commutation logic to the motor position and reliably start the

motor.

•

The align and double align techniques force the motor into alignment by applying a voltage across a

particular motor phase to force the motor to rotate in alignment with this phase.

Initial position detect (IPD) determines the position of the motor based on the deterministic inductance

variation, which is often present in BLDC motors.

The slow first cycle method starts the motor by applying a low frequency cycle to align the rotor position to

the applied commutation by the end of one electrical rotation.

MCF8316A also provides a configurable brake option to ensure the motor is stationary before initiating one of

the above start-up methods. Device enters open loop acceleration after going through the configured start-up

method.

7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction

If the motor is spinning forward (same direction as the commanded direction) with sufficient speed (BEMF), the

MCF8316A resynchronizes with the spinning motor and continues commutation by going directly to closed loop

operation. If the motor speed is too low for closed loop operation, MCF8316A enters open loop operation

to accelerate the motor till it reaches sufficient speed to enter closed loop operation. By resynchronizing

to the spinning motor, the user achieves the fastest possible start-up time for this initial condition. This

resynchronization feature can be enabled or disabled through RESYNC_EN. If resynchronization is disabled,

the MCF8316A can be configured to wait for the motor to coast to a stop and/or apply a brake. After the motor

has stopped spinning, the motor start-up sequence proceeds as in Case 1, considering the motor is stationary.

7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction

If the motor is spinning in the reverse direction (the opposite direction as the commanded direction), the

MCF8316A provides several methods to change the direction and drive the motor to the target speed reference

in the commanded direction.

The reverse drive method allows the motor to be driven so that it decelerates through zero speed. The motor

achieves the shortest possible spin-up time when spinning in the reverse direction.

If reverse drive is not enabled, then the MCF8316A can be configured to wait for the motor to coast to a stop

and/or apply a brake. After the motor has stopped spinning, the motor start-up sequence proceeds as in Case 1,

considering the motor is stationary.

Note

Take care when using the reverse drive or brake feature to ensure that the current is limited to an

acceptable level and that the supply voltage does not surge as a result of energy being returned to the

power supply.

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7.3.10 Motor Start Sequence (MSS)

Figure 7-20 shows the motor-start sequence implemented in the MCF8316A device.

Power On

DIR Change &&

DIR_CHANGE_MODE = 0b

N

ISD_EN

Y

Is motor

sta onary

N

Reverse

Forward

N

Direc on of

Spin

DIR Change &&

DIR_CHANGE_MODE = 1b

N

RVS_DR_EN

Y

RESYNC_EN

Y

HIZ_EN

N

Y

Speed > Open to

Closed Loop Hando

(Reverse)

Hi-Z

N

Speed > Open to

Closed Loop Hando

(Resync)

N

Time >

HIZ_TIME

Y

N

Y

Reverse Closed

Loop Decelera on

N

BRAKE_EN

Reverse

Open Loop

Y

Decelera on

Brake

N

Time >

BRK_TIME

Direc on

Reversal : Zero

Speed

Y

Crossover

Motor Start-up

Open loop

Closed Loop

Figure 7-20. Motor Starting-up Flow

Power-On State

This is the initial state of the Motor Start Sequence (MSS). The MSS starts in

this state on initial power-up or whenever the MCF8316A device comes out of

standby or sleep mode.

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DIR Change &&

In MCF8316A, if direction change command is detected and

DIR_CHANGE_MODE = 0b DIR_CHANGE_MODE is set to 0b during any state (including closed loop), the

Judgement

device re-starts the MSS.

ISD_EN Judgement

After power-on, the MCF8316A MSS enters the ISD_EN judgement where it

checks to see if the initial speed detect (ISD) function is enabled (ISD_EN = 1b).

If ISD is disabled, the MSS proceeds directly to the BRAKE_EN judgement. If

ISD is enabled, MSS advances to the ISD (Is Motor Stationary) state.

ISD State

The MSS determines the initial condition (speed, direction of spin) of the motor

(see Initial Speed Detect (ISD)). If motor is deemed to be stationary (motor BEMF

< STAT_DETECT_THR), the MSS proceeds to BRAKE_EN judgement. If the

motor is not stationary, MSS proceeds to verify the direction of spin.

Direction of Spin

Judgement

The MSS determines whether the motor is spinning in the forward or the

reverse direction. If the motor is spinning in the forward direction, the MCF8316A

proceeds to the RESYNC_EN judgement. If the motor is spinning in the reverse

direction, the MSS proceeds to the RVS_DR_EN judgement.

RESYNC_EN Judgement

If RESYNC_EN is set to 1b, MCF8316A proceeds to Speed > Open to Closed

Loop Handoff (Resync) judgement. If RESYNC_EN is set to 0b, MSS proceeds to

HIZ_EN judgement.

Speed > Open to Closed

Loop Handoff (Resync)

Judgement

If motor speed > OPN_CL_HANDOFF_THR, MCF8316A uses the speed and

position information from the ISD state to transition to the closed loop state (see

Motor Resynchronization ) directly. If motor speed < OPN_CL_HANDOFF_THR,

MCF8316A transitions to open loop state.

RVS_DR_EN Judgement

The MSS checks to see if the reverse drive function is enabled (RVS_DR_EN =

1). If it is enabled, the MSS transitions to check speed of the motor in reverse

direction. If the reverse drive function is not enabled, the MSS advances to the

HIZ_EN judgement.

Speed > Open to Closed

Loop Handoff (Reverse)

Judgement

The MSS checks to see if the reverse speed is high enough for MCF8316A to

decelerate in closed loop. Till the speed (in reverse direction) is high enough,

MSS stays in reverse closed loop deceleration. If speed is too low, then the MSS

transitions to reverse open loop deceleration.

Reverse Closed Loop,

The MCF8316A resynchronizes in the reverse direction, decelerates the motor

Open Loop Deceleration

in closed loop till motor speed falls below the handoff threshold. (see Reverse

and Zero Speed Crossover Drive). When motor speed in reverse direction is too low, the MCF8316A

switches to open-loop, decelerates the motor in open-loop, crosses zero speed,

and accelerates in the forward direction in open-loop before entering closed loop

operation after motor speed is sufficiently high.

HIZ_EN Judgement

The MSS checks to determine whether the coast (Hi-Z) function is enabled

(HIZ_EN =1). If the coast function is enabled, the MSS advances to the coast

routine. If the coast function is disabled, the MSS advances to the BRAKE_EN

judgement.

Coast (Hi-Z) Routine

The device coasts the motor by turning OFF all six MOSFETs for a certain time

configured by HIZ_TIME.

BRAKE_EN Judgement

The MSS checks to determine whether the brake function is enabled

(BRAKE_EN =1). If the brake function is enabled, the MSS advances to the

brake routine. If the brake function is disabled, the MSS advances to the motor

start-up state (see Section 7.3.10.4).

Brake Routine

MCF8316A implements a brake by turning on all three (high-side or low-side)

MOSFETS for BRK_TIME. Brake is applied either using high-side or low-side

MOSFETs based on BRK_MODE configuration.

Closed Loop State

In this state, the MCF8316A drives the motor with FOC.

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7.3.10.1 Initial Speed Detect (ISD)

The ISD function is used to identify the initial condition of the motor and is enabled by setting ISD_EN to 1b. The

initial speed, position and direction is determined by sampling the phase voltage through the internal ADC. ISD

can be disabled by setting ISD_EN to 0b. If the function is disabled (ISD_EN set to 0b), the MCF8316A does not

perform the initial speed detect function and proceeds to check if the brake routine (BRAKE_EN) is enabled.

7.3.10.2 Motor Resynchronization

The motor resynchronization function works when the ISD and resynchronization functions are both enabled

and the device determines that the initial state of the motor is spinning in the forward direction (same direction

as the commanded direction). The speed and position information measured during ISD are used to initialize

the drive state of the MCF8316A, which can transition directly into closed loop (or open loop if motor speed

is not sufficient for closed loop operation) state without needing to stop the motor. In the MCF8316A, motor

resynchronization can be enabled/disabled through RESYNC_EN bit. If motor resynchronization is disabled, the

device proceeds to check if the motor coast (Hi-Z) routine is enabled.

7.3.10.3 Reverse Drive

The MCF8316A uses the reverse drive function to change the direction of the motor rotation when ISD_EN

and RVS_DR_EN are both set to 1b and the ISD determines the motor spin direction to be opposite to that of

the commanded direction. Reverse drive includes synchronizing with the motor speed in the reverse direction,

reverse decelerating the motor through zero speed, changing direction, and accelerating in open loop in forward

(or commanded) direction until the device transitions into closed loop in forward direction (see Figure 7-21). .

MCF8316A provides the option of using the forward direction parameters or a separate set of reverse drive

parameters by configuring REV_DRV_CONFIG.

Speed

Close loop

Handoff to close loop

Open loop

Time

Handoff to open loop

Open Loop

Reverse Deceleration

Figure 7-21. Reverse Drive Function

7.3.10.3.1 Reverse Drive Tuning

MCF8316A provides the option of tuning the open to closed loop handoff threshold, open loop acceleration

(and deceleration) rates and open loop current limit in reverse drive to values different to those used in forward

drive operation; the reverse drive specific parameters can be used by setting REV_DRV_CONFIG to 1b. If

REV_DRV_CONFIG is set to 0b, MCF8316A uses the equivalent parameters configured for forward drive

operation during the reverse drive operation too.

The speed at which motor would enter the open loop in reverse direction can be configured using

REV_DRV_HANDOFF_THR. For a smooth transition without jerks or loss of synchronism, user can

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configure an appropriate current limit when the motor is spinning in open loop during speed reversal using

REV_DRV_OPEN_LOOP_CURRENT. The open loop acceleration rates for the forward direction during speed

reversal are defined using REV_DRV_OPEN_LOOP_ACCEL_A1 and REV_DRV_OPEN_LOOP_ACCEL_A2.

The reverse drive open loop deceleration rate, when the motor is decelerating in the opposite direction

to zero speed, can be configured as a percentage of reverse drive open loop acceleration using

REV_DRV_OPEN_LOOP_DEC.

7.3.10.4 Motor Start-up

There are different options available for motor start-up from a stationary position and these options can be

configured by MTR_STARTUP. In align and double align mode, the motor is aligned to a known position by

injecting a DC current. In IPD mode, the rotor position is estimated by applying 6 different high-frequency pulses.

In slow first cycle mode, the motor is started by applying a low frequency cycle.

7.3.10.4.1 Align

Align is enabled by configuring MTR_STARTUP to 00b. The MCF8316A aligns the motor by injecting a DC

current through a particular phase pattern for a certain time configured by ALIGN_TIME. The phase pattern

during align is generated based on ALIGN_ANGLE. In the MCF8316A, the current limit during align is configured

through ALIGN_OR_SLOW_CURRENT LIMIT.

A fast change in the phase current may result in a sudden change in the driving torque and this could result in

acoustic noise. To avoid this, the MCF8316A ramps up the current from 0 to the current limit at a configurable

ramp rate set by ALIGN_SLOW_RAMP_RATE. At the end of align routine the motor, will be aligned at the known

position.

7.3.10.4.2 Double Align

Double align is enabled by configuring MTR_STARTUP to 01b. Single align is not reliable when the initial

position of the rotor is 180^oout of phase with the applied phase pattern. In this case, it is possible to have

start-up failures using single align. In order to improve the reliabilty of align based start-up, the MCF8316A

provides the option of double align start-up. In double align start-up, MCF8316A uses a phase pattern for the

second align that is 90^oahead of the first align phase pattern. In double align, relevant parameters like align

time, current limit, ramp rate are the same as in the case of single align - two different phase patterns are applied

in succession with the same parameters to ensure that the motor will be aligned to a known position irrespective

of initial rotor position.

7.3.10.4.3 Initial Position Detection (IPD)

Initial Position Detection (IPD) can be enabled by configuring MTR_STARTUP to 10b. In IPD, inductive sense

method is used to determine the initial position of the motor using the spatial variation in the motor inductance.

Align or double align may result in the motor spinning in the reverse direction before starting open loop

acceleration. IPD can be used in such applications where reverse rotation of the motor is unacceptable. IPD

does not wait for the motor to align with the commutation and therefore can allow for a faster motor start-up

sequence. IPD works well when the inductance of the motor varies as a function of position. IPD works by

pulsing current in to the motor and hence can generate acoustics which must be taken into account when

determining the best start-up method for a particular application.

7.3.10.4.3.1 IPD Operation

IPD operates by sequentially applying six different phase patterns according to the following sequence:

BC-> CB-> AB-> BA-> CA-> AC (see Figure 7-22). When the current reaches the threshold configured by

IPD_CURR_THR, the MCF8316A stops driving the particular phase pattern and measures the time taken to

reach the current threshold from when the particular phase pattern was applied. Thus, the time taken to reach

IPD_CURR_THR is measured for all six phase patterns - this time varies as a function of the inductance in

the motor windings. The state with the shortest time represents the state with the minimum inductance. The

minimum inductance is because of the alignment of the north pole of the motor with this particular driving state.

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A

B

IPD_CLK

Clock

C

Drive

B C

C B

A B

B A

C A

A C

IPD_CURR_THR

Current

Search the Minimum Time

Minimum

Time

Smallest

Inductance

Saturation Position of

the Magnetic Field

Permanent

Magnet Position

Figure 7-22. IPD Function

7.3.10.4.3.2 IPD Release Mode

Two modes are available for configuring the way the MCF8316A stops driving the motor when the current

threshold is reached. The recirculate (or brake) mode is selected if IPD_RLS_MODE = 0b. In this configuration,

the low-side (LSC) MOSFET remains ON to allow the current to recirculate between the MOSFET (LSC) and

body diode (LSA) (see Figure 7-23). Hi-Z mode is selected if IPD_RLS_MODE = 1b. In Hi-Z mode, both the

high-side (HSA) and low-side (LSC) MOSFETs are turned OFF and the current recirculates through the body

diodes back to the power supply (see Figure 7-24).

In the Hi-Z mode, the phase current has a faster settle-down time, but that can result in a voltage increase on

V_M. The user must manage this with an appropriate selection of either a clamp circuit or by providing sufficient

capacitance between V_Mand GND to absorb the energy. If the voltage surge cannot be contained or if it is

unacceptable for the application, recirculate mode must be used. When using the recirculate mode, select the

IPD_CLK_FREQ appropriately to give the current in the motor windings enough time to decay to to 0-A before

the next IPD phase pattern is applied.

HSB

HSC

LSC

HSA

VM

LSA

HSB

LSB

HSC

LSC

HSA

VM

LSA

M

LSB

Driving

Brake (Recirculate)

Figure 7-23. IPD Release Mode 0

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HSB

HSC

LSC

HSA

VM

LSA

HSB

HSC

LSC

HSA

VM

LSA

M

LSB

Driving

Hi-Z (Tri-State)

Figure 7-24. IPD Release Mode 1

7.3.10.4.3.3 IPD Advance Angle

After the initial position is detected, the MCF8316A begins driving the motor in open loop at an angle specified

by IPD_ADV_ANGLE.

Advancing the drive angle anywhere from 0° to 180° results in positive torque. Advancing the drive angle by

90° results in maximum initial torque. Applying maximum initial torque could result in uneven acceleration to the

rotor. Select the IPD_ADV_ANGLE to allow for smooth acceleration in the application (see Figure 7-25).

Motor spinning direction

A

B

C

B

A

B

A

B

A

B

C

30 advance

90 advance

120 advance

60 advance

Figure 7-25. IPD Advance Angle

7.3.10.4.4 Slow First Cycle Startup

Slow First Cycle start-up is enabled by configuring MTR_STARTUP to 11b. In slow first cycle start-up, the

MCF8316A starts motor commutation at a frequency defined by SLOW_FIRST_CYCLE_FREQ. The frequency

configured is used only for first cycle, and then the motor commutation follows acceleration profile configured by

open loop acceleration coefficients A1 and A2. The slow first cycle frequency has to be configured to be slow

enough to allow motor to synchronize with the commutation sequence. This mode is useful when fast startup is

desired as it significantly reduces the align time.

7.3.10.4.5 Open loop

Upon completing the motor position initialization with either align, double align, IPD or slow first cycle, the

MCF8316A begins to accelerate the motor in open loop. During open loop, the speed is increased with a fixed

current limit. In open loop, the control PI loops for I_qand I_dactively control the currents. The angle during open

loop is provided from the ramp generator as shown in Figure 7-26

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User Set

Current

I_limit

Accelera on

Control and

Limit

Speed Pro les

SW1

I_limit

I_q_ref

SPEED_REF

DUTY_CMD

VM

0

Torque

Controller

V_q

V_d

V_a

V_b

V_c

Speed

Loop

V

Inverse

Clarke/

SVM

0

Inverse

Park

Speed_meas

I_d_ref = 0

Flux

Controller

Open Loop Ramp

gen

SW2

Generator (Coe

A1 and A2)

I_a

I_d

I_q

I

I_b

I_c

Park

Clarke

est

I

Back-EMF

Observer

V

Figure 7-26. Open Loop

In MCF8316A, the current limit threshold is configured through OL_ILIMIT_CONFIG and is set by ILIMIT

or OL_ILIMIT based on configuration of OL_ILIMIT_CONFIG. The function of the open-loop operation is to

drive the motor to a speed at which the motor generates sufficient BEMF to allow the back-EMF observer to

accurately detect the position of the rotor. The motor is accelerated in open loop and speed at any given time is

determined by Equation 5. In MCF8316A, open loop acceleration coefficients, A1 and A2 are configured through

OL_ACC_A1 and OL_ACC_A2 respectively.

Speed(t) = A1 * t + 0.5 * A2 * t²

(5)

7.3.10.4.6 Transition from Open to Closed Loop

Once the motor has reached a sufficient speed for the back-EMF observer to estimate the angle and speed

of the motor, the MCF8316A transitions into closed loop state. This handoff speed is automatically determined

based on the measured back-EMF and motor speed. Users also have an option to manually set the handoff

speed by configuring OPN_CL_HANDOFF_THR and setting AUTO_HANDOFF_EN to 0b. In order to have

smooth transition and avoid speed transients, the theta_error (Ɵ_gen- Ɵ_est) is decreased linearly after transition.

The ramp rate of theta_error reduction can be configured using THETA_ERROR_RAMP_RATE. If the current

limit set during the open loop is high and if it is not reduced before transition to closed loop, the motor speed

may momentarily rise to higher values than SPEED_REF after transition into closed loop. In order to avoid such

speed variations, configure the IQ_RAMP_EN to 1b, so that i_{q_ref}decreases prior to transition into closed loop.

However if the final speed reference (SPEED_REF) is more than two times the open loop to closed loop hand

off speed (OPN_CL_HANDOFF_THR), then i_{q_ref}is not decreased independent of the IQ_RAMP_EN setting, to

enable faster motor acceleration.

After hand off to closed loop at a sufficient speed, there could be still some theta error, as the estimators may not

be fully aligned. A slow acceleration can be used after the open loop to closed loop transition, ensuring that the

theta error reduces to zero. The slow acceleration can be configured using CL_SLOW_ACC.

Figure 7-27 shows the control sequence in open to closed loop transition. The current i_{q_ref}reduces to a lower

value in current decay region, if IQ_RAMP_EN is set to 1b. If IQ_RAMP_EN is set to 0b, then the current decay

region will not be present in the transition sequence.

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i_qref

THETA_ERROR_RAMP_RATE

Theta_error

SPEED

SPEED_REF

OPN_CL_HANDOFF_THR

II

III

IV

V

I

I. Open Loop Accelera on, II. Current Decay, III. Closed loop slow accelera on

IV. Closed loop accelera on, V. Closed loop steady state

Figure 7-27. Control Sequence in Open to Closed Loop Transition

User Set

I_limit

Accelera on

Control and

Speed Pro les

Current

Limit

SW1

I_limit

I_q_ref

DUTY_CMD

SPEED_REF

Speed_meas

V_M

0

Torque

Controller

V_q

V_d

V

V_a

V_b

V_c

Speed

Loop

Inverse

Clarke/

SVM

0

Inverse

Park

I_d_ref = 0

Flux

Controller

Open Loop Ramp

gen

SW2

Generator (Coe

A1 and A2)

I_a

I_d

I_q

I

I_b

I_c

Park

Clarke

est

I

Back-EMF

Observer

V

Figure 7-28. Open to Closed Loop Transition Control Block Diagram

7.3.11 Closed Loop Operation

The MCF8316A drives the motor using Field Oriented Control (FOC) as shown in Figure 7-29. In closed loop

operation, the motor angle (Ɵ_est) and speed (Speed_meas) are estimated using the back-EMF observer. The

speed and current regulation are achieved using PI control loop. In order to achieve maximum efficiency, the

direct axis current is set to zero (I_{d_ref}= 0), which will ensure that stator and rotor field are orthogonal (90^oout of

phase) to each other.

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Accelera on

Control and

Speed Pro les

DUTY_CMD

SPEED_REF

Speed

Loop

I_limit

I_q_ref

0

V_M

Torque

Controller

Speed_meas

V

V_q

V_d

V_a

V_b

V_c

Inverse

Clarke/

SVM

0

Inverse

Park

I_d_ref = 0

Flux

Controller

I_a

I_d

I_q

I

I_b

I_c

Park

Clarke

est

I

BEMF Observer

V

Figure 7-29. Closed Loop FOC Control

7.3.11.1 Closed loop accelerate

To prevent sudden changes in the torque applied to the motor which could result in acoustic noise, the

MCF8316A device provides the option of limiting the maximum rate at which the speed command can change.

The closed loop acceleration rate parameter sets the maximum rate at which the speed command changes

(shown in Figure 7-30). In the MCF8316A, closed loop acceleration rate is configured through CL_ACC.

y%

Speed command

input

x%

y%

Speed command

after closed loop

accelerate buffer

x%

Closed loop

accelerate settings

Figure 7-30. Closed loop accelerate

7.3.11.2 Speed PI Control

The integrated speed control loop helps maintain a constant speed over varying operating conditions. The K_p

and K_icoefficients are configured through SPD_LOOP_KP and SPD_LOOP_KI. The output of the speed loop

is used to generate the current reference for torque control (I_{q_ref}). The output of the speed loop is limited to

implement a current limit. The current limit is set by configuring ILIMIT. When output of the speed loop saturates,

the integrator is disabled to prevent integral wind-up.

SPEED_REF is derived from the duty command input and speed profiles configured by the user and

SPEED_MEAS is the estimated speed from the back-EMF observer.

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ILIMIT

OUT

K_p

K_i

SPEED_REF

+

I_{q_ref}

-

+

-ILIMIT

+

SPEED_MEAS

Z^-1

Switch close,

if -ILIMIT < OUT < ILIMIT

Figure 7-31. Speed PI Control

7.3.11.3 Current PI Control

The MCF8316A has two PI controllers, one each for I_dand I_qto control flux and torque separately. K_p

and K_icoefficients are the same for both PI controllers and are configured through CURR_LOOP_KP and

CURR_LOOP_KI. The outputs of the current control loops are used to generate voltage signals V_dand V_qto be

applied to the motor. The outputs of the current loops are clamped to supply voltage V_M. I_dcurrent PI loop is

executed first and output of I_dcurrent PI loop V_dis checked for saturation. When the output of the current loop

saturates, the integration is disabled to prevent integral wind-up.

VM

OUT

I_{d_ref}

K_p

K_i

+

V_d

+

-

+

-VM

+

I_d

Z^-1

**Switch close,

if -VM < V_d< VM

** Priority is given to V_d;

V_dis calculated ﬁrst for

saturaꢀon detecꢀon

Figure 7-32. I_dCurrent PI Control

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VM

OUT

K_p

K_i

I_{q_ref}

+

V_q

+

-

+

-VM

+

I_q

**Switch close,

if V_d²+ V_q²< VM²when

overmodula on is

Z^-1

disabled; when enabled,

switch close if -VM < V_q<

VM

** Priority is given to V_d;

V_dis calculated ﬁrst for

satura

ꢀ

on detec

ꢀ

on

Figure 7-33. I_qCurrent PI Control

7.3.11.4 Overmodulation

MCF8316A provides an overmodulation option to operate the motor at a higher speed at the same VM voltage

by increasing the applied fundamental phase voltage by suitably modifying the applied PWM pattern - the higher

fundamental phase voltage is accompanied by an increase in higher order harmonics. This feature can be

enabled by setting OVERMODULATION_ENABLE to 1b.

7.3.12 Motor Parameters

The MCF8316A uses the motor resistance, motor inductance and motor back-EMF constant to estimate motor

position when operating in closed loop. The MCF8316A has the capability of measuring these motor parameters

in the offline state (see Motor Parameter Extraction Tool (MPET)). Offline measurement of parameters, when

enabled, takes place before normal motor operation. The user can also disable the offline measurement and

configure motor parameters through EEPROM. This feature of offline motor parameter measurement is useful to

account for motor to motor variation during manufacturing.

7.3.12.1 Motor Resistance

For a wye-connected motor, the motor phase resistance refers to the resistance from the phase output to the

center tap, R_PH(denoted as R_PHin Figure 7-34). For a delta-connected motor, the motor phase resistance refers

to the equivalent phase to center tap in the wye configuration in Figure 7-34.

Phase A

R

PH

_

PH

R

CT

R

PH

R^PH

R_{PH_PH}

Phase C

Phase B

Figure 7-34. Motor Resistance

For both the delta-connected and the wye-connected motor, the easy way to get the equivalent R_PHis to

measure the resistance between two phase terminals (R_{PH_PH}), and then divide this value by two, R_PH= ½

R_{PH_PH}. In wye-connected motor, if user has access to center tap (CT), R_PHcan also be measured between

center tap (CT) and phase terminal.

Configure the motor resistance (R_PH) to a nearest value from Table 7-2.

44

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Table 7-2. Motor Resistance Look-Up Table

MOTOR_RES

(HEX)

MOTOR_RES

(HEX)

MOTOR_RES

(HEX)

MOTOR_RES

(HEX)

R_PH(Ω)

Self

R_PH(Ω)

0.145

R_PH(Ω)

0.465

R_PH(Ω)

2.1

0x00

0x40

0x80

0xC0

Measurement

(see Motor

Parameter

Extraction Tool

(MPET))

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0.006

0.007

0.008

0.009

0.010

0.011

0.012

0.013

0.014

0.015

0.016

0.017

0.018

0.019

0.020

0.022

0.024

0.026

0.028

0.030

0.032

0.034

0.036

0.038

0.040

0.042

0.044

0.046

0.048

0.050

0.052

0.054

0.056

0.058

0.060

0.062

0.064

0.066

0.068

0.070

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

0x50

0x51

0x52

0x53

0x54

0x55

0x56

0x57

0x58

0x59

0x5A

0x5B

0x5C

0x5D

0x5E

0x5F

0x60

0x61

0x62

0x63

0x64

0x65

0x66

0x67

0x68

0.150

0.155

0.160

0.165

0.170

0.175

0.180

0.185

0.190

0.195

0.200

0.205

0.210

0.215

0.220

0.225

0.230

0.235

0.240

0.245

0.250

0.255

0.260

0.265

0.270

0.275

0.280

0.285

0.290

0.295

0.300

0.305

0.310

0.315

0.320

0.325

0.330

0.335

0.340

0.345

0x81

0x82

0x83

0x84

0x85

0x86

0x87

0x88

0x89

0x8A

0x8B

0x8C

0x8D

0x8E

0x8F

0x90

0x91

0x92

0x93

0x94

0x95

0x96

0x97

0x98

0x99

0x9A

0x9B

0x9C

0x9D

0x9E

0x9F

0xA0

0xA1

0xA2

0xA3

0xA4

0xA5

0xA6

0xA7

0xA8

0.470

0.475

0.480

0.485

0.490

0.495

0.50

0.51

0.52

0.53

0.54

0.55

0.56

0.57

0.58

0.59

0.60

0.61

0.62

0.63

0.64

0.65

0.66

0.67

0.68

0.69

0.70

0.72

0.74

0.76

0.78

0.80

0.82

0.84

0.86

0.88

0.90

0.92

0.94

0.96

0xC1

0xC2

0xC3

0xC4

0xC5

0xC6

0xC7

0xC8

0xC9

0xCA

0xCB

0xCC

0xCD

0xCE

0xCF

0xD0

0xD1

0xD2

0xD3

0xD4

0xD5

0xD6

0xD7

0xD8

0xD9

0xDA

0xDB

0xDC

0xDD

0xDE

0xDF

0xE0

0xE1

0xE2

0xE3

0xE4

0xE5

0xE6

0xE7

0xE8

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.2

3.4

3.6

3.8

4.0

4.2

4.4

4.6

4.8

5.0

5.2

5.4

5.6

5.8

6.0

6.2

6.4

6.6

6.8

7.0

7.2

7.4

7.6

7.8

8.0

8.2

8.4

8.6

8.8

9

9.2

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Table 7-2. Motor Resistance Look-Up Table (continued)

MOTOR_RES

(HEX)

MOTOR_RES

(HEX)

MOTOR_RES

(HEX)

MOTOR_RES

(HEX)

R_PH(Ω)

0.072

R_PH(Ω)

0.350

R_PH(Ω)

0.98

R_PH(Ω)

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

0xA9

0xAA

0xAB

0xAC

0xAD

0xAE

0xAF

0xB0

0xB1

0xB2

0xB3

0xB4

0xB5

0xB6

0xB7

0xB8

0xB9

0xBA

0xBB

0xBC

0xBD

0xBE

0xBF

0xE9

0xEA

0xEB

0xEC

0xED

0xEE

0xEF

0xF0

0xF1

0xF2

0xF3

0xF4

0xF5

0xF6

0xF7

0xF8

0xF9

0xFA

0xFB

0xFC

0xFD

0xFE

0xFF

9.4

0.074

0.076

0.078

0.080

0.082

0.084

0.086

0.088

0.090

0.092

0.094

0.096

0.098

0.100

0.105

0.110

0.115

0.120

0.125

0.130

0.135

0.140

0.355

0.360

0.365

0.370

0.375

0.380

0.385

0.390

0.395

0.400

0.405

0.410

0.415

0.420

0.425

0.430

0.435

0.440

0.445

0.450

0.455

0.460

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

2.05

9.6

9.8

10.0

10.5

11.0

11.5

12.0

12.5

13.0

13.5

14.0

14.5

15.0

15.5

16.0

16.5

17.0

17.5

18.0

18.5

19.0

20.0

7.3.12.2 Motor Inductance

For a wye-connected motor, the motor phase inductance refers to the inductance from the phase output to the

center tap, L_PH(denoted as L_PHin Figure 7-35). For a delta-connected motor, the motor phase inductance refers

to the equivalent phase to center tap in the wye configuration in Figure 7-35.

Phase A

L

PH

_

P

PH

H

L

CT

L

PH

L^PH

L_{PH_PH}

Phase C

Phase B

Figure 7-35. Motor Inductance

For both the delta-connected motor and the wye-connected motor, the easy way to get the equivalent L_PHis

to measure the inductance between two phase terminals (L_{PH_PH}), and then divide this value by two, L_PH= ½

L_{PH_PH}. In wye-connected motor, if user has access to center tap (CT), L_PHcan also be measured between

center tap (CT) and phase terminal.

Configure the motor inductance (L_PH) to a nearest value from Table 7-3.

46

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Table 7-3. Motor Inductance Look-Up Table

MOTOR_IND

(HEX)

MOTOR_IND

(HEX)

MOTOR_IND

(HEX)

MOTOR_IND

(HEX)

L_PH(mH)

0x00

Self

0x40

0.145

0x80

0.465

0xC0

2.1

Measurement

(see Motor

Parameter

Extraction Tool

(MPET))

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0.006

0.007

0.008

0.009

0.010

0.011

0.012

0.013

0.014

0.015

0.016

0.017

0.018

0.019

0.020

0.022

0.024

0.026

0.028

0.030

0.032

0.034

0.036

0.038

0.040

0.042

0.044

0.046

0.048

0.050

0.052

0.054

0.056

0.058

0.060

0.062

0.064

0.066

0.068

0.070

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

0x50

0x51

0x52

0x53

0x54

0x55

0x56

0x57

0x58

0x59

0x5A

0x5B

0x5C

0x5D

0x5E

0x5F

0x60

0x61

0x62

0x63

0x64

0x65

0x66

0x67

0x68

0.150

0.155

0.160

0.165

0.170

0.175

0.180

0.185

0.190

0.195

0.200

0.205

0.210

0.215

0.220

0.225

0.230

0.235

0.240

0.245

0.250

0.255

0.260

0.265

0.270

0.275

0.280

0.285

0.290

0.295

0.300

0.305

0.310

0.315

0.320

0.325

0.330

0.335

0.340

0.345

0x81

0x82

0x83

0x84

0x85

0x86

0x87

0x88

0x89

0x8A

0x8B

0x8C

0x8D

0x8E

0x8F

0x90

0x91

0x92

0x93

0x94

0x95

0x96

0x97

0x98

0x99

0x9A

0x9B

0x9C

0x9D

0x9E

0x9F

0xA0

0xA1

0xA2

0xA3

0xA4

0xA5

0xA6

0xA7

0xA8

0.470

0.475

0.480

0.485

0.490

0.495

0.50

0.51

0.52

0.53

0.54

0.55

0.56

0.57

0.58

0.59

0.60

0.61

0.62

0.63

0.64

0.65

0.66

0.67

0.68

0.69

0.70

0.72

0.74

0.76

0.78

0.80

0.82

0.84

0.86

0.88

0.90

0.92

0.94

0.96

0xC1

0xC2

0xC3

0xC4

0xC5

0xC6

0xC7

0xC8

0xC9

0xCA

0xCB

0xCC

0xCD

0xCE

0xCF

0xD0

0xD1

0xD2

0xD3

0xD4

0xD5

0xD6

0xD7

0xD8

0xD9

0xDA

0xDB

0xDC

0xDD

0xDE

0xDF

0xE0

0xE1

0xE2

0xE3

0xE4

0xE5

0xE6

0xE7

0xE8

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.2

3.4

3.6

3.8

4.0

4.2

4.4

4.6

4.8

5.0

5.2

5.4

5.6

5.8

6.0

6.2

6.4

6.6

6.8

7.0

7.2

7.4

7.6

7.8

8.0

8.2

8.4

8.6

8.8

9

9.2

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Table 7-3. Motor Inductance Look-Up Table (continued)

MOTOR_IND

(HEX)

MOTOR_IND

(HEX)

MOTOR_IND

(HEX)

MOTOR_IND

(HEX)

L_PH(mH)

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0.072

0.074

0.076

0.078

0.080

0.082

0.084

0.086

0.088

0.090

0.092

0.094

0.096

0.098

0.100

0.105

0.110

0.115

0.120

0.125

0.130

0.135

0.140

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

0.350

0.355

0.360

0.365

0.370

0.375

0.380

0.385

0.390

0.395

0.400

0.405

0.410

0.415

0.420

0.425

0.430

0.435

0.440

0.445

0.450

0.455

0.460

0xA9

0xAA

0xAB

0xAC

0xAD

0xAE

0xAF

0xB0

0xB1

0xB2

0xB3

0xB4

0xB5

0xB6

0xB7

0xB8

0xB9

0xBA

0xBB

0xBC

0xBD

0xBE

0xBF

0.98

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

2.05

0xE9

0xEA

0xEB

0xEC

0xED

0xEE

0xEF

0xF0

0xF1

0xF2

0xF3

0xF4

0xF5

0xF6

0xF7

0xF8

0xF9

0xFA

0xFB

0xFC

0xFD

0xFE

0xFF

9.4

9.6

9.8

10.0

10.5

11.0

11.5

12.0

12.5

13.0

13.5

14.0

14.5

15.0

15.5

16.0

16.5

17.0

17.5

18.0

18.5

19.0

20.0

7.3.12.3 Motor Back-EMF constant

The back-EMF constant describes the motor phase-to-neutral back-EMF voltage as a function of the motor

speed. For a wye-connected motor, the motor BEMF constant refers to the BEMF as a function of time from

the phase output to the center tap, Kt_{PH_N}(denoted as Kt_{PH_N}in Figure 7-36). For a delta-connected motor, the

motor BEMF constant refers to the equivalent phase to center tap in the wye configuration in Figure 7-36.

Phase A

E_PH

t_E

CT

Kt_{PH_N}= (1/sqrt(3)) *E_PH* t_E

E_{PH_B}

L_PH

R_PH

Phase B

Phase C

Figure 7-36. Motor back-EMF constant

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For both the delta-connected motor and the wye-connected motor, the easy way to get the equivalent Kt_{PH_N}

is to measure the peak value of BEMF on scope for one electrical cycle between two phase terminals (E_PH),

and then multiply by time duration of one electrical cycle and in order to convert from phase-to-phase to

phase-to-neutral divide by sqrt(3) as shown in Equation 6 .

1

Kt

=

× E × t

3

PH E

(6)

PH_N

Configure the motor BEMF constant (Kt_{PH_N}) to a nearest value from Table 7-4.

Table 7-4. Motor BEMF constant Look-Up Table

MOTOR_BEM

F_CONST

(HEX)

MOTOR_BEMF_ Kt_{PH_N}

Kt_{PH_N}

(mV/Hz)

CONST (HEX)

(mV/Hz)

CONST (HEX)

(mV/Hz)

CONST (HEX)

(mV/Hz)

0x00

Self

0x40

14.5

0x80

46.5

0xC0

210

Measurement

(see Motor

Parameter

Extraction Tool

(MPET))

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

4.0

4.2

4.4

4.6

4.8

5.0

5.2

5.4

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

0x50

0x51

0x52

0x53

0x54

0x55

0x56

0x57

0x58

0x59

0x5A

0x5B

0x5C

0x5D

0x5E

0x5F

0x60

15.0

15.5

16.0

16.5

17.0

17.5

18.0

18.5

19.0

19.5

20.0

20.5

21.0

21.5

22.0

22.5

23.0

23.5

24.0

24.5

25.0

25.5

26.0

26.5

27.0

27.5

28.0

28.5

29.0

29.5

30.0

30.5

0x81

0x82

0x83

0x84

0x85

0x86

0x87

0x88

0x89

0x8A

0x8B

0x8C

0x8D

0x8E

0x8F

0x90

0x91

0x92

0x93

0x94

0x95

0x96

0x97

0x98

0x99

0x9A

0x9B

0x9C

0x9D

0x9E

0x9F

0xA0

47.0

47.5

48.0

48.5

49.0

49.5

50.0

51

0xC1

0xC2

0xC3

0xC4

0xC5

0xC6

0xC7

0xC8

0xC9

0xCA

0xCB

0xCC

0xCD

0xCE

0xCF

0xD0

0xD1

0xD2

0xD3

0xD4

0xD5

0xD6

0xD7

0xD8

0xD9

0xDA

0xDB

0xDC

0xDD

0xDE

0xDF

0xE0

220

230

240

250

260

270

280

290

300

320

340

360

380

400

420

440

460

480

500

520

540

560

580

600

620

640

660

680

700

720

740

760

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

72

74

76

78

80

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Table 7-4. Motor BEMF constant Look-Up Table (continued)

MOTOR_BEM

F_CONST

(HEX)

MOTOR_BEMF_ Kt_{PH_N}

Kt_{PH_N}

(mV/Hz)

CONST (HEX)

(mV/Hz)

CONST (HEX)

(mV/Hz)

CONST (HEX)

(mV/Hz)

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

5.6

0x61

0x62

0x63

0x64

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

31.0

0xA1

0xA2

0xA3

0xA4

0xA5

0xA6

0xA7

0xA8

0xA9

0xAA

0xAB

0xAC

0xAD

0xAE

0xAF

0xB0

0xB1

0xB2

0xB3

0xB4

0xB5

0xB6

0xB7

0xB8

0xB9

0xBA

0xBB

0xBC

0xBD

0xBE

0xBF

82

84

0xE1

0xE2

0xE3

0xE4

0xE5

0xE6

0xE7

0xE8

0xE9

0xEA

0xEB

0xEC

0xED

0xEE

0xEF

0xF0

0xF1

0xF2

0xF3

0xF4

0xF5

0xF6

0xF7

0xF8

0xF9

0xFA

0xFB

0xFC

0xFD

0xFE

0xFF

780

800

5.8

6.0

31.5

32.0

32.5

33.0

33.5

34.0

34.5

35.0

35.5

36.0

36.5

37.0

37.5

38.0

38.5

39.0

39.5

40.0

40.5

41.0

41.5

42.0

42.5

43.0

43.5

44.0

44.5

45.0

45.5

46.0

86

820

6.2

88

840

6.4

90

860

6.6

92

880

6.8

94

900

7.0

96

920

7.2

98

940

7.4

100

105

110

115

120

125

130

135

140

145

150

155

160

165

170

175

180

185

190

195

200

205

960

7.6

980

7.8

1000

1050

1100

1150

1200

1250

1300

1350

1400

1450

1500

1550

1600

1650

1700

1750

1800

1850

1900

2000

8.0

8.2

8.4

8.6

8.8

9.0

9.2

9.4

9.6

9.8

10.0

10.5

11.0

11.5

12.0

12.5

13.0

13.5

14.0

7.3.13 Motor Parameter Extraction Tool (MPET)

The MCF8316A uses motor winding resistance, motor winding inductance and Back-EMF constant to estimate

motor position in closed loop operation. The MCF8316A has capability of automatically measuring motor

parameters in offline state, rather than having the user enter the values themselves. The MPET routine

measures motor winding resistance, inductance, back EMF constant and mechanical load inertia and frictional

coefficients. Offline measurement of parameters takes place before normal motor operation. TI recommends to

estimate the motor parameters before motor startup to minimize the impact caused due to possible parameter

variations.

Figure 7-37 shows the sequence of operation in the MPET routine. The MPET routine is entered when either the

MPET_CMD bit is set to 1b or a non-zero target speed is set. The MPET routine consists of four steps namely,

IPD, Open Loop Acceleration, Current Ramp Down and Coasting. Each one of these steps are executed if the

condition shown below the step evaluates to TRUE; if the condition evaluates to FALSE, the algorithm bypasses

that particular step and moves on to the next step in the sequence. Once all the 4 steps are completed (or

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bypassed), the algorithm exits the MPET routine. If target speed is set to a non-zero value, the algorithm begins

the start-up and acceleration sequence (to target speed reference) once MPET routine is exited.

BEMF Constant and

Mechanical Parameter

Motor Winding R and

L Measurement

Measurement

BEMF constant estimated,

initial speed PI loop

constants tuned

Motor R and L

estimated;

MPET_CMD = 1b ||

Target_speed is non-

zero

Open Loop

Acceleration

Current Ramp

Down

IPD

Coasting

End of MPET

MPET_KE = 1b ||

MPET_MECH = 1b ||

MPET_KE = 1b ||

MPET_MECH = 1b ||

SPD_LOOP_KP = 0 ||

SPD_LOOP_KI = 0

MPET_R = 1b ||

MPET_L = 1b ||

MOTOR_BEMF_CONST = 0 ||

SPD_LOOP_KP = 0 ||

SPD_LOOP_KI = 0

MOTOR_BEMF_CONST = 0 ||

SPD_LOOP_KP = 0 ||

SPD_LOOP_KI = 0

MOTOR_RES = 0 ||

MOTOR_IND = 0

Figure 7-37. MPET Sequence

TI proprietary MPET routine includes following sequence of operation.

•

IPD: The MPET routine starts with IPD, if the user enables motor winding resistance or inductance

measurement by setting MPET_R = 1b and MPET_L = 1b or if the user defines MOTOR_RES = 0 or

MOTOR_IND = 0. The IPD during MPET can be configured using MPET specific configuration parameters

or using the normal motor operation IPD configuration parameters. The IPD configuration selection is

done using MPET_IPD_SELECT. With MPET_IPD_SELECT = 1b, the IPD current limit is configured using

MPET_IPD_CURRENT_LIMIT and the IPD repeat number is configured using MPET_IPD_FREQ. With

MPET_IPD_SELECT = 0b, the IPD current limit and the repeat number is configured using IPD_CURR_THR

and IPD_REPEAT. The IPD timer over flow or the IPD current decay time more than three times the current

ramp up time can result in MPET_IPD_FAULT. TI recommends to run the MPET multiple times to observe for

consistent resistance and inductance reading.

•

Open loop Acceleration:

After IPD, the MPET routine run align and then open loop acceleration if the back-EMF

constant or mechanical parameter measurement are enabled by setting MPET_KE = 1b and

MPET_MECH = 1b. The MPET routine incorporates the sequences for mechanical parameter

measurement, if the speed loop PI constants are defined as zero, even if MPET_MECH =

0b. User can configure MPET specific open loop configuration parameters or use normal motor

operation open loop configuration parameters. The open loop configuration selection is done using

MPET_KE_MEAS_PARAMETER_SELECT. With MPET_KE_MEAS_PARAMETER_SELECT = 1b, the speed

slew rate is defined using MPET_OPEN_LOOP_SLEW_RATE, the open loop current reference is

defined using MPET_OPEN_LOOP_CURR_REF and the open loop speed reference is defined using

MPET_OPEN_LOOP_SPEED_REF. With MPET_KE_MEAS_PARAMETER_SELECT = 0b, the speed slew

rate is defined using OL_ACC_A1 and OL_ACC_A2, 80% of ILIMIT for current reference and 50% of

MAX_SPEED for speed reference.

•

Current Ramp Down: After open loop acceleration, if the mechanical parameter measurement is enabled,

then the MPET routine optimizes the motor current to lower value sufficient to support the load. If mechanical

parameter measurement is disabled (MPET_MECH = 0b, or non-zero speed loop PI parameters) then the

MPET will not have the current ramp down sequence.

Coasting: MPET routine completes the sequence by allowing the motor to coast by enabling Hi-Z. The motor

back EMF and indicative values of mechanical parameters are measured during the motor coasting period. If

the motor back EMF is lower than the threshold defined in STAT_DETECT_THR, the MPET_BEMF_FAULT is

generated.

Selecting the parameters from EEPROM or MPET

The MPET estimated values are available in the MTR_PARAMS Register. Setting the MPET_WRITE_SHADOW

bit to 1, writes the MPET estimated values to the shadow registers and the user-configured (from EEPROM)

values in MOTOR_RES, MOTOR_IND, MOTOR_BEMF_CONST, CURR_LOOP_KP, CURR_LOOP_KI,

SPD_LOOP_KP and SPD_LOOP_KI shadow registers will be overwritten by the estimated values from MPET.

If any of the shadow registers are initialized to zero (from EEPROM registers), the MPET estimated values

are used for those registers independent of the MPET_WRITE_SHADOW setting. The MPET calculates the

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current loop KP and KI by using the measured resistance and inductance. The MPET does an estimation of

the mechanical parameters including the inertia and frictional coefficient at the shaft (includes both motor and

shaft coupled load). These values are used to set an initial values speed loop KP and KI. The estimated speed

loop KP and KI setting can be used as an initial setting only and TI recommends to tune these parameters on

application by the user based on the performance requirement.

7.3.14 Anti-Voltage Surge (AVS)

When a motor is driven, energy is transferred from the power supply into the motor. Some of this energy

is stored in the form of inductive and mechanical energy. If the speed command suddenly drops such that

the BEMF voltage generated by the motor is greater than the voltage that is applied to the motor, then the

mechanical energy of the motor is returned to the power supply and the V_Mvoltage surges. The AVS feature

works to prevent this voltage surge on V_Mand can be enabled by setting AVS_EN to 1b. AVS can be disabled by

setting AVS_EN to 0b. When AVS is disabled, the deceleration rate is configured through CL_DEC_CONFIG

7.3.15 Output PWM Switching Frequency

The MCF8316A provides the option to configure the output PWM switching frequency of the MOSFETs through

PWM_FREQ_OUT. PWM_FREQ_OUT has range of 10-75 kHz. In order to select optimal output PWM switching

frequency, user has to make tradeoff between the current ripple and the switching losses. Generally, motors

having lower L/R ratio require higher PWM switching frequency to reduce current ripple.

7.3.16 Active Braking

Decelerating the motor quickly requires motor mechanical energy to be extracted and disposed - input DC

voltage increases if this energy is returned to the DC input supply. When active braking is enabled, energy taken

from DC power supply is used to brake the motor - this prevents DC voltage spike during fast deceleration. The

mechanical energy of the motor and energy taken from DC source, both are dissipated within the motor itself.

ACTIVE_BRAKE_EN should be set to 1b to enable active braking and avoid DC bus voltage spike during fast

motor deceleration. Active braking can also be used during reverse drive (see Reverse Drive) or motor stop (see

Active Spin-Down) to reduce the motor speed quickly without DC voltage spike.

The maximum limit on the current sourced from the DC bus (i_{dc_ref}) during active braking can be configured

using ACTIVE_BRAKE_CURRENT_LIMIT. The power flow control during active braking is achieved by using

both Q-axis (i_q) and D-axis (i_d) components of current. The D-axis current reference (i_{d_ref}) is generated

from the error between DC bus current limit (i_{dc_ref}) and the estimated DC bus current (i_dc) using a PI

controller. The i_dcvalue is estimated from the measured phase currents, phase voltage and DC bus voltage,

using power balance equation (equating the instantaneous DC bus power to sum of all three instantaneous

phase power assuming 100% efficiency). During active braking, the DC bus current limit (i_{dc_ref}) starts

from zero and linearly increases to ACTIVE_BRAKE_CURRENT_LIMIT with current slew rate as defined by

ACTIVE_BRAKE_BUS_CURRENT_SLEW_RATE. The gain constants of PI controller can be configured using

ACTIVE_BRAKE_KP and ACTIVE_BRAKE_KI. Figure 7-38 shows the active braking id current control loop.

i_{d_ref}

i_{dc_ref}

+

PI

-

ACTIVE_BRAKE_KP

ACTIVE_BRAKE_KI

i_dc

Figure 7-38. Active Braking Current Control Loop for i_{d_ref}

7.3.17 PWM Modulation Schemes

The MCF8316 supports two different modulation schemes, namely, continuous and discontinuous space vector

PWM modulation schemes. In continuous PWM modulation, all the three phases switch all the time as per

the defined switching frequency. In discontinuous PWM modulation, one of the phases is clamped to ground

for 120^oelectrical period, and the other two phases are pulse width modulated. The modulation scheme

is configured using PWM_MODE. Figure 7-39 shows the modulated average phase voltages for different

modulation schemes.

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OUTA

OUTB

OUTC

OUTA - OUTB

Voltage from Phase to GND - Con nuous PWM modula on

OUTB - OUTC

OUTC - OUTA

OUTA

OUTB

Sinusoidal voltage from phase to phase

OUTC

Voltage from Phase to GND - Discon nuous PWM modula on

Figure 7-39. Continuous and Discontinuous PWM Modulation Phase Voltages

Continuous modulation helps in reducing current ripple for motors having low inductance but it results in higher

switching losses because all three phases are switching. Discontinuous modulation has lower switching losses

due to only two phases switching at a time, but higher current ripple.

7.3.18 Dead Time Compensation

Dead time is inserted between the switching instants of high-side and low-side MOSFET in a half bridge leg

to avoid shoot-through condition. Due to dead time insertion, the expected voltage and applied voltage at the

phase node differ based on the phase current direction. The phase node voltage distortion introduces undesired

distortion in the phase current causing audible noise. The distortion in current waveform due to dead time

appear as sixth harmonic of fundamental frequency in the dq reference frame. The MCF8316 integrates a

proprietary dead time compensation using a resonant controller to control the sixth harmonic component in

phase current to zero, ensuring that the current distortion due to dead time is alleviated. The resonant controller

is employed in both i_qand i_dcontrol paths. The dead time compensation can be enabled or disabled by

configuring DEADTIME_COMP_EN.

7.3.19 Motor Stop Options

The MCF8316A provides different options for stopping the motor which can be configured by MTR_STOP.

7.3.19.1 Coast (Hi-Z) Mode

Coast (Hi-Z) mode is configured by setting MTR_STOP to 000b. When motor stop command is received, the

MCF8316A will transition into a high impedance (Hi-Z) state by turning off all MOSFETs. When the MCF8316A

transitions from driving the motor into a Hi-Z state, the inductive current in the motor windings continues to flow

and the energy returns to the power supply through the body diodes in the MOSFET output stage (see example

Figure 7-40).

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HSC

LSC

HSA

LSA

HSB

HSC

LSC

HSA

LSA

HSB

LSB

VM

M

VM

M

LSB

Driving State

High-Impedance State

Figure 7-40. Coast (Hi-Z) Mode

In this example, current is applied to the motor through the high-side phase-A MOSFET (HSA), high-side phase-

B MOSFET(HSB) and returned through the low-side phase-C MOSFET (LSC). When motor stop command is

received all 6 MOSFETs transition to Hi-Z state and the inductive energy returns to supply through body diodes

of MOSFETs LSA, LSB and HSC.

7.3.19.2 Recirculation Mode

Recirculation mode is configured by setting MTR_STOP to 001b. In order to prevent the inductive energy from

returning to DC input supply during motor stop, the MCF8316A allows current to circulate within the MOSFETs

by selectively turning OFF some of the active (ON) MOSFETs for a certain time (auto calculated recirculation

time to allow the inductive current to decay to zero) before transitioning into Hi-Z by turning OFF the remaining

MOSFETs.

Depending on the phase voltage pattern at the time of receiving the stop command, either low-side (see Figure

7-41) or high-side recirculation (see Figure 7-42) will be used to stop the motor without sending the inductive

energy back to the DC input supply.

S3

HSB

HSC

LSC

HSA

LSA

HSB

LSB

HSC

LSC

HSA

LSA

VM

M

VM

M

LSB

Low-Side Recirculaꢀon Mode

Driving State

Figure 7-41. Low-Side Recirculation

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HSC

LSC

HSB

HSA

LSA

HSB

LSB

HSC

LSC

HSA

LSA

VM

M

VM

M

LSB

High-Side Recircula on Mode

Driving State

Figure 7-42. High-Side Recirculation

7.3.19.3 Low-Side Braking

Low-side braking mode is configured by setting MTR_STOP to 010b. When a motor stop command is received,

the output speed is reduced to a value defined by BRAKE_SPEED_THRESHOLD prior to turning all low-side

MOSFETs ON (see example Figure 7-43) for a time configured by MTR_STOP_BRK_TIME. If the motor speed

is below BRAKE_SPEED_THRESHOLD prior to receiving stop command, then the MCF8316A transitions

directly into the brake state. After applying the brake for MTR_STOP_BRK_TIME, the MCF8316A transitions

into the Hi-Z state by turning OFF all MOSFETs.

HSC

LSC

HSA

LSA

HSB

HSC

LSC

HSA

LSA

HSB

LSB

VM

M

VM

M

LSB

Low-Side Braking

Driving State

Figure 7-43. Low-Side Braking

The MCF8316A can also enter low-side braking through BRAKE pin input. When BRAKE pin is pulled to HIGH

state, the output speed is reduced to a value defined by BRAKE_SPEED_THRESHOLD prior to turning all

low-side MOSFETs ON. In this case, MCF8316A stays in low-side brake state till BRAKE pin changes to LOW

state.

7.3.19.4 High-Side Braking

High-side braking mode is configured by setting MTR_STOP to 011b. When a motor stop command is received,

the output speed is reduced to a value defined by BRAKE_SPEED_THRESHOLD prior to turning all high-side

MOSFETs ON (see example Figure 7-44) for a time configured by MTR_STOP_BRK_TIME. If the motor speed

is below BRAKE_SPEED_THRESHOLD prior to receiving stop command, then the MCF8316A transitions

directly into the brake state. After applying the brake for MTR_STOP_BRK_TIME, the MCF8316A transitions

into Hi-Z state by turning OFF all MOSFETs.

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HSC

LSC

HSA

LSA

HSB

HSA

LSA

HSB

LSB

VM

M

VM

M

LSB

LSC

High-Side Braking

Driving State

Figure 7-44. High-Side Braking

7.3.19.5 Active Spin-Down

Active spin down mode is configured by setting MTR_STOP to 100b. When a motor stop command is received,

the MCF8316A reduces SPEED_REF to ACT_SPIN_THR and then transitions to Hi-Z state by turning all

MOSFETs OFF. The advantage of this mode is that by reducing SPEED_REF, the motor is decelerated to lower

speed thereby reducing the phase currents before entering Hi-Z. Now, when the motor transitions into Hi-Z state,

the energy transfer to the power supply is reduced. The threshold ACT_SPIN_THR needs to configured high

enough for MCF8316A to not lose synchronization with the motor.

7.3.19.6 Align Braking

Align braking mode is configured by setting MTR_STOP to 101b. The MCF8316A can also enter align brake

state through the BRAKE pin. In this mode, the MCF8316A aligns the motor by injecting a DC current through

a particular phase pattern for a certain time configured by MTR_STOP_BRK_TIME. The phase pattern during

align is generated based on the angle at which align needs to be performed and this angle can be configured

through ALIGN_ANGLE or the last commutation angle. ALIGN_BRAKE_ANGLE_SEL can be configured to

decide which align angle is to be used by MCF8316A . The current limit threshold during align braking is

configured through ALIGN_OR_SLOW_CURRENT LIMIT.

7.3.20 FG Configuration

The MCF8316A provides information about the motor speed through the Frequency Generate (FG) pin. In

MCF8316A, the FG pin output is configured through FG_CONFIG. When FG_CONFIG is configured to 0b, the

FG output is active as long as the MCF8316A is driving the motor. When FG_CONFIG is configured to 1b, the

MCF8316A provides an FG output until the motor back-EMF falls below FG_BEMF_THR.

7.3.20.1 FG Output Frequency

The FG output frequency can be configured by FG_DIV. Many applications require the FG output to provide a

pulse for every mechanical rotation of the motor Different FG_DIV configurations can accomplish this for 2-pole

up to 30-pole motors.

Figure 7-45 shows the FG output when MCF8316A has been configured to provide FG pulses once every

electrical cycle (2 poles), once every two electrical cycle (4 poles), once every three electrical cycles (6 poles),

once every four electrical cycles (8 poles), and so on.

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Phase Voltage

FG_DIV = 0000b

or 0001b

(Elec cycle)

FG_DIV = 0010b

(Elec cycle*2)

FG_DIV = 0011b

(Elec cycle*3)

FG_DIV = 0100b

(Elec cycle*4)

Figure 7-45. FG Frequency Divider

7.3.20.2 FG Open-Loop and Lock Behavior

During closed loop operation, the driving speed (FG output frequency) and the actual motor speed are

synchronized. During open-loop operation, however, FG may not reflect the actual motor speed. During motor-

lock condition, the FG output is driven high.

The MCF8316A provides three options for controlling the FG output during open loop, as shown in Figure 7-46.

The selection of these options is configured through FG_SEL.

If FG_SEL is set to,

•

00b: When in open loop, the FG output is based on the driving frequency.

01b: When in open loop, the FG output will be driven high.

10b: The FG output will reflect the driving frequency during open loop operation in the first motor start-up

cycle after power-on, sleep/standby; FG will be held high during open loop operation in subsequent start-up

cycles.

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Open Loop

Close Loop

Phase

Voltage

FG_SEL = 00b

FG_SEL = 01b

Close Loop

Open Loop

Close Loop

Phase

Voltage

FG_SEL

= 10b

Any subsequent startup without

power down, sleep, or standby.

Startup a er power on or wake up

from sleep or standby mode

Figure 7-46. FG Behavior During Open Loop

7.3.21 DC Bus Current Limit

The DC bus current limit feature can be used in applications to limit the current supplied by source

without entering the constant current mode. The DC bus current limit feature can be enabled by setting

BUS_CURRENT_LIMIT_ENABLE to 1b. The DC bus current limit threshold can be configured using

BUS_CURRENT_LIMIT. The DC bus current limit limits the speed reference and a functional diagram is shown

in Figure 7-47. Enabling this feature may restrict the speed of the motor so that current drawn from source is

limited. The algorithm estimates the bus current using the measured phase currents, phase voltage and DC bus

voltage. The current limit status is reported on BUS_CURRENT_LIMIT_STATUS.

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Accelera on

Control and

Speed Proﬁles

SPEED_REF

DUTY_CMD

Speed Loop

Speed_meas

BUS_CURRENT_LIMIT

Figure 7-47. DC Bus Current Limit Functional Block Diagram

7.3.22 Protections

The MCF8316A is protected from a host of fault events including motor lock, VM undervoltage, AVDD

undervoltage, buck undervoltage, charge pump undervoltage, overtemperature and overcurrent events. Table

7-5 summarizes the response, recovery modes, power stage status, reporting mechanism for different faults.

Table 7-5. Fault Action and Response

FAULT

CONDITION

CONFIGURATION

REPORT

H-BRIDGE

LOGIC

RECOVERY

VM undervoltage

(NPOR)

Automatic:

V_VM> V_UVLO

V_VM< V_UVLO

—

Hi-Z

Disabled

AVDD undervoltage

(NPOR)

Automatic:

V_AVDD> V_{AVDD_UV}

V_AVDD< V_{AVDD_UV}

—

Hi-Z

Disabled

Buck undervoltage

(BUCK_UV)

Automatic:

V_{FB_BK}> V_{BK_UV}

V_{FB_BK}< V_{BK_UV}

nFAULT and

GATE_DRIVER_FA

ULT_STATUS

register

Charge pump

undervoltage

(VCP_UV)

Automatic:

V_VCP> V_CPUV

V_CP< V_CPUV

—

Hi-Z

Active

Hi-Z

Active

OVP_EN = 0b

OVP_EN = 1b

None

No action (OVP Disabled)

OverVoltage

Protection

(OVP)

nFAULT and

GATE_DRIVER_FA

ULT_STATUS

register

V_VM> V_OVP

Automatic:

V_VM< V_OVP

nFAULT and

GATE_DRIVER_FA

ULT_STATUS

register

Latched:

CLR_FLT

OCP_MODE = 00b

OCP_MODE = 01b

OCP_MODE = 10b

Hi-Z

Active

nFAULT and

GATE_DRIVER_FA

ULT_STATUS

register

Retry:

t_RETRY

Overcurrent

Protection

(OCP)

I_PHASE> I_OCP

nFAULT and

GATE_DRIVER_FA

ULT_STATUS

register

Active

No action

OCP_MODE = 11b

—

None

Active

Hi-Z

Active

Buck Overcurrent

Protection

Retry:

t_RETRY

I_BK> I_{BK_OCP}

—

Disabled

(BUCK_OCP)

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Table 7-5. Fault Action and Response (continued)

FAULT

CONDITION

CONFIGURATION

REPORT

H-BRIDGE

LOGIC

RECOVERY

nFAULT and

CONTROLLER_FA

ULT_STATUS

register

MTR_LCK_MODE =

0000b

Latched:

CLR_FLT

Hi-Z

Active

nFAULT and

CONTROLLER_FA

ULT_STATUS

register

MTR_LCK_MODE =

0001b

Latched:

CLR_FLT

Recirculation

High side brake

Low side brake

Hi-Z

Active

nFAULT and

CONTROLLER_FA

ULT_STATUS

register

MTR_LCK_MODE =

0010b

Latched:

CLR_FLT

nFAULT and

CONTROLLER_FA

ULT_STATUS

register

MTR_LCK_MODE =

0011b

Latched:

CLR_FLT

nFAULT and

CONTROLLER_FA

ULT_STATUS

register

MTR_LCK_MODE =

0100b

Retry:

t_{LCK_RETRY}

Motor lock: Abnormal

Speed; No Motor Lock;

Abnormal BEMF

Motor Lock

(MTR_LCK )

nFAULT and

CONTROLLER_FA

ULT_STATUS

register

MTR_LCK_MODE =

0101b

Retry:

t_{LCK_RETRY}

Recirculation

High side brake

Low side brake

nFAULT and

CONTROLLER_FA

ULT_STATUS

register

MTR_LCK_MODE =

0110b

Retry:

t_{LCK_RETRY}

nFAULT and

CONTROLLER_FA

ULT_STATUS

register

MTR_LCK_MODE =

0111b

Retry:

t_{LCK_RETRY}

nFAULT and

CONTROLLER_FA

ULT_STATUS

register

MTR_LCK_MODE =

1000b

Active

Hi-Z

Active

No action

MTR_LCK_MODE =

1xx1b

None

nFAULT and

HW_LOCK_ILIMIT_MOD CONTROLLER_FA

Latched:

CLR_FLT

E = 0000b

ULT_STATUS

register

nFAULT and

HW_LOCK_ILIMIT_MOD CONTROLLER_FA

Latched:

CLR_FLT

Recirculation

High-side brake

Low-side brake

Hi-Z

Active

E = 0001b

ULT_STATUS

register

nFAULT and

HW_LOCK_ILIMIT_MOD CONTROLLER_FA

Latched:

CLR_FLT

E = 0010b

ULT_STATUS

register

nFAULT and

HW_LOCK_ILIMIT_MOD CONTROLLER_FA

Latched:

CLR_FLT

E = 0011b

ULT_STATUS

register

nFAULT and

HW_LOCK_ILIMIT_MOD CONTROLLER_FA

Hardware Lock-

Detection Current

Limit

Retry:

t_{LCK_RETRY}

E = 0100b

ULT_STATUS

register

V_SOX> HW_LOCK_ILIMIT

(HW_LOCK_ILIMIT

)

nFAULT and

HW_LOCK_ILIMIT_MOD CONTROLLER_FA

Retry:

t_{LCK_RETRY}

Recirculation

High-side brake

Low-side brake

E = 0101b

ULT_STATUS

register

nFAULT and

HW_LOCK_ILIMIT_MOD CONTROLLER_FA

Retry:

t_{LCK_RETRY}

E = 0110b

ULT_STATUS

register

nFAULT and

HW_LOCK_ILIMIT_MOD CONTROLLER_FA

Retry:

t_{LCK_RETRY}

E = 0111b

ULT_STATUS

register

nFAULT and

HW_LOCK_ILIMIT_MOD CONTROLLER_FA

Active

No action

E= 1000b

ULT_STATUS

register

HW_LOCK_ILIMIT_MOD

E = 1xx1b

None

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Table 7-5. Fault Action and Response (continued)

FAULT

CONDITION

CONFIGURATION

REPORT

H-BRIDGE

LOGIC

RECOVERY

nFAULT and

CONTROLLER_FA

ULT_STATUS

register

LOCK_ILIMIT_MODE =

0000b

Latched:

CLR_FLT

Hi-Z

Active

nFAULT and

CONTROLLER_FA

ULT_STATUS

register

LOCK_ILIMIT_MODE =

0001b

Latched:

CLR_FLT

Recirculation

High-side brake

Low-side brake

Hi-Z

Active

nFAULT and

CONTROLLER_FA

ULT_STATUS

register

LOCK_ILIMIT_MODE =

0010b

Latched:

CLR_FLT

nFAULT and

CONTROLLER_FA

ULT_STATUS

register

LOCK_ILIMIT_MODE =

0011b

Latched:

CLR_FLT

nFAULT and

CONTROLLER_FA

ULT_STATUS

register

LOCK_ILIMIT_MODE =

0100b

Retry:

t_{LCK_RETRY}

Software Lock-

Detection Current

Limit

V_SOX> LOCK_ILIMIT

(LOCK_ILIMIT)

nFAULT and

CONTROLLER_FA

ULT_STATUS

register

LOCK_ILIMIT_MODE =

0101b

Retry:

t_{LCK_RETRY}

Recirculation

High-side brake

Low-side brake

nFAULT and

CONTROLLER_FA

ULT_STATUS

register

LOCK_ILIMIT_MODE =

0110b

Retry:

t_{LCK_RETRY}

nFAULT and

CONTROLLER_FA

ULT_STATUS

register

LOCK_ILIMIT_MODE =

0111b

Retry:

t_{LCK_RETRY}

nFAULT and

CONTROLLER_FA

ULT_STATUS

register

LOCK_ILIMIT_MODE=

1000b

Active

Hi-Z

Active

No action

LOCK_ILIMIT_MODE =

1xx1b

None

IPD Timeout Fault

(IPD_T1_FAULT

and

IPD TIME > 500ms

(approx), during IPD

current ramp up or ramp

down

nFAULT and

IPD_TIMEOUT_FAULT_E CONTROLLER_FA

Latched:

CLR_FLT

N = 1

ULT_STATUS

register

IPD_T2_FAULT)

nFAULT and

IPD_TIMEOUT_FAULT_E CONTROLLER_FA

IP Frequency Fault

(IPD_FREQ_FAULT current decay in previous

IPD pulse before the

Latched:

CLR_FLT

Hi-Z

Active

N = 1

ULT_STATUS

register

)

IPD

nFAULT and

CONTROLLER_FA

ULT_STATUS

register

MPET IPD Fault

(MPET_IPD_FAULT

)

Same as IPD Timeout

Fault.

MPET_CMD = 1 or

MPET_R or MPET_L = 1

Latched:

CLR_FLT

MPET Back-EMF

Fault

(MPET_BEMF_FA

ULT)

nFAULT and

CONTROLLER_FA

ULT_STATUS

register

Motor Back EMF <

STAT_DETECT_THR

MPET_CMD = 1 or

MPET_KE = 1

Latched:

CLR_FLT

Hi-Z

Active

OTW_REP = 0b

OTW_REP = 1b

None

Active

No action

nFAULT and

CONTROLLER_FA

ULT_STATUS

register

Thermal warning

(OTW)

Automatic:

T_J< T_OTW– T_{OTW_HYS}

CLR_FLT

T_J> T_OTW

nFAULT and

CONTROLLER_FA

ULT_STATUS

register

Automatic:

T_J< T_TSD– T_{TSD_HYS}

CLR_FLT

Thermal shutdown

(TSD)

T_J> T_TSD

—

Hi-Z

Active

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7.3.22.1 VM Supply Undervoltage Lockout

If at any time the input supply voltage on the VM pin falls lower than the V_UVLOthreshold (VM UVLO falling

threshold), all the integrated FETs, driver charge-pump and digital logic are disabled as shown in Figure 7-48.

MCF8316A goes into reset state whenever VM UVLO event occurs.

V_UVLO(max) rising

V_UVLO(min) rising

V_UVLO(max) falling

V_UVLO(min) falling

V_VM

DEVICE ON

DEVICE OFF

DEVICE ON

Time

Figure 7-48. VM Supply Undervoltage Lockout

7.3.22.2 AVDD Undervoltage Lockout (AVDD_UV)

If at any time the voltage on the AVDD pin falls lower than the V_{AVDD_UV}threshold, all the integrated FETs, driver

charge-pump and digital logic controller are disabled. Since internal circuitry in MCF8316A is powered through

the AVDD regulator, MCF8316A goes into reset state whenever AVDD UV event occurs.

7.3.22.3 BUCK Undervoltage Lockout (BUCK_UV)

If at any time the input supply voltage on the FB_BK pin falls lower than the V_{BK_UVLO}threshold, both the

high-side and low-side MOSFETs of the buck regulator are disabled . Since internal circuitry in MCF8316A is

powered through the buck regulator,MCF8316A goes into reset state whenever buck UV event occurs.

7.3.22.4 VCP Charge Pump Undervoltage Lockout (CPUV)

If at any time the voltage on the VCP pin (charge pump) falls lower than the V_CPUVthreshold, all the integrated

FETs are disabled and the nFAULT pin is driven low. The DRIVER_FAULT and VCP_UV bits are set to 1b in

the status registers. Normal operation resumes (driver operation and the nFAULT pin is released) when the VCP

undervoltage condition clears. The VCP_UV bit stays set until cleared through the CLR_FLT bit.

7.3.22.5 Overvoltage Protection (OVP)

If at any time input supply voltage on the VM pins rises higher lower than the V_OVPthreshold voltage, all the

integrated FETs are disabled and the nFAULT pin is driven low. The DRIVER_FAULT and OVP bits are set to

1b in the status registers. Normal operation resumes (driver operation and the nFAULT pin is released) when the

OVP condition clears. The OVP bit stays set until cleared through the CLR_FLT bit. Setting the OVP_EN to 1b

enables this protection feature.

The OVP threshold can be set to 20-V or 32-V based on the OVP_SEL bit.

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V_VM

V_OVP(max) rising

V_OVP(min) rising

V_OVP(max) falling

V_OVP(min) falling

DEVICE ON

DEVICE OFF

DEVICE ON

nFAULT

Time

Figure 7-49. Over Voltage Protection

7.3.22.6 Overcurrent Protection (OCP)

MOSFET overcurrent event is sensed by monitoring the current flowing through FETs. If the current across a

FET exceeds the I_OCPthreshold for longer than the t_OCPdeglitch time, an OCP event is recognized and action

is taken according to the OCP_MODE bit. The I_OCPthreshold is set through the OCP_LVL, the t_{OCP_DEG}is set

through the OCP_DEG and the OCP_MODE bit can operate in four different modes: OCP latched shutdown,

OCP automatic retry, OCP report only and OCP disabled.

7.3.22.6.1 OCP Latched Shutdown (OCP_MODE = 00b)

When an OCP event happens in this mode, all MOSFETs are disabled and the nFAULT pin is driven low. The

DRIVER_FAULT, OCP and corresponding FET's OCP bits are set to 1b in the status registers. Normal operation

resumes (driver operation and the nFAULT pin is released) when the OCP condition clears and a clear fault

command is issued through the CLR_FLT bit.

Peak Current due

to deglitch time

I_OCP

I_OUTx

t_OCP

nFAULT Released

nFAULT Pulled High

Fault Condition

nFAULT

Clear Fault

Time

Figure 7-50. Overcurrent Protection - Latched Shutdown Mode

7.3.22.6.2 OCP Automatic Retry (OCP_MODE = 01b)

When an OCP event happens in this mode, all the FETs are disabled and the nFAULT pin is driven low.

The DRIVER_FAULT, OCP and corresponding FET's OCP bits are set to 1b in the fault status registers.

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Normal operation resumes automatically (gate driver operation and the nFAULT pin is released) after the t_RETRY

(OCP_RETRY) time elapses. The DRIVER_FAULT bit is reset to 0b after the t_RETRYperiod expires. The OCP,

and corresponding FET's OCP bits are set to 1b until cleared through the CLR_FLT bit.

Peak Current due

to deglitch time

I_OCP

I_OUTx

t_RETRY

t_OCP

nFAULT Released

nFAULT Pulled High

Fault Condition

nFAULT

Time

Figure 7-51. Overcurrent Protection - Automatic Retry Mode

7.3.22.6.3 OCP Report Only (OCP_MODE = 10b)

No protective action is taken when an OCP event happens in this mode. The overcurrent event is reported

by setting the DRIVER_FAULT, OCP, and corresponding FET's OCP bits to 1b in the fault status registers. If

ALARM_PIN_DIS is set to 0b, nFAULT is driven low to report the fault. If ALARM_PIN_DIS is set to 1b, nFAULT

is not driven low. The device continues to operate as usual. The external controller manages the overcurrent

condition by acting appropriately. The reporting clears when the OCP condition clears and a clear fault command

is issued through the CLR_FLT bit.

7.3.22.6.4 OCP Disabled (OCP_MODE = 11b)

No action is taken when an OCP event happens in this mode.

7.3.22.7 Buck Overcurrent Protection

The buck overcurrent event is sensed by monitoring the current flowing through high-side MOSFET of the buck

regulator. If the current through the high-side MOSFET exceeds the I_{BK_OCP}threshold for a time longer than the

deglitch time (t_{OCP_DEG}), a buck OCP event is recognized. MCF8316A goes into reset state whenever buck OCP

event occurs, since the internal circuitry in MCF8316A is powered from the buck regulator output.

7.3.22.8 Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)

The hardware lock detection current limit function provides a configurable threshold for limiting the current

to prevent damage to the system. The output of current sense amplifier is connected to hardware

comparator. If at any time, the voltage on the output of CSA exceeds HW_LOCK_ILIMIT threshold for a time

longer than t_{HW_LOCK_ILIMIT}, a HW_LOCK_ILIMIT event is recognized and action is taken according to the

HW_LOCK_ILIMIT_MODE. The threshold is set through HW_LOCK_ILIMIT, the t_{HW_LCK_ILIMIT}is set through the

HW_LOCK_ILIMIT_DEG. HW_LOCK_ILIMIT_MODE bit can operate in four different modes: HW_LOCK_ILIMIT

latched shutdown, HW_LOCK_ILIMIT automatic retry, HW_LOCK_ILIMIT report only, and HW_LOCK_ILIMIT

disabled.

7.3.22.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xxb)

When a HW_LOCK_ILIMIT event happens in this mode, the status of MOSFET will be configured by

HW_LOCK_ILIMIT_MODE and nFAULT is driven low. Status of MOSFETs during HW_LOCK_ILIMIT:

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•

HW_ LOCK_ILIMIT_MODE = 0000b: All MOSFETs are turned OFF.

HW_ LOCK_ILIMIT_MODE = 0001b: Some of the MOSFETs which are switching are turned OFF while the

rest stay ON till inductive energy is completely recirculated.

•

HW_LOCK_ILIMIT_MODE = 0010b: All-high side MOSFETs are turned ON.

HW_LOCK_ILIMIT_MODE = 0011b: All-low side MOSFETs are turned ON.

The CONTROLLER_FAULT and HW_LOCK_ILIMIT bits are set to 1b in the fault status registers. Normal

operation resumes (gate driver operation and the nFAULT pin is released) when the HW_LOCK_ILIMIT condition

clears and a clear fault command is issued through the CLR_FLT bit.

7.3.22.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 01xxb)

When a HW_LOCK_ILIMIT event happens in this mode, the status of MOSFET will be configured by

HW_LOCK_ILIMIT_MODE and nFAULT is driven low. Status of MOSFET during HW_LOCK_ILIMIT:

•

HW_LOCK_ILIMIT_MODE = 0100b: All MOSFETs are turned OFF.

HW_LOCK_ILIMIT_MODE = 0101b: Some of the MOSFETs which are switching are turned OFF while the

rest stay ON till inductive energy is completely recirculated.

•

HW_LOCK_ILIMIT_MODE = 0110b: All high-side MOSFETs are turned ON

HW_LOCK_ILIMIT_MODE = 0111b: All low-side MOSFETs are turned ON

The CONTROLLER_FAULT and HW_LOCK_ILIMIT bits are set to 1b in the fault status registers. Normal

operation resumes automatically (gate driver operation and the nFAULT pin is released) after the t_{LCK_RETRY}

(configured by LCK_RETRY) time lapses. The CONTROLLER_FAULT and HW_LOCK_ILIMIT bits are reset to

0b after the t_{LCK_RETRY}period expires.

7.3.22.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 1000b)

No protective action is taken when a HW_ LOCK_ILIMIT event happens in this mode. The hardware lock

detection current limit event is reported by setting the CONTROLLER_FAULT and HW_LOCK_ILIMIT bits to

1b in the fault status registers. If ALARM_PIN_DIS is set to 0b, nFAULT is driven low to report the fault. If

ALARM_PIN_DIS is set to 1b, nFAULT is not driven low. The gate drivers continue to operate. The external

controller manages this condition by acting appropriately. The reporting clears when the HW_LOCK_ILIMIT

condition clears and a clear fault command is issued through the CLR_FLT bit.

7.3.22.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE= 1xx1b)

No action is taken when a HW_LOCK_ILIMIT event happens in this mode.

7.3.22.9 Thermal Warning (OTW)

If the die temperature exceeds the thermal warning limit (T_OTW), the OT and OTW bits in the status register are

set to 1b. The reporting of OTW on the nFAULT pin can be enabled by setting OTW_REP to 1b. The device

performs no additional action and continues to function. In this case, the nFAULT pin is released when the die

temperature decreases below the hysteresis point of the thermal warning limit (T_OTW- T_{OTW_HYS}). The OTW bit

remains set until cleared through the CLR_FLT bit and the die temperature is lower than thermal warning limit.

(T_OTW).

Note

Over-temperature warning (OTW) is not reported on nFAULT pin by default.

7.3.22.10 Thermal Shutdown (TSD)

If the die temperature exceeds the thermal shutdown limit (T_TSD), all the FETs are disabled, the charge pump

is shut down, and the nFAULT pin is driven low. In addition, the DRIVER_FAULT, OT and TSD bit in the status

register are set to 1b. Normal operation resumes (driver operation and the nFAULT pin is released) when the

die temperature decreases below the hysteresis point of the thermal shutdown limit (T_TSD- T_{TSD_HYS}). The TSD

bit stays latched high indicating that a thermal event occurred until a clear fault command is issued through the

CLR_FLT bit. This protection feature cannot be disabled.

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7.3.22.11 Motor Lock (MTR_LCK)

The MCF8316A continuously checks for different motor lock conditions (see Motor Lock Detection) during motor

operation. When one of the enabled lock condition happens, a MTR_LCK event is recognized and action is

taken according to the MTR_LCK_MODE.

All locks can be enabled or disabled individually and retry times can be configured through LCK_RETRY .

MTR_LCK_MODE bit can operate in four different modes: MTR_LCK latched shutdown, MTR_LCK automatic

retry, MTR_LCK report only and MTR_LCK disabled.

7.3.22.11.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)

When a MTR_LCK event happens in this mode, the status of MOSFETs will be configured by MTR_LCK_MODE

and nFAULT is driven low. Status of MOSFETs during MTR_LCK:

•

MTR_LCK_MODE = 0000b: All MOSFETs are turned OFF.

MTR_LCK_MODE = 0001b: Some of the MOSFETs which are switching are turned OFF while the rest stay

ON till inductive energy is completely recirculated.

•

MTR_LCK_MODE = 0010b: All high-side MOSFETs are turned ON.

MTR_LCK_MODE = 0011b: All low-side MOSFETs are turned ON.

The CONTROLLER_FAULT, MTR_LCK and respective motor lock condition bits are set to 1b in the fault status

registers. Normal operation resumes (gate driver operation and the nFAULT pin is released) when the MTR_LCK

condition clears and a clear fault command is issued through the CLR_FLT bit.

7.3.22.11.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)

When a MTR_LCK event happens in this mode, the status of MOSFETs will be configured by MTR_LCK_MODE

and nFAULT is driven low. Status of MOSFETs during MTR_LCK:

•

MTR_LCK_MODE = 0100b: All MOSFETs are turned OFF.

MTR_LCK_MODE = 0101b: Some of the MOSFETs which are switching are turned OFF while the rest stay

ON till inductive energy is completely recirculated.

•

MTR_LCK_MODE = 0110b: All high-side MOSFETs are turned ON.

MTR_LCK_MODE = 0111b: All low-side MOSFETs are turned ON.

The CONTROLLER_FAULT, MTR_LCK and respective motor lock condition bits are set to 1b in the fault status

registers. Normal operation resumes automatically (gate driver operation and the nFAULT pin is released) after

the t_{LCK_RETRY}(configured by LCK_RETRY) time lapses. The CONTROLLER_FAULT, MTR_LCK and respective

motor lock condition bits are reset to 0b after the t_{LCK_RETRY}period expires.

7.3.22.11.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)

No protective action is taken when a MTR_LCK event happens in this mode. The motor lock event is reported by

setting the CONTROLLER_FAULT, MTR_LCK and respective motor lock condition bits to 1b in the fault status

registers. If ALARM_PIN_DIS is set to 0b, nFAULT is driven low to report the fault. If ALARM_PIN_DIS is set

to 1b, nFAULT is not driven low. The gate drivers continue to operate. The external controller manages this

condition by acting appropriately. The reporting clears when the MTR_LCK condition clears and a clear fault

command is issued through the CLR_FLT bit.

7.3.22.11.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)

No action is taken when a MTR_LCK event happens in this mode.

7.3.22.12 Motor Lock Detection

The MCF8316A provides different lock detect mechanisms to determine if the motor is in a locked state. Multiple

detection mechanisms work together to ensure the lock condition is detected quickly and reliably. In addition to

detecting if there is a locked motor condition, the MCF8316A can also identify and take action if there is no motor

connected to the system. Each of the lock detect mechanisms and the no-motor detection can be disabled by

their respective register bits (LOCK1/2/3_EN).

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7.3.22.12.1 Lock 1: Abnormal Speed (ABN_SPEED)

MCF8316A monitors the speed continuously and at any time the speed exceeds LOCK_ABN_SPEED, an

ABN_SPEED lock event is recognized and action is taken according to the MTR_LCK_MODE.

The threshold is set through the LOCK_ABN_SPEED register. ABN_SPEED lock can be enabled/disabled by

LOCK1_EN.

7.3.22.12.2 Lock 2: Abnormal BEMF (ABN_BEMF)

MCF8316A estimates back-EMF in order to run motor optimally in closed loop. This estimated back-EMF

is compared against the expected back-EMF calculated using the estimated speed and the BEMF constant.

Whenever motor is stalled the estimated back-EMF is inaccurate due to lower back-EMF at low speed. When the

difference between estimated and expected back-EMF exceeds ABNORMAL_BEMF_THR, an abnormal BEMF

fault is triggered and action is taken according to the MTR_LCK_MODE.

ABN_BEMF lock can be enabled/disabled by LOCK2_EN.

7.3.22.12.3 Lock3: No-Motor Fault (NO_MTR)

The MCF8316A continuously monitors phase currents on all three phases; if any phase current stays below

NO_MTR_THR for 500ms, a NO_MTR event is recognized. The response to the NO_MTR event is configured

through MTR_LCK_MODE. NO_MTR lock can be enabled/disabled by LOCK3_EN.

7.3.22.13 MPET Faults

An error during resistance and inductance measurement is reported using MPET_IPD_FAULT. The

MPET_IPD_FAULT gets triggered when the IPD timer overflows due to unsuccessful attempt to ramp up the

current to the threshold value, same as explained in Section 7.3.22.14. The fault typically gets triggered when

there is no motor connected to MCF8316 or when the MPET IPD current threshold is set high for motors with

high resistance.

An error during BEMF constant measurement is reported using MPET_BEMF_FAULT. This fault gets triggered

when the measured back EMF is less than the threshold set in STAT_DETECT_THR. One example of such fault

scenario can be the motor stall while running in open loop due to incorrect open loop configuration used.

7.3.22.14 IPD Faults

The MCF8316A uses 12-bit timers to estimate the time during the current ramp up and ramp down during IPD,

when the motor start-up is configured as IPD (MTR_STARTUP is set to 10b). During IPD, the algorithm checks

for a successful current ramp-up to IPD_CURR_THR, starting with an IPD clock of 10MHz; if unsuccessful

(timer overflow before current reaches IPD_CURR_THR), IPD is repeated with lower frequency clocks of 1MHz,

100kHz, and 10kHz sequentially. If the IPD timer overflows (current does not reach IPD_CURR_THR) with

all the four clock frequencies, then the IPD_T1_FAULT gets triggered. Similarly the algorithm check sfor a

successful current decay to zero during IPD current ramp down using all the mentioned IPD clock frequencies. If

the IPD timer overflows (current does not ramp down to zero) in all the four attempts, then the IPD_T2_FAULT

gets triggered. The user can enable IPD timeout (IPD timer overflow) by setting IPD_TIMEOUT_FAULT_EN to

1b.

IPD gives incorrect results if the next IPD pulse is commanded before the complete decay of current due to

present IPD pulse. The MCF8316A can generate a fault called IPD_FREQ_FAULT during such a scenario by

setting IPD_FREQ_FAULT_EN to 1b. The IPD_FREQ_FAULT maybe triggerd if the IPD frequency is too high for

the IPD current limit and the IPD release mode or if the motor inductance is too high for the IPD frequency, IPD

current limit and IPD release mode.

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7.4 Device Functional Modes

7.4.1 Functional Modes

7.4.1.1 Sleep Mode

In sleep mode, the MOSFETs, sense amplifiers, buck regulator, charge pump, AVDD LDO regulator and the

I²C bus are disabled. The device can be configured to enter sleep (instead of standby) mode by configuring

DEV_MODE to 1b. SPEED pin determines entry and exit from sleep state as described in Table 7-6.

Note

During power-up and power-down of the device, the nFAULT pin is held low as the internal regulators

are disabled. After the regulators have been enabled, the nFAULT pin is automatically released.

7.4.1.2 Standby Mode

In standby mode the charge pump, AVDD LDO, buck regulator and I²C bus are active. The device can be

configured to enter standby mode by configuring DEV_MODE to 0b. SPEED pin determines entry and exit from

standby state as described in Table 7-6

7.4.1.3 Fault Reset (CLR_FLT)

In the case of latched faults, the device goes into a partial shutdown state to help protect the power MOSFETs

and system. When the fault condition clears, the device can go to the operating state again by setting the

CLR_FLT to 1b.

Table 7-6. Conditions to Enter or Exit Sleep or Standby Modes

SPEED

COMMAND

MODE

ENTER STANDBY

CONDITION

EXIT FROM STANDBY

CONDITION

EXIT FROM SLEEP

CONDITION

ENTER SLEEP CONDITION

SPEED pin voltage < V_{EN_SB}SPEED pin voltage < V_{EN_SL}SPEED pin voltage > V_{EX_SB}SPEED pin voltage > V_{EX_SL}

Analog

for t_{DET_SB_ANA}

for t_{DET_SL_ANA}

for t_{DET_ANA}

SPEED pin low (V <

V_{DIG_IL}) for t_{DET_SL_PWM}

t_{DET_SL_FREQ}

PWM/

Frequency

SPEED pin low (V < V_{DIG_IL}

for t_{EN_SB_PWM}/ t_{EN_SB_FREQ}

)

SPEED pin high (V > V_{DIG_IH}) SPEED pin high (V > V_{DIG_IH})

/

for t_{DET_PWM}

SPEED pin voltage

< V_{EN_SL}for t >

SLEEP_ENTRY_TIME

DIGITAL_SPEED_CTRL is

programmed as 0.

DIGITAL_SPEED_CTRL is

programmed as non-zero.

SPEED pin voltage > V_{EX_SL}

for t_{DET_ANA}

I²C

7.5 External Interface

7.5.1 DRVOFF Functionality

When DRVOFF pin is driven high, all six MOSFETs are disabled. In this mode, if SPEED pin is high, the charge

pump, AVDD regulator, buck regulator and I²C bus are active; driver faults like OCP will be inactive.

7.5.2 SOX Output

MCF8316A can provide the built-in current sense amplifiers' output on the SOX pin. SOX output is available on

pin 38 and can be configured by PIN_38_CONFIG

7.5.3 Oscillator Source

MCF8316A has a built-in oscillator that is used as the clock source for all digital peripherals and timing

measurements. Default configuration for MCF8316A is to use the internal oscillator and it is sufficient to drive the

motor without need for any external crystal or clock sources.

In case MCF8316A does not meet accuracy requirements of timing measurement or speed loop, then

MCF8316A has an option to support an external clock reference.

In order to improve EMI performance, MCF8316A provides the option of modulating the clock frequency by

enabling Spread Spectrum Modulation (SSM) through SPREAD_SPECTRUM_MODULATION_DIS

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.

7.5.3.1 External Clock Source

Speed loop accuracy of MCF8316A over wide operating temperature range can be improved by providing more

accurate optional clock reference on EXT_CLK pin as shown in Figure 7-52. EXT_CLK will be used to calibrate

internal clock oscillator and match the accuracy of the external clock. External clock source can be selected

by configuring CLK_SEL to 11b and setting EXT_CLK_EN to 1b. The external clock source frequency can be

configured through EXT_CLK_CONFIG.

Internal

Oscillator

(60 MHz)

EXT_CLK

Calibrate

Figure 7-52. External Clock Reference

Note

External clock is optional and can be used when higher clock accuracy is needed. MCF8316A will

always power up using the internal oscillator in all modes.

7.5.4 External Watchdog

MCF8316A provides an external watchdog feature - EXT_WD_EN bit should be set to 1b to enable the external

watchdog. When this feature is enabled, the device waits for a tickle (low to high transition in GPIO mode,

WATCHDOG_TICKLE set to 1b in I²C mode) from the external watchdog input for a configured time interval;

if the time interval between two consecutive tickles is higher than the configured time, a watchdog fault is

triggered. This fault can be configured using EXT_WD_FAULT either as a report only fault or as a latched fault

with outputs in Hi-Z state. The latched fault can be cleared by writing 1b to CLR_FLT. In case, the next tickle

arrives before the configured time interval elapses, the watchdog timer is reset and it begins to wait for the next

tickle. This can be used to continuously monitor the health of an external MCU (which is the external watchdog

input) and put the MCF8316A outputs in Hi-Z in case the external MCU is in an erroneous state.

The external watchdog input is selected using EXT_WD_INPUT and can either be the EXT_WD pin or the I²C

interface . The time interval between two tickles to trigger a watchdog fault is configured by EXT_WD_CONFIG;

there are 4 time settings - 100, 200, 500 and 1000ms for the EXT_WD pin based watchdog and 4 time settings -

1, 2, 5 and 10s for the I²C based watchdog.

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7.6 EEPROM access and I²C interface

7.6.1 EEPROM Access

MCF8316A has 1024 bits (16 rows of 64 bits each) of EEPROM, which are used to store the motor configuration

parameters. Erase operations are row-wise (all 64 bits are erased in a single erase operation), but 32-bit write

and read operations are supported. EEPROM can be written and read using the I²C serial interface but erase

cannot be performed using I²C serial interface. The shadow registers corresponding to the EEPROM are located

at addresses 0x000080-0x0000AE.

Note

MCF8316A allows EEPROM write and read operations only when the motor is not spinning.

7.6.1.1 EEPROM Write

In MCF8316A, EEPROM write procedure is as follows,

1. Write register 0x000080 (ISD_CONFIG) with ISD and reverse drive configuration like resync enable, reverse

drive enable, stationary detect threshold, reverse drive handoff threshold etc.

2. Write register 0x000082 (REV_DRIVE_CONFIG) with reverse drive and active brake configuration like

reverse drive open loop acceleration, active brake current limit, Kp, Ki values etc.

3. Write register 0x000084 (MOTOR_STARTUP1) with motor start-up configuration like start-up method, IPD

parameters, align parameters etc.

4. Write register 0x000086 (MOTOR_STARTUP2) with motor start-up configuration like open loop acceleration,

open loop current limit, first cycle frequency etc.

5. Write register 0x000088 (CLOSED_LOOP1) with motor control configuration like closed loop acceleration,

overmodulation enable, PWM frequency, FG signal parameters etc.

6. Write register 0x00008A (CLOSED_LOOP2) with motor control configuration like motor winding resistance

and inductance, motor stop options, brake speed threshold etc.

7. Write register 0x00008C (CLOSED_LOOP3) with motor control configuration like motor BEMF constant,

current loop Kp, Ki etc.

8. Write register 0x00008E (CLOSED_LOOP4) with motor control configuration like speed loop Kp, Ki and

maximum speed.

9. Write register 0x000090 (FAULT_CONFIG1) with fault control configuration software and hardware current

limits, lock current limit and actions, retry times etc.

10. Write register 0x000092 (FAULT_CONFIG2) with fault control configuration like hardware current limit

actions, OV, UV limits and actions, abnormal speed level, no motor threshold etc.

11. Write registers 0x000094 – 0x00009E (SPEED_PROFILES1-6) with speed profile configuration like profile

type, duty cycle, speed clamp level, duty cycle clamp level etc.

12. Write register 0x0000A0 (INT_ALGO_1) with miscellaneous configuration like ISD run time and timeout,

MPET parameters etc.

13. Write register 0x0000A2 (INT_ALGO_2) with miscellaneous configuration like additional MPET parameters,

IPD high resolution enable, active brake current slew rate, closed loop slow acceleration etc.

14. Write registers 0x0000A4 (PIN_CONFIG1) with pin configuration for speed input mode (analog or PWM),

BRAKE pin mode etc.

15. Write registers 0x0000A6 and 0x0000A8 (DEVICE_CONFIG1 and DEVICE_CONFIG2) with device

configuration like pins 36, 37 configuration, pin 38 configuration, dynamic CSA gain enable, dynamic voltage

gain enable, clock source select, speed range select etc.

16. Write register 0x0000AA (PERI_CONFIG1) with peripheral configuration like dead time, bus current limit,

DIR input, SSM enable etc.

17. Write registers 0x0000AC and 0x0000AE (GD_CONFIG1 and GD_CONFIG2) with gate driver configuration

like slew rate, CSA gain, OCP level, mode, OVP enable, level, buck voltage level, buck current limit etc.

18. Write 0x8A500000 into register 0x0000EA to write the shadow register(0x000080-0x0000AE) values into the

EEPROM.

19. Wait for 100ms for the EEPROM write operation to complete

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Steps 1-17 can be selectively executed based on registers/parameters that need to be modified. After all shadow

registers have been updated with the required values, step 18 should be executed to copy the contents of the

shadow registers into the EEPROM.

7.6.1.2 EEPROM Read

In MCF8316A, EEPROM read procedure is as follows,

1. Write 0x40000000 into register 0x0000EA to read the EEPROM data into the shadow registers

(0x000080-0x0000AE).

2. Wait for 100ms for the EEPROM read operation to complete.

3. Read the shadow register values,1 or 2 registers at a time, using the I²C read command as explained

in Section 7.6.2. Shadow register addresses are in the range of 0x000080-0x0000AE. Register address

increases in steps of 2 for 32-bit read operation (since each address is a 16-bit location).

7.6.2 I²C Serial Interface

MCF8316A interfaces with an external MCU over an I²C serial interface. MCF8316A is an I²C target to be

interfaced with a controller. External MCU can use this interface to read/write from/to any non-reserved register

in MCF8316A

Note

For reliable communication, a 100-µs delay should be used between every byte transferred over the

I²C bus.

7.6.2.1 I²C Data Word

The I²C data word format is shown in Table 7-7.

Table 7-7. I²C Data Word Format

TARGET_ID

R/W

CONTROL WORD

DATA

CRC-8

A6 - A0

W0

CW23 - CW0

D15 / D31/ D63 - D0

C7 - C0

Target ID and R/W Bit: The first byte includes the 7-bit I²C target ID (0x01), followed by the read/write command

bit. Every packet in MCF8316A the communication protocol starts with writing a 24-bit control word and hence

the R/W bit is always 0.

24-bit Control Word: The Target Address is followed by a 24-bit control bit. The control word format is shown in

Table 7-8.

Table 7-8. 24-bit Control Word Format

OP_R/W

CRC_EN

DLEN

MEM_SEC

MEM_PAGE

MEM_ADDR

CW23

CW22

CW21- CW20

CW19 - CW16

CW15 - CW12

CW11 - CW0

Each field in the control word is explained in detail below.

OP_R/W – Read/Write: R/W bit gives information on whether this is a read operation or write operation.

Bit value 0 indicates it is a write operation. Bit value 1 indicates it is a read operation. For write operation,

MCF8316A will expect data bytes to be sent after the 24-bit control word. For read operation, MCF8316A will

expect an I²C read request with repeated start or normal start after the 24-bit control word.

CRC_EN – Cyclic Redundancy Check(CRC) Enable: MCF8316A supports CRC to verify the data integrity.

This bit controls whether the CRC feature is enabled or not.

DLEN – Data Length: DLEN field determines the length of the data that will be sent by external MCU to

MCF8316A. MCF8316A protocol supports three data lengths: 16-bit, 32-bit and 64-bit.

Table 7-9. Data Length Configuration

DLEN Value

Data Length

00b

16-bit

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Table 7-9. Data Length Configuration (continued)

DLEN Value

Data Length

01b

10b

11b

32-bit

64-bit

Reserved

MEM_SEC – Memory Section: Each memory location in MCF8316A is addressed using three separate entities

in the control word – Memory Section, Memory Page, Memory Address. Memory Section is a 4-bit field which

denotes the memory section to which the memory location belongs like RAM, ROM etc.

MEM_PAGE – Memory Page: Memory page is a 4-bit field which denotes the memory page to which the

memory location belongs.

MEM_ADDR – Memory Address: Memory address is the last 12-bits of the address. The complete 22-bit

address is constructed internally by MCF8316A using all three fields – Memory Section, Memory Page, Memory

Address. For memory locations 0x000000-0x000800, memory section is 0x0, memory page is 0x0 and memory

address is the lowest 12 bits(0x000 for 0x000000, 0x080 for 0x000080 and 0x800 for 0x000800)

Data Bytes: For a write operation to MCF8316A, the 24-bit control word is followed by data bytes. The DLEN

field in the control word should correspond with the number of bytes sent in this section.

CRC Byte: If the CRC feature is enabled in the control word, CRC byte has to be sent at the end of a write

transaction. Procedure to calculate CRC is explained in CRC Byte Calculation below.

7.6.2.2 I²C Write Operation

MCF8316A write operation over I²C involves the following sequence.

1. I²C start condition.

2. The sequence starts with I²C target start byte, made up of 7-bit target ID (0x01) to identify the MCF8316A

along with the R/W bit set to 0.

3. The start byte is followed by 24-bit control word. Bit 23 in the control word has to be 0 as it is a write

operation.

4. The 24-bit control word is then followed by the data bytes. The length of the data byte depends on the DLEN

field.

a. While sending data bytes, the LSB byte is sent first. Refer below examples for more details.

b. 16-bit/32-bit write – The data sent is written to the address mentioned in Control Word.

c. 64-bit Write – 64-bit is treated as two 32-bit writes. The address mentioned in Control word is taken as

Addr 0. Addr 1 is calculating internally by MCF8316A by incrementing Addr 0 by 2. A total of 8 data

bytes are sent. The first 4 bytes (sent in LSB first way) are written to Addr 0 and the next 4 bytes are

written to Addr 1.

5. If CRC is enabled, the packet ends with a CRC byte. CRC is calculated for the entire packet (Target ID + W

bit, Control Word, Data Bytes).

6. I²C stop condition.

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2 / 4 / 8 DATA BYTES

Write – without CRC

TARGET

ID [6:0]

CONTROL

WORD [23:16]

CONTROL

WORD [15:8]

CONTROL

WORD [7:0]

DATA

BYTES

DATA

BYTES

S

0

ACK

P

2 / 4 / 8 DATA BYTES

Write – with CRC

TARGET

CONTROL

WORD [23:16]

CONTROL

WORD [15:8]

CONTROL

WORD [7:0]

DATA

BYTES

DATA

S

0

ACK

ACK CRC ACK

P

ID [6:0]

BYTES

CRC includes {TARGET ID,0}, CONTROL WORD[23:0], DATA BYTES

Figure 7-53. I²C Write Operation Sequence

7.6.2.3 I²C Read Operation

MCF8316A read operation over I²C involves the following sequence.

1. I²C start condition.

2. The sequence starts with I²C target Start Byte.

3. The Start Byte is followed by 24-bit Control Word. Bit 23 in the control word has to be 1 as it is a read

operation.

4. The control word is followed by a repeated start or normal start.

5. MCF8316A sends the data bytes on SDA. The number of bytes sent by MCF8316A depends on the DLEN

field value in the control word.

a. While sending data bytes, the LSB byte is sent first. Refer the examples below for more details.

b. 16-bit/32-bit Read – The data from the address mentioned in Control Word is sent back.

c. 64-bit Read – 64-bit is treated as two 32-bit read. The address mentioned in Control Word is taken as

Addr 0. Addr 1 is calculating internally by MCF8316A by incrementing Addr 0 by 2. A total of 8 data

bytes are sent by MCF8316A. The first 4 bytes (sent in LSB first way) are read from Addr 0 and the next

4 bytes are read from Addr 1.

d. MCF8316A takes some time to process the control word and read data from the given address. This

involves some delay. It is quite possible that the repeated start with Target ID will be NACK’d. If the

I²C read request has been NACK’d by MCF8316A, retry after few cycles. During this retry, it is not

necessary to send the entire packet along with the control word. It is sufficient to send only the start

condition with target ID and read bit.

6. If CRC is enabled, then MCF8316A sends an additional CRC byte at the end. If CRC is enabled, external

MCU I²C controller has to read this additional byte before sending the stop bit. CRC is calculated for the

entire packet (Target ID + W bit, Control Word, Target ID + R bit, Data Bytes).

7. I²C stop condition.

2 / 4 / 8 DATA BYTES

Read – without CRC

TARGET

ID [6:0]

CONTROL

WORD [23:16]

CONTROL

WORD [15:8]

CONTROL

WORD [7:0]

TARGET

ID [6:0]

DATA

BYTES

DATA

BYTES

S

0

ACK

ACK RS

1

ACK

P

Read – with CRC

TARGET

2 / 4 / 8 DATA BYTES

CONTROL

WORD [23:16]

CONTROL

WORD [15:8]

CONTROL

WORD [7:0]

TARGET

ID [6:0]

DATA

BYTES

DATA

S

0

ACK

ACK RS

1

ACK

ACK CRC ACK

P

ID [6:0]

BYTES

CRC includes {TARGET ID,0}, CONTROL WORD[23:0], {TARGET ID,1}, DATA BYTES

Figure 7-54. I²C Read Operation Sequence

7.6.2.4 Examples of MCF8316A I²C Communication Protocol Packets

All values used in this example section are in hex format. I²C target ID used in the examples is 0x01.

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Example for 32-bit Write Operation: Address – 0x00000080, Data – 0x1234ABCD, CRC Byte – 0x45 (Sample

value; does not match with the actual CRC calculation)

Table 7-10. Example for 32-bit Write Operation Packet

Start Byte

Control Word 0

Control Word 1

Control Data Bytes

Word 2

CRC

Target

ID

I²C

Write

OP_R/ CRC_E DLEN

MEM_S MEM_P MEM_A MEM_A DB0

EC AGE DDR DDR

DB1

DB2

DB3

CRC

Byte

W

N

A6-A0

W0

CW23

CW22

CW21- CW19- CW15- CW11- CW7-

D7-D0

C7-C0

CW20

CW16

CW12

CW8

CW0

0x80

0x01

0x02

0x0

0x1

0x0

0xCD

0xAB

0x34

0x12

0x45

0x50

0x00

Example for 64-bit Write Operation: Address - 0x00000080, Data Address 0x00000080 - Data 0x01234567,

Data Address 0x00000082 – Data 0x89ABCDEF, CRC Byte – 0x45 (Sample value; does not match with the

actual CRC calculation)

Table 7-11. Example for 64-bit Write Operation Packet

Start Byte

Control Word 0

Control Word 1

Control Word Data Bytes

2

CRC

Target I²C

OP_R/W CRC_EN DLEN MEM_SEC MEM_PAGE MEM_ADDR MEM_ADDR DB0 - DB7

CRC

Byte

ID

Write

A6-A0 W0

CW23

CW22

0x1

CW21- CW19-

CW20 CW16

CW15-

CW12

CW11-CW8

0x0

CW7-CW0

[D7-D0] x 8

C7-C0

0x01

0x02

0x0

0x2

0x0

0x80

0x67452301EFCDAB89

0x45

0x60

0x00

Example for 32-bit Read Operation: Address – 0x00000080, Data – 0x1234ABCD, CRC Byte – 0x56 (Sample

value; does not match with the actual CRC calculation)

Table 7-12. Example for 32-bit Read Operation Packet

Start Byte

Control Word 0

Control Word 1 Control Start Byte

Word 2

Byte 0 Byte 1 Byte 2 Byte 3 Byte 4

Target I²C

R/W

CRC_ DLEN MEM_ MEM_ MEM_ MEM_ Target I²C

EN SEC PAGE ADDR ADDR ID Read

DB0

DB1

DB2

DB3

CRC

Byte

ID

Write

A6-A0 W0

CW23 CW22 CW21- CW19- CW15- CW11- CW7- A6-A0 W0

D7-D0 D7-D0 D7-D0 D7-D0 C7-C0

CW20 CW16 CW12 CW8

CW0

0x80

0x01

0x02

0x0

0x1

0x0

0x01

0x03

0x1

0xCD 0xAB

0x34

0x12

0x56

0xD0

0x00

7.6.2.5 Internal Buffers

MCF8316A uses buffers internally to store the data received on I²C. Highest priority is given to collecting data on

the I²C Bus. There are 2 buffers (ping-pong) for I²C Rx Data and 2 buffers (ping-pong) for I²C Tx Data.

A write request from external MCU is stored in Rx Buffer 1 and then the parsing block is triggered to work on

this data in Rx Buffer 1. While MCF8316A is processing a write packet from Rx Buffer 1, if there is another new

read/write request, the entire data from the I²C bus is stored in Rx Buffer 2 and it will be processed after the

current request.

MCF8316A can accommodate a maximum of two consecutive read/write requests. If MCF8316A is busy due to

high priority interrupts, the data sent will be stored in internal buffers (Rx Buffer 1 and Rx Buffer 2). At this point,

if there is a third read/write request, the Target ID will be NACK’d as the buffers are already full.

During read operations, the read request is processed and the read data from the register is stored in the Tx

Buffer along with the CRC byte, if enabled. Now if the external MCU initiates an I²C Read (Target ID + R bit), the

data from this Tx Buffer is sent over I²C. Since there are two Tx Buffers, register data from 2 MCF8316A reads

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can be buffered. Given this scenario, if there is a third read request, the control word will be stored in the Rx

Buffer 1, but it will not be processed by MCF8316A as the Tx Buffers are full.

Once a data is read from Tx Buffer, the data is no longer stored in the Tx buffer. The buffer is cleared and it

becomes available for the next data to be stored. If the read transaction was interrupted in between and if the

MCU had not read all the bytes, external MCU can initiate another I²C read (only I²C read, without any control

word information) to read all the data bytes from first.

7.6.2.6 CRC Byte Calculation

An 8-bit CCIT polynomial (x⁸+ x²+ x + 1) is used for CRC computation.

CRC Calculation in Write Operation: When the external MCU writes to MCF8316A, if the CRC is enabled, the

external MCU has to compute an 8-bit CRC byte and add the CRC byte at the end of the data. MCF8316A will

compute CRC using the same polynomial internally and if there is a mismatch, the write request is discarded.

Input data for CRC calculation by external MCU for write operation are listed below:

1. Target ID + write bit.

2. Control word – 3 bytes

3. Data bytes – 2/4/8 bytes

CRC Calculation in Read Operation: When the external MCU reads from MCF8316A, if the CRC is enabled,

MCF8316A sends the CRC byte at the end of the data. The CRC computation in read operation involves the

start byte, control words sent by external MCU along with data bytes sent by MCF8316A. Input data for CRC

calculation by external MCU to verify the data sent by MCF8316A are listed below :

1. Target ID + write bit

2. Control word – 3 bytes

3. Target ID + read bit

4. Data bytes – 2/4/8 bytes

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7.7 EEPROM (Non-Volatile) Register Map

7.7.1 Algorithm_Configuration Registers

ALGORITHM_CONFIGURATION Registers lists the memory-mapped registers for the Algorithm_Configuration

registers. All register offset addresses not listed in ALGORITHM_CONFIGURATION Registers should be

considered as reserved locations and the register contents should not be modified.

Table 7-13. ALGORITHM_CONFIGURATION Registers

Address Acronym

ISD_CONFIG

Register Name

Section

80h

82h

84h

86h

88h

8Ah

8Ch

8Eh

94h

96h

98h

9Ah

9Ch

9Eh

ISD Configuration

Section 7.7.1.1

Section 7.7.1.2

Section 7.7.1.3

Section 7.7.1.4

Section 7.7.1.5

Section 7.7.1.6

Section 7.7.1.7

Section 7.7.1.8

Section 7.7.1.9

Section 7.7.1.10

Section 7.7.1.11

Section 7.7.1.12

Section 7.7.1.13

Section 7.7.1.14

REV_DRIVE_CONFIG

MOTOR_STARTUP1

MOTOR_STARTUP2

CLOSED_LOOP1

Reverse Drive Configuration

Motor Startup Configuration 1

Motor Startup Configuration 2

Closed Loop Configuration 1

Closed Loop Configuration 2

Closed Loop Configuration 3

Closed Loop Configuration 4

Speed Profile Configuration 1

Speed Profile Configuration 2

Speed Profile Configuration 3

Speed Profile Configuration 4

Speed Profile Configuration 5

Speed Profile Configuration 6

CLOSED_LOOP2

CLOSED_LOOP3

CLOSED_LOOP4

SPEED_PROFILES1

SPEED_PROFILES2

SPEED_PROFILES3

SPEED_PROFILES4

SPEED_PROFILES5

SPEED_PROFILES6

Complex bit access types are encoded to fit into small table cells. Algorithm_Configuration Access Type Codes

shows the codes that are used for access types in this section.

Table 7-14. Algorithm_Configuration Access Type

Codes

Access Type

Read Type

R

Code

Description

R

Read

Write Type

W

Write

Reset or Default Value

-n

Value after reset or the default

value

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7.7.1.1 ISD_CONFIG Register (Address = 80h) [Reset = 00000000h]

ISD_CONFIG is shown in ISD_CONFIG Register and described in ISD_CONFIG Register Field Descriptions.

Return to the ALGORITHM_CONFIGURATION Registers.

Register to configure initial speed detect settings

Figure 7-55. ISD_CONFIG Register

31

30

29

28

27

26

25

24

PARITY

R/W-0h

ISD_EN

R/W-0h

BRAKE_EN

R/W-0h

HIZ_EN

R/W-0h

RVS_DR_EN

R/W-0h

RESYNC_EN

R/W-0h

FW_DRV_RESYN_THR

R/W-0h

23

22

21

20

19

18

17

16

FW_DRV_RESYN_THR

R/W-0h

BRK_MODE

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

BRK_TIME

R/W-0h

15

14

13

12

11

10

9

8

BRK_TIME

HIZ_TIME

R/W-0h

STAT_DETECT

_THR

R/W-0h

6

R/W-0h

0

7

5

4

3

2

1

STAT_DETECT_THR

REV_DRV_HANDOFF_THR

REV_DRV_OPEN_LOOP_CURR

ENT

R/W-0h

Table 7-15. ISD_CONFIG Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

31

30

PARITY

ISD_EN

0h

Parity bit

0h

ISD enable

0h = Disable

1h = Enable

29

28

27

26

BRAKE_EN

HIZ_EN

R/W

0h

Brake enable

0h = Disable

1h = Enable

Hi-Z enable

0h = Disable

1h = Enable

RVS_DR_EN

RESYNC_EN

Reverse drive enable

0h = Disable

1h = Enable

Resynchronization enable

0h = Disable

1h = Enable

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Table 7-15. ISD_CONFIG Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

25-22

FW_DRV_RESYN_THR

R/W

0h

Minimum speed threshold to resynchronize to close loop (% of

MAX_SPEED)

0h = 5%

1h = 10%

2h = 15%

3h = 20%

4h = 25%

5h = 30%

6h = 35%

7h = 40%

8h = 45%

9h = 50%

Ah = 55%

Bh = 60%

Ch = 70%

Dh = 80%

Eh = 90%

Fh = 100%

21

BRK_MODE

R/W

0h

Brake mode

0h = All three high side FETs turned ON

1h = All three low side FETs turned ON

20

RESERVED

BRK_TIME

R/W

0h

Reserved

19-17

16-13

Brake time

0h = 10 ms

1h = 50 ms

2h = 100 ms

3h = 200 ms

4h = 300 ms

5h = 400 ms

6h = 500 ms

7h = 750 ms

8h = 1 s

9h = 2 s

Ah = 3 s

Bh = 4 s

Ch = 5 s

Dh = 7.5 s

Eh = 10 s

Fh = 15 s

78

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Table 7-15. ISD_CONFIG Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

12-9

HIZ_TIME

R/W

0h

Hi-Z time

0h = 10 ms

1h = 50 ms

2h = 100 ms

3h = 200 ms

4h = 300 ms

5h = 400 ms

6h = 500 ms

7h = 750 ms

8h = 1 s

9h = 2 s

Ah = 3 s

Bh = 4 s

Ch = 5 s

Dh = 7.5 s

Eh = 10 s

Fh = 15 s

8-6

STAT_DETECT_THR

R/W

0h

BEMF threshold to detect if motor is stationary

0h = 50 mV

1h = 75 mV

2h = 100 mV

3h = 250 mV

4h = 500 mV

5h = 750 mV

6h = 1000 mV

7h = 1500 mV

5-2

REV_DRV_HANDOFF_T R/W

HR

0h

Speed threshold used to transition to open loop during reverse

deceleration (% of MAX_SPEED)

0h = 2.5%

1h = 5%

2h = 7.5%

3h = 10%

4h = 12.5%

5h = 15%

6h = 20%

7h = 25%

8h = 30%

9h = 40%

Ah = 50%

Bh = 60%

Ch = 70%

Dh = 80%

Eh = 90%

Fh = 100%

1-0

REV_DRV_OPEN_LOOP R/W

_CURRENT

0h

Open loop current limit during speed reversal

0h = 1.5 A

1h = 2.5 A

2h = 3.5 A

3h = 5.0 A

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7.7.1.2 REV_DRIVE_CONFIG Register (Address = 82h) [Reset = 00000000h]

REV_DRIVE_CONFIG is shown in REV_DRIVE_CONFIG Register and described in REV_DRIVE_CONFIG

Register Field Descriptions.

Return to the ALGORITHM_CONFIGURATION Registers.

Register to configure reverse drive settings

Figure 7-56. REV_DRIVE_CONFIG Register

31

30

29

28

27

26

25

24

PARITY

R/W-0h

REV_DRV_OPEN_LOOP_ACCEL_A1

R/W-0h

REV_DRV_OPEN_LOOP_ACCEL_A2

R/W-0h

23

22

21

20

19

18

17

16

REV_DRV_OP

EN_LOOP_AC

CEL_A2

ACTIVE_BRAKE_CURRENT_LIMIT

ACTIVE_BRAKE_KP

R/W-0h

15

R/W-0h

14

13

12

11

3

10

2

9

8

ACTIVE_BRAKE_KP

R/W-0h

ACTIVE_BRAKE_KI

R/W-0h

7

6

5

4

1

0

ACTIVE_BRAKE_KI

R/W-0h

Table 7-16. REV_DRIVE_CONFIG Register Field Descriptions

Bit

31

Field

PARITY

Type

Reset

Description

R/W

0h

Parity bit

30-27

REV_DRV_OPEN_LOOP R/W

_ACCEL_A1

0h

Open loop acceleration coefficient A1 during reverse drive

0h = 0.01 Hz/s

1h = 0.05 Hz/s

2h = 1 Hz/s

3h = 2.5 Hz/s

4h = 5 Hz/s

5h = 10 Hz/s

6h = 25 Hz/s

7h = 50 Hz/s

8h = 75 Hz/s

9h = 100 Hz/s

Ah = 250 Hz/s

Bh = 500 Hz/s

Ch = 750 Hz/s

Dh = 1000 Hz/s

Eh = 5000 Hz/s

Fh = 10000 Hz/s

80

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Table 7-16. REV_DRIVE_CONFIG Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

26-23

REV_DRV_OPEN_LOOP R/W

_ACCEL_A2

0h

Open loop acceleration coefficient A2 during reverse drive

0h = 0.0 Hz/s2

1h = 0.05 Hz/s2

2h = 1 Hz/s2

3h = 2.5 Hz/s2

4h = 5 Hz/s2

5h = 10 Hz/s2

6h = 25 Hz/s2

7h = 50 Hz/s2

8h = 75 Hz/s2

9h = 100 Hz/s2

Ah = 250 Hz/s2

Bh = 500 Hz/s2

Ch = 750 Hz/s2

Dh = 1000 Hz/s2

Eh = 5000 Hz/s2

Fh = 10000 Hz/s2

22-20

ACTIVE_BRAKE_CURRE R/W

NT_LIMIT

0h

Bus current limit during active braking

0h = 0.5 A

1h = 1 A

2h = 2 A

3h = 3 A

4h = 4 A

5h = 5 A

6h = 6 A

7h = 7 A

19-10

9-0

ACTIVE_BRAKE_KP

ACTIVE_BRAKE_KI

R/W

0h

10-bit value for active braking loop Kp. Kp = ACTIVE_BRAKE_KP /

2⁷

10-bit value for active braking loop Ki. Ki = ACTIVE_BRAKE_KI / 2⁹

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7.7.1.3 MOTOR_STARTUP1 Register (Address = 84h) [Reset = 00000000h]

MOTOR_STARTUP1 is shown in MOTOR_STARTUP1 Register and described in MOTOR_STARTUP1 Register

Field Descriptions.

Return to the ALGORITHM_CONFIGURATION Registers.

Register to configure motor startup settings1

Figure 7-57. MOTOR_STARTUP1 Register

31

30

MTR_STARTUP

R/W-0h

29

28

27

26

25

17

24

PARITY

R/W-0h

ALIGN_SLOW_RAMP_RATE

R/W-0h

ALIGN_TIME

R/W-0h

23

22

21

13

5

20

19

18

16

ALIGN_TIME

ALIGN_OR_SLOW_CURRENT_ILIMIT

IPD_CLK_FRE

Q

R/W-0h

14

R/W-0h

8

15

12

4

11

10

2

9

1

IPD_CLK_FREQ

IPD_CURR_THR

IPD_RLS_MOD

E

R/W-0h

3

R/W-0h

0

7

6

IPD_ADV_ANGLE

IPD_REPEAT

R/W-0h

OL_ILIMIT_CO IQ_RAMP_EN ACTIVE_BRAK REV_DRV_CO

NFIG

E_EN

NFIG

R/W-0h

Table 7-17. MOTOR_STARTUP1 Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

31

PARITY

0h

Parity bit

30-29

MTR_STARTUP

0h

Motor start-up method

0h = Align

1h = Double Align

2h = IPD

3h = Slow first cycle

28-25

ALIGN_SLOW_RAMP_RA R/W

TE

0h

Align, slow first cycle and open loop current ramp rate

0h = 0.1 A/s

1h = 1 A/s

2h = 5 A/s

3h = 10 A/s

4h = 15 A/s

5h = 25 A/s

6h = 50 A/s

7h = 100 A/s

8h = 150 A/s

9h = 200 A/s

Ah = 250 A/s

Bh = 500 A/s

Ch = 1000 A/s

Dh = 2000 A/s

Eh = 5000 A/s

Fh = No Limit A/s

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Table 7-17. MOTOR_STARTUP1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

24-21

ALIGN_TIME

R/W

0h

Align time

0h = 10 ms

1h = 50 ms

2h = 100 ms

3h = 200 ms

4h = 300 ms

5h = 400 ms

6h = 500 ms

7h = 750 ms

8h = 1 s

9h = 1.5 s

Ah = 2 s

Bh = 3 s

Ch = 4 s

Dh = 5 s

Eh = 7.5 s

Fh = 10 s

20-17

ALIGN_OR_SLOW_CUR R/W

RENT_ILIMIT

0h

Align or slow first cycle current limit

0h = 0.125 A

1h = 0.25 A

2h = 0.5 A

3h = 1.0 A

4h = 1.5 A

5h = 2.0 A

6h = 2.5 A

7h = 3.0 A

8h = 3.5 A

9h = 4.0 A

Ah = 4.5 A

Bh = 5.0 A

Ch = 5.5 A

Dh = 6.0 A

Eh = 7.0 A

Fh = 8.0 A

16-14

IPD_CLK_FREQ

R/W

0h

IPD clock frequency

0h = 50 Hz

1h = 100 Hz

2h = 250 Hz

3h = 500 Hz

4h = 1000 Hz

5h = 2000 Hz

6h = 5000 Hz

7h = 10000 Hz

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Table 7-17. MOTOR_STARTUP1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

13-9

IPD_CURR_THR

R/W

0h

IPD current threshold

0h = 0.25 A

1h = 0.5 A

2h = 0.75 A

3h = 1.0 A

4h = 1.25 A

5h = 1.5 A

6h = 2.0 A

7h = 2.5 A

8h = 3.0 A

9h = 3.667 A

Ah = 4.0 A

Bh = 4.667 A

Ch = 5.0 A

Dh = 5.333 A

Eh = 6.0 A

Fh = 6.667 A

10h = 7.333 A

11h = 8.0 A

12h = NA

13h = NA

14h = NA

15h = NA

16h = NA

17h = NA

18h = NA

19h = NA

1Ah = NA

1Bh = NA

1Ch = NA

1Dh = NA

1Eh = NA

1Fh = NA

8

IPD_RLS_MODE

IPD_ADV_ANGLE

R/W

0h

IPD release mode

0h = Brake

1h = Tristate

7-6

IPD advance angle

0h = 0°

1h = 30°

2h = 60°

3h = 90°

5-4

IPD_REPEAT

R/W

0h

Number of times IPD is executed

0h = 1 time

1h = average of 2 times

2h = average of 3 times

3h = average of 4 times

3

2

OL_ILIMIT_CONFIG

IQ_RAMP_EN

R/W

0h

Open loop current limit configuration

0h = Open loop current limit defined by OL_ILIMIT

1h = Open loop current limit defined by ILIMIT

Iq ramp down before transition to close loop

0h = Disable Iq ramp down

1h = Enable Iq ramp down

84

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Table 7-17. MOTOR_STARTUP1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1

ACTIVE_BRAKE_EN

R/W

0h

Active braking enable

0h = Disable Active Brake

1h = Enable Active Brake

0

REV_DRV_CONFIG

R/W

0h

Chooses between forward and reverse drive setting for reverse drive

0h = Open loop current, A1, A2 based on forward drive

1h = Open loop current, A1, A2 based on reverse drive

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7.7.1.4 MOTOR_STARTUP2 Register (Address = 86h) [Reset = 00000000h]

MOTOR_STARTUP2 is shown in MOTOR_STARTUP2 Register and described in MOTOR_STARTUP2 Register

Field Descriptions.

Return to the ALGORITHM_CONFIGURATION Registers.

Register to configure motor startup settings2

Figure 7-58. MOTOR_STARTUP2 Register

31

30

29

28

27

26

25

24

16

PARITY

R/W-0h

OL_ILIMIT

R/W-0h

OL_ACC_A1

R/W-0h

23

22

21

20

19

18

17

OL_ACC_A1

OL_ACC_A2

R/W-0h

AUTO_HANDO

FF_EN

OPN_CL_HANDOFF_THR

R/W-0h

15

R/W-0h

14

13

5

12

4

11

3

10

9

1

8

0

OPN_CL_HANDOFF_THR

R/W-0h

ALIGN_ANGLE

R/W-0h

7

6

2

SLOW_FIRST_CYC_FREQ

FIRST_CYCLE

_FREQ_SEL

THETA_ERROR_RAMP_RATE

R/W-0h

Table 7-18. MOTOR_STARTUP2 Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

31

PARITY

OL_ILIMIT

0h

Parity bit

30-27

0h

Open loop current limit

0h = 0.125 A

1h = 0.25 A

2h = 0.5 A

3h = 1.0 A

4h = 1.5 A

5h = 2.0 A

6h = 2.5 A

7h = 3.0 A

8h = 3.5 A

9h = 4.0 A

Ah = 4.5 A

Bh = 5.0 A

Ch = 5.5 A

Dh = 6.0 A

Eh = 7.0 A

Fh = 8.0 A

86

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Table 7-18. MOTOR_STARTUP2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

26-23

OL_ACC_A1

R/W

0h

Open loop acceleration coefficient A1

0h = 0.01 Hz/s

1h = 0.05 Hz/s

2h = 1 Hz/s

3h = 2.5 Hz/s

4h = 5 Hz/s

5h = 10 Hz/s

6h = 25 Hz/s

7h = 50 Hz/s

8h = 75 Hz/s

9h = 100 Hz/s

Ah = 250 Hz/s

Bh = 500 Hz/s

Ch = 750 Hz/s

Dh = 1000 Hz/s

Eh = 5000 Hz/s

Fh = 10000 Hz/s

22-19

OL_ACC_A2

R/W

0h

Open loop acceleration coefficient A2

0h = 0.0 Hz/s2

1h = 0.05 Hz/s2

2h = 1 Hz/s2

3h = 2.5 Hz/s2

4h = 5 Hz/s2

5h = 10 Hz/s2

6h = 25 Hz/s2

7h = 50 Hz/s2

8h = 75 Hz/s2

9h = 100 Hz/s2

Ah = 250 Hz/s2

Bh = 500 Hz/s2

Ch = 750 Hz/s2

Dh = 1000 Hz/s2

Eh = 5000 Hz/s2

Fh = 10000 Hz/s2

18

AUTO_HANDOFF_EN

R/W

0h

Auto handoff enable

0h = Disable Auto Handoff (and use OPN_CL_HANDOFF_THR)

1h = Enable Auto Handoff

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Table 7-18. MOTOR_STARTUP2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

17-13

OPN_CL_HANDOFF_TH R/W

R

0h

Open to close loop handoff threshold (% of MAX_SPEED)

0h = 1%

1h = 2%

2h = 3%

3h = 4%

4h = 5%

5h = 6%

6h = 7%

7h = 8%

8h = 9%

9h = 10%

Ah = 11%

Bh = 12%

Ch = 13%

Dh = 14%

Eh = 15%

Fh = 16%

10h = 17%

11h = 18%

12h = 19%

13h = 20%

14h = 22.5%

15h = 25%

16h = 27.5%

17h = 30%

18h = 32.5%

19h = 35%

1Ah = 37.5%

1Bh = 40%

1Ch = 42.5%

1Dh = 45%

1Eh = 47.5%

1Fh = 50%

88

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Table 7-18. MOTOR_STARTUP2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

12-8

ALIGN_ANGLE

R/W

0h

Align angle

0h = 0°

1h = 10°

2h = 20°

3h = 30°

4h = 45°

5h = 60°

6h = 70°

7h = 80°

8h = 90°

9h = 110°

Ah = 120°

Bh = 135°

Ch = 150°

Dh = 160°

Eh = 170°

Fh = 180°

10h = 190°

11h = 210°

12h = 225°

13h = 240°

14h = 250°

15h = 260°

16h = 270°

17h = 280°

18h = 290°

19h = 315°

1Ah = 330°

1Bh = 340°

1Ch = 350°

1Dh = N/A

1Eh = N/A

1Fh = N/A

7-4

SLOW_FIRST_CYC_FRE R/W

Q

0h

Frequency of first cycle in close loop startup (% of MAX_SPEED)

0h = 1%

1h = 2%

2h = 3%

3h = 5%

4h = 7.5%

5h = 10%

6h = 12.5%

7h = 15%

8h = 17.5%

9h = 20%

Ah = 25%

Bh = 30%

Ch = 35%

Dh = 40%

Eh = 45%

Fh = 50%

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Table 7-18. MOTOR_STARTUP2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3

FIRST_CYCLE_FREQ_S R/W

EL

0h

First cycle frequency in open loop for align, double align and IPD

startup options

0h = Defined by SLOW_FIRST_CYC_FREQ

1h = 0 Hz

2-0

THETA_ERROR_RAMP_ R/W

RATE

0h

Ramp rate for reducing difference between estimated theta and open

loop theta

0h = 0.01 deg/ms

1h = 0.05 deg/ms

2h = 0.1 deg/ms

3h = 0.15 deg/ms

4h = 0.2 deg/ms

5h = 0.5 deg/ms

6h = 1 deg/ms

7h = 2 deg/ms

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7.7.1.5 CLOSED_LOOP1 Register (Address = 88h) [Reset = 00000000h]

CLOSED_LOOP1 is shown in CLOSED_LOOP1 Register and described in CLOSED_LOOP1 Register Field

Descriptions.

Return to the ALGORITHM_CONFIGURATION Registers.

Register to configure close loop settings1

Figure 7-59. CLOSED_LOOP1 Register

31

30

29

28

27

26

25

24

PARITY

OVERMODULA

TION_ENABLE

CL_ACC

CL_DEC_CON

FIG

R/W-0h

23

R/W-0h

22

R/W-0h

19

R/W-0h

16

21

20

12

18

10

17

CL_DEC

R/W-0h

PWM_FREQ_OUT

R/W-0h

15

14

13

11

9

8

PWM_FREQ_O PWM_MODE

UT

FG_SEL

R/W-0h

FG_DIV

R/W-0h

6

7

5

4

3

2

1

0

FG_CONFIG

FG_BEMF_THR

R/W-0h

AVS_EN

DEADTIME_CO SPEED_LOOP LOW_SPEED_

MP_EN

_DIS

RECIRC_BRAK

E_EN

R/W-0h

Table 7-19. CLOSED_LOOP1 Register Field Descriptions

Bit

31

30

Field

PARITY

Type

Reset

Description

R/W

0h

Parity bit

OVERMODULATION_EN R/W

ABLE

0h

Overmodulation enable

0h = Disable Over Modulation

1h = Enable Over Modulation

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Table 7-19. CLOSED_LOOP1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

29-25

CL_ACC

R/W

0h

Closed loop acceleration

0h = 0.5 Hz/s

1h = 1 Hz/s

2h = 2.5 Hz/s

3h = 5 Hz/s

4h = 7.5 Hz/s

5h = 10 Hz/s

6h = 20 Hz/s

7h = 40 Hz/s

8h = 60 Hz/s

9h = 80 Hz/s

Ah = 100 Hz/s

Bh = 200 Hz/s

Ch = 300 Hz/s

Dh = 400 Hz/s

Eh = 500 Hz/s

Fh = 600 Hz/s

10h = 700 Hz/s

11h = 800 Hz/s

12h = 900 Hz/s

13h = 1000 Hz/s

14h = 2000 Hz/s

15h = 4000 Hz/s

16h = 6000 Hz/s

17h = 8000 Hz/s

18h = 10000 Hz/s

19h = 20000 Hz/s

1Ah = 30000 Hz/s

1Bh = 40000 Hz/s

1Ch = 50000 Hz/s

1Dh = 60000 Hz/s

1Eh = 70000 Hz/s

1Fh = No limit

24

CL_DEC_CONFIG

R/W

0h

Closed loop deceleration configuration

0h = Closed loop deceleration defined by CL_DEC

1h = Closed loop deceleration defined by CL_ACC

92

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Table 7-19. CLOSED_LOOP1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

23-19

CL_DEC

R/W

0h

Closed loop deceleration. This register is used only if AVS is disabled

and CL_DEC_CONFIG is set to '0'

0h = 0.5 Hz/s

1h = 1 Hz/s

2h = 2.5 Hz/s

3h = 5 Hz/s

4h = 7.5 Hz/s

5h = 10 Hz/s

6h = 20 Hz/s

7h = 40 Hz/s

8h = 60 Hz/s

9h = 80 Hz/s

Ah = 100 Hz/s

Bh = 200 Hz/s

Ch = 300 Hz/s

Dh = 400 Hz/s

Eh = 500 Hz/s

Fh = 600 Hz/s

10h = 700 Hz/s

11h = 800 Hz/s

12h = 900 Hz/s

13h = 1000 Hz/s

14h = 2000 Hz/s

15h = 4000 Hz/s

16h = 6000 Hz/s

17h = 8000 Hz/s

18h = 10000 Hz/s

19h = 20000 Hz/s

1Ah = 30000 Hz/s

1Bh = 40000 Hz/s

1Ch = 50000 Hz/s

1Dh = 60000 Hz/s

1Eh = 70000 Hz/s

1Fh = No limit

18-15

PWM_FREQ_OUT

R/W

0h

Output PWM switching frequency

0h = 10 kHz

1h = 15 kHz

2h = 20 kHz

3h = 25 kHz

4h = 30 kHz

5h = 35 kHz

6h = 40 kHz

7h = 45 kHz

8h = 50 kHz

9h = 55 kHz

Ah = 60 kHz

Bh = 65 kHz

Ch = 70 kHz

Dh = 75 kHz

Eh = N/A

Fh = N/A

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Table 7-19. CLOSED_LOOP1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

14

PWM_MODE

R/W

0h

PWM modulation

0h = Continuous Space Vector Modulation

1h = Discontinuous Space Vector Modulation

13-12

11-8

FG_SEL

FG_DIV

R/W

0h

FG select

0h = Output FG in open loop and closed loop

1h = Output FG in only closed loop

2h = Output FG in open loop for the first try.

3h = N/A

FG division factor

0h = Divide by 1 (2-pole motor mechanical speed)

1h = Divide by 1 (2-pole motor mechanical speed)

2h = Divide by 2 (4-pole motor mechanical speed)

3h = Divide by 3 (6-pole motor mechanical speed)

4h = Divide by 4 (8-pole motor mechanical speed) ...

Fh = Divide by 15 (30-pole motor mechanical speed)

7

FG_CONFIG

R/W

0h

FG output configuration

0h = FG active as long as motor is driven

1h = FG active till BEMF drops below BEMF threshold defined by

FG_BEMF_THR

6-4

FG_BEMF_THR

FG output BEMF threshold

0h = +/- 1mV

1h = +/- 2mV

2h = +/- 5mV

3h = +/- 10mV

4h = +/- 20mV

5h = +/- 30mV

6h = N/A

7h = N/A

3

2

1

0

AVS_EN

R/W

0h

AVS enable

0h = Disable

1h = Enable

DEADTIME_COMP_EN

SPEED_LOOP_DIS

Deadtime compensation enable

0h = Disable

1h = Enable

Speed loop disable

0h = Enable

1h = Disable

LOW_SPEED_RECIRC_B R/W

RAKE_EN

Stop mode applied when stop mode is recirculation brake and motor

running in align or open loop

0h = Hi-z

1h = Low Side Brake

94

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7.7.1.6 CLOSED_LOOP2 Register (Address = 8Ah) [Reset = 00000000h]

CLOSED_LOOP2 is shown in CLOSED_LOOP2 Register and described in CLOSED_LOOP2 Register Field

Descriptions.

Return to the ALGORITHM_CONFIGURATION Registers.

Register to configure close loop settings2

Figure 7-60. CLOSED_LOOP2 Register

31

30

29

28

20

12

4

27

19

11

3

26

25

24

16

8

PARITY

R/W-0h

MTR_STOP

R/W-0h

MTR_STOP_BRK_TIME

R/W-0h

23

15

7

22

21

18

17

ACT_SPIN_THR

R/W-0h

BRAKE_SPEED_THRESHOLD

R/W-0h

14

13

10

9

MOTOR_RES

R/W-0h

6

5

2

1

0

MOTOR_IND

R/W-0h

Table 7-20. CLOSED_LOOP2 Register Field Descriptions

Bit

31

Field

Type

R/W

Reset

Description

PARITY

0h

Parity bit

30-28

MTR_STOP

0h

Motor stop method

0h = Hi-z

1h = Recirculation Mode

2h = Low side braking

3h = High side braking

4h = Active spin down

5h = Align braking

6h = N/A

7h = N/A

27-24

MTR_STOP_BRK_TIME R/W

0h

Brake time during motor stop

0h = 0.1 ms

1h = 0.1 ms

2h = 0.25 ms

3h = 0.5 ms

4h = 1 ms

5h = 5 ms

6h = 10 ms

7h = 50 ms

8h = 100 ms

9h = 250 ms

Ah = 500 ms

Bh = 1000 ms

Ch = 2500 ms

Dh = 5000 ms

Eh = 10000 ms

Fh = 15000 ms

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Table 7-20. CLOSED_LOOP2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

23-20

ACT_SPIN_THR

R/W

0h

Speed threshold for active spin down (% of MAX_SPEED)

0h = 100 %

1h = 90 %

2h = 80 %

3h = 70 %

4h = 60%

5h = 50 %

6h = 45 %

7h = 40 %

8h = 35 %

9h = 30 %

Ah = 25 %

Bh = 20 %

Ch = 15 %

Dh = 10 %

Eh = 5 %

Fh = 2.5 %

19-16

BRAKE_SPEED_THRES R/W

HOLD

0h

Speed threshold for BRAKE pin and motor stop options (low-side

braking or high-side braking or align braking) (% of MAX_SPEED)

0h = 100 %

1h = 90 %

2h = 80 %

3h = 70 %

4h = 60%

5h = 50 %

6h = 45 %

7h = 40 %

8h = 35 %

9h = 30 %

Ah = 25 %

Bh = 20 %

Ch = 15 %

Dh = 10 %

Eh = 5 %

Fh = 2.5 %

15-8

7-0

MOTOR_RES

MOTOR_IND

R/W

0h

8-bit values for motor phase resistance

8-bit values for motor phase inductance

96

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7.7.1.7 CLOSED_LOOP3 Register (Address = 8Ch) [Reset = 00000000h]

CLOSED_LOOP3 is shown in CLOSED_LOOP3 Register and described in CLOSED_LOOP3 Register Field

Descriptions.

Return to the ALGORITHM_CONFIGURATION Registers.

Register to configure close loop settings3

Figure 7-61. CLOSED_LOOP3 Register

31

30

29

28

27

26

25

17

24

16

PARITY

R/W-0h

MOTOR_BEMF_CONST

R/W-0h

23

22

21

20

19

18

MOTOR_BEMF

_CONST

CURR_LOOP_KP

R/W-0h

15

R/W-0h

11

14

13

12

4

10

9

8

0

CURR_LOOP_KP

R/W-0h

CURR_LOOP_KI

R/W-0h

7

6

5

3

2

1

CURR_LOOP_KI

R/W-0h

SPD_LOOP_KP

R/W-0h

Table 7-21. CLOSED_LOOP3 Register Field Descriptions

Bit

31

Field

PARITY

Type

Reset

Description

R/W

0h

Parity bit

30-23

22-13

MOTOR_BEMF_CONST R/W

0h

8-bit values for motor BEMF constant

CURR_LOOP_KP

CURR_LOOP_KI

SPD_LOOP_KP

R/W

0h

10-bit value for current Iq and Id loop Kp. Kp = 8LSB of

CURR_LOOP_KP / 10^2MSB of CURR_LOOP_KP. Set to 0 for auto

calculation of current loop Kp.

12-3

2-0

0h

10-bit value for current Iq and Id loop Ki. Ki = 1000 * 8LSB of

CURR_LOOP_KI / 10^2MSB of CURR_LOOP_KI. Set to 0 for auto

calculation of current loop Ki.

3 MSB bits for speed loop Kp. Kp = 0.01 * 8LSB of SPD_LOOP_KP /

10^2MSB of SPD_LOOP_KP

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7.7.1.8 CLOSED_LOOP4 Register (Address = 8Eh) [Reset = X]

CLOSED_LOOP4 is shown in CLOSED_LOOP4 Register and described in CLOSED_LOOP4 Register Field

Descriptions.

Return to the ALGORITHM_CONFIGURATION Registers.

Register to configure close loop settings4

Figure 7-62. CLOSED_LOOP4 Register

31

30

22

14

29

21

13

5

28

27

26

18

10

2

25

17

9

24

16

8

PARITY

R/W-0h

SPD_LOOP_KP

R/W-0h

23

20

19

SPD_LOOP_KI

R/W-0h

15

12

4

11

3

SPD_LOOP_KI

MAX_SPEED

R/W-X

R/W-0h

7

6

1

0

MAX_SPEED

R/W-X

Table 7-22. CLOSED_LOOP4 Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

31

PARITY

0h

Parity bit

30-24

SPD_LOOP_KP

SPD_LOOP_KI

MAX_SPEED

0h

7 LSB bits for speed loop Kp. Kp = 0.01 * 8LSB of SPD_LOOP_KP /

10^2MSB of SPD_LOOP_KP. Set to 0 for auto calculation of speed

loop Kp.

23-14

13-0

R/W

0h

X

10-bit value for speed loop Ki. Ki = 0.1 * 8LSB of SPD_LOOP_KI /

10^2MSB of SPD_LOOP_KI. Set to 0 for auto calculation of speed

loop Ki.

14-bit value for setting maximum value of speed in electrical Hz

Maximum motor electrical speed (Hz): {MOTOR_SPEED/6} For

example: if MOTOR_SPEED is 0x2710, then maximum motor speed

(Hz) = 10000(0x2710)/6 = 1666 Hz

98

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7.7.1.9 SPEED_PROFILES1 Register (Address = 94h) [Reset = X]

SPEED_PROFILES1 is shown in SPEED_PROFILES1 Register and described in SPEED_PROFILES1 Register

Field Descriptions.

Return to the ALGORITHM_CONFIGURATION Registers.

Register to configure speed profile1

Figure 7-63. SPEED_PROFILES1 Register

31

30

29

28

20

12

4

27

19

11

3

26

25

17

9

24

16

8

PARITY

R/W-0h

SPEED_PROFILE_CONFIG

R/W-0h

DUTY_ON1

R/W-X

23

15

7

22

21

13

5

18

DUTY_ON1

R/W-X

DUTY_OFF1

R/W-X

14

10

DUTY_OFF1

R/W-X

DUTY_CLAMP1

R/W-X

6

2

1

0

DUTY_CLAMP1

R/W-X

DUTY_A

R/W-X

Table 7-23. SPEED_PROFILES1 Register Field Descriptions

Bit

31

Field

Type

Reset

Description

PARITY

R/W

0h

Parity bit

30-29

SPEED_PROFILE_CONFI R/W

G

0h

Configuration for speed profiles

0h = Speed Reference Mode

1h = Linear Mode

2h = Staircase Mode

3h = Forward Reverse Mode

28-21

20-13

12-5

DUTY_ON1

R/W

X

Duty_ON1 configuration (%) = {(DUTY_ON1/255)*100}

Duty_OFF1 Configuration (%) = {(DUTY_OFF1/255)*100}

DUTY_OFF1

DUTY_CLAMP1

Duty_CLAMP1 Configuration Duty Cycle for clamping speed (%) =

{(DUTY_CLAMP1/255)*100}

4-0

DUTY_A

R/W

X

5 MSB bits for Duty Cycle A

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7.7.1.10 SPEED_PROFILES2 Register (Address = 96h) [Reset = X]

SPEED_PROFILES2 is shown in SPEED_PROFILES2 Register and described in SPEED_PROFILES2 Register

Field Descriptions.

Return to the ALGORITHM_CONFIGURATION Registers.

Register to configure speed profile2

Figure 7-64. SPEED_PROFILES2 Register

31

30

22

14

6

29

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

PARITY

R/W-0h

DUTY_A

R/W-X

DUTY_B

R/W-X

23

15

7

21

13

5

DUTY_B

R/W-X

DUTY_C

R/W-X

DUTY_C

R/W-X

DUTY_D

R/W-X

1

0

DUTY_D

R/W-X

DUTY_E

R/W-0h

Table 7-24. SPEED_PROFILES2 Register Field Descriptions

Bit

31

Field

Type

R/W

Reset

Description

PARITY

DUTY_A

0h

Parity bit

30-28

X

3 LSB bits for Duty Cycle A Duty_A Configuration Duty Cycle A (%) =

{(DUTY_A/255)*100}

27-20

19-12

11-4

DUTY_B

DUTY_C

DUTY_D

DUTY_E

R/W

X

Duty_B Configuration Duty Cycle B (%) = {(DUTY_B/255)*100}

Duty_C Configuration Duty Cycle C (%) = {(DUTY_C/255)*100}

Duty_D Configuration Duty Cycle D (%) = {(DUTY_D/255)*100}

4 MSB bits for Duty Cycle E

X

3-0

0h

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7.7.1.11 SPEED_PROFILES3 Register (Address = 98h) [Reset = X]

SPEED_PROFILES3 is shown in SPEED_PROFILES3 Register and described in SPEED_PROFILES3 Register

Field Descriptions.

Return to the ALGORITHM_CONFIGURATION Registers.

Register to configure speed profile3

Figure 7-65. SPEED_PROFILES3 Register

31

30

22

14

6

29

28

20

12

4

27

19

11

3

26

18

10

2

25

24

16

8

PARITY

R/W-0h

DUTY_E

R/W-X

DUTY_ON2

R/W-X

23

15

7

21

17

DUTY_ON2

R/W-X

DUTY_OFF2

R/W-X

13

9

DUTY_OFF2

R/W-X

DUTY_CLAMP2

R/W-X

5

1

0

DUTY_CLAMP2

R/W-X

RESERVED

R/W-0h

Table 7-25. SPEED_PROFILES3 Register Field Descriptions

Bit

31

Field

Type

R/W

Reset

Description

PARITY

DUTY_E

0h

Parity bit

30-27

X

4 LSB bits for Duty Cycle E Duty_E Configuration Duty Cycle E (%) =

{(DUTY_E/255)*100}

26-19

18-11

10-3

DUTY_ON2

R/W

X

Duty_ON2 Configuration (%) = {(DUTY_ON2/255)*100}

Duty_OFF2 Configuration (%) = {(DUTY_OFF2/255)*100}

DUTY_OFF2

DUTY_CLAMP2

Duty_CLAMP2 Configuration Duty Cycle for clamping speed (%) =

{(DUTY_CLAMP1/255)*100}

2-0

RESERVED

R/W

0h

Reserved

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7.7.1.12 SPEED_PROFILES4 Register (Address = 9Ah) [Reset = X]

SPEED_PROFILES4 is shown in SPEED_PROFILES4 Register and described in SPEED_PROFILES4 Register

Field Descriptions.

Return to the ALGORITHM_CONFIGURATION Registers.

Register to configure speed profile4

Figure 7-66. SPEED_PROFILES4 Register

31

30

22

14

29

21

13

28

20

12

27

26

18

10

25

17

9

24

16

8

PARITY

R/W-0h

SPEED_OFF1

R/W-X

23

19

SPEED_OFF1

R/W-X

SPEED_CLAMP1

R/W-X

15

11

SPEED_CLAM

P1

SPEED_A

R/W-X

7

6

5

4

3

2

1

0

SPEED_A

R/W-X

SPEED_B

R/W-X

Table 7-26. SPEED_PROFILES4 Register Field Descriptions

Bit

31

Field

PARITY

Type

R/W

Reset

Description

0h

Parity bit

30-23

SPEED_OFF1

SPEED_CLAMP1

SPEED_A

X

Turn off speed Configuration Turn off speed (% of MAX_SPEED) =

{(SPEED_OFF1/255)*100}

22-15

14-7

6-0

R/W

X

Clamp Speed Configuration Clamp Speed (% of MAX_SPEED) =

{(SPEED_CLAMP1/255)*100}

Speed A configuration SPEED A (% of MAX_SPEED) = {(SPEED_A/

255)*100}

SPEED_B

7 MSB of SPEED_B configuration

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7.7.1.13 SPEED_PROFILES5 Register (Address = 9Ch) [Reset = X]

SPEED_PROFILES5 is shown in SPEED_PROFILES5 Register and described in SPEED_PROFILES5 Register

Field Descriptions.

Return to the ALGORITHM_CONFIGURATION Registers.

Register to configure speed profile5

Figure 7-67. SPEED_PROFILES5 Register

31

30

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

PARITY

R/W-0h

SPEED_B

R/W-X

SPEED_C

R/W-X

23

22

SPEED_C

SPEED_D

R/W-X

15

7

14

6

SPEED_D

R/W-X

SPEED_E

R/W-X

1

0

SPEED_E

R/W-X

RESERVED

R/W-0h

Table 7-27. SPEED_PROFILES5 Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

31

30

PARITY

SPEED_B

0h

Parity bit

X

1 LSB of SPEED_B configuration Speed B Configuration SPEED

B(% of MAX_SPEED) = {(SPEED_B/255)*100}

29-22

21-14

13-6

5-0

SPEED_C

SPEED_D

SPEED_E

R/W

X

Speed C configuration SPEED C (% of MAX_SPEED) = {(SPEED_A/

255)*100}

X

Speed D configuration SPEED D (% of MAX_SPEED) =

{(SPEED_D/255)*100}

X

Speed E Configuration SPEED E (% of MAX_SPEED) =

{(SPEED_E/255)*100}

RESERVED

0h

Reserved

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7.7.1.14 SPEED_PROFILES6 Register (Address = 9Eh) [Reset = X]

SPEED_PROFILES6 is shown in SPEED_PROFILES6 Register and described in SPEED_PROFILES6 Register

Field Descriptions.

Return to the ALGORITHM_CONFIGURATION Registers.

Register to configure speed profile6

Figure 7-68. SPEED_PROFILES6 Register

31

30

22

14

29

21

13

28

20

12

27

26

18

10

25

17

9

24

16

8

PARITY

R/W-0h

SPEED_OFF2

R/W-X

23

19

SPEED_OFF2

R/W-X

SPEED_CLAMP2

R/W-X

15

11

SPEED_CLAM

P2

RESERVED

R/W-X

7

R/W-X

3

6

5

4

2

1

0

RESERVED

R/W-X

Table 7-28. SPEED_PROFILES6 Register Field Descriptions

Bit

31

Field

PARITY

Type

R/W

Reset

Description

0h

Parity bit

30-23

SPEED_OFF2

SPEED_CLAMP2

RESERVED

X

Turn off speed Configuration Turn off speed (% of MAX_SPEED) =

{(SPEED_OFF2/255)*100}

22-15

14-0

R/W

X

Clamp Speed Configuration Clamp Speed (% of MAX_SPEED) =

{(SPEED_CLAMP2/255)*100}

Reserved

7.7.2 Fault_Configuration Registers

FAULT_CONFIGURATION Registers lists the memory-mapped registers for the Fault_Configuration registers.

All register offset addresses not listed in FAULT_CONFIGURATION Registers should be considered as reserved

locations and the register contents should not be modified.

Table 7-29. FAULT_CONFIGURATION Registers

Address Acronym

Register Name

Section

90h

92h

FAULT_CONFIG1

FAULT_CONFIG2

Fault Configuration 1

Fault Configuration 2

Section 7.7.2.1

Section 7.7.2.2

Complex bit access types are encoded to fit into small table cells. Fault_Configuration Access Type Codes

shows the codes that are used for access types in this section.

Table 7-30. Fault_Configuration Access Type Codes

Access Type

Read Type

R

Code

Description

R

Read

Write Type

W

Write

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Table 7-30. Fault_Configuration Access Type Codes

(continued)

Access Type

Code

Description

Reset or Default Value

-n

Value after reset or the default

value

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7.7.2.1 FAULT_CONFIG1 Register (Address = 90h) [Reset = 00000000h]

FAULT_CONFIG1 is shown in FAULT_CONFIG1 Register and described in FAULT_CONFIG1 Register Field

Descriptions.

Return to the FAULT_CONFIGURATION Registers.

Register to configure fault settings1

Figure 7-69. FAULT_CONFIG1 Register

31

30

29

28

27

26

25

24

16

PARITY

R/W-0h

ILIMIT

HW_LOCK_ILIMIT

R/W-0h

23

22

21

20

19

18

17

HW_LOCK_ILI

MIT

LOCK_ILIMIT

R/W-0h

LOCK_ILIMIT_MODE

R/W-0h

15

R/W-0h

14

6

13

12

11

3

10

2

9

8

0

LOCK_ILIMIT_

MODE

LOCK_ILIMIT_DEG

LCK_RETRY

R/W-0h

1

7

5

4

LCK_RETRY

MTR_LCK_MODE

IPD_TIMEOUT IPD_FREQ_FA SATURATION_

_FAULT_EN

ULT_EN

FLAGS_EN

R/W-0h

Table 7-31. FAULT_CONFIG1 Register Field Descriptions

Bit

31

Field

Type

R/W

Reset

Description

PARITY

ILIMIT

0h

Parity bit

30-27

0h

Reference for torque PI loop

0h = 0.125 A

1h = 0.25 A

2h = 0.5 A

3h = 1.0 A

4h = 1.5 A

5h = 2.0 A

6h = 2.5 A

7h = 3.0 A

8h = 3.5 A

9h = 4.0 A

Ah = 4.5 A

Bh = 5.0 A

Ch = 5.5 A

Dh = 6.0 A

Eh = 7.0 A

Fh = 8.0 A

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Table 7-31. FAULT_CONFIG1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

26-23

HW_LOCK_ILIMIT

R/W

0h

Comparator based lock detection current limit

0h = 0.125 A

1h = 0.25 A

2h = 0.5 A

3h = 1.0 A

4h = 1.5 A

5h = 2.0 A

6h = 2.5 A

7h = 3.0 A

8h = 3.5 A

9h = 4.0 A

Ah = 4.5 A

Bh = 5.0 A

Ch = 5.5 A

Dh = 6.0 A

Eh = 7.0 A

Fh = 8.0 A

22-19

LOCK_ILIMIT

R/W

0h

ADC based lock detection current threshold

0h = 0.125 A

1h = 0.25 A

2h = 0.5 A

3h = 1.0 A

4h = 1.5 A

5h = 2.0 A

6h = 2.5 A

7h = 3.0 A

8h = 3.5 A

9h = 4.0 A

Ah = 4.5 A

Bh = 5.0 A

Ch = 5.5 A

Dh = 6.0 A

Eh = 7.0 A

Fh = 8.0 A

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Table 7-31. FAULT_CONFIG1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

18-15

LOCK_ILIMIT_MODE

R/W

0h

Lock current limit mode

0h = Ilimit lock detection causes latched fault; nFAULT active; Gate

driver is tristated

1h = Ilimit lock detection causes latched fault; nFAULT active; Gate

driver is in recirculation mode

2h = Ilimit lock detection causes latched fault; nFAULT active; Gate

driver is in high-side brake mode (All high-side FETs are turned ON)

3h = Ilimit lock detection causes latched fault; nFAULT active; Gate

driver is in low-side brake mode (All low-side FETs are turned ON)

4h = Fault automatically cleared after LCK_RETRY time. Number of

retries limited to AUTO_RETRY_TIMES. If number of retries exceed

AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated;

nFAULT active

5h = Fault automatically cleared after LCK_RETRY time. Number of

retries limited to AUTO_RETRY_TIMES. If number of retries exceed

AUTO_RETRY_TIMES, fault is latched; Gate driver is in recirculation

mode; nFAULT active

6h = Fault automatically cleared for AUTO_RETRY_TIMES after

LCK_RETRY time; Gate driver is in high-side brake mode (All-high

side FETs are turned ON); nFAULT active

7h = Fault automatically cleared after LCK_RETRY time. Number of

retries limited to AUTO_RETRY_TIMES. If number of retries exceed

AUTO_RETRY_TIMES, fault is latched; Gate driver is in low-side

brake mode (All-low side FETs are turned ON); nFAULT active

8h = Ilimit lock detection current limit is in report only but no action is

taken; nFAULT active

9h = ILIMIT LOCK is disabled

Ah = ILIMIT LOCK is disabled

Bh = ILIMIT LOCK is disabled

Ch = ILIMIT LOCK is disabled

Dh = ILIMIT LOCK is disabled

Eh = ILIMIT LOCK is disabled

Fh = ILIMIT LOCK is disabled

14-11

LOCK_ILIMIT_DEG

R/W

0h

Lock detection current limit deglitch time

0h = 0.05 ms

1h = 0.1 ms

2h = 0.2 ms

3h = 0.5 ms

4h = 1 ms

5h = 2.5 ms

6h = 5 ms

7h = 7.5 ms

8h = 10 ms

9h = 25 ms

Ah = 50 ms

Bh = 75 ms

Ch = 100 ms

Dh = 200 ms

Eh = 500 ms

Fh = 1000 ms

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Table 7-31. FAULT_CONFIG1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

10-7

LCK_RETRY

R/W

0h

Lock detection retry time

0h = 100 ms

1h = 500 ms

2h = 1 s

3h = 2 s

4h = 3 s

5h = 4 s

6h = 5 s

7h = 6 s

8h = 7 s

9h = 8 s

Ah = 9 s

Bh = 10 s

Ch = 11 s

Dh = 12 s

Eh = 13 s

Fh = 14 s

6-3

MTR_LCK_MODE

R/W

0h

Motor Lock Mode

0h = Motor lock detection causes latched fault; nFAULT active; Gate

driver is tristated

1h = Motor lock detection causes latched fault; nFAULT active; Gate

driver is in recirculation mode

2h = Motor lock detection causes latched fault; nFAULT active; Gate

driver is in high-side brake mode (All high-side FETs are turned ON)

3h = Motor lock detection causes latched fault; nFAULT active; Gate

driver is in low-side brake mode (All low-side FETs are turned ON)

4h = Fault automatically cleared after LCK_RETRY time. Number of

retries limited to AUTO_RETRY_TIMES. If number of retries exceed

AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated;

nFAULT active

5h = Fault automatically cleared after LCK_RETRY time. Number of

retries limited to AUTO_RETRY_TIMES. If number of retries exceed

AUTO_RETRY_TIMES, fault is latched; Gate driver is in recirculation

mode; nFAULT active

6h = Fault automatically cleared for AUTO_RETRY_TIMES after

LCK_RETRY time; Gate driver is in high-side brake mode (All high-

side FETs are turned ON); nFAULT active

7h = Fault automatically cleared after LCK_RETRY time. Number of

retries limited to AUTO_RETRY_TIMES. If number of retries exceed

AUTO_RETRY_TIMES, fault is latched; Gate driver is in low-side

brake mode (All low-side FETs are turned ON); nFAULT active

8h = Motor lock detection current limit is in report only but no action

is taken; nFAULT active

9h = Motor lock detection is disabled

Ah = Motor lock detection is disabled

Bh = Motor lock detection is disabled

Ch = Motor lock detection is disabled

Dh = Motor lock detection is disabled

Eh = Motor lock detection is disabled

Fh = Motor lock detection is disabled

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Table 7-31. FAULT_CONFIG1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

2

IPD_TIMEOUT_FAULT_E R/W

N

0h

IPD timeout fault enable

0h = Disable

1h = Enable

1

0

IPD_FREQ_FAULT_EN

R/W

0h

IPD frequency fault enable

0h = Disable

1h = Enable

SATURATION_FLAGS_E R/W

N

Enables indication of current loop and speed loop saturation

0h = Disable

1h = Enable

110

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7.7.2.2 FAULT_CONFIG2 Register (Address = 92h) [Reset = 00000000h]

FAULT_CONFIG2 is shown in FAULT_CONFIG2 Register and described in FAULT_CONFIG2 Register Field

Descriptions.

Return to the FAULT_CONFIGURATION Registers.

Register to configure fault settings2

Figure 7-70. FAULT_CONFIG2 Register

31

30

29

28

27

26

25

17

24

PARITY

LOCK1_EN

LOCK2_EN

LOCK3_EN

LOCK_ABN_SPEED

ABNORMAL_B

EMF_THR

R/W-0h

23

R/W-0h

22

R/W-0h

21

R/W-0h

18

R/W-0h

16

20

19

11

ABNORMAL_BEMF_THR

R/W-0h

NO_MTR_THR

R/W-0h

HW_LOCK_ILIMIT_MODE

R/W-0h

15

14

13

12

10

2

9

8

0

HW_LOCK_ILI

MIT_MODE

HW_LOCK_ILIMIT_DEG

MIN_VM_MOTOR

R/W-0h

7

R/W-0h

6

5

4

3

1

MIN_VM_MOD

E

MAX_VM_MOTOR

MAX_VM_MOD

E

AUTO_RETRY_TIMES

R/W-0h

Table 7-32. FAULT_CONFIG2 Register Field Descriptions

Bit

31

30

Field

PARITY

Type

R/W

Reset

Description

0h

Parity bit

LOCK1_EN

0h

Lock 1 : Abnormal speed enable

0h = Disable

1h = Enable

29

28

LOCK2_EN

R/W

0h

Lock 2 : Abnormal BEMF enable

0h = Disable

1h = Enable

LOCK3_EN

Lock 3 : No motor enable

0h = Disable

1h = Enable

27-25

LOCK_ABN_SPEED

Abnormal speed lock threshold (% of MAX_SPEED)

0h = 130%

1h = 140%

2h = 150%

3h = 160%

4h = 170%

5h = 180%

6h = 190%

7h = 200%

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Table 7-32. FAULT_CONFIG2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

24-22

ABNORMAL_BEMF_THR R/W

0h

Abnormal BEMF lock threshold (% of expected BEMF)

0h = 10%

1h = 20%

2h = 30%

3h = 40%

4h = 50%

5h = 60%

6h = 70%

7h = 80%

21-19

NO_MTR_THR

R/W

0h

No motor lock threshold

0h = 0.05 A

1h = 0.075 A

2h = 0.1A

3h = 0.125 A

4h = 0.25 A

5h = 0.5 A

6h = 0.75 A

7h = 1.0 A

112

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Table 7-32. FAULT_CONFIG2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

18-15

HW_LOCK_ILIMIT_MODE R/W

0h

Hardware lock detection current mode

0h = Hardware Ilimit lock detection causes latched fault; nFAULT

active; Gate driver is tristated

1h = Hardware Ilimit lock detection causes latched fault;

nFAULTactive; Gate driver is in recirculation mode

2h = Hardware Ilimit lock detection causes latched fault; nFAULT

active; Gate driver is in high-side brake mode (All high-side FETs are

turned ON)

3h = Hardware Ilimit lock detection causes latched fault; nFAULT

active; Gate driver is in low-side brake mode (All low-side FETs are

turned ON)

4h = Fault automatically cleared after LCK_RETRY time. Number of

retries limited to AUTO_RETRY_TIMES. If number of retries exceed

AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated

5h = Fault automatically cleared after LCK_RETRY time. Number of

retries limited to AUTO_RETRY_TIMES. If number of retries exceed

AUTO_RETRY_TIMES, fault is latched; Gate driver is in recirculation

mode

6h = Fault automatically cleared after LCK_RETRY time. Number of

retries limited to AUTO_RETRY_TIMES. If number of retries exceed

AUTO_RETRY_TIMES, fault is latched; Gate driver is in high-side

brake mode (All high-side FETs are turned ON)

7h = Fault automatically cleared after LCK_RETRY time. Number of

retries limited to AUTO_RETRY_TIMES. If number of retries exceed

AUTO_RETRY_TIMES, fault is latched; Gate driver is in low-side

brake mode (All low-side FETs are turned ON)

8h = Hardware Ilimit lock detection is in report only but no action is

taken

9h = Hardware Ilimit lock detection is disabled

Ah = Hardware Ilimit lock detection is disabled

Bh = Hardware Ilimit lock detection is disabled

Ch = Hardware Ilimit lock detection is disabled

Dh = Hardware Ilimit lock detection is disabled

Eh = Hardware Ilimit lock detection is disabled

Fh = Hardware Ilimit lock detection is disabled

14-11

HW_LOCK_ILIMIT_DEG R/W

0h

Hardware lock detection current limit deglitch time

0h = No Deglitch

1h = 1 µs

2h = 2 µs

3h = 3 µs

4h = 4 µs

5h = 5 µs

6h = 6 µs

7h = 7 µs

8h = 8 µs

9h = 9 µs

Ah = 10 µs

Bh = 11 µs

Ch = 12 µs

Dh = 13 µs

Eh = 14 µs

Fh = 15 µs

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Table 7-32. FAULT_CONFIG2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

10-8

MIN_VM_MOTOR

R/W

0h

Minimum voltage for running motor

0h = No Limit

1h = 4.5 V

2h = 5 V

3h = 5.5 V

4h = 6 V

5h = 7.5 V

6h = 10 V

7h = 12.5 V

7

MIN_VM_MODE

R/W

0h

Undervoltage fault mode

0h = Latch on Undervoltage

1h = Automatic clear if voltage in bounds

6-4

MAX_VM_MOTOR

Maximum voltage for running motor

0h = No Limit

1h = 20 V

2h = 22.5 V

3h = 25 V

4h = 27.5 V

5h = 30 V

6h = 32.5 V

7h = 35 V

3

MAX_VM_MODE

R/W

0h

Overvoltage fault mode

0h = Latch on Overvoltage

1h = Automatic clear if voltage in bounds

2-0

AUTO_RETRY_TIMES

Automatic retry attempts

0h = No Limit

1h = 2

2h = 3

3h = 5

4h = 7

5h = 10

6h = 15

7h = 20

7.7.3 Hardware_Configuration Registers

HARDWARE_CONFIGURATION Registers lists the memory-mapped registers for the Hardware_Configuration

registers. All register offset addresses not listed in HARDWARE_CONFIGURATION Registers should be

considered as reserved locations and the register contents should not be modified.

Table 7-33. HARDWARE_CONFIGURATION Registers

Address Acronym

Register Name

Section

A4h

A6h

A8h

AAh

ACh

AEh

PIN_CONFIG

Hardware Pin Configuration

Device Configuration 1

Device Configuration 2

Peripheral Configuration 1

Gate Driver Configuration 1

Gate Driver Configuration 2

Section 7.7.3.1

Section 7.7.3.2

Section 7.7.3.3

Section 7.7.3.4

Section 7.7.3.5

Section 7.7.3.6

DEVICE_CONFIG1

DEVICE_CONFIG2

PERI_CONFIG1

GD_CONFIG1

GD_CONFIG2

Complex bit access types are encoded to fit into small table cells. Hardware_Configuration Access Type Codes

shows the codes that are used for access types in this section.

114

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Table 7-34. Hardware_Configuration Access Type

Codes

Access Type

Read Type

R

Code

Description

R

Read

Write

Write Type

W

W1C

W

Write

1C

1 to clear

Reset or Default Value

-n

Value after reset or the default

value

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7.7.3.1 PIN_CONFIG Register (Address = A4h) [Reset = 00000000h]

PIN_CONFIG is shown in PIN_CONFIG Register and described in PIN_CONFIG Register Field Descriptions.

Return to the HARDWARE_CONFIGURATION Registers.

Register to configure hardware pins

Figure 7-71. PIN_CONFIG Register

31

30

22

14

6

29

21

13

5

28

20

12

4

27

26

18

10

2

25

17

9

24

16

8

PARITY

R/W-0h

RESERVED

R/W-0h

23

15

7

19

RESERVED

R/W-0h

11

3

RESERVED

R/W-0h

1

0

RESERVED

BRAKE_PIN_M ALIGN_BRAKE

BRAKE_INPUT

SPEED_MODE

R/W-0h

ODE

_ANGLE_SEL

R/W-0h

Table 7-35. PIN_CONFIG Register Field Descriptions

Bit

31

Field

Type

R/W

Reset

Description

PARITY

0h

Parity bit

30-6

5

RESERVED

0h

Reserved

BRAKE_PIN_MODE

0h

Brake pin mode

0h = Low side Brake

1h = Align Brake

4

ALIGN_BRAKE_ANGLE_ R/W

SEL

0h

Align brake angle select

0h = Use last commutation angle before entering align braking

1h = Use ALIGN_ANGLE configuration for align braking

3-2

BRAKE_INPUT

R/W

Brake pin override

0h = Hardware Pin BRAKE

1h = Override pin and brake / align according to BRAKE_PIN_MODE

2h = Override pin and do not brake / align

3h = Hardware Pin BRAKE

1-0

SPEED_MODE

R/W

0h

Configure speed control mode from speed pin

0h = Analog Mode

1h = Controlled by Duty Cycle of SPEED Input Pin

2h = Register Override mode

3h = Controlled by Frequency of SPEED Input Pin

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7.7.3.2 DEVICE_CONFIG1 Register (Address = A6h) [Reset = X]

DEVICE_CONFIG1 is shown in DEVICE_CONFIG1 Register and described in DEVICE_CONFIG1 Register

Field Descriptions.

Return to the HARDWARE_CONFIGURATION Registers.

Register to configure device

Figure 7-72. DEVICE_CONFIG1 Register

31

30

29

PIN_38_CONFIG

R/W-0h

28

27

26

18

10

2

25

24

16

8

PARITY

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

I2C_TARGET_ADDR

R/W-X

23

15

7

22

21

20

12

4

19

17

I2C_TARGET_ADDR

R/W-X

RESERVED

R/W-X

14

13

11

9

1

RESERVED

R/W-X

6

5

3

0

RESERVED

R/W-X

RESERVED

R/W-0h

BUS_VOLT

R/W-0h

Table 7-36. DEVICE_CONFIG1 Register Field Descriptions

Bit

31

Field

Type

R/W

Reset

Description

PARITY

0h

Parity bit

30

RESERVED

PIN_38_CONFIG

0h

Reserved

29-28

0h

Pin 38 configuration

0h = N/A

1h = SOA

2h = SOB

3h = SOC

27

26-20

19-5

4-2

RESERVED

R/W

0h

X

Reserved

I2C_TARGET_ADDR

RESERVED

I2C target address

Reserved

X

RESERVED

0h

Reserved

1-0

BUS_VOLT

Maximum bus voltage configuration

0h = 15 V

1h = 30 V

2h = 60 V

3h = Not defined

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7.7.3.3 DEVICE_CONFIG2 Register (Address = A8h) [Reset = 00000000h]

DEVICE_CONFIG2 is shown in DEVICE_CONFIG2 Register and described in DEVICE_CONFIG2 Register

Field Descriptions.

Return to the HARDWARE_CONFIGURATION Registers.

Register to configure device

Figure 7-73. DEVICE_CONFIG2 Register

31

30

22

14

29

21

13

28

27

26

18

10

25

17

9

24

16

PARITY

R/W-0h

INPUT_MAXIMUM_FREQ

R/W-0h

23

20

19

INPUT_MAXIMUM_FREQ

R/W-0h

15

12

11

8

SLEEP_ENTRY_TIME

DYNAMIC_CSA DYNAMIC_VOL DEV_MODE

CLK_SEL

R/W-0h

EXT_CLK_EN

_GAIN_EN

TAGE_GAIN_E

N

R/W-0h

5

R/W-0h

3

R/W-0h

0

7

6

4

2

1

EXT_CLK_CONFIG

EXT_WD_EN

EXT_WD_CONFIG

EXT_WD_INPU EXT_WD_FAUL

T

R/W-0h

Table 7-37. DEVICE_CONFIG2 Register Field Descriptions

Bit

Field

Type

Reset

Description

31

PARITY

R/W

0h

Parity bit

30-16

INPUT_MAXIMUM_FREQ R/W

0h

Input frequency on speed pin for speed control mode as "controlled

by frequency speed pin input" that corresponds to 100% duty cycle.

Input duty cycle = Input frequency / INPUT_MAXIMUM_FREQ

15-14

SLEEP_ENTRY_TIME

R/W

0h

Device enters sleep mode when speed input is held continuously

below the speed threshold for SEEP_ENTRY_TIME

0h = 50 µs

1h = 200 µs

2h = 20 ms

3h = 200 ms

13

12

DYNAMIC_CSA_GAIN_E R/W

N

0h

Adjust CSA gain at 1ms rate for optimal current resolution at all

current levels

0h = Disable

1h = Enable

DYNAMIC_VOLTAGE_GA R/W

IN_EN

Adjust voltage gain at 1ms rate for optimal voltage resolution at all

voltage levels

0h = Dynamic Voltage Gain is Disabled

1h = Dynamic Voltage Gain is Enabled

11

DEV_MODE

CLK_SEL

R/W

0h

Device mode select

0h = Standby Mode

1h = Sleep Mode

10-9

Clock source

0h = Internal Oscillator

1h = N/A

2h = N/A

3h = External Clock input

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Table 7-37. DEVICE_CONFIG2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

8

EXT_CLK_EN

R/W

0h

External clock mode enable

0h = Disable

1h = Enable

7-5

EXT_CLK_CONFIG

R/W

0h

External clock configuration

0h = 8 kHz

1h = 16 kHz

2h = 32 kHz

3h = 64 kHz

4h = 128 kHz

5h = 256 kHz

6h = 512 kHz

7h = 1024 kHz

4

EXT_WD_EN

R/W

0h

External watchdog enable

0h = Disable

1h = Enable

3-2

EXT_WD_CONFIG

Time between watchdog tickles

0h = 100ms if GPIO mode; 1s if I2C mode

1h = 200ms if GPIO mode; 2s if I2C mode

2h = 500ms if GPIO mode; 5s if I2C mode

3h = 1000ms if GPIO mode; 10s if I2C mode

1

0

EXT_WD_INPUT

EXT_WD_FAULT

R/W

0h

External watchdog input mode

0h = Watchdog tickle over I2C

1h = Watchdog tickle over GPIO

External watchdog fault mode

0h = Report Only

1h = Latch with Hi-Z outputs

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7.7.3.4 PERI_CONFIG1 Register (Address = AAh) [Reset = 40000000h]

PERI_CONFIG1 is shown in PERI_CONFIG1 Register and described in PERI_CONFIG1 Register Field

Descriptions.

Return to the HARDWARE_CONFIGURATION Registers.

Register to peripheral1

Figure 7-74. PERI_CONFIG1 Register

31

30

29

28

20

12

27

19

11

26

25

24

PARITY

SPREAD_SPE

CTRUM_MODU

LATION_DIS

RESERVED

BUS_CURRENT_LIMIT

R/W-0h

23

R/W-1h

22

R/W-0h

21

18

17

16

BUS_CURRENT_LIMIT

BUS_CURREN

T_LIMIT_ENAB

LE

DIR_INPUT

DIR_CHANGE_ SELF_TEST_E ACTIVE_BRAK

MODE

NABLE

E_SPEED_DEL

TA_LIMIT

R/W-0h

13

R/W-0h

10

R/W-0h

9

R/W-0h

8

15

14

ACTIVE_BRAKE_SPEED_DELTA_LIMIT

ACTIVE_BRAKE_MOD_INDEX_LIMIT

SPEED_RANG ALARM_PIN_DI

E_SEL

S

R/W-0h

7

6

5

4

3

2

1

0

RESERVED

R/W-0h

Table 7-38. PERI_CONFIG1 Register Field Descriptions

Bit

Field

Type

Reset

Description

31

30

PARITY

R/W

0h

Parity bit

SPREAD_SPECTRUM_M R/W

ODULATION_DIS

1h

Spread spectrum modulation disable

0h = SSM is Enabled

1h = SSM is Disabled

29-26

25-22

RESERVED

R/W

0h

Reserved

BUS_CURRENT_LIMIT

Bus current limit

0h = 0.125 A

1h = 0.25 A

2h = 0.5 A

3h = 1.0 A

4h = 1.5 A

5h = 2.0 A

6h = 2.5 A

7h = 3.0 A

8h = 3.5 A

9h = 4.0 A

Ah = 4.5 A

Bh = 5.0 A

Ch = 5.5 A

Dh = 6.0 A

Eh = 7.0 A

Fh = 8.0 A

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Table 7-38. PERI_CONFIG1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

21

BUS_CURRENT_LIMIT_E R/W

NABLE

0h

Bus current limit enable

0h = Disable

1h = Enable

20-19

DIR_INPUT

R/W

0h

DIR pin override

0h = Hardware Pin DIR

1h = Override DIR pin with clockwise rotation OUTA-OUTB-OUTC

2h = Override DIR pin with counter clockwise rotation OUTA-OUTC-

OUTB

3h = Hardware Pin DIR

18

DIR_CHANGE_MODE

SELF_TEST_ENABLE

R/W

Response to change of DIR pin status

0h = Follow motor stop options and ISD routine on detecting DIR

change

1h = Change the direction through Reverse Drive while continuously

driving the motor

17

0h

Self-test on power up enable

0h = STL is disabled

1h = STL is enabled

16-13

ACTIVE_BRAKE_SPEED R/W

_DELTA_LIMIT

Difference between final speed and present speed beyond which

active braking will be applied

0h = 2.5%

1h = 5%

2h = 10%

3h = 15%

4h = 20%

5h = 25%

6h = 30%

7h = 35%

8h = 40%

9h = 45%

Ah = 50%

Bh = 60%

Ch = 70%

Dh = 80%

Eh = 90%

Fh = 100%

12-10

ACTIVE_BRAKE_MOD_I R/W

NDEX_LIMIT

0h

Modulation index limit beyond which active braking will be applied

0h = 0%

1h = 40%

2h = 50%

3h = 60%

4h = 70%

5h = 80%

6h = 90%

7h = 100%

9

8

SPEED_RANGE_SEL

ALARM_PIN_DIS

R/W

0h

Speed range selection for digital speed (PWM duty or frequency to

speed mode)

0h = 325 Hz to 95 kHz

1h = 10 Hz to 325 Hz

Alarm pin disable

0h = Alarm pin is enabled

1h = Alarm pin is disabled

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Table 7-38. PERI_CONFIG1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

7-0

RESERVED

R/W

0h

Reserved

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7.7.3.5 GD_CONFIG1 Register (Address = ACh) [Reset = 10228100h]

GD_CONFIG1 is shown in GD_CONFIG1 Register and described in GD_CONFIG1 Register Field Descriptions.

Return to the HARDWARE_CONFIGURATION Registers.

Register to configure gated driver settings1

Figure 7-75. GD_CONFIG1 Register

31

30

29

28

27

26

25

24

PARITY

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-1h

SLEW_RATE

R/W-0h

RESERVED

R/W-0h

23

22

21

20

19

18

17

16

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-1h

RESERVED

R/W-0h

OVP_SEL

R/W-0h

OVP_EN

R/W-0h

RESERVED

R/W-1h

OTW_REP

R/W-0h

15

14

13

12

11

10

9

8

RESERVED

R/W-1h

RESERVED

R/W-0h

OCP_DEG

R/W-0h

TRETRY

R/W-0h

OCP_LVL

R/W-0h

OCP_MODE

R/W-1h

7

6

5

4

3

2

1

0

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

CSA_GAIN

R/W-0h

Table 7-39. GD_CONFIG1 Register Field Descriptions

Bit

31

Field

PARITY

Type

R/W

Reset

Description

0h

Parity bit

30-29

28

RESERVED

SLEW_RATE

0h

Reserved

1h

27-26

0h

Slew rate

0h = Slew rate is 25 V/µs

1h = Slew rate is 50 V/µs

2h = Slew rate is 150 V/µs

3h = Slew rate is 200 V/µs

25-24

23

RESERVED

OVP_SEL

R/W

0h

1h

0h

Reserved

22

21

20

19

Overvoltage protection level

0h = VM overvoltage level is 32-V

1h = VM overvoltage level is 20-V

18

OVP_EN

R/W

0h

Overvoltage protection enable

0h = Overvoltage protection is disabled

1h = Overvoltage protection is enabled

17

16

RESERVED

OTW_REP

R/W

1h

0h

Reserved

Overtemperature warning reporting on nFAULT

0h = Over temperature reporting on nFAULT is disabled

1h = Over temperature reporting on nFAULT is enabled

15

14

RESERVED

R/W

1h

0h

Reserved

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Table 7-39. GD_CONFIG1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

13-12

OCP_DEG

R/W

0h

OCP deglitch time

0h = OCP deglitch time is 0.2 µs

1h = OCP deglitch time is 0.6 µs

2h = OCP deglitch time is 1.1 µs

3h = OCP deglitch time is 1.6 µs

11

10

TRETRY

R/W

0h

1h

OCP retry time

0h = OCP retry time is 5 ms

1h = OCP retry time is 500 ms

OCP_LVL

OCP_MODE

OCP level

0h = OCP level is 16 A (Typical)

1h = OCP level is 24 A (Typical)

9-8

OCP fault mode

0h = Overcurrent causes a latched fault

1h = Overcurrent causes an automatic retrying fault

2h = Overcurrent is report only but no action is taken

3h = Overcurrent is not reported and no action is taken

7

6

RESERVED

CSA_GAIN

R/W

0h

Reserved

5

4

3

2

1-0

Current Sense Amplifier (CSA) gain (used only if

DYNAMIC_CSA_GAIN_EN = 0)

0h = CSA gain is 0.15 V/A

1h = CSA gain is 0.3 V/A

2h = CSA gain is 0.6 V/A

3h = CSA gain is 1.2 V/A

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7.7.3.6 GD_CONFIG2 Register (Address = AEh) [Reset = 01200000h]

GD_CONFIG2 is shown in GD_CONFIG2 Register and described in GD_CONFIG2 Register Field Descriptions.

Return to the HARDWARE_CONFIGURATION Registers.

Register to configure gated driver settings2

Figure 7-76. GD_CONFIG2 Register

31

30

29

28

27

26

25

24

PARITY

DELAY_COMP

_EN

TARGET_DELAY

BUCK_SR

BUCK_PS_DIS

R/W-0h

22

R/W-0h

17

R/W1C-1h

16

23

21

13

5

20

19

11

3

18

10

2

BUCK_CL

R/W-0h

BUCK_SEL

R/W-1h

BUCK_DIS

R/W-0h

RESERVED

R/W-0h

15

14

6

12

9

1

8

0

RESERVED

R/W-0h

7

4

RESERVED

R/W-0h

Table 7-40. GD_CONFIG2 Register Field Descriptions

Bit

31

30

Field

Type

R/W

Reset

Description

PARITY

0h

Parity bit

DELAY_COMP_EN

0h

Driver delay compensation enable

0h = Disable

1h = Enable

29-26

TARGET_DELAY

R/W

0h

Target delay

0h = Automatic based on slew rate

1h = 0.4 µs

2h = 0.6 µs

3h = 0.8 µs

4h = 1 µs

5h = 1.2 µs

6h = 1.4 µs

7h = 1.6 µs

8h = 1.8 µs

9h = 2 µs

Ah = 2.2 µs

Bh = 2.4 µs

Ch = 2.6 µs

Dh = 2.8 µs

Eh = 3 µs

Fh = 3.2 µs

25

24

BUCK_SR

R/W

0h

1h

Buck slew rate

0h = Buck's FET slew rate is 1000V/µs

1h = Buck's FET slew rate is 200V/µs

BUCK_PS_DIS

R/W1C

Buck power sequencing disable

0h = Buck power sequencing is enabled

1h = Buck power sequencing is disabled

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Table 7-40. GD_CONFIG2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

23

BUCK_CL

R/W

0h

Buck current limit

0h = Buck regulator current limit is set to 600 mA

1h = Buck regulator current limit is set to 150 mA

22-21

BUCK_SEL

R/W

1h

Buck voltage selection

0h = Buck voltage is 3.3 V

1h = Buck voltage is 5.0 V

2h = Buck voltage is 4.0 V

3h = Buck voltage is 5.7 V

20

BUCK_DIS

RESERVED

R/W

0h

Buck disable

0h = Buck regulator is enabled

1h = Buck regulator is disabled

19-0

Reserved

7.7.4 Internal_Algorithm_Configuration Registers

INTERNAL_ALGORITHM_CONFIGURATION Registers

the Internal_Algorithm_Configuration registers. All

lists

register

the

memory-mapped

addresses

registers

not listed

for

in

offset

INTERNAL_ALGORITHM_CONFIGURATION Registers should be considered as reserved locations and the

register contents should not be modified.

Table 7-41. INTERNAL_ALGORITHM_CONFIGURATION Registers

Address Acronym

Register Name

Section

A0h

A2h

INT_ALGO_1

INT_ALGO_2

Internal Algorithm Configuration 1

Internal Algorithm Configuration 2

Section 7.7.4.1

Section 7.7.4.2

Complex bit access types are encoded to fit into small table cells. Internal_Algorithm_Configuration Access Type

Codes shows the codes that are used for access types in this section.

Table 7-42. Internal_Algorithm_Configuration

Access Type Codes

Access Type

Read Type

R

Code

Description

R

Read

Write Type

W

Write

Reset or Default Value

-n

Value after reset or the default

value

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7.7.4.1 INT_ALGO_1 Register (Address = A0h) [Reset = X]

INT_ALGO_1 is shown in INT_ALGO_1 Register and described in INT_ALGO_1 Register Field Descriptions.

Return to the INTERNAL_ALGORITHM_CONFIGURATION Registers.

Register to configure internal algorithm parameters1

Figure 7-77. INT_ALGO_1 Register

31

30

29

28

27

26

25

24

PARITY

RESERVED

FG_ANGLE_IN SPEED_PIN_GLITCH_FILTER FAST_ISD_EN

ISD_STOP_TIME

TERPOLATE_E

N

R/W-0h

23

R/W-X

22

R/W-0h

21

R/W-0h

20

12

19

11

18

17

9

16

ISD_RUN_TIME

R/W-0h

ISD_TIMEOUT

R/W-0h

AUTO_HANDOFF_MIN_BEMF

R/W-0h

RESERVED

R/W-0h

15

14

13

10

8

RESERVED

R/W-0h

MPET_IPD_CURRENT_LIMIT

R/W-0h

MPET_IPD_FREQ

R/W-0h

MPET_OPEN_LOOP_CURRENT_REF

R/W-0h

7

6

5

4

3

2

1

0

MPET_OPEN_LOOP_SPEED_R

EF

MPET_OPEN_LOOP_SLEW_RATE

REV_DRV_OPEN_LOOP_DEC

R/W-0h

Table 7-43. INT_ALGO_1 Register Field Descriptions

Bit

31

30

29

Field

Type

R/W

Reset

Description

PARITY

RESERVED

0h

Parity bit

X

Reserved

FG_ANGLE_INTERPOLA R/W

TE_EN

0h

Angle interpolation for FG enable

0h = Disable

1h = Enable

28-27

SPEED_PIN_GLITCH_FIL R/W

TER

0h

Glitch filter applied on speed pin input

0h = No Glitch Filter

1h = 0.2 µs

2h = 0.5 µs

3h = 1.0 µs

26

FAST_ISD_EN

R/W

0h

Fast initial speed detection enable

0h = Disable Fast ISD

1h = Enable Fast ISD

25-24

ISD_STOP_TIME

Persistence time for declaring motor has stopped

0h = 1 ms

1h = 5 ms

2h = 50 ms

3h = 100 ms

23-22

ISD_RUN_TIME

R/W

0h

Persistence time for declaring motor is running

0h = 1 ms

1h = 5 ms

2h = 50 ms

3h = 100 ms

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Table 7-43. INT_ALGO_1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

21-20

ISD_TIMEOUT

R/W

0h

Timeout in case ISD is unable to reliably detect speed or direction

0h = 500ms

1h = 750 ms

2h = 1000 ms

3h = 2000 ms

19-17

AUTO_HANDOFF_MIN_B R/W

EMF

0h

Minimum BEMF for handoff

0h = 0 mV

1h = 50 mV

2h = 100 mV

3h = 250 mV

4h = 500 mV

5h = 1000 mV

6h = 1250 mV

7h = 1500 mV

16-15

14-13

RESERVED

R/W

0h

Reserved

MPET_IPD_CURRENT_LI R/W

MIT

IPD current limit for MPET

0h = 0.1 A

1h = 0.5 A

2h = 1.0 A

3h = 2.0 A

12-11

10-8

MPET_IPD_FREQ

R/W

0h

Number of times IPD is executed for MPET

0h = 1

1h = 2

2h = 4

3h = 8

MPET_OPEN_LOOP_CU R/W

RRENT_REF

Open loop current reference

0h = 1 A

1h = 2 A

2h = 3 A

3h = 4 A

4h = 5 A

5h = 6 A

6h = 7 A

7h = 8 A

7-6

5-3

MPET_OPEN_LOOP_SP R/W

EED_REF

0h

Open loop speed reference for MPET (% of MAXIMUM_SPEED)

0h = 15%

1h = 25%

2h = 35%

3h = 50%

MPET_OPEN_LOOP_SL R/W

EW_RATE

Open loop slew rate for MPET (Hz/s)

0h = 0.1 Hz/s

1h = 0.5 Hz/s

2h = 1 Hz/s

3h = 2 Hz/s

4h = 3 Hz/s

5h = 5 Hz/s

6h = 10 Hz/s

7h = 20 Hz/s

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Table 7-43. INT_ALGO_1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

2-0

REV_DRV_OPEN_LOOP R/W

_DEC

0h

% of open loop acceleration to be applied during open loop

deceleration in reverse drive

0h = 50%

1h = 60%

2h = 70%

3h = 80%

4h = 90%

5h = 100%

6h = 125%

7h = 150%

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7.7.4.2 INT_ALGO_2 Register (Address = A2h) [Reset = 00000000h]

INT_ALGO_2 is shown in INT_ALGO_2 Register and described in INT_ALGO_2 Register Field Descriptions.

Return to the INTERNAL_ALGORITHM_CONFIGURATION Registers.

Register to configure internal algorithm parameters2

Figure 7-78. INT_ALGO_2 Register

31

30

22

14

6

29

21

13

5

28

20

12

4

27

26

18

10

2

25

17

9

24

16

8

PARITY

R/W-0h

RESERVED

R/W-0h

23

15

7

19

RESERVED

R/W-0h

11

3

RESERVED

R/W-0h

CL_SLOW_ACC

R/W-0h

1

0

CL_SLOW_ACC

ACTIVE_BRAKE_BUS_CURRENT_SLEW_RATE MPET_IPD_SE MPET_KE_ME IPD_HIGH_RE

LECT

AS_PARAMET SOLUTION_EN

ER_SELECT

R/W-0h

Table 7-44. INT_ALGO_2 Register Field Descriptions

Bit

31

Field

Type

R/W

Reset

Description

PARITY

0h

Parity bit

30-10

9-6

RESERVED

CL_SLOW_ACC

0h

Reserved

0h

Close loop acceleration when estimator is not yet fully aligned

0h = 0.1 Hz/s

1h = 1 Hz/s

2h = 2 Hz/s

3h = 3 Hz/s

4h = 5 Hz/s

5h = 10 Hz/s

6h = 20 Hz/s

7h = 30 Hz/s

8h = 40 Hz/s

9h = 50 Hz/s

Ah = 100 Hz/s

Bh = 200 Hz/s

Ch = 500 Hz/s

Dh = 750 Hz/s

Eh = 1000 Hz/s

Fh = 2000 Hz/s

5-3

ACTIVE_BRAKE_BUS_C R/W

URRENT_SLEW_RATE

0h

Bus current slew rate during active braking

0h = 10 A/s

1h = 50 A/s

2h = 100 A/s

3h = 250 A/s

4h = 500 A/s

5h = 1000 A/s

6h = 5000 A/s

7h = No Limit

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Table 7-44. INT_ALGO_2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

2

MPET_IPD_SELECT

R/W

0h

Selection between MPET_IPD_CURRENT_LIMIT for IPD current

limit, MPET_IPD_FREQ for IPD Repeat OR IPD_CURR_THR for

IPD current limit, IPD_REPEAT for IPD Repeat

0h = Configured parameters for normal motor operation

1h = MPET specific parameters

1

0

MPET_KE_MEAS_PARA R/W

METER_SELECT

0h

Selection between MPET_OPEN_LOOP_SLEW_RATE for slew

rate, MPET_OPEN_LOOP_CURR_REF for current reference,

MPET_OPEN_LOOP_SPEED_REF for speed reference OR

OL_ACC_A1, OL_ACC_A2 for slew rate, 80% of ILIMIT for current

reference and 50% of MAX_SPEED for speed reference

0h = Configured parameters for normal motor operation

1h = MPET specific parameters

IPD_HIGH_RESOLUTION R/W

_EN

IPD high resolution enable

0h = Disable

1h = Enable

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7.8 RAM (Volatile) Register Map

7.8.1 Fault_Status Registers

FAULT_STATUS Registers lists the memory-mapped registers for the Fault_Status registers. All register offset

addresses not listed in FAULT_STATUS Registers should be considered as reserved locations and the register

contents should not be modified.

Table 7-45. FAULT_STATUS Registers

Address Acronym

Register Name

Section

E0h

E2h

GATE_DRIVER_FAULT_STATUS Fault Status Register

CONTROLLER_FAULT_STATUS Fault Status Register

Section 7.8.1.1

Section 7.8.1.2

Complex bit access types are encoded to fit into small table cells. Fault_Status Access Type Codes shows the

codes that are used for access types in this section.

Table 7-46. Fault_Status Access Type Codes

Access Type

Read Type

R

Code

Description

R

Read

Reset or Default Value

-n

Value after reset or the default

value

7.8.1.1 GATE_DRIVER_FAULT_STATUS Register (Address = E0h) [Reset = 00000000h]

GATE_DRIVER_FAULT_STATUS is shown in GATE_DRIVER_FAULT_STATUS Register and described in

GATE_DRIVER_FAULT_STATUS Register Field Descriptions.

Return to the FAULT_STATUS Registers.

Status of various gate driver faults

Figure 7-79. GATE_DRIVER_FAULT_STATUS Register

31

30

29

28

27

26

25

24

DRIVER_FAUL

T

BK_FLT

RESERVED

OCP

NPOR

OVP

OT

RESERVED

R-0h

23

22

21

20

19

18

17

16

OTW

R-0h

TSD

R-0h

OCP_HC

R-0h

OCP_LC

R-0h

OCP_HB

R-0h

OCP_LB

R-0h

OCP_HA

R-0h

OCP_LA

R-0h

15

14

13

12

11

10

9

8

RESERVED

R-0h

OTP_ERR

R-0h

BUCK_OCP

R-0h

BUCK_UV

R-0h

VCP_UV

R-0h

RESERVED

R-0h

7

6

5

4

3

2

1

0

RESERVED

R-0h

Table 7-47. GATE_DRIVER_FAULT_STATUS Register Field Descriptions

Bit

Field

Type

Reset

Description

31

DRIVER_FAULT

R

0h

Logic OR of driver fault registers

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Table 7-47. GATE_DRIVER_FAULT_STATUS Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

30

BK_FLT

R

0h

Buck fault

0h = No buck regulator fault condition is detected

1h = Buck regulator fault condition is detected

29

28

RESERVED

OCP

R

0h

Reserved

Overcurrent protection status

0h = No overcurrent condition is detected

1h = Overcurrent condition is detected

27

26

25

NPOR

OVP

OT

R

0h

Supply power on reset

0h = Power on reset condition is detected on VM

1h = No power-on-reset condition is detected on VM

Supply overvoltage protection status

0h = No overvoltage condition is detected on VM

1h = Overvoltage condition is detected on VM

Overtemperature fault status

0h = No overtemperature warning / shutdown is detected

1h = Overtemperature warning / shutdown is detected

24

23

RESERVED

OTW

R

0h

Reserved

Overtemperature warning status

0h = No overtemperature warning is detected

1h = Overtemperature warning is detected

22

21

20

19

18

17

16

TSD

R

0h

Overtemperature shutdown status

0h = No overtemperature shutdown is detected

1h = Overtemperature shutdown is detected

OCP_HC

OCP_LC

OCP_HB

OCP_LB

OCP_HA

OCP_LA

Overcurrent status on high-side switch of OUTC

0h = No overcurrent detected on high-side switch of OUTC

1h = Overcurrent detected on high-side switch of OUTC

Overcurrent status on low-side switch of OUTC

0h = No overcurrent detected on low-side switch of OUTC

1h = Overcurrent detected on low-side switch of OUTC

Overcurrent status on high-side switch of OUTB

0h = No overcurrent detected on high-side switch of OUTB

1h = Overcurrent detected on high-side switch of OUTB

Overcurrent status on low-side switch of OUTB

0h = No overcurrent detected on low-side switch of OUTB

1h = Overcurrent detected on low-side switch of OUTB

Overcurrent status on high-side switch of OUTA

0h = No overcurrent detected on high-side switch of OUTA

1h = Overcurrent detected on high-side switch of OUTA

Overcurrent status on low-side switch of OUTA

0h = No overcurrent detected on low-side switch of OUTA

1h = Overcurrent detected on low-side switch of OUTA

15

14

RESERVED

OTP_ERR

R

0h

Reserved

One-time programmable (OTP) error

0h = No OTP error is detected

1h = OTP Error is detected

13

BUCK_OCP

R

0h

Buck regulator overcurrent status

0h = No buck regulator overcurrent is detected

1h = Buck regulator overcurrent is detected

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Table 7-47. GATE_DRIVER_FAULT_STATUS Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

12

BUCK_UV

R

0h

Buck regulator undervoltage status

0h = No buck regulator undervoltage is detected

1h = Buck regulator undervoltage is detected

11

VCP_UV

R

0h

Charge pump undervoltage status

0h = No charge pump undervoltage is detected

1h = Charge pump undervoltage is detected

10-0

RESERVED

Reserved

7.8.1.2 CONTROLLER_FAULT_STATUS Register (Address = E2h) [Reset = 00000000h]

CONTROLLER_FAULT_STATUS is shown in CONTROLLER_FAULT_STATUS Register and described in

CONTROLLER_FAULT_STATUS Register Field Descriptions.

Return to the FAULT_STATUS Registers.

Status of various controller faults

Figure 7-80. CONTROLLER_FAULT_STATUS Register

31

30

29

28

27

26

25

24

CONTROLLER

_FAULT

RESERVED

IPD_FREQ_FA IPD_T1_FAULT IPD_T2_FAULT BUS_CURREN MPET_IPD_FA MPET_BEMF_

ULT

T_LIMIT_STAT

US

ULT

FAULT

R-0h

19

R-0h

18

R-0h

17

R-0h

16

23

22

21

20

ABN_SPEED

ABN_BEMF

NO_MTR

MTR_LCK

LOCK_ILIMIT HW_LOCK_ILI MTR_UNDER_ MTR_OVER_V

MIT

VOLTAGE

OLTAGE

R-0h

15

R-0h

14

R-0h

13

R-0h

12

R-0h

11

R-0h

10

9

8

SPEED_LOOP CURRENT_LO

_SATURATION OP_SATURATI

ON

RESERVED

R-0h

7

R-0h

6

5

4

3

2

1

0

RESERVED

R-0h

RESERVED

R-0h

RESERVED

R-0h

RESERVED

R-0h

Table 7-48. CONTROLLER_FAULT_STATUS Register Field Descriptions

Bit

Field

Type

Reset

Description

31

CONTROLLER_FAULT

R

0h

Logic OR of controller fault status registers

0h = No controller fault condition is detected

1h = Controller fault condition is detected

30

29

RESERVED

R

0h

Reserved

IPD_FREQ_FAULT

Indicates IPD frequency fault

0h = No IPD frequency fault detected

1h = IPD frequency fault detected

28

IPD_T1_FAULT

R

0h

Indicates IPD T1 fault

0h = No IPD T1 fault detected

1h = IPD T1 fault detected

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Table 7-48. CONTROLLER_FAULT_STATUS Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

27

IPD_T2_FAULT

R

0h

Indicates IPD T2 fault

0h = No IPD T2 fault detected

1h = IPD T2 fault detected

26

25

24

23

22

21

20

19

18

17

16

15

14

BUS_CURRENT_LIMIT_S R

TATUS

0h

Indicates status of bus current limit

0h = No bus current limit fault detected

1h = Bus current limit fault detected

MPET_IPD_FAULT

MPET_BEMF_FAULT

ABN_SPEED

R

Indicates error during resistance and inductance measurement

0h = No MPET IPD fault detected

1h = MPET IPD fault detected

Indicates error during BEMF constant measurement

0h = No MPET BEMF fault detected

1h = MPET BEMF fault detected

Indicates abnormal speed motor lock condition

0h = No abnormal speed fault detected

1h = Abnormal speed fault detected

ABN_BEMF

Indicates abnormal BEMF motor lock condition

0h = No abnormal BEMF fault detected

1h = Abnormal BEMF fault detected

NO_MTR

Indicates no motor fault

0h = No motor fault not detected

1h = No motor fault detected

MTR_LCK

Indicates when one of the motor lock is triggered

0h = Motor lock fault not detected

1h = Motor lock fault detected

LOCK_ILIMIT

Indicates lock Ilimit fault

0h = No lock current limit fault detected

1h = Lock current limit fault detected

HW_LOCK_ILIMIT

MTR_UNDER_VOLTAGE

MTR_OVER_VOLTAGE

Indicates hardware lock Ilimit fault

0h = No hardware lock current limit fault detected

1h = Hardware lock current limit fault detected

Indicates motor undervoltage fault

0h = No motor undervoltage detected

1h = Motor undervoltage detected

Indicates motor overvoltage fault

0h = No motor overvoltage detected

1h = Motor overvoltage detected

SPEED_LOOP_SATURAT R

ION

Indicates speed loop saturation

0h = No speed loop saturation detected

1h = Speed loop saturation detected

CURRENT_LOOP_SATU

RATION

R

Indicates current loop saturation

0h = No current loop saturation detected

1h = Current loop saturation detected

13-3

RESERVED

R

0h

Reserved

2

1

0

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7.8.2 System_Status Registers

SYSTEM_STATUS Registers lists the memory-mapped registers for the System_Status registers. All register

offset addresses not listed in SYSTEM_STATUS Registers should be considered as reserved locations and the

register contents should not be modified.

Table 7-49. SYSTEM_STATUS Registers

Address Acronym

Register Name

Section

E4h

E6h

E8h

ALGO_STATUS

System Status Register

Section 7.8.2.1

Section 7.8.2.2

Section 7.8.2.3

MTR_PARAMS

ALGO_STATUS_MPET

Complex bit access types are encoded to fit into small table cells. System_Status Access Type Codes shows the

codes that are used for access types in this section.

Table 7-50. System_Status Access Type Codes

Access Type

Read Type

R

Code

Description

R

Read

Reset or Default Value

-n

Value after reset or the default

value

7.8.2.1 ALGO_STATUS Register (Address = E4h) [Reset = 00000000h]

ALGO_STATUS is shown in ALGO_STATUS Register and described in ALGO_STATUS Register Field

Descriptions.

Return to the SYSTEM_STATUS Registers.

Status of various system and algorithm parameters

Figure 7-81. ALGO_STATUS Register

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

25

17

9

24

16

8

VOLT_MAG

R-0h

VOLT_MAG

R-0h

RESERVED

R-0h

2

1

0

RESERVED

R-0h

RESERVED

R-0h

RESERVED

R-0h

RESERVED

R-0h

RESERVED

R-0h

Table 7-51. ALGO_STATUS Register Field Descriptions

Bit

Field

Type

Reset

Description

31-16

VOLT_MAG

R

0h

16-bit value indicating output voltage magnitude. Voltage magnitude

= (VOLT_MAG * 100 / 32767) %

15-4

3

RESERVED

R

0h

Reserved

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Table 7-51. ALGO_STATUS Register Field Descriptions (continued)

Bit

2

Field

Type

Reset

Description

Reserved

RESERVED

R

0h

1

R

0h

0

R

0h

7.8.2.2 MTR_PARAMS Register (Address = E6h) [Reset = 00000000h]

MTR_PARAMS is shown in MTR_PARAMS Register and described in MTR_PARAMS Register Field

Descriptions.

Return to the SYSTEM_STATUS Registers.

Status of various motor parameters

Figure 7-82. MTR_PARAMS Register

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

1

16

0

MOTOR_R

R-0h

MOTOR_BEMF_CONST

R-0h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

MOTOR_L

R-0h

RESERVED

R-0h

Table 7-52. MTR_PARAMS Register Field Descriptions

Bit

Field

Type

Reset

Description

31-24

23-16

15-8

7-0

MOTOR_R

R

0h

8-bit value indicating measured motor resistance

8-bit value indicating measured BEMF constant

8-bit value indicating measured motor inductance

Reserved

MOTOR_BEMF_CONST

MOTOR_L

R

0h

R

0h

RESERVED

R

0h

7.8.2.3 ALGO_STATUS_MPET Register (Address = E8h) [Reset = 00000000h]

ALGO_STATUS_MPET is shown in ALGO_STATUS_MPET Register and described in ALGO_STATUS_MPET

Register Field Descriptions.

Return to the SYSTEM_STATUS Registers.

Status of various MPET parameters

Figure 7-83. ALGO_STATUS_MPET Register

31

30

29

28

27

26

25

24

MPET_R_STAT MPET_L_STAT MPET_KE_STA MPET_MECH_

MPET_PWM_FREQ

R-0h

US

TUS

R-0h

STATUS

R-0h

23

15

7

22

14

6

21

13

5

20

19

11

3

18

10

2

17

16

8

RESERVED

R-0h

12

4

9

RESERVED

R-0h

1

0

RESERVED

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Figure 7-83. ALGO_STATUS_MPET Register (continued)

R-0h

Table 7-53. ALGO_STATUS_MPET Register Field Descriptions

Bit

31

Field

Type

Reset

Description

MPET_R_STATUS

MPET_L_STATUS

MPET_KE_STATUS

MPET_MECH_STATUS

MPET_PWM_FREQ

R

0h

Indicates status of resistance measurement

Indicates status of inductance measurement

Indicates status of BEMF constant measurement

Indicates status of mechanical parameter measurement

30

R

0h

29

R

0h

28

R

0h

27-24

R

0h

4-bit value indicating MPET recommended PWM switching

frequency based on electrical time constant

23-0

RESERVED

R

0h

Reserved

7.8.3 Device_Control Registers

DEVICE_CONTROL Registers lists the memory-mapped registers for the Device_Control registers. All register

offset addresses not listed in DEVICE_CONTROL Registers should be considered as reserved locations and the

register contents should not be modified.

Table 7-54. DEVICE_CONTROL Registers

Address Acronym

EAh DEV_CTRL

Register Name

Section

Section 7.8.3.1

Complex bit access types are encoded to fit into small table cells. Device_Control Access Type Codes shows the

codes that are used for access types in this section.

Table 7-55. Device_Control Access Type Codes

Access Type

Read Type

R

Code

Description

R

Read

Write Type

W

Write

Reset or Default Value

-n

Value after reset or the default

value

7.8.3.1 DEV_CTRL Register (Address = EAh) [Reset = 00000000h]

DEV_CTRL is shown in DEV_CTRL Register and described in DEV_CTRL Register Field Descriptions.

Return to the DEVICE_CONTROL Registers.

Figure 7-84. DEV_CTRL Register

31

30

29

28

27

26

25

24

EEPROM_WRT EEPROM_REA

D

CLR_FLT

CLR_FLT_RET

RY_COUNT

EEPROM_WRITE_ACCESS_KEY

W-0h

R/W-0h

23

R/W-0h

22

W-0h

21

W-0h

20

19

11

18

17

16

8

EEPROM_WRITE_ACCESS_KEY

W-0h

FORCED_ALIGN_ANGLE

W-0h

15

14

13

FORCED_ALIGN_ANGLE

12

10

9

WATCHDOG_T

ICKLE

RESERVED

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Figure 7-84. DEV_CTRL Register (continued)

W-0h

R/W-0h

W-0h

7

6

5

4

3

2

1

0

RESERVED

W-0h

Table 7-56. DEV_CTRL Register Field Descriptions

Bit

31

30

29

28

Field

Type

R/W

W

Reset

Description

EEPROM_WRT

EEPROM_READ

CLR_FLT

0h

Write the configuration to EEPROM

0h

Read the default configuration from EEPROM

Clears all faults

0h

CLR_FLT_RETRY_COUN

T

W

0h

Clears fault retry count

27-20

19-11

10

EEPROM_WRITE_ACCE

SS_KEY

W

0h

EEPROM write access key

FORCED_ALIGN_ANGLE W

9-bit value (in °) used during forced align state ( FORCE_ALIGN_EN

= 1) Angle applied (°) = FORCED_ALIGN_ANGLE % 360°

WATCHDOG_TICKLE

RESERVED

R/W

RAM bit to tickle watchdog in I2C mode. This bit should be written to

1b by external controller every EXT_WD_CONFIG. MCF8316A will

reset this bit to 0b.

9-0

W

0h

Reserved

7.8.4 Algorithm_Control Registers

ALGORITHM_CONTROL Registers lists the memory-mapped registers for the Algorithm_Control registers. All

register offset addresses not listed in ALGORITHM_CONTROL Registers should be considered as reserved

locations and the register contents should not be modified.

Table 7-57. ALGORITHM_CONTROL Registers

Address Acronym

Register Name

Section

ECh

EEh

F0h

F2h

ALGO_CTRL1

Algorithm Control Register

Current PI Controller Register

Speed PI Controller Register

Section 7.8.4.1

Section 7.8.4.2

Section 7.8.4.3

Section 7.8.4.4

ALGO_CTRL2

CURRENT_PI

SPEED_PI

Complex bit access types are encoded to fit into small table cells. Algorithm_Control Access Type Codes shows

the codes that are used for access types in this section.

Table 7-58. Algorithm_Control Access Type Codes

Access Type

Read Type

R

Code

Description

R

Read

Write Type

W

Write

Reset or Default Value

-n

Value after reset or the default

value

7.8.4.1 ALGO_CTRL1 Register (Address = ECh) [Reset = 00000000h]

ALGO_CTRL1 is shown in ALGO_CTRL1 Register and described in ALGO_CTRL1 Register Field Descriptions.

Return to the ALGORITHM_CONTROL Registers.

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Algorithm control register for debug

Figure 7-85. ALGO_CTRL1 Register

31

30

22

14

29

21

13

28

27

DIGITAL_SPEED_CTRL

W-0h

26

18

10

25

17

9

24

16

8

OVERRIDE

W-0h

23

20

19

DIGITAL_SPEED_CTRL

W-0h

15

12

11

CLOSED_LOO FORCE_ALIGN FORCE_SLOW FORCE_IPD_E FORCE_ISD_E FORCE_ALIGN FORCE_IQ_REF_SPEED_LOOP

P_DIS

_EN

_FIRST_CYCL

E_EN

N

_ANGLE_SRC_

SEL

_DIS

W-0h

7

W-0h

6

W-0h

5

W-0h

4

W-0h

3

W-0h

2

W-0h

1

0

FORCE_IQ_REF_SPEED_LOOP_DIS

W-0h

Table 7-59. ALGO_CTRL1 Register Field Descriptions

Bit

Field

Type

Reset

Description

31

OVERRIDE

W

0h

Use to control the SPD_CTRL bits. If OVERRIDE = 1b, speed

command can be written by the user through serial interface.

0h = SPEED_CMD using Analog/PWM/Freq mode

1h = SPEED_CMD using SPD_CTRL[14:0]

30-16

15

DIGITAL_SPEED_CTRL

CLOSED_LOOP_DIS

W

0h

Digital speed control If OVERRIDE = 1b, then SPEED_CMD is

control using DIGITAL_SPEED_CTRL

Use to disable closed loop

0h = Enable Closed Loop

1h = Disable Closed loop, motor commutation in open loop

14

13

FORCE_ALIGN_EN

W

0h

Force align state enable

0h = Disable Force Align state, device comes out of align state if

MTR_STARTUP is selected as ALIGN or DOUBLE ALIGN

1h = Enable Force Align state, device stays in align state if

MTR_STARTUP is selected as ALIGN or DOUBLE ALIGN

FORCE_SLOW_FIRST_C W

YCLE_EN

Force slow first cycle enable

0h = Disable Force Slow First Cycle state, device comes out of

slow first cycle state if MTR_STARTUP is selected as SLOW FIRST

CYCLE

1h = Enable Force Slow First Cycle state, device stays in slow first

cycle state if MTR_STARTUP is selected as SLOW FIRST CYCLE

12

11

FORCE_IPD_EN

FORCE_ISD_EN

W

0h

Force IPD enable

0h = Disable Force IPD state, device comes out of IPD state if

MTR_STARTUP is selected as IPD

1h = Enable Force IPD state, device stays in IPD state if

MTR_STARTUP is selected as IPD

Force ISD enable

0h = Disable Force ISD state, device comes out of ISD state if

ISD_EN is set

1h = Enable Force ISD state, device stays in ISD state if ISD_EN is

set

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Table 7-59. ALGO_CTRL1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

10

FORCE_ALIGN_ANGLE_

SRC_SEL

W

0h

Force align angle state source select

0h = Force Align Angle defined by ALIGN_ANGLE

1h = Force Align Angle defined by FORCED_ALIGN_ANGLE

9-0

FORCE_IQ_REF_SPEED

_LOOP_DIS

W

0h

Sets Iq_ref when speed loop is disabled If SPEED_LOOP_DIS

= 1b, then Iq_ref is set using IQ_REF_SPEED_LOOP_DIS

Iq_ref = (FORCE_IQ_REF_SPEED_LOOP_DIS / 500) *

10, if FORCE_IQ_REF_SPEED_LOOP_DIS < 500 -

(FORCE_IQ_REF_SPEED_LOOP_DIS - 512) / 500 * 10 if

FORCE_IQ_REF_SPEED_LOOP_DIS > 512 Valid values are 0 to

500 and 512 to 1000

7.8.4.2 ALGO_CTRL2 Register (Address = EEh) [Reset = 00000000h]

ALGO_CTRL2 is shown in ALGO_CTRL2 Register and described in ALGO_CTRL2 Register Field Descriptions.

Return to the ALGORITHM_CONTROL Registers.

Algorithm control register for debug

Figure 7-86. ALGO_CTRL2 Register

31

30

29

28

27

26

25

24

RESERVED

CURRENT_LO FORCE_VD_CURRENT_LOOP_

OP_DIS

W-0h

DIS

W-0h

21

W-0h

23

15

7

22

14

6

20

19

18

17

9

16

8

FORCE_VD_CURRENT_LOOP_DIS

W-0h

13

5

12

11

10

FORCE_VQ_CURRENT_LOOP_DIS

W-0h

4

3

2

1

0

FORCE_VQ_CURRENT_LOOP_ MPET_CMD

DIS

MPET_R

MPET_L

MPET_KE

MPET_MECH MPET_WRITE_

SHADOW

W-0h

Table 7-60. ALGO_CTRL2 Register Field Descriptions

Bit

31-27

26

Field

Type

Reset

Description

RESERVED

W

0h

Reserved

CURRENT_LOOP_DIS

W

0h

Use to control the FORCE_VD_CURRENT_LOOP_DIS and

FORCE_VQ_CURRENT_LOOP_DIS. If CURRENT_LOOP_DIS =

1b, current loop and speed loop are disabled

0h = Enable Current Loop

1h = Disable Current Loop

25-16

FORCE_VD_CURRENT_

LOOP_DIS

W

0h

Sets Vd_ref when current loop and speed loop

are disabled If CURRENT_LOOP_DIS = 1b, then

Vd is controlled using FORCE_VD_CURRENT_LOOP_DIS

Vd_ref = (FORCE_VD_CURRENT_LOOP_DIS / 500)

if FORCE_VD_CURRENT_LOOP_DIS < 500 -

(FORCE_VD_CURRENT_LOOP_DIS - 512) / 500 if

FORCE_VD_CURRENT_LOOP_DIS > 512 Valid values: 0 to 500

and 512 to 1000

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Table 7-60. ALGO_CTRL2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

15-6

FORCE_VQ_CURRENT_

LOOP_DIS

W

0h

Sets Vq_ref when current loop speed loop are

disabled If CURRENT_LOOP_DIS = 1b, then Vq

is controlled using FORCE_VQ_CURRENT_LOOP_DIS

Vq_ref = (FORCE_VQ_CURRENT_LOOP_DIS / 500)

if FORCE_VQ_CURRENT_LOOP_DIS < 500 -

(FORCE_VQ_CURRENT_LOOP_DIS - 512) / 500 if

FORCE_VQ_CURRENT_LOOP_DIS > 512 Valid values: 0 to 500

and 512 to 1000

5

4

MPET_CMD

MPET_R

W

0h

Initiates motor parameter measurement routine when set to 1b

Enables motor resistance measurement during motor parameter

measurement routine

0h = Disable Motor Resistance measurement during motor

parameter measurement routine

1h = Enable Motor Resistance measurement during motor parameter

measurement routine

3

2

1

0

MPET_L

W

0h

Enables motor inductance measurement during motor parameter

measurement routine

0h = Disable Motor Inductance measurement during motor

parameter measurement routine

1h = Enable Motor Inductance measurement during motor parameter

measurement routine

MPET_KE

Enables motor BEMF constant measurement during motor

parameter measurement routine

0h = Disables Motor BEMF constant measurement during motor

parameter measurement routine

1h = Enable Motor BEMF constant measurement during motor

parameter measurement routine

MPET_MECH

Enables motor mechanical parameter measurement during motor

parameter measurement routine

0h = Disable Motor mechanical parameter measurement during

motor parameter measurement routine

1h = Enable Motor mechanical parameter measurement during

motor parameter measurement routine

MPET_WRITE_SHADOW

Write measured parameters to shadow register when set to 1b

7.8.4.3 CURRENT_PI Register (Address = F0h) [Reset = 00000000h]

CURRENT_PI is shown in CURRENT_PI Register and described in CURRENT_PI Register Field Descriptions.

Return to the ALGORITHM_CONTROL Registers.

Current PI controller used

Figure 7-87. CURRENT_PI Register

31

15

30

29

28

12

27

26

25

24

23

22

21

20

4

19

18

17

1

16

0

CURRENT_LOOP_KP

R-0h

CURRENT_LOOP_KI

R-0h

14

13

11

10

9

8

7

6

5

3

2

CURRENT_LOOP_KI

R-0h

RESERVED

R-0h

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Table 7-61. CURRENT_PI Register Field Descriptions

Bit

Field

Type

Reset

Description

31-22

21-12

11-0

CURRENT_LOOP_KP

CURRENT_LOOP_KI

RESERVED

R

0h

10-bit value for current loop Kp; same scaling as CURR_LOOP_KP

10-bit value for current loop Ki; same scaling as CURR_LOOP_KI

Reserved

R

0h

R

0h

7.8.4.4 SPEED_PI Register (Address = F2h) [Reset = 00000000h]

SPEED_PI is shown in SPEED_PI Register and described in SPEED_PI Register Field Descriptions.

Return to the ALGORITHM_CONTROL Registers.

Speed PI controller used

Figure 7-88. SPEED_PI Register

31

15

30

29

28

12

27

26

25

24

23

22

21

20

4

19

18

17

1

16

0

SPEED_LOOP_KP

R-0h

SPEED_LOOP_KI

R-0h

14

13

11

10

9

8

7

6

5

3

2

SPEED_LOOP_KI

R-0h

RESERVED

R-0h

Table 7-62. SPEED_PI Register Field Descriptions

Bit

31-22

Field

Type

Reset

Description

SPEED_LOOP_KP

SPEED_LOOP_KI

RESERVED

R

0h

10-bit value for speed loo Kp; same scaling as SPD_LOOP_KP

10-bit value for speed loop Ki; same scaling as SPD_LOOP_KI

Reserved

21-12

11-0

R

0h

R

0h

7.8.5 Algorithm_Variables Registers

ALGORITHM_VARIABLES Registers lists the memory-mapped registers for the Algorithm_Variables registers.

All register offset addresses not listed in ALGORITHM_VARIABLES Registers should be considered as reserved

locations and the register contents should not be modified.

Table 7-63. ALGORITHM_VARIABLES Registers

Address Acronym

ALGORITHM_STATE

Register Name

Section

210h

216h

410h

43Eh

440h

442h

466h

476h

478h

47Eh

480h

482h

4BAh

4BCh

4D4h

Current Algorithm State Register

FG Speed Feedback Register

Calculated DC Bus Current Register

Measured Current on Phase A Register

Measured Current on Phase B Register

Measured Current on Phase C Register

CSA Gain Register

Section 7.8.5.1

Section 7.8.5.2

Section 7.8.5.3

Section 7.8.5.4

Section 7.8.5.5

Section 7.8.5.6

Section 7.8.5.7

Section 7.8.5.8

Section 7.8.5.9

Section 7.8.5.10

Section 7.8.5.11

Section 7.8.5.12

Section 7.8.5.13

Section 7.8.5.14

Section 7.8.5.15

FG_SPEED_FDBK

BUS_CURRENT

PHASE_CURRENT_A

PHASE_CURRENT_B

PHASE_CURRENT_C

CSA_GAIN_FEEDBACK

VOLTAGE_GAIN_FEEDBACK

VM_VOLTAGE

Voltage Gain Register

VM Voltage Register

PHASE_VOLTAGE_VA

PHASE_VOLTAGE_VB

PHASE_VOLTAGE_VC

SIN_COMMUTATION_ANGLE

COS_COMMUTATION_ANGLE

IALPHA

Phase Voltage Register

Sine of Commutation Angle

Cosine of Commutation Angle

IALPHA Current Register

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Table 7-63. ALGORITHM_VARIABLES Registers (continued)

Address Acronym

Register Name

Section

4D6h

4D8h

4DAh

4E4h

4E6h

4E8h

4EAh

524h

53Ah

548h

5CCh

5FCh

5FEh

67Ah

684h

6B8h

6FCh

742h

744h

752h

756h

IBETA

IBETA Current Register

Section 7.8.5.16

Section 7.8.5.17

Section 7.8.5.18

Section 7.8.5.19

Section 7.8.5.20

Section 7.8.5.21

Section 7.8.5.22

Section 7.8.5.23

Section 7.8.5.24

Section 7.8.5.25

Section 7.8.5.26

Section 7.8.5.27

Section 7.8.5.28

Section 7.8.5.29

Section 7.8.5.30

Section 7.8.5.31

Section 7.8.5.32

Section 7.8.5.33

Section 7.8.5.34

Section 7.8.5.35

Section 7.8.5.36

VALPHA

VALPHA Voltage Register

VBETA Voltage Register

Measured d-axis Current Register

Measured q-axis Current Register

VD Voltage Register

VBETA

ID

IQ

VD

VQ

VQ Voltage Register

IQ_REF_ROTOR_ALIGN

SPEED_REF_OPEN_LOOP

IQ_REF_OPEN_LOOP

SPEED_REF_CLOSED_LOOP

ID_REF_CLOSED_LOOP

IQ_REF_CLOSED_LOOP

ISD_STATE

Align Current Reference

Open Loop Speed Register

Open Loop Current Reference

Speed Reference Register

Reference for Current Loop Register

ISD State Register

ISD_SPEED

ISD Speed Register

IPD_STATE

IPD State Register

IPD_ANGLE

Calculated IPD Angle Register

Estimated BEMF EQ Register

Estimated BEMF ED Register

Speed Feedback Register

Estimated Motor Position Register

ED

EQ

SPEED_FDBK

THETA_EST

Complex bit access types are encoded to fit into small table cells. Algorithm_Variables Access Type Codes

shows the codes that are used for access types in this section.

Table 7-64. Algorithm_Variables Access Type Codes

Access Type

Read Type

R

Code

Description

R

Read

Reset or Default Value

-n

Value after reset or the default

value

7.8.5.1 ALGORITHM_STATE Register (Address = 210h) [Reset = 00000000h]

ALGORITHM_STATE is shown in ALGORITHM_STATE Register and described in ALGORITHM_STATE

Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

Current Algorithm State Register

Figure 7-89. ALGORITHM_STATE Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

RESERVED

R-0h

ALGORITHM_STATE

R-0h

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Table 7-65. ALGORITHM_STATE Register Field Descriptions

Bit

Field

Type

Reset

Description

31-16

15-0

RESERVED

ALGORITHM_STATE

R

0h

Reserved

R

0h

16-bit value indicating current state of device

0h = MOTOR_IDLE

1h = MOTOR_ISD

2h = MOTOR_TRISTATE

3h = MOTOR_BRAKE_ON_START

4h = MOTOR_IPD

5h = MOTOR_SLOW_FIRST_CYCLE

6h = MOTOR_ALIGN

7h = MOTOR_OPEN_LOOP

8h = MOTOR_CLOSED_LOOP_UNALIGNED

9h = MOTOR_CLOSED_LOOP_ALIGNED

Ah = MOTOR_CLOSED_LOOP_ACTIVE_BRAKING

Bh = MOTOR_SOFT_STOP

Ch = MOTOR_RECIRCULATE_STOP

Dh = MOTOR_BRAKE_ON_STOP

Eh = MOTOR_FAULT

Fh = MOTOR_MPET_MOTOR_STOP_CHECK

10h = MOTOR_MPET_MOTOR_STOP_WAIT

11h = MOTOR_MPET_MOTOR_BRAKE

12h = MOTOR_MPET_ALGORITHM_PARAMETERS_INIT

13h = MOTOR_MPET_RL_MEASURE

14h = MOTOR_MPET_KE_MEASURE

15h = MOTOR_MPET_STALL_CURRENT_MEASURE

16h = MOTOR_MPET_TORQUE_MODE

17h = MOTOR_MPET_DONE

18h = MOTOR_MPET_FAULT

7.8.5.2 FG_SPEED_FDBK Register (Address = 216h) [Reset = 00000000h]

FG_SPEED_FDBK is shown in FG_SPEED_FDBK Register and described in FG_SPEED_FDBK Register Field

Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

Speed Feedback from FG

Figure 7-90. FG_SPEED_FDBK Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

FG_SPEED_FDBK

R-0h

Table 7-66. FG_SPEED_FDBK Register Field Descriptions

Bit

Field

Type

Reset

Description

31-0

FG_SPEED_FDBK

R

0h

32-bit value indicating FG estimated rotor speed; FGEstimatedSpeed

(Hz) = (FG_SPEED_FDBK / 2²⁷) * MAX_SPEED

7.8.5.3 BUS_CURRENT Register (Address = 410h) [Reset = 00000000h]

BUS_CURRENT is shown in BUS_CURRENT Register and described in BUS_CURRENT Register Field

Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

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Calculated Supply Current Register

Figure 7-91. BUS_CURRENT Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

BUS_CURRENT

R-0h

Table 7-67. BUS_CURRENT Register Field Descriptions

Bit

Field

Type

Reset

Description

31-0

BUS_CURRENT

R

0h

32-bit value indicating DC bus current; I_dcBus (A) =

(BUS_CURRENT / 2²⁷) * 1.25

7.8.5.4 PHASE_CURRENT_A Register (Address = 43Eh) [Reset = 00000000h]

PHASE_CURRENT_A is shown in PHASE_CURRENT_A Register and described in PHASE_CURRENT_A

Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

Measured current on Phase A Register

Figure 7-92. PHASE_CURRENT_A Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

PHASE_CURRENT_A

R-0h

Table 7-68. PHASE_CURRENT_A Register Field Descriptions

Bit

Field

Type

Reset

Description

31-0

PHASE_CURRENT_A

R

0h

32-bit value indicating measured current on Phase A; Ia (A) =

(PHASE_CURRENT_A / 2²⁷) * 1.25

7.8.5.5 PHASE_CURRENT_B Register (Address = 440h) [Reset = 00000000h]

PHASE_CURRENT_B is shown in PHASE_CURRENT_B Register and described in PHASE_CURRENT_B

Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

Measured current on Phase B Register

Figure 7-93. PHASE_CURRENT_B Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

PHASE_CURRENT_B

R-0h

Table 7-69. PHASE_CURRENT_B Register Field Descriptions

Bit

Field

Type

Reset

Description

31-0

PHASE_CURRENT_B

R

0h

32-bit value indicating measured current on Phase B; Ib (A)=

(PHASE_CURRENT_B / 2²⁷) * 1.25

7.8.5.6 PHASE_CURRENT_C Register (Address = 442h) [Reset = 00000000h]

PHASE_CURRENT_C is shown in PHASE_CURRENT_C Register and described in PHASE_CURRENT_C

Register Field Descriptions.

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Return to the ALGORITHM_VARIABLES Registers.

Measured current on Phase C Register

Figure 7-94. PHASE_CURRENT_C Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

PHASE_CURRENT_C

R-0h

Table 7-70. PHASE_CURRENT_C Register Field Descriptions

Bit

Field

Type

Reset

Description

31-0

PHASE_CURRENT_C

R

0h

32-bit value indicating measured current on Phase C; Ic (A) =

(PHASE_CURRENT_C / 2²⁷) * 1.25

7.8.5.7 CSA_GAIN_FEEDBACK Register (Address = 466h) [Reset = 00000000h]

CSA_GAIN_FEEDBACK is shown in CSA_GAIN_FEEDBACK Register

and

described

in

CSA_GAIN_FEEDBACK Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

VM Voltage Register

Figure 7-95. CSA_GAIN_FEEDBACK Register

31

30

29

28

27

26

25

24

23

22

21

20

19

3

18

2

17

1

16

0

RESERVED

R-0h

15

14

13

12

11

10

9

8

7

6

5

4

CSA_GAIN_FEEDBACK

R-0h

Table 7-71. CSA_GAIN_FEEDBACK Register Field Descriptions

Bit

Field

Type

Reset

Description

31-16

15-0

RESERVED

R

0h

Reserved

CSA_GAIN_FEEDBACK

R

0h

16-bit value indicating current sense gain

0h = 1.2 V/A

1h = 0.6 V/A

2h = 0.3 V/A

3h = 0.15 V/A

7.8.5.8 VOLTAGE_GAIN_FEEDBACK Register (Address = 476h) [Reset = 00000000h]

VOLTAGE_GAIN_FEEDBACK is shown in VOLTAGE_GAIN_FEEDBACK Register and described in

VOLTAGE_GAIN_FEEDBACK Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

Voltage Gain Register

Figure 7-96. VOLTAGE_GAIN_FEEDBACK Register

31

30

29

28

27

26

25

24

23

22

21

20

19

3

18

2

17

1

16

0

RESERVED

R-0h

15

14

13

12

11

10

9

8

7

6

5

4

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Figure 7-96. VOLTAGE_GAIN_FEEDBACK Register (continued)

VOLTAGE_GAIN_FEEDBACK

R-0h

Table 7-72. VOLTAGE_GAIN_FEEDBACK Register Field Descriptions

Bit

Field

Type

Reset

Description

31-16

15-0

RESERVED

R

0h

Reserved

VOLTAGE_GAIN_FEEDB

ACK

R

0h

16-bit value indicating voltage gain

0h = 60V

1h = 30V

2h = 15V

7.8.5.9 VM_VOLTAGE Register (Address = 478h) [Reset = 00000000h]

VM_VOLTAGE is shown in VM_VOLTAGE Register and described in VM_VOLTAGE Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

Supply voltage register

Figure 7-97. VM_VOLTAGE Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

VM_VOLTAGE

R-0h

Table 7-73. VM_VOLTAGE Register Field Descriptions

Bit

Field

Type

Reset

Description

31-0

VM_VOLTAGE

R

0h

32-bit value indicating DC bus voltage; DC Bus Voltage (V) =

VM_VOLTAGE * 60 / 2²⁷

7.8.5.10 PHASE_VOLTAGE_VA Register (Address = 47Eh) [Reset = 00000000h]

PHASE_VOLTAGE_VA is shown in PHASE_VOLTAGE_VA Register and described in PHASE_VOLTAGE_VA

Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

Phase Voltage Register

Figure 7-98. PHASE_VOLTAGE_VA Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

PHASE_VOLTAGE_VA

R-0h

Table 7-74. PHASE_VOLTAGE_VA Register Field Descriptions

Bit

Field

Type

Reset

Description

32-bit value indicating phase voltage Va during ISD; Va (V) =

PHASE_VOLTAGE_VA * 60 / (sqrt(3) * 2²⁷

31-0

PHASE_VOLTAGE_VA

R

0h

)

7.8.5.11 PHASE_VOLTAGE_VB Register (Address = 480h) [Reset = 00000000h]

PHASE_VOLTAGE_VB is shown in PHASE_VOLTAGE_VB Register and described in PHASE_VOLTAGE_VB

Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

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Phase Voltage Register

Figure 7-99. PHASE_VOLTAGE_VB Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

PHASE_VOLTAGE_VB

R-0h

Table 7-75. PHASE_VOLTAGE_VB Register Field Descriptions

Bit

Field

Type

Reset

Description

32-bit value indicating phase voltage Vb during ISD; Vb (V) =

PHASE_VOLTAGE_VB * 60 / (sqrt(3) * 2²⁷

31-0

PHASE_VOLTAGE_VB

R

0h

)

7.8.5.12 PHASE_VOLTAGE_VC Register (Address = 482h) [Reset = 00000000h]

PHASE_VOLTAGE_VC is shown in PHASE_VOLTAGE_VC Register and described in PHASE_VOLTAGE_VC

Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

Phase Voltage Register

Figure 7-100. PHASE_VOLTAGE_VC Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

PHASE_VOLTAGE_VC

R-0h

Table 7-76. PHASE_VOLTAGE_VC Register Field Descriptions

Bit

Field

Type

Reset

Description

32-bit value indicating phase voltage Vc during ISD; Vc (V)=

PHASE_VOLTAGE_VC * 60 / (sqrt(3) * 2²⁷

31-0

PHASE_VOLTAGE_VC

R

0h

)

7.8.5.13 SIN_COMMUTATION_ANGLE Register (Address = 4BAh) [Reset = 00000000h]

SIN_COMMUTATION_ANGLE is shown in SIN_COMMUTATION_ANGLE Register and described in

SIN_COMMUTATION_ANGLE Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

Sine of Commutation Angle

Figure 7-101. SIN_COMMUTATION_ANGLE Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

SIN_COMMUTATION_ANGLE

R-0h

Table 7-77. SIN_COMMUTATION_ANGLE Register Field Descriptions

Bit

Field

Type

Reset

Description

32-bit value indicating sine of commutation angle;

sinCommutationAngle = (SIN_COMMUTATION_ANGLE / 2²⁷

31-0

SIN_COMMUTATION_AN

GLE

R

0h

)

7.8.5.14 COS_COMMUTATION_ANGLE Register (Address = 4BCh) [Reset = 00000000h]

COS_COMMUTATION_ANGLE is shown in COS_COMMUTATION_ANGLE Register and described in

COS_COMMUTATION_ANGLE Register Field Descriptions.

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Return to the ALGORITHM_VARIABLES Registers.

Cosine of Commutation Angle

Figure 7-102. COS_COMMUTATION_ANGLE Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

COS_COMMUTATION_ANGLE

R-0h

Table 7-78. COS_COMMUTATION_ANGLE Register Field Descriptions

Bit

Field

Type

Reset

Description

32-bit value indicating cosine of commutation angle;

cosCommutationAngle = (COS_COMMUTATION_ANGLE / 2²⁷

31-0

COS_COMMUTATION_A

NGLE

R

0h

)

7.8.5.15 IALPHA Register (Address = 4D4h) [Reset = 00000000h]

IALPHA is shown in IALPHA Register and described in IALPHA Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

IALPHA Current Register

Figure 7-103. IALPHA Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

IALPHA

R-0h

Table 7-79. IALPHA Register Field Descriptions

Bit

Field

Type

Reset

Description

31-0

IALPHA

R

0h

32-bit value indicating calculated I_alpha; I_alpha (A) = (IALPHA /

2²⁷) * 1.25

7.8.5.16 IBETA Register (Address = 4D6h) [Reset = 00000000h]

IBETA is shown in IBETA Register and described in IBETA Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

IBETA Current Register

Figure 7-104. IBETA Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

IBETA

R-0h

Table 7-80. IBETA Register Field Descriptions

Bit

Field

Type

Reset

Description

31-0

IBETA

R

0h

32-bit value indicating calculated I_beta; I_beta (A)= (IBETA / 2²⁷) *

1.25

7.8.5.17 VALPHA Register (Address = 4D8h) [Reset = 00000000h]

VALPHA is shown in VALPHA Register and described in VALPHA Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

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VALPHA Voltage Register

Figure 7-105. VALPHA Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

VALPHA

R-0h

Table 7-81. VALPHA Register Field Descriptions

Bit

Field

Type

Reset

Description

31-0

VALPHA

R

0h

32-bit value indicating calculated V_alpha; V_alpha (V) = (VALPHA /

2²⁷) * 60 / sqrt(3)

7.8.5.18 VBETA Register (Address = 4DAh) [Reset = 00000000h]

VBETA is shown in VBETA Register and described in VBETA Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

VBETA Voltage Register

Figure 7-106. VBETA Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

VBETA

R-0h

Table 7-82. VBETA Register Field Descriptions

Bit

Field

Type

Reset

Description

31-0

VBETA

R

0h

32-bit value indicating calculated V_beta; V_beta (V) = (VBETA / 2²⁷

* 60 / sqrt(3)

)

7.8.5.19 ID Register (Address = 4E4h) [Reset = 00000000h]

ID is shown in ID Register and described in ID Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

Measured d-axis Current Register

Figure 7-107. ID Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

ID

R-0h

Table 7-83. ID Register Field Descriptions

Bit

Field

Type

Reset

Description

32-bit value indicating estimated Id; Id (A) = (ID / 2²⁷) * 1.25

31-0

ID

R

0h

7.8.5.20 IQ Register (Address = 4E6h) [Reset = 00000000h]

IQ is shown in IQ Register and described in IQ Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

Measured q-axis Current Register

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Figure 7-108. IQ Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

IQ

R-0h

Table 7-84. IQ Register Field Descriptions

Bit

Field

Type

Reset

Description

32-bit value indicating estimated Iq; Iq (A) = (IQ / 2²⁷) * 1.25

31-0

IQ

R

0h

7.8.5.21 VD Register (Address = 4E8h) [Reset = 00000000h]

VD is shown in VD Register and described in VD Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

VD Voltage Register

Figure 7-109. VD Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

VD

R-0h

Table 7-85. VD Register Field Descriptions

Bit

Field

Type

Reset

Description

32-bit value indicating applied Vd; Vd (V) = (VD / 2²⁷) * 60 / sqrt(3)

31-0

VD

R

0h

7.8.5.22 VQ Register (Address = 4EAh) [Reset = 00000000h]

VQ is shown in VQ Register and described in VQ Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

VQ Voltage Register

Figure 7-110. VQ Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

VQ

R-0h

Table 7-86. VQ Register Field Descriptions

Bit

Field

Type

Reset

Description

32-bit value indicating applied Vq; Vq (V)= (VQ / 2²⁷) * 60 / sqrt(3)

31-0

VQ

R

0h

7.8.5.23 IQ_REF_ROTOR_ALIGN Register (Address = 524h) [Reset = 00000000h]

IQ_REF_ROTOR_ALIGN is shown in IQ_REF_ROTOR_ALIGN Register

and

described

in

IQ_REF_ROTOR_ALIGN Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

Align Current Reference

Figure 7-111. IQ_REF_ROTOR_ALIGN Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

IQ_REF_ROTOR_ALIGN

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Figure 7-111. IQ_REF_ROTOR_ALIGN Register (continued)

R-0h

Table 7-87. IQ_REF_ROTOR_ALIGN Register Field Descriptions

Bit

Field

Type

Reset

Description

31-0

IQ_REF_ROTOR_ALIGN

R

0h

32-bit value indicating Align Current Reference; IqRefRotorAlign (A)

= (IQ_REF_ROTOR_ALIGN / 2²⁷) * 1.25

7.8.5.24 SPEED_REF_OPEN_LOOP Register (Address = 53Ah) [Reset = 00000000h]

SPEED_REF_OPEN_LOOP is shown in SPEED_REF_OPEN_LOOP Register and described in

SPEED_REF_OPEN_LOOP Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

Speed at which motor transitions to close loop

Figure 7-112. SPEED_REF_OPEN_LOOP Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

SPEED_REF_OPEN_LOOP

R-0h

Table 7-88. SPEED_REF_OPEN_LOOP Register Field Descriptions

Bit

Field

Type

Reset

Description

31-0

SPEED_REF_OPEN_LO

OP

R

0h

32-bit value indicating open loop speed reference;

OpenLoopSpeedRef (Hz) = (SPEED_REF_OPEN_LOOP / 2²⁷) *

MAX_SPEED

7.8.5.25 IQ_REF_OPEN_LOOP Register (Address = 548h) [Reset = 00000000h]

IQ_REF_OPEN_LOOP is shown in IQ_REF_OPEN_LOOP Register and described in IQ_REF_OPEN_LOOP

Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

Open Loop Current Reference

Figure 7-113. IQ_REF_OPEN_LOOP Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

IQ_REF_OPEN_LOOP

R-0h

Table 7-89. IQ_REF_OPEN_LOOP Register Field Descriptions

Bit

Field

Type

Reset

Description

32-bit value indicating Open Loop Current Reference

IqRefOpenLoop (A) = (IQ_REF_OPEN_LOOP / 2²⁷) * 1.25

31-0

IQ_REF_OPEN_LOOP

R

0h

7.8.5.26 SPEED_REF_CLOSED_LOOP Register (Address = 5CCh) [Reset = 00000000h]

SPEED_REF_CLOSED_LOOP is shown in SPEED_REF_CLOSED_LOOP Register and described in

SPEED_REF_CLOSED_LOOP Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

Speed Reference Register

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Figure 7-114. SPEED_REF_CLOSED_LOOP Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

SPEED_REF_CLOSED_LOOP

R-0h

Table 7-90. SPEED_REF_CLOSED_LOOP Register Field Descriptions

Bit

Field

Type

Reset

Description

31-0

SPEED_REF_CLOSED_L R

OOP

0h

32-bit value indicating reference for speed loop; Speed reference

in closed loop (Hz) = (SPEED_REF_CLOSED_LOOP/ 2²⁷) *

MAX_SPEED

7.8.5.27 ID_REF_CLOSED_LOOP Register (Address = 5FCh) [Reset = 00000000h]

ID_REF_CLOSED_LOOP is shown in ID_REF_CLOSED_LOOP Register and described in

ID_REF_CLOSED_LOOP Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

Reference for Current Loop Register

Figure 7-115. ID_REF_CLOSED_LOOP Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

ID_REF_CLOSED_LOOP

R-0h

Table 7-91. ID_REF_CLOSED_LOOP Register Field Descriptions

Bit

Field

Type

Reset

Description

31-0

ID_REF_CLOSED_LOOP

R

0h

32-bit value indicating Id_ref for flux loop; IdRefClosedLoop (A) =

(ID_REF_CLOSED_LOOP / 2²⁷) * 1.25

7.8.5.28 IQ_REF_CLOSED_LOOP Register (Address = 5FEh) [Reset = 00000000h]

IQ_REF_CLOSED_LOOP is shown in IQ_REF_CLOSED_LOOP Register and described in

IQ_REF_CLOSED_LOOP Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

Reference for Current Loop Register

Figure 7-116. IQ_REF_CLOSED_LOOP Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

IQ_REF_CLOSED_LOOP

R-0h

Table 7-92. IQ_REF_CLOSED_LOOP Register Field Descriptions

Bit

Field

Type

Reset

Description

31-0

IQ_REF_CLOSED_LOOP

R

0h

32-bit value indicating Iq_ref for torque loop ; IqRefClosedLoop (A) =

(IQ_REF_CLOSED_LOOP / 2²⁷) *1.25

7.8.5.29 ISD_STATE Register (Address = 67Ah) [Reset = 00000000h]

ISD_STATE is shown in ISD_STATE Register and described in ISD_STATE Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

ISD state Register

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Figure 7-117. ISD_STATE Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

RESERVED

R-0h

ISD_STATE

R-0h

Table 7-93. ISD_STATE Register Field Descriptions

Bit

Field

Type

Reset

Description

31-16

15-0

RESERVED

ISD_STATE

R

0h

Reserved

R

0h

16-bit value indicating current ISD state

0h = ISD_INIT

1h = ISD_MOTOR_STOP_CHECK

2h = ISD_MOTOR_DIRECTION_CHECK

3h = ISD_COMPLETE

4h = ISD_FAULT

7.8.5.30 ISD_SPEED Register (Address = 684h) [Reset = 00000000h]

ISD_SPEED is shown in ISD_SPEED Register and described in ISD_SPEED Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

ISD Speed Register

Figure 7-118. ISD_SPEED Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

ISD_SPEED

R-0h

Table 7-94. ISD_SPEED Register Field Descriptions

Bit

Field

Type

Reset

Description

31-0

ISD_SPEED

R

0h

32-bit value indicating calculated speed during ISD state; ISD_Speed

(Hz) = (ISD_SPEED / 2²⁷) * MAX_SPEED

7.8.5.31 IPD_STATE Register (Address = 6B8h) [Reset = 00000000h]

IPD_STATE is shown in IPD_STATE Register and described in IPD_STATE Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

IPD state Register

Figure 7-119. IPD_STATE Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

RESERVED

R-0h

IPD_STATE

R-0h

Table 7-95. IPD_STATE Register Field Descriptions

Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

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Table 7-95. IPD_STATE Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

15-0

IPD_STATE

R

0h

16-bit value indicating current IPD state

0h = IPD_INIT

1h = IPD_VECTOR_CONFIG

2h = IPD_RUN

3h = IPD_SLOW_RISE_CLOCK

4h = IPD_SLOW_FALL_CLOCK

5h = IPD_WAIT_CURRENT_DECAY

6h = IPD_GET_TIMES

7h = IPD_SET_NEXT_VECTOR

8h = IPD_CALC_SECTOR_RISE

9h = IPD_CALC_ROTOR_POSITION

Ah = IPD_CALC_ANGLE

Bh = IPD_COMPLETE

Ch = IPD_FAULT

7.8.5.32 IPD_ANGLE Register (Address = 6FCh) [Reset = 00000000h]

IPD_ANGLE is shown in IPD_ANGLE Register and described in IPD_ANGLE Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

Calculated IPD Angle Register

Figure 7-120. IPD_ANGLE Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

IPD_ANGLE

R-0h

Table 7-96. IPD_ANGLE Register Field Descriptions

Bit

Field

Type

Reset

Description

31-0

IPD_ANGLE

R

0h

32-bit value indicating measured IPD angle; IPD_Angle (°) =

(IPD_ANGLE / 2²⁷) * 360°

7.8.5.33 ED Register (Address = 742h) [Reset = 00000000h]

ED is shown in ED Register and described in ED Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

Estimated BEMF EQ Register

Figure 7-121. ED Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

ED

R-0h

Table 7-97. ED Register Field Descriptions

Bit

Field

Type

Reset

Description

32-bit value indicating estimated Ed; Ed (V) = (ED / 2²⁷) * 60 / sqrt(3)

31-0

ED

R

0h

7.8.5.34 EQ Register (Address = 744h) [Reset = 00000000h]

EQ is shown in EQ Register and described in EQ Register Field Descriptions.

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Return to the ALGORITHM_VARIABLES Registers.

Estimated BEMF ED Register

Figure 7-122. EQ Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

EQ

R-0h

Table 7-98. EQ Register Field Descriptions

Bit

Field

Type

Reset

Description

32-bit value indicating estimated Eq; Eq (V) = (EQ / 2²⁷) * 60 / sqrt(3)

31-0

EQ

R

0h

7.8.5.35 SPEED_FDBK Register (Address = 752h) [Reset = 00000000h]

SPEED_FDBK is shown in SPEED_FDBK Register and described in SPEED_FDBK Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

Speed Feedback Register

Figure 7-123. SPEED_FDBK Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

SPEED_FDBK

R-0h

Table 7-99. SPEED_FDBK Register Field Descriptions

Bit

Field

Type

Reset

Description

31-0

SPEED_FDBK

R

0h

32-bit value indicating estimated rotor speed; EstimatedSpeed (Hz) =

(SPEED_FDBK / 2²⁷)* MAX_SPEED

7.8.5.36 THETA_EST Register (Address = 756h) [Reset = 00000000h]

THETA_EST is shown in THETA_EST Register and described in THETA_EST Register Field Descriptions.

Return to the ALGORITHM_VARIABLES Registers.

Estimated motor position Register

Figure 7-124. THETA_EST Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

THETA_EST

R-0h

Table 7-100. THETA_EST Register Field Descriptions

Bit

Field

Type

Reset

Description

31-0

THETA_EST

R

0h

32-bit value indicating estimated rotor angle; EstimatedAngle (°) =

(THETA_EST / 2²⁷) * 360°

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8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and

TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

8.1 Application Information

The MCF8316A device is used in sensorless 3-phase BLDC motor control. The driver provides a high

performance, high-reliability, flexible solution for appliances, fans, pumps, residential and living fans, seat cooling

fans, automotive fans and blowers. The following section shows a common application of the MCF8316A device.

8.2 Typical Applications

Figure 8-1 shows the typical schematic of MCF8316A

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V_VM

+

47 nF

CPL

1 µF

VM

0.1 µF

>10 µF

CPH

CP

AVDD

AGND

SPEED/WAKE (PWM/Analog/Freq)

C_AVDD

1 µF

DRVOFF

BRAKE

DIR

DVDD

AGND

C_DVDD

Optional

Control

Interface

EXT_CLK

EXT_WD

Replace resistor (R_BK) with

inductor (L_BK) for larger

external load or to reduce

power dissipaꢀon

L_BK

SOX

SW_BK

External

Load

R_BK

C_BK

MCF8316A

GND_BK

FB_BK

OUTA

AVDD or EXT SUPPLY

R_FG

R_nFAULT

FG

nFAULT

OUTB

AVDD or EXT SUPPLY

R_SDA

R_SCL

OUTC

PGND

Optional

Serial

Interface

SDA

I²C

SCL

Figure 8-1. Primary Application Schematic

Table 8-1 lists the recommended values of the external components for MCF8316A.

Table 8-1. MCF8316A External Components

COMPONENTS

PIN 1

PIN 2

RECOMMENDED

X5R or X7R, 0.1-µF, TI recommends a capacitor

voltage rating at least twice the normal operating

voltage of the device

C_VM1

VM

PGND

≥ 10-µF, TI recommends a capacitor voltage rating at

least twice the normal operating voltage of the device

C_VM2

C_CP

VM

CP

PGND

VM

X5R or X7R, 16-V, 1-µF capacitor

X5R or X7R, 47-nF, TI recommends a capacitor

voltage rating at least twice the normal operating

voltage of the pin

C_FLY

CPH

CPL

X5R or X7R, 1-µF, ≥ 6.3-V. In order for AVDD to

accurately regulate output voltage, capacitor should

have effective capacitance between 0.7-µF to 1.3-µF

at 3.3-V across operating temperature.

C_AVDD

AVDD

AGND

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Table 8-1. MCF8316A External Components (continued)

COMPONENTS

PIN 1

PIN 2

RECOMMENDED

X5R or X7R, 1-µF, ≥ 4-V. In order for DVDD to

accurately regulate output voltage, capacitor should

have effective capacitance between 0.6-µF to 1.3-µF

at 1.5-V across operating temperature.

C_DVDD

AVDD

AGND

C_BK

L_BK

SW_BK

GND_BK

FB_BK

FG

X5R or X7R, buck-output rated capacitor

Buck-output inductor

SW_BK

R_FG

1.8 to 5-V Supply

1.8 to 3.3-V Supply

5.1-kΩ, Pull-up resistor

R_nFAULT

R_SDA

R_SCL

nFAULT

SDA

5.1-kΩ, Pull-up resistor

SCL

5.1-kΩ, Pull-up resistor

Recommended application range for MCF8316A is shown in Table 8-2.

Table 8-2. Recommended Application Range

Parameter

Min

4.5

0.6

0.006

-

Max

Unit

V

Motor voltage

35

Back-EMF constant (see Motor Back-EMF constant)

Motor resistance (see Motor Resistance)

Motor inductance (see Motor Inductance)

Motor electrical speed

2000

20

mV/Hz

Ω

20

mH

Hz

1500

8

Peak motor phase current

-

A

Default EEPROM configuration for MCF8316A is listed in Table 8-3. Default values are chosen for reliable motor

startup and closed loop operation. Refer to MCF8316A tuning guide which provides step by step procedure to

tune a 3-phase BLDC motor in closed loop, conform to use-case and explore features in the device.

Table 8-3. Recommended Default Values

Address Name

Address

Recommended Value

ISD_CONFIG

0x00000080

0x00000082

0x00000084

0x00000086

0x00000088

0x0000008A

0x0000008C

0x0000008E

0x00000094

0x00000096

0x00000098

0x0000009A

0x0000009C

0x0000009E

0x00000090

0x00000092

0x000000A4

0x000000A6

0x000000A8

0x000000AA

0x000000AC

0x64738C20

0x28200000

0x0B6807D0

0x2306600C

0x0D3201B5

0x1BAD0000

0x00000000

0x000D0000

0x00000000

0x3EC80106

0x70D00888

0x00000000

0x00101462

0x4000F00F

0x41C01F00

0x1C450100

REV_DRIVE_CONFIG

MOTOR_STARTUP1

MOTOR_STARTUP2

CLOSED_LOOP1

CLOSED_LOOP2

CLOSED_LOOP3

CLOSED_LOOP4

SPEED_PROFILES1

SPEED_PROFILES2

SPEED_PROFILES3

SPEED_PROFILES4

SPEED_PROFILES5

SPEED_PROFILES6

FAULT_CONFIG1

FAULT_CONFIG2

PIN_CONFIG

DEVICE_CONFIG1

DEVICE_CONFIG2

PERI_CONFIG1

GD_CONFIG1

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Table 8-3. Recommended Default Values (continued)

Address Name

GD_CONFIG2

INT_ALGO_1

INT_ALGO_2

Address

Recommended Value

0x000000AE

0x000000A0

0x000000A2

0x00200000

0x2433407D

0x000001A7

Once the device EEPROM is programmed with the desired configuration, device can be operated stand-alone

and I²C serial interface is not required anymore. Speed can be commanded using SPEED pin.

Below are the two essential parameters that are required to spin the motor in closed loop.

1. Maximum motor speed.

2. Current limit for torque PI loop.

8.2.1 Application Curves

8.2.1.1 Motor startup

Figure 8-2 shows the FG waveform and the phase current waveform at different motor operations.

Figure 8-2. Motor Startup - FG and Phase current

8.2.1.2 MPET

Figure 8-3 shows the phase current waveform during motor parameter measurement. Figure 8-4 shows the IPD

current waveform during R, L and Ke measurement. Bottom half of Figure 8-4 shows the IPD current waveform

during R and L measurement. R is measured during the rising of phase current and L is measured during the

falling of phase current. After R and L measurement, motor spins in open loop. Once the speed reaches MPET

open loop speed reference [MPET_OPEN_LOOP_SPEED_REF], motor is coasted. BEMF voltage of all three

phases are measured and Ke is calculated.

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Figure 8-3. MPET - Phase current

Figure 8-4. IPD current waveform during Rand L

measurement

8.2.1.3 Dead time compensation

Figure 8-5 shows the phase current waveform when dead time compensation is disabled. Fundamental

frequency of phase current is 40 Hz. Fast Fourier transform (FFT) of phase current plot shows harmonics at

160 Hz and 220 Hz. Figure 8-6 shows the phase current waveform when dead time compensation is enabled.

Phase current looks more sinusoidal and the FFT of phase current plot does not have any harmonics.

Figure 8-5. Phase current and FFT - Dead time

compensation disabled

Figure 8-6. Phase current and FFT - Dead time

compensation enabled

8.2.1.4 Auto handoff

Figure 8-7 shows the auto handoff feature in MCF8316A where the motor transitions seamlessly from open loop

to closed loop.

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Figure 8-7. Auto-handoff

8.2.1.5 Motor stop – recirculation mode

Figure 8-8 shows the supply voltage and phase current waveform after stopping the motor. Recirculation mode

in MCF8316A prevents the supply voltage from overshoots.

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Figure 8-8. Motor stop - recirculation mode

8.2.1.6 Anti voltage surge (AVS)

When motor speed decelerates at a very high deceleration rate, mechanical energy from the motor returns to

the power supply which could result in pumping up the supply voltage, VM. Figure 8-9 shows overshoot in

power supply voltage when AVS is disabled. Motor decelerates from 100% duty cycle to 10% duty cycle at

a deceleration rate of 70,000 Hz/sec. Figure 8-10 shows no overshoot in power supply voltage when AVS is

enabled.

Figure 8-9. Power supply voltage and phase

current waveform when AVS is disabled

Figure 8-10. Power supply voltage and phase

current waveform when AVS is enabled

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9 Power Supply Recommendations

9.1 Bulk Capacitance

Having an appropriate local bulk capacitance is an important factor in motor drive system design. It is generally

beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.

The amount of local capacitance needed depends on a variety of factors, including:

•

The highest current required by the motor system

The capacitance and current capability of the power supply

The amount of parasitic inductance between the power supply and motor system

The acceptable voltage ripple

The type of motor used (brushed DC, brushless DC, stepper)

The motor braking method

The inductance between the power supply and the motor drive system limits the rate at which current can

change from the power supply. If the local bulk capacitance is too small, the system responds to excessive

current demands or dumps from the motor with a change in VM voltage. When adequate bulk capacitance is

used, the VM voltage remains stable and high current can be quickly supplied.

The data sheet generally provides a recommended value, but system-level testing is required to determine the

appropriate bulk capacitor.

Parasitic Wire

Inductance

Motor Drive System

Power Supply

VM

+

Motor Driver

œ

GND

Local

Bulk Capacitor

IC Bypass

Capacitor

Figure 9-1. Example Setup of Motor Drive System With External Power Supply

The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases

when the motor transfers energy to the supply.

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10 Layout

10.1 Layout Guidelines

The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver

device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used

when connecting PCB layers. These practices minimize parasitic inductance and allow the bulk capacitor to

deliver high current.

Small-value capacitors should be ceramic, and placed closely to device pins.

The high-current device outputs should use wide metal traces.

To reduce noise coupling and EMI interference from large transient currents into small-current signal paths,

grounding should be partitioned between PGND and AGND. TI recommends connecting all non-power stage

circuitry (including the thermal pad) to AGND to reduce parasitic effects and improve power dissipation from the

device. Optionally, GND_BK can be split. Ensure grounds are connected through net-ties or wide resistors to

reduce voltage offsets and maintain gate driver performance.

The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to

connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias helps dissipate

the I²× R_DS(on)heat that is generated in the device.

To improve thermal performance, maximize the ground area that is connected to the thermal pad ground across

all possible layers of the PCB. Using thick copper pours can lower the junction-to-air thermal resistance and

improve thermal dissipation from the die surface.

Separate the SW_BK and FB_BK traces with ground separation to reduce buck switching from coupling as noise

into the buck outer feedback loop. Widen the FB_BK trace as much as possible to allow for faster load switching.

Figure 10-1 shows a layout example for the MCF8316A. Also, for layout example, refer to MCF8316A EVM.

166 Submit Document Feedback

Product Folder Links: MCF8316A

MCF8316A

SLLSFI0A – AUGUST 2021 – REVISED DECEMBER 2021

www.ti.com

10.2 Layout Example

Figure 10-1. Recommended Layout Example

Submit Document Feedback 167

Product Folder Links: MCF8316A

MCF8316A

SLLSFI0A – AUGUST 2021 – REVISED DECEMBER 2021

www.ti.com

10.3 Thermal Considerations

The MCF8316A has thermal shutdown (TSD) as previously described. A die temperature in excess of 150°C

(minimally) disables the device until the temperature drops to a safe level.

Any tendency of the device to enter thermal shutdown is an indication of excessive power dissipation, insufficient

heatsinking, or too high an ambient temperature.

10.3.1 Power Dissipation

The power dissipated in the output FET resistance (R_DS(on)) dominates power dissipation in MCF8316A.

At start-up and fault conditions, the FET current is much higher than normal operating FET current; remember to

take these peak currents and their duration into consideration.

The total device power dissipation is the power dissipated in each of the three half-bridges added together along

with standby power, LDO and buck regulator losses.

The maximum amount of power that the device can dissipate depends on ambient temperature and heatsinking.

Note that R_DS(on)increases with temperature, so as the device heats, the power dissipation increases. Take this

into consideration when sizing the heatsink.

A summary of equations for calculating each loss is shown below in Table 10-1.

Table 10-1. Power Losses for MCF8316A

Loss type

MCF8316A

P_standby= VM x I_{VM_TA}

Standby power

LDO

P_LDO= (VM-V_AVDD) x I_AVDD, if BUCK_PS_DIS = 1b

P_LDO= (V_BK-V_AVDD) x I_AVDD, if BUCK_PS_DIS = 0b

P_CON= 3 x (I_RMS(FOC))²x R_ds,on(TA)

P_SW= 3 x I_PK(FOC)x V_PK(FOC)x t_rise/fallx f_PWM

P_diode= 3 x I_PK(FOC)x V_diodex t_deadx f_PWM

P_BK= 0.11 x V_BKx I_BK(η_BK= 90%)

FET conduction

FET switching

Diode

Buck

168 Submit Document Feedback

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SLLSFI0A – AUGUST 2021 – REVISED DECEMBER 2021

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11 Device and Documentation Support

11.1 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.2 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

11.3 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.4 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most-

current data available for the designated device. This data is subject to change without notice and without

revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.

Submit Document Feedback 169

Product Folder Links: MCF8316A

PACKAGE MATERIALS INFORMATION

www.ti.com

2-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

MCF8316A1VRGFR

VQFN

RGF

40

3000

330.0

16.4

5.25

7.25

1.45

8.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

2-Jan-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VQFN RGF 40

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 35.0

MCF8316A1VRGFR

3000

Pack Materials-Page 2

PACKAGE OUTLINE

VQFN - 1 mm max height

PLASTIC QUAD FLAT PACK- NO LEAD

A

RGF0040E

5.1

4.9

B

PIN 1 INDEX AREA

7.1

6.9

1 MAX

C

SEATING PLANE

0.08 C

3.8

3.6

3.5

0.05

0.00

(0.1) TYP

20

13

36X 0.5

21

12

SYMM

41

5.8

5.6

5.5

1

32

0.3

40X

PIN 1 ID

(OPTIONAL)

0.2

33

40

SYMM

0.1

C A B

C

0.5

0.3

40X

0.05

4224999/B 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RGF0040E

PLASTIC QUAD FLAT PACK- NO LEAD

(4.8)

(3.7)

(3.5)

40

33

40X (0.6)

40X (0.25)

1

32

(Ø0.2) TYP

VIA

SYMM

41

(5.7) (5.5)

(6.8)

(1.35)

(1.25)

21

12

13

20

(R0.05) TYP

36x (0.5)

(0.625)

(0.975)

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 12X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED METAL

METAL UNDER

SOLDER MASK

NON- SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4224999/B 06/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RGF0040E

PLASTIC QUAD FLAT PACK- NO LEAD

(4.8)

(3.5)

36X (0.5)

40

33

40X (0.6)

40X (0.25)

41

1

32

12X

(1.15)

SYMM

(5.5)

(6.8)

(0.675)

(1.35)

12

21

(R0.05) TYP

13

20

(1.25)

12X (1.05)

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

69% PRINTED COVERAGE BY AREA

SCALE: 12X

4224999/B 06/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	MCF8316A_V01
厂家：	TEXAS INSTRUMENTS
描述：	MCF8316A Sensorless Field Oriented Control (FOC) Integrated FET BLDC Driver
文件：	总178页 (文件大小：6928K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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