MCP6292 [TI]
双路、5.5V、10MHz、低噪声 (8.7nV/√Hz)、RRIO 运算放大器;
| 型号： | MCP6292 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路、5.5V、10MHz、低噪声 (8.7nV/√Hz)、RRIO 运算放大器 放大器 运算放大器 |
| 文件： | 总46页 (文件大小：2528K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MCP6291, MCP6292, MCP6294
ZHCSGF0D –JULY 2017–REVISED OCTOBER 2019
MCP629x 10MHz 轨至轨运算放大器
1 特性
3 说明
1
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增益带宽积产品：典型值 10MHz
MCP6291（单通道）、MCP6292（双通道）和
MCP6294（四通道）器件组成了一个通用低功耗运算
放大器系列。具有轨至轨 输入和输出摆幅、低静态电
流（每通道的典型值为 600μA）、10MHz 的较宽带宽
和低噪声（10kHz 时为 8.7nV/√Hz）等特性，因此对
于需要在成本与性能间实现良好平衡的各类 应用需
求， 本系列器件非常有吸引力。其低输入偏置电流使
该系列器件适合用于带有高源阻抗的 应用 。
工作电源电压范围：2.4V 至 5.5V
轨至轨输入/输出
低输入偏置电流：1pA
低静态电流：0.6mA
输入电压噪声：8.7nV/√Hz（f = 10kHz 时）
内部射频和 EMI 滤波器
工作温度范围：–40°C 至 125°C
单位增益稳定
MCP629x 采用稳健耐用的设计，方便电路设计人员使
用。该器件具有单位增益稳定的集成 RFI 和 EMI 抑制
滤波器，在过驱条件下不会出现反相并且具有高静电放
电 (ESD) 保护（4kV 人体模型 (HBM)）。
由于具有电阻式开环输出阻抗，因此可在更高的容
性负载下更轻松地实现稳定
2 应用
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电源模块
MCP629x 系列的工作温度范围为 –40°C 至 125°C。
该系列器件的电源电压范围为 2.4V 至 5.5V。
烟雾探测器
HVAC：暖通空调
电池供电 应用
传感器信号调节
光电二极管放大器
模拟滤波器
器件信息(1)
器件型号
MCP6291
封装
SOT-23 (5)
SC70 (5)
封装尺寸（标称值）
1.60mm × 2.90mm
1.25mm × 2.00mm
3.91mm × 4.90mm
3.00mm × 3.00mm
1.60mm × 2.90mm
8.65mm × 3.91mm
4.40mm × 5.00mm
SOIC (8)
医疗仪器
MCP6292
MCP6294
VSSOP (8)
SOT-23 (8)
SOIC (14)
TSSOP (14)
笔记本电脑和 PDA
条形码扫描仪
音频接收器
汽车信息娱乐系统
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
小信号过冲与负载电容间的关系
低侧电机控制
60
VBUS
50
40
30
20
ILOAD
ZLOAD
5 V
+
MCP629x
VOUT
RSHUNT
VSHUNT
0.1 ꢀ
RF
165 kꢀ
10
0
Overshoot+
Overshoot-
RG
0
50
100
150
200
250
300
3.4 kꢀ
Capacitive Load (pF)
C025
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS879
MCP6291, MCP6292, MCP6294
ZHCSGF0D –JULY 2017–REVISED OCTOBER 2019
www.ti.com.cn
目录
8.3 Feature Description................................................. 19
8.4 Device Functional Modes........................................ 19
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application .................................................. 20
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 4
Pin Configuration and Functions......................... 5
Specifications......................................................... 8
7.1 Absolute Maximum Ratings ...................................... 8
7.2 ESD Ratings.............................................................. 8
7.3 Recommended Operating Conditions....................... 8
7.4 Thermal Information: MCP6291................................ 8
7.5 Thermal Information: MCP6292................................ 9
7.6 Thermal Information: MCP6294................................ 9
9
10 Power Supply Recommendations ..................... 22
10.1 Input and ESD Protection ..................................... 22
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 23
12 器件和文档支持 ..................................................... 24
12.1 文档支持................................................................ 24
12.2 相关链接................................................................ 24
12.3 接收文档更新通知 ................................................. 24
12.4 社区资源................................................................ 24
12.5 商标....................................................................... 24
12.6 静电放电警告......................................................... 24
12.7 Glossary................................................................ 24
13 机械、封装和可订购信息....................................... 24
7.7 Electrical Characteristics: VS (Total Supply Voltage) =
(V+) – (V–) = 2.4 V to 5.5 V..................................... 10
7.8 Typical Characteristics............................................ 12
Detailed Description ............................................ 18
8.1 Overview ................................................................. 18
8.2 Functional Block Diagram ....................................... 18
8
4 修订历史记录
Changes from Revision C (January 2019) to Revision D
Page
•
已添加 向数据表添加了 SOT-23 (8) (DDF) 封装 .................................................................................................................... 1
Changes from Revision B (April 2018) to Revision C
Page
•
•
•
•
•
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已删除 从器件信息 表中删除了 SOT-23 封装预览符号........................................................................................................... 1
已添加 向器件信息 表添加了 SC70 封装 ................................................................................................................................ 1
Added DCK package information to Device Comparison Table ........................................................................................... 4
Deleted DBV package preview notation from Pin Configuration and Functions section........................................................ 5
Added DCK package drawing and pin functions to Pin Configuration and Functions section............................................... 5
Added DBV (SOT-23) and DCK (SC70) thermal information................................................................................................. 8
Changes from Revision A (October 2017) to Revision B
Page
•
Added DGK package to Thermal Information table .............................................................................................................. 9
Changes from Original (July 2017) to Revision A
Page
•
•
•
•
•
•
已删除 删除了器件信息 表中的 MCP6291 SC70、SOT-553 和 SOIC 封装........................................................................... 1
已删除 删除了器件信息 表中的 MCP6292 WSON 和 VSSOP (10) 封装................................................................................ 1
已更改 将器件信息 表中的 MCP6294 14 引脚 SOIC 封装从预览更改为生产数据.................................................................. 1
Deleted DCK, DRL, DSG, RTE and 8-pin D packages from Device Comparison table ....................................................... 4
Deleted DRL (SOT-533) package from MCP6291 pinout image and table in Pin Configuration and Functions section ..... 5
Deleted MCP6291 DCK (SC70) and D (SOIC) package pinout drawings and pin information from Pin Configuration
and Functions section............................................................................................................................................................. 5
•
Deleted MCP6292 DSG (WSON) and DGS (VSSOP) package pinout drawings and pin table information in Pin
Configuration and Functions section ..................................................................................................................................... 6
2
Copyright © 2017–2019, Texas Instruments Incorporated
MCP6291, MCP6292, MCP6294
www.ti.com.cn
ZHCSGF0D –JULY 2017–REVISED OCTOBER 2019
•
•
Deleted package preview note from MCP6294 pinout drawing in Pin Configuration and Functions section ....................... 7
Added MCP6294 Thermal Information table ......................................................................................................................... 9
Copyright © 2017–2019, Texas Instruments Incorporated
3
MCP6291, MCP6292, MCP6294
ZHCSGF0D –JULY 2017–REVISED OCTOBER 2019
www.ti.com.cn
5 Device Comparison Table
PACKAGE LEADS
NO. OF
DEVICE
CHANNELS
DBV
5
DCK
5
D
—
8
DGK
—
PW
—
DDF
—
MCP6291
MCP6292
MCP6294
1
2
4
—
—
8
—
8
—
—
14
—
14
—
4
Copyright © 2017–2019, Texas Instruments Incorporated
MCP6291, MCP6292, MCP6294
www.ti.com.cn
ZHCSGF0D –JULY 2017–REVISED OCTOBER 2019
6 Pin Configuration and Functions
MCP6291 DBV Package
5-Pin SOT-23
MCP6291 DCK Package
5-Pin SC70
Top View
Top View
OUT
V-
1
2
3
5
4
V+
IN+
Vœ
1
2
3
5
V+
+IN
-IN
INœ
4
OUT
Not to scale
Pin Functions: MCP6921
PIN
NO.
I/O
DESCRIPTION
NAME
SOT-23 (DBV)
SC70 (DCK)
–IN
+IN
OUT
V–
4
3
1
2
5
3
1
4
8
5
I
Inverting input
Noninverting input
Output
I
O
—
—
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
V+
Copyright © 2017–2019, Texas Instruments Incorporated
5
MCP6291, MCP6292, MCP6294
ZHCSGF0D –JULY 2017–REVISED OCTOBER 2019
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MCP6292 D, DGK, DDF Packages
8-Pin SOIC, VSSOP
Top View
OUT A
-IN A
+IN A
V-
1
2
3
4
8
7
6
5
V+
OUT B
-IN B
+IN B
Pin Functions: MCP6292
PIN
I/O
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
OUT A
OUT B
V–
NO.
2
I
I
Inverting input, channel A
3
Noninverting input, channel A
Inverting input, channel B
Noninverting input, channel B
Output, channel A
6
I
5
I
1
O
O
—
—
7
Output, channel B
4
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
V+
8
6
Copyright © 2017–2019, Texas Instruments Incorporated
MCP6291, MCP6292, MCP6294
www.ti.com.cn
ZHCSGF0D –JULY 2017–REVISED OCTOBER 2019
MCP6294 D, PW Packages
14-Pin SOIC, TSSOP
Top View
OUT A
-IN A
+IN A
V+
1
2
3
4
5
6
7
14 OUT D
A
D
13 -IN D
12 +IN D
11 V-
+IN B
-IN B
OUT B
10 +IN C
9
8
-IN C
B
C
OUT C
Pin Functions: MCP6294
PIN
I/O
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
–IN C
+IN C
–IN D
+IN D
OUT A
OUT B
OUT C
OUT D
V–
NO.
2
I
I
Inverting input, channel A
3
Noninverting input, channel A
Inverting input, channel B
Noninverting input, channel B
Inverting input, channel C
Noninverting input, channel C
Inverting input, channel D
Noninverting input, channel D
Output, channel A
6
I
5
I
9
I
10
13
12
1
I
I
I
O
O
O
O
—
—
7
Output, channel B
8
Output, channel C
14
11
4
Output, channel D
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
V+
Copyright © 2017–2019, Texas Instruments Incorporated
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MCP6291, MCP6292, MCP6294
ZHCSGF0D –JULY 2017–REVISED OCTOBER 2019
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)(1)
MIN
(V–) – 0.5
–10
MAX
UNIT
Supply voltage
6
(V+) + 0.5
(V+) – (V–) + 0.2
10
V
Common-mode
Voltage(2)
V
Signal input pins
Differential
Current(2)
mA
mA
°C
Output short-circuit(3)
Specified, TA
Continuous
–40
125
150
150
Junction, TJ
°C
Storage, Tstg
–65
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5 V beyond the supply
rails to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
over operating free-air temperature range (unless otherwise noted)
VALUE
±4000
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.4
MAX
UNIT
VS
Supply voltage
5.5
V
Specified temperature
–40
125
°C
7.4 Thermal Information: MCP6291
MCP6291
THERMAL METRIC(1)
DBV (SOT-23)
5 PINS
221.7
DCK (SC70)
5 PINS
263.3
75.5
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
144.7
49.7
51.0
Junction-to-top characterization parameter
Junction-to-board characterization parameter
26.1
1.0
ψJB
49.0
50.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8
Copyright © 2017–2019, Texas Instruments Incorporated
MCP6291, MCP6292, MCP6294
www.ti.com.cn
ZHCSGF0D –JULY 2017–REVISED OCTOBER 2019
7.5 Thermal Information: MCP6292
MCP6292
THERMAL METRIC(1)
D (SOIC)
8 PINS
157.6
104.6
99.7
DGK (VSSOP)
8 PINS
201.2
DDF (SOT-23)
8 PINS
184.4
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
85.7
112.8
122.9
99.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
55.6
21.2
18.7
ψJB
99.2
121.4
99.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Thermal Information: MCP6294
MCP6294
THERMAL METRIC(1)
D (SOIC)
14 PINS
106.9
64
PW (TSSOP)
14 PINS
135.8
64
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
63
79
Junction-to-top characterization parameter
Junction-to-board characterization parameter
25.9
15.7
ψJB
62.7
78.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2017–2019, Texas Instruments Incorporated
9
MCP6291, MCP6292, MCP6294
ZHCSGF0D –JULY 2017–REVISED OCTOBER 2019
www.ti.com.cn
7.7 Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 2.4 V to 5.5 V
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VS = 5 V
±0.3
±3
±5
VOS
Input offset voltage
mV
VS = 5 V, TA = –40°C to 125°C
VS = 5 V, TA = –40°C to 125°C
VS = 2.4 V – 5.5 V, VCM = (V–)
At DC
dVOS/dT Drift
PSRR Power-supply rejection ratio
Channel separation, DC
INPUT VOLTAGE RANGE
±1.1
±7
µV/°C
µV/V
dB
100
VCM
Common-mode voltage range
VS = 2.4 V to 5.5 V
(V–) – 0.1
80
(V+) + 0.1
V
VS = 5.5 V
(V–) – 0.1 V < VCM < (V+) – 1.4 V
TA = –40°C to 125°C
103
87
VS = 5.5 V
VCM = –0.1 V to 5.6 V
TA = –40°C to 125°C
57
CMRR
Common-mode rejection ratio
dB
VS = 2.4 V
(V–) – 0.1 V < VCM < (V+) – 1.4 V
TA = –40°C to 125°C
88
VS = 2.4 V
VCM = –0.1 V to 1.9 V
TA = –40°C to 125°C
81
INPUT BIAS CURRENT
IB
Input bias current
Input offset current
±1
pA
pA
IOS
±0.05
NOISE
En
Input voltage noise (peak-to-peak)
Input voltage noise density
Input current noise density
VS = 5 V, f = 0.1 Hz to 10 Hz
VS = 5 V, f = 10 kHz, RL = 10 kΩ
VS = 5 V, f = 1 kHz, RL = 10 kΩ
f = 1 kHz
4.77
8.7
16
µVPP
nV/√Hz
fA/√Hz
en
in
10
INPUT CAPACITANCE
CID
CIC
Differential
2
4
pF
pF
Common-mode
OPEN-LOOP GAIN
VS = 2.4 V
(V–) + 0.04 V < VO < (V+) – 0.04 V
RL = 10 kΩ
100
130
100
130
VS = 5.5 V
(V–) + 0.05 V < VO < (V+) – 0.05 V
RL = 10 kΩ
104
AOL
Open-loop voltage gain
dB
VS = 2.4 V
(V–) + 0.06 V < VO < (V+) – 0.06 V
RL = 2 kΩ
VS = 5.5 V
(V–) + 0.15 V < VO < (V+) – 0.15 V
RL = 2 kΩ
FREQUENCY RESPONSE
GBP
φm
Gain bandwidth product
VS = 5 V, G = 1
VS = 5 V, G = 1
VS = 5 V, G = 1
10
55
MHz
°
Phase margin
Slew rate
SR
6.5
V/µs
To 0.1%, VS = 5 V, 2-V step , G = 1
CL = 100 pF
0.5
1
tS
Settling time
µs
µs
To 0.01%, VS = 5 V, 2-V step , G = 1
CL = 100 pF
VS = 5 V
VIN × gain > VS
tOR
Overload recovery time
0.2
10
Copyright © 2017–2019, Texas Instruments Incorporated
MCP6291, MCP6292, MCP6294
www.ti.com.cn
ZHCSGF0D –JULY 2017–REVISED OCTOBER 2019
Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 2.4 V to 5.5 V (continued)
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
PARAMETER
THD + N Total harmonic distortion + noise(1)
OUTPUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VS = 5 V
VO = 1 VRMS
G = 1, f = 1 kHz
0.0008%
VS = 5.5 V, RL = 10 kΩ
VS = 5.5 V, RL = 2 kΩ
VS = 5 V
15
50
VO
Voltage output swing from supply rails
mV
ISC
ZO
Short-circuit current
±50
100
mA
Open-loop output impedance
VS = 5 V, f = 10 MHz
Ω
POWER SUPPLY
IQ Quiescent current per amplifier
VS = 5.5 V, IO = 0 mA
600
1300
µA
(1) Third-order filter; bandwidth = 80 kHz at –3 dB.
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MCP6291, MCP6292, MCP6294
ZHCSGF0D –JULY 2017–REVISED OCTOBER 2019
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7.8 Typical Characteristics
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
500
400
2500
2000
1500
1000
500
300
200
100
0
0
œ100
œ200
œ300
œ400
œ500
œ500
œ1000
œ1500
œ2000
œ2500
0
25
50
75
100
125
150
-4
-3
-2
-1
0
1
2
3
4
œ50
œ25
Temperature (°C)
Input Common Mode Voltage (V)
C003
C005
V+ = 2.75 V, V– = –2.75 V
图 1. Offset Voltage vs Temperature
图 2. Offset Voltage vs Common-Mode Voltage
120
210
1000
Gain
Phase
100
80
60
40
20
0
180
500
0
150
120
90
60
30
0
500
1000
-20
1.5
2.0
2.5
3.0
Supply Voltage (V)
VS = 2.4 V to 5.5 V
3.5
4.0
4.5
5.0
5.5
100
1k
10k
100k
Frequency (Hz)
1M
10M
C006
C004
CL = 10 pF
图 4. Open-Loop Gain and Phase vs Frequency
图 3. Offset Voltage vs Power Supply
40
30
250
200
150
100
50
IBN
IBP
IOS
20
10
0
-10
-20
-30
-40
0
G = +1
G = +10
G = -1
œ50
0
25
Temperature (°C)
图 6. Input Bias Current vs Temperature
50
75
100
125
œ50
œ25
1k
10k
100k
Frequency (Hz)
1M
10M
C007
C008
图 5. Closed-Loop Gain vs Frequency
12
版权 © 2017–2019, Texas Instruments Incorporated
MCP6291, MCP6292, MCP6294
www.ti.com.cn
ZHCSGF0D –JULY 2017–REVISED OCTOBER 2019
Typical Characteristics (接下页)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
3
2
120
100
80
60
40
20
0
PSRR-
PSRR+
CMRR
-40°C
-40°C
125°C
85°C
1
25°C
0
25°C
85°C
œ1
œ2
œ3
125°C
10
20
30
40
50
60
Output Current (mA)
1k
10k
100k
Frequency (Hz)
1M
10M
C009
V+ = 2.75 V, V– = –2.75 V
C011
图 8. CMRR and PSRR vs Frequency
图 7. Output Voltage Swing vs Output Current
(Referred to Input)
10
9
8
7
6
5
4
3
2
1
55
50
45
40
35
30
0
25
50
75
100
125
150
œ50
œ25
0
25
50
75
100
125
œ50
œ25
Temperature (°C)
Temperature (°C)
C016
C012
VS = 5.5 V
VCM = (V–) – 0.1 V to (V+) – 1.4 V
TA= –40°C to 125°C
VS = 5.5 V
VCM = (V–) – 0.1 V to (V+) + 0.1 V
RL= 10 kΩ
TA= –40°C to 125°C
RL= 10 kΩ
图 10. CMRR vs Temperature
图 9. CMRR vs Temperature
10
9
8
7
6
5
Time (1s/div)
0
25
50
75
100
125
œ50
œ25
Temperature (°C)
C013
C014
VS = 2.4 V to 5.5 V
图 11. PSRR vs Temperature
VS = 2.4 V to 5.5 V
图 12. 0.1-Hz to 10-Hz Input Voltage Noise
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Typical Characteristics (接下页)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
120
100
80
60
40
20
0
-90
-95
-100
-105
-110
-115
-120
10
100
1k
Frequency (Hz)
10k
100k
100
1k
Frequency (Hz)
10k
C015
C017
VS = 5.5 V
VCM = 2.5 V
G = 1
RL = 2 kΩ
VOUT = 0.5 VRMS
BW = 80 kHz
图 13. Input Voltage Noise Spectral Density vs Frequency
œ40
图 14. THD + N vs Frequency
œ40
œ60
œ60
œ80
œ80
œ100
œ100
œ120
œ120
0.001
0.01
0.1
1
0.001
0.01
0.1
1
Output Voltage Amplitude (VRMS
)
Output Voltage Amplitude (VRMS
)
C019
C018
VS = 5.5 V
G = –1
VCM = 2.5 V
RL = 2 kΩ
VS = 5.5 V
G = 1
VCM = 2.5 V
RL = 2 kΩ
BW = 80 kHz
f = 1 kHz
BW = 80 kHz
f = 1 kHz
图 16. THD + N vs Amplitude
图 15. THD + N vs Amplitude
800
700
600
500
400
300
200
100
0
600
580
560
540
520
500
1.5
0
25
50
75
100
125
œ50
œ25
2
2.5
3
3.5
4
4.5
5
5.5
Temperature (°C)
Supply Voltage (V)
C021
C020
图 17. Quiescent Current vs Supply Voltage
图 18. Quiescent Current vs Temperature
14
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ZHCSGF0D –JULY 2017–REVISED OCTOBER 2019
Typical Characteristics (接下页)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
200
60
50
160
40
120
30
80
20
40
10
0
Overshoot+
Overshoot-
0
10k
0
50
100
150
200
250
300
100k
Frequency (Hz)
1M
10M
Capacitive Load (pF)
C025
C024
V+ = 2.75 V
V– = –2.75 V
G = 1 V/V
RL = 10 kΩ
VOUT step = 100 mVp-p
图 20. Small-Signal Overshoot vs Load Capacitance
图 19. Open-Loop Output Impedance vs Frequency
60
50
40
30
20
10
0
Input
Output
Overshoot(+)
Overshoot(-)
Time (200 µs/div)
0
50
100
150
200
250
300
Capacitive Load (pF)
C026
C036
V+ = 2.75 V
V– = –2.75 V
G = –1 V/V
V+ = 2.75 V, V– = –2.75 V
RL = 10 kΩ
VOUT step = 100 mVp-p
图 21. Small-Signal Overshoot vs Load Capacitance
图 22. No Phase Reversal
Input
Output
INPUT
OUTPUT
Time (1 µs/div)
Time (0.1µs/div)
C028
C030
V+ = 2.75 V
V– = –2.75 V
G = –10 V/V
V+ = 2.75 V
V– = –2.75 V
G = 1 V/V
图 23. Overload Recovery
图 24. Small-Signal Step Response
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Typical Characteristics (接下页)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
80
60
40
20
Sinking
0
Sourcing
œ20
œ40
Input
œ60
Output
œ80
Time (1 µs/div)
0
25
50
75
100
125
œ50
œ25
Temperature (°C)
C031
C034
V+ = 2.75 V
G = 1 V/V
V– = –2.75 V
CL = 100 pF
图 25. Large-Signal Step Response
图 26. Short-Circuit Current vs Temperature
0
-20
140
120
100
80
-40
-60
60
-80
40
-100
-120
-140
20
0
10M
100M
Frequency (Hz)
1G
C041
100
1k
10k 100k
Frequency (Hz)
1M
10M
PRF = –10 dBm
C038
V+ = 2.75 V, V– = –2.75 V
图 28. Channel Separation vs Frequency
图 27. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR+) vs Frequency
200
160
120
80
90
75
60
45
30
15
0
40
0
0
10
20
30
40
50
60
70
80
90 100
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Capacitive Load (pF)
Output Voltage (V)
C037
C023
VS = 5.5 V
VS = 5.5 V
图 29. Phase Margin vs Capacitive Load
图 30. Open Loop Voltage Gain vs Output Voltage
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ZHCSGF0D –JULY 2017–REVISED OCTOBER 2019
Typical Characteristics (接下页)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
100
100
75
75
50
50
25
25
0
0
-25
-50
-75
-100
-125
-150
œ25
œ50
œ75
œ100
0
0.3
0.6
0.9
0
0.3
0.6
0.9
1.2
1.5
Settling time (µs)
Settling time (µs)
C032
C033
图 31. Large Signal Settling Time (Positive)
图 32. Large Signal Settling Time (Negative)
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8 Detailed Description
8.1 Overview
The MCP629x series is a family of low-power, rail-to-rail input and output op amps. These devices operate from
2.4 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications. The
input common-mode voltage range includes both rails and allows the MCP629x series to be used in any single-
supply application. Rail-to-rail input and output swing significantly increases dynamic range in low-supply
applications and are designed for driving sampling analog-to-digital converters (ADCs).
8.2 Functional Block Diagram
V+
Reference
Current
VIN+
VINÛ
VBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
VÛ
(Ground)
18
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ZHCSGF0D –JULY 2017–REVISED OCTOBER 2019
8.3 Feature Description
8.3.1 Rail-to-Rail Input
The input common-mode voltage range of the MCP629x family extends 100 mV beyond the supply rails for the
full supply voltage range of 2.4 V to 5.5 V. This performance is achieved with a complementary input stage: an
N-channel input differential pair in parallel with a P-channel differential pair, as the Functional Block Diagram
shows. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 100 mV
above the positive supply, whereas the P-channel pair is active for inputs from 100 mV below the negative
supply to approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in
which both pairs are on. This 200-mV transition region can vary up to 200 mV with process variation. Thus, the
transition region (with both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, and up to
(V+) – 1 V to (V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift,
and THD can degrade compared to device operation outside this region.
8.3.2 Rail-to-Rail Output
Designed as a low-power, low-voltage operational amplifier, the MCP629x series delivers a robust output drive
capability. A class AB output stage with common-source transistors achieves full rail-to-rail output swing
capability. For resistive loads of 10 kΩ, the output swings to within 15 mV of either supply rail, regardless of the
applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the
rails.
8.3.3 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device
enters the saturation region, the charge carriers in the output devices require time to return to the linear state.
After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore,
the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew
time. The overload recovery time for the MCP629x series is approximately 200 ns.
8.4 Device Functional Modes
The MCP629x family has a single functional mode. These devices are powered on as long as the power-supply
voltage is between 2.4 V (±1.2 V) and 5.5 V (±2.75 V).
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The MCP629x series features 10-MHz bandwidth and 6.5-V/µs slew rate with only 600µA of supply current per
channel, providing good AC performance at low power consumption. DC applications are well served with a low
input noise voltage of 8.7 nV / √Hz at 10 kHz, low input bias current, and a typical input offset voltage of 0.3 mV.
9.2 Typical Application
图 33 shows the MCP629x configured in a low-side, motor-control application.
VBUS
ILOAD
ZLOAD
5 V
+
MCP629x
VOUT
RSHUNT
VSHUNT
0.1 ꢀ
RF
165 kꢀ
RG
3.4 kꢀ
图 33. MCP629x in a Low-Side, Motor-Control Application
9.2.1 Design Requirements
The design requirements for this design are:
•
•
•
Load current: 0 A to 1 A
Output voltage: 4.95 V
Maximum shunt voltage: 100 mV
20
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ZHCSGF0D –JULY 2017–REVISED OCTOBER 2019
Typical Application (接下页)
9.2.2 Detailed Design Procedure
The transfer function of the circuit in 图 33 is shown in 公式 1.
VOUT = ILOAD ìRSHUNT ìGain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from
0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using 公式 2.
VSHUNT _MAX
100mV
1A
RSHUNT
=
=
=100mW
ILOAD_MAX
(2)
Using 公式 2, RSHUNT is 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is amplified by the MCP629x to
produce an output voltage of roughly 0 V to 4.95 V. The gain needed by the MCP629x to produce the necessary
output voltage is calculated using 公式 3:
V
OUT _MAX - VOUT _MIN
(
)
Gain =
VIN_MAX - V
IN_MIN
(3)
Using 公式 3, the required gain is calculated to be 49.5 V/V, which is set with resistors RF and RG. 公式 4 is used
to size the resistors, RF and RG, to set the gain of the MCP629x to 49.5 V/V.
R
(
)
F
Gain = 1+
R
G
(4)
Choosing RF as 165 kΩ and RG as 3.4 kΩ provides a combination that equals roughly 49.5 V/V. 图 34 shows the
measured transfer function of the circuit shown in 图 33.
9.2.3 Application Curve
5
4
3
2
1
0
0
0.2
0.4
0.6
0.8
1
ILOAD (A)
C219
图 34. Low-Side, Current-Sense Transfer Function
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MCP6291, MCP6292, MCP6294
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10 Power Supply Recommendations
The MCP629x series is specified for operation from 2.4 V to 5.5 V (±1.2 V to ±2.75 V); many specifications apply
from –40°C to 125°C. The Typical Characteristics section presents parameters that can exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 6 V can permanently damage the device; see the Absolute
Maximum Ratings table.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Example section.
10.1 Input and ESD Protection
The MCP629x series incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to 10-
mA, as stated in the Absolute Maximum Ratings table. 图 35 shows how a series input resistor is added to the
driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and the
value must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA maximum
VOUT
Device
VIN
5 kW
图 35. Input Current Protection
22
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MCP6291, MCP6292, MCP6294
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ZHCSGF0D –JULY 2017–REVISED OCTOBER 2019
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp
itself. Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the
analog circuitry.
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise
pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the
ground current. For more detailed information, see Circuit Board Layout Techniques.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much
better as opposed to in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. As shown in 图 37, keeping RF and
RG close to the inverting input minimizes parasitic capacitance on the inverting input.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
•
•
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is
recommended to remove moisture introduced into the device packaging during the cleaning process. A
low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
11.2 Layout Example
VIN A
VIN B
+
+
VOUT A
VOUT B
RG
RG
RF
RF
图 36. Schematic Representation for 图 37
Place components
close to device and to
each other to reduce
parasitic errors.
OUT A
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
VS+
GND
OUT A
V+
RF
OUT B
GND
-IN A
+IN A
Vœ
OUT B
-IN B
RF
RG
GND
VIN A
RG
+IN B
VIN B
Keep input traces short
and run the input traces
as far away from
the supply lines
Use low-ESR,
GND
ceramic bypass
capacitor. Place as
close to the device
as possible.
VSœ
Ground (GND) plane on another layer
as possible.
图 37. Layout Example
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12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
《电路板布局技巧》(SLOA089)
12.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 1. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
MCP6291
MCP6292
MCP6294
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
24
版权 © 2017–2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
6-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MCP6291IDBVR
MCP6291IDCKR
MCP6292IDDFR
MCP6292IDGKR
ACTIVE
ACTIVE
SOT-23
SC70
DBV
DCK
DDF
DGK
5
5
8
8
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1U3F
1EL
Samples
Samples
Samples
Samples
SN
ACTIVE SOT-23-THIN
NIPDAU
M292
M292
ACTIVE
ACTIVE
VSSOP
VSSOP
NIPDAU | SN
| NIPDAUAG
MCP6292IDGKT
DGK
8
250
RoHS & Green
NIPDAU | SN
| NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
M292
Samples
MCP6292IDR
MCP6294IDR
MCP6294IPWR
MCP6294IPWT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
2500 RoHS & Green
2500 RoHS & Green
2000 RoHS & Green
NIPDAU | SN
NIPDAU
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
MC6292
Samples
Samples
Samples
Samples
14
14
14
MCP6294D
MCP6294
MCP6294
TSSOP
TSSOP
PW
PW
250
RoHS & Green
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Jun-2023
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MCP6291IDBVR
MCP6291IDBVR
MCP6291IDCKR
MCP6292IDDFR
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DDF
5
5
5
8
3000
3000
3000
3000
180.0
180.0
178.0
180.0
8.4
8.4
9.0
8.4
3.2
3.2
2.4
3.2
3.2
3.2
2.5
3.2
1.4
1.4
1.2
1.4
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
SOT-23-
THIN
MCP6292IDGKR
MCP6292IDGKR
MCP6292IDGKT
MCP6292IDGKT
MCP6292IDGKT
MCP6292IDR
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
DGK
D
8
8
2500
2500
250
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
16.4
12.4
12.4
5.3
5.3
5.3
5.3
5.3
6.4
6.5
6.9
6.9
3.4
3.4
3.4
3.4
3.4
5.2
9.0
5.6
5.6
1.4
1.4
1.4
1.4
1.4
2.1
2.1
1.6
1.6
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
16.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
8
8
250
8
250
8
2500
2500
2000
250
MCP6294IDR
SOIC
D
14
14
14
MCP6294IPWR
MCP6294IPWT
TSSOP
TSSOP
PW
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MCP6291IDBVR
MCP6291IDBVR
MCP6291IDCKR
MCP6292IDDFR
MCP6292IDGKR
MCP6292IDGKR
MCP6292IDGKT
MCP6292IDGKT
MCP6292IDGKT
MCP6292IDR
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DDF
DGK
DGK
DGK
DGK
DGK
D
5
5
3000
3000
3000
3000
2500
2500
250
210.0
210.0
190.0
210.0
366.0
366.0
356.0
366.0
366.0
356.0
356.0
366.0
366.0
185.0
185.0
190.0
185.0
364.0
364.0
356.0
364.0
364.0
356.0
356.0
364.0
364.0
35.0
35.0
30.0
35.0
50.0
50.0
35.0
50.0
50.0
35.0
35.0
50.0
50.0
5
SOT-23-THIN
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
8
8
8
8
8
250
8
250
8
2500
2500
2000
250
MCP6294IDR
SOIC
D
14
14
14
MCP6294IPWR
MCP6294IPWT
TSSOP
TSSOP
PW
PW
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.38
0.22
8X
0.1
C A B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/C 10/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/C 10/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/C 10/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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