MM74C374J [TI]
CMOS SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20, 0.300 INCH, CERAMIC, DIP-20;
| 型号： | MM74C374J |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CMOS SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20, 0.300 INCH, CERAMIC, DIP-20 驱动 CD 输出元件 逻辑集成电路 触发器 |
| 文件： | 总8页 (文件大小：380K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1988
MM54C373/MM74C373 TRI-STATE Octal D-Type Latch
É
MM54C374/MM74C374 TRI-STATE Octal D-Type Flip-Flop
General Description
The MM54C373/MM74C373, MM54C374/MM74C374 are
integrated, complementary MOS (CMOS), 8-bit storage ele-
ments with TRI-STATE outputs. These outputs have been
specially designed to drive high capacitive loads, such as
one might find when driving a bus, and to have a fan out of 1
when driving standard TTL. When a high logic level is ap-
plied to the OUTPUT DISABLE input, all outputs go to a high
impedance state, regardless of what signals are present at
the other inputs and the state of the storage elements.
Both the MM54C373/MM74C373 and the MM54C374/
MM74C374 are being assembled in 20-pin dual-in-line pack-
ages with 0.300 pin centers.
×
Features
Y
Wide supply voltage range
High noise immunity
Low power consumption
TTL compatibility
3V to 15V
0.45 V (typ.)
Y
Y
Y
CC
ut of 1
ddard L
The MM54C373/MM74C373 is an 8-bit latch. When LATCH
ENABLE is high, the Q outputs will follow the D inputs.
When LATCH ENABLE goes low, data at the D inputs,
which meets the set-up and hold time requirements, will be
retained at the outputs until LATCH ENABLE returns high
again.
Y
Y
Y
Y
Bus driving capability
TRI-STATE outputs
Eight storage elements in one pkage
Single CLOCK/LATCH ENABLE anOUTPUT
DISABLE control in
The MM54C374/MM74C374 is an 8-bit, D-type, positive-
edge triggered flip-flop. Data at the D inputs, meeting the
set-up and hold time requirements, is transferred to the Q
outputs on positive-going transitions of the CLOCK input.
Y
20-pin dual-in-linwith 0.300 centers takes
×
half board sp24-pin ackage
Connection Diagrams
MM54C373/MM74C373
Dual-In-Line Package
MM54C374/MM74C374
Dual-In-Line Package
TL/F/5906–1
TL/F/5906–2
Top View
Top View
Order Number MM54C373 or MM74C373
Order Number MM54C374 or MM74C374
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/5906
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Power Dissipation
Dual-In-Line
Small Outline
700 mW
500 mW
b
a
0.3V
Voltage at Any Pin
0.3V to V
CC
Operating V Range
CC
3V to 15V
18V
Operating Temperature Range (T )
A
Absolute Maximum V
CC
b
b
a
55 C to 125 C
MM54C373
MM74C373
§
40 C to 85 C
§
Lead Temperature (T )
L
(Soldering, 10 seconds)
a
§
§
260 C
§
b
a
65 C to 150 C
Storage Temperature Range (T )
S
§
§
DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
e
e
V
V
V
V
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
V
V
5V
3.5
8.0
V
V
IN(1)
CC
10V
CC
e
e
V
V
5V
V
V
IN(0)
CC
10V
CC
e
e
e b
5V, I
O
V
V
10 mA
e b
4.5
9.0
V
V
OUT(1)
OUT(0)
CC
10V, I
10 mA
CC
O
e
e
e
V
V
5V, I
10 mA
0.5
1.0
V
V
CC
O
e
10V, I
10 mA
CC
O
e
e
e
I
I
I
Logical ‘‘1’’ Input Current
Logical ‘‘0’’ Input Current
TRI-STATE Leakage Current
V
V
15V, V
15V
0V
.005
mA
mA
IN(1)
IN(0)
OZ
CC
CC
IN
IN
e
b
15V, V
1
0.05
e
e
e
e
V
V
15V, V
15V, V
15V
0V
0.05
1.0
mA
mA
CC
O
b
b
005
CC
O
e
I
Supply Current
V
CC
15V
0.05
300
mA
CC
CMOS/LPTTL INTERFACE
e
e
b
b
V
V
V
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Output Voltage
54C
74C
V
V
4.5V
1.5
1.5
V
V
IN(1)
CC
CC
4.75V
CC
CC
e
54C
54C
V
V
0.8
0.8
V
V
IN(0)
CC
4.75V
CC
e
e
b
b
54C
74C
V
V
4.5
60 mA
V
V
0.4
0.4
V
V
OUT(1)
CC
O
CC
e
4.75V, I
360 mA
CC
O
CC
e
b
1.6 mA
5
4.5
2.4
2.4
V
V
e b
4.75V, I
1.6 mA
e
1.6 mA
O
V
Logical ‘‘0’’ Output Voltage
74
.5V, I
O
0.4
0.4
V
V
OUT(0)
e
4.75V, I
1.6 mA
O
OUTPUT DRIVE (Short C
e
e
0V
I
I
I
I
Output So
5V, V
SOURCE
SOURCE
SINK
CC
OUT
b
b
b
12
24
48
mA
mA
mA
mA
e
25 C (Note 4)
§
A
e
e
0V
Output Sou
V
CC
10V, V
OUT
b
24
e
T
25 C (Note 4)
§
A
e
e
V
Output Sink Current
(N-Channel)
V
T
5V, V
OUT
CC
CC
6
12
e
25 C (Note 4)
§
A
e
e
V
Output Sink Current
(N-Channel)
V
CC
10V, V
OUT
SINK
CC
24
48
e
T
A
25 C (Note 4)
§
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
2
AC Electrical Characteristics*
e
e
e
e
t 20 ns, unless otherwise noted
f
MM54C373/MM74C373, T
25 C, C
§
50 pF, t
A
L
r
Symbol
Parameter
Conditions
Min
Typ
Max
Units
e
e
50 pF
t , t
pd0 pd1
Propagation Delay,
V
CC
V
CC
V
CC
V
CC
5V, C
165
70
330
140
390
170
ns
ns
ns
ns
L
e
e
e
e
50 pF
LATCH ENABLE to Output
10V, C
L
e
5V, C
150 pF
195
85
L
e
10V, C
150 pF
L
e
V
t , t
pd0 pd1
Propagation Delay Data
In to Output
LATCH ENABLE
CC
e
50 pF
e
e
e
e
V
CC
V
CC
V
CC
V
CC
5V, C
155
70
310
140
370
170
ns
ns
ns
ns
L
e
10V, C
50 pF
L
e
5V, C
150 pF
185
85
L
e
10V, C
150 pF
L
e
HOLD
t
f
t
Minimum Set-Up Time Data In
to CLOCK/LATCH ENABLE
t
0 ns
SET-UP
e
e
V
CC
V
CC
5V
70
35
140
70
ns
ns
10V
Maximum LATCH ENABLE
Frequency
MAX
e
e
V
V
5V
3.5
4.
6.7
9.0
MHz
MHz
CC
CC
10V
Minimum LATCH ENABLE
Pulse Width
V
V
5V
e
75
55
150
ns
ns
PWH
CC
10V
CC
e
e
t , t
r f
Maximum LATCH ENABLE
Rise and Fall Time
V
V
5V
NA
ms
ms
CC
10V
CC
e
e
e
t
t
t
, t
1H 0H
Propagation Delay OUTPUT
DISABLE to High Impedance
State (from a Logic Level)
R
10k, C
5 pF
L
L
e
e
V
V
5V
105
60
210
120
ns
ns
CC
CC
10V
e
, t
H1 H0
Propagation Delay OUTPUT
DISABLE to Logic Level
R
L
10k, C
50 pF
L
e
e
V
V
5V
105
45
210
90
ns
ns
CC
CC
(from High Impedance State)
e
e
e
e
, t
THL TLH
Transition Time
V
V
V
65
35
130
70
ns
ns
ns
ns
CC
CC
C
CC
5
F
110
70
220
140
10V, C
150 pF
L
C
C
Input Capacitance
Input Capacitance
put ote 2)
7.5
7.5
5
10
10
7.5
15
pF
pF
pF
pF
pF
LE
OUTPUT ISABLE
Iput ote 2)
OD
C
C
Input Capacita
Output Capacitanc
Any Other Input (Note 2)
IN
High Impedance
State (Note 2)
OUT
10
C
PD
Capacitce
Per Package (Note 3)
200
*AC Parameterted testing.
3
AC Electrical Characteristics* (Continued)
e
e
e
e
MM54C374/MM74C374, T
25 C, C
§
50 pF, t
t
f
20 ns, unless otherwise noted
A
L
r
Symbol
Parameter
Conditions
Min
Typ
Max
Units
e
e
e
e
e
50 pF
t , t
pd0 pd1
Propagation Delay,
CLOCK to Output
V
CC
V
CC
V
CC
V
CC
5V, C
L
150
65
300
130
360
160
ns
ns
ns
ns
e
10V, C
50 pF
L
e
5V, C
150 pF
180
80
L
e
10V, C
150 pF
L
e
HOLD
t
Minimum Set-Up Time Data In
to CLOCK/LATCH ENABLE
t
0 ns
SET-UP
e
e
V
CC
V
CC
5V
70
35
140
70
ns
ns
10V
e
e
t
f
t
, t
PWH PWL
Minimum CLOCK Pulse Width
Maximum CLOCK Frequency
V
V
5V
70
50
140
100
ns
ns
CC
10V
CC
e
e
V
V
5V
3.5
5
7.0
10
MHz
MHz
MAX
CC
10V
CC
e
e
e
e
, t
1H 0H
Propagation Delay OUTPUT
DISABLE to High Impedance
State (from a Logic Level)
R
10k, C
50 pF
L
L
e
e
V
CC
V
CC
5V
105
60
2
s
ns
10V
e
t , t
H1 H0
Propagation Delay OUTPUT
DISABLE to Logic Level
R
10k, C
50 pF
L
L
e
e
V
CC
V
CC
5V
10
45
210
90
n
ns
(from High Impedance State)
10V
e
e
e
e
t , t
THL TLH
Transition Time
V
CC
V
CC
V
CC
V
CC
5V, C
50 pF
30
70
ns
ns
ns
ns
L
e
10V, C
50 pF
L
e
5V, C
150 p
0
70
220
140
L
e
10V, C
150 p
L
l
e
e
t , t
r f
Maximum CLOCK Rise
and Fall Time
V
V
5V
15
2000
00
ms
ms
CC
l
10V
CC
C
C
Input Capacitance
Input Capacitance
CLOCK Input (Not
7.5
7.5
5
10
10
7.5
15
pF
pF
pF
pF
pF
CLK
OUTPUT DISAB
Input (Note 2)
OD
C
C
Input Capacitance
Output Capacitance
Any Other Input (N
IN
HigImpedance
Ste (Note
OUT
10
C
PD
Power Dissipation Capacitance
Per Package (Note )
250
*AC Parameters are guaranteed by DC correlattesting.
Note 2: Capacitance is guaranteed by periodic teg.
Note 3: C determines the no load AC power consuce. For complete explanation see 54C/74C Family Characteristics Application Note
PD
AN-90.
Note 4: These are peak output c. Continut is rated at 12 mA max.
4
e
Typical Performance Characteristics T
25 C
§
A
MM54C373/MM74C373
Propagation Delay, LATCH
ENABLE to Output vs Load
Capacitance
MM54C373/MM74C373
Propagation Delay,
Data In to Output
MM54C374/MM74C374
Propagation Delay,
CLOCK to Output
vs Load Capacitance
vs Load Capacitance
TL/F/5906–3
MM54C373/MM74C373,
MM54C374/MM74C374
Change in Propagation Delay per
pF of Load Capacitance (Dt /pF)
vs Power Supply Voltage
MM54C373/MM74C373,
MM54C374/MM74C374
Output Sink Current vs V
M54C3M74C37
M54C374M74C4 Output
PD
b
V
OUT
Soce Current s V
OUT
CC
TL/F/5906–4
Truth Table
MM54C373/MM74C373
MM54C374/M74C374
Output
LATCH
put
le
e
e
e
e
e
e
D
Q
Clock
D
Q
L
H
Low logic level
High logic level
Irrelevant
Disable
ENABLE
L
L
H
H
H
L
L
L
H
L
L
L
H
L
H
L
X
L
Q
Low to high logic level transition
Preexisting output level
L
X
X
X
Q
Q
Hi-Z
High impedance output state
H
H
X
Hi-Z
5
Typical Applications
Data Bus Interfacing Element
Simple, Latching, Octal, LED Indicator
Driver with Blanking for Use as Data Display,
Bus Monitor, mP Front Panel Display, Etc.
TL/F/5906–5
906–6
Logic Diagrams
MM54C373/MM74C373 (1 of 8 Latches)
TL/F/5906–7
C374 (1 of 8 Flip-Flops)
TL/F/5906–8
6
TRI-STATE Test Circuits and Switching Time Waveforms
e
e
50 pF
t , t
1H H1
t
1H
, C
L
5 pF
t
H1
, C
L
TL/F/5906–10
TL/F/5906–9
e
e
50 pF
t , t
0H H0
t
0H
, C
L
5 pF
t
H0
, C
L
T/5906–12
TL/F/5906–11
Switching Time Waveforms
MM54C373/MM7373
e
Output Disable
GND
TL/F/5906–13
M54C374/MM74C374
e
Output Disable
GND
TL/F/5906–14
7
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54C373J, MM54C374J, MM74C373J or MM74C374J
NS Package Number J20A
al-In-Line Package (N)
Order NumbM54C374N, MM74C373N or MM74C374N
age Number N20A
LIFE SUPPORT
NATIONAL’S AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCAs used herein:
1. Life support ms are devices or
systems which, (ed for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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