MPC506 [TI]
16V、16:1、单通道通用模拟多路复用器;
| 型号： | MPC506 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16V、16:1、单通道通用模拟多路复用器 开关 信号电路 复用器 复用器或开关 |
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MPC506A
MPC507A
M
P
C
5
0
6
M
P
C
5
0
7
SBFS018A – JANUARY 1988 – REVISED OCTOBER 2003
Single-Ended 16-Channel/Differential 8-Channel
CMOS ANALOG MULTIPLEXERS
FUNCTIONAL DIAGRAMS
FEATURES
● ANALOG OVERVOLTAGE PROTECTION: 70VPP
● NO CHANNEL INTERACTION DURING
1kΩ
1kΩ
1kΩ
OVERVOLTAGE
In 1
Out
● BREAK-BEFORE-MAKE SWITCHING
● ANALOG SIGNAL RANGE: ±15V
● STANDBY POWER: 7.5mW typ
● TRUE SECOND SOURCE
In 2
Decoder/
Driver
In 16
Overvoltage
Clamp and
Signal
DESCRIPTION
5V
Ref
Level
Shift
The MPC506A is a 16-channel single-ended analog multi-
plexer, and the MPC507A is an 8-channel differential multi-
plexer.
Isolation
(1) (1) (1)
(1) (1)
NOTE: (1) Digital
Input Protection.
The MPC506A and MPC507A multiplexers have input over-
voltage protection. Analog input voltages may exceed either
power supply voltage without damaging the device or dis-
turbing the signal path of other channels. The protection
circuitry assures that signal fidelity is maintained even under
fault conditions that would destroy other multiplexers. Analog
inputs can withstand 70VPP signal levels and standard ESD
tests. Signal sources are protected from short circuits should
multiplexer power loss occur; each input presents a 1kΩ
resistance under this condition. Digital inputs can also sus-
tain continuous faults up to 4V greater than either supply
voltage.
MPC506A
VREF A0 A1 A2 A3 EN
1kΩ
1kΩ
In 1A
In 8A
Out A
Out B
1kΩ
1kΩ
In 1B
In 8B
Decoder/
Driver
Overvoltage
Clamp and
Signal
These features make the MPC506A and MPC507A ideal for
use in systems where the analog signals originate from
external equipment or separately powered sources.
5V
Ref
Level
Shift
Isolation
(1)
(1)
(1) (1)
The MPC506A and MPC507A are fabricated with Burr-
Brown’s dielectrically isolated CMOS technology. The multi-
plexers are available in plastic DIP and plastic SOIC pack-
ages. Temperature range is –40/+85°C.
NOTE: (1) Digital
Input Protection.
MPC507A
VREF A0 A1 A2
EN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1988-2003, Texas Instruments Incorporated
www.ti.com
ELECTRICAL CHARACTERISTICS
Supplies = +15V, –15V; VREF (Pin 13) = Open; VAH (Logic Level High) = +4.0V; VAL (Logic Level Low) = +0.8V unless otherwise specified.
MPC506A/MPC507A
PARAMETER
TEMP
MIN
TYP
MAX
UNITS
ANALOG CHANNEL CHARACTERISTICS
VS, Analog Signal Range
R
Full
+25°C
Full
+25°C
Full
+25°C
Full
Full
–15
+15
1.5
1.8
V
ON, On Resistance(1)
1.3
1.5
0.5
kΩ
kΩ
nA
nA
nA
nA
nA
µA
nA
nA
nA
IS (OFF), Off Input Leakage Current
10
ID (OFF), Off Output Leakage Current
MPC506A
0.2
5
5
MPC507A
I
I
D (OFF) with Input Overvoltage Applied(2)
D (ON), On Channel Leakage Current
MPC506A
+25°C
+25°C
Full
2
2
10
10
MPC507A
Full
IDIFF Differential Off Output Leakage Current
(MPC507A Only)
Full
10
nA
DIGITAL INPUT CHARACTERISTICS
V
V
V
V
AL, Input Low Threshold
AH, Input High Threshold(3)
AL, MOS Drive(4)
Full
Full
+25°C
+25°C
Full
0.8
0.8
1.0
V
V
V
V
µA
4.0
6.0
AH, MOS Drive(4)
IA, Input Leakage Current (High or Low)(5)
SWITCHING CHARACTERISTICS
tA, Access Time
+25°C
Full
+25°C
+25°C
Full
0.3
µs
µs
ns
ns
ns
ns
ns
µs
µs
dB
pF
pF
pF
pF
pF
0.6
t
t
OPEN, Break-Before-Make Delay
ON (EN), Enable Delay (ON)
25
50
80
200
500
500
tOFF (EN), Enable Delay (OFF)
+25°C
Full
250
Settling Time (0.1%)
(0.01%)
"OFF Isolation"(6)
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
25°C
1.2
3.5
68
5
50
25
5
C
C
S (OFF), Channel Input Capacitance
D (OFF), Channel Output Capacitance: MPC506A
MPC507A
CA, Digital Input Capacitance
CDS, (OFF), Input to Output Capacitance
+25°C
0.1
POWER REQUIREMENTS
PD, Power Dissipation
I+, Current Pin 1(7)
Full
Full
Full
7.5
0.7
5
mW
mA
µA
1.5
20
I–, Current Pin 27(7)
NOTES: (1) VOUT = ±10V, IOUT = –100µA. (2) Analog overvoltage = ±33V. (3) To drive from DTL/TTL circuits. 1kΩ pull-up resistors to +5.0V supply are recommended.
(4) VREF = +10V. (5) Digital input leakage is primarily due to the clamp diodes. Typical leakage is less than 1nA at 25°C. (6) VEN = 0.8V, RL = 1kΩ,
CL = 15pF, VS = 7Vrms, f = 100kHz. Worst-case isolation occurs on channel 8 due to proximity of the output pins. (7) VEN, VA = 0V or 4.0V.
MPC506A, MPC507A
2
SBFS018A
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PIN CONFIGURATION
Top View
Top View
28 Out A
27 –VSUPPLY
26 In 8A
25 In 7A
24 In 6A
23 In 5A
22 In 4A
21 In 3A
28 Out
+VSUPPLY
Out B
NC
1
2
+VSUPPLY
1
2
27 –VSUPPLY
26 In 8
25 In 7
24 In 6
23 In 5
22 In 4
21 In 3
NC
3
NC
3
In 8B
In 7B
In 6B
In 5B
In 4B
In 3B
In 2B
In 1B
Ground
VREF
4
In 16
4
5
In 15
5
6
In 14
6
7
In 13
7
8
In 12
8
In 2A
20
In 2
20
9
9
In 11
In 1A
19
In 1
19
10
11
12
13
14
10
11
12
13
14
In 10
Enable
18
Enable
18
In 9
Address A0
17
Address A0
17
Ground
VREF
Address A1
16
Address A1
16
Address A2
15
Address A2
15
NC
Address A3
MPC507A (Plastic)
MPC506A (Plastic)
TRUTH TABLES
MPC506A
MPC507A
"ON"
"ON"
A3
A2
A1
A0
EN
CHANNEL
CHANNEL
A2
A1
A0
EN
PAIR
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
L
L
H
H
L
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
None
1
2
3
4
5
6
7
8
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
L
None
H
H
H
H
H
H
H
H
1
2
3
4
5
6
7
8
L
H
H
L
9
H
L
10
11
12
13
14
15
16
H
H
L
L
H
H
H
MPC506A, MPC507A
3
SBFS018A
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ABSOLUTE MAXIMUM RATINGS(1)
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see
the Package Option Addendum located at the end of this
data sheet.
Voltage between supply pins ............................................................... 44V
V
REF to ground, V+ to ground ............................................................... 22V
V– to ground ........................................................................................ 25V
Digital input overvoltage:
V
EN, VA: VSUPPLY (+) ............................................................................ +4V
SUPPLY (–) ............................................................................ –4V
or 20mA, whichever occurs first.
V
Analog input overvoltage:
VS: VSUPPLY (+) .................................................................................. +20V
V
SUPPLY (–).................................................................................. –20V
Continuous current, S or D ............................................................... 20mA
Peak current, S or D
(pulsed at 1ms, 10% duty cycle max) ............................................ 40mA
Power dissipation* ............................................................................. 2.0W
Operating temperature range ........................................... –40°C to +85°C
Storage temperature range ............................................. –65°C to +150°C
*Derate 20.0mW/°C above TA = 70
NOTE: (1) Absolute maximum ratings are limiting values, applied individu-
ally, beyond which the serviceability of the circuit may be impaired. Func-
tional operation under any of these conditions is not necessarily implied.
TYPICAL PERFORMANCE CURVES
TA = +25°C unless otherwise noted.
SETTLING TIME vs
SOURCE RESISTANCE FOR 20V STEP CHANGE
1k
CROSSTALK vs SIGNAL FREQUENCY
1
100
0.1
To ±0.01%
R
= 100kΩ
s
R
s
= 10kΩ
10
0.01
0.001
R
s
= 1kΩ
R
= 100Ω
s
To ±0.1%
1
0.1
0.0001
0.01
0.1
1
10
100
1
10
100
1k
10k
Source Resistance (kΩ)
Signal Frequency (Hz)
COMBINED CMR vs
FREQUENCY MPC507A AND INA110
120
100
80
60
40
20
0
G = 500
G = 100
G = 10
1
10
100
1k
10k
Frequency (Hz)
MPC506A, MPC507A
4
SBFS018A
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DISCUSSION OF
SPECIFICATIONS
DC CHARACTERISTICS
Input Offset Voltage
The static or dc transfer accuracy of transmitting the multi-
plexer input voltage to the output depends on the channel
ON resistance (RON), the load impedance, the source imped-
ance, the load bias current and the multiplexer leakage
current.
Bias current generates an input OFFSET voltage as a result
of the IR drop across the multiplexer ON resistance and
source resistance. A load bias current of 10nA will generate
an offset voltage of 20µV if a 1kΩ source is used. In general,
for the MPC506A, the OFFSET voltage at the output is
determined by:
Single-Ended Multiplexer Static Accuracy
The major contributors to static transfer accuracy for single-
ended multiplexers are:
VOFFSET = (IB + IL) (RON + RS)
where IB = Bias current of device multiplexer is driving
IL = Multiplexer leakage current
Source resistance loading error
Multiplexer ON resistance error
dc offset error caused by both load bias current and
multiplexer leakage current.
RON = Multiplexer ON resistance
RS = Source resistance
Differential Multiplexer Static Accuracy
Resistive Loading Errors
Static accuracy errors in a differential multiplexer are diffi-
cult to control, especially when it is used for multiplexing
low-level signals with full-scale ranges of 10mV to 100mV.
The source and load impedances will determine the input
resistive loading errors. To minimize these errors:
• Keep loading impedance as high as possible. This mini-
mizes the resistive loading effects of the source resistance
and multiplexer ON resistance. As a guideline, load
impedance of 108Ω or greater will keep resistive loading
errors to 0.002% or less for 1000Ω source impedances. A
106Ω load impedance will increase source loading error
to 0.2% or more.
The matching properties of the multiplexer, source and
output load play a very important part in determining the
transfer accuracy of the multiplexer. The source impedance
unbalance, common-mode impedance, load bias current
mismatch, load differential impedance mismatch, and com-
mon-mode impedance of the load all contribute errors to the
multiplexer. The multiplexer ON resistance mismatch, leak-
age current mismatch and ON resistance also contribute to
differential errors.
• Use sources with impedances as low as possible. A
1000Ω source resistance will present less than 0.001%
loading error and 10kΩ source resistance will increase
source loading error to 0.01% with a 108 load impedance.
Referring to Figure 2, the effects of these errors can be
minimized by following the general guidelines described in
this section, especially for low-level multiplexing applica-
tions.
Input resistive loading errors are determined by the follow-
ing relationship (see Figure 1).
IBIAS
RS1
RON
RS1A
RON1A
IBIAS A
VM
Cd/2
Cd/2
Measured
Voltage
IL
Rd/2
RCM
IL
RCM
RS16
ROFF
VS1
VS1
ZL
ZL
RS1B
RON1B IBIAS B
RCM1
VS16
CCM
Rd/2
RS8A
ROFF8A
FIGURE 1. MPC506A Static Accuracy Equivalent Circuit.
Source and Multiplexer Resistive Loading Error
VS8
RS8B
ROFF8B
RCM8
R
S +RON
(RS +RON) =
×100
R
S +RON +RL
where RS = source resistance
RL = load resistance
FIGURE 2. MPC507A Static Accuracy Equivalent Circuit.
RON = multiplexer ON resistance
MPC506A, MPC507A
5
SBFS018A
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Load (Output Device) Characteristics
see that the amplitude of the switching transients seen at the
source and load decrease proportionally as the capacitance
of the load and source increase. The trade-off for reduced
switching transient amplitude is increased settling time. In
effect, the amplitude of the transients seen at the source and
load are:
• Use devices with very low bias current. Generally, FET
input amplifiers should be used for low-level signals less
than 50mV FSR. Low bias current bipolar input amplifi-
ers are acceptable for signal ranges higher than 50mV
FSR. Bias current matching will determine the input
offset.
dVL = (i/C) dt
where i = C (dV/dt) of the CMOS FET switches
C = load or source capacitance
• The system dc common-mode rejection (CMR) can never
be better than the combined CMR of the multiplexer and
driven load. System CMR will be less than the device
which has the lower CMR figure.
The source must then redistribute this charge, and the effect
of source resistance on settling time is shown in the Typical
Performance Curves. This graph shows the settling time for
a 20V step change on the input. The settling time for smaller
step changes on the input will be less than that shown in the
curve.
• Load impedances, differential and common-mode, should
be 1010Ω or higher.
SOURCE CHARACTERISTICS
• The source impedance unbalance will produce offset,
common-mode and channel-to-channel gain-scatter er-
rors. Use sources which do not have large impedance
unbalances if at all possible.
RSA
Node A
CdA
RdA
Load
RdB
CSA
RCMS
• Keep source impedances as low as possible to minimize
resistive loading errors.
ZCM
MPC507A
Channel
Source
CSB
• Minimize ground loops. If signal lines are shielded,
ground all shields to a common point at the system analog
common.
Node B
CCMS
CdB
RSB
If the MPC507A is used for multiplexing high-level signals
of 1V to 10V full-scale ranges, the foregoing precautions
should still be taken, but the parameters are not as critical as
for low-level signal applications.
DYNAMIC CHARACTERISTICS
Settling Time
The gate-to-source and gate-to-drain capacitance of the
CMOS FET switches, the RC time constants of the source
and the load determine the settling time of the multiplexer.
FIGURE 4. Settling and Common-Mode Effects—
MPC507A
Governed by the charge transfer relation i = C (dV/dt), the
charge currents transferred to both load and source by the
analog switches are determined by the amplitude and rise
time of the signal driving the CMOS FET switches and the
gate-to-drain and gate-to-source junction capacitances as
shown in Figures 3 and 4. Using this relationship, one can
Switching Time
This is the time required for the CMOS FET to turn ON
after a new digital code has been applied to the Channel
Address inputs. It is measured from the 50 percent point of
the address input signal to the 90 percent point of the analog
signal seen at the output for a 10V signal change between
channels.
MPC506A Channel
Load
Crosstalk
Source
Node A
Crosstalk is the amount of signal feedthrough from the
seven (MPC507A) or 15 (MPC506A) OFF channels ap-
pearing at the multiplexer output. Crosstalk is caused by the
voltage divider effect of the OFF channel, OFF resistance
and junction capacitances in series with the RON and RS
impedances of the ON channel. Crosstalk is measured with
a 20Vp-p 1000Hz sine wave applied to all off channels. The
crosstalk for these multiplexers is shown in the Typical
Performance Curves.
RS
CL
RL
CS
FIGURE 3. Settling Time Effects—MPC506A.
MPC506A, MPC507A
6
SBFS018A
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Factors which will degrade multiplexer and system DC
CMR are:
Common-Mode Rejection (MPC507A Only)
The matching properties of the load, multiplexer and source
affect the common-mode rejection (CMR) capability of a
differentially multiplexed system. CMR is the ability of the
multiplexer and input amplifier to reject signals that are
common to both inputs, and to pass on only the signal
difference to the output. For the MPC507A, protection is
provided for common-mode signals of ±20V above the
power supply voltages with no damage to the analog switches.
• Amplifier bias current and differential impedance mis-
match
• Load impedance mismatch
• Multiplexer impedance and leakage current mismatch
• Load and source common-mode impedance
AC CMR roll-off is determined by the amount of common-
mode capacitances (absolute and mismatch) from each
signal line to ground. Larger capacitances will limit CMR
at higher frequencies; thus, if good CMR is desired at
higher frequencies, the common-mode capacitances and
unbalance of signal lines and multiplexer to amplifier wiring
must be minimized. Use twisted-shielded pair signal lines
wherever possible.
The CMR of the MPC507A and Burr-Brown's INA110
instrumentation amplifier (G = 100) is 110dB at DC to 10Hz
with a 6dB/octave roll-off to 70dB at 1000Hz. This measure-
ment of CMR is shown in the Typical Performance Curves
and is made with a Burr-Brown INA110 instrumentation
amplifier connected for gains of 500, 100, and 10.
SWITCHING WAVEFORMS
Typical at +25°C, unless otherwise noted.
BREAK-BEFORE-MAKE DELAY (tOPEN
)
VA Input
2V/Div
MPC506A1
+5V
4.0V
VAM
A3
A2
In 1
Address Drive
(VA)
VA
A1 In 2 Thru In 15
A0
1 On
16 On
Output
0.5V/Div
0V
In 16
50Ω
Output
VOUT
Out
1kΩ
En
GND
50%
50%
+4.0V
12.5pF
tOPEN
100ns/Div
NOTE: (1) Similar connection for MPC507A.
ENABLE DELAY (tON (EN), tOFF (EN))
Enable Drive
MPC506A1
V
AM = 4.0V
A3
A2
+10V
In 1
50%
A1
A0
0V
In 2 Thru In 16
Output
90%
1 On
Out
En
GND
VA
12.5pF
90%
1kΩ
50Ω
t
ON(EN)
tOFF(EN)
In 1 Thru
In 16 Off
Output
2V/Div
NOTE: (1) Similar connection for MPC507A.
100ns/Div
MPC506A, MPC507A
7
SBFS018A
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PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS
TA = +25°C, VS = ±15V, VAM = +4V, VAL = 0.8V and VREF = Open, unless otherwise noted.
ON RESISTANCE vs INPUT SIGNAL, SUPPLY VOLTAGE
100µA
RON = V2/100µA
V2
In
Out
VIN
NORMALIZED ON RESISTANCE
vs SUPPLY VOLTAGE
ON RESISTANCE vs
ANALOG INPUT VOLTAGE
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
±125°C > TA > –55°C
TA = +125°C
VIN = +5V
TA = +25°C
TA = –55°C
±5
±6
±7
±8
±9 ±10 ±11 ±12 ±13 ±14 ±15
–10 –8
–6
–4
–2
0
2
4
6
8
10
Supply Voltage (V)
Analog Input (V)
ANALOG INPUT OVERVOLTAGE CHARACTERISTICS
21
18
7
Positive Input Overvoltage
6
5
4
3
2
1
0
15
12
9
IO (Off)
IIN
Analog Input
Current (IIN
A
A
)
+VIN
6
Output Off
Leakage Current
IO (Off)
3
0
+12
+15 +18
+21
+24
+27
+30
+33
+36
Analog Input Overvoltage (V)
21
18
Negative Input Overvoltage
4
2
0
15
12
9
IO (Off)
A
IIN
Analog Input
Current (IIN
A
)
−VIN
6
Output Off
Leakage Current
IO (Off)
3
0
−12
−15 −18
−21
−24
−27
−30
−33
−36
Analog Input Overvoltage (V)
MPC506A, MPC507A
8
SBFS018A
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PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (CONT)
TA = +25°C, VS = ±15V, VAM = +4V, VAL = 0.8V and VREF = Open, unless otherwise noted.
LEAKAGE CURRENT vs TEMPERATURE
En
+0.8V
Out
Out
A
ID (Off)
A
I
D (On)
En
A1
±
±10V
10V
A0
±
10V
±10V
+4.0V
100nA
10nA
1nA
Off Output
Current
ID (Off)
Out
IS (Off)
A
On Leakage
Current ID (On)
±10V
En
±
+0.8V
10V
Off Input
Leakage Current
IS (Off)
100pA
10pA
NOTE: (1) Two measurements per channel: +10V/–10V and –10V/+10V.
(Two measurements per device for ID (Off): +10V/–10V and –10V/+10V).
25
50
75
Temperature (°C)
100
125
ON-CHANNEL CURRENT vs VOLTAGE
±14
±12
±10
±8
–55°C
+25°C
+125°C
A
±VIN
±6
±4
±2
0
0
±2
±4
±6
±8
±10
±12
±14
±16
VIN –Voltage Across Switch (V)
MPC506A, MPC507A
9
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PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (CONT)
TA = +25°C, VS = ±15V, VAM = +4V, VAL = 0.8V and VREF = Open, unless otherwise noted.
SUPPLY CURRENT vs TOGGLE FREQUENCY
+15V/+10V
8
+ISUPPLY
A
6
4
2
0
MPC506A(1)
+V
A3
A2
±10V/±5V
±10V/±5V
In 1
In 2 Thru In 15
In 16
VA
A1
A0
VS = ±15V
50Ω
Out
En
GND –V
VS = ±10V
+4V
10MΩ
14pF
A
–ISUPPLY
100
1k
10k
100k
1M
10M
–15V/–10V
Toggle Frequency (Hz)
NOTE: (1) Similar connection for MPC507A.
ACCESS TIME vs LOGIC LEVEL (High)
1000
900
800
700
600
500
400
300
+15V
+V
In 1
In 2 Thru
In 15
VREF
A3
A2
–10V
VA
VREF = Open for logic high levels ≤ 6V
REF = Logic high for logic high levels > 6V
A1
A0
MPC
506A(1)
V
50Ω
In 16
Out
+10V
Probe
En
GND –V
–15V
+4V
14pF
10MΩ
3
4
5
6
7
8
9
10 11 12 13 14 15
NOTE: (1) Similar connection for MPC507A.
Logic Level High (V)
ACCESS TIME WAVEFORM
Address
Drive (VA)
VAH
4.0V
VA Input
2V/Div
1/2VAH
0V
10V
90%
Output A
5V/Div
10V
tA
200ns/Div
MPC506A, MPC507A
10
SBFS018A
www.ti.com
Differential Multiplexer (MPC507A)
INSTALLATION AND
OPERATING INSTRUCTIONS
Single or multitiered configurations can be used to expand
multiplexer channel capacity up to 64 channels using a
64 x 1 or an 8 x 8 configuration.
The ENABLE input, pin 18, is included for expansion of
the number of channels on a single node as illustrated in
Figure 5. With ENABLE line at a logic 1, the channel is
selected by the 3-bit (MPC507A or 4-bit MPC506A) Chan-
nel Select Address (shown in the Truth Tables). If ENABLE
is at logic 0, all channels are turned OFF, even if the Channel
Address Lines are active. If the ENABLE line is not to be
used, simply tie it to +V supply.
Single-Node Expansion
The 64 x 1 configuration is simply eight (MPC507A) units
tied to a single node. Programming is accomplished with a
6-bit counter, using the 3LSBs of the counter to control
Channel Address inputs A0, A1, A2 and the 3MSBs of the
counter to drive a 1-of-8 decoder. The 1-of-8 decoder then
is used to drive the ENABLE inputs (pin 18) of the MPC507A
multiplexers.
If the +15V and/or –15V supply voltage is absent or shorted
to ground, the MPC507A and MPC506A multiplexers will
not be damaged; however, some signal feedthrough to the
output will occur. Total package power dissipation must not
be exceeded.
Two-Tier Expansion
Using an 8 x 8 two-tier structure for expansion to 64
channels, the programming is simplified. The 6-bit counter
output does not require a 1-of-8 decoder. The 3LSBs of the
counter drive the A0, A1 and A2 inputs of the eight first-tier
multiplexers and the 3MSBs of the counter are applied to the
A0, A1, and A2 inputs of the second-tier multiplexer.
For best settling speed, the input wiring and interconnec-
tions between multiplexer output and driven devices should
be kept as short as possible. When driving the digital inputs
from TTL, open collector output with pull up resistors are
recommended (see Typical Performance Curves, Access
Time).
Single vs Multitiered Channel Expansion
To preserve common-mode rejection of the MPC507A, use
twisted-shielded pair wire for signal lines and inter-tier
connections and/or multiplexer output lines. This will help
common-mode capacitance balance and reduce stray signal
pickup. If shields are used, all shields should be connected
as close as possible to system analog common or to the
common-mode guard driver.
In addition to reducing programming complexity, two-tier
configuration offers the added advantages over single-node
expansion of reduced OFF channel current leakage (reduced
OFFSET), better CMR, and a more reliable configuration if
a channel should fail ON in the single-node configuration,
data cannot be taken from any channel, whereas only one
channel group is failed (8 or 16) in the multitiered configu-
ration.
In 1
MPC
506A
In 2
In 3
Out
28
Group 1
Ch1-16
In 1
In 2
In 3
Group 1
Enable
Out
Multiplexer
Output
In 16
18
28
A3 A2 A1 A0
MPC506A
Direct
6-Bit
To
Group
2
En
+V
In 16
18
Binary
Counter
20
Multiplexer
Output
21
22
23
24
25
A0 A1 A2 A3
Out
Direct
In 1
28
Buffered
OPA602
1/4 OPA404
MPC506A
En
+V
18
In 16
A3 A2 A1 A0
To
Group
3
A0 A1 A2 A3
In 1
In 2
In 3
Group 4
Enable
Out
Buffered
OPA602
1/4 OPA404
Out
18
18
MPC506A
Group 4
MPC506A
En
+V
28
49-64
28
In 16
Settling time to 0.01% for RS 100Ω
—Two MPC506A units in parallel 10µs
—Four MPC507A units in parallel 12µs
A0 A1 A2 A3
FIGURE 5. 64-Channel, Single-Tier Expansion.
CHANNEL EXPANSION
4LSBs
4MSBs
Settling Time to
8-Bit Channel
Address Generator
Single-Ended Multiplexer (MPC506A)
0.01% is 20µs
with RS = 100Ω
Up to 64 channels (four multiplexers) can be connected to a
single node, or up to 256 channels using 17 MPC506A
multiplexers on a two-tiered structure as shown in Figures 5
and 6.
FIGURE 6. Channel Expansion up to 256 Channels Using
16x16 Two-Tiered Expansion
MPC506A, MPC507A
11
SBFS018A
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
12-Mar-2013
PACKAGING INFORMATION
Orderable Device
MPC506AP
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
ACTIVE
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
NTD
28
28
28
28
28
28
28
28
28
28
28
28
13
13
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
N / A for Pkg Type
MPC506AP
MPC506AP
MPC506AU
MPC506AU
MPC506AU
MPC506AU
MPC507AP
MPC507AP
MPC507AU
MPC507AU
MPC507AU
MPC507AU
MPC506APG4
MPC506AU
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NTD
DW
DW
DW
DW
NTD
NTD
DW
DW
DW
DW
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
20
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
N / A for Pkg Type
-40 to 85
MPC506AU/1K
MPC506AU/1KG4
MPC506AUG4
MPC507AP
1000
1000
20
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
13
Green (RoHS
& no Sb/Br)
MPC507APG4
MPC507AU
13
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
20
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
MPC507AU/1K
MPC507AU/1KG4
MPC507AUG4
1000
1000
20
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Mar-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MPC506AU/1K
MPC507AU/1K
SOIC
SOIC
DW
DW
28
28
1000
1000
330.0
330.0
32.4
32.4
11.35 18.67
11.35 18.67
3.1
3.1
16.0
16.0
32.0
32.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MPC506AU/1K
MPC507AU/1K
SOIC
SOIC
DW
DW
28
28
1000
1000
367.0
367.0
367.0
367.0
55.0
55.0
Pack Materials-Page 2
MECHANICAL DATA
MPDI056 – APRIL 2001
NTD (R-PDIP-T28)
PLASTIC DUAL-IN-LINE
D
1.565 (39,75)
1.380 (35,05)
28
15
0.580 (14,73)
0.485 (12,32)
D
1
14
Index
Area
0.250 (6,35)
MAX
H
E
C
0.070 (1,78)
0.030 (0,76)
0.195 (4,95)
0.125 (3,18)
0.015 (0,38)
0.625 (15,88)
0.600 (15,24)
MIN
Base
Plane
C
–C–
E
Seating
Plane
0.200 (5,08)
0.115 (2,92)
0.600 (15,26)
0.100 (2,54)
0.015 (0,38)
0.008 (0,20)
0.022 (0,56)
0.014 (0,36)
0.010 (0,25)
C
0.005 (0,13)
MIN 4 PL
Full Lead
0.060 (1,52)
F
M
C
D
0.000 (0,00)
0.700 (17,78)
MAX
F
4202496/A 03/01
NOTES: A. All linear dimensions are in inches (millimeters).
I. Distance between leads including dambar protrusions
to be 0.005 (0,13) minumum.
B. This drawing is subject to change without notice.
J. A visual index feature must be located within the
cross-hatched area.
C. Dimensions are measured with the package
seated in JEDEC seating plane gauge GS-3.
K. For automatic insertion, any raised irregularity on the
top surface (step, mesa, etc.) shall be symmetrical
about the lateral and longitudinal package centerlines.
L. Controlling dimension in inches.
D. Dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 (0,25).
E. Dimensions measured with the leads constrained to be
perpendicular to Datum C.
F. Dimensions are measured at the lead tips with the
leads unconstrained.
M. Falls within JEDEC MS-011-AB.
G. Pointed or rounded lead tips are preferred to ease
insertion.
H. Maximum dimension does not include dambar
protrusions. Dambar protrusions shall not exceed
0.010 (0,25).
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