MSP-STK430B320_技术文档

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

Low Supply Voltage Range, 2.7 V – 5.5 V

Integrated 12+2 Bit A/D Converter

Low Operation Current, 3 mA at 1 MHz,

3 V

Family Members Include:

– MSP430P325, 16KB OTP, 512 Byte RAM

Ultralow Power Consumption (Standby

Mode Down to 0.1 A)

EPROM Version Available for Prototyping:

PMS430E325

Five Power-Saving Modes

Serial Onboard Programming

Wakeup From Standby Mode in 6 s

Programmable Code Protection by Security

Fuse

16-Bit RISC Architecture, 300 ns Instruction

Cycle Time

Avaliable in 64 Pin Quad Flatpack (QFP),

68 Pin Plastic J-Leaded Chip Carrier

(PLCC), 68 Pin J-Leaded Ceramic Chip

Carrier (JLCC) Package (EPROM Version)

Single Common 32 kHz Crystal, Internal

System Clock up to 3.3 MHz

Integrated LCD Driver for up to 84

Segments

description

The Texas Instruments MSP430 is an ultralow-power mixed-signal microcontroller family consisting of several

deviceswhichfeaturedifferentsetsofmodulestargetedtovariousapplications. Themicrocontrollerisdesigned

to be battery operated for an extended application lifetime. With 16-bit RISC architecture, 16-bit integrated

registers on the CPU, and a constant generator, the MSP430 achieves maximum code efficiency. The digitally-

controlled oscillator, together with the frequency-locked-loop (FLL), provides a wakeup from a low-power mode

to active mode in less than 6 s.

PG Package

(TOP VIEW)

64 636261 6059585756 55545352

1

2

3

4

5

6

7

8

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

AV

DV

SV

Rext

A2

COM0

CC

S20/O20/CMPI

S19/O19

S18/O18

S17/O17

S16/O16

S15/O15

S14/O14

S13/O13

S12/O12

S11/O11

S10/O10

S9/O9

A3

A4

A5

9

Xin

Xout/TCLK

CIN

10

11

12

13

14

15

16

17

18

19

TP0.0

TP0.1

TP0.2

TP0.3

TP0.4

TP0.5

P0.0

S8/O8

S7/O7

S6/O6

S5/O5

S4/O4

P0.1/RXD

S3/O3

202122 232425 26 272829303132

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

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MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

description (continued)

Typicalapplicationsincludesensorsystemsthatcaptureanalogsignals, convertthemtodigitalvalues, andthen

process the data and display them or transmit them to a host system. The MSP430x32x offers an integrated

12+2 bit A/D converter with six multiplexed inputs.

AVAILABLE OPTIONS

PACKAGED DEVICES

PLASTIC

64-PIN QFP

(PM)

PLASTIC

68-PIN PLCC

(FN)

CERAMIC

68-PIN JLCC

(FZ)

PLASTIC

64-PIN QFP

(PG)

T

A

–40°C to 85°C

25°C

MSP430P325IPG

—

MSP430P325IPM

—

MSP430P325IFN

—

PMS430E325FZ

functional block diagram

RST/NMI

XIN Xout/TCLK

XBUF

P0.0

P0.7

Oscillator

FLL

System Clock

ACLK

MCLK

256/512 B

RAM

Power-on-

Reset

8 b Timer/

Counter

I/O Port

8/16 kB ROM

16 kB OTP

8 I/O’s, All With

Interr. Cap.

TXD

RXD

Serial Protocol

Support

’C’: ROM

’P’: OTP

3 Int. Vectors

TDI/VPP

TDO/TDI

MAB, 16 Bit

MDB, 16 Bit

MAB, 4 Bit

CPU

Test

JTAG

MCB

Incl. 16 Reg.

MDB, 8 Bit

Bus

Conv

TMS

TCK

LCD

ADC

Watchdog

Timer

Timer/Port

Basic

Timer1

12 + 2 Bit

84 Segments

Applications:

Com0–3

A/D Conv.

Timer, O/P

6 Channels

Current S.

S0–19/O2–19

S20/O20CMPI

f

15/16 Bit

LCD

1, 2, 3, 4 MUX

CMPI

6

A0–5

SVCC

TP0.0–5

CIN

R33

R13

R03

Rext

R23

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MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

Terminal Functions

TERMINAL

NAME

I/O

DESCRIPTION

NO.

1

AV

A0

A1

Positive analog supply voltage

Analog ground reference

CC

63

SS

61

I

Analog-to-digital converter input port 0 or digital input port 0

Analog-to-digital converter input port 1 or digital input port 1

Analog-to-digital converter inputs ports 2–5 or digital inputs ports 2–5

Input used as enable of counter TPCNT1 – Timer/Port

Common outputs, used for LCD backplanes – LCD

Positive digital supply voltage

62

A2–A5

CIN

5–8

11

I

COM0–3

51–54

2

O

DV

CC

SS

64

Digital ground reference

P0.0

18

19

I/O

General-purpose digital I/O

P0.1/RXD

P0.2/TXD

P0.3–P0.7

Rext

I/O

General-purpose digital I/O, receive digital input port, 8-Bit Timer/Counter

General-purpose digital I/O, transmit data output port, 8-Bit Timer/Counter

Five general-purpose digital I/Os, bit 3 to bit 7

20

I/O

21–25

4

I/O

I

Programming resistor input of internal current source

Reset input or non-maskable interrupt input

RST/NMI

R03

59

29

I

Input of fourth positive analog LCD level (V4) – LCD

Input of third positive analog LCD level (V3) – LCD

Input of second positive analog LCD level (V2) – LCD

Output of first positive analog LCD level (V1) – LCD

R13

28

I

R23

27

I

R33

26

O

SV

S0

S1

3

Switched AV to analog-to-digital converter

CC

30

O

Segment line S0 – LCD

31

Segment line S1 – LCD

S2–S5/O2–O5

S20/O20/CMPI

32–35

50

O

Segment lines S2 to S5 or digital output ports O2–O5, group 1 – LCD

Segment line S20 can be used as comparator input port CMPI – Timer/Port

I/O

S6–S9/O6–O9

S10–S13/O10–O13

S14–S17/O14–O17

S18-S19/O18-O19

TCK

36–39

40–43

44–47

48, 49

58

O

I

Segment lines S6 to S9 or digital output ports O6–O9, group 2 – LCD

Segment lines S10 to S13 or digital output ports O10–O13, group 3 – LCD

Segment lines S14 to S17 or digital output ports O14 to O17, group 4 – LCD

Segment lines S18 and S19 or digital output port O18 and O19, group 5 – LCD

Test clock, clock input terminal for device programming and test

Test data output, data output terminal or data input during programming

Test data input, data input terminal or input of programming voltage

Test mode select, input terminal for device programming and test

General-purpose 3-state digital output port, bit 0 – Timer/Port

TDO/TDI

55

I/O

I

TDI/VPP

56

TMS

57

I

TP0.0

12

O

TP0.1

TP0.2

TP0.3

TP0.4

TP0.5

13

14

15

16

17

O

General-purpose 3-state digital output port, bit 1 – Timer/Port

General-purpose 3-state digital output port, bit 2 – Timer/Port

General-purpose 3-state digital output port, bit 3 – Timer/Port

General-purpose 3-state digital output port, bit 4 – Timer/Port

General-purpose digital input/output port, bit 5 – Timer/Port

O

I/O

XBUF

Xin

60

9

O

I

Clock signal output of system clock MCLK or crystal clock ACLK

Input terminal of crystal oscillator

Xout/TCLK

10

I/O

Output terminal of crystal oscillator or test clock input

3

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MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

short-form description

processing unit

The processing unit is based on a consistent and orthogonally-designed CPU and instruction set. This design

structure results in a RISC-like architecture, highly transparent to the application development, and it is

distinguished by ease of programming. All operations other than program-flow instructions are consequently

performed as register operations in conjunction with seven addressing modes for source and four modes for

destination operand.

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R4

Program Counter

CPU

Stack Pointer

Sixteen registers are located inside the CPU,

providing reduced instruction execution time. This

reduces a register-register operation execution

time to one cycle of the processor frequency.

Status Register

Constant Generator

General-Purpose Register

Four of the registers are reserved for special

use as a program counter, a stack pointer, a status

register, and a constant generator. The remaining

registers are available as general-purpose

registers.

R5

Peripherals are connected to the CPU using a

data address and control bus and can be handled

easily with all instructions for memory

manipulation.

General-Purpose Register

R14

R15

instruction set

The instruction set for this register-register architecture provides a powerful and easy-to-use assembler

language. The instruction set consists of 51 instructions with three formats and seven addressing modes.

Table 1 provides a summation and example of the three types of instruction formats; the addressing modes are

listed in Table 2.

Table 1. Instruction Word Formats

Dual operands, source-destination

Single operands, destination only

Relative jump, un-/conditional

e.g. ADD R4, R5

e.g. CALL R8

e.g. JNE

R4 + R5 → R5

PC → (TOS), R8 → PC

Jump-on equal bit = 0

Each instruction that operates on word and byte data is identified by the suffix B.

Examples: Instructions for word operation Instructions for byte operation

MOV

EDE, TONI

#235h, &MEM

R5

MOV.B

ADD.B

EDE, TONI

ADD

#35h, &MEM

PUSH

SWPB

PUSH.B R5

—

R5

4

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MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

Table 2. Address Mode Descriptions

ADDRESS MODE

Register

s

d

√

SYNTAX

MOV Rs, Rd

EXAMPLE

MOV R10, R11

OPERATION

√

R10 → R11

Indexed

√

MOV X(Rn), Y(Rm)

MOV EDE, TONI

MOV &MEM, &TCDAT

MOV @Rn, Y(Rm)

MOV @Rn+, RM

MOV #X, TONI

MOV 2(R5), 5(R6)

M(2 + R5) → M(6 + R6)

M(EDE) → M(TONI)

Symbolic (PC relative)

Absolute

√

M(MEM) → M(TCDAT)

M(R10) → M(Tab + R6)

M(R10) → R11, R10 + 2 → R10

#45 → M(TONI)

Indirect

√

MOV @R10, Tab(R6)

MOV @R10+, R11

MOV #45, TONI

Indirect autoincrement

Immediate

√

NOTE: s = source

d = destination

Computedbranches(BR)andsubroutinecalls(CALL)instructionsusethesameaddressingmodesastheother

instructions. These addressing modes provide indirect addressing, ideally suited for computed branches and

calls. The full use of this programming capability permits a program structure different from conventional 8- and

16-bit controllers. For example, numerous routines can easily be designed to deal with pointers and stacks

instead of using flag type programs for flow control.

operation modes and interrupts

The MSP430 operating modes support various advanced requirements for ultralow power and ultralow energy

consumption. This is achieved by the intelligent management of the operations during the different module

operation modes and CPU states. The requirements are fully supported during interrupt event handling. An

interrupt event awakens the system from each of the various operating modes and returns with the RETI

instruction to the mode that was selected before the interrupt event. The clocks used are ACLK and MCLK.

ACLK is the crystal frequency and MCLK is a multiple of ACLK and is used as the system clock.

The software can configure five operating modes:

Active mode (AM). The CPU is enabled with different combinations of active peripheral modules.

Low power mode 0 (LPM0). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals

are active, and loop control for MCLK is active.

Low power mode 1 (LPM1). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals

are active, and loop control for MCLK is inactive.

Low power mode 2 (LPM2). The CPU is disabled, peripheral operation continues, ACLK signal is active,

and MCLK and loop control for MCLK are inactive.

Low power mode 3 (LPM3). The CPU is disabled, peripheral operation continues, ACLK signal is active,

MCLKand loop control for MCLK are inactive, and the dc generator for the digital controlled oscillator(DCO)

(

MCLK generator) is switched off.

Low power mode 4 (LPM4). The CPU is disabled, peripheral operation continues, ACLK signal is inactive

(crystal oscillator stopped), MCLK and loop control for MCLK are inactive, and the dc generator for the DCO

is switched off.

The special function registers (SFR) include module-enable bits that stop or enable the operation of the specific

peripheral module. All registers of the peripherals may be accessed if the operational function is stopped or

enabled. However, some peripheral current-saving functions are accessed through the state of local register

bits. An example is the enable/disable of the analog voltage generator in the LCD peripheral, which is turned

on or off using one register bit.

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MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

operation modes and interrupts (continued)

The most general bits that influence current consumption and support fast turnon from low-power operating

modesarelocatedinthestatusregister(SR). FourofthesebitscontroltheCPUandthesystemclockgenerator:

SCG1, SCG0, OscOff, and CPUOff.

15

Reserved For Future

Enhancements

9

8

7

0

V

SCG1

SCG0

OscOff

rw-0

CPUOff

GIE

N

Z

C

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the ROM with an address range of

0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction

sequence.

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM INTERRUPT WORD ADDRESS PRIORITY

WDTIFG

Power-up, external reset, watchdog

Reset

0FFFEh

15, highest

(see Note1)

Non-maskable,

(Non)-maskable

NMIIFG (see Notes 1 and 3)

OFIFG (see Notes 1 and 4)

NMI, oscillator fault

Dedicated I/O P0.0

0FFFCh

0FFFAh

0FFF8h

14

13

12

P0.0IFG

Maskable

Dedicated I/O P0.1 or 8-Bit Timer/Counter

RXD

P0.1IFG

0FFF6h

0FFF4h

0FFF2h

0FFF0h

0FFEEh

0FFECh

11

10

9

Watchdog Timer

WDTIFG

ADCIFG

Maskable

8

7

6

ADC

Maskable

0FFEAh

0FFE8h

5

4

RC1FG, RC2FG, EN1FG

(see Note 2)

Timer/Port

0FFE6h

0FFE4h

0FFE2h

0FFE0h

3

2

1

Basic Timer1

BTIFG

Maskable

I/O port 0, P0.2–7

0, lowest

P0.27IFG (see Note 1)

NOTES: 1. Multiple source flags

2. Timer/Port interrupt flags are located in the T/P registers

3. Non-maskable: neither the individual nor the general interrupt enable bit will disable an interrupt event.

4. (Non)-maskable: the individual interrupt enable bit can disable on interrupt event, but the general interrupt enable bit cannot.

6

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MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

operation modes and interrupts (continued)

special function registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits

that are not allocated to a functional purpose are not physically present in the device. Simple SW access is

provided with this arrangement.

interrupt enable 1 and 2

7

6

5

4

3

2

1

0

Address

0h

P0IE.1

P0IE.0

OFIE

WDTIE

rw-0

WDTIE:

OFIE:

P0IE.0:

P0IE.1:

Watchdog Timer enable signal

Oscillator fault enable signal

Dedicated I/O P0.0

P0.1 or 8-Bit Timer/Counter, RXD

7

6

5

4

3

2

1

0

Address

01h

BTIE

TPIE

ADIE

rw-0

ADIE:

TPIE:

BTIE:

A/D converter enable signal

Timer/Port enable signal

Basic Timer1 enable signal

interrupt flag register 1 and 2

7

6

5

4

3

2

1

0

Address

02h

NMIIFG

P0IFG.1

rw-0

P0IFG.0

OFIFG

WDTIFG

rw-0

rw-1

rw-0

WDTIFG:

Set on overflow or security key violation

or

Reset on V

power on or reset condition at RST/NMI-pin

CC

OFIFG:

Flag set on oscillator fault

Dedicated I/O P0.0

P0.1 or 8-Bit Timer/Counter, RXD

Signal at RST/NMI-pin

P0.0IFG:

P0.1IFG:

NMIIFG:

7

6

5

4

3

2

1

0

Address

03h

BTIFG

ADIFG

rw

rw-0

BTIFG

ADFIG

Basic Timer1 flag

Analog-to-digital converter flag

7

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MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

operation modes and interrupts (continued)

module enable register 1 and 2

7

6

5

4

3

2

1

0

Address

04h

Address

05h

Legend rw:

Bit can be read and written.

rw-0:

Bit can be read and written. It is reset by PUC.

SFR bit not present in device.

memory organization

MSP430P325

PMS430E325

FFFFh

Int. Vector

FFE0h

FFDFh

16 kB OTP

or

EPROM

C000h

03FFh

512B RAM

0200h

01FFh

0100h

16b Per.

00FFh

0010h

8b Per.

000Fh

0000h

SFR

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MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

peripherals

Peripherals connect to the CPU through data, address, and control busses and can be handled easily with all

instructions for memory manipulation.

peripheral file map

PERIPHERALS WITH WORD ACCESS

Watchdog

ADC

Watchdog Timer control

WDTCTL

ADAT

0120h

Data register

Reserved

Control register

Input enable register

Input register

0118h

0116h

0114h

o112h

0110h

ACTL

AEN

AIN

PERIPHERALS WITH BYTE ACCESS

EPROM control

EPROM

EPCTL

CBCTL

054h

053h

Crystal buffer

System clock

Crystal buffer control

SCG frequency control

SCFQCTL 052h

SCG frequency integrator

SCFI1

SCFI0

051h

050h

Timer/Port

Timer/Port enable

Timer/Port data

Timer/Port counter2

Timer/Port counter1

Timer/Port control

TPE

TPD

TPCNT2

TPCNT1

TPCTL

04Fh

04Eh

04Dh

04Ch

04Bh

8-Bit Timer/Counter

Basic Timer1

LCD

8-Bit Timer/Counter data

8-Bit Timer/Counter preload

8-Bit Timer/Counter control

TCDAT

TCPLD

TCCTL

044h

043h

042h

Basic Timer counter2

Basic Timer counter1

Basic Timer control

BTCNT2

BTCNT1

BTCTL

047h

046h

040h

LCD memory 15

:

LCDM15

:

03Fh

:

LCD memory 1

LCD control & mode

LCDM1

LCDCTL

031h

030h

Port P0

Port P0 interrupt enable

Port P0 interrupt edge select

Port P0 interrupt flag

Port P0 direction

Port P0 output

Port P0 input

P0IE

015h

014h

013h

012h

011h

010h

P0IES

P0IFG

P0DIR

P0OUT

P0IN

Special function

SFR interrupt flag2

SFR interrupt flag1

SFR interrupt enable2

SFR interrupt enable1

IFG2

IFG1

IE2

003h

002h

001h

000h

IE1

oscillator and system clock

Twoclocksareusedinthesystem, thesystem(master)clock(MCLK)andtheauxiliaryclock(ACLK). TheMCLK

isamultipleoftheACLK. TheACLK runswiththecrystaloscillatorfrequency. Thespecialdesignoftheoscillator

supports the feature of low current consumption and the use of a 32 768 Hz crystal. The crystal is connected

across two terminals without any other external components being required.

The oscillator starts after applying VCC, due to a reset of the control bit (OscOff) in the status register (SR). It

can be stopped by setting the OscOff bit to a 1. The enabled clock signals ACLK, ACLK/2, ACLK/4, or MCLK

are accessible for use by external devices at output terminal XBUF.

9

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MSP430P325

MIXED SIGNAL MICROCONTROLLER

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oscillator and system clock (continued)

The controller system clock has to operate with different requirements according to the application and system

conditions. Requirements include:

High frequency in order to react quickly to system hardware requests or events

Low frequency in order to minimize current consumption, EMI, etc.

Stable frequency for timer applications e.g. real-time clock (RTC)

Enable start-stop operation with a minimum of delay

These requirements cannot all be met with fast frequency high-Q crystals or with RC-type low-Q oscillators. The

compromise selected for the MSP430 uses a low-crystal frequency, which is multiplied to achieve the desired

nominal operating range:

f

= (N+1) × f

crystal)

(

(system)

The crystal frequency multiplication is achieved with a frequency locked loop (FLL) technique. The factor N is

set to 31 after a power-up clear condition. The FLL technique, in combination with a digital controlled oscillator

(DCO) provides immediate start-up capability together with long term crystal stability. The frequency variation

of the DCO with the FLL inactive is typically 330 ppm, which means that with a cycle time of 1 µs the maximum

possible variation is 0.33 ns. For more precise timing, the FLL can be used forcing longer cycle times, if the

previous cycle time was shorter than the selected one. This switching of cycle times makes it possible to meet

the chosen system frequency over a long period of time.

The start-up operation of the system clock depends on the previous machine state. During a power-up clear

(PUC), the DCO is reset to its lowest possible frequency. The control logic starts operation immediately after

recognition of PUC. Connect operation of the FLL control logic requires the presence of a stable crystal

oscillator.

digital I/O

One 8-Bit I/O port (Port0) is implemented. Six control registers give maximum flexibility of digital input/output

to the application:

All individual I/O bits are programmable independently.

Any combination of input, output, and interrupt conditions is possible.

Interrupt processing of external events is fully implemented for all eight bits of port P0.

Provides read/write access to all registers with all instructions

The six registers are:

Input register

Contains information at the pins

Contains output information

Output register

Direction register

Interrupt flags

Controls direction

Indicates if interrupt(s) are pending

Contains input signal change necessary for interrupt

Contains interrupt enable pins

Interrupt edge select

Interrupt enable

All six registers contain eight bits except for the interrupt flag register and the interrupt enable register. The two

LSBsof the interrupt flag and interrupt enable registers are located in the special functions register (SFR). Three

interrupt vectors are implemented, one for Port0.0, one for Port0.1, and one commonly used for any interrupt

event on Port0.2 to Port0.7. The Port0.1 and Port0.2 pin function is shared with the 8-Bit Timer/Counter.

10

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MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

LCD drive

Liquid crystal displays (LCDs) for static, 2-, 3- and 4-MUX operations can be driven directly. The controller LCD

logic operation is defined by software using memory-bit manipulation. LCD memory is part of the LCD module,

not part of data memory. Eight mode and control bits define the operation and current consumption of the LCD

drive. The information for the individual digits can be easily obtained using table programming techniques

combined with the correct addressing mode. The segment information is stored in LCD memory using

instructions for memory manipulation.

The drive capability is mainly defined by the external resistor divider that supports the analog levels for 2-, 3-

and 4-MUX operation. Groups of the LCD segment lines can be selected for digital output signals. The

MSP430x32x configuration has four common signal lines and 21 segment lines.

A/D converter

The analog-to-digital converter (ADC) is a cascaded converter type that converts analog signals from V

to

CC

GND. It is a 12+2 bit converter with a software or automatically-controlled range select. Five inputs can be

selected for analog or digital function. A ratiometric current source can be used on four of the analog pins. The

current is adjusted by an external resistor and is enabled/disabled by bits located in the control registers. The

conversion is started by setting the start-of-conversion bit (SOC) in the control register and the

end-of-conversions sets the interrupt flag. The analog input signal is sampled starting with SOC during the next

twelve MCLK clock pulses. The power-down bit in the control register controls the operating mode of the ADC

peripheral. The current consumption and operation is stopped when it is set. The system reset PUC sets the

power-down bit.

Basic Timer1

The Basic Timer1 (BT1) divides the frequency of MCLK or ACLK, as selected with the SSEL bit, to provide low

frequency control signals. This is done within the system by one central divider, the Basic Timer1, to support

low current applications. The BTCTL control register contains the flags which control or select the different

operational functions. When the supply voltage is applied or when a reset of the device (RST/NMI pin), a

watchdog overflow or a watchdog security key violation occurs, and all bits in the register hold undefined or

unchanged status. The user software usually configures the operational conditions on the BT1 during

initialization.

The Basic Timer1 has two 8-Bit timers which can be cascaded to a 16-bit timer. Both timers can be read and

written by software. Two bits in the SFR address range handle the system control interaction according to the

function implemented in the Basic Timer1. These two bits are the Basic Timer1 interrupt flag (BTIFG) and the

Basic Timer1 interrupt enable (BTIE) bit.

Watchdog Timer

The primary function of the Watchdog Timer (WDT) module is to perform a controlled system restart after a

software upset has occurred. If the selected time interval expires, a system reset is generated. If this watchdog

function is not needed in an application, the module can work as an interval timer, which generates an interrupt

after the selected time interval.

The Watchdog Timer counter (WDTCNT) is a 15/16-bit up-counter which is not directly accessible by software.

The WDTCNT is controlled using the Watchdog Timer control register (WDTCTL), which is an 8-Bit read/write

register. Writing to WDTCTL, in both operating modes (watchdog or timer) is only possible by using the correct

password in the high-byte. The low-byte stores data written to the WDTCTL. The high-byte password is 05Ah.

If any value other than 05Ah is written to the high-byte of the WDTCTL, a system reset PUC is generated. When

the password is read its value is 069h. This minimizes accidental write operations to the WDTCTL register. In

addition to the Watchdog Timer control bits, two bits included in the WDTCTL configure the NMI pin.

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

8-Bit Timer/Counter

The 8-Bit interval timer supports three major functions for the application:

Serial communication or data exchange

Pulse counting or pulse accumulation

Timer

The 8-Bit Timer/Counter peripheral includes the following major blocks: an 8-Bit up-counter with preload

register, an 8-Bit control register, an input clock selector, an edge detection (e.g. Start bit detection for

asynchronous protocols), and an input and output data latch, triggered by the carry-out-signal from the 8-Bit

counter.

The 8-Bit counter counts up with an input clock which is selected by two control bits from the control register.

The four possible clock sources are MCLK, ACLK, the external signal from terminal P0.1, and the signal from

the logical AND of MCLK and terminal P0.1.

Two counter inputs (load, enable) control the counter operation. The load input controls load operations. A

write-access to the counter results in loading the content of the preload register into the counter. The software

writes or reads the preload register with all instructions. The preload register acts as a buffer and can be written

immediately after the load of the counter is completed. The enable input enables the count operation. When

the enable signal is set to high, the counter will count-up each time a positive clock edge is applied to the clock

input of the counter.

Serial protocols, like UART protocol, need start-bit edge-detection to determine, at the receiver, the start of a

data transmission. When this function is activated, the counter starts counting after the start-bit condition is

detected. The first signal level is sampled into the RXD input data-latch after completing the first timing interval,

which is programmed into the counter. Two latches are used for input and output data (RXD_FF and TXD_FF)

are clocked by the counter after the programmed timing interval has elapsed.

UART

The serial communication uses software and the 8-Bit Timer/Counter hardware. The hardware supports the

output of the serial data stream, bit-by-bit, with the timing determined by the counter. The software/hardware

interface connects the mixed signal controller to external devices, systems, or networks.

Timer/Port

The Timer/Port module has two 8-Bit counters, an input that triggers one counter, and six 3-state digital outputs.

Both counters have an independent clock-selector for selecting an external signal or one of the internal clocks

(ACLK or MCLK). One of the counters has an extended control capability to halt, count continuously, or gate

the counter by selecting one of two external signals. This gate signal sets the interrupt flag, if an external signal

is selected, and the gate stops the counter.

Both timers can be read from and written to by software. The two 8-Bit counters can be cascaded to a 16-bit

counter. A common interrupt vector is implemented. The interrupt flag can be set from three events in the 8-Bit

counter mode (gate signal, overflow from the counters) or from two events in the 16-bit counter mode (gate

signal, overflow from the MSB of the cascaded counter).

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

†

absolute maximum ratings

Voltage applied at V

to V (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V

SS

CC

Voltage applied to any pin (referenced to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V

+ 0.3 V

SS

CC

Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 2 mA

Storage temperature,T (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C

stg

T

(programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 5: All voltage values relative to V

.

SS

recommended operating conditions

MIN

NOM

MAX

UNIT

Supply voltage, V

CC

(MSP430P/E325)

2.7

5.5

V

Supply voltage, during programming OTP/EPROM

(AV = DV = V

MSP430P325, PMS430E325

2.7

5

0

5.5

V

)

CC

SS

Supply voltage, V

MSP430P325

PMS430E325

–40

85

Operating free-air temperature range, T

°C

Hz

A

25

XTAL frequency, f

(XTAL)

32 768

V

= 3 V

= 5 V

DC

2.2

3.3

CC

Processor frequency (signal MCLK), f

MHz

(system)

CC

Low-level input voltage, V (excluding Xin, Xout)

V

+0.8

IL

SS

V

High-level input voltage, V (excluding Xin, Xout)

IH

0.7 V

V

CC

V

CC

= 3 V/5 V

Low-level input voltage, V

V

SS

0.2×V

IL(Xin, Xout)

IH(Xin, Xout)

High-level input voltage, V

0.8×V

V

CC

f(MHz)

3.3

2.2

1.5

Minimum

2.7

3

5

5.5

V

CC

(V)

V

CC

– Supply Voltage – V

NOTE: Minimum processor frequency is defined by system clock.

Figure 1. Processor Frequency vs Supply Voltage

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

supply current into AV +DV

CC

excluding external current, f

= 1 MHz

system

CC

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

T

= –40°C to 85°C,

= –40°C

V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

3000

5000

Active mode, A/D conversion in

power-down

A

CC

I

P325

µA

(AM)

T

A

10000 12000

T

A

70

150

6

110

200

12

25

2.4

2

Low power mode, (LPM0, LPM1)

Low power mode, (LPM2)

µA

(CPUOff)

(LPM2)

T

A

T

A

T

A

15

T

A

1.5

1.3

1.6

5.2

4.2

4

T

A

= 25°C

V

CC

V

CC

V

CC

= 3 V

T

A

= 85°C

2.8

7

I

Low power mode, (LPM3)

Low power mode, (LPM4)

µA

(LPM3)

T

A

= –40°C

T

A

= 25°C

= 5 V

6.5

7

T

A

= 85°C

T

A

= –40°C

0.1

0.4

0.8

1.3

I

T

A

= 25°C

= 3 V/5 V

µA

(LPM4)

T

A

= 85°C

NOTE: All inputs are tied to 0 V or V . Outputs do not source or sink any current. The current consumption in LPM2, LPM3 and LPM4 are

CC

measured with active Basic Timer1 (ACLK selected) and LCD module (f

=1024 Hz, 4 MUX).

(LCD)

current consumption of active mode versus system frequency

= I × f [MHz]

I

AM

AM[1 MHz]

system

current consumption of active mode versus supply voltage

= I + 200 µA/V × (V –3 V)

I

AM

AM[3 V]

CC

Schmitt-trigger inputs Port 0, P0.x Timer/Port, CIN, TP 0.5

PARAMETER

TEST CONDITIONS

MIN

1.2

2.3

0.5

1.4

0.3

0.6

TYP

MAX

2.1

3.4

1.35

2.3

1

UNIT

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

V

IT+

V

IT–

V

hys

Positive-going input threshold voltage

Negative-going input threshold voltage

V

Hysteresis (V –V

)

IT+ IT–

1.4

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

outputs – Port 0: P0.x; Timer/Port: TP0.0...5; LCD: Sxx/Oxx; XBUF, (see Note 6)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I

= –1.2 mA,

= –3.5 mA,

= –1.5 mA,

= –4.5 mA,

= 1.2 mA,

= 3.5 mA,

= 1.5 mA,

= 4.5 mA,

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 3 V,

= 5 V,

= 3 V,

= 5 V,

See Note 6

See Note 7

See Note 6

See Note 7

See Note 6

See Note 7

See Note 6

See Note 7

V

–0.4

V

OH

OL

CC

V

–1

CC

V

High-level output current

V

OH

OL

V

CC

–0.4

V

–1

CC

V

SS

V

SS

V

SS

V

SS

V

+0.4

SS

V

+1

SS

V

Low-level output voltage

V

+0.4

SS

V

+1

SS

NOTES: 6. The maximum total current, I

voltage drop specified.

max and I max, for all outputs combined, should not exceed ±9.6 mA to satisfy the maximum

OL

OH

7. Themaximumtotalcurrent,I

drop specified.

maxandI max,foralloutputscombined,shouldnotexceed±20mAtosatisfythemaximumvoltage

OL

OH

leakage current (see Note 8)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Timer/Port:V

(see Note 9)

)

(TP0.x,CIN

I

Leakage current, Timer/Port

±50

nA

lkg(TP)

Port 0: V

(P0.x)

(see Note 10)

I

Leakage current, port 0

Leakage current, S20

Leakage current, ADC

Leakage current, RST/NMI

±50

±30

±50

nA

lkg(P0x)

V

CC

= 3 V/5 V

V

(S20)

= V

to V

SS CC

lkg(S20)

ADC: Ax, x= 0 to 5

(see Note 11)

lkg(Ax)

lkg(RST/NMI)

NOTES: 8. The leakage current is measured with V

SS

or V

applied to the corresponding pin(s), unless otherwise noted.

CC

9. All Timer/Port pins TP0.0 to TP0.5 are Hi-Z. Pins CIN and TP.0 to TP0.5 are connected together during leakage current

measurement. In the leakage measurement the input CIN is included. The input voltage is V or V

.

CC

SS

10. The port pin must be selected for input and there must be no optional pullup or pulldown resistor.

11. The input voltage is V = V to V , the current source is off, AEN.x bit is normally reset to stop throughput current flowing from

(IN)

terminal.

SS

CC

V

CC

to V

SS

input frequency – Port 0: P0.1; Timer/Port: CIN, TP0.5

PARAMETER

TEST CONDITIONS

MIN

DC

TYP

MAX

UNIT

MHz

ns

f

t

Input frequency

f

(system)

(IN)

P0.x, CIN, TP.5

3 V

5 V

300

125

or t

High level or low level time

(H)

(L)

ns

output frequency

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f

XBUF,

C

= 20 pF

f

MHz

XBUF

Xdc

L

(system)

60%

f

= 1.1 MHz

40%

35%

MCLK

C

= 20 pF,

L

t

Duty cycle of O/P frequency

= f

XBUF ACLK

65%

V

CC

= 3 V/5 V

= f

XBUF ACLK/n

50%

15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

external interrupt timing

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Port P0: External trigger signal for the

interrupt flag (see Notes 12 and 13)

t

1.5

cycle

(int)

NOTES: 12. The external signal sets the interrupt flag every time t

is met. It may be set even with trigger signals shorter than t

. The

(int)

conditions to set the flag must be met independently of this timing constraint. Input frequency (t

(int)

) is defined in MCLK cycles.

(int)

13. The external signal needs additionally a timing resulting from the maximum input frequency constraint.

RAM

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

CPU halted (see Note 14)

1.8

V

RAMh

NOTE 14: This parameter defines the minimum supply voltage when the data in the program memory RAM remains unchanged. No program

execution should take place during this supply voltage condition.

DCO

PARAMETER

TEST CONDITIONS

= 1A0h, FN_4=FN_3=FN_2=0

MIN

TYP

MAX

UNIT

f

DCO

N

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 3 V/5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

1

MHz

(NOM)

DCO

0.15

0.18

1.25

1.45

0.36

0.39

2.5

3

0.6

0.62

4.7

f

= 00 0110 0000, FN_4=FN_3=FN_2=0

= 11 0100 0000 FN_4=FN_3=FN_2=0

= 00 0110 0000, FN_4=FN_3=0, FN_2=1

= 11 0100 0000, FN_4=FN_3=0, FN_2=1

= 00 0110 0000, FN_4=0, FN_3= 1, FN_2=X

= 11 0100 0000, FN_4= 0, FN_3=1, FN_2=X

= 00 0110 0000 FN_4 =1, FN_3=FN_2=X

= 11 0100 0000, FN_4=1, FN_3=FN_2=X

DCO3

DCO26

DCO3

DC26

f

MHz

(NOM)

N

DCO

5.5

1.05

1.2

2xf

3xf

4xf

(NOM)

8.1

9.9

0.5

0.6

3.7

4.5

0.7

0.8

4.8

6

1.5

DCO3

DCO26

DCO3

DCO26

1.8

11

13.8

1.85

2.4

13.3

17.7

N

S

f

= f

MCLK NOM

,

FN_4=FN_3=FN_2=0

NDCO

V

= 3 V/5 V

A0h 1A0h

1.07

340h

1.13

DCO

CC

f

= S × f

V

NDCO+1

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

f

(DCO26)

4xf

3xf

NOM

f

(DCO26)

f

(DCO3)

Legend

NOM

f

(DCO26)

f

(DCO3)

2xf

f

NOM

Tolerance at Tap 26

f

(DCO26)

DCO Frequency

Adjusted by Bits

2 9–2 5 in SCFI1

f

(DCO3)

NOM

Tolerance at Tap 3

f

(DCO3)

FN_2 = 0

FN_3 = 0

FN_4 = 0

FN_2 = 1

FN_3 = 0

FN_4 = 0

FN_2 = X

FN_3 = 1

FN_4 = 0

FN_2 = X

FN_3 = X

FN_4 = 1

Figure 2

crystal oscillator

PARAMETER

Integrated capacitance at input

TEST CONDITIONS

MIN NOM

MAX

UNIT

pF

C

V

= 3 V/5 V

12

(Xin)

CC

Integrated capacitance at output

pF

(Xout)

CC

PUC/POR

PARAMETER

TEST CONDITIONS

MIN NOM

MAX

250

2.4

UNIT

µs

V

t

150

(POR_delay)

T

= –40°C

= 25°C

= 85°C

1.5

1.2

0.9

0

A

V

POR

T

A

2.1

V

(POR)

V

CC

= 3 V/5 V

T

A

1.8

V

(min)

0.4

V

t

PUC/POR

Reset is accepted internally

2

µs

(reset)

V

VCC

V

(POR)

No POR

POR

V

(min)

t

Figure 3. Power-On Reset (POR) vs Supply Voltage

17

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

3

2.4

2.5

2

2.1

1.8

MAX

1.5

1

MIN

0.9

1.2

0.5

25°C

0

–40

–20

0

20

40

60

80

Temperature [°C]

Figure 4. V

vs Temperature

(POR)

LCD

PARAMETER

TEST CONDITIONS

<= 10 nA

MIN

–0.125

TYP

MAX

UNIT

V

Output 1 (HLCD)

I

V

CC

V

O(HLCD)

(HLCD)

CC

+0.125

V

= 3 V/5 V

V

CC

Output 0 (LLCD)

Input leakage

Resistance

<= 10 nA

V

SS

V

SS

O(LLCD)

(LLCD)

R03 = V

SS,

I

I(R03)

I(R13)

I(R23)

No load at all seg and com pins

R13 = V / 3,

CC

No load at all seg and com pins

V

= 3 V/5 V

±20

nA

CC

R23 = 2 V / 3,

CC

No load at all seg and com pins

r

I

= –3 µA,

50

kΩ

o(Rx3 to Sxx)

(SXX)

CC

comparator (Timer/Port)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

350

UNIT

µA

V

CC

V

CC

V

CC

V

CC

V

CC

= 3 V

250

450

I

Comparator (Timer/Port)

CPON = 1

(com)

= 5 V

600

V

Internal reference voltage at (–) terminal

Input hysteresis (comparator)

= 3 V/5 V

= 3 V

0.23×V

0.25×V

5

0.26×V

37

V

ref(com)

CC

V

mV

hys(com)

=5 V

10

42

wake-up LPM3

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

CC

V

CC

V

CC

V

CC

V

CC

= 3 V

f = 1 MHz

6

= 5 V

= 3 V

= 5 V

t

Delay time

µs

(LPM3)

f = 2 MHz

f = 3 MHz

6

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

ADC supply current (f

= 1 MHz)

(ADCLK)

PARAMETER

TEST CONDITIONS

MIN NOM

200

MAX

400

UNIT

µA

I

SV

on, current source off,

V

= 3 V

= 5 V

(ADC)

CC

ADC current

SV

300

740

µA

(ADC)

CC

SV

(switched AV

)

CC

PARAMETER

TEST CONDITIONS

= –8 mA,

MIN

–0.2 V

NOM

MAX

UNIT

V

SV

on,

I

V

= 2.5 V

= 5 V

CC

V

CC

V

CC

(SVCC)

CC

(SVCC)

off, SV = 0 V,

CC

I

V

±0.1

µA

(SVCC)

CC

= 3 V/5 V

Z

Input impedance

off,

V

40

100

kΩ

(SVCC)

CC

current source (ADC)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

= V

= 6 mA,

– V

V

= 3 V/5 V,

0.246 ×

(SVCC)

95

0.249 ×

0.252 ×

(SVCC)

1600

(Rext)

(SVCC)

(RI),

CC

V

Voltage, (Rext)

External resistor

(Rext)

I

V

(RI)

(SVCC)

R

V

= 3 V/5 V

= 3 V,

Ω

(ext)

CC

VA0..A3 = 0 .. 0.4 × V

, I

,

=

S

(SVCC)

CC

–1

–3.2

–1.5

–3.2

1

3.2

1.5

3.2

µA

V

/R = 1 mA

(Rext) (ext)

VA0..A3 = 0 .. 0.4 × V

= V /R

V

CC

V

CC

V

CC

= 3 V,

= 5 V,

(SVCC)

µA

I

S

= 6 mA

(Rext) (ext)

∆I

S

Load compliance

VA0..A3 = 0 .. 0.5 × V

(SVCC)

I

S

= V

/R

= 1 mA

(Rext) (ext)

VA0..A3 = 0 .. 0.5 × V

= V /R

(SVCC)

I

S

= 6 mA

(Rext) (ext)

19

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

A/D converter (f

= 1 MHz)

(ADCLK)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

12 + 2

bits

12-bit conversion

12+2-bit conversion

12-bit conversion

0.1

1.5

f

Conversion frequency

Conversion cycles

f

= f

(con) (ADCLK)

V

= 3 V/5 V

MHz

(con)

CC

0.14

96

cycles of

ADCLK

f

= f

/N

(concyc)

(ADCLK) (MCLK)

CC

12+2-bit conversion

132

LSB Voltage

V

= 3 V/5 V

0.000061×V

SVCC

V

CC

INL

0 ≤ DDV ≤ 127

–2

–3

2

3

LSB

1

2

3

4

128 ≤ DDV ≤ 255

256 ≤ DDV ≤ 2047

2048 ≤ DDV ≤ 4095

Integral nonlinearity

(see Note 15)

–7

7

–10

10

Differential nonlinearity

(see Note 16)

DNL

V

= 3 V/5 V

–1

1

LSB

CC

V

/R

= 6mA, Range A

0.008

0.015

(Rext) (ext)

Temperature stability

V

= 3 V/5 V

dN/dT

dN/dV

LSB/°C

LSB/V

CC

Range B

Range A, B, V

SV

CC

/R = 1 mA,

(Rext) (ext)

CC

V

rejection ratio

1.25

0.24

0.49

0.6

(SVCC)

±10%

% FSR

(see Note 18)

A

Range A

V

= 3 V/5 V

–1.2

–1.7

–0.49

–0.6

0.6

CC

% FSR

(see Note 18)

B

Range B

Conversion offset 12 bit analog input to

digital value (see Note 17)

% FSR

(see Note 18)

C

Range C

Range D

Range ABCD

–1.8

% FSR

(see Note 18)

D

–1.7

0.49

0.13

Conversion offset 14 bit analog input to

digital value (see Note 17)

%FSR

(see Note 18)

ABCD

–0.27

–0.06

Slope 12 bit

Slope 14 bit

V

= 3 V/5 V

0.9925

0.9982

1

1.0075

1.0018

CC

C

R

Input capacitance

V

= 3 V/5 V

40

2

45

pF

(IN)

CC

Serial input resistance

kΩ

(SIN)

CC

NOTES: 15. DDV is short form of delta digital value. The DDV is a span of conversion results. It is assumed that the conversion is of 12 bit not

12+2 bit.

16. DNL is valid for all 12-bit ranges and the 14-bit (12+2) range.

17. Offset referred to full scale 12/14 bit

18. FSRx: full scale range, separate for the four 12-bit ranges and the 14-bit (12+2) range.

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

JTAG

PARAMETER

TEST CONDITIONS

MIN

DC

TYP

MAX

5

UNIT

V

= 3 V

= 5 V

CC

f

TCK frequency

MHz

(TCK)

10

CC

JTAG/test

Pullup resistors on TMS, TCK, TDI

(see Note 19)

R

V

= 3 V/ 5 V

25

11

60

90

12

kΩ

(TEST)

CC

Fuse blow voltage, E/P versions

(see Note 21)

V

(FB)

V

JTAG/fuse (see Note 20)

I

t

Supply current on TDI to blow fuse

Time to blow the fuse

100

1

mA

ms

V

(FB)

V

Programming voltage, applied to TDI/VPP

Current from programming voltage source

Programming time, single pulse

11

5

11.5

100

13

70

(PP)

(pps)

(ppf)

I

t

mA

ms

µs

EPROM (E) and OTP(P) –

versions only

Programming time, fast algorithm

Number of pulses for successful programming

P

4

100 Pulses

year

n

Data retention T < 55°C

10

J

2

Erase time wave length 2537 Å at 15 Ws/cm

(UV lamp of 12 mW/ cm )

t

30

min

(erase)

2

EPROM (E) versions only

Write/Erase cycles

1000

cycles

NOTES: 19. The TMS and TCK pullup resistors are implemented in all C-, P-, and E-versions.

20. Once the JTAG fuse is blown, no further access to the MSP430 JTAG/test feature is possible. The JTAG block switches to by-pass

mode.

21. The voltage supply to blow the JTAG fuse is applied to TDI/VPP pin when fuse blowing is desired.

21

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

TYPICAL CHARACTERISTICS

DIGITAL CONTROLLED OSCILLATOR FREQUENCY

vs

SUPPLY VOLTAGE

1.2

OPERATING FREE-AIR TEMPERATURE

1.8

1.5

1.2

0.9

1

0.8

0.6

0.4

0.3

0

0.2

0

–40

–20

0

20

40

60

80

90

0

2

4

6

V

CC

– Supply Voltage – V

T – Operating Free-Air Temperature – °C

Figure 5

Figure 6

22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

TYPICAL CHARACTERISTICS

typical input/output schematics

V

CC

V

CC

(see Note A)

(see Note B)

(see Note A)

GND

(see Note A)

GND

CMOS INPUT (RST/NMI)

CMOS SCHMITT-TRIGGER INPUT (CIN)

V

CC

(see Note A)

(see Note B)

(see Note A)

GND

I/O WITH SCHMITT-TRIGGER INPUT (P0.x, TP5)

CMOS 3-STATE OUTPUT (TP0–4, XBUF)

TDO_Internal

V

CC

TDO_Control

TDI_Control

60 k TYP

TDI_Internal

MSP430P/E325: TMS, TCK

MSP430P/E325: TDO/TDI

NOTES: A. Optionalselection of pullup or pulldown resistors with ROM (masked) versions. Anti-parallel diodes are connected between AV

SS

and DV

.

SS

B. Fuses for the optional pullup and pulldown resistors can only be programmed at the factory.

23

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

TYPICAL CHARACTERISTICS

typical input/output schematics

VC

VD

COM 0–3

Control COM0–3

VA

S0, S1

VB

Segment control

VA

VB

S2/O2–Sn/On

Segment control

LCDCTL (LCDM5,6,7)

Data (LCD RAM bits 0–3

or bits 4–7)

LCD OUTPUT (COM0–4, Sn, Sn/On)

NOTE: The signals VA, VB, VC, and VD come from the LCD module analog voltage generator.

VPP_ Internal

TDI_ Internal

TDI/VPP

JTAG

Fuse

TDO/TDI_Control

TDO/TDI

TMS

TDO_ Internal

JTAG Fuse

Blow

Control

From/To JTAG_CBT_SIG_REG

NOTES: A. During programming activity and when blowing the JTAG enable fuse, the TDI/VPP terminal is used to apply the correct voltage

source. The TDO/TDI terminal is used to apply the test input data for JTAG circuitry.

B. The TDI/VPP terminal of the ’P325 and ’E325 does not have an internal pullup resistor. An external pulldown resistor is

recommended to avoid a floating node which could increase the current consumption of the device.

C. The TDO/TDI terminal is in a high-impedance state after POR. The ’P325 and ’E325 needs a pullup or a pulldown resistor to avoid

floating a node which could increase the current consumption of the device.

Figure 7. MSP430P325/E325: TDI/VPP, TDO/TDI

24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

TYPICAL CHARACTERISTICS

JTAG fuse check mode

MSP430 devices that have the fuse on the TDI/VPP terminal have a fuse check mode that tests the continuity

of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check

current, I , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/VPP pin to ground if the fuse is not burned.

TF

Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power

consumption.

Activation of the fuze check mode occurs with the first negative edge on the TMS pin after power-up or if TMS

is being held low during power-up. The second positive edge on the TMS pin deactivates the fuse check mode.

After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse

check mode has the potential to be activated.

Time TMS Goes Low After POR

TMS

I

TF

I

TDI

Figure 8. Fuse Check Mode Current, MSP430P/E325

Care must be taken to avoid accidentally activating the fuse check mode, including guarding against EMI/ESD

spikes that could cause signal edges on the TMS pin.

Configuration of TMS, TCK, TDI/VPP and TDO/TDI pins in applications.

P/E3xx

TDI

TDO

TMS

TCK

68k, pulldown

Open

25

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

MECHANICAL DATA

PG (R-PQFP-G64)

PLASTIC QUAD FLATPACK

0,45

0,25

M

0,20

1,00

51

33

52

32

14,20 18,00

13,80 17,20

12,00 TYP

64

20

1

19

0,15 NOM

18,00 TYP

20,20

19,80

24,40

23,60

Gage Plane

0,25

0,10 MIN

2,70 TYP

0°–10°

1,10

0,70

Seating Plane

3,10 MAX

0,10

4040101/B 03/95

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Contact field sales office to determine if a tighter coplanarity requirement is available for this package.

26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

MECHANICAL DATA

MSP430P325 (PM package)

PM PACKAGE

(TOP VIEW)

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

DV

CC

SV

CC

Rext

S19/O19

S18/O18

S17/O17

S16/O16

S15/O15

S14/O14

S13/O13

S12/O12

S11/O11

S10/O10

1

2

3

4

5

6

7

8

9

48

47

46

45

44

43

42

41

40

39

A2

A3

A4

A5

Xin

Xout/TCLK

CIN

10

TP0.0 11

TP0.1 12

TP0.2 13

38 S9/O9

37 S8/O8

36

35

34

33

S7/O7

S6/O6

S5/O5

S4/O4

14

15

16

TP0.3

TP0.4

TP0.5

1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32

27

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

MECHANICAL DATA

PM (S-PQFP-G64)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

M

0,08

33

48

49

32

64

17

0,13 NOM

1

16

7,50 TYP

Gage Plane

10,20

SQ

9,80

0,25

12,20

SQ

0,05 MIN

0°–7°

11,80

1,45

1,35

0,75

0,45

Seating Plane

1,60 MAX

0,08

4040152/C 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

D. May also be thermally enhanced plastic with leads connected to the die pads.

28

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

MECHANICAL DATA

MSP430P325 (FN package)

FN PACKAGE

(TOP VIEW)

9

8

7

6

5

4

3

2

1 68 67 66 65 64 63 62 61

60 S20/O20/CMPI

DV

SV

10

11

12

13

14

15

16

17

CC

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

S19/O19

S18/O18

S17/O17

S16/O16

S15/O15

S14/O14

S13/O13

S12/O12

S11/O11

S10/O10

S9/O9

Rext

A2

A3

A4

A5

Xin

Xout/TCLK 18

19

20

21

22

23

24

25

26

CIN

TP0.0

TP0.1

TP0.2

TP0.3

TP0.4

TP0.5

P0.0

S8/O8

S7/O7

S6/O6

S5/O5

S4/O4

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

NC – No internal connection

29

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

MECHANICAL DATA

FN (S-PQCC-J**)

PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane

0.004 (0,10)

0.180 (4,57) MAX

0.120 (3,05)

D

0.090 (2,29)

D1

0.020 (0,51) MIN

3

1

19

0.032 (0,81)

0.026 (0,66)

4

18

D2/E2

E

E1

8

14

0.021 (0,53)

0.013 (0,33)

0.050 (1,27)

9

13

0.007 (0,18)

M

0.008 (0,20) NOM

D/E

D1/E1

D2/E2

NO. OF

PINS

**

MIN

0.385 (9,78)

MAX

MIN

MAX

MIN

MAX

0.395 (10,03)

0.350 (8,89)

0.356 (9,04)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

20

28

44

52

68

84

0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)

0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)

0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)

0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)

1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)

4040005/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

30

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

PMS430E325 (FZ package)

FZ PACKAGE

(TOP VIEW)

9

8

7

6

5

4

3

2

1 68 67 66 65 64 63 62 61

60 S20/O20/CMPI

DV

SV

10

11

12

13

14

15

16

17

CC

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

S19/O19

S18/O18

S17/O17

S16/O16

S15/O15

S14/O14

S13/O13

S12/O12

S11/O11

S10/O10

S9/O9

rext

A2

A3

A4

A5

Xin

Xout/TCLK 18

19

20

21

22

23

24

25

26

CIN

TP0.0

TP0.1

TP0.2

TP0.3

TP0.4

TP0.5

P0.0

S8/O8

S7/O7

S6/O6

S5/O5

S4/O4

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

NC – No internal connection

31

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

MECHANICAL DATA

FZ (S-CQCC-J**)

J-LEADED CERAMIC CHIP CARRIER

28 LEAD SHOWN

0.040 (1,02)

45°

Seating Plane

0.180 (4,57)

0.155 (3,94)

0.140 (3,55)

0.120 (3,05)

A

B

1

4

26

25

5

0.050 (1,27)

C

(at Seating

Plane)

A

B

0.032 (0,81)

0.026 (0,66)

0.020 (0,51)

0.014 (0,36)

19

11

18

12

0.025 (0,64) R TYP

0.040 (1,02) MIN

0.120 (3,05)

0.090 (2,29)

A

B

C

JEDEC

NO. OF

PINS**

OUTLINE

MIN

MAX

MIN

MAX

MIN

MAX

0.485

0.495

0.430

0.455

0.410

0.430

MO-087AA

MO-087AB

MO-087AC

MO-087AD

28

44

52

68

(12,32)

(12,57)

(10,92)

(11,56)

(10,41)

(10,92)

0.685

0.695

0.630

0.655

0.610

0.630

(17,40)

(17,65)

(16,00)

(16,64)

(15,49)

(16,00)

0.785

0.795

0.730

0.765

0.680

0.740

(19,94)

(20,19)

(18,54)

(19,43)

(17,28)

(18,79)

0.985

0.995

0.930

0.955

0.910

0.930

(25,02)

(25,27)

(23,62)

(24,26)

(23,11)

(23,62)

4040219/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

32

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MPLC004A – OCTOBER 1994

FN (S-PQCC-J**)

PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane

0.004 (0,10)

0.180 (4,57) MAX

0.120 (3,05)

D

0.090 (2,29)

D1

0.020 (0,51) MIN

3

1

19

0.032 (0,81)

0.026 (0,66)

4

18

D2/E2

E

E1

8

14

0.021 (0,53)

0.013 (0,33)

0.050 (1,27)

9

13

0.007 (0,18)

M

0.008 (0,20) NOM

D/E

D1/E1

D2/E2

NO. OF

PINS

**

MIN

0.385 (9,78)

MAX

MIN

MAX

MIN

MAX

0.395 (10,03)

0.350 (8,89)

0.356 (9,04)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

20

28

44

52

68

84

0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)

0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)

0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)

0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)

1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)

4040005/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MQFP008 – JULY 1998

PG (R-PQFP-G64)

PLASTIC QUAD FLATPACK

0,45

0,25

M

0,20

1,00

51

33

52

32

14,20 18,00

13,80 17,20

12,00 TYP

64

20

1

19

0,15 NOM

18,00 TYP

20,20

19,80

24,00

23,20

Gage Plane

0,25

0,10 MIN

2,70 TYP

0°–10°

1,10

0,70

Seating Plane

3,10 MAX

0,10

4040101/B 03/95

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Contact field sales office to determine if a tighter coplanarity requirement is available for this package.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996

PM (S-PQFP-G64)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

M

0,08

33

48

49

32

64

17

0,13 NOM

1

16

7,50 TYP

Gage Plane

10,20

SQ

9,80

0,25

12,20

SQ

0,05 MIN

0°–7°

11,80

1,45

1,35

0,75

0,45

Seating Plane

0,08

1,60 MAX

4040152/C 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

D. May also be thermally enhanced plastic with leads connected to the die pads.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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型号：	MSP-STK430B320
厂家：	TEXAS INSTRUMENTS
描述：	MIXED SIGNAL MICROCONTROLLER 混合信号微控制器微控制器
文件：	总39页 (文件大小：576K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MSP-STK430B320 [TI]

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