MSP430BT5190_V01_技术文档

MSP430BT5190

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SLAS703C – APRIL 2010 – REVISED SEPTEMBER 2020

MSP430BT5190 Mixed-Signal Microcontroller

•

Unified clock system

1 Features

– FLL control loop for frequency stabilization

– Low-power low-frequency internal clock source

(VLO)

– Low-frequency trimmed internal reference

source (REFO)

•

Designed for use with CC2560 TI Bluetooth^®

based solutions

•

Commercially licensed Mindtree^™Ethermind

Bluetooth Stack for MSP430

– Bluetooth v2.1 + enhanced data rate (EDR)

compliant

– 32-kHz crystals

– High-frequency crystals up to 32 MHz

16-bit timer TA0, Timer_A with five capture/

compare registers

16-bit timer TA1, Timer_A with three capture/

compare registers

16-bit timer TB0, Timer_B with seven capture/

compare shadow registers

Up to four universal serial communication

interfaces (USCIs)

– Serial port profile (SPP)

– Sample applications

•

Low supply voltage range:

3.6 V down to 1.8 V

Ultra-low power consumption

– Active mode (AM):

all system clocks active

230 µA/MHz at 8 MHz, 3 V, flash program

execution (typical)

110 µA/MHz at 8 MHz, 3 V, RAM program

execution (typical)

– USCI_A0, USCI_A1, USCI_A2, and USCI_A3

each support:

•

Enhanced UART supports automatic baud-

rate detection

– Standby mode (LPM3):

real-time clock (RTC) with crystal, watchdog,

and supply supervisor operational, full RAM

retention, fast wakeup:

1.7 µA at 2.2 V, 2.1 µA at 3 V (typical)

low-power oscillator (VLO), general-purpose

counter, watchdog, and supply supervisor

operational, full RAM retention, fast wakeup:

1.2 µA at 3 V (typical)

•

IrDA encoder and decoder

Synchronous SPI

– USCI_B0, USCI_B1, USCI_B2, and USCI_B3

each support:

•

I²C

Synchronous SPI

•

12-bit analog-to-digital converter (ADC)

– Internal reference

– Off mode (LPM4):

full RAM retention, supply supervisor

operational, fast wakeup:

1.2 µA at 3 V (typical)

– 14 external channels, 2 internal channels

Hardware multiplier supports 32-bit operations

Serial onboard programming, no external

programming voltage needed

3-channel internal DMA

Basic timer with RTC feature

•

– Shutdown mode (LPM4.5):

0.1 µA at 3 V (typical)

Wake up from standby mode in less than 5 µs

16-bit RISC architecture

•

2 Applications

Flexible power-management system

– Fully integrated LDO with programmable

regulated core supply voltage

– Supply voltage supervision, monitoring, and

brownout

•

Remote Controls

Thermostats

Smart Meters

Blood Glucose Meters

Pulseoximeters

3 Description

The TI MSP430^™family of ultra-low-power microcontrollers consists of several devices featuring different sets of

peripherals targeted for various applications. The architecture, combined with extensive low-power modes, is

optimized to achieve extended battery life in portable measurement applications. The device features a powerful

16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to active mode in less

than 5 µs.

MSP430BT5190 is a microcontroller configuration with three 16-bit timers, a high-performance 12-bit ADC, four

USCIs, a hardware multiplier, DMA, an RTC module with alarm capabilities, and 87 I/O pins.

The MSP430BT5190 microcontroller is designed for commercial use with TI’s CC2560 based Bluetooth solutions

in conjunction with Mindtree’s Ethermind Bluetooth stack and SPP. This MSP430BT5190+CC2560 Bluetooth

platform is ideal for applications that need a wireless serial link for cable replacement, such as remote controls,

thermostats, smart meters, blood glucose meters, pulseoximeters, and many others.

For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide

Device Information

PART NUMBER⁽¹⁾

MSP430BT5190IPZ

PACKAGE

BODY SIZE⁽²⁾

14 mm × 14 mm

7 mm × 7 mm

LQFP (100)

MSP430BT5190IZCA

nFBGA (113)

MSP430BT5190IZQW⁽³⁾

MicroStar Junior^™BGA (113)

(1) For the most current part, package, and ordering information, see the Package Option Addendum

in Section Mechanical, Packaging, and Orderable Information, or see the TI website at www.ti.com.

(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the

Mechanical Data in Section Mechanical, Packaging, and Orderable Information.

(3) All orderable part numbers in the ZQE (MicroStar Junior BGA) package have been changed to a

status of Last Time Buy. Visit the Product life cycle page for details on this status.

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4 Functional Block Diagram

Figure 4-1 shows the functional block diagram.

PA

PB

PC

PD

PE

PF

P11.x

XIN XOUT

DVCC DVSS AVCC AVSS

RST/NMI

P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x P10.x

XT2IN

I/O Ports

ACLK

Power

Management

I/O Ports

P3/P4

2×8 I/Os

I/O Ports

P5/P6

2×8 I/Os

I/O Ports

P7/P8

2×8 I/Os

I/O Ports

P9/P10

2×8 I/Os

I/O Ports

P11

1×3 I/Os

Unified

Clock

System

P1/P2

2×8 I/Os

Interrupt

Capability

256KB

Flash

16KB

RAM

XT2OUT

SYS

SMCLK

LDO

SVM/SVS

Brownout

Watchdog

PB

1×16 I/Os

PC

1×16 I/Os

PD

1×16 I/Os

PE

1×16 I/Os

PF

1×3 I/Os

PA

1×16 I/Os

MCLK

MAB

MDB

CPUXV2

and

Working

Registers

DMA

3 Channel

EEM

(L: 8+2)

ADC12_A

USCI0,1,2,3

12 Bit

200 KSPS

TA0

TA1

TB0

USCI_Ax:

UART,

IrDA, SPI

JTAG/

SBW

Interface

RTC_A

MPY32

CRC16

REF

Timer_A

5 CC

Registers

Timer_A

3 CC

Registers

Timer_B

7 CC

Registers

16 Channels

(14 ext/2 int)

Autoscan

UCSI_Bx:

SPI, I2C

Figure 4-1. Functional Block Diagram

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Functional Block Diagram.............................................. 3

5 Revision History.............................................................. 4

6 Terminal Configuration and Functions..........................7

6.1 Pin Diagrams.............................................................. 7

6.2 Signal Descriptions..................................................... 9

7 Specifications................................................................ 14

7.1 Absolute Maximum Ratings...................................... 14

7.2 ESD Ratings............................................................. 14

7.3 Recommended Operating Conditions.......................14

7.4 Active Mode Supply Current Into V_CCExcluding

7.27 Wake-up Times From Low-Power Modes and

Reset...........................................................................28

7.28 Timer_A...................................................................29

7.29 Timer_B...................................................................29

7.30 USCI (UART Mode), Recommended Operating

Conditions................................................................... 29

7.31 USCI (UART Mode)................................................ 29

7.32 USCI (SPI Master Mode), Recommended

Operating Conditions...................................................30

7.33 USCI (SPI Master Mode)........................................ 30

7.34 USCI (SPI Slave Mode).......................................... 32

7.35 USCI (I²C Mode).....................................................34

7.36 12-Bit ADC, Power Supply and Input Range

External Current.......................................................... 15

Conditions................................................................... 35

7.37 12-Bit ADC, Timing Parameters..............................35

7.38 12-Bit ADC, Linearity Parameters...........................35

7.39 12-Bit ADC, Temperature Sensor and Built-In

7.5 Low-Power Mode Supply Currents (Into V_CC

)

Excluding External Current..........................................16

7.6 Thermal Characteristics............................................16

7.7 Schmitt-Trigger Inputs – General-Purpose I/O .........17

7.8 Inputs – Ports P1 and P2..........................................17

7.9 Leakage Current – General-Purpose I/O..................17

7.10 Outputs – General-Purpose I/O (Full Drive

Strength)......................................................................17

7.11 Outputs – General-Purpose I/O (Reduced Drive

Strength)......................................................................18

7.12 Output Frequency – General-Purpose I/O..............18

7.13 Typical Characteristics – Outputs, Full Drive

V_MID............................................................................36

7.40 REF, External Reference........................................ 37

7.41 REF, Built-In Reference.......................................... 38

7.42 Flash Memory......................................................... 39

7.43 JTAG and Spy-Bi-Wire Interface.............................39

8 Detailed Description......................................................40

8.1 CPU.......................................................................... 40

8.2 Operating Modes...................................................... 41

8.3 Interrupt Vector Addresses....................................... 42

8.4 Memory Organization................................................44

8.5 Bootstrap Loader (BSL)............................................ 44

8.6 JTAG Operation........................................................ 45

8.7 Flash Memory........................................................... 46

8.8 RAM..........................................................................46

8.9 Peripherals................................................................47

8.10 Input/Output Schematics.........................................68

8.11 Device Descriptors (TLV)........................................ 92

9 Device and Documentation Support............................95

9.1 Device Support......................................................... 95

9.2 Documentation Support............................................ 98

9.3 Support Resources................................................... 98

9.4 Trademarks...............................................................98

9.5 Electrostatic Discharge Caution................................98

9.6 Export Control Notice................................................98

9.7 Glossary....................................................................98

Strength (PxDS.y = 1)................................................. 19

7.14 Typical Characteristics – Outputs, Reduced

Drive Strength (PxDS.y = 0)........................................20

7.15 Crystal Oscillator, XT1, Low-Frequency Mode .......21

7.16 Crystal Oscillator, XT1, High-Frequency Mode ......22

7.17 Crystal Oscillator, XT2............................................ 23

7.18 Internal Very-Low-Power Low-Frequency

Oscillator (VLO)...........................................................24

7.19 Internal Reference, Low-Frequency Oscillator

(REFO)........................................................................24

7.20 DCO Frequency......................................................24

7.21 PMM, Brown-Out Reset (BOR)...............................25

7.22 PMM, Core Voltage.................................................26

7.23 PMM, SVS High Side..............................................26

7.24 PMM, SVM High Side............................................. 27

7.25 PMM, SVS Low Side...............................................28

7.26 PMM, SVM Low Side..............................................28

5 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from revision B to revision C

Changes from August 7, 2015 to September 11, 2020

Page

•

Updated the numbering for sections, tables, figures, and cross-references throughout the document..............1

Added nFBGA package (ZXH) information throughout document......................................................................1

Added note about status change for all orderable part numbers in the ZQE package in Device Information ... 1

Changed the MAX value of the I_ERASEand I_MERASE, I_BANKparameters in Section 7.42, Flash Memory ......... 39

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Changes from revision A to revision B

Changes from August 5, 2013 to August 6, 2015

Page

•

Document format and organization changes throughout, including addition of section numbering ...................1

Added Device Information table..........................................................................................................................1

Moved functional block diagram to Figure 4-1, Functional Block Diagram ........................................................3

Added Section Device Characteristics, Device Characteristics, and moved Table 6-1 to it............................... 6

Added signal names to ZQW pinout...................................................................................................................7

Added Section 7.2, ESD Ratings .....................................................................................................................14

Added note to C_VCORE..................................................................................................................................... 14

Moved Section 7.6, Thermal Characteristics ...................................................................................................16

Changed the TYP value of C_L,effwith Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF.................21

Corrected spelling of MRG bits in symbol and description for f_MCLK,MRGparameter........................................ 39

Corrected spelling of NMIIFG in Table 8-6, System Module Interrupt Vector Registers ..................................49

Changed P5.3 schematic (added P5SEL.2 and XT2BYPASS inputs with AND and OR gates) ..................... 78

Changed P5SEL.3 column from X to 0 for "P5.3 (I/O)" rows............................................................................78

Changed P7.1 schematic (added P7SEL.1 input and OR gate).......................................................................83

Changed P7SEL.1 column from X to 0 for "P7.1 (I/O)" rows............................................................................83

Added Section 9 and moved Tools Support, Device Nomenclature, ESD Caution, and Trademarks sections to

it........................................................................................................................................................................95

Added Section Mechanical, Packaging, and Orderable Information ............................................................... 99

•

Changes from initial release to revision A

Added Applications, Development Tools Support, and Device and Development Tool Nomenclature sections.

Signal Descriptions table, Added note about pullup resistor to RST/NMI/SBWTDIO pin.

DMA Trigger Assignments table, Changed SYSRSTIV interrupt event at 1Ch to Reserved.

Recommended Operating Conditions, Added note about interaction between minimum VCC and SVS; Added

note about test conditions for typical values.

DCO Frequency, Added note (1).

12-Bit ADC, Temperature Sensor and Built-In VMID, Changed ADC12 tSENSOR(sample) MIN to 100 μs;

changed note (2).

Flash Memory, Changed I_ERASEand I_MERASE, I^BANKlimits.

Changed SLAU265 references to SLAU319 or SLAU320 as appropriate.

Editorial changes throughout.

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Device Characteristics

Table 6-1 summarizes the device characteristics.

Table 6-1. Device Characteristics

USCI

FLASH

(KB)

SRAM

(KB)

ADC12_A

(Ch)

DEVICE^{(1) (2)}

Timer_A⁽³⁾Timer_B⁽⁴⁾

I/O

PACKAGE

CHANNEL A: CHANNEL B:

UART, IrDA,

SPI

SPI, I²C

100 PZ,

113 ZQW

MSP430BT5190

256

16

5, 3

7

4

14 ext, 2 int

87

(1) For the most current part, package, and ordering information, see the Package Option Addendum in Section Mechanical, Packaging,

and Orderable Information, or see the TI website at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and

PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first

instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.

(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and

PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first

instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.

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6 Terminal Configuration and Functions

6.1 Pin Diagrams

Figure 6-1 shows the pinout of the 100-pin PZ package.

P6.4/A4

P6.5/A5

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

P9.7

2

P9.6

P6.6/A6

3

P9.5/UCA2RXDUCA2SOMI

P9.4/UCA2TXD/UCA2SIMO

P9.3/UCB2CLK/UCA2STE

P9.2/UCB2SOMI/UCB2SCL

P9.1/UCB2SIMO/UCB2SDA

P9.0/UCB2STE/UCA2CLK

P8.7

P6.7/A7

4

P7.4/A12

5

P7.5/A13

6

P7.6/A14

7

P7.7/A15

8

P5.0/A8/VREF+/VeREF+

P5.1/A9/VREF−/VeREF−

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

P8.6/TA1.1

AVCC

AVSS

P8.5/TA1.0

DVCC2

DVSS2

P7.0/XIN

VCORE

P7.1/XOUT

DVSS1

P8.4/TA0.4

P8.3/TA0.3

DVCC1

P8.2/TA0.2

P1.0/TA0CLK/ACLK

P1.1/TA0.0

P1.2/TA0.1

P1.3/TA0.2

P1.4/TA0.3

P1.5/TA0.4

P1.6/SMCLK

P1.7

P8.1/TA0.1

P8.0/TA0.0

P7.3/TA1.2

P7.2/TB0OUTH/SVMOUT

P5.7/UCA1RXD/UCA1SOMI

P5.6/UCA1TXD/UCA1SIMO

P5.5/UCB1CLK/UCA1STE

P5.4/UCB1SOMI/UCB1SCL

P2.0/TA1CLK/MCLK

Figure 6-1. 100-Pin PZ Package (Top View)

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Figure 6-2 shows the pinout of the 113-pin ZQW package.

P6.4

A1

P6.2

A2

RST

A3

PJ.1

A4

P5.3

A5

P5.2

A6

P11.2

A7

P11.0

A8

P10.6

A9

P10.4

A10

P10.1

A11

P9.7

A12

P6.6

B1

P6.3

B2

P6.1

B3

PJ.3

B4

PJ.0

B5

DVSS4 DVCC4 P10.7

P10.5

B9

P10.3

B10

P9.6

B11

P9.5

B12

B6

B7

B8

P7.5

C1

P6.7

C2

Reserved

C3

P9.4

C11

P9.2

C12

P5.0

D1

P7.6

D2

P6.0

D4

PJ.2

D5

TEST

D6

P11.1

D7

P10.2

D8

P10.0

D9

P9.0

D11

P8.7

D12

P5.1

E1

AVCC

E2

P6.5

E4

Reserved Reserved Reserved Reserved

P9.3

E9

P8.6

E11

DVCC2

E12

E5

E6

E7

E8

P7.0

F1

AVSS

F2

P7.4

F4

Reserved

F5

Reserved

F8

P9.1

F9

P8.5

F11

DVSS2

F12

P7.1

G1

DVSS1

G2

P7.7

G4

Reserved

G5

Reserved

G8

P8.3

G9

P8.4 VCORE

G11

G12

P1.0

H1

DVCC1

H2

P1.1

H4

Reserved Reserved Reserved

A8

H8

P8.0

H9

P8.1

H11

P8.2

H12

H5

H6

H7

P1.3

J1

P1.4

J2

P1.2

J4

P2.7

J5

P3.2

J6

P3.5

J7

P4.0

J8

P5.5

J9

P7.2

J11

P7.3

J12

P1.5

K1

P1.6

K2

P5.6

K11

P5.7

K12

P1.7

L1

P2.1

L2

P2.3

L3

P2.5

L4

P3.0

L5

P3.3

L6

P3.4

L7

P3.7

L8

P4.2

L9

P4.3

L10

P4.5

L11

P5.4

L12

P2.0

M1

P2.2

M2

P2.4

M3

P2.6

M4

P3.1

M5

DVSS3 DVCC3

M6

M7

P3.6

M8

P4.1

M9

P4.4

M10

P4.6

M11

P4.7

M12

Figure 6-2. 113-Pin ZQW Package (Top View)

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6.2 Signal Descriptions

Section 6.2.1 describes the signals.

6.2.1 Terminal Functions

TERMINAL

NO.

I/O⁽¹⁾

DESCRIPTION

NAME

PZ ZQW

General-purpose digital I/O

Analog input A4 – ADC

P6.4/A4

P6.5/A5

P6.6/A6

P6.7/A7

P7.4/A12

P7.5/A13

P7.6/A14

P7.7/A15

1

2

3

4

5

6

7

8

A1

E4

B1

C2

F4

C1

D2

G4

I/O

General-purpose digital I/O

Analog input A5 – ADC

General-purpose digital I/O

Analog input A6 – ADC

General-purpose digital I/O

Analog input A7 – ADC

General-purpose digital I/O

Analog input A12 –ADC

General-purpose digital I/O

Analog input A13 – ADC

General-purpose digital I/O

Analog input A14 – ADC

General-purpose digital I/O

Analog input A15 – ADC

General-purpose digital I/O

Analog input A8 – ADC

Output of reference voltage to the ADC

P5.0/A8/VREF+/VeREF+

P5.1/A9/VREF-/VeREF-

9

D1

E1

I/O

Input for an external reference voltage to the ADC

General-purpose digital I/O

Analog input A9 – ADC

Negative terminal for the ADC reference voltage for both sources, the internal

reference voltage, or an external applied reference voltage

10

AVCC

AVSS

11

12

E2

F2

Analog power supply

Analog ground supply

General-purpose digital I/O

Input terminal for crystal oscillator XT1

P7.0/XIN

13

14

F1

I/O

General-purpose digital I/O

Output terminal of crystal oscillator XT1

P7.1/XOUT

G1

DVSS1

DVCC1

15

16

G2

H2

Digital ground supply

Digital power supply

General-purpose digital I/O with port interrupt

P1.0/TA0CLK/ACLK

P1.1/TA0.0

17

18

19

H1

H4

J4

I/O TA0 clock signal TACLK input

ACLK output (divided by 1, 2, 4, 8, 16, or 32)

General-purpose digital I/O with port interrupt

I/O TA0 CCR0 capture: CCI0A input, compare: Out0 output

BSL transmit output

General-purpose digital I/O with port interrupt

I/O TA0 CCR1 capture: CCI1A input, compare: Out1 output

BSL receive input

P1.2/TA0.1

General-purpose digital I/O with port interrupt

TA0 CCR2 capture: CCI2A input, compare: Out2 output

P1.3/TA0.2

P1.4/TA0.3

P1.5/TA0.4

20

21

22

J1

J2

K1

I/O

General-purpose digital I/O with port interrupt

I/O

TA0 CCR3 capture: CCI3A input compare: Out3 output

General-purpose digital I/O with port interrupt

TA0 CCR4 capture: CCI4A input, compare: Out4 output

I/O

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TERMINAL

NO.

I/O⁽¹⁾

DESCRIPTION

NAME

PZ ZQW

General-purpose digital I/O with port interrupt

SMCLK output

P1.6/SMCLK

P1.7

23

24

K2

L1

I/O

I/O General-purpose digital I/O with port interrupt

General-purpose digital I/O with port interrupt

I/O TA1 clock signal TA1CLK input

MCLK output

P2.0/TA1CLK/MCLK

25

M1

General-purpose digital I/O with port interrupt

TA1 CCR0 capture: CCI0A input, compare: Out0 output

P2.1/TA1.0

P2.2/TA1.1

P2.3/TA1.2

26

27

28

L2

M2

L3

I/O

General-purpose digital I/O with port interrupt

TA1 CCR1 capture: CCI1A input, compare: Out1 output

I/O

General-purpose digital I/O with port interrupt

TA1 CCR2 capture: CCI2A input, compare: Out2 output

I/O

General-purpose digital I/O with port interrupt

RTCCLK output

P2.4/RTCCLK

P2.5

29

30

31

M3

L4

I/O

I/O General-purpose digital I/O with port interrupt

General-purpose digital I/O with port interrupt

I/O

P2.6/ACLK

M4

ACLK output (divided by 1, 2, 4, 8, 16, or 32)

General-purpose digital I/O with port interrupt

I/O Conversion clock output ADC

DMA external trigger input

P2.7/ADC12CLK/DMAE0

P3.0/UCB0STE/UCA0CLK

32

33

J5

L5

General-purpose digital I/O

Slave transmit enable – USCI_B0 SPI mode

Clock signal input – USCI_A0 SPI slave mode

I/O

Clock signal output – USCI_A0 SPI master mode

General-purpose digital I/O

P3.1/UCB0SIMO/UCB0SDA

P3.2/UCB0SOMI/UCB0SCL

34

35

M5

J6

I/O Slave in, master out – USCI_B0 SPI mode

I²C data – USCI_B0 I²C mode

General-purpose digital I/O

I/O Slave out, master in – USCI_B0 SPI mode

I²C clock – USCI_B0 I²C mode

General-purpose digital I/O

Clock signal input – USCI_B0 SPI slave mode

Clock signal output – USCI_B0 SPI master mode

P3.3/UCB0CLK/UCA0STE

36

L6

I/O

Slave transmit enable – USCI_A0 SPI mode

DVSS3

DVCC3

37

38

M6

M7

Digital ground supply

Digital power supply

General-purpose digital I/O

P3.4/UCA0TXD/UCA0SIMO

P3.5/UCA0RXD/UCA0SOMI

39

40

L7

J7

I/O Transmit data – USCI_A0 UART mode

Slave in, master out – USCI_A0 SPI mode

General-purpose digital I/O

I/O Receive data – USCI_A0 UART mode

Slave out, master in – USCI_A0 SPI mode

General-purpose digital I/O

Slave transmit enable – USCI_B1 SPI mode

Clock signal input – USCI_A1 SPI slave mode

Clock signal output – USCI_A1 SPI master mode

P3.6/UCB1STE/UCA1CLK

P3.7/UCB1SIMO/UCB1SDA

41

42

M8

L8

I/O

General-purpose digital I/O

I/O Slave in, master out – USCI_B1 SPI mode

I²C data – USCI_B1 I²C mode

General-purpose digital I/O

TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output

P4.0/TB0.0

P4.1/TB0.1

43

44

J8

I/O

General-purpose digital I/O

TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output

M9

I/O

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TERMINAL

NAME

NO.

I/O⁽¹⁾

DESCRIPTION

PZ ZQW

General-purpose digital I/O

TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output

P4.2/TB0.2

P4.3/TB0.3

P4.4/TB0.4

P4.5/TB0.5

P4.6/TB0.6

45

46

47

48

49

L9

I/O

General-purpose digital I/O

TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output

L10

General-purpose digital I/O

TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output

M10 I/O

General-purpose digital I/O

TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output

L11

I/O

General-purpose digital I/O

TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output

M11

General-purpose digital I/O

P4.7/TB0CLK/SMCLK

50

51

M12 I/O TB0 clock input

SMCLK output

General-purpose digital I/O

P5.4/UCB1SOMI/UCB1SCL

L12

J9

I/O Slave out, master in – USCI_B1 SPI mode

I²C clock – USCI_B1 I²C mode

General-purpose digital I/O

Clock signal input – USCI_B1 SPI slave mode

Clock signal output – USCI_B1 SPI master mode

P5.5/UCB1CLK/UCA1STE

52

I/O

Slave transmit enable – USCI_A1 SPI mode

General-purpose digital I/O

P5.6/UCA1TXD/UCA1SIMO

P5.7/UCA1RXD/UCA1SOMI

P7.2/TB0OUTH/SVMOUT

53

54

55

K11

K12

J11

I/O Transmit data – USCI_A1 UART mode

Slave in, master out – USCI_A1 SPI mode

General-purpose digital I/O

I/O Receive data – USCI_A1 UART mode

Slave out, master in – USCI_A1 SPI mode

General-purpose digital I/O

I/O Switch all PWM outputs high impedance – Timer TB0

SVM output

General-purpose digital I/O

TA1 CCR2 capture: CCI2B input, compare: Out2 output

P7.3/TA1.2

P8.0/TA0.0

P8.1/TA0.1

P8.2/TA0.2

P8.3/TA0.3

P8.4/TA0.4

56

57

58

59

60

61

J12

H9

I/O

General-purpose digital I/O

TA0 CCR0 capture: CCI0B input, compare: Out0 output

I/O

General-purpose digital I/O

TA0 CCR1 capture: CCI1B input, compare: Out1 output

H11

H12

G9

I/O

General-purpose digital I/O

TA0 CCR2 capture: CCI2B input, compare: Out2 output

I/O

General-purpose digital I/O

TA0 CCR3 capture: CCI3B input, compare: Out3 output

I/O

General-purpose digital I/O

TA0 CCR4 capture: CCI4B input, compare: Out4 output

G11

I/O

VCORE⁽²⁾

DVSS2

62

63

64

G12

F12

E12

Regulated core power supply output (internal use only, no external current loading)

Digital ground supply

Digital power supply

DVCC2

General-purpose digital I/O

TA1 CCR0 capture: CCI0B input, compare: Out0 output

P8.5/TA1.0

65

F11

I/O

General-purpose digital I/O

TA1 CCR1 capture: CCI1B input, compare: Out1 output

P8.6/TA1.1

P8.7

66

67

E11

D12

I/O

I/O General-purpose digital I/O

General-purpose digital I/O

Slave transmit enable – USCI_B2 SPI mode

Clock signal input – USCI_A2 SPI slave mode

P9.0/UCB2STE/UCA2CLK

68

D11

I/O

Clock signal output – USCI_A2 SPI master mode

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TERMINAL

NO.

I/O⁽¹⁾

DESCRIPTION

NAME

PZ ZQW

General-purpose digital I/O

P9.1/UCB2SIMO/UCB2SDA

P9.2/UCB2SOMI/UCB2SCL

69

70

F9

I/O Slave in, master out – USCI_B2 SPI mode

I²C data – USCI_B2 I²C mode

General-purpose digital I/O

C12

I/O Slave out, master in – USCI_B2 SPI mode

I²C clock – USCI_B2 I²C mode

General-purpose digital I/O

Clock signal input – USCI_B2 SPI slave mode

Clock signal output – USCI_B2 SPI master mode

P9.3/UCB2CLK/UCA2STE

71

E9

I/O

Slave transmit enable – USCI_A2 SPI mode

General-purpose digital I/O

P9.4/UCA2TXD/UCA2SIMO

P9.5/UCA2RXD/UCA2SOMI

72

73

C11

B12

I/O Transmit data – USCI_A2 UART mode

Slave in, master out – USCI_A2 SPI mode

General-purpose digital I/O

I/O Receive data – USCI_A2 UART mode

Slave out, master in – USCI_A2 SPI mode

P9.6

P9.7

74

75

B11

A12

I/O General-purpose digital I/O

General-purpose digital I/O

Slave transmit enable – USCI_B3 SPI mode

Clock signal input – USCI_A3 SPI slave mode

P10.0/UCB3STE/UCA3CLK

76

D9

I/O

Clock signal output – USCI_A3 SPI master mode

General-purpose digital I/O

P10.1/UCB3SIMO/UCB3SDA

P10.2/UCB3SOMI/UCB3SCL

77

78

A11

D8

I/O Slave in, master out – USCI_B3 SPI mode

I²C data – USCI_B3 I²C mode

General-purpose digital I/O

I/O Slave out, master in – USCI_B3 SPI mode

I²C clock – USCI_B3 I²C mode

General-purpose digital I/O

Clock signal input – USCI_B3 SPI slave mode

Clock signal output – USCI_B3 SPI master mode

P10.3/UCB3CLK/UCA3STE

79

B10

I/O

Slave transmit enable – USCI_A3 SPI mode

General-purpose digital I/O

P10.4/UCA3TXD/UCA3SIMO

P10.5/UCA3RXD/UCA3SOMI

80

81

A10

B9

I/O Transmit data – USCI_A3 UART mode

Slave in, master out – USCI_A3 SPI mode

General-purpose digital I/O

I/O Receive data – USCI_A3 UART mode

Slave out, master in – USCI_A3 SPI mode

P10.6

P10.7

82

83

A9

B8

I/O General-purpose digital I/O

General-purpose digital I/O

ACLK output (divided by 1, 2, 4, 8, 16, or 32)

P11.0/ACLK

P11.1/MCLK

P11.2/SMCLK

84

85

86

A8

D7

A7

I/O

General-purpose digital I/O

MCLK output

I/O

General-purpose digital I/O

SMCLK output

I/O

DVCC4

DVSS4

87

88

B7

B6

Digital power supply

Digital ground supply

General-purpose digital I/O

I/O

P5.2/XT2IN

89

90

91

A6

A5

D6

Input terminal for crystal oscillator XT2

General-purpose digital I/O

I/O

P5.3/XT2OUT

TEST/SBWTCK⁽³⁾

Output terminal of crystal oscillator XT2

Test mode pin – Selects four wire JTAG operation.

Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated

I

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TERMINAL

NAME

NO.

I/O⁽¹⁾

DESCRIPTION

PZ ZQW

General-purpose digital I/O

JTAG test data output port

PJ.0/TDO⁽⁴⁾

92

93

94

95

B5

A4

D5

B4

I/O

General-purpose digital I/O

JTAG test data input or test clock input

PJ.1/TDI/TCLK⁽⁴⁾

PJ.2/TMS⁽⁴⁾

General-purpose digital I/O

JTAG test mode select

General-purpose digital I/O

JTAG test clock

PJ.3/TCK⁽⁴⁾

Reset input active low⁽⁵⁾

I/O Nonmaskable interrupt input

RST/NMI/SBWTDIO⁽³⁾

96

A3

Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated.

General-purpose digital I/O

I/O

P6.0/A0

P6.1/A1

P6.2/A2

P6.3/A3

97

98

D4

B3

A2

B2

Analog input A0 – ADC

General-purpose digital I/O

I/O

Analog input A1 – ADC

General-purpose digital I/O

I/O

99

Analog input A2 – ADC

General-purpose digital I/O

I/O

100

Analog input A3 – ADC

G5,

E8,

F8,

G8,

H8,

E7,

H7,

E6,

H6,

E5,

F5,

H5,

C3

Reserved

N/A

Reserved. Connect to ground.

(1) I = input, O = output, N/A = not available on this package offering

(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended

capacitor value, C_VCORE

.

(3) See Section 8.5 and Section 8.6 for use with BSL and JTAG functions, respectively.

(4) See Section 8.6 for use with JTAG function.

(5) When this pin is configured as reset, the internal pullup resistor is enabled by default.

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

V

Voltage applied at V_CCto V_SS

–0.3

4.1

Voltage applied to any pin (excluding VCORE)⁽²⁾

–0.3 V_CC+ 0.3

±2

V

Diode current at any device pin

mA

°C

(3)

Storage temperature range, T_stg

–55

105

95

Maximum junction temperature, T_J

°C

(1) Stresses beyond those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V_SS. VCORE is for internal device use only. No external DC loading or voltage should be applied.

(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

7.2 ESD Ratings

VALUE

±1000

±250

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as

±1000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as

±250 V may actually have higher performance.

7.3 Recommended Operating Conditions

Typical values are specified at V_CC= 3.3 V and T_A= 25°C (unless otherwise noted)

MIN NOM MAX UNIT

Supply voltage during program execution and flash programming

V_CC

1.8

3.6

V

(1) (2)

(AV_CC= DV_CC1/2/3/4= DV_CC

)

V_SS

T_A

Supply voltage (AV_SS= DV_SS1/2/3/4= DV_SS

Operating free-air temperature

)

0

I version

–40

85 °C

nF

T_J

Operating junction temperature

C_VCORE

Recommended capacitor at VCORE⁽³⁾

470

C_DVCC

C_VCORE

/

Capacitor ratio of DVCC to VCORE

10

PMMCOREVx = 0, 1.8 V ≤ V_CC≤ 3.6 V

PMMCOREVx = 1, 2.0 V ≤ V_CC≤ 3.6 V

PMMCOREVx = 2, 2.2 V ≤ V_CC≤ 3.6 V

PMMCOREVx = 3, 2.4 V ≤ V_CC≤ 3.6 V

0

8.0

12.0

Processor frequency (maximum MCLK

frequency)^{(4) (5)}(see Figure 7-1)

f_SYSTEM

MHz

20.0

25.0

(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be

tolerated during power up and operation.

(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Section 7.23 threshold parameters for

the exact values and further details.

(3) A capacitor tolerance of ±20% or better is required.

(4) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the

specified maximum frequency.

(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

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25

20

12

8

3

2, 3

2

1, 2

1, 2, 3

1

0

0, 1

0, 1, 2

0, 1, 2, 3

0

1.8

2.0

2.2

2.4

3.6

Supply Voltage - V

The numbers within the fields denote the supported PMMCOREVx settings.

Figure 7-1. Frequency vs Supply Voltage

7.4 Active Mode Supply Current Into V_CCExcluding External Current

over recommended operating free-air temperature (unless otherwise noted)^{(1) (2) (3)}

FREQUENCY (f_DCO= f_MCLK= f_SMCLK

)

PARAMETE EXECUTION

PMMCOREV

x

V_CC

1 MHz

8 MHz 12 MHz 20 MHz

25 MHz

UNIT

R

MEMORY

TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX

0

1

2

3

0

1

2

3

0.29 0.33 1.84 2.08

0.32

0.33

0.35

2.08

2.24

2.36

3.10

3.50

3.70

I_{AM, Flash}

Flash

3 V

mA

6.37

6.75

8.90 9.60

4.50 4.90

0.17 0.19 0.88 0.99

0.18

0.19

0.20

1.00

1.13

1.20

1.47

1.68

1.78

I_{AM, RAM}

RAM

3 V

mA

2.82

3.00

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external

load capacitance are chosen to closely match the required 12.5 pF.

(3) Characterized with program executing typical data processing.

f_ACLK= 32786 Hz, f_DCO= f_MCLK= f_SMCLKat specified frequency.

XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.

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7.5 Low-Power Mode Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)^{(1) (2)}

–40°C

25°C

60°C

85°C

PARAMETER

V_CC

PMMCOREVx

UNIT

TYP MAX

2.2 V

3 V

0

3

0

3

0

1

2

0

1

2

3

0

1

2

3

0

1

2

3

69

73

93

100

69

73

93

100

69

73

93

100

69

73

93

100

Low-power

I_LPM0,1MHz

µA

mode 0^{(3) (9)}

2.2 V

3 V

11

15.5

17.5

11

15.5

17.5

11

15.5

17.5

11

15.5

17.5

Low-power

I_LPM2

µA

mode 2^{(4) (9)}

11.7

1.4

1.5

1.8

1.9

2.0

1.0

1.1

1.2

1.1

1.2

1.3

0.10

11.7

1.7

1.8

2.0

2.1

2.3

2.4

2.3

1.2

1.3

1.4

1.2

1.3

0.10

11.7

2.6

2.9

3.3

2.8

3.1

3.5

3.9

2.0

2.3

2.8

3.0

1.9

2.2

2.6

2.9

0.20

11.7

6.6

2.2 V

9.9

10.1

7.1

Low-power mode 3,

crystal mode^{(5) (9)}

I_LPM3,XT1LF

2.4

13.6

µA

10.5

10.6

11.8

5.8

3 V

2.6

14.8

12.9

1.42

6.0

Low-power mode 3,

VLO mode^{(6) (9)}

I_LPM3,VLO

3 V

6.2

1.62

1.35

6.2

13.9

12.9

5.7

5.9

Low-power

I_LPM4

3 V

µA

mode 4^{(7) (9)}

6.1

1.52

0.13

6.2

13.9

1.14

I_LPM4.5

Low-power mode 4.5⁽⁸⁾

0.50

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external

load capacitance are chosen to closely match the required 12.5 pF.

(3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), f_ACLK= 32768 Hz, f_MCLK= 0 MHz, f_SMCLK= f_DCO= 1 MHz

(4) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), f_ACLK= 32768 Hz, f_MCLK= 0 MHz, f_SMCLK= f_DCO= 0 MHz, DCO setting =

1 MHz operation, DCO bias generator enabled.

(5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), f_ACLK= 32768 Hz, f_MCLK= f_SMCLK= f_DCO= 0 MHz

(6) Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), f_ACLK= f_VLO, f_MCLK= f_SMCLK= f_DCO= 0 MHz

(7) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), f_DCO= f_ACLK= f_MCLK= f_SMCLK= 0 MHz

(8) Internal regulator disabled. No data retention.

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), f_DCO= f_ACLK= f_MCLK= f_SMCLK= 0 MHz

(9) Current for brownout, high side supervisor (SVS_H) normal mode included. Low-side supervisor and monitors disabled (SVS_L, SVM_L).

High side monitor disabled (SVM_H). RAM retention enabled.

7.6 Thermal Characteristics

VALUE

50.1

60

UNIT

QFP (PZ)

Low-K board (JESD51-3)

High-K board (JESD51-7)

BGA (ZQW)

QFP (PZ)

θ_JA

Junction-to-ambient thermal resistance, still air

Junction-to-case thermal resistance

°C/W

40.8

42

BGA (ZQW)

QFP (PZ)

8.9

θ_JC

°C/W

BGA (ZQW)

8

16

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7.7 Schmitt-Trigger Inputs – General-Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

1.8 V

3 V

MIN

0.80

1.50

0.45

0.75

0.3

TYP

MAX UNIT

1.40

V

2.10

V_IT+

V_IT–

V_hys

Positive-going input threshold voltage

1.8 V

3 V

1.00

V

1.65

Negative-going input threshold voltage

1.8 V

3 V

0.85

V

1.0

Input voltage hysteresis (V_IT+– V_IT–

)

0.4

For pullup: V_IN= V_SS

For pulldown: V_IN= V_CC

R_Pull

C_I

Pullup or pulldown resistor⁽¹⁾

Input capacitance

20

35

5

50

kΩ

pF

V_IN= V_SSor V_CC

(1) Also applies to RST pin when the pullup or pulldown resistor is enabled.

7.8 Inputs – Ports P1 and P2

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER⁽¹⁾

TEST CONDITIONS

V_CC

MIN

MAX UNIT

Port P1, P2: P1.x to P2.x, external trigger pulse

duration to set interrupt flag

t_(int)

External interrupt timing⁽²⁾

2.2 V, 3 V

20

ns

(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.

(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t_(int)is met. It may be set by trigger signals

shorter than t_(int)

.

7.9 Leakage Current – General-Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

(1) (2)

I_lkg(Px.y)

High-impedance leakage current

1.8 V, 3 V

±50 nA

(1) The leakage current is measured with V_SSor V_CCapplied to the corresponding pins, unless otherwise noted.

(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is

disabled.

7.10 Outputs – General-Purpose I/O (Full Drive Strength)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_(OHmax)= –3 mA⁽¹⁾

V_CC

MIN

V_CC– 0.25

V_CC– 0.60

V_CC– 0.25

V_CC– 0.60

MAX UNIT

V_CC

1.8 V

I_(OHmax)= –10 mA⁽²⁾

I_(OHmax)= –5 mA⁽¹⁾

I_(OHmax)= –15 mA⁽²⁾

I_(OLmax)= 3 mA⁽¹⁾

I_(OLmax)= 10 mA⁽²⁾

I_(OLmax)= 5 mA⁽¹⁾

I_(OLmax)= 15 mA⁽²⁾

V_CC

V_OH

High-level output voltage

V

V_CC

3 V

1.8 V

3 V

V_CC

V_SSV_SS+ 0.25

V_SSV_SS+ 0.60

V_SSV_SS+ 0.25

V_SSV_SS+ 0.60

V_OL

Low-level output voltage

V

(1) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage

drop specified.

(2) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage

drop specified.

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7.11 Outputs – General-Purpose I/O (Reduced Drive Strength)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽³⁾

PARAMETER

TEST CONDITIONS

I_(OHmax)= –1 mA⁽¹⁾

V_CC

MIN

V_CC– 0.25

V_CC– 0.60

V_CC– 0.25

V_CC– 0.60

MAX UNIT

V_CC

1.8 V

I_(OHmax)= –3 mA⁽²⁾

I_(OHmax)= –2 mA⁽¹⁾

I_(OHmax)= –6 mA⁽²⁾

I_(OLmax)= 1 mA⁽¹⁾

I_(OLmax)= 3 mA⁽²⁾

I_(OLmax)= 2 mA⁽¹⁾

I_(OLmax)= 6 mA⁽²⁾

V_CC

V_OH

High-level output voltage

V

V_CC

3 V

1.8 V

3 V

V_CC

V_SSV_SS+ 0.25

V_SSV_SS+ 0.60

V_SSV_SS+ 0.25

V_SSV_SS+ 0.60

V_OL

Low-level output voltage

V

(1) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage

drop specified.

(2) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage

drop specified.

(3) Selecting reduced drive strength may reduce EMI.

7.12 Output Frequency – General-Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX UNIT

V_CC= 1.8 V

PMMCOREVx = 0

16

Port output frequency

(with load)

f_Px.y

P1.6/SMCLK ^{(1) (2)}

MHz

25

V_CC= 3 V

PMMCOREVx = 3

V_CC= 1.8 V

PMMCOREVx = 0

P1.0/TA0CLK/ACLK

P1.6/SMCLK

16

f_{Port_CLK}

Clock output frequency

MHz

25

P2.0/TA1CLK/MCLK

V_CC= 3 V

PMMCOREVx = 3

C_L= 20 pF⁽²⁾

(1) A resistive divider with 2 × R1 between V_CCand V_SSis used as load. The output is connected to the center tap of the divider. For full

drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. C_L= 20 pF is connected to the output to V_SS

.

(2) The output voltage reaches at least 10% and 90% V_CCat the specified toggle frequency.

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7.13 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

60.0

T_A= 25°C

T_A= 85°C

24

20

16

12

8

V_CC= 1.8 V

Px.y

V_CC= 3.0 V

Px.y

55.0

50.0

45.0

40.0

35.0

30.0

25.0

20.0

15.0

10.0

5.0

T_A= 25°C

T_A= 85°C

4

0.0

0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

V_OL– Low-Level Output Voltage – V

Figure 7-2. Typical Low-Level Output Current vs

Low-Level Output Voltage

Figure 7-3. Typical Low-Level Output Current vs

Low-Level Output Voltage

0

0.0

V_CC= 1.8 V

Px.y

V_CC= 3.0 V

-5.0

Px.y

-10.0

-15.0

-20.0

-25.0

-30.0

-35.0

-40.0

-4

-8

-12

T_A= 85°C

-16

-45.0

T_A= 85°C

-50.0

-55.0

T_A= 25°C

-60.0

T_A= 25°C

-20

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

V_OH– High-Level Output Voltage – V

Figure 7-4. Typical High-Level Output Current vs

High-Level Output Voltage

Figure 7-5. Typical High-Level Output Current vs

High-Level Output Voltage

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7.14 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

8.0

7.0

6.0

5.0

4.0

3.0

2.0

1.0

0.0

25.0

20.0

15.0

10.0

5.0

T_A= 25°C

T_A= 85°C

V_CC= 3.0 V

Px.y

V_CC= 1.8 V

Px.y

T_A= 25°C

T_A= 85°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

V_OL– Low-Level Output Voltage – V

Figure 7-6. Typical Low-Level Output Current vs

Low-Level Output Voltage

Figure 7-7. Typical Low-Level Output Current vs

Low-Level Output Voltage

0.0

V_CC= 1.8 V

V_CC= 3.0 V

Px.y

-1.0

-5.0

-2.0

-3.0

-4.0

-10.0

T_A= 85°C

-5.0

-15.0

T_A= 85°C

-6.0

T_A= 25°C

-20.0

T_A= 25°C

-7.0

-8.0

-25.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

V_OH– High-Level Output Voltage – V

Figure 7-8. Typical High-Level Output Current vs

High-Level Output Voltage

Figure 7-9. Typical High-Level Output Current vs

High-Level Output Voltage

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7.15 Crystal Oscillator, XT1, Low-Frequency Mode

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER⁽¹⁾

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 1,

T_A= 25°C

0.075

Differential XT1 oscillator crystal

current consumption from lowest

drive setting, LF mode

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 2,

T_A= 25°C

ΔI_DVCC.LF

3 V

0.170

µA

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 3,

T_A= 25°C

0.290

XT1 oscillator crystal frequency,

LF mode

f_XT1,LF0

XTS = 0, XT1BYPASS = 0

32768

Hz

XT1 oscillator logic-level square-

wave input frequency, LF mode

f_XT1,LF,SW

XTS = 0, XT1BYPASS = 1^{(5) (6)}

10 32.768

210

50 kHz

XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 0,

f_XT1,LF= 32768 Hz, C_L,eff= 6 pF

Oscillation allowance for

LF crystals⁽⁷⁾

OA_LF

kΩ

XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 1,

f_XT1,LF= 32768 Hz, C_L,eff= 12 pF

300

XTS = 0, XCAPx = 0⁽²⁾

XTS = 0, XCAPx = 1

XTS = 0, XCAPx = 2

XTS = 0, XCAPx = 3

1

5.5

Integrated effective load

capacitance, LF mode⁽¹⁾

C_L,eff

pF

8.5

12.0

XTS = 0, Measured at ACLK,

f_XT1,LF= 32768 Hz

Duty cycle, LF mode

30%

10

70%

Oscillator fault frequency,

LF mode⁽⁴⁾

f_Fault,LF

XTS = 0⁽³⁾

10000

Hz

ms

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 0,

T_A= 25°C, C_L,eff= 6 pF

1000

500

t_START,LF

Start-up time, LF mode

3 V

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 3,

T_A= 25°C, C_L,eff= 12 pF

(1) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a

correct setup, the effective load capacitance should always match the specification of the used crystal.

(2) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

(3) Measured with logic-level input frequency but also applies to operation with crystals.

(4) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies between the MIN and MAX might set the flag.

(5) When XT1BYPASS is set, XT1 circuits are automatically powered down. The input signal must be a digital square wave with the

parametrics defined in the Section 7.7 section.

(6) Maximum frequency of operation of the entire device cannot be exceeded.

(7) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the

XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following

guidelines, but should be evaluated based on the actual crystal selected for the application:

•

For XT1DRIVEx = 0, C_L,eff≤ 6 pF.

For XT1DRIVEx = 1, 6 pF ≤ C_L,eff≤ 9 pF.

For XT1DRIVEx = 2, 6 pF ≤ C_L,eff≤ 10 pF.

For XT1DRIVEx = 3, C_L,eff≥ 6 pF.

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7.16 Crystal Oscillator, XT1, High-Frequency Mode

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER⁽¹⁾

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

f_OSC= 4 MHz,

XTS = 1, XOSCOFF = 0,

XT1BYPASS = 0, XT1DRIVEx = 0,

T_A= 25°C

200

f_OSC= 12 MHz,

XTS = 1, XOSCOFF = 0,

XT1BYPASS = 0, XT1DRIVEx = 1,

T_A= 25°C

260

325

450

XT1 oscillator crystal current,

HF mode

I_DVCC.HF

3 V

µA

f_OSC= 20 MHz,

XTS = 1, XOSCOFF = 0,

XT1BYPASS = 0, XT1DRIVEx = 2,

T_A= 25°C

f_OSC= 32 MHz,

XTS = 1, XOSCOFF = 0,

XT1BYPASS = 0, XT1DRIVEx = 3,

T_A= 25°C

XT1 oscillator crystal frequency,

HF mode 0

XTS = 1,

f_XT1,HF0

f_XT1,HF1

f_XT1,HF2

f_XT1,HF3

4

8

MHz

XT1BYPASS = 0, XT1DRIVEx = 0⁽⁶⁾

XT1 oscillator crystal frequency,

HF mode 1

XTS = 1,

16 MHz

24 MHz

32 MHz

XT1BYPASS = 0, XT1DRIVEx = 1⁽⁶⁾

XT1 oscillator crystal frequency,

HF mode 2

XTS = 1,

16

24

XT1BYPASS = 0, XT1DRIVEx = 2⁽⁶⁾

XT1 oscillator crystal frequency,

HF mode 3

XTS = 1,

XT1BYPASS = 0, XT1DRIVEx = 3⁽⁶⁾

XT1 oscillator logic-level square-

wave input frequency, HF mode,

bypass mode

XTS = 1,

f_XT1,HF,SW

1.5

32 MHz

XT1BYPASS = 1^{(5) (6)}

XTS = 1,

XT1BYPASS = 0, XT1DRIVEx = 0,

f_XT1,HF= 6 MHz, C_L,eff= 15 pF

450

320

200

0.5

XTS = 1,

XT1BYPASS = 0, XT1DRIVEx = 1,

f_XT1,HF= 12 MHz, C_L,eff= 15 pF

Oscillation allowance for

HF crystals⁽⁷⁾

OA_HF

Ω

XTS = 1,

XT1BYPASS = 0, XT1DRIVEx = 2,

f_XT1,HF= 20 MHz, C_L,eff= 15 pF

XTS = 1,

XT1BYPASS = 0, XT1DRIVEx = 3,

f_XT1,HF= 32 MHz, C_L,eff= 15 pF

f_OSC= 6 MHz, XTS = 1,

XT1BYPASS = 0, XT1DRIVEx = 0,

T_A= 25°C, C_L,eff= 15 pF

t_START,HF

Start-up time, HF mode

3 V

ms

pF

f_OSC= 20 MHz, XTS = 1,

XT1BYPASS = 0, XT1DRIVEx = 2,

T_A= 25°C, C_L,eff= 15 pF

0.3

Integrated effective load

C_L,eff

XTS = 1

1

capacitance, HF mode^{(1) (2)}

XTS = 1, Measured at ACLK,

f_XT1,HF2= 20 MHz

Duty cycle, HF mode

40%

30

50%

60%

300 kHz

Oscillator fault frequency,

HF mode⁽⁴⁾

f_Fault,HF

XTS = 1⁽³⁾

(1) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a

correct setup, the effective load capacitance should always match the specification of the used crystal.

(2) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

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(3) Measured with logic-level input frequency but also applies to operation with crystals.

(4) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies between the MIN and MAX might set the flag.

(5) When XT1BYPASS is set, XT1 circuits are automatically powered down. The input signal must be a digital square wave with the

parametrics defined in the Section 7.7 section.

(6) This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device

operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.

(7) Oscillation allowance is based on a safety factor of 5 for recommended crystals.

7.17 Crystal Oscillator, XT2

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)^{(2) (5)}

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

f_OSC= 4 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 0,

T_A= 25°C

200

f_OSC= 12 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 1,

T_A= 25°C

260

325

450

XT2 oscillator crystal current

consumption

I_DVCC.XT2

3 V

µA

f_OSC= 20 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 2,

T_A= 25°C

f_OSC= 32 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 3,

T_A= 25°C

XT2 oscillator crystal frequency,

mode 0

f_XT2,HF0

f_XT2,HF1

f_XT2,HF2

f_XT2,HF3

f_XT2,HF,SW

XT2DRIVEx = 0, XT2BYPASS = 0⁽⁷⁾

XT2DRIVEx = 1, XT2BYPASS = 0⁽⁷⁾

XT2DRIVEx = 2, XT2BYPASS = 0⁽⁷⁾

XT2DRIVEx = 3, XT2BYPASS = 0⁽⁷⁾

XT2BYPASS = 1^{(6) (7)}

4

8

MHz

XT2 oscillator crystal frequency,

mode 1

16 MHz

24 MHz

32 MHz

XT2 oscillator crystal frequency,

mode 2

16

24

1.5

XT2 oscillator crystal frequency,

mode 3

XT2 oscillator logic-level square-

wave input frequency, bypass mode

XT2DRIVEx = 0, XT2BYPASS = 0,

f_XT2,HF0= 6 MHz, C_L,eff= 15 pF

450

320

200

XT2DRIVEx = 1, XT2BYPASS = 0,

f_XT2,HF1= 12 MHz, C_L,eff= 15 pF

Oscillation allowance for

HF crystals⁽⁸⁾

OA_HF

Ω

XT2DRIVEx = 2, XT2BYPASS = 0,

f_XT2,HF2= 20 MHz, C_L,eff= 15 pF

XT2DRIVEx = 3, XT2BYPASS = 0,

f_XT2,HF3= 32 MHz, C_L,eff= 15 pF

f_OSC= 6 MHz

XT2BYPASS = 0, XT2DRIVEx = 0,

T_A= 25°C, C_L,eff= 15 pF

0.5

0.3

t_START,HF

Start-up time

3 V

ms

pF

f_OSC= 20 MHz

XT2BYPASS = 0, XT2DRIVEx = 2,

T_A= 25°C, C_L,eff= 15 pF

Integrated effective load

C_L,eff

1

capacitance, HF mode^{(1) (2)}

Duty cycle

Measured at ACLK, f_XT2,HF2= 20 MHz

XT2BYPASS = 1⁽³⁾

40%

30

50%

60%

300 kHz

f_Fault,HF

Oscillator fault frequency⁽⁴⁾

(1) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a

correct setup, the effective load capacitance should always match the specification of the used crystal.

(2) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

(3) Measured with logic-level input frequency but also applies to operation with crystals.

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(4) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies between the MIN and MAX might set the flag.

(5) To improve EMI on the XT2 oscillator the following guidelines should be observed.

•

Keep the traces between the device and the crystal as short as possible.

Design a good ground plane around the oscillator pins.

Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.

Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.

Use assembly materials and techniques that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.

If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.

(6) When XT2BYPASS is set, XT2 circuits are automatically powered down. The input signal must be a digital square wave with the

parametrics defined in the Section 7.7 section.

(7) This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device

operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.

(8) Oscillation allowance is based on a safety factor of 5 for recommended crystals.

7.18 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

VLO frequency

VLO frequency temperature drift

TEST CONDITIONS

V_CC

MIN

TYP

9.4

0.5

4

MAX UNIT

14 kHz

%/°C

f_VLO

Measured at ACLK

1.8 V to 3.6 V

6

df_VLO/d_T

Measured at ACLK⁽¹⁾

Measured at ACLK⁽²⁾

Measured at ACLK

df_VLO/dV_CCVLO frequency supply voltage drift

Duty cycle

%/V

40%

50%

60%

(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))

(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

7.19 Internal Reference, Low-Frequency Oscillator (REFO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

I_REFO

REFO oscillator current consumption T_A= 25°C

1.8 V to 3.6 V

3 V

3

µA

REFO frequency calibrated

Measured at ACLK

32768

Hz

f_REFO

Full temperature range

T_A= 25°C

±3.5%

±1.5%

%/°C

%/V

REFO absolute tolerance calibrated

df_REFO/d_T

REFO frequency temperature drift

Measured at ACLK⁽¹⁾

1.8 V to 3.6 V

0.01

1.0

df_REFO/dV_CC

REFO frequency supply voltage drift Measured at ACLK⁽²⁾

Duty cycle

Measured at ACLK

40%/60% duty cycle

40%

50%

25

60%

t_START

REFO start-up time

µs

(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))

(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

7.20 DCO Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

DCORSELx = 0, DCOx = 0, MODx = 0

DCORSELx = 0, DCOx = 31, MODx = 0

DCORSELx = 1, DCOx = 0, MODx = 0

DCORSELx = 1, DCOx = 31, MODx = 0

DCORSELx = 2, DCOx = 0, MODx = 0

DCORSELx = 2, DCOx = 31, MODx = 0

DCORSELx = 3, DCOx = 0, MODx = 0

DCORSELx = 3, DCOx = 31, MODx = 0

DCORSELx = 4, DCOx = 0, MODx = 0

MIN

0.07

0.70

0.15

1.47

0.32

3.17

0.64

6.07

1.3

TYP

MAX UNIT

0.20 MHz

1.70 MHz

0.36 MHz

3.45 MHz

0.75 MHz

7.38 MHz

1.51 MHz

14.0 MHz

3.2 MHz

f_DCO(0,0)

f_DCO(0,31)

f_DCO(1,0)

f_DCO(1,31)

f_DCO(2,0)

f_DCO(2,31)

f_DCO(3,0)

f_DCO(3,31)

f_DCO(4,0)

DCO frequency (0, 0)⁽¹⁾

DCO frequency (0, 31)⁽¹⁾

DCO frequency (1, 0)⁽¹⁾

DCO frequency (1, 31)⁽¹⁾

DCO frequency (2, 0)⁽¹⁾

DCO frequency (2, 31)⁽¹⁾

DCO frequency (3, 0)⁽¹⁾

DCO frequency (3, 31)⁽¹⁾

DCO frequency (4, 0)⁽¹⁾

24

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over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

DCORSELx = 4, DCOx = 31, MODx = 0

DCORSELx = 5, DCOx = 0, MODx = 0

DCORSELx = 5, DCOx = 31, MODx = 0

DCORSELx = 6, DCOx = 0, MODx = 0

DCORSELx = 6, DCOx = 31, MODx = 0

DCORSELx = 7, DCOx = 0, MODx = 0

DCORSELx = 7, DCOx = 31, MODx = 0

MIN

12.3

2.5

TYP

MAX UNIT

28.2 MHz

6.0 MHz

f_DCO(4,31)

f_DCO(5,0)

f_DCO(5,31)

f_DCO(6,0)

f_DCO(6,31)

f_DCO(7,0)

f_DCO(7,31)

DCO frequency (4, 31)⁽¹⁾

DCO frequency (5, 0)⁽¹⁾

DCO frequency (5, 31)⁽¹⁾

DCO frequency (6, 0)⁽¹⁾

DCO frequency (6, 31)⁽¹⁾

DCO frequency (7, 0)⁽¹⁾

DCO frequency (7, 31)⁽¹⁾

23.7

4.6

54.1 MHz

10.7 MHz

88.0 MHz

19.6 MHz

135 MHz

39.0

8.5

60

Frequency step between range

DCORSEL and DCORSEL + 1

S_DCORSEL

S_DCO

S_RSEL= f_{DCO(DCORSEL+1,DCO)}/f_{DCO(DCORSEL,DCO)}

S_DCO= f_{DCO(DCORSEL,DCO+1)}/f_{DCO(DCORSEL,DCO)}

1.2

2.3 ratio

Frequency step between tap DCO

and DCO + 1

1.02

40%

1.12 ratio

Duty cycle

Measured at SMCLK

f_DCO= 1 MHz

50%

0.1

60%

%/°C

%/V

df_DCO/dT

DCO frequency temperature drift⁽²⁾

df_DCO/dV_CCDCO frequency voltage drift⁽³⁾

f_DCO= 1 MHz

1.9

(1) When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, f_DCO, should be set to reside within the

range of f_{DCO(n, 0),MAX}≤ f_DCO≤ f_{DCO(n, 31),MIN}, where f_{DCO(n, 0),MAX}represents the maximum frequency specified for the DCO frequency,

range n, tap 0 (DCOx = 0) and f_{DCO(n,31),MIN}represents the minimum frequency specified for the DCO frequency, range n, tap 31

(DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual

f_DCOfrequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the

selected range is at its minimum or maximum tap setting.

(2) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))

(3) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

Typical DCO Frequency, V_CC= 3.0 V,T_A= 25°C

100

10

DCOx = 31

1

DCOx = 0

0.1

0

1

2

3

4

5

6

7

DCORSEL

Figure 7-10. Typical DCO Frequency

7.21 PMM, Brown-Out Reset (BOR)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

BOR_Hon voltage,

DV_CCfalling level

V(DV_CC_BOR_IT–)

| dDV_CC/d_t| < 3 V/s

1.45

V

BOR_Hoff voltage,

DV_CCrising level

V(DV_CC_BOR_IT+)

V(DV_CC_BOR_hys)

| dDV_CC/d_t| < 3 V/s

0.80

60

1.30

1.50

250

V

BOR_Hhysteresis

mV

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over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Pulse duration required at RST/NMI pin

to accept a reset

t_RESET

2

µs

7.22 PMM, Core Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

2.4 V ≤ DV_CC≤ 3.6 V

2.2 V ≤ DV_CC≤ 3.6 V

2.0 V ≤ DV_CC≤ 3.6 V

1.8 V ≤ DV_CC≤ 3.6 V

2.4 V ≤ DV_CC≤ 3.6 V

2.2 V ≤ DV_CC≤ 3.6 V

2.0 V ≤ DV_CC≤ 3.6 V

1.8 V ≤ DV_CC≤ 3.6 V

MIN

TYP

1.90

1.80

1.60

1.40

1.94

1.84

1.64

1.44

MAX

UNIT

V

V_CORE3(AM)

V_CORE2(AM)

V_CORE1(AM)

V_CORE0(AM)

Core voltage, active mode, PMMCOREV = 3

Core voltage, active mode, PMMCOREV = 2

Core voltage, active mode, PMMCOREV = 1

Core voltage, active mode, PMMCOREV = 0

V

V_CORE3(LPM) Core voltage, low-current mode, PMMCOREV = 3

V_CORE2(LPM) Core voltage, low-current mode, PMMCOREV = 2

V_CORE1(LPM) Core voltage, low-current mode, PMMCOREV = 1

V_CORE0(LPM) Core voltage, low-current mode, PMMCOREV = 0

V

7.23 PMM, SVS High Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SVSHE = 0, DV_CC= 3.6 V

0

nA

I_(SVSH)

SVS current consumption

SVSHE = 1, DV_CC= 3.6 V, SVSHFP = 0

SVSHE = 1, DV_CC= 3.6 V, SVSHFP = 1

SVSHE = 1, SVSHRVL = 0

200

1.5

µA

1.57

1.79

1.98

2.10

1.62

1.88

2.07

2.20

2.32

2.52

2.90

1.68

1.88

2.08

2.18

1.74

1.94

2.14

2.30

2.40

2.70

3.10

1.78

SVSHE = 1, SVSHRVL = 1

1.98

V

V_{(SVSH_IT–)}

SVS_Hon voltage level⁽¹⁾

SVSHE = 1, SVSHRVL = 2

2.21

SVSHE = 1, SVSHRVL = 3

2.31

1.85

2.07

2.28

SVSHE = 1, SVSMHRRL = 0

SVSHE = 1, SVSMHRRL = 1

SVSHE = 1, SVSMHRRL = 2

SVSHE = 1, SVSMHRRL = 3

SVSHE = 1, SVSMHRRL = 4

SVSHE = 1, SVSMHRRL = 5

SVSHE = 1, SVSMHRRL = 6

SVSHE = 1, SVSMHRRL = 7

2.42

V

V_{(SVSH_IT+)}

SVS_Hoff voltage level⁽¹⁾

2.55

2.88

3.23

SVSHE = 1, dV_DVCC/dt = 10 mV/µs,

SVSHFP = 1

2.5

20

t_pd(SVSH)

SVS_Hpropagation delay

µs

SVSHE = 1, dV_DVCC/dt = 1 mV/µs,

SVSHFP = 0

SVSHE = 0 → 1, dV_DVCC/dt = 10 mV/µs,

SVSHFP = 1

12.5

100

t_(SVSH)

SVS_Hon or off delay time

DV_CCrise time

µs

SVSHE = 0 → 1, dV_DVCC/dt = 1 mV/µs,

SVSHFP = 0

dV_DVCC/dt

0

1000 V/s

(1) The SVS_Hsettings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage

Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and use.

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7.24 PMM, SVM High Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SVMHE = 0, DV_CC= 3.6 V

0

nA

I_(SVMH)

SVM_Hcurrent consumption

SVMHE= 1, DV_CC= 3.6 V, SVMHFP = 0

SVMHE = 1, DV_CC= 3.6 V, SVMHFP = 1

SVMHE = 1, SVSMHRRL = 0

SVMHE = 1, SVSMHRRL = 1

SVMHE = 1, SVSMHRRL = 2

SVMHE = 1, SVSMHRRL = 3

SVMHE = 1, SVSMHRRL = 4

SVMHE = 1, SVSMHRRL = 5

SVMHE = 1, SVSMHRRL = 6

SVMHE = 1, SVSMHRRL = 7

SVMHE = 1, SVMHOVPE = 1

200

1.5

µA

1.85

1.62

1.88

2.07

2.20

2.32

2.52

2.90

1.74

1.94

2.14

2.30

2.40

2.70

3.10

3.75

2.07

2.28

2.42

V_(SVMH)

SVM_Hon or off voltage level⁽¹⁾

2.55

2.88

3.23

V

SVMHE = 1, dV_DVCC/dt = 10 mV/µs,

SVMHFP = 1

2.5

20

t_pd(SVMH)

SVM_Hpropagation delay

SVM_Hon or off delay time

µs

SVMHE = 1, dV_DVCC/dt = 1 mV/µs,

SVMHFP = 0

SVMHE = 0 → 1, dV_DVCC/dt = 10 mV/µs,

SVMHFP = 1

12.5

100

t_(SVMH)

SVMHE = 0 → 1, dV_DVCC/dt = 1 mV/µs,

SVMHFP = 0

(1) The SVM_Hsettings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage

Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and use.

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7.25 PMM, SVS Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SVSLE = 0, PMMCOREV = 2

0

nA

µA

I_(SVSL)

SVS_Lcurrent consumption

SVSLE = 1, PMMCOREV = 2, SVSLFP = 0

SVSLE = 1, PMMCOREV = 2, SVSLFP = 1

200

1.5

SVSLE = 1, dV_CORE/dt = 10 mV/µs,

SVSLFP = 1

2.5

20

t_pd(SVSL)

SVS_Lpropagation delay

SVS_Lon or off delay time

µs

SVSLE = 1, dV_CORE/dt = 1 mV/µs,

SVSLFP = 0

SVSLE = 0 → 1, dV_CORE/dt = 10 mV/µs,

SVSLFP = 1

12.5

100

t_(SVSL)

SVSLE = 0 → 1, dV_CORE/dt = 1 mV/µs,

SVSLFP = 0

7.26 PMM, SVM Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SVMLE = 0, PMMCOREV = 2

0

nA

µA

I_(SVML)

SVM_Lcurrent consumption

SVMLE= 1, PMMCOREV = 2, SVMLFP = 0

SVMLE= 1, PMMCOREV = 2, SVMLFP = 1

200

1.5

SVMLE = 1, dV_CORE/dt = 10 mV/µs,

SVMLFP = 1

2.5

20

t_pd(SVML)

SVM_Lpropagation delay

SVM_Lon or off delay time

µs

SVMLE = 1, dV_CORE/dt = 1 mV/µs,

SVMLFP = 0

SVMLE = 0 → 1, dV_CORE/dt = 10 mV/µs,

SVMLFP = 1

12.5

100

t_(SVML)

SVMLE = 0 → 1, dV_CORE/dt = 1 mV/µs,

SVMLFP = 0

7.27 Wake-up Times From Low-Power Modes and Reset

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP MAX UNIT

PMMCOREV = SVSMLRRL = n f_MCLK≥ 4.0 MHz

(where n = 0, 1, 2, or 3),

f_MCLK< 4.0 MHz

SVSLFP = 1

5

t_WAKE-UP-

Wake-up time from LPM2, LPM3, or LPM4

to active mode⁽¹⁾

µs

FAST

6

PMMCOREV = SVSMLRRL = n

(where n = 0, 1, 2, or 3),

SVSLFP = 0

t_WAKE-UP-

Wake-up time from LPM2, LPM3 or LPM4 to

active mode⁽²⁾

150 165 µs

SLOW

t_WAKE-UP-

Wake-up time from LPM4.5 to active mode⁽³⁾

2

3

ms

LPM5

t_WAKE-UP-

Wake-up time from RST or BOR event to

active mode⁽³⁾

RESET

(1) This value represents the time from the wake-up event to the first active edge of MCLK. The wakeup time depends on the performance

mode of the low-side supervisor (SVS_L) and low-side monitor (SVM_L). Fastest wakeup times are possible with SVS_Land SVM_Lin full

performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVS_Land SVM_Lwhile

operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx

and MSP430x6xx Family User's Guide (SLAU208).

(2) This value represents the time from the wake-up event to the first active edge of MCLK. The wakeup time depends on the performance

mode of the low-side supervisor (SVS_L) and low-side monitor (SVM_L). In this case, the SVS_Land SVM_Lare in normal mode (low

current) mode when operating in AM, LPM0, and LPM1. Various options are available for SVS_Land SVM_Lwhile operating in LPM2,

LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx

Family User's Guide (SLAU208).

(3) This value represents the time from the wake-up event to the reset vector execution.

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7.28 Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK

f_TA

Timer_A input clock frequency

External: TACLK

1.8 V, 3 V

25 MHz

Duty cycle = 50% ±10%

All capture inputs, Minimum pulse

duration required for capture

t_TA,cap

Timer_A capture timing

1.8 V, 3 V

20

ns

7.29 Timer_B

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK

f_TB

Timer_B input clock frequency

External: TBCLK

1.8 V, 3 V

25 MHz

Duty cycle = 50% ±10%

All capture inputs, Minimum pulse

duration required for capture

t_TB,cap

Timer_B capture timing

1.8 V, 3 V

20

ns

7.30 USCI (UART Mode), Recommended Operating Conditions

PARAMETER

CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK

External: UCLK

f_USCI

USCI input clock frequency

f_SYSTEMMHz

Duty cycle = 50% ±10%

BITCLK clock frequency

(equals baud rate in MBaud)

f_BITCLK

1 MHz

7.31 USCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

2.2 V

3 V

MIN

TYP

MAX UNIT

50

600

ns

600

t_τ

UART receive deglitch time⁽¹⁾

50

(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are

correctly recognized, their duration should exceed the maximum specification of the deglitch time.

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7.32 USCI (SPI Master Mode), Recommended Operating Conditions

PARAMETER

CONDITIONS

Internal: SMCLK, ACLK

Duty cycle = 50% ±10%

V_CC

MIN

MAX UNIT

f_USCI

USCI input clock frequency

f_SYSTEMMHz

7.33 USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

(see Figure 7-11 and Figure 7-12)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

SMCLK, ACLK

f_USCI

USCI input clock frequency

f_SYSTEMMHz

Duty cycle = 50% ±10%

PMMCOREV = 0

1.8 V

3 V

55

38

30

25

0

t_SU,MI

SOMI input data setup time

SOMI input data hold time

SIMO output data valid time⁽²⁾

SIMO output data hold time⁽³⁾

ns

2.4 V

3 V

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

1.8 V

3 V

0

t_HD,MI

ns

2.4 V

3 V

0

1.8 V

3 V

20

UCLK edge to SIMO valid,

C_L= 20 pF, PMMCOREV = 0

18

ns

16

t_VALID,MO

2.4 V

3 V

UCLK edge to SIMO valid,

C_L= 20 pF, PMMCOREV = 3

15

1.8 V

3 V

–10

–8

C_L= 20 pF, PMMCOREV = 0

C_L= 20 pF, PMMCOREV = 3

t_HD,MO

ns

2.4 V

3 V

–10

–8

(1) f_UCxCLK= 1/2t_LO/HIwith t_LO/HI≥ max(t_{VALID,MO(USCI)}+ t_SU,SI(Slave), t_SU,MI(USCI)+ t_{VALID,SO(Slave)}).

For the slave parameters t_SU,SI(Slave)and t_{VALID,SO(Slave)}, refer to the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams

in Figure 7-11 and Figure 7-12.

(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data

on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure

7-11 and Figure 7-12.

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1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_LO/HI

t_SU,MI

t_HD,MI

SOMI

t_HD,MO

t_VALID,MO

SIMO

Figure 7-11. SPI Master Mode, CKPH = 0

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_LO/HI

t_HD,MI

t_SU,MI

SOMI

t_HD,MO

t_VALID,MO

SIMO

Figure 7-12. SPI Master Mode, CKPH = 1

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7.34 USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

(see Figure 7-13 and Figure 7-14)

PARAMETER

TEST CONDITIONS

V_CC

1.8 V

3 V

MIN

11

8

MAX UNIT

PMMCOREV = 0

t_STE,LEAD

t_STE,LAG

t_STE,ACC

t_STE,DIS

t_SU,SI

STE lead time, STE low to clock

ns

2.4 V

3 V

7

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

6

1.8 V

3 V

3

STE lag time, Last clock to STE high

ns

2.4 V

3 V

3

1.8 V

3 V

66

50

ns

36

STE access time, STE low to SOMI data out

2.4 V

3 V

30

1.8 V

3 V

23

ns

16

STE disable time, STE high to SOMI high

impedance

2.4 V

3 V

13

1.8 V

3 V

5

2

5

SIMO input data setup time

SIMO input data hold time

ns

2.4 V

3 V

1.8 V

3 V

t_HD,SI

ns

2.4 V

3 V

UCLK edge to SOMI valid,

C_L= 20 pF,

PMMCOREV = 0

1.8 V

76

60

3 V

2.4 V

3 V

t_VALID,SO

SOMI output data valid time⁽²⁾

SOMI output data hold time⁽³⁾

ns

UCLK edge to SOMI valid,

C_L= 20 pF,

PMMCOREV = 3

44

40

1.8 V

3 V

18

12

10

8

C_L= 20 pF,

PMMCOREV = 0

t_HD,SO

ns

2.4 V

3 V

C_L= 20 pF,

PMMCOREV = 3

(1) f_UCxCLK= 1/2t_LO/HIwith t_LO/HI≥ max(t_{VALID,MO(Master)}+ t_SU,SI(USCI), t_{SU,MI(Master)}+ t_{VALID,SO(USCI)}).

For the master parameters t_{SU,MI(Master)}and t_{VALID,MO(Master)}, refer to the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams

in Figure 7-13 and Figure 7-14.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure

7-13 and Figure 7-14.

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t_STE,LEAD

t_STE,LAG

STE

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_SU,SI

t_LO/HI

t_HD,SI

SIMO

t_HD,SO

t_VALID,SO

t_STE,ACC

t_STE,DIS

SOMI

Figure 7-13. SPI Slave Mode, CKPH = 0

t_STE,LEAD

t_STE,LAG

STE

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_LO/HI

t_HD,SI

t_SU,SI

SIMO

t_HD,MO

t_VALID,SO

t_STE,ACC

t_STE,DIS

SOMI

Figure 7-14. SPI Slave Mode, CKPH = 1

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7.35 USCI (I²C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see

Figure 7-15)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

Internal: SMCLK, ACLK

External: UCLK

f_USCI

USCI input clock frequency

f_SYSTEMMHz

Duty cycle = 50% ±10%

f_SCL

SCL clock frequency

2.2 V, 3 V

0

4.0

0.6

4.7

0.6

0

400

kHz

µs

f_SCL≤ 100 kHz

f_SCL> 100 kHz

f_SCL≤ 100 kHz

f_SCL> 100 kHz

t_HD,STA

Hold time (repeated) START

t_SU,STA

Setup time for a repeated START

2.2 V, 3 V

µs

t_HD,DAT

t_SU,DAT

Data hold time

Data setup time

2.2 V, 3 V

ns

250

4.0

0.6

50

f_SCL≤ 100 kHz

f_SCL> 100 kHz

t_SU,STO

Setup time for STOP

2.2 V, 3 V

µs

ns

2.2 V

3 V

600

t_SP

Pulse duration of spikes suppressed by input filter

50

t_HD,STA

t_SU,STA

t_HD,STA

t_BUF

SDA

SCL

t_LOW

t_HIGH

t_SP

t_SU,DAT

t_SU,STO

t_HD,DAT

Figure 7-15. I²C Mode Timing

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7.36 12-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

2.2

0

TYP

MAX UNIT

AV_CCand DV_CCare connected together,

AV_SSand DV_SSare connected together,

V_(AVSS)= V_(DVSS)= 0 V

Analog supply voltage,

full performance

AV_CC

3.6

V

V_(Ax)

Analog input voltage range⁽²⁾All ADC12 analog input pins Ax

AV_CC

155

220

25

V

2.2 V

3 V

125

150

20

Operating supply current into f_ADC12CLK= 5.0 MHz, ADC12ON = 1,

I_{ADC12_A}

µA

AVCC terminal⁽³⁾

REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0

C_I

R_I

Input capacitance

Only one terminal Ax can be selected at one time

0 V ≤ V_Ax≤ AV_CC

2.2 V

pF

Ω

Input MUX ON resistance

10

200

1900

(1) The leakage current is specified by the digital I/O input leakage.

(2) The analog input voltage range must be within the selected reference voltage range V_R+to V_R–for valid conversion results. If the

reference voltage is supplied by an external source or if the internal reference voltage is used and REFOUT = 1, then decoupling

capacitors are required. See Section 7.40 and Section 7.41.

(3) The internal reference supply current is not included in current consumption parameter I_{ADC12_A}

.

7.37 12-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

For specified performance of ADC12 linearity

parameters

f_ADC12CLK

f_ADC12OSC

2.2 V, 3 V

0.45

4.8

5.4 MHz

Internal ADC12

oscillator⁽³⁾

ADC12DIV = 0, f_ADC12CLK= f_ADC12OSC

2.2 V, 3 V

4.2

2.4

4.8

5.4 MHz

REFON = 0, Internal oscillator,

f_ADC12OSC= 4.2 MHz to 5.4 MHz

3.1

µs

t_CONVERT

Conversion time

Sampling time

External f_ADC12CLKfrom ACLK, MCLK or SMCLK,

ADC12SSEL ≠ 0

(2)

R_S= 400 Ω, R_I= 1000 Ω, C_I= 20 pF,

t_Sample

2.2 V, 3 V

1000

ns

(1)

τ = [R_S+ R_I] × C_I

(1) Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB:

t_Sample= ln(2ⁿ⁺¹) x (R_S+ R_I) × C_I+ 800 ns, where n = ADC resolution = 12, R_S= external source resistance

(2) 13 × ADC12DIV × 1/f_ADC12CLK

(3) The ADC12OSC is sourced directly from MODOSC inside the UCS.

7.38 12-Bit ADC, Linearity Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

1.4 V ≤ (V_eREF+– V_REF–/V_eREF–)min ≤ 1.6 V

1.6 V < (V_eREF+– V_REF–/V_eREF–)min ≤ V_AVCC

V_CC

MIN

TYP

MAX UNIT

±2

LSB

±1.7

Integral linearity error

(INL)

E_I

2.2 V, 3 V

Differential

linearity error (DNL)

(V_eREF+– V_REF–/V_eREF–)min ≤ (V_eREF+– V_REF–/V_eREF–),

C_VREF+= 20 pF

E_D

E_O

E_G

E_T

2.2 V, 3 V

±1.0 LSB

±2.0 LSB

±3.5 LSB

(V_eREF+– V_REF–/V_eREF–)min ≤ (V_eREF+– V_REF–/V_eREF–),

Internal impedance of source R_S< 100 Ω, C_VREF+= 20 pF

Offset error

±1.0

±1.4

(V_eREF+– V_REF–/V_eREF–)min ≤ (V_eREF+– V_REF–/V_eREF–),

C_VREF+= 20 pF

Gain error

(V_eREF+– V_REF–/V_eREF–)min ≤ (V_eREF+– V_REF–/V_eREF–),

C_VREF+= 20 pF

Total unadjusted error

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7.39 12-Bit ADC, Temperature Sensor and Built-In V_MID

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER⁽¹⁾

TEST CONDITIONS

V_CC

2.2 V

3 V

MIN

TYP

680

2.25

MAX UNIT

ADC12ON = 1, INCH = 0Ah,

T_A= 0°C

V_SENSOR

See ⁽²⁾

mV

2.2 V

3 V

TC_SENSOR

ADC12ON = 1, INCH = 0Ah

mV/°C

2.2 V

3 V

100

Sample time required if

channel 10 is selected⁽³⁾

ADC12ON = 1, INCH = 0Ah,

Error of conversion result ≤ 1 LSB

t_{SENSOR(sample)}

µs

AV_CCdivider at channel 11,

V_AVCCfactor

ADC12ON = 1, INCH = 0Bh

0.48

0.5

0.52 V_AVCC

V_MID

2.2 V

3 V

1.06

1.44

1.1

1.5

1.14

V

1.56

AV_CCdivider at channel 11

Sample time required if

channel 11 is selected⁽⁴⁾

ADC12ON = 1, INCH = 0Bh,

Error of conversion result ≤ 1 LSB

t_VMID(sample)

2.2 V, 3 V

1000

ns

(1) The temperature sensor is provided by the REF module. See the REF module parametric, I_REF+, regarding the current consumption of

the temperature sensor.

(2) The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in

temperature sensor. The TLV structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference

voltage levels. The sensor voltage can be computed as V_SENSE= TC_SENSOR× (Temperature,°C) + V_SENSOR, where TC_SENSORand

V_SENSORcan be computed from the calibration values for higher accuracy. See also the MSP430x5xx and MSP430x6xx Family User's

Guide (SLAU208).

(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t_SENSOR(on)

(4) The on-time t_VMID(on)is included in the sampling time t_VMID(sample); no additional on time is needed.

.

1000

950

900

850

800

750

700

650

600

550

500

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80

Ambient Temperature (°C)

Figure 7-16. Typical Temperature Sensor Voltage

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7.40 REF, External Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

1.4

0

TYP

MAX UNIT

(2)

V_eREF+

Positive external reference voltage input

V_eREF+> V_REF–/V_eREF–

AV_CC

1.2

V

(3)

V_REF–/V_eREF–

Negative external reference voltage input V_eREF+> V_REF–/V_eREF–

(V_eREF+

V_REF–/V_eREF–

–

Differential external reference voltage

V_eREF+> V_REF–/V_eREF–

input

(4)

1.4

AV_CC

V

)

1.4 V ≤ V_eREF+≤ V_AVCC

V_eREF–= 0 V

,

f_ADC12CLK= 5

MHz,ADC12SHTx = 1h,

Conversion rate 200 ksps

2.2 V, 3 V

±8.5

±26

I_VeREF+,

I_{VREF–/VeREF–}

Static input current

µA

µF

1.4 V ≤ V_eREF+≤ V_AVCC

V_eREF–= 0 V

f_ADC12CLK= 5

,

±1

MHz,ADC12SHTx = 8h,

Conversion rate 20 ksps

C_VREF+/-

Capacitance at VREF+ or VREF- terminal See ⁽⁵⁾

10

(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, C_i, is

also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the

recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.

(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced

accuracy requirements.

(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced

accuracy requirements.

(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with

reduced accuracy requirements.

(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external

reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).

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7.41 REF, Built-In Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

REFVSEL = {2} for 2.5 V,

REFON = REFOUT = 1, I_VREF+= 0 A

3 V

2.50 ±1.5%

1.98 ±1.5%

1.49 ±1.5%

Positive built-in reference

voltage output

REFVSEL = {1} for 2.0 V,

REFON = REFOUT = 1, I_VREF+= 0 A

V_REF+

3 V

V

REFVSEL = {0} for 1.5 V,

REFON = REFOUT = 1, I_VREF+= 0 A

2.2 V, 3 V

REFVSEL = {0} for 1.5 V, reduced

performance

1.8

AVCC minimum voltage,

Positive built-in reference

active

REFVSEL = {0} for 1.5 V

2.2

2.3

2.8

AV_CC(min)

REFVSEL = {1} for 2.0 V

REFVSEL = {2} for 2.5 V

REFON = 1, REFOUT = 0, REFBURST = 0

REFON = 1, REFOUT = 1, REFBURST = 0

3 V

100

0.9

140

1.5

µA

Operating supply current into

AVCC terminal^{(2) (3)}

I_REF+

mA

REFVSEL = {0, 1, 2},

Load-current regulation,

VREF+ terminal⁽⁴⁾

I_VREF+= +10 µA/–1000 µA,

AV_CC= AV_{CC (min)}for each reference level,

REFVSEL = (0, 1, 2}, REFON = REFOUT = 1

I_L(VREF+)

2500 µV/mA

Capacitance at VREF+ and

VREF- terminals

C_VREF+/-

REFON = REFOUT = 1⁽⁶⁾

20

100

pF

I_VREF+= 0 A,

REFVSEL = (0, 1, 2}, REFON = 1,

REFOUT = 0 or 1

Temperature coefficient of

built-in reference⁽⁵⁾

TC_REF+

30

50 ppm/°C

AV_CC= AV_{CC (min)}- AV_CC(max)

,

Power supply rejection ratio T_A= 25°C,

PSRR_DC

PSRR_AC

120

300

µV/V

(DC)

REFVSEL = (0, 1, 2}, REFON = 1,

REFOUT = 0 or 1

AV_CC= AV_{CC (min)}- AV_CC(max)

,

T_A= 25°C,

f = 1 kHz, ΔVpp = 100 mV,

REFVSEL = (0, 1, 2}, REFON = 1,

REFOUT = 0 or 1

Power supply rejection ratio

(AC)

6.4

mV/V

AV_CC= AV_{CC (min)}- AV_CC(max)

,

REFVSEL = (0, 1, 2}, REFOUT = 0,

REFON = 0 → 1

75

Settling time of reference

voltage⁽⁷⁾

t_SETTLE

µs

AV_CC= AV_{CC (min)}- AV_CC(max)

,

C_VREF= C_VREF(max),

REFVSEL = (0, 1, 2}, REFOUT = 1,

REFON = 0 → 1

(1) The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers,

one smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal, as

well as, used as the reference for the conversion and utilizes the larger buffer. When REFOUT = 0, the reference is only used as the

reference for the conversion and utilizes the smaller buffer.

(2) The internal reference current is supplied from terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a

conversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current

contribution of the larger buffer without external load.

(3) The temperature sensor is provided by the REF module. Its current is supplied from terminal AVCC and is equivalent to I_REF+with

REFON =1 and REFOUT = 0.

(4) Contribution only due to the reference and buffer including package. This does not include resistance due to other factors such as PCB

traces.

(5) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).

(6) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external

reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).

(7) The condition is that the error in a conversion started after t_REFONis less than ±0.5 LSB. The settling time depends on the external

capacitive load when REFOUT = 1.

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7.42 Flash Memory

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEST

CONDITIONS

PARAMETER

MIN

TYP

MAX UNIT

DV_{CC(PGM/ERASE)}Program and erase supply voltage

1.8

3.6

5

V

I_PGM

Average supply current from DVCC during program

3

6

mA

I_ERASE

Average supply current from DVCC during erase

15 mA

Average supply current from DVCC during mass erase or bank

erase

I_MERASE, I_BANK

t_CPT

6

Cumulative program time

See ⁽¹⁾

16

ms

cycles

years

µs

Program and erase endurance

Data retention duration

10⁴

100

64

10⁵

t_Retention

t_Word

T_J= 25°C

See ⁽²⁾

Word or byte program time

Block program time for first byte or word

85

65

t_{Block, 0}

See ⁽²⁾

49

µs

Block program time for each additional byte or word, except for last

byte or word

t_{Block, 1–(N–1)}

t_{Block, N}

See ⁽²⁾

37

55

23

49

73

32

µs

Block program time for last byte or word

Erase time for segment, mass erase, and bank erase when

available

t_Erase

ms

MCLK frequency in marginal read mode

(FCTL4.MRG0 = 1 or FCTL4. MRG1 = 1)

f_MCLK,MRG

0

1

MHz

(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming

methods: individual word or byte write and block write modes.

(2) These values are hardwired into the state machine of the flash controller.

7.43 JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEST

CONDITIONS

PARAMETER

Spy-Bi-Wire input frequency

MIN

TYP

MAX UNIT

f_SBW

2.2 V, 3 V

0

20 MHz

t_SBW,Low

t_{SBW, En}

t_SBW,Rst

Spy-Bi-Wire low clock pulse length

2.2 V, 3 V

0.025

15

1

µs

Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)⁽¹⁾

2.2 V, 3 V

Spy-Bi-Wire return to normal operation time

15

0

100

5

µs

2.2 V

3 V

MHz

f_TCK

TCK input frequency, 4-wire JTAG⁽²⁾

Internal pulldown resistance on TEST

0

10 MHz

80 kΩ

R_internal

2.2 V, 3 V

45

60

(1) Tools that access the Spy-Bi-Wire interface must wait for the t_SBW,Entime after pulling the TEST/SBWTCK pin high before applying the

first SBWTCK clock edge.

(2) f_TCKmay be restricted to meet the timing requirements of the module selected.

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8 Detailed Description

8.1 CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,

other than program-flow instructions, are performed as register operations in conjunction with seven addressing

modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register

operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant

generator, respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all

instructions.

The instruction set consists of the original 51 instructions with three formats and seven address modes and

additional instructions for the expanded address range. Each instruction can operate on word and byte data.

Program Counter

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R4

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15

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8.2 Operating Modes

The MSP430 has one active mode and six software selectable low-power modes of operation. An interrupt event

can wake up the device from any of the low-power modes, service the request, and restore back to the low-

power mode on return from the interrupt program.

The following operating modes can be configured by software:

•

Active mode (AM)

– All clocks are active

•

Low-power mode 0 (LPM0)

– CPU is disabled

– ACLK and SMCLK remain active

– MCLK is disabled

– FLL loop control remains active

Low-power mode 1 (LPM1)

– CPU is disabled

– FLL loop control is disabled

– ACLK and SMCLK remain active

– MCLK is disabled

Low-power mode 2 (LPM2)

– CPU is disabled

– MCLK, FLL loop control, and DCOCLK are disabled

– DCO DC generator remains enabled

– ACLK remains active

Low-power mode 3 (LPM3)

– CPU is disabled

– MCLK, FLL loop control, and DCOCLK are disabled

– DCO DC generator is disabled

– ACLK remains active

•

Low-power mode 4 (LPM4)

– CPU is disabled

– ACLK is disabled

– MCLK, FLL loop control, and DCOCLK are disabled

– DCO DC generator is disabled

– Crystal oscillator is stopped

– Complete data retention

Low-power mode 4.5 (LPM4.5)

– Internal regulator disabled

– No data retention

•

– Wake-up signal from RST, digital I/O

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8.3 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h. The vector

contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 8-1. Interrupt Sources, Flags, and Vectors

SYSTEM

INTERRUPT

WORD

ADDRESS

INTERRUPT SOURCE

INTERRUPT FLAG

PRIORITY

System Reset

Power-Up

External Reset

Watchdog Time-out, Password

Violation

WDTIFG, KEYV (SYSRSTIV)^{(1) (3)}

Reset

0FFFEh

63, highest

Flash Memory Password Violation

PMM Password Violation

System NMI

PMM

Vacant Memory Access

JTAG Mailbox

SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,

VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,

JMBOUTIFG (SYSSNIV)⁽¹⁾

(Non)maskable

0FFFCh

0FFFAh

62

61

User NMI

NMI

Oscillator Fault

NMIIFG, OFIFG, ACCVIFG (SYSUNIV)^{(1) (3)}

TBCCR0 CCIFG0 ⁽²⁾

Flash Memory Access Violation

TB0

Maskable

0FFF8h

0FFF6h

60

59

TBCCR1 CCIFG1 ... TBCCR6 CCIFG6,

TBIFG (TBIV)^{(1) (2)}

Watchdog Timer_A Interval Timer

Mode

WDTIFG

Maskable

0FFF4h

58

USCI_A0 Receive or Transmit

USCI_B0 Receive or Transmit

ADC12_A

UCA0RXIFG, UCA0TXIFG (UCA0IV)^{(1) (2)}

UCB0RXIFG, UCB0TXIFG (UCAB0IV)^{(1) (2)}

ADC12IFG0 ... ADC12IFG15 (ADC12IV)^{(1) (2)}

TA0CCR0 CCIFG0⁽²⁾

Maskable

0FFF2h

0FFF0h

0FFEEh

0FFECh

57

56

55

54

TA0

TA0CCR1 CCIFG1 ... TA0CCR4 CCIFG4,

TA0IFG (TA0IV)^{(1) (2)}

TA0

Maskable

0FFEAh

53

USCI_A2 Receive or Transmit

UCA2RXIFG, UCA2TXIFG (UCA2IV)^{(1) (2)}

UCB2RXIFG, UCB2TXIFG (UCB2IV)^{(1) (2)}

DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)^{(1) (2)}

TA1CCR0 CCIFG0⁽²⁾

Maskable

0FFE8h

0FFE6h

0FFE4h

0FFE2h

52

51

50

49

USCI_B2 Receive or Transmit

DMA

TA1

TA1CCR1 CCIFG1 ... TA1CCR2 CCIFG2,

TA1IFG (TA1IV)^{(1) (2)}

TA1

Maskable

0FFE0h

48

I/O Port P1

P1IFG.0 to P1IFG.7 (P1IV)^{(1) (2)}

UCA1RXIFG, UCA1TXIFG (UCA1IV)^{(1) (2)}

UCB1RXIFG, UCB1TXIFG (UCB1IV)^{(1) (2)}

UCA3RXIFG, UCA3TXIFG (UCA3IV)^{(1) (2)}

UCB3RXIFG, UCB3TXIFG (UCB3IV)^{(1) (2)}

P2IFG.0 to P2IFG.7 (P2IV)^{(1) (2)}

Maskable

0FFDEh

0FFDCh

0FFDAh

0FFD8h

0FFD6h

0FFD4h

47

46

45

44

43

42

USCI_A1 Receive or Transmit

USCI_B1 Receive or Transmit

USCI_A3 Receive or Transmit

USCI_B3 Receive or Transmit

I/O Port P2

RTCRDYIFG, RTCTEVIFG, RTCAIFG,

RT0PSIFG, RT1PSIFG (RTCIV)^{(1) (2)}

RTC_A

Maskable

0FFD2h

41

0FFD0h

⋮

40

Reserved

Reserved⁽⁴⁾

⋮

0FF80h

0, lowest

(1) Multiple source flags

(2) Interrupt flags are located in the module.

(3) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.

(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

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(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To

maintain compatibility with other devices, TI recommends reserving these locations.

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8.4 Memory Organization

Table 8-2 lists the memory locations and sizes for the device.

Table 8-2. Memory Organization

MSP430BT5190

Memory (flash)

Total Size

256KB

Main: interrupt vector

Main: code memory

Flash

00FFFFh–00FF80h

045BFFh–005C00h

Bank D

Bank C

Bank B

Bank A

64KB

03FFFFh–030000h

64KB

02FFFFh–020000h

Main: code memory

64KB

01FFFFh–010000h

64KB

045BFFh–040000h

00FFFFh–005C00h

Size

16KB

Sector 3

4KB

005BFFh–004C00h

Sector 2

Sector 1

Sector 0

Info A

4KB

RAM

004BFFh–003C00h

4KB

003BFFh–002C00h

4KB

002BFFh–001C00h

128 B

0019FFh–001980h

Info B

128 B

00197Fh–001900h

Information memory (flash)

Info C

Info D

BSL 3

BSL 2

BSL 1

BSL 0

Size

128 B

0018FFh–001880h

128 B

00187Fh–001800h

512 B

0017FFh–001600h

512 B

0015FFh–001400h

Bootstrap loader (BSL) memory (Flash)

512 B

0013FFh–001200h

512 B

0011FFh–001000h

4KB

Peripherals

000FFFh–000000h

8.5 Bootstrap Loader (BSL)

The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the

device memory through the BSL is protected by an user-defined password. Usage of the BSL requires four pins

as shown in Table 8-3. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/

SBWTCK pins. For further details on interfacing to development tools and device programmers, see the MSP430

Hardware Tools User's Guide (SLAU278). For a complete description of the features of the BSL and its

implementation, see the MSP430 Programming Via the Bootstrap Loader User's Guide (SLAU319).

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Table 8-3. BSL Pin Requirements and Functions

DEVICE SIGNAL

BSL FUNCTION

RST/NMI/SBWTDIO

Entry sequence signal

Data transmit

TEST/SBWTCK

P1.1

P1.2

VCC

VSS

Data receive

Power supply

Ground supply

8.6 JTAG Operation

8.6.1 JTAG Standard Interface

The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving

data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the

JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430

development tools and device programmers. The JTAG pin requirements are shown in Table 8-4. For further

details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's

Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see

MSP430 Programming Via the JTAG Interface (SLAU320).

Table 8-4. JTAG Pin Requirements and Functions

DEVICE SIGNAL

DIRECTION

FUNCTION

JTAG clock input

JTAG state control

JTAG data input; TCLK input

JTAG data output

Enable JTAG pins

External reset

PJ.3/TCK

IN

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

IN

OUT

IN

TEST/SBWTCK

RST/NMI/SBWTDIO

VCC

IN

Power supply

VSS

Ground supply

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8.6.2 Spy-Bi-Wire Interface

In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. Spy-

Bi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire

interface pin requirements are shown in Table 8-5. For further details on interfacing to development tools and

device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278). For a complete description of

the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface

(SLAU320).

Table 8-5. Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL

TEST/SBWTCK

RST/NMI/SBWTDIO

VCC

DIRECTION

FUNCTION

Spy-Bi-Wire clock input

Spy-Bi-Wire data input/output

Power supply

IN

IN, OUT

VSS

Ground supply

8.7 Flash Memory

The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the

CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the

flash memory include:

•

Flash memory has n segments of main memory and four segments of information memory (A to D) of

128 bytes each. Each segment in main memory is 512 bytes in size.

•

Segments 0 to n may be erased in one step, or each segment may be individually erased.

Segments A to D can be erased individually. Segments A to D are also called information memory.

Segment A can be locked separately.

8.8 RAM

The RAM is made up of n sectors. Each sector can be completely powered down to save leakage; however, all

data is lost. Features of the RAM include:

•

RAM has n sectors. The size of a sector can be found in Section 8.4.

Each sector 0 to n can be complete disabled; however, data retention is lost.

Each sector 0 to n automatically enters low-power retention mode when possible.

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8.9 Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all

instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide

(SLAU208).

8.9.1 Digital I/O

There are up to ten 8-bit I/O ports implemented: For 100-pin options, P1 through P10 are complete. P11 contains

three individual I/O ports. For 80-pin options, P1 through P7 are complete. P8 contains seven individual I/O

ports. P9 through P11 do not exist. Port PJ contains four individual I/O ports, common to all devices.

•

All individual I/O bits are independently programmable.

Any combination of input, output, and interrupt conditions is possible.

Pullup or pulldown on all ports is programmable.

Drive strength on all ports is programmable.

Edge-selectable interrupt and LPM4.5 wakeup input capability is available for all bits of ports P1 and P2.

Read and write access to port-control registers is supported by all instructions.

Ports can be accessed byte-wise (P1 through P11) or word-wise in pairs (PA through PF).

8.9.2 Oscillator and System Clock

The clock system is supported by the Unified Clock System (UCS) module that includes support for a 32-kHz

watch crystal oscillator (XT1 LF mode), an internal very-low-power low-frequency oscillator (VLO), an internal

trimmed low-frequency oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a high-

frequency crystal oscillator (XT1 HF mode or XT2). The UCS module is designed to meet the requirements of

both low system cost and low power consumption. The UCS module features digital frequency locked loop (FLL)

hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple

of the selected FLL reference frequency. The internal DCO provides a fast turnon clock source and stabilizes in

less than 5 µs. The UCS module provides the following clock signals:

•

Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal, a high-frequency crystal, the internal low-

frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally controlled

oscillator DCO.

•

Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made

available to ACLK.

Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by

same sources made available to ACLK.

ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.

8.9.3 Power-Management Module (PMM)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains

programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor

(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is

implemented to provide the proper internal reset signal to the device during power-on and power-off. The SVS

and SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply

voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not

automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.

8.9.4 Hardware Multiplier (MPY)

The multiplication operation is supported by a dedicated peripheral module. The module performs operations

with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication as well as signed

and unsigned multiply-and-accumulate operations.

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8.9.5 Real-Time Clock (RTC_A)

The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated real-

time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers that

can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Calendar mode

integrates an internal calendar which compensates for months with less than 31 days and includes leap year

correction. The RTC_A also supports flexible alarm functions and offset-calibration hardware.

8.9.6 Watchdog Timer (WDT_A)

The primary function of the WDT_A module is to perform a controlled system restart after a software problem

occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed

in an application, the module can be configured as an interval timer and can generate interrupts at selected time

intervals.

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8.9.7 System Module (SYS)

The SYS module handles many of the system functions within the device. These include power-on reset and

power-up clear handling, NMI source selection and management, reset interrupt vector generators, bootstrap

loader entry mechanisms, and configuration management (device descriptors). It also includes a data exchange

mechanism through JTAG called a JTAG mailbox that can be used in the application.

Table 8-6. System Module Interrupt Vector Registers

INTERRUPT VECTOR

ADDRESS

INTERRUPT EVENT

VALUE

PRIORITY

REGISTER

SYSRSTIV, System Reset

019Eh

No interrupt pending

Brownout (BOR)

RST/NMI (POR)

PMMSWBOR (BOR)

Wakeup from LPMx.5

Security violation (BOR)

SVSL (POR)

00h

02h

Highest

04h

06h

08h

0Ah

0Ch

SVSH (POR)

0Eh

SVML_OVP (POR)

SVMH_OVP (POR)

PMMSWPOR (POR)

WDT time-out (PUC)

WDT password violation (PUC)

KEYV flash password violation (PUC)

Reserved

10h

12h

14h

16h

18h

1Ah

1Ch

Peripheral area fetch (PUC)

PMM password violation (PUC)

Reserved

1Eh

20h

22h to 3Eh

00h

Lowest

Highest

SYSSNIV, System NMI

019Ch

No interrupt pending

SVMLIFG

02h

SVMHIFG

04h

SVSMLDLYIFG

SVSMHDLYIFG

VMAIFG

06h

08h

0Ah

JMBINIFG

0Ch

JMBOUTIFG

0Eh

SVMLVLRIFG

10h

SVMHVLRIFG

12h

Reserved

14h to 1Eh

00h

Lowest

Highest

SYSUNIV, User NMI

019Ah

No interrupt pending

NMIIFG

02h

OFIFG

04h

ACCVIFG

06h

Reserved

08h

Reserved

0Ah to 1Eh

Lowest

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8.9.8 DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU intervention.

For example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM.

Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces

system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move

data to or from a peripheral.

Table 8-7. DMA Trigger Assignments

CHANNEL

TRIGGER⁽¹⁾

0

1

2

0

DMAREQ

1

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

Reserved

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

Reserved

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

Reserved

2

3

4

5

6

7

8

Reserved

9

Reserved

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Reserved

UCA0RXIFG

UCA0TXIFG

UCB0RXIFG

UCB0TXIFG

UCA1RXIFG

UCA1TXIFG

UCB1RXIFG

UCB1TXIFG

ADC12IFGx

Reserved

UCA0RXIFG

UCA0TXIFG

UCB0RXIFG

UCB0TXIFG

UCA1RXIFG

UCA1TXIFG

UCB1RXIFG

UCB1TXIFG

ADC12IFGx

Reserved

UCA0RXIFG

UCA0TXIFG

UCB0RXIFG

UCB0TXIFG

UCA1RXIFG

UCA1TXIFG

UCB1RXIFG

UCB1TXIFG

ADC12IFGx

Reserved

MPY ready

DMA2IFG

MPY ready

DMA0IFG

MPY ready

DMA1IFG

DMAE0

(1) Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers do not

cause any DMA trigger event when selected.

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8.9.9 Universal Serial Communication Interface (USCI)

The USCI modules are used for serial data communication. The USCI module supports synchronous

communication protocols such as SPI (3-pin or 4-pin) and I²C, and asynchronous communication protocols such

as UART, enhanced UART with automatic baud-rate detection, and IrDA. Each USCI module contains two

portions, A and B.

The USCI_An module provides support for SPI (3-pin or 4-pin), UART, enhanced UART, or IrDA.

The USCI_Bn module provides support for SPI (3-pin or 4-pin) or I²C.

The MSP430BT5190 includes four complete USCI modules (n = 0 to 3).

8.9.10 TA0

TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 can support multiple

capture/compare registers, PWM outputs, and interval timing. It also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare

registers.

Table 8-8. TA0 Signal Connections

INPUT PIN

NUMBER

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

OUTPUT PIN NUMBER

PZ, ZQW

DEVICE INPUT MODULE INPUT

MODULE

BLOCK

SIGNAL

PZ, ZQW

17, H1-P1.0

TA0CLK

ACLK

TACLK

ACLK

Timer

CCR0

NA

SMCLK

TA0CLK

TA0.0

SMCLK

TACLK

CCI0A

CCI0B

17, H1-P1.0

18, H4-P1.1

57, H9-P8.0

18, H4-P1.1

57, H9-P8.0

TA0.0

TA0

TA0.0

ADC12 (internal)

ADC12SHSx = {1}

DV_SS

GND

DV_CC

TA0.1

DV_SS

DV_CC

TA0.2

DV_SS

DV_CC

TA0.3

DV_SS

DV_CC

TA0.4

DV_SS

DV_CC

V_CC

CCI1A

CCI1B

GND

19, J4-P1.2

58, H11-P8.1

CCR1

CCR2

CCR3

CCR4

TA1

TA2

TA3

TA4

TA0.1

TA0.2

TA0.3

TA0.4

V_CC

20, J1-P1.3

CCI2A

CCI2B

GND

20, J1-P1.3

59, H12-P8.2

V_CC

21, J2-P1.4

60, G9-P8.3

CCI3A

CCI3B

GND

21, J2-P1.4

60, G9-P8.3

V_CC

22, K1-P1.5

CCI4A

CCI4B

GND

22, K1-P1.5

61, G11-P8.4

V_CC

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8.9.11 TA1

TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 can support multiple

capture/compare registers, PWM outputs, and interval timing. It also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare

registers.

Table 8-9. TA1 Signal Connections

INPUT PIN

NUMBER

OUTPUT PIN

NUMBER

DEVICE INPUT

SIGNAL

MODULE INPUT

SIGNAL

MODULE

OUTPUT SIGNAL

DEVICE OUTPUT

SIGNAL

MODULE BLOCK

PZ, ZQW

25, M1-P2.0

TA1CLK

ACLK

SMCLK

TA1CLK

TA1.0

DV_SS

TACLK

ACLK

SMCLK

TACLK

CCI0A

CCI0B

GND

Timer

NA

TA0

TA1

TA2

NA

25, M1-P2.0

26, L2-P2.1

65, F11-P8.5

26, L2-P2.1

65, F11-P8.5

CCR0

CCR1

CCR2

TA1.0

TA1.1

TA1.2

DV_CC

V_CC

27, M2-P2.2

66, E11-P8.6

TA1.1

DV_SS

CCI1A

CCI1B

GND

27, M2-P2.2

66, E11-P8.6

DV_CC

V_CC

28, L3-P2.3

56, J12-P7.3

TA1.2

DV_SS

CCI2A

CCI2B

GND

28, L3-P2.3

56, J12-P7.3

DV_CC

V_CC

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8.9.12 TB0

TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. TB0 can support multiple

capture/compare registers, PWM outputs, and interval timing. It also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare

registers.

Table 8-10. TB0 Signal Connections

INPUT PIN

NUMBER

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

OUTPUT PIN NUMBER

PZ, ZQW

DEVICE INPUT MODULE INPUT

MODULE

BLOCK

SIGNAL

PZ, ZQW

50, M12-P4.7

TB0CLK

ACLK

TBCLK

ACLK

Timer

CCR0

NA

SMCLK

TB0CLK

TB0.0

SMCLK

TBCLK

CCI0A

50, M12-P4.7

43, J8-P4.0

ADC12 (internal)

ADC12SHSx = {2}

43, J8-P4.0

TB0.0

CCI0B

TB0

TB0.0

DV_SS

DV_CC

TB0.1

GND

V_CC

44, M9-P4.1

CCI1A

44, M9-P4.1

ADC12 (internal)

ADC12SHSx = {3}

TB0.1

CCI1B

CCR1

TB1

TB0.1

DV_SS

DV_CC

GND

V_CC

45, L9-P4.2

TB0.2

DV_SS

CCI2A

CCI2B

GND

V_CC

45, L9-P4.2

46, L10-P4.3

47, M10-P4.4

48, L11-P4.5

49, M11-P4.6

CCR2

CCR3

CCR4

CCR5

CCR6

TB2

TB3

TB4

TB5

TB6

TB0.2

TB0.3

TB0.4

TB0.5

TB0.6

DV_CC

46, L10-P4.3

TB0.3

DV_SS

CCI3A

CCI3B

GND

V_CC

DV_CC

47, M10-P4.4

TB0.4

DV_SS

CCI4A

CCI4B

GND

V_CC

DV_CC

48, L11-P4.5

TB0.5

DV_SS

CCI5A

CCI5B

GND

V_CC

DV_CC

49, M11-P4.6

TB0.6

ACLK (internal)

DV_SS

CCI6A

CCI6B

GND

V_CC

DV_CC

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8.9.13 ADC12_A

The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR

core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The conversion-

and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU

intervention.

8.9.14 CRC16

The CRC16 module produces a signature based on a sequence of entered data values and can be used for data

checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.

8.9.15 REF Voltage Reference

The reference module (REF) is responsible for generation of all critical reference voltages that can be used by

the various analog peripherals in the device.

8.9.16 Embedded Emulation Module (EEM) (L Version)

The EEM supports real-time in-system debugging. The L version of the EEM has the following features:

•

Eight hardware triggers or breakpoints on memory access

Two hardware triggers or breakpoints on CPU register write access

Up to ten hardware triggers can be combined to form complex triggers or breakpoints

Two cycle counters

Sequencer

State storage

Clock control on module level

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8.9.17 Peripheral File Map

Table 8-11 lists the base address for the registers of each module.

Table 8-11. Peripheral Map

OFFSET ADDRESS

RANGE

MODULE NAME

BASE ADDRESS

Special Functions (see Table 8-12)

PMM (see Table 8-13)

0100h

0120h

0140h

0150h

0158h

015Ch

0160h

0180h

01B0h

0200h

0220h

0240h

0260h

0280h

02A0h

0320h

0340h

0380h

03C0h

04A0h

04C0h

0500h

0510h

0520h

0530h

05C0h

05E0h

0600h

0620h

0640h

0660h

0680h

06A0h

0700h

000h-01Fh

000h-010h

000h-00Fh

000h-007h

000h-001h

000h-01Fh

000h-001h

000h-01Fh

000h-00Bh

000h-00Ah

000h-01Fh

000h-02Eh

000h-01Bh

000h-02Fh

000h-00Fh

000h-00Ah

000h-01Fh

000h-03Eh

Flash Control (see Table 8-14)

CRC16 (see Table 8-15)

RAM Control (see Table 8-16)

Watchdog (see Table 8-17)

UCS (see Table 8-18)

SYS (see Table 8-19)

Shared Reference (see Table 8-20)

Port P1, P2 (see Table 8-21)

Port P3, P4 (see Table 8-22)

Port P5, P6 (see Table 8-23)

Port P7, P8 (see Table 8-24)

Port P9, P10 (see Table 8-25)

Port P11 (see Table 8-26)

Port PJ (see Table 8-27)

TA0 (see Table 8-28)

TA1 (see Table 8-29)

TB0 (see Table 8-30)

Real-Time Clock (RTC_A) (see Table 8-31)

32-Bit Hardware Multiplier (see Table 8-32)

DMA General Control (see Table 8-33)

DMA Channel 0 (see Table 8-33)

DMA Channel 1 (see Table 8-33)

DMA Channel 2 (see Table 8-33)

USCI_A0 (see Table 8-34)

USCI_B0 (see Table 8-35)

USCI_A1 (see Table 8-36)

USCI_B1 (see Table 8-37)

USCI_A2 (see Table 8-38)

USCI_B2 (see Table 8-39)

USCI_A3 (see Table 8-40)

USCI_B3 (see Table 8-41)

ADC12_A (see Table 8-42)

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Table 8-12. Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION

REGISTER

OFFSET

SFR interrupt enable

SFR interrupt flag

SFRIE1

00h

02h

04h

SFRIFG1

SFR reset pin control

SFRRPCR

Table 8-13. PMM Registers (Base Address: 0120h)

REGISTER DESCRIPTION

REGISTER

OFFSET

PMM Control 0

PMMCTL0

00h

02h

04h

06h

0Ch

0Eh

10h

PMM control 1

PMMCTL1

SVSMHCTL

SVSMLCTL

PMMIFG

SVS high side control

SVS low side control

PMM interrupt flags

PMM interrupt enable

PMM power mode 5 control

PMMIE

PM5CTL0

Table 8-14. Flash Control Registers (Base Address: 0140h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Flash control 1

Flash control 3

Flash control 4

FCTL1

FCTL3

FCTL4

00h

04h

06h

Table 8-15. CRC16 Registers (Base Address: 0150h)

REGISTER DESCRIPTION

REGISTER

CRC data input

CRC16DI

00h

02h

04h

06h

CRC data input reverse byte

CRC initialization and result

CRC result reverse byte

CRCDIRB

CRCINIRES

CRCRESR

Table 8-16. RAM Control Registers (Base Address: 0158h)

REGISTER DESCRIPTION

REGISTER

OFFSET

RAM control 0

RCCTL0

00h

Table 8-17. Watchdog Registers (Base Address: 015Ch)

REGISTER DESCRIPTION

REGISTER

Watchdog timer control

WDTCTL

Table 8-18. UCS Registers (Base Address: 0160h)

REGISTER DESCRIPTION

REGISTER

UCS control 0

UCS control 1

UCS control 2

UCS control 3

UCS control 4

UCS control 5

UCS control 6

UCS control 7

UCS control 8

UCSCTL0

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

UCSCTL1

UCSCTL2

UCSCTL3

UCSCTL4

UCSCTL5

UCSCTL6

UCSCTL7

UCSCTL8

56

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Table 8-19. SYS Registers (Base Address: 0180h)

REGISTER DESCRIPTION

REGISTER

OFFSET

System control

SYSCTL

00h

02h

06h

08h

0Ah

0Ch

0Eh

18h

1Ah

1Ch

1Eh

Bootstrap loader configuration area

JTAG mailbox control

SYSBSLC

SYSJMBC

SYSJMBI0

SYSJMBI1

SYSJMBO0

SYSJMBO1

SYSBERRIV

SYSUNIV

SYSSNIV

JTAG mailbox input 0

JTAG mailbox input 1

JTAG mailbox output 0

JTAG mailbox output 1

Bus Error vector generator

User NMI vector generator

System NMI vector generator

Reset vector generator

SYSRSTIV

Table 8-20. Shared Reference Registers (Base Address: 01B0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Shared reference control

REFCTL

00h

Table 8-21. Port P1, P2 Registers (Base Address: 0200h)

REGISTER DESCRIPTION

REGISTER

Port P1 input

P1IN

00h

02h

04h

06h

08h

0Ah

0Eh

18h

1Ah

1Ch

01h

03h

05h

07h

09h

0Bh

1Eh

19h

1Bh

1Dh

Port P1 output

Port P1 direction

P1OUT

P1DIR

P1REN

P1DS

P1SEL

P1IV

Port P1 pullup/pulldown enable

Port P1 drive strength

Port P1 selection

Port P1 interrupt vector word

Port P1 interrupt edge select

Port P1 interrupt enable

Port P1 interrupt flag

P1IES

P1IE

P1IFG

P2IN

Port P2 input

Port P2 output

P2OUT

P2DIR

P2REN

P2DS

P2SEL

P2IV

Port P2 direction

Port P2 pullup/pulldown enable

Port P2 drive strength

Port P2 selection

Port P2 interrupt vector word

Port P2 interrupt edge select

Port P2 interrupt enable

Port P2 interrupt flag

P2IES

P2IE

P2IFG

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Table 8-22. Port P3, P4 Registers (Base Address: 0220h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P3 input

P3IN

00h

02h

04h

06h

08h

0Ah

01h

03h

05h

07h

09h

0Bh

Port P3 output

Port P3 direction

P3OUT

P3DIR

P3REN

P3DS

Port P3 pullup/pulldown enable

Port P3 drive strength

Port P3 selection

P3SEL

P4IN

Port P4 input

Port P4 output

P4OUT

P4DIR

P4REN

P4DS

Port P4 direction

Port P4 pullup/pulldown enable

Port P4 drive strength

Port P4 selection

P4SEL

Table 8-23. Port P5, P6 Registers (Base Address: 0240h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P5 input

P5IN

00h

02h

04h

06h

08h

0Ah

01h

03h

05h

07h

09h

0Bh

Port P5 output

P5OUT

P5DIR

P5REN

P5DS

Port P5 direction

Port P5 pullup/pulldown enable

Port P5 drive strength

Port P5 selection

P5SEL

P6IN

Port P6 input

Port P6 output

P6OUT

P6DIR

P6REN

P6DS

Port P6 direction

Port P6 pullup/pulldown enable

Port P6 drive strength

Port P6 selection

P6SEL

Table 8-24. Port P7, P8 Registers (Base Address: 0260h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P7 input

P7IN

00h

02h

04h

06h

08h

0Ah

01h

03h

05h

07h

09h

0Bh

Port P7 output

P7OUT

P7DIR

P7REN

P7DS

Port P7 direction

Port P7 pullup/pulldown enable

Port P7 drive strength

Port P7 selection

P7SEL

P8IN

Port P8 input

Port P8 output

P8OUT

P8DIR

P8REN

P8DS

Port P8 direction

Port P8 pullup/pulldown enable

Port P8 drive strength

Port P8 selection

P8SEL

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Table 8-25. Port P9, P10 Registers (Base Address: 0280h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P9 input

P9IN

00h

02h

04h

06h

08h

0Ah

01h

03h

05h

07h

09h

0Bh

Port P9 output

Port P9 direction

P9OUT

P9DIR

P9REN

P9DS

Port P9 pullup/pulldown enable

Port P9 drive strength

Port P9 selection

P9SEL

P10IN

Port P10 input

Port P10 output

P10OUT

P10DIR

P10REN

P10DS

Port P10 direction

Port P10 pullup/pulldown enable

Port P10 drive strength

Port P10 selection

P10SEL

Table 8-26. Port P11 Registers (Base Address: 02A0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P11 input

P11IN

00h

02h

04h

06h

08h

0Ah

Port P11 output

P11OUT

P11DIR

P11REN

P11DS

Port P11 direction

Port P11 pullup/pulldown enable

Port P11 drive strength

Port P11 selection

P11SEL

Table 8-27. Port J Registers (Base Address: 0320h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port PJ input

PJIN

00h

02h

04h

06h

08h

Port PJ output

PJOUT

PJDIR

PJREN

PJDS

Port PJ direction

Port PJ pullup/pulldown enable

Port PJ drive strength

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Table 8-28. TA0 Registers (Base Address: 0340h)

REGISTER DESCRIPTION

REGISTER

OFFSET

TA0 control

TA0CTL

00h

02h

04h

06h

08h

0Ah

10h

12h

14h

16h

18h

1Ah

20h

2Eh

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

Capture/compare control 3

Capture/compare control 4

TA0 counter register

TA0CCTL0

TA0CCTL1

TA0CCTL2

TA0CCTL3

TA0CCTL4

TA0R

Capture/compare register 0

Capture/compare register 1

Capture/compare register 2

Capture/compare register 3

Capture/compare register 4

TA0 expansion register 0

TA0 interrupt vector

TA0CCR0

TA0CCR1

TA0CCR2

TA0CCR3

TA0CCR4

TA0EX0

TA0IV

Table 8-29. TA1 Registers (Base Address: 0380h)

REGISTER DESCRIPTION

REGISTER

OFFSET

TA1 control

TA1CTL

00h

02h

04h

06h

10h

12h

14h

16h

20h

2Eh

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

TA1 counter register

TA1CCTL0

TA1CCTL1

TA1CCTL2

TA1R

Capture/compare register 0

Capture/compare register 1

Capture/compare register 2

TA1 expansion register 0

TA1 interrupt vector

TA1CCR0

TA1CCR1

TA1CCR2

TA1EX0

TA1IV

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Table 8-30. TB0 Registers (Base Address: 03C0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

TB0 control

TB0CTL

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

12h

14h

16h

18h

1Ah

1Ch

1Eh

20h

2Eh

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

Capture/compare control 3

Capture/compare control 4

Capture/compare control 5

Capture/compare control 6

TB0 register

TB0CCTL0

TB0CCTL1

TB0CCTL2

TB0CCTL3

TB0CCTL4

TB0CCTL5

TB0CCTL6

TB0R

Capture/compare register 0

Capture/compare register 1

Capture/compare register 2

Capture/compare register 3

Capture/compare register 4

Capture/compare register 5

Capture/compare register 6

TB0 expansion register 0

TB0 interrupt vector

TB0CCR0

TB0CCR1

TB0CCR2

TB0CCR3

TB0CCR4

TB0CCR5

TB0CCR6

TB0EX0

TB0IV

Table 8-31. Real-Time Clock Registers (Base Address: 04A0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

RTC control 0

RTCCTL0

00h

01h

02h

03h

08h

0Ah

0Ch

0Dh

0Eh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

RTC control 1

RTCCTL1

RTC control 2

RTCCTL2

RTC control 3

RTCCTL3

RTC prescaler 0 control

RTC prescaler 1 control

RTC prescaler 0

RTC prescaler 1

RTC interrupt vector word

RTCPS0CTL

RTCPS1CTL

RTCPS0

RTCPS1

RTCIV

RTC seconds/counter register 1

RTC minutes/counter register 2

RTC hours/counter register 3

RTC day of week/counter register 4

RTC days

RTCSEC/RTCNT1

RTCMIN/RTCNT2

RTCHOUR/RTCNT3

RTCDOW/RTCNT4

RTCDAY

RTC month

RTCMON

RTC year low

RTCYEARL

RTCYEARH

RTCAMIN

RTC year high

RTC alarm minutes

RTC alarm hours

RTCAHOUR

RTCADOW

RTCADAY

RTC alarm day of week

RTC alarm days

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Table 8-32. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

16-bit operand 1 – multiply

MPY

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

12h

14h

16h

18h

1Ah

1Ch

1Eh

20h

22h

24h

26h

28h

2Ah

2Ch

16-bit operand 1 – signed multiply

16-bit operand 1 – multiply accumulate

16-bit operand 1 – signed multiply accumulate

16-bit operand 2

MPYS

MAC

MACS

OP2

16 × 16 result low word

RESLO

RESHI

16 × 16 result high word

16 × 16 sum extension register

SUMEXT

MPY32L

MPY32H

MPYS32L

MPYS32H

MAC32L

MAC32H

MACS32L

MACS32H

OP2L

32-bit operand 1 – multiply low word

32-bit operand 1 – multiply high word

32-bit operand 1 – signed multiply low word

32-bit operand 1 – signed multiply high word

32-bit operand 1 – multiply accumulate low word

32-bit operand 1 – multiply accumulate high word

32-bit operand 1 – signed multiply accumulate low word

32-bit operand 1 – signed multiply accumulate high word

32-bit operand 2 – low word

32-bit operand 2 – high word

OP2H

32 × 32 result 0 – least significant word

32 × 32 result 1

RES0

RES1

32 × 32 result 2

RES2

32 × 32 result 3 – most significant word

MPY32 control register 0

RES3

MPY32CTL0

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Table 8-33. DMA Registers (Base Address DMA General Control: 0500h,

DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)

REGISTER DESCRIPTION

REGISTER

OFFSET

DMA channel 0 control

DMA0CTL

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Eh

DMA channel 0 source address low

DMA channel 0 source address high

DMA channel 0 destination address low

DMA channel 0 destination address high

DMA channel 0 transfer size

DMA0SAL

DMA0SAH

DMA0DAL

DMA0DAH

DMA0SZ

DMA channel 1 control

DMA1CTL

DMA1SAL

DMA1SAH

DMA1DAL

DMA1DAH

DMA1SZ

DMA channel 1 source address low

DMA channel 1 source address high

DMA channel 1 destination address low

DMA channel 1 destination address high

DMA channel 1 transfer size

DMA channel 2 control

DMA2CTL

DMA2SAL

DMA2SAH

DMA2DAL

DMA2DAH

DMA2SZ

DMA channel 2 source address low

DMA channel 2 source address high

DMA channel 2 destination address low

DMA channel 2 destination address high

DMA channel 2 transfer size

DMA module control 0

DMACTL0

DMACTL1

DMACTL2

DMACTL3

DMACTL4

DMAIV

DMA module control 1

DMA module control 2

DMA module control 3

DMA module control 4

DMA interrupt vector

Table 8-34. USCI_A0 Registers (Base Address: 05C0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI control 1

UCA0CTL1

00h

01h

06h

07h

08h

0Ah

0Ch

0Eh

10h

12h

13h

1Ch

1Dh

1Eh

USCI control 0

UCA0CTL0

UCA0BR0

USCI baud rate 0

USCI baud rate 1

UCA0BR1

USCI modulation control

USCI status

UCA0MCTL

UCA0STAT

UCA0RXBUF

UCA0TXBUF

UCA0ABCTL

UCA0IRTCTL

UCA0IRRCTL

UCA0IE

USCI receive buffer

USCI transmit buffer

USCI LIN control

USCI IrDA transmit control

USCI IrDA receive control

USCI interrupt enable

USCI interrupt flags

USCI interrupt vector word

UCA0IFG

UCA0IV

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Table 8-35. USCI_B0 Registers (Base Address: 05E0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI synchronous control 1

USCI synchronous control 0

USCI synchronous bit rate 0

USCI synchronous bit rate 1

USCI synchronous status

UCB0CTL1

00h

01h

06h

07h

0Ah

0Ch

0Eh

10h

12h

1Ch

1Dh

1Eh

UCB0CTL0

UCB0BR0

UCB0BR1

UCB0STAT

UCB0RXBUF

UCB0TXBUF

UCB0I2COA

UCB0I2CSA

UCB0IE

USCI synchronous receive buffer

USCI synchronous transmit buffer

USCI I2C own address

USCI I2C slave address

USCI interrupt enable

USCI interrupt flags

UCB0IFG

USCI interrupt vector word

UCB0IV

Table 8-36. USCI_A1 Registers (Base Address: 0600h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI control 1

UCA1CTL1

00h

01h

06h

07h

08h

0Ah

0Ch

0Eh

10h

12h

13h

1Ch

1Dh

1Eh

USCI control 0

UCA1CTL0

UCA1BR0

USCI baud rate 0

USCI baud rate 1

UCA1BR1

USCI modulation control

USCI status

UCA1MCTL

UCA1STAT

UCA1RXBUF

UCA1TXBUF

UCA1ABCTL

UCA1IRTCTL

UCA1IRRCTL

UCA1IE

USCI receive buffer

USCI transmit buffer

USCI LIN control

USCI IrDA transmit control

USCI IrDA receive control

USCI interrupt enable

USCI interrupt flags

USCI interrupt vector word

UCA1IFG

UCA1IV

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Table 8-37. USCI_B1 Registers (Base Address: 0620h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI synchronous control 1

USCI synchronous control 0

USCI synchronous bit rate 0

USCI synchronous bit rate 1

USCI synchronous status

UCB1CTL1

00h

01h

06h

07h

0Ah

0Ch

0Eh

10h

12h

1Ch

1Dh

1Eh

UCB1CTL0

UCB1BR0

UCB1BR1

UCB1STAT

UCB1RXBUF

UCB1TXBUF

UCB1I2COA

UCB1I2CSA

UCB1IE

USCI synchronous receive buffer

USCI synchronous transmit buffer

USCI I2C own address

USCI I2C slave address

USCI interrupt enable

USCI interrupt flags

UCB1IFG

USCI interrupt vector word

UCB1IV

Table 8-38. USCI_A2 Registers (Base Address: 0640h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI control 1

UCA2CTL1

00h

01h

06h

07h

08h

0Ah

0Ch

0Eh

10h

12h

13h

1Ch

1Dh

1Eh

USCI control 0

UCA2CTL0

UCA2BR0

USCI baud rate 0

USCI baud rate 1

UCA2BR1

USCI modulation control

USCI status

UCA2MCTL

UCA2STAT

UCA2RXBUF

UCA2TXBUF

UCA2ABCTL

UCA2IRTCTL

UCA2IRRCTL

UCA2IE

USCI receive buffer

USCI transmit buffer

USCI LIN control

USCI IrDA transmit control

USCI IrDA receive control

USCI interrupt enable

USCI interrupt flags

USCI interrupt vector word

UCA2IFG

UCA2IV

Table 8-39. USCI_B2 Registers (Base Address: 0660h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI synchronous control 1

USCI synchronous control 0

USCI synchronous bit rate 0

USCI synchronous bit rate 1

USCI synchronous status

UCB2CTL1

00h

01h

06h

07h

0Ah

0Ch

0Eh

10h

12h

1Ch

1Dh

1Eh

UCB2CTL0

UCB2BR0

UCB2BR1

UCB2STAT

UCB2RXBUF

UCB2TXBUF

UCB2I2COA

UCB2I2CSA

UCB2IE

USCI synchronous receive buffer

USCI synchronous transmit buffer

USCI I2C own address

USCI I2C slave address

USCI interrupt enable

USCI interrupt flags

UCB2IFG

USCI interrupt vector word

UCB2IV

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Table 8-40. USCI_A3 Registers (Base Address: 0680h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI control 1

UCA3CTL1

00h

01h

06h

07h

08h

0Ah

0Ch

0Eh

10h

12h

13h

1Ch

1Dh

1Eh

USCI control 0

UCA3CTL0

UCA3BR0

USCI baud rate 0

USCI baud rate 1

UCA3BR1

USCI modulation control

USCI status

UCA3MCTL

UCA3STAT

UCA3RXBUF

UCA3TXBUF

UCA3ABCTL

UCA3IRTCTL

UCA3IRRCTL

UCA3IE

USCI receive buffer

USCI transmit buffer

USCI LIN control

USCI IrDA transmit control

USCI IrDA receive control

USCI interrupt enable

USCI interrupt flags

USCI interrupt vector word

UCA3IFG

UCA3IV

Table 8-41. USCI_B3 Registers (Base Address: 06A0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI synchronous control 1

USCI synchronous control 0

USCI synchronous bit rate 0

USCI synchronous bit rate 1

USCI synchronous status

UCB3CTL1

00h

01h

06h

07h

0Ah

0Ch

0Eh

10h

12h

1Ch

1Dh

1Eh

UCB3CTL0

UCB3BR0

UCB3BR1

UCB3STAT

UCB3RXBUF

UCB3TXBUF

UCB3I2COA

UCB3I2CSA

UCB3IE

USCI synchronous receive buffer

USCI synchronous transmit buffer

USCI I2C own address

USCI I2C slave address

USCI interrupt enable

USCI interrupt flags

UCB3IFG

USCI interrupt vector word

UCB3IV

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Table 8-42. ADC12_A Registers (Base Address: 0700h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Control register 0

ADC12CTL0

00h

02h

04h

0Ah

0Ch

0Eh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

22h

24h

26h

28h

2Ah

2Ch

2Eh

30h

32h

34h

36h

38h

3Ah

3Ch

3Eh

Control register 1

ADC12CTL1

Control register 2

ADC12CTL2

Interrupt-flag register

Interrupt-enable register

Interrupt-vector-word register

ADC12IFG

ADC12IE

ADC12IV

ADC memory-control register 0

ADC memory-control register 1

ADC memory-control register 2

ADC memory-control register 3

ADC memory-control register 4

ADC memory-control register 5

ADC memory-control register 6

ADC memory-control register 7

ADC memory-control register 8

ADC memory-control register 9

ADC memory-control register 10

ADC memory-control register 11

ADC memory-control register 12

ADC memory-control register 13

ADC memory-control register 14

ADC memory-control register 15

Conversion memory 0

ADC12MCTL0

ADC12MCTL1

ADC12MCTL2

ADC12MCTL3

ADC12MCTL4

ADC12MCTL5

ADC12MCTL6

ADC12MCTL7

ADC12MCTL8

ADC12MCTL9

ADC12MCTL10

ADC12MCTL11

ADC12MCTL12

ADC12MCTL13

ADC12MCTL14

ADC12MCTL15

ADC12MEM0

ADC12MEM1

ADC12MEM2

ADC12MEM3

ADC12MEM4

ADC12MEM5

ADC12MEM6

ADC12MEM7

ADC12MEM8

ADC12MEM9

ADC12MEM10

ADC12MEM11

ADC12MEM12

ADC12MEM13

ADC12MEM14

ADC12MEM15

Conversion memory 1

Conversion memory 2

Conversion memory 3

Conversion memory 4

Conversion memory 5

Conversion memory 6

Conversion memory 7

Conversion memory 8

Conversion memory 9

Conversion memory 10

Conversion memory 11

Conversion memory 12

Conversion memory 13

Conversion memory 14

Conversion memory 15

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8.10 Input/Output Schematics

8.10.1 Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger

Pad Logic

P1REN.x

DV_SS

DV_CC

0

1

P1DIR.x

0

1

Direction

0: Input

1: Output

P1OUT.x

0

1

Module X OUT

P1.0/TA0CLK/ACLK

P1.1/TA0.0

P1.2/TA0.1

P1.3/TA0.2

P1.4/TA0.3

P1.5/TA0.4

P1.6/SMCLK

P1.7

P1DS.x

0: Low drive

1: High drive

P1SEL.x

P1IN.x

EN

D

Module X IN

P1IRQ.x

P1IE.x

EN

Q

P1IFG.x

Set

P1SEL.x

P1IES.x

Interrupt

Edge

Select

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Table 8-43. Port P1 (P1.0 to P1.7) Pin Functions

CONTROL BITS OR SIGNALS

PIN NAME (P1.x)

x

FUNCTION

P1DIR.x

P1SEL.x

P1.0/TA0CLK/ACLK

0

P1.0 (I/O)

TA0.TA0CLK

ACLK

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

P1.1/TA0.0

1

2

3

4

5

P1.1 (I/O)

TA0.CCI0A

TA0.0

I: 0; O: 1

0

1

P1.2/TA0.1

P1.2 (I/O)

TA0.CCI1A

TA0.1

I: 0; O: 1

0

1

P1.3/TA0.2

P1.3 (I/O)

TA0.CCI2A

TA0.2

I: 0; O: 1

0

1

P1.4/TA0.3

P1.4 (I/O)

TA0.CCI3A

TA0.3

I: 0; O: 1

0

1

P1.5/TA0.4

P1.5 (I/O)

TA0.CCI4A

TA0.4

I: 0; O: 1

0

1

P1.6/SMCLK

P1.7

6

7

P1.6 (I/O)

SMCLK

I: 0; O: 1

1

P1.7 (I/O)

I: 0; O: 1

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8.10.2 Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger

Pad Logic

P2REN.x

DV_SS

DV_CC

0

1

P2DIR.x

0

1

Direction

0: Input

1: Output

P2OUT.x

0

1

Module X OUT

P2.0/TA1CLK/MCLK

P2.1/TA1.0

P2.2/TA1.1

P2.3/TA1.2

P2.4/RTCCLK

P2.5

P2.6/ACLK

P2DS.x

0: Low drive

1: High drive

P2SEL.x

P2IN.x

EN

D

P2.7/ADC12CLK/DMAE0

Module X IN

P2IRQ.x

P2IE.x

EN

Q

P2IFG.x

Set

P2SEL.x

P2IES.x

Interrupt

Edge

Select

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Table 8-44. Port P2 (P2.0 to P2.7) Pin Functions

CONTROL BITS OR SIGNALS

PIN NAME (P2.x)

x

FUNCTION

P2DIR.x

P2SEL.x

P2.0/TA1CLK/MCLK

0

P2.0 (I/O)

TA1CLK

MCLK

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

P2.1/TA1.0

1

2

3

4

P2.1 (I/O)

TA1.CCI0A

TA1.0

I: 0; O: 1

0

1

P2.2/TA1.1

P2.2 (I/O)

TA1.CCI1A

TA1.1

I: 0; O: 1

0

1

P2.3/TA1.2

P2.3 (I/O)

TA1.CCI2A

TA1.2

I: 0; O: 1

0

1

P2.4/RTCCLK

P2.4 (I/O)

RTCCLK

P2.5 (I/O

P2.6 (I/O)

ACLK

I: 0; O: 1

1

P2.5

5

6

I: 0; O: 1

P2.6/ACLK

I: 0; O: 1

1

P2.7/ADC12CLK/DMAE0

7

P2.7 (I/O)

DMAE0

I: 0; O: 1

0

1

ADC12CLK

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8.10.3 Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger

Pad Logic

P3REN.x

DV_SS

DV_CC

0

1

P3DIR.x

0

1

Direction

0: Input

1: Output

P3OUT.x

0

1

Module X OUT

P3.0/UB0STE/UCA0CLK

P3DS.x

0: Low drive

1: High drive

P3.1/UCB0SIMO/UCB0SDA

P3.2/UCB0SOMI/UCB0SCL

P3.3/USC0CLK/UCA0STE

P3.4/UCA0TXD/UCA0SIMO

P3.5/UCA0RXD/UCA0SOMI

P3.6/UCB1STE/UCA1CLK

P3.7/UCB1SIMO/UCB1SDA

P3SEL.x

P3IN.x

EN

D

Module X IN

Table 8-45. Port P3 (P3.0 to P3.7) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P3.x)

x

FUNCTION

P3DIR.x

P3SEL.x

P3.0/UCB0STE/UCA0CLK

0

P3.0 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

UCB0STE/UCA0CLK^{(2) (4)}

X

P3.1/UCB0SIMO/UCB0SDA

P3.2/UCB0SOMI/UCB0SCL

P3.3/UCB0CLK/UCA0STE

P3.4/UCA0TXD/UCA0SIMO

P3.5/UCA0RXD/UCA0SOMI

P3.6/UCB1STE/UCA1CLK

P3.7/UCB1SIMO/UCB1SDA

1

2

3

4

5

6

7

P3.1 (I/O)

I: 0; O: 1

UCB0SIMO/UCB0SDA^{(2) (3)}

P3.2 (I/O)

X

I: 0; O: 1

UCB0SOMI/UCB0SCL^{(2) (3)}

X

P3.3 (I/O)

I: 0; O: 1

UCB0CLK/UCA0STE⁽²⁾

P3.4 (I/O)

X

I: 0; O: 1

UCA0TXD/UCA0SIMO⁽²⁾

X

P3.5 (I/O)

I: 0; O: 1

UCA0RXD/UCA0SOMI⁽²⁾

P3.6 (I/O)

X

I: 0; O: 1

X

UCB1STE/UCA1CLK^{(2) (5)}

P3.7 (I/O)

I: 0; O: 1

X

UCB1SIMO/UCB1SDA^{(2) (3)}

(1) X = Don't care

(2) The pin direction is controlled by the USCI module.

(3) If the I2C functionality is selected, the output drives only the logical 0 to V_SSlevel.

(4) UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI B0 is forced to

3-wire SPI mode if 4-wire SPI mode is selected.

(5) UCA1CLK function takes precedence over UCB1STE function. If the pin is required as UCA1CLK input or output, USCI B1 is forced to

3-wire SPI mode if 4-wire SPI mode is selected.

72

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8.10.4 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger

Pad Logic

P4REN.x

DV_SS

DV_CC

0

1

P4DIR.x

0

1

Direction

0: Input

1: Output

P4OUT.x

0

1

Module X OUT

P4.0/TB0.0

P4.1/TB0.1

P4.2/TB0.2

P4.3/TB0.3

P4.4/TB0.4

P4.5/TB0.5

P4DS.x

0: Low drive

1: High drive

P4SEL.x

P4IN.x

P4.6/TB0.6

P4.7/TB0CLK/SMCLK

EN

D

Module X IN

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Table 8-46. Port P4 (P4.0 to P4.7) Pin Functions

CONTROL BITS OR SIGNALS

PIN NAME (P4.x)

P4.0/TB0.0

x

FUNCTION

P4DIR.x

P4SEL.x

0

4.0 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

TB0.CCI0A and TB0.CCI0B

TB0.0⁽¹⁾

0

1

P4.1/TB0.1

1

2

3

4

5

6

7

4.1 (I/O)

I: 0; O: 1

TB0.CCI1A and TB0.CCI1B

TB0.1⁽¹⁾

0

1

P4.2/TB0.2

4.2 (I/O)

I: 0; O: 1

TB0.CCI2A and TB0.CCI2B

TB0.2⁽¹⁾

0

1

P4.3/TB0.3

4.3 (I/O)

I: 0; O: 1

TB0.CCI3A and TB0.CCI3B

TB0.3⁽¹⁾

0

1

P4.4/TB0.5

4.4 (I/O)

I: 0; O: 1

TB0.CCI4A and TB0.CCI4B

TB0.4⁽¹⁾

0

1

P4.5/TB0.5

4.5 (I/O)

I: 0; O: 1

TB0.CCI5A and TB0.CCI5B

TB0.5⁽¹⁾

0

1

P4.6/TB0.6

4.6 (I/O)

I: 0; O: 1

TB0.CCI6A and TB0.CCI6B

TB0.6⁽¹⁾

0

1

P4.7/TB0CLK/SMCLK

4.7 (I/O)

I: 0; O: 1

TB0CLK

0

1

SMCLK

(1) Setting TBOUTH causes all Timer_B configured outputs to be set to high impedance.

74

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8.10.5 Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger

Pad Logic

To ADC12

INCHx = y

To/From

ADC12 Reference

P5REN.x

DV_SS

DV_CC

0

1

P5DIR.x

0

1

P5OUT.x

0

1

Module X OUT

P5.0/A8/VREF+/VeREF+

P5.1/A9/VREF–/VeREF–

P5DS.x

0: Low drive

1: High drive

P5SEL.x

P5IN.x

Bus

Keeper

EN

D

Module X IN

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Table 8-47. Port P5 (P5.0 and P5.1) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P5.x)

x

FUNCTION

P5DIR.x

P5SEL.x

REFOUT

P5.0/A8/VREF+/VeREF+

0

P5.0 (I/O)⁽²⁾

A8/VeREF+⁽³⁾

A8/VREF+⁽⁴⁾

P5.1 (I/O)⁽²⁾

A9/VeREF–⁽⁵⁾

A9/VREF–⁽⁶⁾

I: 0; O: 1

0

1

0

1

X

0

1

X

0

1

X

P5.1/A9/VREF–/VeREF–

1

I: 0; O: 1

X

(1) X = Don't care

(2) Default condition

(3) Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A. Channel A8, when

selected with the INCHx bits, is connected to the VREF+/VeREF+ pin.

(4) Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. The ADC12_A, VREF+ reference is available at the pin. Channel A8, when selected with the INCHx bits, is connected

to the VREF+/VeREF+ pin.

(5) Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A. Channel A9, when selected

with the INCHx bits, is connected to the VREF-/VeREF- pin.

(6) Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. The ADC12_A, VREF– reference is available at the pin. Channel A9, when selected with the INCHx bits, is connected

to the VREF-/VeREF- pin.

76

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8.10.6 Port P5, P5.2, Input/Output With Schmitt Trigger

Pad Logic

To XT2

P5REN.2

DV_SS

DV_CC

0

1

P5DIR.2

0

1

P5OUT.2

0

1

Module X OUT

P5.2/XT2IN

P5DS.2

0: Low drive

1: High drive

P5SEL.2

P5IN.2

Bus

Keeper

EN

D

Module X IN

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8.10.7 Port P5, P5.3, Input/Output With Schmitt Trigger

Pad Logic

To XT2

P5REN.3

DV_SS

DV_CC

0

1

P5DIR.3

0

1

P5OUT.3

0

1

Module X OUT

P5SEL.2

P5.3/XT2OUT

P5DS.3

0: Low drive

1: High drive

XT2BYPASS

P5SEL.3

P5IN.3

Bus

Keeper

EN

D

Module X IN

Table 8-48. Port P5 (P5.2 and P5.3) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P5.x)

x

FUNCTION

P5DIR.x

P5SEL.2

P5SEL.3

XT2BYPASS

P5.2/XT2IN

2

P5.2 (I/O)

I: 0; O: 1

0

1

0

1

X

0

X

0

1

X

0

1

XT2IN crystal mode⁽²⁾

XT2IN bypass mode⁽²⁾

P5.3 (I/O)

X

P5.3/XT2OUT

3

I: 0; O: 1

XT2OUT crystal mode⁽³⁾

P5.3 (I/O)⁽³⁾

X

0

(1) X = Don't care

(2) Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal

mode or bypass mode.

(3) Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as

general-purpose I/O.

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8.10.8 Port P5, P5.4 to P5.7, Input/Output With Schmitt Trigger

Pad Logic

P5REN.x

DV_SS

DV_CC

0

1

P5DIR.x

0

1

Direction

0: Input

1: Output

P5OUT.x

0

1

Module X OUT

P5.4/UCB1SOMI/UCB1SCL

P5.5/UCB1CLK/UCA1STE

P5.6/UCA1TXD/UCA1SIMO

P5.7/UCA1RXD/UCA1SOMI

P5DS.x

0: Low drive

1: High drive

P5SEL.x

P5IN.x

EN

D

Module X IN

Table 8-49. Port P5 (P5.4 to P5.7) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P5.x)

x

FUNCTION

P5DIR.x

I: 0; O: 1

X

P5SEL.x

P5.4/UCB1SOMI/UCB1SCL

4

P5.4 (I/O)

0

1

0

1

0

1

0

1

UCB1SOMI/UCB1SCL^{(2) (3)}

P5.5/UCB1CLK/UCA1STE

P5.6/UCA1TXD/UCA1SIMO

P5.7/UCA1RXD/UCA1SOMI

5

6

7

P5.5 (I/O)

I: 0; O: 1

X

UCB1CLK/UCA1STE^{(2) (4)}

P5.6 (I/O)

I: 0; O: 1

X

UCA1TXD/UCA1SIMO⁽²⁾

P5.7 (I/O)

I: 0; O: 1

X

UCA1RXD/UCA1SOMI⁽²⁾

(1) X = Don't care

(2) The pin direction is controlled by the USCI module.

(3) If the I2C functionality is selected, the output drives only the logical 0 to V_SSlevel.

(4) UCB1CLK function takes precedence over UCA1STE function. If the pin is required as UCB1CLK input or output, USCI A1 is forced to

3-wire SPI mode if 4-wire SPI mode is selected.

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8.10.9 Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger

Pad Logic

To ADC12

INCHx = y

P6REN.x

DV_SS

DV_CC

0

1

P6DIR.x

0

1

P6OUT.x

0

1

Module X OUT

P6.0/A0

P6DS.x

0: Low drive

1: High drive

P6.1/A1

P6.2/A2

P6.3/A3

P6.4/A4

P6.5/A5

P6.6/A6

P6.7/A7

P6SEL.x

P6IN.x

Bus

Keeper

EN

D

Module X IN

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Table 8-50. Port P6 (P6.0 to P6.7) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P6.x)

x

FUNCTION

P6DIR.x

P6SEL.x

INCHx

P6.0/A0

P6.1/A1

P6.2/A2

P6.3/A3

P6.4/A4

P6.5/A5

P6.6/A6

P6.7/A7

0

P6.0 (I/O)

A0^{(2) (3)}

I: 0; O: 1

0

X

0

X

0

X

1

X

2

X

3

X

4

X

5

X

6

X

7

X

1

2

3

4

5

6

7

P6.1 (I/O)

A1^{(2) (3)}

I: 0; O: 1

X

0

P6.2 (I/O)

A2^{(2) (3)}

I: 0; O: 1

X

0

P6.3 (I/O)

A3^{(2) (3)}

I: 0; O: 1

X

0

P6.4 (I/O)

A4^{(2) (3)}

I: 0; O: 1

X

0

P6.5 (I/O)

A5^{(1) (2) (3)}

P6.6 (I/O)

A6^{(2) (3)}

I: 0; O: 1

X

I: 0; O: 1

X

0

X

0

P6.7 (I/O)

A7^{(2) (3)}

I: 0; O: 1

X

(1) X = Don't care

(2) Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals.

(3) The ADC12_A channel Ax is connected internally to AV_SSif not selected by the respective INCHx bits.

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8.10.10 Port P7, P7.0, Input/Output With Schmitt Trigger

Pad Logic

To XT1

P7REN.0

DV_SS

DV_CC

0

1

P7DIR.0

0

1

P7OUT.0

0

1

Module X OUT

P7.0/XIN

P7DS.0

0: Low drive

1: High drive

P7SEL.0

P7IN.0

Bus

Keeper

EN

D

Module X IN

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8.10.11 Port P7, P7.1, Input/Output With Schmitt Trigger

Pad Logic

To XT1

P7REN.1

DV_SS

DV_CC

0

1

P7DIR.1

0

1

P7OUT.1

0

1

Module X OUT

P7SEL.0

P7.1/XOUT

P7DS.1

0: Low drive

1: High drive

XT1BYPASS

P7SEL.1

P7IN.1

Bus

Keeper

EN

D

Module X IN

Table 8-51. Port P7 (P7.0 and P7.1) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P7.x)

x

FUNCTION

P7DIR.x

P7SEL.0

P7SEL.1

XT1BYPASS

P7.0/XIN

0

P7.0 (I/O)

I: 0; O: 1

0

1

0

1

X

0

X

0

1

X

0

1

XIN crystal mode⁽²⁾

XIN bypass mode⁽²⁾

P7.1 (I/O)

X

P7.1/XOUT

1

I: 0; O: 1

XOUT crystal mode⁽³⁾

P7.1 (I/O)⁽³⁾

X

0

(1) X = Don't care

(2) Setting P7SEL.0 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P7.0 is configured for crystal

mode or bypass mode.

(3) Setting P7SEL.0 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.1 can be used as

general-purpose I/O.

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8.10.12 Port P7, P7.2 and P7.3, Input/Output With Schmitt Trigger

Pad Logic

P7REN.x

DV_SS

DV_CC

0

1

P7DIR.x

0

1

Direction

0: Input

1: Output

P7OUT.x

0

1

Module X OUT

P7.2/TB0OUTH/SVMOUT

P7.3/TA1.2

P7DS.x

0: Low drive

1: High drive

P7SEL.x

P7IN.x

EN

D

Module X IN

Table 8-52. Port P7 (P7.2 and P7.3) Pin Functions

CONTROL BITS OR SIGNALS

PIN NAME (P7.x)

x

FUNCTION

P7DIR.x

P7SEL.x

P7.2/TB0OUTH/SVMOUT

2

P7.2 (I/O)

TB0OUTH

SVMOUT

P7.3 (I/O)

TA1.CCI2B

TA1.2

I: 0; O: 1

0

1

0

1

0

1

P7.3/TA1.2

3

I: 0; O: 1

0

1

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8.10.13 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger

Pad Logic

To ADC12

INCHx = y

P7REN.x

DV_SS

DV_CC

0

1

P7DIR.x

0

1

P7OUT.x

0

1

Module X OUT

P7.4/A12

P7.5/A13

P7.6/A14

P7.7/A15

P7DS.x

0: Low drive

1: High drive

P7SEL.x

P7IN.x

Bus

Keeper

EN

D

Module X IN

Table 8-53. Port P7 (P7.4 to P7.7) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P7.x)

x

FUNCTION

P7DIR.x

P7SEL.x

INCHx

P7.4/A12

P7.5/A13

P7.6/A14

P7.7/A15

4

P7.4 (I/O)

I: 0; O: 1

0

X

0

X

12

X

A12^{(2) (3)}

P7.5 (I/O)

A13^{(2) (3)}

P7.6 (I/O)

A14^{(2) (3)}

P7.7 (I/O)

A15^{(2) (3)}

X

5

6

7

I: 0; O: 1

X

I: 0; O: 1

X

0

13

X

0

14

X

I: 0; O: 1

X

15

(1) X = Don't care

(2) Setting the P7SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals.

(3) The ADC12_A channel Ax is connected internally to AV_SSif not selected by the respective INCHx bits.

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8.10.14 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger

Pad Logic

P8REN.x

0

1

DV_SS

DV_CC

1

P8DIR.x

0

1

Direction

0: Input

1: Output

0

1

P8OUT.x

Module X OUT

P8.0/TA0.0

P8DS.x

0: Low drive

1: High drive

P8.1/TA0.1

P8.2/TA0.2

P8.3/TA0.3

P8.4/TA0.4

P8.5/TA1.0

P8.6/TA1.1

P8.7

P8SEL.x

P8IN.x

EN

D

Module X IN

Table 8-54. Port P8 (P8.0 to P8.7) Pin Functions

CONTROL BITS OR SIGNALS

PIN NAME (P8.x)

x

FUNCTION

P8DIR.x

P8SEL.x

P8.0/TA0.0

P8.1/TA0.1

P8.2/TA0.2

P8.3/TA0.3

P8.4/TA0.4

P8.5/TA1.0

P8.6/TA1.1

P8.7

0

P8.0 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

TA0.CCI0B

TA0.0

0

1

2

3

4

5

6

7

P8.1 (I/O)

TA0.CCI1B

TA0.1

I: 0; O: 1

0

1

P8.2 (I/O)

TA0.CCI2B

TA0.2

I: 0; O: 1

0

1

P8.3 (I/O)

TA0.CCI3B

TA0.3

I: 0; O: 1

0

1

P8.4 (I/O)

TA0.CCI4B

TA0.4

I: 0; O: 1

0

1

P8.5 (I/O)

TA1.CCI0B

TA1.0

I: 0; O: 1

0

1

P8.6 (I/O)

TA1.CCI1B

TA1.1

I: 0; O: 1

0

1

P8.7 (I/O)

I: 0; O: 1

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8.10.15 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger

Pad Logic

P9REN.x

DV_SS

DV_CC

0

1

P9DIR.x

0

1

Direction

0: Input

1: Output

P9OUT.x

0

1

Module X OUT

P9.0/UCB2STE/UCA2CLK

P9.1/UCB2SIMO/UCB2SDA

P9.2/UCB2SOMI/UCB2SCL

P9.3/UCB2CLK/UCA2STE

P9.4/UCA2TXD/UCA2SIMO

P9.5/UCA2RXD/UCA2SOMI

P9.6

P9DS.x

0: Low drive

1: High drive

P9SEL.x

P9IN.x

EN

D

P9.7

Module X IN

Table 8-55. Port P9 (P9.0 to P9.7) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P9.x)

x

FUNCTION

P9DIR.x

I: 0; O: 1

X

P9SEL.x

P9.0/UCB2STE/UCA2CLK

0

P9.0 (I/O)

0

1

0

1

0

1

0

1

0

1

0

1

0

UCB2STE/UCA2CLK^{(2) (4)}

P9.1/UCB2SIMO/UCB2SDA

P9.2/UCB2SOMI/UCB2SCL

P9.3/UCB2CLK/UCA2STE

P9.4/UCA2TXD/UCA2SIMO

P9.5/UCA2RXD/UCA2SOMI

1

2

3

4

5

P9.1 (I/O)

I: 0; O: 1

X

UCB2SIMO/UCB2SDA^{(2) (3)}

P9.2 (I/O)

I: 0; O: 1

X

UCB2SOMI/UCB2SCL^{(2) (3)}

P9.3 (I/O)

I: 0; O: 1

X

UCB2CLK/UCA2STE^{(2) (5)}

P9.4 (I/O)

I: 0; O: 1

X

UCA2TXD/UCA2SIMO⁽²⁾

P9.5 (I/O)

I: 0; O: 1

X

UCA2RXD/UCA2SOMI⁽²⁾

P9.6 (I/O)

P9.6

P9.7

6

7

I: 0; O: 1

P9.7 (I/O)

(1) X = Don't care

(2) The pin direction is controlled by the USCI module.

(3) If the I2C functionality is selected, the output drives only the logical 0 to V_SSlevel.

(4) UCA2CLK function takes precedence over UCB2STE function. If the pin is required as UCA2CLK input or output, USCI B2 is forced to

3-wire SPI mode if 4-wire SPI mode is selected.

(5) UCB2CLK function takes precedence over UCA2STE function. If the pin is required as UCB2CLK input or output, USCI A2 is forced to

3-wire SPI mode if 4-wire SPI mode is selected.

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8.10.16 Port P10, P10.0 to P10.7, Input/Output With Schmitt Trigger

Pad Logic

P10REN.x

DV_SS

DV_CC

0

1

P10DIR.x

0

1

Direction

0: Input

1: Output

P10OUT.x

0

1

Module X OUT

P10.0/UCB3STE/UCA3CLK

P10.1/UCB3SIMO/UCB3SDA

P10.2/UCB3SOMI/UCB3SCL

P10.3/UCB3CLK/UCA3STE

P10.4/UCA3TXD/UCA3SIMO

P10.5/UCA3RXD/UCA3SOMI

P10.6

P10DS.x

0: Low drive

1: High drive

P10SEL.x

P10IN.x

EN

D

P10.7

Module X IN

Table 8-56. Port P10 (P10.0 to P10.7) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P10.x)

x

FUNCTION

P10DIR.x

P10SEL.x

P10.0/UCB3STE/UCA3CLK

0

P10.0 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

UCB3STE/UCA3CLK^{(2) (4)}

X

P10.1/UCB3SIMO/UCB3SDA

P10.2/UCB3SOMI/UCB3SCL

P10.3/UCB3CLK/UCA3STE

P10.4/UCA3TXD/UCA3SIMO

P10.5/UCA3RXD/UCA3SOMI

P10.6

1

2

3

4

5

6

7

P10.1 (I/O)

I: 0; O: 1

UCB3SIMO/UCB3SDA^{(2) (3)}

P10.2 (I/O)

X

I: 0; O: 1

UCB3SOMI/UCB3SCL^{(2) (3)}

X

P10.3 (I/O)

I: 0; O: 1

UCB3CLK/UCA3STE⁽²⁾

P10.4 (I/O)

X

I: 0; O: 1

UCA3TXD/UCA3SIMO⁽²⁾

X

P10.5 (I/O)

I: 0; O: 1

UCA3RXD/UCA3SOMI⁽²⁾

P10.6 (I/O)

X

I: 0; O: 1

Reserved⁽⁵⁾

X

I: 0; O: 1

x

P10.7

P10.7 (I/O)

Reserved⁽⁵⁾

(1) X = Don't care

(2) The pin direction is controlled by the USCI module.

(3) If the I2C functionality is selected, the output drives only the logical 0 to V_SSlevel.

(4) UCA3CLK function takes precedence over UCB3STE function. If the pin is required as UCA3CLK input or output, USCI B3 is forced to

3-wire SPI mode if 4-wire SPI mode is selected.

(5) The secondary function on these pins are reserved for factory test purposes. Application should keep the P10SEL.x of these ports

cleared to prevent potential conflicts with the application.

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8.10.17 Port P11, P11.0 to P11.2, Input/Output With Schmitt Trigger

Pad Logic

P11REN.x

0

1

DV_SS

DV_CC

1

P11DIR.x

0

1

Direction

0: Input

1: Output

P11OUT.x

0

1

Module X OUT

P11.0/ACLK

P11.1/MCLK

P11.2/SMCLK

P11DS.x

0: Low drive

1: High drive

P11SEL.x

P11IN.x

EN

D

Module X IN

Table 8-57. Port P11 (P11.0 to P11.2) Pin Functions

CONTROL BITS OR SIGNALS

PIN NAME (P11.x)

x

FUNCTION

P11DIR.x

P11SEL.x

P11.0/ACLK

P11.1/MCLK

P11.2/SMCLK

0

P11.0 (I/O)

ACLK

I: 0; O: 1

0

1

0

1

0

1

2

P11.1 (I/O)

MCLK

I: 0; O: 1

1

I: 0; O: 1

1

P11.2 (I/O)

SMCLK

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8.10.18 Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output

Pad Logic

PJREN.0

0

1

DV_SS

DV_CC

1

PJDIR.0

DVCC

0

1

PJOUT.0

0

1

From JTAG

PJ.0/TDO

PJDS.0

0: Low drive

1: High drive

From JTAG

PJIN.0

EN

D

8.10.19 Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output

Pad Logic

PJREN.x

0

1

DV_SS

DV_CC

1

PJDIR.x

DVSS

0

1

PJOUT.x

0

1

From JTAG

PJ.1/TDI/TCLK

PJ.2/TMS

PJ.3/TCK

PJDS.x

0: Low drive

1: High drive

From JTAG

PJIN.x

EN

D

To JTAG

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Table 8-58. Port PJ (PJ.0 to PJ.3) Pin Functions

CONTROL BITS

OR SIGNALS⁽¹⁾

PIN NAME (PJ.x)

x

FUNCTION

PJDIR.x

I: 0; O: 1

X

PJ.0/TDO

0

PJ.0 (I/O)⁽²⁾

TDO⁽³⁾

PJ.1/TDI/TCLK

PJ.2/TMS

1

2

3

PJ.1 (I/O)⁽²⁾

TDI/TCLK^{(3) (4)}

PJ.2 (I/O)⁽²⁾

TMS^{(3) (4)}

I: 0; O: 1

X

I: 0; O: 1

X

PJ.3/TCK

PJ.3 (I/O)⁽²⁾

TCK^{(3) (4)}

I: 0; O: 1

X

(1) X = Don't care

(2) Default condition

(3) The pin direction is controlled by the JTAG module.

(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.

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8.11 Device Descriptors (TLV)

Table 8-59 shows the complete contents of the device descriptor tag-length-value (TLV) structure.

Table 8-59. Device Descriptor Table

MSP430BT5190

SIZE

(bytes)

DESCRIPTION

ADDRESS

VALUE

06h

Info Block

Info length

CRC length

01A00h

01A01h

01A02h

01A04h

01A05h

01A06h

01A07h

01A08h

01A09h

01A0Ah

01A0Eh

01A10h

01A12h

01A14h

01A15h

01A16h

01A18h

1

2

1

4

2

1

2

06h

CRC value

per unit

05h

Device ID

80h

Hardware revision

Firmware revision

Die Record Tag

Die Record length

Lot/Wafer ID

per unit

08h

Die Record

0Ah

per unit

11h

Die X position

Die Y position

Test results

ADC12 Calibration

ADC12 Calibration Tag

ADC12 Calibration length

ADC Gain Factor

ADC Offset

10h

per unit

ADC 1.5-V Reference

Temp. Sensor 30°C

01A1Ah

01A1Ch

01A1Eh

01A20h

01A22h

01A24h

2

per unit

ADC 1.5-V Reference

Temp. Sensor 85°C

ADC 2.0-V Reference

Temp. Sensor 30°C

ADC 2.0-V Reference

Temp. Sensor 85°C

ADC 2.5-V Reference

Temp. Sensor 30°C

ADC 2.5-V Reference

Temp. Sensor 85°C

REF Calibration

REF Calibration Tag

REF Calibration length

REF 1.5-V Reference

REF 2.0-V Reference

REF 2.5-V Reference

Peripheral Descriptor Tag

Peripheral Descriptor Length

01A26h

01A27h

01A28h

01A2Ah

01A2Ch

01A2Eh

01A2Fh

1

2

1

12h

06h

per unit

02h

Peripheral Descriptor

61h

08h

8Ah

Memory 1

Memory 2

Memory 3

2

0Ch

86h

0Eh

30h

2Eh

98h

Memory 4

Memory 5

2

0/1

NA

92

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Table 8-59. Device Descriptor Table (continued)

MSP430BT5190

SIZE

(bytes)

DESCRIPTION

ADDRESS

VALUE

00h

Delimiter

1

Peripheral count

21h

00h

23h

MSP430CPUXV2

SBW

2

00h

0Fh

00h

05h

EEM-8

00h

FCh

TI BSL

00h

1Fh

Package

SFR

10h

41h

02h

30h

PMM

02h

38h

FCTL

01h

3Ch

CRC16-straight

CRC16-bit reversed

RAMCTL

WDT_A

UCS

00h

3Dh

00h

44h

00h

40h

01h

48h

02h

42h

SYS

03h

A0h

REF

05h

51h

Port 1/2

Port 3/4

Port 5/6

Port 7/8

Port 9/10

Port 11/12

JTAG

02h

52h

02h

53h

02h

54h

02h

55h

02h

56h

08h

5Fh

02h

62h

TA0

04h

61h

TA1

04h

67h

TB0

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Table 8-59. Device Descriptor Table (continued)

MSP430BT5190

SIZE

(bytes)

DESCRIPTION

ADDRESS

VALUE

0Eh

68h

RTC

2

02h

85h

MPY32

04h

47h

DMA-3

0Ch

90h

USCI_A/B

ADC12_A

04h

90h

04h

90h

04h

90h

08h

D1h

Interrupts

TB0.CCIFG0

TB0.CCIFG1..6

WDTIFG

1

64h

65h

40h

90h

91h

D0h

60h

61h

94h

95h

46h

62h

63h

50h

92h

93h

96h

97h

51h

68h

00h

USCI_A0

USCI_B0

ADC12_A

TA0.CCIFG0

TA0.CCIFG1..4

USCI_A2

USCI_B2

DMA

TA1.CCIFG0

TA1.CCIFG1..2

P1

USCI_A1

USCI_B1

USCI_A3

USCI_B3

P2

RTC_A

Delimiter

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9 Device and Documentation Support

9.1 Device Support

9.1.1 Getting Started and Next Steps

For an introduction to the MSP430^™family of devices and the tools and libraries that are available to help with

your development, visit the Getting Started page.

9.1.2 Development Tools Support

All MSP430^™microcontrollers are supported by a wide variety of software and hardware development tools.

Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools.

9.1.2.1 Hardware Features

See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.

Break-

points

(N)

Range

Break-

points

LPMx.5

Debugging

Support

MSP430

Architecture

4-Wire

JTAG

2-Wire

JTAG

Clock

Control

State

Sequencer

Trace

Buffer

MSP430Xv2

Yes

8

Yes

No

9.1.2.2 Recommended Hardware Options

9.1.2.2.1 Experimenter Boards

Experimenter Boards and Evaluation kits are available for some MSP430 devices. These kits feature additional

hardware components and connectivity for full system evaluation and prototyping. See www.ti.com/msp430tools

for details.

9.1.2.2.2 Debugging and Programming Tools

Hardware programming and debugging tools are available from TI and from its third party suppliers. See the full

list of available tools at www.ti.com/msp430tools.

9.1.2.2.3 Production Programmers

The production programmers expedite loading firmware to devices by programming several devices

simultaneously.

Part Number

PC Port

Features

Provider

Program up to eight devices at a time. Works with a PC or as a

stand-alone device.

MSP-GANG

Serial and USB

Texas Instruments

9.1.2.3 Recommended Software Options

9.1.2.3.1 Integrated Development Environments

Software development tools are available from TI or from third parties. Open source solutions are also available.

This device is supported by Code Composer Studio^™IDE (CCS).

9.1.2.3.2 MSP430Ware

MSP430Ware is a collection of code examples, data sheets, and other design resources for all MSP430 devices

delivered in a convenient package. In addition to providing a complete collection of existing MSP430 design

resources, MSP430Ware also includes a high-level API called MSP430 Driver Library. This library makes it easy

to program MSP430 hardware. MSP430Ware is available as a component of CCS or as a stand-alone package.

9.1.2.3.3 TI-RTOS

TI-RTOS is an advanced real-time operating system for the MSP430 microcontrollers. It features preemptive

deterministic multitasking, hardware abstraction, memory management, and real-time analysis. TI-RTOS is

available free of charge and is provided with full source code.

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9.1.2.3.4 Command-Line Programmer

MSP430 Flasher is an open-source, shell-based interface for programming MSP430 microcontrollers through a

FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP430 Flasher can be used to

download binary files (.txt or .hex) files directly to the MSP430 microcontroller without the need for an IDE.

9.1.3 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP

MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These

prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully

qualified production devices (MSP).

XMS – Experimental device that is not necessarily representative of the final device's electrical specifications

MSP – Fully qualified production device

XMS devices are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated

fully. TI's standard warranty applies.

Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.

TI recommends that these devices not be used in any production system because their expected end-use failure

rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature

range, package type, and distribution format. Figure 9-1 provides a legend for reading the complete device

name.

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MSP 430 F 5 438 A I PM T -EP

Processor Family

MCU Platform

Device Type

Series

Feature Set

Optional: Additional Features

Optional: Tape and Reel

Packaging

Optional: Temperature Range

Optional: Revision

Processor Family

CC = Embedded RF Radio

MSP = Mixed-Signal Processor

XMS = Experimental Silicon

PMS = Prototype Device

MCU Platform

Device Type

430 = MSP430 low-power microcontroller platform

Memory Type

C = ROM

F = Flash

FR = FRAM

G = Flash

L = No nonvolatile memory

Specialized Application

AFE = Analog front end

BQ = Contactless power

CG = ROM medical

FE = Flash energy meter

FG = Flash medical

FW = Flash electronic flow meter

Series

1 = Up to 8 MHz

2 = Up to 16 MHz

3 = Legacy

4 = Up to 16 MHz with LCD driver

5 = Up to 25 MHz

6 = Up to 25 MHz with LCD driver

0 = Low-voltage series

Feature Set

Various levels of integration within a series

Updated version of the base part number

Optional: Revision

Optional: Temperature Range S = 0°C to 50°C

C = 0°C to 70°C

I = –40°C to 85°C

T = –40°C to 105°C

Packaging

http://www.ti.com/packaging

Optional: Tape and Reel

T = Small reel

R = Large reel

No markings = Tube or tray

Optional: Additional Features -EP = Enhanced product (–40°C to 105°C)

-HT = Extreme temperature parts (–55°C to 150°C)

-Q1 = Automotive Q100 qualified

Figure 9-1. Device Nomenclature

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9.2 Documentation Support

The following documents describe the MSP430BT5190 device. Copies of these documents are available on the

Internet at www.ti.com.

SLAU208 MSP430x5xx and MSP430x6xx Family User's Guide. Detailed information on the modules and

peripherals available in this device family.

SLAZ071 MSP430BT5190 Device Erratasheet. Describes the known exceptions to the functional

specifications for all silicon revisions of this device.

9.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

9.4 Trademarks

Mindtree^™is a trademark of Mindtree Ltd.

MSP430^™, MicroStar Junior^™, Code Composer Studio^™, and TI E2E^™are trademarks of Texas Instruments.

Bluetooth^®is a registered trademark of Bluetooth SIG, Inc.

All other trademarks are the property of their respective owners.

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

9.6 Export Control Notice

Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as

defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled

product restricted by other applicable national regulations, received from disclosing party under nondisclosure

obligations (if any), or any direct product of such technology, to any destination to which such export or re-export

is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.

Department of Commerce and other competent Government authorities to the extent required by those laws.

9.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

98

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MSP430BT5190

SLAS703C – APRIL 2010 – REVISED SEPTEMBER 2020

www.ti.com

Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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99

Product Folder Links: MSP430BT5190

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Aug-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

MSP430BT5190IPZR

LQFP

PZ

100

113

1000

2500

330.0

24.4

16.4

17.0

7.3

17.0

7.3

2.1

1.5

20.0

12.0

24.0

16.0

Q2

Q1

MSP430BT5190IZQWR BGA MI

ZQW

CROSTA

R JUNI

OR

MSP430BT5190IZQWT BGA MI

ZQW

113

250

180.0

16.4

7.3

1.5

12.0

16.0

Q1

CROSTA

R JUNI

OR

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Aug-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

MSP430BT5190IPZR

LQFP

PZ

100

113

1000

2500

350.0

43.0

MSP430BT5190IZQWR BGA MICROSTAR

JUNIOR

ZQW

MSP430BT5190IZQWT BGA MICROSTAR

JUNIOR

ZQW

113

250

213.0

191.0

55.0

Pack Materials-Page 2

PACKAGE OUTLINE

NFBGA - 1 mm max height

PLASTIC BALL GRID ARRAY

ZCA0113A

A

7.1

6.9

B

BALL A1 CORNER

7.1

6.9

1 MAX

C

SEATING PLANE

0.08 C

0.25

0.15

BALL TYP

5.5

TYP

(0.75) TYP

SYMM

M

L

K

J

(0.75) TYP

H

G

F

E

D

C

SYMM

5.5

TYP

0.35

0.25

113X Ø

B

A

0.15

0.05

C

A B

1

2

3

4

5

6

7

8

9 10 11 12

0.5 TYP

4225149/A 08/2019

NanoFree is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

NFBGA - 1 mm max height

PLASTIC BALL GRID ARRAY

ZCA0113A

(0.5) TYP

1

2

3

4

5

6

7

8

9

10 11 12

A

B

C

D

E

F

113X (Ø0.25)

SYMM

G

H

J

K

L

M

SYMM

LAND PATTERN EXAMPLE

SCALE: 10X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

EXPOSED

METAL

(Ø 0.25)

METAL

(Ø 0.25)

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON- SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4225149/A 08/2019

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments

Literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com

EXAMPLE STENCIL DESIGN

NFBGA - 1 mm max height

PLASTIC BALL GRID ARRAY

ZCA0113A

(0.5) TYP

1

2

3

4

5

6

7

8

9

10 11 12

A

B

C

D

E

F

(R0.05)

SYMM

G

H

J

METAL TYP

113X ( 0.25)

K

L

M

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.100 mm THICK STENCIL

SCALE: 10X

4225149/A 08/2019

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

MECHANICAL DATA

MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996

PZ (S-PQFP-G100)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

75

M

0,08

51

50

76

26

100

0,13 NOM

1

25

12,00 TYP

Gage Plane

14,20

SQ

13,80

0,25

16,20

SQ

0,05 MIN

0°–7°

15,80

1,45

1,35

0,75

0,45

Seating Plane

0,08

1,60 MAX

4040149/B 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

1

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IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

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warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	MSP430BT5190_V01
厂家：	TEXAS INSTRUMENTS
描述：	MSP430BT5190 Mixed-Signal Microcontroller 微控制器
文件：	总110页 (文件大小：2734K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MSP430BT5190_V01 [TI]

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