MSP430F2013-EP_16_技术文档

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

D

Low Supply Voltage Range 1.8 V to 3.6 V

D

Brownout Detector

Ultralow-Power Consumption

− Active Mode: 220 µA at 1 MHz, 2.2 V

− Standby Mode: 0.5 µA

D

Serial Onboard Programming,

No External Programming Voltage Needed

Programmable Code Protection by

Security Fuse

− Off Mode (RAM Retention): 0.1 µA

D

Five Power-Saving Modes

D

On-Chip Emulation Logic with Spy-Bi-Wire

Interface

Ultrafast Wake-Up From Standby Mode in

less than 1 µs

16-Bit RISC Architecture, 62.5 ns

Instruction Cycle Time

Family Members Include:

†

MSP430F2001 : 1KB + 256B Flash Memory

128B RAM

†

MSP430F2011 : 2KB + 256B Flash Memory

Basic Clock Module Configurations:

− Internal Frequencies up to 16MHz with

4 Calibrated Frequencies to 1%

− Internal Very Low Power LF oscillator

− 32-kHz Crystal

128B RAM

†

MSP430F2002 : 1KB + 256B Flash Memory

128B RAM

†

MSP430F2012 : 2KB + 256B Flash Memory

128B RAM

− External Digital Clock Source

MSP430F2003: 1KB + 256B Flash Memory

128B RAM

MSP430F2013: 2KB + 256B Flash Memory

128B RAM

Available in a 14-Pin Plastic Small-Outline

Thin Package (TSSOP), 14-Pin Plastic Dual

Inline Package (PDIP), and 16-Pin QFN

For Complete Module Descriptions, Refer

to the MSP430x2xx Family User’s Guide

D

16-Bit Timer_A With Two Capture/Compare

Registers

On-Chip Comparator for Analog Signal

Compare Function or Slope A/D

(MSP430x20x1 only)

D

10-Bit, 200-ksps A/D Converter with Internal

Reference, Sample-and-Hold, and

Autoscan. (MSP430x20x2 only)

†

Product Preview

16-Bit Sigma-Delta A/D Converter with

Differential PGA Inputs, and Internal

Reference (MSP430x20x3 only)

Universal Serial Interface (USI), supporting

SPI and I2C

(MSP430x20x2 and MSP430x20x3 only)

description

The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low power

modes is optimized to achieve extended battery life in portable measurement applications. The device features

a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.

The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1µs.

The MSP430x20xx series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer, and ten

I/O pins. In addition the MSP430x20x1 has a versatile analog comparator. The MSP430x20x2 and

MSP430x20x3 have built-in communication capability using synchronous protocols (SPI or I2C), and a 10-bit

A/D converter (MSP430x20x2) or a 16-bit sigma-delta A/D converter (MSP430x20x3).

Typical applications include sensor systems that capture analog signals, convert them to digital values, and then

process the data for display or for transmission to a host system. Stand alone RF sensor front end is another

area of application.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2005 Texas Instruments Incorporated

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢀ ꢊ ꢋ ꢌꢍ ꢁꢊ ꢎꢏ ꢐ ꢑ ꢀꢊ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢌ ꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

AVAILABLE OPTIONS

PACKAGED DEVICES

PLASTIC

14-PIN TSSOP

(PW)

PLASTIC

16-PIN QFN

(RSA)

T

A

†

14-PIN DIP

(N)

†

MSP430F2001IRSA

MSP430F2011IRSA

†

MSP430F2002IRSA

MSP430F2001IPW

MSP430F2011IPW

MSP430F2001IN

MSP430F2011IN

†

MSP430F2002IPW

MSP430F2002IN

−40°C to 85°C

†

MSP430F2012IPW

MSP430F2003IPW

MSP430F2013IPW

MSP430F2012IN

MSP430F2012IRSA

†

MSP430F2003IRSA

MSP430F2003IN

†

MSP430F2013IN

MSP430F2013IRSA

†

Product Preview

device pinout, MSP430x20x1

PW or N PACKAGE

(TOP VIEW)

14

13

12

11

10

9

1

2

3

4

5

6

7

V

SS

CC

XIN/P2.6/TA1

P1.0/TACLK/ACLK/CA0

P1.1/TA0/CA1

XOUT/P2.7

TEST/SBWTCK

P1.2/TA1/CA2

RST/NMI/SBWTDIO

P1.7/CAOUT/CA7/TDO/TDI

P1.6/TA1/CA6/TDI/TCLK

P1.3/CAOUT/CA3

P1.4/SMCLK/CA4/TCK

P1.5/TA0/CA5/TMS

8

RSA PACKAGE

(TOP VIEW)

15 14

1

12

11

10

9

XIN/P2.6/TA1

XOUT/P2.7

P1.0/TACLK/ACLK/CA0

2

P1.1/TA0/CA1

P1.2/TA1/CA2

3

4

TEST/SBWTCK

RST/NMI/SBWTDIO

P1.3/CAOUT/CA3

6

7

2

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

device pinout, MSP430x20x2

PW or N PACKAGE

(TOP VIEW)

14

13

12

11

10

9

1

2

3

4

5

6

7

V

SS

CC

XIN/P2.6/TA1

XOUT/P2.7

P1.0/TACLK/ACLK/A0

P1.1/TA0/A1

TEST/SBWTCK

RST/NMI/SBWTDIO

P1.2/TA1/A2

P1.3/ADC10CLK/A3/VREF−/VeREF−

P1.7/A7/SDI/SDA/TDO/TDI

P1.4/SMCLK/A4/VREF+/VeREF+/TCK

P1.5/TA0/A5/SCLK/TMS

8

P1.6/TA1/A6/SDO/SCL/TDI/TCLK

RSA PACKAGE

(TOP VIEW)

15 14

1

2

3

4

12

11

10

9

XIN/P2.6/TA1

XOUT/P2.7

P1.0/TACLK/ACLK/A0

P1.1/TA0/A1

P1.2/TA1/A2

TEST/SBWTCK

RST/NMI/SBWTDIO

P1.3/ADC10CLK/A3/VREF−/VeREF−

6

7

3

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

device pinout, MSP430x20x3

PW or N PACKAGE

(TOP VIEW)

14

13

12

11

10

9

1

2

3

4

5

6

7

V

SS

CC

XIN/P2.6/TA1

P1.0/TACLK/ACLK/A0+

P1.1/TA0/A0−/A4+

P1.2/TA1/A1+/A4−

P1.3/VREF/A1−

XOUT/P2.7

TEST/SBWTCK

RST/NMI/SBWTDIO

P1.7/A3−/SDI/SDA/TDO/TDI

P1.6/TA1/A3+/SDO/SCL/TDI/TCLK

P1.4/SMCLK/A2+/TCK

8

P1.5/TA0/A2−/SCLK/TMS

RSA PACKAGE

(TOP VIEW)

15 14

1

2

3

4

12

11

10

9

XIN/P2.6/TA1

XOUT/P2.7

P1.0/TACLK/ACLK/A0+

P1.1/TA0/A0−/A4+

P1.2/TA1/A1+/A4−

P1.3/VREF/A1−

TEST/SBWTCK

RST/NMI/SBWTDIO

6

7

4

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ꢀ ꢊꢋꢌ ꢍ ꢁꢊ ꢎ ꢏꢐꢑ ꢀ ꢊꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢌꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

functional block diagram, MSP430x20x1

P2.x &

XIN/XOUT

2

VCC

VSS

P1.x & JTAG

8

XIN

XOUT

Port P1

Port P2

ACLK

Comparator

_A+

Basic Clock

System+

Flash

RAM

8 I/O

2 I/O

SMCLK

Interrupt

capability,

pull−up/down pull−up/down

Interrupt

capability,

2kB

1kB

128B

8 channel

input mux

MCLK

resistors

MAB

16MHz

CPU

incl. 16

Registers

MDB

Emulation

(2BP)

Watchdog

WDT+

Timer_A2

JTAG

Interface

Brownout

Protection

2 CC

15/16−Bit

Registers

Spy−Bi Wire

RST/NMI

NOTE: See port schematics section for detailed I/O information.

functional block diagram, MSP430x20x2

P2.x &

XIN/XOUT

2

VCC

VSS

P1.x & JTAG

8

XIN

XOUT

Port P1

Port P2

ACLK

ADC10

Basic Clock

System+

Flash

RAM

8 I/O

Interrupt

capability,

pull−up/down pull−up/down

resistors

2 I/O

Interrupt

capability,

10−bit

8 Channels

Autoscan

DTC

SMCLK

2kB

1kB

128B

MCLK

resistors

MAB

16MHz

CPU

incl. 16

Registers

MDB

Emulation

(2BP)

USI

Watchdog

WDT+

Timer_A2

JTAG

Interface

Brownout

Protection

Universal

Serial

2 CC

15/16−Bit

Registers

Interface

SPI, I2C

Spy−Bi Wire

RST/NMI

NOTE: See port schematics section for detailed I/O information.

5

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ꢀ ꢊ ꢋ ꢌꢍ ꢁꢊ ꢎꢏ ꢐ ꢑ ꢀꢊ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢌ ꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

functional block diagram, MSP430x20x3

P2.x &

XIN/XOUT

2

VCC

VSS

P1.x & JTAG

8

XIN

XOUT

Port P1

Port P2

ACLK

SD16_A

Basic Clock

System+

Flash

RAM

8 I/O

Interrupt

capability,

pull−up/down pull−up/down

resistors

2 I/O

Interrupt

capability,

16−bit

Sigma−

Delta A/D

Converter

SMCLK

2kB

1kB

128B

MCLK

resistors

MAB

16MHz

CPU

incl. 16

Registers

MDB

Emulation

(2BP)

USI

Watchdog

WDT+

Timer_A2

JTAG

Interface

Brownout

Protection

Universal

Serial

2 CC

15/16−Bit

Registers

Interface

SPI, I2C

Spy−Bi Wire

RST/NMI

NOTE: See port schematics section for detailed I/O information.

6

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Terminal Functions, MSP430x20x1

TERMINAL

PW, or N

RSA

NO.

1

DESCRIPTION

NAME

I/O

NO.

P1.0/TACLK/ACLK/CA0

2

I/O General-purpose digital I/O pin

Timer_A, clock signal TACLK input

ACLK signal ouput

Comparator_A+, CA0 input

P1.1/TA0/CA1

P1.2/TA1/CA2

3

4

2

3

I/O General-purpose digital I/O pin

Timer_A, capture: CCI0A input, compare: Out0 output

Comparator_A+, CA1 input

I/O General-purpose digital I/O pin

Timer_A, capture: CCI1A input, compare: Out1 output

Comparator_A+, CA2 input

P1.3/CAOUT/CA3

5

6

4

5

I/O General-purpose digital I/O pin

Comparator_A+, output / CA3 input

P1.4/SMCLK/C4/TCK

I/O General-purpose digital I/O pin

SMCLK signal output

Comparator_A+, CA4 input

JTAG test clock, input terminal for device programming and test

P1.5/TA0/CA5/TMS

P1.6/TA1/CA6/TDI/TCLK

P1.7/CAOUT/CA7/TDO/TDI

XIN/P2.6/TA1

7

8

6

7

I/O General-purpose digital I/O pin

Timer_A, compare: Out0 output

Comparator_A+, CA5 input

JTAG test mode select, input terminal for device programming and test

I/O General-purpose digital I/O pin

Timer_A, compare: Out1 output

Comparator_A+, CA6 input

JTAG test data input or test clock input during programming and test

†

9

8

I/O General-purpose digital I/O pin

Comparator_A+, output / CA7 input

JTAG test data output terminal or test data input during programming and

test

13

12

I/O Input terminal of crystal oscillator

General-purpose digital I/O pin

Timer_A, compare: Out1 output

XOUT/P2.7

12

10

11

9

I/O Output terminal of crystal oscillator

General-purpose digital I/O pin

RST/NMI/SBWTDIO

TEST/SBWTCK

I

Reset or nonmaskable interrupt input

Spy-Bi-Wire test data input/output during programming and test

10

I

Selects test mode for JTAG pins on Port1. The device protection fuse is

connected to TEST.

Spy-Bi-Wire test clock input during programming and test

V

1

16

14

Supply voltage

Ground reference

Not connected

CC

14

NA

SS

NC

13, 15

QFN Pad

Package

Pad

NA QFN package pad connection to V recommended.

SS

†

TDO or TDI is selected via JTAG instruction.

NOTE: If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection

to this pad after reset.

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢀ ꢊ ꢋ ꢌꢍ ꢁꢊ ꢎꢏ ꢐ ꢑ ꢀꢊ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢌ ꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Terminal Functions, MSP430x20x2

TERMINAL

PW, or N

RSA

NO.

1

DESCRIPTION

NAME

I/O

NO.

P1.0/TACLK/ACLK/A0

2

I/O General-purpose digital I/O pin

Timer_A, clock signal TACLK input

ACLK signal ouput

ADC10 analog input A0

P1.1/TA0/A1

P1.2/TA1/A2

3

4

5

2

3

4

I/O General-purpose digital I/O pin

Timer_A, capture: CCI0A input, compare: Out0 output

ADC10 analog input A1

I/O General-purpose digital I/O pin

Timer_A, capture: CCI1A input, compare: Out1 output

ADC10 analog input A2

P1.3/ADC10CLK/

A3/VREF−/VeREF−

I/O General-purpose digital I/O pin

ADC10 conversion clock output

ADC10 analog input A3

Input for negative external reference voltage/negative internal reference

voltage output

P1.4/SMCLK/A4/VREF+/VeREF+/

TCK

6

5

I/O General-purpose digital I/O pin

SMCLK signal output

ADC10 analog input A4

Input for positive external reference voltage/positive internal reference

voltage output

JTAG test clock, input terminal for device programming and test

P1.5/TA0/A5/SCLK/TMS

7

8

6

7

I/O General-purpose digital I/O pin

Timer_A, compare: Out0 output

ADC10 analog input A5

USI: external clock input in SPI or I2C mode; clock output in SPI mode

JTAG test mode select, input terminal for device programming and test

P1.6/TA1/A6/SDO/SCL/TDI/TCLK

I/O General-purpose digital I/O pin

Timer_A, capture: CCI1B input, compare: Out1 output

ADC10 analog input A6

USI: Data output in SPI mode; I2C clock in I2C mode

JTAG test data input or test clock input during programming and test

†

P1.7/A7/SDI/SDA/TDO/TDI

XIN/P2.6/TA1

9

8

I/O General-purpose digital I/O pin

ADC10 analog input A7

USI: Data input in SPI mode; I2C data in I2C mode

JTAG test data output terminal or test data input during programming and

test

13

12

I/O Input terminal of crystal oscillator

General-purpose digital I/O pin

Timer_A, compare: Out1 output

XOUT/P2.7

12

10

11

9

I/O Output terminal of crystal oscillator

General-purpose digital I/O pin

RST/NMI/SBWTDIO

TEST/SBWTCK

I

Reset or nonmaskable interrupt input

Spy-Bi-Wire test data input/output during programming and test

10

I

Selects test mode for JTAG pins on Port1. The device protection fuse is

connected to TEST.

Spy-Bi-Wire test clock input during programming and test

V

1

NA

Supply voltage

CC

14

Ground reference

SS

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Terminal Functions, MSP430x20x2 (Continued)

TERMINAL

PW, or N

RSA

NO.

16

DESCRIPTION

NAME

I/O

NO.

NA

DV

Digital supply voltage

Analog supply voltage

Digital ground reference

Analog ground reference

CC

AV

DV

15

CC

14

SS

AV

13

QFN Pad

Package

Pad

NA QFN package pad connection to V recommended.

SS

†

TDO or TDI is selected via JTAG instruction.

NOTE: If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection

to this pad after reset.

Terminal Functions, MSP430x20x3

TERMINAL

PW, or N

RSA

NO.

1

DESCRIPTION

NAME

I/O

NO.

P1.0/TACLK/ACLK/A0+

2

I/O General-purpose digital I/O pin

Timer_A, clock signal TACLK input

ACLK signal ouput

SD16_A positive analog input A0

P1.1/TA0/A0−/A4+

3

4

5

6

7

2

3

4

5

6

I/O General-purpose digital I/O pin

Timer_A, capture: CCI0A input, compare: Out0 output

SD16_A negative analog input A0

SD16_A positive analog input A4

P1.2/TA1/A1+/A4−

I/O General-purpose digital I/O pin

Timer_A, capture: CCI1A input, compare: Out1 output

SD16_A positive analog input A1

SD16_A negative analog input A4

P1.3/VREF/A1−

I/O General-purpose digital I/O pin

Input for an external reference voltage/internal reference voltage output

(can be used as mid-voltage)

SD16_A negative analog input A1

P1.4/SMCLK/A2+/TCK

P1.5/TA0/A2−/SCLK/TMS

I/O General-purpose digital I/O pin

SMCLK signal output

SD16_A positive analog input A2

JTAG test clock, input terminal for device programming and test

I/O General-purpose digital I/O pin

Timer_A, compare: Out0 output

SD16_A negative analog input A2

USI: external clock input in SPI or I2C mode; clock output in SPI mode

JTAG test mode select, input terminal for device programming and test

P1.6/TA1/A3+/SDO/SCL/TDI/TCLK

8

9

7

8

I/O General-purpose digital I/O pin

Timer_A, capture: CCI1B input, compare: Out1 output

SD16_A positive analog input A3

USI: Data output in SPI mode; I2C clock in I2C mode

JTAG test data input or test clock input during programming and test

†

P1.7/A3−/SDI/SDA/TDO/TDI

I/O General-purpose digital I/O pin

SD16_A negative analog input A3

USI: Data input in SPI mode; I2C data in I2C mode

JTAG test data output terminal or test data input during programming and

test

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Terminal Functions, MSP430x20x3 (Continued)

TERMINAL

PW, or N

RSA

NO.

12

DESCRIPTION

NAME

I/O

NO.

XIN/P2.6/TA1

XOUT/P2.7

13

I/O Input terminal of crystal oscillator

General-purpose digital I/O pin

Timer_A, compare: Out1 output

12

10

11

9

I/O Output terminal of crystal oscillator

General-purpose digital I/O pin

RST/NMI/SBWTDIO

TEST/SBWTCK

I

Reset or nonmaskable interrupt input

Spy-Bi-Wire test data input/output during programming and test

10

I

Selects test mode for JTAG pins on Port1. The device protection fuse is

connected to TEST.

Spy-Bi-Wire test clock input during programming and test

V

1

NA

16

15

14

13

Supply voltage

CC

14

Ground reference

SS

DV

NA

Digital supply voltage

Analog supply voltage

Digital ground reference

Analog ground reference

CC

AV

DV

CC

SS

AV

QFN Pad

Package

Pad

NA QFN package pad connection to V recommended.

SS

†

TDO or TDI is selected via JTAG instruction.

NOTE: If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection

to this pad after reset.

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

short-form description

CPU

Program Counter

Stack Pointer

PC/R0

The MSP430 CPU has a 16-bit RISC architecture

that is highly transparent to the application. All

operations, other than program-flow instructions,

are performed as register operations in

conjunction with seven addressing modes for

source operand and four addressing modes for

destination operand.

SP/R1

Status Register

SR/CG1/R2

Constant Generator

CG2/R3

R4

General-Purpose Register

The CPU is integrated with 16 registers that

provide reduced instruction execution time. The

register-to-register operation execution time is

one cycle of the CPU clock.

R5

R6

R7

Four of the registers, R0 to R3, are dedicated as

program counter, stack pointer, status register,

and constant generator respectively. The

remaining registers are general-purpose

registers.

R8

R9

Peripherals are connected to the CPU using data,

address, and control buses, and can be handled

with all instructions.

R10

R11

instruction set

R12

R13

The instruction set consists of 51 instructions with

three formats and seven address modes. Each

instruction can operate on word and byte data.

Table 1 shows examples of the three types of

instruction formats; the address modes are listed

in Table 2.

R14

R15

Table 1. Instruction Word Formats

Dual operands, source-destination

Single operands, destination only

Relative jump, un/conditional

e.g. ADD R4,R5

R4 + R5 −−−> R5

e.g. CALL

e.g. JNE

R8

PC −−>(TOS), R8−−> PC

Jump-on-equal bit = 0

Table 2. Address Mode Descriptions

ADDRESS MODE

Register

S

D

SYNTAX

EXAMPLE

MOV R10,R11

MOV 2(R5),6(R6)

OPERATION

F

MOV Rs,Rd

R10 −−> R11

Indexed

MOV X(Rn),Y(Rm)

MOV EDE,TONI

MOV &MEM,&TCDAT

MOV @Rn,Y(Rm)

M(2+R5)−−> M(6+R6)

M(EDE) −−> M(TONI)

M(MEM) −−> M(TCDAT)

M(R10) −−> M(Tab+R6)

Symbolic (PC relative)

Absolute

Indirect

MOV @R10,Tab(R6)

MOV @R10+,R11

MOV #45,TONI

Indirect

autoincrement

M(R10) −−> R11

R10 + 2−−> R10

F

MOV @Rn+,Rm

Immediate

MOV #X,TONI

#45 −−> M(TONI)

NOTE: S = source

D = destination

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

operating modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt

event can wake up the device from any of the five low-power modes, service the request and restore back to

the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

D

Active mode AM;

All clocks are active

Low-power mode 0 (LPM0);

−

CPU is disabled

ACLK and SMCLK remain active. MCLK is disabled

D

Low-power mode 1 (LPM1);

−

CPU is disabled

ACLK and SMCLK remain active. MCLK is disabled

DCO’s dc-generator is disabled if DCO not used in active mode

Low-power mode 2 (LPM2);

−

CPU is disabled

MCLK and SMCLK are disabled

DCO’s dc-generator remains enabled

ACLK remains active

D

Low-power mode 3 (LPM3);

−

CPU is disabled

MCLK and SMCLK are disabled

DCO’s dc-generator is disabled

ACLK remains active

Low-power mode 4 (LPM4);

−

CPU is disabled

ACLK is disabled

MCLK and SMCLK are disabled

DCO’s dc-generator is disabled

Crystal oscillator is stopped

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh−0FFC0h.

The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g. flash is not programmed) the CPU will

go into LPM4 immediately after power-up.

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM INTERRUPT

WORD ADDRESS

PRIORITY

Power-up

External reset

PORIFG

RSTIFG

Watchdog Timer+

Flash key violation

PC out-of-range (see Note 1)

Reset

0FFFEh

31, highest

WDTIFG

KEYV

(see Note 2)

NMIIFG

OFIFG

ACCVIFG

NMI

Oscillator fault

Flash memory access violation

(non)-maskable,

(non)-maskable

0FFFCh

30

(see Notes 2 & 4)

0FFFAh

0FFF8h

0FFF6h

0FFF4h

0FFF2h

29

28

27

26

25

Comparator_A+ (MSP430x20x1 only)

Watchdog Timer+

CAIFG (see Note 3)

WDTIFG

maskable

Timer_A2

TACCR0 CCIFG (see Note 3)

TACCR1 CCIFG.

TAIFG (see Notes 2 & 3)

Timer_A2

maskable

0FFF0h

24

0FFEEh

0FFECh

23

22

ADC10 (MSP430x20x2 only)

SD16_A (MSP430x20x3 only)

ADC10IFG (see Note 3)

maskable

SD16CCTL0 SD16OVIFG,

SD16CCTL0 SD16IFG

(see Notes 2 & 3)

0FFEAh

21

USI

USIIFG, USISTTIFG

(see Notes 2 & 3)

maskable

0FFE8h

0FFE6h

0FFE4h

20

19

18

(MSP430x20x2, MSP430x20x3 only)

I/O Port P2

(two flags)

P2IFG.6 to P2IFG.7

(see Notes 2 & 3)

I/O Port P1

(eight flags)

P1IFG.0 to P1IFG.7

(see Notes 2 & 3)

0FFE2h

0FFE0h

17

16

(see Note 5)

0FFDEh ... 0FFC0h

15 ... 0, lowest

NOTES: 1. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h−01FFh).

2. Multiple source flags

3. Interrupt flags are located in the module

4. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.

5. The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if

necessary.

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

special function registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits

not allocated to a functional purpose are not physically present in the device. Simple software access is provided

with this arrangement.

interrupt enable 1 and 2

7

6

5

4

3

2

1

0

Address

0h

OFIE

WDTIE

ACCVIE

NMIIE

rw-0

WDTIE:

Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer

is configured in interval timer mode.

OFIE:

Oscillator fault enable

NMIIE:

ACCVIE:

(Non)maskable interrupt enable

Flash access violation interrupt enable

7

6

5

4

3

2

1

0

Address

01h

interrupt flag register 1 and 2

7

6

5

4

3

2

1

0

Address

02h

NMIIFG

RSTIFG

PORIFG

OFIFG

WDTIFG

rw-0

rw-(0)

rw-1

rw-(0)

rw-(1)

WDTIFG:

Set on Watchdog Timer overflow (in watchdog mode) or security key violation.

Reset on V power-up or a reset condition at RST/NMI pin in reset mode.

Flag set on oscillator fault

CC

OFIFG:

RSTIFG:

External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on V

power-up

CC

PORIFG:

NMIIFG:

Power-On Reset interrupt flag. Set on V

Set via RST/NMI-pin

power-up.

CC

7

6

5

4

3

2

1

0

Address

03h

Legend

rw:

Bit can be read and written.

rw-0,1:

rw-(0,1):

Bit can be read and written. It is Reset or Set by PUC.

Bit can be read and written. It is Reset or Set by POR.

SFR bit is not present in device

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

memory organization

MSP430F200x

MSP430F201x

Memory

Size

1KB Flash

2KB Flash

Main: interrupt vector

Main: code memory

Flash

0FFFFh−0FFC0h

0FFFFh−0FC00h

0FFFFh−0FFC0h

0FFFFh−0F800h

Information memory

Size

256 Byte

Flash

010FFh − 01000h

RAM

Size

128 Byte

027Fh − 0200h

Peripherals

16-bit

8-bit

8-bit SFR

01FFh − 0100h

0FFh − 010h

0Fh − 00h

01FFh − 0100h

0FFh − 010h

0Fh − 00h

flash memory

The flash memory can be programmed via the Spy-Bi-Wire/JTAG port, or in-system by the CPU. The CPU can

perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

D

Flash memory has n segments of main memory and four segments of information memory (A to D) of 64

bytes each. Each segment in main memory is 512 bytes in size.

D

Segments 0 to n may be erased in one step, or each segment may be individually erased.

Segments A to D can be erased individually, or as a group with segments 0−n.

Segments A to D are also called information memory.

D

Segment A contains calibration data. After reset segment A is protected against programming and erasing.

It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data

is required.

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ꢀ ꢊ ꢋ ꢌꢍ ꢁꢊ ꢎꢏ ꢐ ꢑ ꢀꢊ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢌ ꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

peripherals

Peripherals are connected to the CPU through data, address, and control busses and can be handled using

all instructions. For complete module descriptions, refer to the MSP430x2xx Family User’s Guide.

oscillator and system clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal

oscillator, an internal very low power, low frequency oscillator and an internal digitally-controlled oscillator

(DCO). The basic clock module is designed to meet the requirements of both low system cost and low-power

consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic

clock module provides the following clock signals:

D

Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.

Main clock (MCLK), the system clock used by the CPU.

Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.

DCO Calibration Data (provided from factory in flash info memory segment A)

DCO Frequency

Calibration Register

CALBC1_1MHz

CALDCO_1MHz

CALBC1_8MHz

CALDCO_8MHz

CALBC1_12MHz

CALDCO_12MHz

CALBC1_16MHz

CALDCO_16MHz

Size

byte

Address

010FFh

010FEh

010FDh

010FCh

010FBh

010FAh

010F9h

010F8h

1 MHz

8 MHz

12 MHz

16 MHz

brownout

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on

and power off.

digital I/O

There is one 8-bit I/O port implemented—port P1—and two bits of I/O port P2:

D

All individual I/O bits are independently programmable.

Any combination of input, output, and interrupt condition is possible.

Edge-selectable interrupt input capability for all the eight bits of port P1 and the two bits of port P2.

Read/write access to port-control registers is supported by all instructions.

Each I/O has an individually programmable pull-up/pull-down resistor.

WDT+ watchdog timer

The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a

software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog

function is not needed in an application, the module can be disabled or configured as an interval timer and can

generate interrupts at selected time intervals.

16

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

timer_A2

Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple

capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare

registers.

Timer_A2 Signal Connections (MSP43020x1 only)

Input

Pin Number

Device

Input Signal

Module

Input Name

Module

Block

Module

Output Signal

Output

Pin Number

PW, N

RSA

PW, N

RSA

2 - P1.0

1 - P1.0

TACLK

ACLK

TACLK

ACLK

Timer

CCR0

CCR1

NA

TA0

TA1

SMCLK

INCLK

CCI0A

CCI0B

GND

2 - P1.0

3 - P1.1

1 - P1.0

2 - P1.1

TACLK

TA0

3 - P1.1

7 - P1.5

2 - P1.1

6 - P1.5

ACLK (internal)

V

SS

V

CC

V

CC

4 - P1.2

3 - P1.2

TA1

CCI1A

CCI1B

GND

4 - P1.2

8 - P1.6

13 - P2.6

3 - P1.2

7 - P1.6

12 - P2.6

CAOUT (internal)

V

SS

V

CC

V

CC

Timer_A2 Signal Connections (MSP430F20x2, MSP430F20x3)

Input

Pin Number

Device

Input Signal

Module

Input Name

Module

Block

Module

Output Signal

Output

Pin Number

PW, N

RSA

PW, N

RSA

2 - P1.0

1 - P1.0

TACLK

ACLK

TACLK

ACLK

Timer

CCR0

CCR1

NA

TA0

TA1

SMCLK

INCLK

CCI0A

CCI0B

GND

2 - P1.0

3 - P1.1

7 - P1.5

1 - P1.0

2 - P1.1

6 - P1.5

TACLK

TA0

3 - P1.1

7 - P1.5

2 - P1.1

6 - P1.5

ACLK (internal)

V

SS

V

CC

V

CC

4 - P1.2

8 - P1.6

3 - P1.2

7 - P1.6

TA1

CCI1A

CCI1B

GND

4 - P1.2

8 - P1.6

13 - P2.6

3 - P1.2

7 - P1.6

12 - P2.6

V

SS

V

CC

V

CC

comparator_A+ (MSP430x20x1 only)

The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions,

battery-voltage supervision, and monitoring of external analog signals.

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

USI (MSP430x20x2 and MSP430x20x3 only)

The universal serial interface (USI) module is used for serial data communication and provides the basic

hardware for synchronous communication protocols like SPI and I2C.

ADC10 (MSP430x20x2 only)

The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR

core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion

result handling allowing ADC samples to be converted and stored without any CPU intervention.

SD16_A (MSP430x20x3 only)

The SD16_A module supports 16-bit analog-to-digital conversions. The module implements a 16-bit

sigma-delta core and reference generator. In addition to external analog inputs, an internal V

temperature sensor are also available.

sense and

CC

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

peripheral file map

PERIPHERALS WITH WORD ACCESS

ADC10 (MSP430x20x2 only)

ADC control 0

ADC control 1

ADC memory

ADC10CTL0

ADC10MEM

01B0h

01B2h

01B4h

SD16_A (MSP430x20x3 only) General Control

SD16CTL

SD16CCTL0

SD16IV

0100h

0102h

0110h

0112h

Channel 0 Control

Interrupt vector word register

Channel 0 conversion memory

SD16MEM0

Timer_A

Capture/compare register

Timer_A register

Capture/compare control

Timer_A control

TACCR1

TACCR0

TAR

TACCTL1

TACCTL0

TACTL

TAIV

0174h

0172h

0170h

0164h

0162h

0160h

012Eh

Timer_A interrupt vector

Flash Memory

Flash control 3

Flash control 2

Flash control 1

FCTL3

FCTL2

FCTL1

012Ch

012Ah

0128h

Watchdog Timer+

Watchdog/timer control

WDTCTL

0120h

PERIPHERALS WITH BYTE ACCESS

Analog enable

ADC10 (MSP430x20x2 only)

ADC10AE

04Ah

SD16_A (MSP430x20x3 only) Channel 0 Input Control

SD16INCTL0

SD16AE

0B0h

0B7h

Analog Enable

USI

USI control 0

USI control 1

USI clock control

USI bit counter

USI shift register

USICTL0

USICTL1

USICKCTL

USICNT

USISR

078h

079h

07Ah

07Bh

07Ch

(MSP430x20x2 and

MSP430x20x3 only)

Comparator_A+

(MSP430x20x1 only)

Comparator_A+ port disable

Comparator_A+ control 2

Comparator_A+ control 1

CAPD

CACTL2

CACTL1

05Bh

05Ah

059h

Basic Clock System+

Port P2

Basic clock system control 3

Basic clock system control 2

Basic clock system control 1

DCO clock frequency control

BCSCTL3

BCSCTL2

BCSCTL1

DCOCTL

053h

058h

057h

056h

Port P2 resistor enable

Port P2 selection

Port P2 interrupt enable

Port P2 interrupt edge select

Port P2 interrupt flag

Port P2 direction

P2REN

P2SEL

P2IE

P2IES

P2IFG

P2DIR

P2OUT

P2IN

02Fh

02Eh

02Dh

02Ch

02Bh

02Ah

029h

028h

Port P2 output

Port P2 input

Port P1

Port P1 resistor enable

Port P1 selection

Port P1 interrupt enable

Port P1 interrupt edge select

Port P1 interrupt flag

Port P1 direction

P1REN

P1SEL

P1IE

P1IES

P1IFG

P1DIR

P1OUT

P1IN

027h

026h

025h

024h

023h

022h

021h

020h

Port P1 output

Port P1 input

Special Function

SFR interrupt flag 2

SFR interrupt flag 1

SFR interrupt enable 2

SFR interrupt enable 1

IFG2

IFG1

IE2

003h

002h

001h

000h

IE1

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

†

absolute maximum ratings

Voltage applied at V

to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V

CC

SS

Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V +0.3 V

Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA

CC

Storage temperature, T (unprogrammed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C

stg

Storage temperature, T (programmed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C

stg

NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended

operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

2. All voltages referenced to V . The JTAG fuse-blow voltage, V , is allowed to exceed the absolute maximum rating. The voltage

SS

FB

is applied to the TEST pin when blowing the JTAG fuse.

3. Higher temperature may be applied during board soldering process according to the current JEDEC J−STD−020 specification with

peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

recommended operating conditions

MIN

1.8

NOM

MAX UNITS

Supply voltage during program execution, V

CC

3.6

V

Supply voltage during program/erase flash memory, V

CC

2.2

Supply voltage, V

SS

0

V

Operating free-air temperature range, T

−40

dc

85

6

°C

A

V

= 1.8 V,

CC

Duty Cycle = 50% 10%

V

= 2.7 V,

CC

Duty Cycle = 50% 10%

dc

12

16

Processor frequency f

SYSTEM

(Maximum MCLK frequency)

MHz

V

≥ 3.3 V,

CC

Duty Cycle = 50% 10%

NOTES: 1. The MSP430 CPU is clocked directly with MCLK.

Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.

2. Modules might have a different maximum input clock specification. Refer to the specification of the respective module in this

datasheet.

Legend:

16 MHz

Supply voltage range,

during flash memory

programming

12 MHz

Supply voltage range,

during program execution

6 MHz

1.8 V

2.2 V

2.7 V

3.3 V 3.6 V

Supply Voltage −V

NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V

of 2.2 V.

CC

Figure 1. Save Operating Area

20

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

active mode supply current (into V ) excluding external current (see Notes 1 and 2)

CC

PARAMETER

TEST CONDITIONS

= f = 1MHz, f

Program executes in flash,

BCSCTL1 = CALBC1_1MHz,

DCOCTL = CALDCO_1MHz,

VCC

MIN

TYP

MAX UNIT

f

= f

= 32,768Hz,

DCO MCLK SMCLK ACLK

2.2 V

220

270

µA

Active mode (AM)

current (1MHz)

I

AM, 1MHz

3 V

2.2 V

3 V

300

190

260

1.2

370

CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0

f

= f = f = 1MHz, f = 32,768Hz,

DCO MCLK SMCLK ACLK

Program executes in RAM,

Active mode (AM)

current (1MHz)

BCSCTL1 = CALBC1_1MHz,

DCOCTL = CALDCO_1MHz,

CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0

I

µA

f

= f = 32,768Hz/8 = 4,096Hz,

= f

MCLK SMCLK ACLK

2.2 V

3 V

3

f

= 0Hz,

DCO

Active mode (AM)

current (4kHz)

Program executes in flash,

SELMx = 11, SELS = 1, DIVMx = DIVSx = DIVAx = 11,

CPUOFF = 0, SCG0 = 1, SCG1 = 0, OSCOFF = 0

I

µA

4

AM, 4kHz

1.6

f

= f

≈ 100kHz, f = 0Hz,

ACLK

MCLK SMCLK DCO(0, 0)

2.2 V

3 V

37

40

50

µA

55

Active mode (AM)

current (100kHz)

Program executes in flash,

RSELx = 0, DCOx = 0,

CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 1

AM,100kHz

NOTES: 1. All inputs are tied to 0 V or V . Outputs do not source or sink any current.

CC

2. The currents are characterized with a Micro Crystal CC4V−T1A SMD cyrstal with a load capacitance of 9 pF.

The internal and external load capacitance is chosen to closely match the required 9pF.

typical characteristics − active mode supply current (into V

)

CC

5.0

4.0

3.0

2.0

1.0

0.0

4.0

f

= 16 MHz

DCO

T

= 85 °C

= 25 °C

A

3.0

T

A

V

= 3 V

CC

2.0

1.0

0.0

f

= 12 MHz

DCO

T

= 85 °C

= 25 °C

A

T

A

f

= 8 MHz

DCO

2.0

f

= 1 MHz

V

CC

= 2.2 V

DCO

1.5

2.5

3.0

3.5

4.0

0.0

4.0

8.0

12.0

16.0

V

CC

− Supply Voltage − V

f

DCO

− DCO Frequency − MHz

Figure 2. Active mode current vs V , T = 25°C

Figure 3. Active mode current vs DCO frequency

CC

A

21

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

low power mode supply currents (into V ) excluding external current (see Notes 1 and 2)

CC

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX UNIT

f

= 0MHz,

MCLK

2.2 V

65

80

µA

= f

SMCLK DCO

= 1MHz,

Low-power mode

0 (LPM0) current,

see Note 3

= 32,768Hz,

ACLK

I

LPM0, 1MHz

BCSCTL1 = CALBC1_1MHz,

DCOCTL = CALDCO_1MHz,

3 V

85

100

CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0

f

= 0MHz,

= f

= 0Hz,

MCLK

SMCLK DCO(0, 0)

ACLK

2.2 V

3 V

37

41

22

25

48

µA

52

≈ 100kHz,

Low-power mode

0 (LPM0) current,

see Note 3

I

LPM01,00kHz

RSELx = 0, DCOx = 0,

CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 1

f

= f

MCLK SMCLK

= 0MHz, f = 1MHz,

DCO

2.2 V

3 V

29

µA

32

f

= 32,768Hz,

Low-power mode

1 (LPM2) current,

see Note 4

ACLK

BCSCTL1 = CALBC1_1MHz,

DCOCTL = CALDCO_1MHz,

CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0

LPM2

T

= −40°C

= 25°C

= 85°C

= −40°C

= 25°C

= 85°C

= −40°C

= 25°C

= 85°C

= −40°C

= 25°C

= 85°C

= −40°C

= 25°C

= 85°C

0.7

1.4

0.9

1.6

0.4

0.5

1.0

0.5

0.6

1.3

0.1

0.8

1.2

1.0

A

T

A

2.2 V

3 V

Low-power mode

3 (LPM3) current,

see Note 4

f

= f = 0MHz,

= f

= 32,768Hz,

DCO MCLK SMCLK

T

A

2.3

µA

1.2

f

ACLK

I

LPM3,LFXT1

CPUOFF = 1, SCG0 = 1, SCG1 = 1,

OSCOFF = 0

T

A

T

A

1.2

2.8

0.7

T

A

T

A

T

A

2.2 V

3 V

Low-power mode

3 current, (LPM3)

see Note 4

f

= f = 0MHz,

= f

from internal LF oscillator (VLO),

DCO MCLK SMCLK

T

A

1.6

µA

0.9

f

ACLK

I

LPM3,VLO

CPUOFF = 1, SCG0 = 1, SCG1 = 1,

OSCOFF = 0

T

A

T

A

0.9

1.8

0.5

T

A

f

= f = f = 0MHz,

= 32,768Hz,

T

A

DCO MCLK SMCLK

Low-power mode

4 (LPM4) current,

see Note 5

f

ACLK

T

A

0.5

1.5

2.2 V/3 V

µA

LPM4

CPUOFF = 1, SCG0 = 1, SCG1 = 1,

OSCOFF = 1

T

A

NOTES: 1. All inputs are tied to 0 V or V . Outputs do not source or sink any current.

CC

2. The currents are characterized with a Micro Crystal CC4V−T1A SMD crystal with a load capacitance of 9 pF.

The internal and external load capacitance is chosen to closely match the required 9pF.

3. Current for brownout and WDT clocked by SMCLK included.

4. Current for brownout and WDT clocked by ACLK included.

5. Current for brownout included.

22

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

Schmitt-trigger inputs − Ports P1 and P2

PARAMETER

TEST CONDITIONS

VCC

MIN

0.45

1.00

1.35

0.25

0.55

0.75

0.2

TYP

MAX UNIT

0.75

1.65

2.25

0.55

1.20

1.65

1.0

V

CC

V

Positive-going input threshold

voltage

2.2 V

3 V

V

IT+

V

CC

V

Negative-going input threshold

voltage

2.2 V

3 V

V

IT−

2.2 V

3 V

Input voltage hysteresis (V

IT+

−

V

hys

V

)

0.3

1.0

IT−

For pull-up: V = V

For pull-down: V = V

IN

;

IN SS

R

C

Pull-up/pull-down resistor

Input Capacitance

20

35

50

kW

Pull

I

CC

V

IN

= V

SS

or V

CC

5

pF

inputs − Ports P1 and P2

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX UNIT

Port P1, P2: P1.x to P2.x, External

trigger puls width to set interrupt

flag, (see Note 1)

t

External interrupt timing

2.2 V/3 V

20

ns

(int)

NOTES: 1. An external signal sets the interrupt flag every time the minimum interrupt puls width t

(int)

is met. It may be set even with trigger signals

shorter than t

(int)

.

leakage current − Ports P1 and P2

PARAMETER

TEST CONDITIONS

see Notes 1 and 2

or V applied to the corresponding pin(s), unless otherwise noted.

VCC

MIN

TYP

MAX UNIT

50 nA

I

High-impedance leakage current

2.2 V/3 V

lkg(Px.x)

NOTES: 1. The leakage current is measured with V

SS

CC

2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pull-up/pull-down resistor is

disabled.

23

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

outputs − Ports P1 and P2

PARAMETER

TEST CONDITIONS

= −1.5 mA (see Notes 1)

= −6 mA (see Notes 2)

= −1.5 mA (see Notes 1)

= −6 mA (see Notes 2)

= 1.5 mA (see Notes 1)

= 6 mA (see Notes 2)

= 1.5 mA (see Notes 1)

= 6 mA (see Notes 2)

VCC

2.2 V

3 V

MIN

−0.25

TYP

MAX

UNIT

I

V

CC

V

CC

V

CC

V

CC

(OHmax)

(OLmax)

CC

V

−0.6

High-level output

voltage

CC

−0.25

V

OH

OL

V

CC

3 V

V

−0.6

CC

2.2 V

3 V

V

+0.25

SS

V

V +0.6

SS

Low-level output

voltage

V

+0.25

+0.6

SS

3 V

V

SS

NOTES: 1. The maximum total current, I

voltage drop specified.

and I

, for all outputs combined, should not exceed 12 mA to hold the maximum

OHmax

OLmax

2. The maximum total current, I

voltage drop specified.

and I

, for all outputs combined, should not exceed 48 mA to hold the maximum

OHmax

output frequency − Ports P1 and P2

PARAMETER

TEST CONDITIONS

VCC

2.2 V

3 V

MIN

TYP

MAX UNIT

10 MHz

12 MHz

16 MHz

Port output frequency

(with load)

P1.4/SMCLK, C = 20 pF, R = 1 kOhm

L

f

Px.y

(see Note 1 and 2)

2.2 V

3 V

P2.0/ACLK, P1.4/SMCLK, C = 20 pF

L

(see Note 2)

Clock output frequency

Port_CLK

NOTES: 1. A resistive divider with 2 times 0.5 kW between V

and V

is used as load. The output is connected to the center tap of the divider.

at the specified toggle frequency.

CC

SS

2. The output voltage reaches at least 10% and 90% V

CC

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

typical characteristics − outputs

TYPICAL LOW-LEVEL OUTPUT CURRENT

vs

LOW-LEVEL OUTPUT VOLTAGE

30.0

25.0

20.0

15.0

10.0

5.0

50.0

40.0

30.0

20.0

10.0

0.0

V

CC

P1.7

= 2.2 V

V

CC

P1.7

= 3 V

T

A

= 25°C

= 85°C

T

= 25°C

= 85°C

A

T

A

T

A

0.0

0.5

1.0

1.5

2.0

2.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

V

OL

− Low-Level Output Voltage − V

V

OL

− Low-Level Output Voltage − V

Figure 4

Figure 5

TYPICAL HIGH-LEVEL OUTPUT CURRENT

vs

HIGH-LEVEL OUTPUT VOLTAGE

0.0

−10.0

−20.0

−30.0

−40.0

−50.0

0.0

−5.0

V

= 3 V

V

= 2.2 V

CC

P1.7

CC

P1.7

−10.0

−15.0

−20.0

−25.0

T

A

= 85°C

T

= 85°C

A

T

A

= 25°C

T

= 25°C

A

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

2.5

V

OH

− High-Level Output Voltage − V

V

OH

− High-Level Output Voltage − V

Figure 6

Figure 7

NOTE: One output loaded at a time.

25

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

POR/brownout reset (BOR) (see Notes 1 and 2)

PARAMETER

TEST CONDITIONS

dV /dt ≤ 3 V/s

VCC

MIN

TYP

MAX UNIT

V

(see Figure 8)

0.7 × V

V

CC(start)

CC

(B_IT−)

(see Figure 8 through Figure 10)

(see Figure 8)

dV /dt ≤ 3 V/s

1.71

180

V

(B_IT−)

hys(B_IT−)

d(BOR)

CC

dV /dt ≤ 3 V/s

70

2

130

mV

µs

CC

t

(see Figure 8)

2000

Pulse length needed at RST/NMI pin

to accepted reset internally

t

2.2 V/3 V

µs

(reset)

NOTES: 1. The current consumption of the brownout module is already included in the I

current consumption data. The voltage level V

(B_IT−)

CC

+ V

is ≤ 1.8V.

2. During power up, the CPU begins code execution following a period of t

hys(B_IT−)

after V

CC

= V

(B_IT−)

+ V . The default

hys(B_IT−)

d(BOR)

CC(min)

DCO settings must not be changed until V

operating frequency.

≥ V

, where V

is the minimum supply voltage for the desired

CC

CC(min)

V

CC

V

hys(B_IT−)

V

(B_IT−)

V

CC(start)

1

0

t

d(BOR)

Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage

26

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

typical characteristics − POR/brownout reset (BOR)

V

t

CC

pw

2

3 V

V

= 3 V

CC

Typical Conditions

1.5

1

V

CC(drop)

0.5

0

0.001

1

1000

1 ns

− Pulse Width − µs

t

− Pulse Width − µs

t

pw

Figure 9. V

Level With a Square Voltage Drop to Generate a POR/Brownout Signal

CC(drop)

V

t

CC

pw

2

3 V

V

= 3 V

CC

Typical Conditions

1.5

1

V

CC(drop)

0.5

0

t = t

f

r

0.001

1

1000

t

r

f

t

− Pulse Width − µs

t

− Pulse Width − µs

pw

Figure 10. V

Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal

CC(drop)

27

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

main DCO characteristics

D

All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14

overlaps RSELx = 15.

D

DCO control bits DCOx have a step size as defined by parameter S

.

DCO

D

Modulation control bits MODx select how often f

is used within the period of 32 DCOCLK

DCO(RSEL,DCO+1)

cycles. The frequency f

to:

is used for the remaining cycles. The frequency is an average equal

DCO(RSEL,DCO)

32 f_{DCO(RSEL,DCO)} f_{DCO(RSEL,DCO)1)}

f_average

+

MOD f_{DCO(RSEL,DCO)})(32*MOD) f_{DCO(RSEL,DCO)1)}

DCO frequency

PARAMETER

TEST CONDITIONS

RSELx < 14

VCC

MIN

1.8

TYP

MAX UNIT

3.6

V

RSELx = 14

2.2

3.0

Vcc

Supply voltage range

RSELx = 15

f

DCO frequency (0, 0)

DCO frequency (0, 3)

DCO frequency (1, 3)

DCO frequency (2, 3)

DCO frequency (3, 3)

DCO frequency (4, 3)

DCO frequency (5, 3)

DCO frequency (6, 3)

DCO frequency (7, 3)

DCO frequency (8, 3)

DCO frequency (9, 3)

DCO frequency (10, 3)

DCO frequency (11, 3)

DCO frequency (12, 3)

DCO frequency (13, 3)

DCO frequency (14, 3)

DCO frequency (15, 3)

DCO frequency (15, 7)

Frequency step between

RSELx = 0, DCOx = 0, MODx = 0

RSELx = 0, DCOx = 3, MODx = 0

RSELx = 1, DCOx = 3, MODx = 0

RSELx = 2, DCOx = 3, MODx = 0

RSELx = 3, DCOx = 3, MODx = 0

RSELx = 4, DCOx = 3, MODx = 0

RSELx = 5, DCOx = 3, MODx = 0

RSELx = 6, DCOx = 3, MODx = 0

RSELx = 7, DCOx = 3, MODx = 0

RSELx = 8, DCOx = 3, MODx = 0

RSELx = 9, DCOx = 3, MODx = 0

RSELx = 10, DCOx = 3, MODx = 0

RSELx = 11, DCOx = 3, MODx = 0

RSELx = 12, DCOx = 3, MODx = 0

RSELx = 13, DCOx = 3, MODx = 0

RSELx = 14, DCOx = 3, MODx = 0

RSELx = 15, DCOx = 3, MODx = 0

RSELx = 15, DCOx = 7, MODx = 0

2.2 V/3 V

3 V

0.06

0.07

0.10

0.14

0.20

0.28

0.39

0.54

0.80

1.10

1.60

2.50

3.00

4.30

6.00

8.60

12.0

16.0

0.14 MHz

0.17 MHz

0.20 MHz

0.28 MHz

0.40 MHz

0.54 MHz

0.77 MHz

1.06 MHz

1.50 MHz

2.10 MHz

3.00 MHz

4.30 MHz

5.50 MHz

7.30 MHz

9.60 MHz

13.9 MHz

18.5 MHz

26.0 MHz

DCO(0,0)

DCO(0,3)

DCO(1,3)

DCO(2,3)

DCO(3,3)

DCO(4,3)

DCO(5,3)

DCO(6,3)

DCO(7,3)

DCO(8,3)

DCO(9,3)

DCO(10,3)

DCO(11,3)

DCO(12,3)

DCO(13,3)

DCO(14,3)

DCO(15,3)

DCO(15,7)

3 V

S

f =

/f

2.2 V/3 V

1.55

ratio

1.12

RSEL

DCO

RSDECLO(RSEL+1,DCO) DCO(RSEL,DCO)

range RSEL and RSEL+1

Frequency step between

tap DCO and DCO+1

S

S f =

DCDOCO(RSEL,DCO+1) DCO(RSEL,DCO)

2.2 V/3 V

1.05

40

1.08

50

Duty Cycle

Measured at P1.4/SMCLK

60

%

28

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

calibrated DCO frequencies − tolerance at calibration

PARAMETER

TEST CONDITIONS

T

VCC

MIN

−1

TYP

0.2

MAX UNIT

+1

A

Frequency tolerance at calibration

25°C

3 V

%

BCSCTL1= CALBC1_1MHz;

DCOCTL = CALDCO_1MHz

Gating time: 5ms

f

1MHz calibration value

8MHz calibration value

25°C

3 V

0.990

7.920

11.88

15.84

1

8

1.010 MHz

8.080 MHz

CAL(1MHz)

BCSCTL1= CALBC1_8MHz;

DCOCTL = CALDCO_8MHz

Gating time: 5ms

f

25°C

CAL(8MHz)

BCSCTL1= CALBC1_12MHz;

12MHz calibration value DCOCTL = CALDCO_12MHz

Gating time: 5ms

f

12 12.12 MHz

16 16.16 MHz

CAL(12MHz)

BCSCTL1= CALBC1_16MHz;

16MHz calibration value DCOCTL = CALDCO_16MHz

Gating time: 2ms

f

CAL(16MHz)

calibrated DCO frequencies − tolerance over temperature 0°C − +85°C

PARAMETER

TEST CONDITIONS

T

VCC

3.0 V

2.2 V

3.0 V

3.6 V

2.2 V

3.0 V

3.6 V

2.2 V

3.0 V

3.6 V

MIN

TYP

MAX UNIT

A

1 MHz tolerance over temperature

8 MHz tolerance over temperature

12 MHz tolerance over temperature

16 MHz tolerance over temperature

0°C − +85°C

−2.5

0.5

1.0

2.0

1

+2.5

+3.0

%

−2.5

−3.0

0.970

0.975

0.970

7.760

7.800

7.600

11.70

1.030 MHz

1.025 MHz

1.030 MHz

8.400 MHz

8.200 MHz

8.240 MHz

BCSCTL1= CALBC1_1MHz;

DCOCTL = CALDCO_1MHz

Gating time: 5ms

1

f

1MHz calibration value

8MHz calibration value

0°C − +85°C

CAL(1MHz)

1

8

BCSCTL1= CALBC1_8MHz;

DCOCTL = CALDCO_8MHz

Gating time: 5ms

8

f

CAL(8MHz)

8

12 12.30 MHz

BCSCTL1= CALBC1_12MHz;

DCOCTL = CALDCO_12MHz

Gating time: 5ms

f

12MHz calibration value

16MHz calibration value

0°C − +85°C

CAL(12MHz)

BCSCTL1= CALBC1_16MHz;

DCOCTL = CALDCO_16MHz

Gating time: 2ms

3.0 V

3.6 V

15.52

15.00

16 16.48 MHz

f

CAL(16MHz)

29

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

calibrated DCO frequencies − tolerance over supply voltage V

CC

PARAMETER

TEST CONDITIONS

T

VCC

MIN

−2.5

−3

TYP

MAX UNIT

A

1 MHz tolerance over V

8 MHz tolerance over V

25°C

1.8 V − 3.6 V

2.2 V − 3.6 V

3.0 V − 3.6 V

2

+2.5

+3

%

CC

2

CC

12 MHz tolerance over V

CC

16 MHz tolerance over V

BCSCTL1= CALBC1_1MHz;

DCOCTL = CALDCO_1MHz

Gating time: 5ms

f

1MHz calibration value

8MHz calibration value

25°C

1.8 V − 3.6 V

2.2 V − 3.6 V

3.0 V − 3.6 V

0.970

7.760

11.64

15.00

1

8

1.030 MHz

8.240 MHz

CAL(1MHz)

BCSCTL1= CALBC1_8MHz;

DCOCTL = CALDCO_8MHz

Gating time: 5ms

f

CAL(8MHz)

BCSCTL1= CALBC1_12MHz;

12MHz calibration value DCOCTL = CALDCO_12MHz

Gating time: 5ms

f

12 12.36 MHz

16 16.48 MHz

CAL(12MHz)

BCSCTL1= CALBC1_16MHz;

16MHz calibration value DCOCTL = CALDCO_16MHz

Gating time: 2ms

f

CAL(16MHz)

calibrated DCO frequencies − overall tolerance

PARAMETER

TEST CONDITIONS

T

VCC

MIN

−5

TYP

MAX UNIT

A

1 MHz tolerance overall

8 MHz tolerance overall

12 MHz tolerance overall

16 MHz tolerance overall

−40°C − +85°C

1.8 V − 3.6 V

2.2 V − 3.6 V

3.0 V − 3.6 V

2

3

+5

+6

%

−5

−6

BCSCTL1= CALBC1_1MHz;

DCOCTL = CALDCO_1MHz

Gating time: 5ms

f

1MHz calibration value

8MHz calibration value

−40°C − +85°C

1.8 V − 3.6 V

2.2 V − 3.6 V

3.0 V − 3.6 V

0.950

7.600

11.40

15.00

1

8

1.050 MHz

8.400 MHz

CAL(1MHz)

BCSCTL1= CALBC1_8MHz;

DCOCTL = CALDCO_8MHz

Gating time: 5ms

f

CAL(8MHz)

BCSCTL1= CALBC1_12MHz;

f

12MHz calibration value DCOCTL = CALDCO_12MHz −40°C − +85°C

12 12.60 MHz

16 17.00 MHz

CAL(12MHz)

Gating time: 5ms

BCSCTL1= CALBC1_16MHz;

16MHz calibration value DCOCTL = CALDCO_16MHz −40°C − +85°C

Gating time: 2ms

f

CAL(16MHz)

30

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

typical characteristics − calibrated 1MHz DCO frequency

1.03

1.02

V

= 1.8 V

= 2.2 V

CC

1.01

1.00

0.99

0.98

0.97

CC

V

CC

= 3.0 V

V

CC

= 3.6 V

−50.0 −25.0

0.0

25.0

50.0

75.0 100.0

T

A

− Temperature − °C

Figure 11. Calibrated 1 MHz Frequency vs. Temperature

1.03

1.02

1.01

T

= 85 °C

= 25 °C

A

1.00

0.99

0.98

0.97

T

A

T

A

= −40 °C

1.5

2.0

2.5

3.0

3.5

4.0

V

CC

− Supply Voltage − V

Figure 12. Calibrated 1 MHz Frequency vs. V

CC

31

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

wake-up from lower power modes (LPM3/4)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX UNIT

BCSCTL1= CALBC1_1MHz;

DCOCTL = CALDCO_1MHz

2.2 V/3 V

2

BCSCTL1= CALBC1_8MHz;

DCOCTL = CALDCO_8MHz

2.2 V/3 V

3 V

1.5

DCO clock wake-up time from

LPM3/4

(see Note 1)

t

µs

DCO,LPM3/4

BCSCTL1= CALBC1_12MHz;

DCOCTL = CALDCO_12MHz

1

BCSCTL1= CALBC1_16MHz;

DCOCTL = CALDCO_16MHz

1

CPU wake-up time from LPM3/4

(see Note 2)

1/f

+

MCLK

CPU,LPM3/4

t

Clock,LPM3/4

NOTES: 1. The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g. port interrupt) to the first clock edge

observable externally on a clock pin (MCLK or SMCLK).

2. Parameter applicable only if DCOCLK is used for MCLK.

typical characteristics − DCO clock wake-up time from LPM3/4

10.00

RSELx = 0...11

1.00

0.10

RSELx = 12...15

0.10

1.00

DCO Frequency − MHz

10.00

Figure 13. Clock wake-up time from LPM3 vs DCO frequency

32

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

crystal oscillator, LFXT1, low frequency modes (see Note 4)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX UNIT

LFXT1 oscillator crystal

frequency, LF mode 0, 1

f

XTS = 0, LFXT1Sx = 0 or 1

1.8 V − 3.6 V

32,768

Hz

LFXT1,LF

LFXT1 oscillator logic level

square wave input frequency,

LF mode

f

XTS = 0, LFXT1Sx = 3

XTS = 0, LFXT1Sx = 0;

1.8 V − 3.6 V

10,000 32,768 50,000

Hz

kW

LFXT1,LF,logic

f

C

= 32,768 kHz,

500

200

LFXT1,LF

= 6 pF

L,eff

XTS = 0, LFXT1Sx = 0;

= 32,768 kHz,

Oscillation Allowance for LF

crystals

OA

LF

f

LFXT1,LF

= 12 pF

C

L,eff

XTS = 0, XCAPx = 0

XTS = 0, XCAPx = 1

XTS = 0, XCAPx = 2

XTS = 0, XCAPx = 3

XTS = 0, Measured at

1

5.5

8.5

11

pF

Integrated effective Load

Capacitance, LF mode

(see Note 1)

C

L,eff

Duty Cycle

LF mode

P1.4/ACLK, f

Hz

= 32,768

2.2 V/3 V

30

10

50

70

%

LFXT1,LF

Osc. fault frequency threshold,

LF mode (see Note 3)

XTS = 0, LFXT1Sx = 3

(see Note 2)

f

10,000

Hz

Fault,LF

NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin).

Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a

correct setup the effective load capacitance should always match the specification of the used crystal.

2. Measured with logic level input frequency but also applies to operation with crystals.

3. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.

Frequencies in between might set the flag.

4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.

− Keep as short of a trace as possible between the device and the crystal.

− Design a good ground plane around the oscillator pins.

− Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

− Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

− Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.

− If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

− Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other

documentation. This signal is no longer required for the serial programming adapter.

internal very low power, low frequency oscillator (VLO)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

12

MAX UNIT

f

VLO frequency

2.2 V/3 V

4

20

kHz

VLO

df

VLO

/dT

VLO frequency temperature drift (see Note 1)

VLO frequency supply voltage

0.5

%/°C

df /dV

VLO CC

T

A

= 25°C (see Note 2)

1.8V...3.6V

4

%/V

drift

NOTES: 1. Calculated using the box method: (MAX(−40...85_C) − MIN(−40...85_C))/MIN(−40...85_C)/(85_C − (−40_C))

2. Calculated using the box method: (MAX(1.8...3.6V) − MIN(1.8...3.6V))/MIN(1.8...3.6V)/(3.6V − 1.8V)

33

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

Timer_A

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK;

External: TACLK, INCLK;

Duty Cycle = 50% 10%

2.2 V

10

f

t

Timer_A clock frequency

Timer_A, capture timing

MHz

16

TA

3 V

TA0, TA1

2.2 V/3 V

20

ns

TA,cap

USI, Universal Serial Interface (MSP430x20x2, MSP430x20x3 only)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX UNIT

External: SCLK;

2.2 V

10

f

USI clock frequency

MHz

16

Duty Cycle = 50% 10%;

SPI Slave Mode

USI

3 V

Low-level output voltage on SDA

and SCL

USI module in I2C mode

V

2.2 V/3 V

V

SS

V +0.4

SS

V

OL,I2C

I

= 1.5 mA

(OLmax)

typical characteristics − USI low-level output voltage on SDA and SCL (MSP430x20x2, MSP430x20x3 only)

5.0

4.0

3.0

2.0

1.0

0.0

5.0

4.0

3.0

2.0

1.0

0.0

T

A

= 25°C

V

CC

= 2.2 V

V

CC

= 3 V

T

= 25°C

= 85°C

A

T

A

= 85°C

T

A

0.0

0.2

0.4

0.6

0.8

1.0

0.0

0.2

0.4

0.6

0.8

1.0

V

OL

− Low-Level Output Voltage − V

V

OL

− Low-Level Output Voltage − V

Figure 14. USI Low-Level Output Voltage vs.

Output Current

Figure 15. USI Low-Level Output Voltage vs.

Output Current

34

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

MSP430x20x1 electrical characteristics over recommended ranges of supply voltage and

operating free-air temperature (unless otherwise noted)

Comparator_A+ (see Note 1, MSP430x20x1 only)

PARAMETER

TEST CONDITIONS

VCC

2.2 V

3 V

MIN

TYP

25

MAX UNIT

40

µA

60

I

CAON=1, CARSEL=0, CAREF=0

(DD)

45

30

CAON=1, CARSEL=0,

CAREF=1/2/3,

no load at P1.0/CA0 and P1.1/CA1

2.2 V

3 V

50

µA

71

(Refladder/RefDiode)

45

Common-mode input

voltage

V

CAON=1

2.2 V/3 V

0

V

CC

−1

V

(IC)

Voltage @ 0.25 V

node

PCA0=1, CARSEL=1, CAREF=1,

no load at P1.0/CA0 and P1.1/CA1

CC

V

0.23

0.47

0.24

0.48

0.25

0.5

(Ref025)

V

CC

node

Voltage @ 0.5V

PCA0=1, CARSEL=1, CAREF=2,

no load at P1.0/CA0 and P1.1/CA1

CC

V

2.2 V/3 V

(Ref050)

(RefVT)

V

CC

PCA0=1, CARSEL=1, CAREF=3,

no load at P1.0/CA0 and P1.1/CA1,

2.2 V

3 V

390

400

480

490

540

550

V

(see Figure 19 and Figure 20)

mV

T

A

= 85°C

V

Offset voltage

See Note 2

CAON=1

2.2 V/3 V

−30

0

30

mV

(offset)

Input hysteresis

0.7

1.4

hys

T

= 25°C, Overdrive 10 mV,

A

2.2 V

3 V

80

70

165

300

240

2.8

2.2

Without filter: CAF=0

(see Note 3, Figure 16 and

Figure 17)

ns

120

1.9

1.5

Response time

(low−high and high−low)

t

(response)

T

= 25°C, Overdrive 10 mV,

A

2.2 V

1.4

0.9

With filter: CAF=1

(see Note 3, Figure 16 and

Figure 17)

µs

3 V

NOTES: 1. The leakage current for the Comparator_A+ terminals is identical to I

specification.

lkg(Px.x)

2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements.

The two successive measurements are then summed together.

3. Response time measured at P1.3/CAOUT.

35

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

MSP430x20x1 electrical characteristics over recommended ranges of supply voltage and

operating free-air temperature (unless otherwise noted) (continued)

0 V

V

CC

0

1

CAF

CAON

To Internal

Modules

Low Pass Filter

0

1

0

1

+

_

V+

V−

CAOUT

Set CAIFG

Flag

τ ≈ 2.0 µs

Figure 16. Block Diagram of Comparator_A+ Module

V

CAOUT

Overdrive

V−

400 mV

V+

t

(response)

Figure 17. Overdrive Definition

CASHORT

CA1

CA0

1

+

−

I

= 10µA

OUT

V

IN

Comparator_A+

CASHORT = 1

Figure 18. Comparator_A+ Short Resistance Test Condition

36

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

MSP430x20x1 electrical characteristics over recommended ranges of supply voltage and

operating free-air temperature (unless otherwise noted) (continued)

typical characteristics − Comparator_A+ (MSP430x20x1 only)

650

600

550

500

450

400

650

600

550

500

450

400

V

= 2.2 V

V

CC

= 3 V

CC

Typical

−45

−25

−5

15

35

55

75

95

−45

−25

−5

15

35

55

75

95

T

A

− Free-Air Temperature − °C

T

A

− Free-Air Temperature − °C

Figure 20. V

vs Temperature, V

= 2.2 V

Figure 19. V

vs Temperature, V

= 3 V

(RefVT)

CC

(RefVT)

CC

100.00

10.00

1.00

V

CC

= 1.8V

V

= 2.2V

CC

V

CC

= 3.0V

V

CC

= 3.6V

0.6

0.0

0.2

/V

0.4

0.8

1.0

V

− Normalized Input Voltage − V/V

IN CC

Figure 21. Short Resistance vs V /V

IN CC

37

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

MSP430x20x2 electrical characteristics over recommended ranges of supply voltage and

operating free-air temperature (unless otherwise noted) (continued)

10-bit ADC, power supply and input range conditions (see Note 1, MSP430x20x2 only)

PARAMETER

TEST CONDITIONS

= 0 V

SS

VCC

MIN

2.2

TYP

MAX UNIT

V

CC

Analog supply voltage range

V

3.6

V

All Ax terminals.

Analog inputs selected in ADC10AE

register.

Analog input voltage range

(see Note 2)

V

Ax

0

V

CC

V

f

= 5.0 MHz

ADC10CLK

2.2 V

3 V

0.52

0.6

1.05

1.2

ADC10 supply current

(see Note 3)

ADC10ON = 1, REFON = 0

ADC10SHT0 = 1, ADC10SHT1 = 0,

ADC10DIV = 0

I

mA

ADC10

f

= 5.0 MHz

ADC10CLK

REF2_5V=0

REF2_5V=1

2.2 V/3 V

3 V

mA

Reference supply current,

reference buffer disabled

(see Note 4)

ADC10ON = 0,

REFON = 1,

REFOUT = 0

I

0.25

0.4

REF+

REFB

f

= 5.0 MHz

ADC10CLK

ADC10SR=0 2.2 V/3 V

ADC10SR=1 2.2 V/3 V

1.1

1.4

mA

ADC10ON = 0,

REFON = 1,

REF2_5V = 0

REFOUT = 1

Reference buffer supply current

(see Note 4)

I

0.46

0.55

Only one terminal Ax selected at a

time

C

R

Input capacitance

27

pF

I

Input MUX ON resistance

0V ≤ V ≤ V

Ax CC

2.2 V/3 V

2000

Ω

NOTES: 1. The leakage current is defined in the leakage current table with Px.x/Ax parameter.

2. The analog input voltage range must be within the selected reference voltage range V

to V

for valid conversion results.

R+

R−

3. The internal reference supply current is not included in current consumption parameter I

.

ADC10

4. The internal reference current is supplied via terminal V . Consumption is independent of the ADC10ON control bit, unless a

CC

conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.

38

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

MSP430x20x2 electrical characteristics over recommended ranges of supply voltage and

operating free-air temperature (unless otherwise noted) (continued)

10-bit ADC, built-in voltage reference (MSP430x20x2 only)

PARAMETER

TEST CONDITIONS

VCC

MIN TYP

MAX UNIT

I

≤ 1mA, REF2_5V=0

≤ 0.5mA, REF2_5V=1

≤ 1mA, REF2_5V=1

2.2

V

VREF+

CC

Positive built-in reference analog

supply voltage range

V

+0.15

REF+

V

CC,REF+

V

+0.15

REF+

1.41

≤ I

max, REF2_5V=0 2.2 V/3 V

1.5

2.5

1.59

2.65

0.5

1

V

VREF+ VREF+

Positive built-in reference voltage

REF+

≤ I max, REF2_5V=1

VREF+ VREF+

3 V

2.2 V

3 V

2.35

I

Maximum V

REF+

load current

mA

LD,VREF+

I

= 500 µA +/− 100 µA

VREF+

Analog input voltage V ≈ 0.75 V;

REF2_5V=0

2.2 V/3 V

3 V

2

LSB

Ax

V

load regulation

REF+

I

= 500 µA 100 µA

VREF+

Analog input voltage V ≈ 1.25 V;

REF2_5V=1

2

LSB

Ax

I

=

VREF+

100µA→900µA,

≈ 0.5 x V

ADC10SR=0

ADC10SR=1

3 V

3V

400

V

load regulation response time

ns

Ax

REF+

Error of conversion

result ≤ 1 LSB

2000

100

Max. capacitance at pin V

(see Note 1)

I

≤

1mA,

REF+

VREF+

C

2.2 V/3 V

pF

VREF+

REFON=1, REFOUT=1

I

= const. with

VREF+

0 mA ≤ I

TC

Temperature coefficient

100 ppm/°C

REF+

≤ 1 mA

VREF+

Settling time of internal reference

voltage (see Note 2)

I

= 0.5 mA, REF2_5V=0

VREF+

3.6 V

2.2 V

30

t

REFON

REFON = 0 → 1

I

= 0.5 mA,

VREF+

µs

ADC10SR=0

ADC10SR=1

1

Settling time of reference buffer

(see Note 2)

REF2_5V=0,

REFON = 1,

t

REFBURST

2.5

REFBURST = 1

NOTES: 1. The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA2/A4/V

/V (REFOUT=1),

REF+ eREF+

must be limited; the reference buffer may become unstable otherwise.

2. The condition is that the error in a conversion started after t

REFON

or t is less than 0.5 LSB.

RefBuf

39

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

MSP430x20x2 electrical characteristics over recommended ranges of supply voltage and

operating free-air temperature (unless otherwise noted) (continued)

10-bit ADC, external reference (see Note 1, MSP430x20x2 only)

PARAMETER

TEST CONDITIONS

VCC

MIN

1.4

TYP

MAX UNIT

V

> V

eREF+

eREF−

V

CC

3.0

SREF1 = 1, SREF0 = 0

Positive external reference input

voltage range (see Note 2)

V

eREF+

V

≤ V

− 0.15V

eREF−

eREF+ CC

1.4

0

SREF1 = 1, SREF0 = 1 (see Note 3)

Negative external reference input

voltage range (see Note 4)

V

> V

1.2

eREF−

eREF+

eREF−

Differential external reference input

voltage range

∆V

eREF

V

> V

(see Note 5)

1.4

V

eREF+

eREF−

CC

1

∆V

eREF

= V

− V

eREF+

eREF−

0V ≤ V

SREF1 = 1, SREF0 = 0

≤ V ,

CC

eREF+

2.2 V/3 V

µA

I

Static input current into V

VeREF+

eREF+

0V ≤V

eREF+

≤ V − 0.15V ≤ 3V

CC

2.2 V/3 V

0

1

µA

SREF1 = 1, SREF0 = 1 (see Note 3)

0V ≤ V ≤ V

VeREF−

eREF−

eREF− CC

NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, C , is also

I

the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the

recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.

2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced

accuracy requirements.

3. Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer

supply current I

REFB

. The current consumption can be limited to the sample and conversion period with REBURST = 1.

4. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced

accuracy requirements.

5. The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied

with reduced accuracy requirements.

40

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ꢀ ꢊꢋꢌ ꢍ ꢁꢊ ꢎ ꢏꢐꢑ ꢀ ꢊꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢌꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

MSP430x20x2 electrical characteristics over recommended ranges of supply voltage and

operating free-air temperature (unless otherwise noted) (continued)

10-bit ADC, timing parameters (MSP430x20x2 only)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX UNIT

For specified

performance of

ADC10 linearity

parameters

ADC10SR=0 2.2 V/3 V

ADC10SR=1 2.2 V/3 V

0.45

6.3

f

ADC10 input clock frequency

MHz

1.5

ADC10CLK

0.45

3.7

ADC10DIVx=0, ADC10SSELx = 0

= f

ADC10 built-in oscillator frequency

2.2 V/3 V

6.3 MHz

ADC10OSC

f

ADC10CLK ADC10OSC

ADC10 built-in oscillator,

ADC10SSELx = 0

2.06

3.51

100

µs

f

= f

ADC10CLK ADC10OSC

t

Conversion time

CONVERT

13×

f

from ACLK, MCLK or

ADC10CLK

ADC10DIV×

1/f

µs

SMCLK: ADC10SSELx ≠ 0

ADC10CLK

Turn on settling time of the ADC

(see Note 1)

ns

ADC10ON

NOTES: 1. The condition is that the error in a conversion started after t

settled.

is less than 0.5 LSB. The reference and input signal are already

ADC10ON

10-bit ADC, linearity parameters (MSP430x20x2 only)

PARAMETER

Integral linearity error

Differential linearity error

Offset error

TEST CONDITIONS

VCC

MIN

TYP

MAX UNIT

E

2.2 V/3 V

1

2

5

LSB

I

D

O

G

T

Source impedance R < 100 Ω,

S

1.1

Gain error

2

Total unadjusted error

41

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ꢀ ꢊ ꢋ ꢌꢍ ꢁꢊ ꢎꢏ ꢐ ꢑ ꢀꢊ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢌ ꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

MSP430x20x2 electrical characteristics over recommended ranges of supply voltage and

operating free-air temperature (unless otherwise noted) (continued)

10-bit ADC, temperature sensor and built-in V

(MSP430x20x2 only)

MID

PARAMETER

TEST CONDITIONS

VCC

2.2 V

3 V

MIN

TYP

40

MAX

120

160

UNIT

Temperature sensor supply

current (see Note 1)

REFON = 0, INCHx = 0Ah,

I

µA

SENSOR

T

A

= 25_C

ADC10ON = 1, INCHx = 0Ah

(see Notes 2, 3)

60

†

2.2 V/3 V

3.44

3.55

3.66 mV/°C

TC

SENSOR

ADC10ON = 1, INCHx = 0Ah

(see Notes 2, 3)

V

Sensor offset voltage

−100

TBD

935

100

TBD

1035

mV

Offset,Sensor

Temperature sensor voltage

2.2 V/3 V

TBD

985

at T = 85°C

A

Temperature sensor voltage

Sensor output voltage

(see Note 4)

V

Sensor

at T = 25°C

A

Temperature sensor voltage

at T = 0°C (see Note 2)

A

Sample time required if

channel 10 is selected (see

Note 5)

ADC10ON = 1, INCHx = 0Ah,

Error of conversion result ≤ 1 LSB

2.2 V/3 V

30

µs

t

Sensor(sample)

2.2 V

3 V

NA

Current into divider at channel

11 (see Note 6)

I

ADC10ON = 1, INCHx = 0Bh,

µA

VMID

2.2 V

3 V

1.06

1.46

1.1

1.5

1.14

1.54

V

CC

divider at channel 11

V

MID

V

MID

is ≈0.5 x V

CC

Sample time required if

channel 11 is selected (see

Note 7)

2.2 V

3 V

1400

1220

ADC10ON = 1, INCHx = 0Bh,

Error of conversion result ≤ 1 LSB

t

ns

VMID(sample)

†

Not production tested, limits characterized

NOTES: 1. The sensor current I

is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON=1 and INCH=0Ah and sample signal

is included in I . When REFON = 0, I applies during conversion of the temperature

SENSOR

is high). When REFON = 1, I

SENSOR

sensor input (INCH = 0Ah).

2. Not production tested, limits characterized.

3. The following formula can be used to calculate the temperature sensor output voltage:

REF+ SENSOR

V

= TC

( 273 + T [°C] ) + V [mV] or

Offset,sensor

Sensor,typ

Sensor

T [°C] + V

(T = 0°C) [mV]

Sensor

A

4. Results based on characterization and/or production test, not TC

5. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t

or V .

Offset,sensor

Sensor

.

SENSOR(on)

6. No additional current is needed. The V

is used during sampling.

MID

7. The on-time t

VMID(on)

is included in the sampling time t ; no additional on time is needed.

VMID(sample)

42

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

MSP430x20x3 electrical characteristics over recommended ranges of supply voltage and

operating free-air temperature (unless otherwise noted)

SD16_A, power supply and recommended operating conditions (MSP430x20x3 only)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

3.6

UNIT

AV

= DV

= V

CC

SS

CC

SS

CC

SS

AV

CC

Analog supply voltage range

2.5

V

= 0V

GAIN: 1,2

GAIN: 4,8,16

GAIN: 32

3 V

730

1050

1150

1700

SD16LP = 0,

= 1 MHz,

SD16OSR = 256

810

f

SD16

Analog supply current

including internal reference

1160

I_SD16

µA

SD16LP = 1,

GAIN: 1

3 V

720

810

1030

1150

f

= 0.5 MHz,

SD16

GAIN: 32

SD16OSR = 256

SD16LP = 0

(Low power mode disabled)

3 V

0.03

1

1.1

f

SD16 input clock frequency

MHz

SD16

SD16LP = 1

(Low power mode enabled)

0.5

SD16_A, input range (MSP430x20x3 only)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

−(V

REF

GAIN

/2)/ +(V

/2)/

GAIN

REF

Bipolar Mode, SD16UNI = 0

mV

Differential full scale input voltage

range (see Note 1)

V

ID,FSR

+(V

/2)/

REF

GAIN

Unipolar Mode, SD16UNI = 1

0

mV

kΩ

SD16GAINx=1

500

250

125

62

SD16GAINx=2

SD16GAINx=4

SD16GAINx=8

SD16GAINx=16

SD16GAINx=32

SD16GAINx=1

SD16GAINx=32

SD16GAINx=1

SD16GAINx=32

Differential input voltage range

for specified performance

(see Note 1)

V

ID

SD16REFON=1

31

15

3 V

200

75

Input impedance

(one input pin to AV

Z

f

= 1MHz

I

SD16

)

SS

300

100

400

150

Differential Input impedance

(IN+ to IN−)

kΩ

V

ID

SD16

AV

SS

-0.1V

V

I

Absolute input voltage range

AV

CC

Common-mode input voltage

range

AV

SS

-0.1V

V

IC

V

CC

NOTES: 1. The analog input range depends on the reference voltage applied to V

. If V is sourced externally, the full-scale range

REF

is defined by V

FSR+

= +(V /2)/GAIN and V

REF FSR−

= −(V /2)/GAIN. The analog input range should not exceed 80% of

REF

V

or V .

FSR+

FSR−

43

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅꢆꢈ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢅ ꢆꢇ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢅ ꢆ ꢄ

ꢀ ꢊ ꢋ ꢌꢍ ꢁꢊ ꢎꢏ ꢐ ꢑ ꢀꢊ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢌ ꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

MSP430x20x3 electrical characteristics over recommended ranges of supply voltage and

operating free-air temperature (unless otherwise noted) (continued)

SD16_A, SINAD performance (f

= 1MHz, SD16OSRx = 1024, SD16REFON = 1, MSP430x20x3 only)

SD16

PW, or N

MIN TYP

RSA

PARAMETER

TEST CONDITIONS

VCC

UNIT

MIN

TYP

SD16GAINx = 1,

Signal Amplitude: V = 500mV,

Signal Frequency: f = 100Hz

IN

3 V

84

82

78

73

68

62

85

83

79

74

69

63

TBD

IN

SD16GAINx = 2,

Signal Amplitude: V = 250mV,

3 V

TBD

IN

Signal Frequency: f = 100Hz

IN

SD16GAINx = 4,

Signal Amplitude: V = 125mV,

IN

Signal Frequency: f = 100Hz

IN

Signal-to-Noise + Distortion Ratio

(OSR = 1024)

SINAD

1024

dB

SD16GAINx = 8,

Signal Amplitude: V = 62mV,

IN

Signal Frequency: f = 100Hz

IN

SD16GAINx = 16,

Signal Amplitude: V = 31mV,

IN

Signal Frequency: f = 100Hz

IN

SD16GAINx = 32,

Signal Amplitude: V = 15mV,

IN

Signal Frequency: f = 100Hz

IN

SD16_A, SINAD performance (f

= 1MHz, SD16OSRx = 256, SD16REFON = 1, MSP430x20x3 only)

SD16

PW, or N

MIN TYP

RSA

PARAMETER

TEST CONDITIONS

VCC

UNIT

MIN

TYP

SD16GAINx = 1,

Signal Amplitude: V = 500mV,

Signal Frequency: f = 100Hz

IN

3 V

80

74

69

63

58

52

81

75

70

64

59

53

TBD

IN

SD16GAINx = 2,

Signal Amplitude: V = 250mV,

3 V

TBD

IN

Signal Frequency: f = 100Hz

IN

SD16GAINx = 4,

Signal Amplitude: V = 125mV,

IN

Signal Frequency: f = 100Hz

IN

Signal-to-Noise + Distortion Ratio

(OSR = 256)

SINAD

256

dB

SD16GAINx = 8,

Signal Amplitude: V = 62mV,

IN

Signal Frequency: f = 100Hz

IN

SD16GAINx = 16,

Signal Amplitude: V = 31mV,

IN

Signal Frequency: f = 100Hz

IN

SD16GAINx = 32,

Signal Amplitude: V = 15mV,

IN

Signal Frequency: f = 100Hz

IN

44

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ꢀ ꢊꢋꢌ ꢍ ꢁꢊ ꢎ ꢏꢐꢑ ꢀ ꢊꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢌꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

MSP430x20x3 electrical characteristics over recommended ranges of supply voltage and

operating free-air temperature (unless otherwise noted) (continued)

typical characteristics − SD16_A SINAD performance over OSR (MSP430x20x3 only)

100.0

95.0

90.0

85.0

80.0

75.0

70.0

65.0

60.0

PW, or N

55.0

50.0

10.00

100.00

OSR

1000.00

Figure 22. SINAD performance over OSR, f

= 1MHz, SD16REFON = 1, SD16GAINx = 1

SD16

SD16_A, performance (f

= 1MHz, SD16OSRx = 256, SD16REFON = 1, MSP430x20x3 only)

SD16

PARAMETER

TEST CONDITIONS

SD16GAINx = 1

VCC

3 V

MIN

0.97

TYP

1.00

MAX

1.02

2.02

3.96

7.84

UNIT

SD16GAINx = 2

1.90

3.76

7.36

1.96

3.86

7.62

SD16GAINx = 4

G

Nominal Gain (see Note 1)

SD16GAINx = 8

SD16GAINx = 16

SD16GAINx = 32

SD16GAINx = 1 (see Note 2)

14.56 15.04 15.52

27.20 28.35 29.76

15

dG/dT

dG/dV

Gain Temperature Drift

ppm/_C

SD16GAINx = 1; V

(see Note 3)

= 2.5V - 3.6V

CC

Gain Supply Voltage Drift

2.5V-3.6V

0.35

%/V

CC

SD16GAINx = 1

SD16GAINx = 32

SD16GAINx = 1

SD16GAINx = 32

SD16GAINx = 1,

3 V

0.2

1.5

E

Offset Error (see Note 1)

%FSR

OS

4

20

Offset Error Temperature

Coefficient (see Note 1)

ppm

FSR/_C

dE /dT

OS

20

100

Common-mode input signal:

= 500 mV, f = 50 Hz, 100 Hz

3 V

>90

V

ID

IN

CMRR

PSRR

Common-Mode Rejection Ratio

Power Supply Rejection Ratio

dB

SD16GAINx = 32,

Common-mode input signal:

3 V

>75

>80

V

= 16 mV, f = 50 Hz, 100 Hz

ID

SD16GAINx = 1

IN

NOTES: 1. Not production tested, limits characterized.

2. Calculated using the box method: (MAX(−40...85_C) − MIN(−40...85_C))/MIN(−40...85_C)/(85_C − (−40_C))

3. Calculated using the box method: (MAX(2.5...3.6V) − MIN(2.5...3.6V))/MIN(2.5...3.6V)/(3.6V − 2.5V)

45

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ꢀ ꢊ ꢋ ꢌꢍ ꢁꢊ ꢎꢏ ꢐ ꢑ ꢀꢊ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢌ ꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

MSP430x20x3 electrical characteristics over recommended ranges of supply voltage and

operating free-air temperature (unless otherwise noted) (continued)

SD16_A, temperature sensor (MSP430x20x3 only)

PARAMETER

TEST CONDITIONS

See Note 1

VCC

MIN

1.18

TYP

1.32

MAX

1.46

100

UNIT

mV/K

mV

TC

Sensor

Sensor temperature coefficient

Sensor offset voltage

V

See Note 1

−100

Offset,Sensor

Temperature sensor voltage

3 V

435

475

395

360

515

435

400

at T = 85°C

A

Temperature sensor voltage

Sensor output voltage

(see Note 3)

355

320

V

mV

Sensor

at T = 25°C

A

Temperature sensor voltage

at T = 0°C (see Note 1)

A

NOTES: 1. Not production tested, limits characterized.

2. The following formula can be used to calculate the temperature sensor output voltage:

V

= TC

( 273 + T [°C] ) + V [mV] or

Sensor,typ

Sensor

Offset,sensor

T [°C] + V

Sensor

(T = 0°C) [mV]

A

3. Results based on characterization and/or production test, not TC

or V .

Offset,sensor

Sensor

SD16_A, built-in voltage reference (MSP430x20x3 only)

PARAMETER

TEST CONDITIONS

VCC

3 V

MIN

TYP

MAX

1.26

280

UNIT

V

REF

Internal reference voltage

Reference supply current

Temperature coefficient

SD16REFON = 1, SD16VMIDON = 0

1.14

1.20

190

18

I

3 V

µA

REF

TC

3 V

50 ppm/K

SD16REFON = 1, SD16VMIDON = 0

(see Note 1)

C

V

REF

load capacitance

100

nF

REF

I

V

maximum load current

SD16REFON = 1; SD16VMIDON = 0

3 V

200

nA

ms

LOAD

REF(I)

SD16REFON = 0 → 1;

SD16VMIDON = 0;

t

Turn on time

5

ON

C

= 100nF

REF

SD16REFON = 1; SD16VMIDON = 0

PSRR

Line regulation

10

uV/V

NOTES: 1. There is no capacitance required on V

voltage noise.

. However, a capacitance of at least 100nF is recommended to reduce any reference

REF

SD16_A, reference output buffer (MSP430x20x3 only)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

1.2

MAX

UNIT

V

Reference buffer output voltage

SD16REFON = 1, SD16VMIDON = 1

3 V

V

REF,BUF

Reference Supply + Reference

output buffer quiescent current

I

SD16REFON = 1, SD16VMIDON = 1

3 V

385

100

600

µA

REF,BUF

Required load capacitance

on V

REF

C

SD16REFON = 1, SD16VMIDON = 1

470

nF

REF(O)

I

Maximum load current on V

REF

3 V

1

mA

mV

LOAD,Max

Maximum voltage variation vs. load current

|I

| = 0 to 1mA

−15

+15

LOAD

SD16REFON = 0 → 1;

SD16VMIDON = 1;

t

Turn on time

3 V

µs

ON

C

= 470nF

REF

SD16_A, external reference input (MSP430x20x3 only)

PARAMETER

Input voltage range

Input current

TEST CONDITIONS

VCC

3 V

MIN

1.0

TYP

1.25

MAX

1.5

UNIT

V

SD16REFON = 0

REF(I)

I

3 V

50

nA

REF(I)

46

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ꢀ ꢊꢋꢌ ꢍ ꢁꢊ ꢎ ꢏꢐꢑ ꢀ ꢊꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢌꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

Flash Memory

PARAMETER

TEST CONDITIONS

VCC

MIN

2.2

TYP

MAX UNIT

V

CC(PGM/

ERASE)

Program and Erase supply voltage

Flash Timing Generator frequency

3.6

V

f

I

t

257

476

5

kHz

mA

FTG

Supply current from V

during program

during erase

2.2 V/3.6 V

1

PGM

CC

7

mA

ERASE

CPT

CC

Cumulative program time (see Note 1)

Cumulative mass erase time

Program/Erase endurance

Data retention duration

10

ms

20

ms

CMErase

4

10

5

10

cycles

years

t

T = 25°C

J

100

Retention

t

Word or byte program time

30

25

Word

st

Block program time for 1 byte or word

Block, 0

Block program time for each additional byte or word

Block program end-sequence wait time

Mass erase time

18

Block, 1-63

Block, End

Mass Erase

Seg Erase

see Note 2

t

FTG

6

10593

4819

Segment erase time

NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming

methods: individual word/byte write and block write modes.

2. These values are hardwired into the Flash Controller’s state machine (t

FTG

= 1/f ).

FTG

RAM

PARAMETER

TEST CONDITIONS

CPU halted

MIN

TYP

MAX UNIT

V

RAM retention supply voltage (see Note 1)

1.6

V

(RAMh)

NOTE 1: This parameter defines the minimum supply voltage V

happen during this supply voltage condition.

when the data in RAM remains unchanged. No program execution should

CC

47

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ꢀ ꢊ ꢋ ꢌꢍ ꢁꢊ ꢎꢏ ꢐ ꢑ ꢀꢊ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢌ ꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

JTAG and Spy-Bi-Wire Interface

TEST

CONDITIONS

PARAMETER

VCC

MIN

TYP

MAX

UNIT

f

t

Spy-Bi-Wire input frequency

2.2 V / 3 V

0

20

15

MHz

us

SBW

Spy-Bi-Wire low clock pulse length

0.025

SBW,Low

Spy-Bi-Wire enable time

t

(TEST high to acceptance of first clock edge, see

Note 1)

2.2 V/ 3 V

1

us

SBW,En

t

f

Spy-Bi-Wire return to normal operation time

2.2 V/ 3 V

2.2 V

15

0

100

5

us

SBW,Ret

MHz

kΩ

TCK input frequency − 4-wire JTAG (see Note 2)

Internal pull-down resistance on TEST

TCK

3 V

0

10

90

R

2.2 V/ 3 V

25

60

Internal

NOTES: 1. Tools accessing the Spy-Bi-Wire interface need to wait for the maximum t

before appling the first SBWCLK clock edge.

time after pulling the TEST/SBWCLK pin high

SBW,En

2.

f

may be restricted to meet the timing requirements of the module selected.

TCK

JTAG Fuse (see Note 1)

TEST

CONDITIONS

PARAMETER

VCC

MIN

TYP

MAX

UNIT

V

Supply voltage during fuse-blow condition

Voltage level on TEST for fuse-blow

Supply current into TEST during fuse blow

Time to blow fuse

T

A

= 25°C

2.5

6

V

CC(FB)

7

100

1

FB

I

t

mA

ms

FB

NOTES: 1. Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible and JTAG is switched

to bypass mode.

48

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ꢀ ꢊꢋꢌ ꢍ ꢁꢊ ꢎ ꢏꢐꢑ ꢀ ꢊꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢌꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

APPLICATION INFORMATION, MSP430x20x1

Port P1 (P1.0 to P1.3) pin functions, MSP430x20x1

CONTROL BITS / SIGNALS

PIN NAME (P1.X)

X

FUNCTION

P1DIR.x

P1SEL.x

CAPD.x

P1.0/TACLK/ACLK/

CA0

0

P1.0† Input/Output

0/1

0

1

X

0

1

X

0

1

X

0

1

X

0

1

0

1

0

1

0

1

Timer_A2.TACLK/INCLK

ACLK

1

CA0 (see Note 3)

P1.1† Input/Output

Timer_A2.CCI0A

Timer_A2.TA0

CA1 (see Note 3)

P1.2† Input/Output

Timer_A2.CCI1A

Timer_A2.TA1

CA2 (see Note 3)

P1.3† Input/Output

N/A

X

P1.1/TA0/CA1

P1.2/TA1/CA2

P1.3/CAOUT/CA3

1

2

3

0/1

0

1

X

0/1

0

1

X

0/1

0

CAOUT

1

CA3 (see Note 3)

X

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable.

2. X: Don’t care.

3. Setting the CAPD.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying

analog signals. Selecting the CAx input pin to the comparator multiplexer with the P2CAx bits automatically disables the input buffer

for that pin, regardless of the state of the associated CAPD.x bit.

49

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢀ ꢊ ꢋ ꢌꢍ ꢁꢊ ꢎꢏ ꢐ ꢑ ꢀꢊ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢌ ꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P1 (P1.0 to P1.3) pin schematics, MSP430x20x1

Pad Logic

To Comparator_A+

From Comparator_A+

CAPD.x

P1REN.x

DVSS

DVCC

0

1

P1DIR.x

0

1

Direction

0: Input

1: Output

0

1

P1OUT.x

Module X OUT

P1.0/TACLK/ACLK/CA0

P1.1/TA0/CA1

P1.2/TA1/CA2

Bus

Keeper

P1SEL.x

P1IN.x

P1.3/CAOUT/CA3

EN

D

Module X IN

P1IRQ.x

P1IE.x

EN

Q

Set

P1IFG.x

Interrupt

Edge

Select

P1SEL.x

P1IES.x

Control signal “From Comparator_A+”

SIGNAL “FROM COMPARATOR_A+” = 1

PIN NAME

FUNCTION

P2CA4

P2CA0

P2CA3

P2CA2

P2CA1

P1.0/TACLK/ACLK/CA0

P1.1/TA0/CA1

CA0

CA1

CA2

CA3

0

1

0

N/A

0

N/A

0

N/A

1

OR

P1.2/TA1/CA2

1

0

1

0

P1.3/CAOUT/CA3

N/A

0

1

NOTES: 1. N/A: Not available or not applicable.

50

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ꢀ ꢊꢋꢌ ꢍ ꢁꢊ ꢎ ꢏꢐꢑ ꢀ ꢊꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢌꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P1 (P1.4 to P1.7) pin functions, MSP430x20x1

CONTROL BITS / SIGNALS

PIN NAME (P1.X)

X

FUNCTION

P1DIR.x

P1SEL.x

CAPD.x

JTAG Mode

P1.4/SMCLK/CA4/

TCK

4

P1.4† Input/Output

0/1

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

0

1

0

1

0

1

N/A

SMCLK

1

CA4 (see Note 3)

TCK (see Note 4)

P1.5† Input/Output

N/A

X

P1.5/TA0/CA5/

TMS

5

6

7

0/1

0

Timer_A2.TA0

CA5 (see Note 3)

TMS (see Note 4)

P1.6† Input/Output

N/A

1

X

P1.6/TA1/CA6/

TDI

0/1

0

Timer_A2.TA1

CA6 (see Note 3)

TDI (see Note 4)

P1.7† Input/Output

N/A

1

X

P1.7/CAOUT/CA7/

TDO/TDI

0/1

0

CAOUT

1

CA7 (see Note 3)

TDO/TDI (see Notes 4, 5)

X

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable.

2. X: Don’t care.

3. Setting the CAPD.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying

analog signals. Selecting the CAx input pin to the comparator multiplexer with the P2CAx bits automatically disables the input buffer

for that pin, regardless of the state of the associated CAPD.x bit.

4. In JTAG mode the internal pull-up/down resistors are disabled.

5. Function controlled by JTAG

51

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ꢀ ꢊ ꢋ ꢌꢍ ꢁꢊ ꢎꢏ ꢐ ꢑ ꢀꢊ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢌ ꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P1 (P1.4 to P1.6) pin schematics, MSP430x20x1

Pad Logic

To Comparator_A+

From Comparator_A+

CAPD.x

P1REN.x

DVSS

DVCC

0

1

P1DIR.x

0

1

Direction

0: Input

1: Output

0

1

P1OUT.x

Module X OUT

P1.4/SMCLK/CA4/TCK

P1.5/TA0/CA5/TMS

P1.6/TA1/CA6/TDI

Bus

Keeper

P1SEL.x

P1IN.x

EN

D

Module X IN

P1IRQ.x

P1IE.x

EN

Q

Set

P1IFG.x

Interrupt

Edge

Select

P1SEL.x

P1IES.x

To JTAG

From JTAG

Control signal “From Comparator_A+”

SIGNAL “FROM COMPARATOR_A+” = 1

PIN NAME

FUNCTION

P2CA3

P2CA2

P2CA1

P1.4/SMCLK/CA4/TCK

CA4

CA5

CA6

1

0

1

0

1

0

P1.5/TA0/CA5/TMS

P1.6/TA1/CA6/TDI

NOTES: 1. N/A: Not available or not applicable.

52

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ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢅ ꢆ ꢈꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢅ ꢆ ꢇꢉ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅꢆ ꢄ

ꢀ ꢊꢋꢌ ꢍ ꢁꢊ ꢎ ꢏꢐꢑ ꢀ ꢊꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢌꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P1 (P1.7) pin schematics, MSP430x20x1

Pad Logic

To Comparator_A+

From Comparator_A+

CAPD.7

P1REN.7

DVSS

DVCC

0

1

P1DIR.7

0

1

Direction

0: Input

1: Output

P1OUT.7

0

1

Module X OUT

P1.7/CAOUT/CA7/TDO/TDI

Bus

Keeper

P1SEL.7

P1IN.7

EN

D

Module X IN

P1IRQ.7

P1IE.7

EN

Q

Set

P1IFG.7

Interrupt

Edge

Select

P1SEL.7

P1IES.7

To JTAG

From JTAG

From JTAG (TDO)

Control signal “From Comparator_A+”

SIGNAL “FROM COMPARATOR_A+” = 1

PIN NAME

FUNCTION

P2CA3

P2CA2

P2CA1

P1.7/CAOUT/CA7/TDO/TDI

CA7

1

NOTES: 1. N/A: Not available or not applicable.

53

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅꢆꢈ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢅ ꢆꢇ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢅ ꢆ ꢄ

ꢀ ꢊ ꢋ ꢌꢍ ꢁꢊ ꢎꢏ ꢐ ꢑ ꢀꢊ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢌ ꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P2 (P2.6) pin schematics, MSP430x20x1

LFXT1 Oscillator

BCSCTL3.LFXT1Sx = 11

P2.7/XOUT

LFXT1 off

0

1

LFXT1CLK

P2SEL.7

P2REN.6

Pad Logic

DVSS

0

1

DVCC

P2DIR.6

0

1

Direction

0: Input

1: Output

0

1

P2OUT.6

Module X OUT

P2.6/XIN/TA1

Bus

Keeper

P2SEL.6

P2IN.6

EN

D

Module X IN

P2IRQ.6

P2IE.6

EN

Set

Q

P2IFG.6

Interrupt

Edge

Select

P2SEL.6

P2IES.6

Port P2 (P2.6) pin functions, MSP430x20x1

CONTROL BITS / SIGNALS

PIN NAME (P2.X)

X

FUNCTION

P2DIR.x

P2SEL.x

P2.6/XIN/TA1

6

P2.6 Input/Output

XIN† (see Note 3)

Timer_A2.TA1

0/1

0

1

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable.

2. X: Don’t care.

3. XIN is used as digital clock input if the bits LFXT1Sx in register BCSCTL3 are set to 11.

54

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢀ ꢊꢋꢌ ꢍ ꢁꢊ ꢎ ꢏꢐꢑ ꢀ ꢊꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢌꢓ

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P2 (P2.7) pin schematics, MSP430x20x1

LFXT1 Oscillator

BCSCTL3.LFXT1Sx = 11

LFXT1 off

0

1

LFXT1CLK

From P2.6/XIN

P2.6/XIN/TA1

Pad Logic

P2SEL.6

P2REN.7

DVSS

DVCC

0

1

P2DIR.7

0

1

Direction

0: Input

1: Output

0

1

P2OUT.7

Module X OUT

P2.7/XOUT

Bus

Keeper

P2SEL.7

P2IN.7

EN

D

Module X IN

P2IRQ.7

P2IE.7

EN

Set

Q

P2IFG.7

Interrupt

Edge

Select

P2SEL.7

P2IES.7

Port P2 (P2.7) pin functions, MSP430x20x1

CONTROL BITS / SIGNALS

PIN NAME (P2.X)

X

FUNCTION

P2DIR.x

P2SEL.x

P2.7/XOUT

7

P2.7 Input/Output

DVSS

0/1

0

1

XOUT† (see Note 3)

1

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable.

2. X: Don’t care.

3. If the pin P2.7/XOUT is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection

to this pin after reset.

55

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅꢆꢈ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢅ ꢆꢇ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢅ ꢆ ꢄ

ꢀ ꢊ ꢋ ꢌꢍ ꢁꢊ ꢎꢏ ꢐ ꢑ ꢀꢊ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢌ ꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

APPLICATION INFORMATION, MSP430x20x2

Port P1 (P1.0 to P1.2) pin functions, MSP430x20x2

CONTROL BITS / SIGNALS

PIN NAME (P1.X)

X

FUNCTION

P1DIR.x

P1SEL.x

ADC10AE.x

INCHx

N/A

0

P1.0/TACLK/ACLK/A0

0

P1.0† Input/Output

0/1

0

1

X

0

1

X

0

1

X

0

1

0

1

0

1

Timer_A2.TACLK/INCLK

ACLK

1

A0 (see Note 3)

P1.1† Input/Output

Timer_A2.CCI0A

Timer_A2.TA0

X

P1.1/TA0/A1

P1.2/TA1/A2

1

2

0/1

0

N/A

1

A1 (see Note 3)

P1.2† Input/Output

Timer_A2.CCI1A

Timer_A2.TA1

X

0/1

0

N/A

2

1

A2 (see Note 3)

X

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable.

2. X: Don’t care.

3. Setting the ADC10AE.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when

applying analog signals.

56

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢂ

ꢃ

ꢄ

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ꢇ

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ꢀ ꢊꢋꢌ ꢍ ꢁꢊ ꢎ ꢏꢐꢑ ꢀ ꢊꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢌꢓ

ꢂ

ꢃ

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ꢆ

ꢇ

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P1 (P1.0 to P1.2) pin schematics, MSP430x20x2

Pad Logic

To ADC 10

INCHx = x

ADC10AE.x

P1REN.x

DVSS

DVCC

0

1

P1DIR.x

0

1

Direction

0: Input

1: Output

0

1

P1OUT.x

Module X OUT

P1.0/TACLK/ACLK/A0

P1.1/TA0/A1

P1.2/TA1/A2

Bus

Keeper

P1SEL.x

P1IN.x

EN

D

Module X IN

P1IRQ.x

P1IE.x

EN

Q

Set

P1IFG.x

Interrupt

Edge

Select

P1SEL.x

P1IES.x

57

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅꢆꢈ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢅ ꢆꢇ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢅ ꢆ ꢄ

ꢀ ꢊ ꢋ ꢌꢍ ꢁꢊ ꢎꢏ ꢐ ꢑ ꢀꢊ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢌ ꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P1 (P1.3) pin schematics, MSP430x20x2

SREF2

VSS

Pad Logic

0

1

To ADC 10 V

R−

A3

INCHx = 3

ADC10AE.3

P1REN.3

P1DIR.3

DVSS

DVCC

0

1

0

1

Direction

0: Input

1: Output

0

1

P1OUT.3

Module X OUT

P1.3/ADC10CLK/

A3/VREF−/VeREF−

Bus

Keeper

P1SEL.3

P1IN.3

EN

D

Module X IN

P1IRQ.3

P1IE.3

EN

Q

Set

P1IFG.3

Interrupt

Edge

Select

P1SEL.3

P1IES.3

Port P1 (P1.0 to P1.3) pin functions, MSP430x20x2

CONTROL BITS / SIGNALS

PIN NAME (P1.X)

X

FUNCTION

P1DIR.x

P1SEL.x

ADC10AE.x

INCHx

N/A

3

P1.3/ADC10CLK/

A3/VREF−/VeREF−

3

P1.3† Input/Output

0/1

0

1

0

1

N/A

ADC10CLK

1

A3 (see Note 3)

X

VREF−/VeREF− (see Notes 3, 4)

X

N/A

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable.

2. X: Don’t care.

3. Setting the ADC10AE.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when

applying analog signals.

4. An applied voltage is used as negative reference if bit SREF3 in register ADC10CTL0 is set.

58

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢅ ꢆ ꢈꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢅ ꢆ ꢇꢉ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅꢆ ꢄ

ꢀ ꢊꢋꢌ ꢍ ꢁꢊ ꢎ ꢏꢐꢑ ꢀ ꢊꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢌꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P1 (P1.4 to P1.7) pin functions, MSP430x20x2

CONTROL BITS / SIGNALS

PIN NAME (P1.X)

X

FUNCTION

JTAG

Mode

P1DIR.x

P1SEL.x

USIP.x

ADC10AE.x

INCHx

P1.4/SMCLK/A4/

VREF+/VeREF+/

TCK

4

P1.4† Input/Output

N/A

0/1

0

1

X

0

1

N/A

4

0

SMCLK

1

A4 (see Note 3)

X

N/A

VREF+/VeREF+

(see Notes 3, 4)

X

1

N/A

0

TCK (see Note 5)

P1.5† Input/Output

N/A

X

0/1

0

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

1

0

1

0

1

0

P1.5/TA0/SCLK/A5/

TMS

5

6

7

X

1

N/A

5

Timer_A2.TA0

SCLK

1

X

A5 (see Note 3)

TMS (see Note 5)

P1.6† Input/Output

Timer_A2.CCI1B

Timer_A2.TA1

SDO (SPI) / SCL (I2C)

A6 (see Note 3)

TDI (see Note 5)

P1.7† Input/Output

N/A

X

1

X

P1.6/TA1/SDO/SCL/A6/

TDI

0/1

0

N/A

6

1

X

1

X

P1.7/SDI/SDA/A7/

TDO/TDI

0/1

0

N/A

7

DVSS

1

SDI (SPI) / SDA (I2C)

A7 (see Note 3)

X

TDO/TDI (see Notes 5,

6)

X

1

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable.

2. X: Don’t care.

3. Setting the ADC10AE.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when

applying analog signals.

4. The reference voltage is output if bit REFOUT in register ADC10CTL0 is set. An applied voltage is used as positive reference if

bits SREF0/1 in register ADC10CTL0 are set to 10 or 11.

5. In JTAG mode the internal pull-up/down resistors are disabled.

6. Function controlled by JTAG

59

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅꢆꢈ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢅ ꢆꢇ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢅ ꢆ ꢄ

ꢀ ꢊ ꢋ ꢌꢍ ꢁꢊ ꢎꢏ ꢐ ꢑ ꢀꢊ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢌ ꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P1 (P1.4) pin schematics, MSP430x20x2

Pad Logic

To/from ADC10

positive reference

A4

INCHx = 4

ADC10AE.4

P1REN.4

DVSS

DVCC

0

1

P1DIR.4

0

1

Direction

0: Input

1: Output

0

1

P1OUT.4

Module X OUT

P1.4/SMCLK/A4/VREF+/VeREF+/TCK

Bus

Keeper

P1SEL.4

EN

D

Module X IN

P1IRQ.4

P1IE.4

EN

Q

Set

P1IFG.4

Interrupt

Edge

Select

P1SEL.4

P1IES.4

To JTAG

From JTAG

60

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢅ ꢆ ꢈꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢅ ꢆ ꢇꢉ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅꢆ ꢄ

ꢀ ꢊꢋꢌ ꢍ ꢁꢊ ꢎ ꢏꢐꢑ ꢀ ꢊꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢌꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P1 (P1.5) pin schematics, MSP430x20x2

Pad Logic

A5

INCHx = 5

ADC10AE.5

P1REN.5

P1SEL.5

USIPE5

DVSS

DVCC

0

1

P1DIR.5

0

1

Direction

0: Input

1: Output

USI Module Direction

P1OUT.5

0

1

Module X OUT

P1.5/TA0/SCLK/A5/TMS

Bus

Keeper

EN

P1IN.5

EN

D

Module X IN

P1IE.5

EN

Q

P1IRQ.5

Set

P1IFG.5

Interrupt

Edge

Select

P1SEL.5

P1IES.5

To JTAG

From JTAG

61

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅꢆꢈ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢅ ꢆꢇ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢅ ꢆ ꢄ

ꢀ ꢊ ꢋ ꢌꢍ ꢁꢊ ꢎꢏ ꢐ ꢑ ꢀꢊ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢌ ꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P1 (P1.6) pin schematics, MSP430x20x2

Pad Logic

A6

INCHx = 6

ADC10AE.6

P1REN.6

P1SEL.6

USIPE6

DVSS

DVCC

0

1

P1DIR.6

0

1

Direction

0: Input

1: Output

USI Module Direction

0

1

P1OUT.6

Module X OUT

P1.6/TA1/SDO/SCL/A6/TDI

USI Module Output

2

(I C Mode)

Bus

Keeper

EN

P1IN.6

EN

D

Module X IN

P1IE.6

EN

Q

P1IRQ.6

Set

P1IFG.6

Interrupt

Edge

Select

P1SEL.6

P1IES.6

To JTAG

From JTAG

62

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢅ ꢆ ꢈꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢅ ꢆ ꢇꢉ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅꢆ ꢄ

ꢀ ꢊꢋꢌ ꢍ ꢁꢊ ꢎ ꢏꢐꢑ ꢀ ꢊꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢌꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P1 (P1.7) pin schematics, MSP430x20x2

Pad Logic

A7

INCHx = 7

ADC10AE.7

P1REN.7

P1SEL.7

USIPE7

DVSS

DVCC

0

1

P1DIR.7

0

1

Direction

0: Input

1: Output

USI Module Direction

P1OUT.7

0

1

Module X OUT

P1.7/SDI/SDA/A7/TDO/TDI

USI Module Output

2

(I C Mode)

Bus

Keeper

EN

P1IN.7

EN

D

Module X IN

P1IE.7

EN

Q

P1IRQ.7

Set

P1IFG.7

Interrupt

Edge

Select

P1SEL.7

P1IES.7

To JTAG

From JTAG

From JTAG (TDO)

63

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅꢆꢈ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢅ ꢆꢇ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢅ ꢆ ꢄ

ꢀ ꢊ ꢋ ꢌꢍ ꢁꢊ ꢎꢏ ꢐ ꢑ ꢀꢊ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢌ ꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P2 (P2.6) pin schematics, MSP430x20x2

LFXT1 Oscillator

BCSCTL3.LFXT1Sx = 11

P2.7/XOUT

LFXT1 off

0

1

LFXT1CLK

P2SEL.7

P2REN.6

Pad Logic

DVSS

0

1

DVCC

P2DIR.6

0

1

Direction

0: Input

1: Output

0

1

P2OUT.6

Module X OUT

P2.6/XIN/TA1

Bus

Keeper

P2SEL.6

P2IN.6

EN

D

Module X IN

P2IRQ.6

P2IE.6

EN

Set

Q

P2IFG.6

Interrupt

Edge

Select

P2SEL.6

P2IES.6

Port P2 (P2.6) pin functions, MSP430x20x2

CONTROL BITS / SIGNALS

PIN NAME (P2.X)

X

FUNCTION

P2DIR.x

P2SEL.x

P2.6/XIN/TA1

6

P2.6 Input/Output

XIN† (see Note 3)

Timer_A2.TA1

0/1

0

1

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable.

2. X: Don’t care.

3. XIN is used as digital clock input if the bits LFXT1Sx in register BCSCTL3 are set to 11.

64

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢃ

ꢄ

ꢅ

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ꢇ

ꢅ

ꢆ

ꢇ

ꢉ

ꢀ

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ꢀ ꢊꢋꢌ ꢍ ꢁꢊ ꢎ ꢏꢐꢑ ꢀ ꢊꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢌꢓ

ꢂ

ꢃ

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P2 (P2.7) pin schematics, MSP430x20x2

LFXT1 Oscillator

BCSCTL3.LFXT1Sx = 11

LFXT1 off

0

1

LFXT1CLK

From P2.6/XIN

P2.6/XIN/TA1

Pad Logic

P2SEL.6

P2REN.7

DVSS

DVCC

0

1

P2DIR.7

0

1

Direction

0: Input

1: Output

0

1

P2OUT.7

Module X OUT

P2.7/XOUT

Bus

Keeper

P2SEL.7

P2IN.7

EN

D

Module X IN

P2IRQ.7

P2IE.7

EN

Set

Q

P2IFG.7

Interrupt

Edge

Select

P2SEL.7

P2IES.7

Port P2 (P2.7) pin functions, MSP430x20x2

CONTROL BITS / SIGNALS

PIN NAME (P2.X)

X

FUNCTION

P2DIR.x

P2SEL.x

P2.7/XOUT

7

P2.7 Input/Output

DVSS

0/1

0

1

XOUT† (see Note 3)

1

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable.

2. X: Don’t care.

3. If the pin P2.7/XOUT is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection

to this pin after reset.

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ꢀ ꢊ ꢋ ꢌꢍ ꢁꢊ ꢎꢏ ꢐ ꢑ ꢀꢊ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢌ ꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

APPLICATION INFORMATION, MSP430x20x3

Port P1 (P1.0 to P1.3) pin functions, MSP430x20x3

CONTROL BITS / SIGNALS

PIN NAME (P1.X)

X

FUNCTION

P1DIR.x

P1SEL.x

SD16AE.x

INCHx

N/A

0

P1.0/TACLK/ACLK/A0+

0

P1.0† Input/Output

0/1

0

1

X

0

1

X

0

1

X

0

1

X

0

1

0

1

0

1

0

1

Timer_A2.TACLK/INCLK

ACLK

1

A0+ (see Note 3)

P1.1† Input/Output

Timer_A2.CCI0A

Timer_A2.TA0

X

P1.1/TA0/A0−/A4+

P1.2/TA1/A1+/A4−

P1.3/VREF/A1−

1

2

3

0/1

0

N/A

0

1

A0− (see Notes 3, 4)

A4+ (see Note 3)

P1.2† Input/Output

Timer_A2.CCI1A

Timer_A2.TA1

X

4

0/1

0

N/A

1

A1+ (see Note 3)

A4− (see Notes 3, 4)

P1.3† Input/Output

VREF

X

4

0/1

X

N/A

1

A1− (see Notes 3, 4)

X

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable.

2. X: Don’t care.

3. Setting the SD16AE.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when

applying analog signals.

4. With SD16AE.x = 0 the negative inputs are connected to VSS if the corresponding input is selected.

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ꢀ ꢊꢋꢌ ꢍ ꢁꢊ ꢎ ꢏꢐꢑ ꢀ ꢊꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢌꢓ

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P1 (P1.0) pin schematics, MSP430x20x3

INCH=0

Pad Logic

A0+

SD16AE.0

P1REN.0

DVSS

DVCC

0

1

P1DIR.0

0

1

Direction

0: Input

1: Output

0

1

P1OUT.0

Module X OUT

P1.0/TACLK/ACLK/A0+

Bus

Keeper

P1SEL.0

P1IN.0

EN

D

Module X IN

P1IRQ.0

P1IE.0

EN

Q

Set

P1IFG.0

Interrupt

Edge

Select

P1SEL.0

P1IES.0

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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅꢆꢈ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢅ ꢆꢇ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢅ ꢆ ꢄ

ꢀ ꢊ ꢋ ꢌꢍ ꢁꢊ ꢎꢏ ꢐ ꢑ ꢀꢊ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢌ ꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P1 (P1.1) pin schematics, MSP430x20x3

=4

INCH

A4+

=0

Pad Logic

INCH

0

1

AV

SS

A0−

SD16AE.1

P1REN.1

P1DIR.1

DVSS

DVCC

0

1

0

1

Direction

0: Input

1: Output

0

1

P1OUT.1

Module X OUT

+

P1.1/TA0/A0−/A4

Bus

Keeper

P1SEL.1

P1IN.1

EN

D

Module X IN

P1IRQ.1

P1IE.1

EN

Q

Set

P1IFG.1

Interrupt

Edge

Select

P1SEL.1

P1IES.1

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P1 (P1.2) pin schematics, MSP430x20x3

=1

INCH

A1+

=4

Pad Logic

INCH

0

1

AV

SS

A4−

SD16AE.2

P1REN.2

P1DIR.2

DVSS

DVCC

0

1

0

1

Direction

0: Input

1: Output

0

1

P1OUT.2

Module X OUT

P1.2/TA1/A1+/A4−

Bus

Keeper

P1SEL.2

P1IN.2

EN

D

Module X IN

P1IRQ.2

P1IE.2

EN

Q

Set

P1IFG.2

Interrupt

Edge

Select

P1SEL.2

P1IES.2

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ꢀ ꢊ ꢋ ꢌꢍ ꢁꢊ ꢎꢏ ꢐ ꢑ ꢀꢊ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢌ ꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P1 (P1.3) pin schematics, MSP430x20x3

Pad Logic

V

REF

=1

INCH

0

1

AV

SS

A1−

SD16AE.3

P1REN.3

DVSS

DVCC

0

1

P1DIR.3

0

1

Direction

0: Input

1: Output

0

1

P1OUT.3

P1.3/VREF/A1−

Bus

Keeper

P1SEL.3

P1IN.3

EN

P1IE.3

EN

Q

P1IRQ.3

Set

P1IFG.3

Interrupt

Edge

Select

P1SEL.3

P1IES.3

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ꢀ ꢊꢋꢌ ꢍ ꢁꢊ ꢎ ꢏꢐꢑ ꢀ ꢊꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢌꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P1 (P1.4 to P1.7) pin functions, MSP430x20x3

CONTROL BITS / SIGNALS

PIN NAME (P1.X)

X

FUNCTION

JTAG

Mode

P1DIR.x

P1SEL.x

USIP.x

SD16AE.x

INCHx

P1.4/SMCLK/A2+/

TCK

4

P1.4† Input/Output

N/A

0/1

0

1

X

0

1

X

0

1

X

0

1

X

N/A

X

0

1

X

0

1

X

0

1

X

0

1

X

N/A

2

0

1

0

1

0

1

0

1

SMCLK

1

A2+ (see Note 3)

TCK (see Note 5)

P1.5† Input/Output

N/A

X

P1.5/TA0/SCLK/A2−/

TMS

5

6

7

0/1

0

N/A

2

X

Timer_A2.TA0

SCLK

1

X

1

A2− (see Notes 3, 4)

TMS (see Note 5)

P1.6† Input/Output

Timer_A2.CCI1B

Timer_A2.TA1

SDO (SPI) / SCL (I2C)

A3+ (see Note 3)

TDI (see Note 5)

P1.7† Input/Output

N/A

X

P1.6/TA1/SDO/SCL/A3+/

TDI

0/1

0

X

N/A

3

X

1

X

1

X

P1.7/SDI/SDA/A3−/

TDO/TDI

0/1

0

X

N/A

3

X

DVSS

1

X

SDI (SPI) / SDA (I2C)

A3− (see Notes 3, 4)

TDO/TDI (see Notes 5, 6)

X

1

X

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable.

2. X: Don’t care.

3. Setting the SD16AE.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when

applying analog signals.

4. With SD16AE.x = 0 the negative inputs are connected to VSS if the corresponding input is selected.

5. In JTAG mode the internal pull-up/down resistors are disabled.

6. Function controlled by JTAG

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ꢀ ꢊ ꢋ ꢌꢍ ꢁꢊ ꢎꢏ ꢐ ꢑ ꢀꢊ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢌ ꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P1 (P1.4) pin schematics, MSP430x20x3

INCH=2

A2+

Pad Logic

SD16AE.4

P1REN.4

DVSS

DVCC

0

1

P1DIR.4

0

1

Direction

0: Input

1: Output

0

1

P1OUT.4

Module X OUT

P1.4/SMCLK/A2+/TCK

Bus

Keeper

P1SEL.4

P1IN.4

EN

D

Module X IN

P1IRQ.4

P1IE.4

EN

Q

Set

P1IFG.4

Interrupt

Edge

Select

P1SEL.4

P1IES.4

To JTAG

From JTAG

72

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ꢀ ꢊꢋꢌ ꢍ ꢁꢊ ꢎ ꢏꢐꢑ ꢀ ꢊꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢌꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P1 (P1.5) pin schematics, MSP430x20x3

Pad Logic

=2

INCH

0

1

AV

SS

A2−

SD16AE.5

P1REN.5

P1SEL.5

USIPE5

DVSS

DVCC

0

1

P1DIR.5

0

1

Direction

0: Input

1: Output

USI Module Direction

0

1

P1OUT.5

Module X OUT

P1.5/TA0/SCLK/A2−/TMS

Bus

Keeper

EN

P1IN.5

EN

D

Module X IN

P1IE.5

EN

Q

P1IRQ.5

Set

P1IFG.5

Interrupt

Edge

Select

P1SEL.5

P1IES.5

To JTAG

From JTAG

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ꢀ ꢊ ꢋ ꢌꢍ ꢁꢊ ꢎꢏ ꢐ ꢑ ꢀꢊ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢌ ꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P1 (P1.6) pin schematics, MSP430x20x3

Pad Logic

INCH=3

A3+

SD16AE.6

P1REN.6

P1SEL.6

USIPE6

DVSS

DVCC

0

1

P1DIR.6

0

1

Direction

0: Input

1: Output

USI Module Direction

0

1

P1OUT.6

Module X OUT

P1.6/TA1/SDO/SCL/A3+/TDI

USI Module Output

2

(I

)

C Mode

Bus

Keeper

EN

P1IN.6

EN

D

Module X IN

P1IRQ.6

P1IE.6

EN

Q

Set

P1IFG.6

Interrupt

Edge

Select

P1SEL.6

P1IES.6

To JTAG

From JTAG

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ꢀ ꢊꢋꢌ ꢍ ꢁꢊ ꢎ ꢏꢐꢑ ꢀ ꢊꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢌꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P1 (P1.7) pin schematics, MSP430x20x3

Pad Logic

INCH=3

0

1

AV

SS

A3−

SD16AE.x

P1REN.x

P1SEL.x

USIPE7

DVSS

DVCC

0

1

P1DIR.x

0

1

Direction

0: Input

1: Output

USI Module Direction

0

1

P1OUT.x

Module X OUT

P1.7/SDI/SDA/A3−/TDO/TDI

USI Module Output

2

(I

)

C Mode

Bus

Keeper

EN

P1IN.x

EN

D

Module X IN

P1IRQ.x

P1IE.x

EN

Q

Set

P1IFG.x

Interrupt

Edge

Select

P1SEL.x

P1IES.x

To JTAG

From JTAG

From JTAG (TDO)

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ꢀ ꢊ ꢋ ꢌꢍ ꢁꢊ ꢎꢏ ꢐ ꢑ ꢀꢊ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢌ ꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P2 (P2.6) pin schematics, MSP430x20x3

LFXT1 Oscillator

BCSCTL3.LFXT1Sx = 11

P2.7/XOUT

LFXT1 off

0

1

LFXT1CLK

P2SEL.7

P2REN.6

Pad Logic

DVSS

0

1

DVCC

P2DIR.6

0

1

Direction

0: Input

1: Output

0

1

P2OUT.6

Module X OUT

P2.6/XIN/TA1

Bus

Keeper

P2SEL.6

P2IN.6

EN

D

Module X IN

P2IRQ.6

P2IE.6

EN

Set

Q

P2IFG.6

Interrupt

Edge

Select

P2SEL.6

P2IES.6

Port P2 (P2.6) pin functions, MSP430x20x3

CONTROL BITS / SIGNALS

PIN NAME (P2.X)

X

FUNCTION

P2DIR.x

P2SEL.x

P2.6/XIN/TA1

6

P2.6 Input/Output

XIN† (see Note 3)

Timer_A2.TA1

0/1

0

1

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable.

2. X: Don’t care.

3. XIN is used as digital clock input if the bits LFXT1Sx in register BCSCTL3 are set to 11.

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Port P2 (P2.7) pin schematics, MSP430x20x3

LFXT1 Oscillator

BCSCTL3.LFXT1Sx = 11

LFXT1 off

0

1

LFXT1CLK

From P2.6/XIN

P2.6/XIN/TA1

Pad Logic

P2SEL.6

P2REN.7

DVSS

DVCC

0

1

P2DIR.7

0

1

Direction

0: Input

1: Output

0

1

P2OUT.7

Module X OUT

P2.7/XOUT

Bus

Keeper

P2SEL.7

P2IN.7

EN

D

Module X IN

P2IRQ.7

P2IE.7

EN

Set

Q

P2IFG.7

Interrupt

Edge

Select

P2SEL.7

P2IES.7

Port P2 (P2.7) pin functions, MSP430x20x3

CONTROL BITS / SIGNALS

PIN NAME (P2.X)

X

FUNCTION

P2DIR.x

P2SEL.x

P2.7/XOUT

7

P2.7 Input/Output

DVSS

0/1

0

1

XOUT† (see Note 3)

1

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable.

2. X: Don’t care.

3. If the pin P2.7/XOUT is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection

to this pin after reset.

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ꢀ ꢊ ꢋ ꢌꢍ ꢁꢊ ꢎꢏ ꢐ ꢑ ꢀꢊ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢌ ꢓ

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

Data Sheet Revision History

Literature

Number

Summary

SLAS491

Preliminary PRODUCT PREVIEW datasheet release.

MSP430x20x3 production datasheet release.

Updated specification and added characterization graphs.

NOTE: The referring page and figure numbers are referred to the respective document revision.

SLAS491A

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MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

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IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

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型号：	MSP430F2013-EP_16
厂家：	TEXAS INSTRUMENTS
描述：	MIXED SIGNAL MICROCONTROLLER
文件：	总80页 (文件大小：1650K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MSP430F2013-EP_16 [TI]

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