MSP430F2101IPW_技术文档

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SLAS439 − SEPTEMBER 2004

D

Low Supply Voltage Range 1.8 V to 3.6 V

D

Serial Onboard Programming,

No External Programming Voltage Needed

Programmable Code Protection by

Security Fuse

Ultralow-Power Consumption

− Active Mode: 200 µA at 1 MHz, 2.2 V

− Standby Mode: 0.7 µA

− Off Mode (RAM Retention): 0.1 µA

Ultrafast Wake-Up From Standby Mode in

less than 1 µs

16-Bit RISC Architecture, 65 ns

Instruction Cycle Time

D

Bootstrap Loader in Flash Devices

D

Family Members Include:

MSP430F2101: 1KB + 256B Flash Memory

128B RAM

MSP430F2111: 2KB + 256B Flash Memory

128B RAM

MSP430F2121: 4KB + 256B Flash Memory

256B RAM

Basic Clock Module Configurations:

− Internal Frequencies up to 16MHz

− 32-kHz Crystal

− High-Frequency Crystal up to 16MHz

− Resonator

MSP430F2131: 8KB + 256B Flash Memory

256B RAM

D

Available in a 20-Pin Plastic Small-Outline

Wide Body (SOWB) Package, 20-Pin Plastic

Small-Outline Thin (TSSOP) Package,

20-Pin TVSOP and 24-Pin QFN

For Complete Module Descriptions, Refer

to the MSP430x2xx Family User’s Guide

− External Clock Source

D

16-Bit Timer_A With Three

Capture/Compare Registers

On-Chip Comparator for Analog Signal

Compare Function or Slope A/D

Conversion

description

The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low power

modes is optimized to achieve extended battery life in portable measurement applications. The device features

a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.

The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1µs.

The MSP430x21x1 series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer, versatile

analog comparator and sixteen I/O pins.

Typical applications include sensor systems that capture analog signals, convert them to digital values, and then

process the data for display or for transmission to a host system. Stand alone RF sensor front end is another

area of application. The analog comparator provides slope A/D conversion capability.

AVAILABLE OPTIONS

PACKAGED DEVICES

PLASTIC

20-PIN SOWB

(DW)

PLASTIC

20-PIN TSSOP

(PW)

PLASTIC

20-PIN TVSOP

(DGV)

PLASTIC

24-PIN QFN

(RGE)

T

A

MSP430F2101IDW

MSP430F2111IDW

MSP430F2121IDW

MSP430F2131IDW

MSP430F2101IPW

MSP430F2111IPW

MSP430F2121IPW

MSP430F2131IPW

MSP430F2101IDGV

MSP430F2111IDGV

MSP430F2121IDGV

MSP430F2131IDGV

MSP430F2101IRGE

MSP430F2111IRGE

MSP430F2121IRGE

MSP430F2131IRGE

−40°C to 85°C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2004 Texas Instruments Incorporated

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1

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SLAS439 − SEPTEMBER 2004

device pinout

RGE PACKAGE

(TOP VIEW)

DW, PW, or DGV PACKAGE

(TOP VIEW)

TEST

P1.7/TA2/TDO/TDI

P1.6/TA1/TDI/TCLK

P1.5/TA0/TMS

P1.4/SMCLK/TCK

P1.3/TA2

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

V

CC

P2.5/CA5

V

SS

XOUT/P2.7/CA7

XIN/P2.6/CA6

P1.2/TA1

RST/NMI

P1.1/TA0

24 23 22 21 20 19

NC

P1.5/TA0/TMS

P1.4/SMCLK/TCK

P1.3/TA2

1

2

3

4

5

6

18

17

16

15

14

13

P2.0/ACLK/CA2

P2.1/INCLK/CA3

P2.2/CAOUT/TA0/CA4

P1.0/TACLK

V

SS

P2.4/TA2/CA1

P2.3/TA1/CA0

XOUT/P2.7/CA7

XIN/P2.6/CA6

RST/NMI

P1.2/TA1

P1.1/TA0

P2.0/ACLK/CA2

P1.0/TACLK

7 8 9 10 11 12

Note: NC pins not internally connected

Power Pad connection to V recommended

SS

functional block diagram

P1.x &

JTAG

P2.x &

XIN/XOUT

V

RST/NMI

CC

SS

XIN

XOUT

ACLK

Basic

Clock

8kB Flash

4kB Flash

2KB Flash

1KB Flash

256B RAM

128B RAM

I/O Port P1

8 I/Os with

Interrupt

I/O Port P2

8 I/Os with

Interrupt

SMCLK

Brownout

Protection

Capability

MCLK

CPU &

Working

Registers

Emulation

Comparator_

A+

Watchdog

WDT+

Timer_A3

3 CC

Registers

8 Channel

Input Mux

15/16−Bit

Note: See port schematics section for detailed I/O information

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SLAS439 − SEPTEMBER 2004

Terminal Functions

TERMINAL

DW, PW, or DGV

RGE

NO.

13

DESCRIPTION

NAME

I/O

NO.

13

P1.0/TACLK

P1.1/TA0

I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input

14

I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input,

compare: Out0 output/BSL transmit

P1.2/TA1

15

16

17

18

19

20

8

15

16

17

18

20

21

6

I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input,

compare: Out1 output

P1.3/TA2

I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input,

compare: Out2 output

P1.4/SMCLK/TCK

P1.5/TA0/TMS

P1.6/TA1/TDI/TCLK

I/O General-purpose digital I/O pin/SMCLK signal output/test clock, input

terminal for device programming and test

I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output/test

mode select, input terminal for device programming and test

I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/test

data input or test clock input during programming and test

†

P1.7/TA2/TDO/TDI

P2.0/ACLK/CA2

P2.1/INCLK/CA3

I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/test

data output terminal or test data input during programming and test

I/O General-purpose digital I/O pin/ACLK output/comparator_A+, CA2

input

9

7

I/O General-purpose digital I/O pin/Timer_A, clock signal at

INCLK/comparator_A+, CA3 input

P2.2/CAOUT/

TA0/CA4

10

11

12

8

I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input/

comparator_A+, output/comparator_A+, CA4 input/BSL receive

P2.3/CA0/TA1

10

11

I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/

comparator_A+, CA0 input

P2.4/CA1/TA2

I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/

comparator_A+, CA1 input

P2.5/CA5

3

6

24

4

I/O General-purpose digital I/O pin/ comparator_A+, CA5 input

XIN/P2.6/CA6

I/O Input terminal of crystal oscillator/general-purpose digital I/O pin/

comparator_A+, CA6 input

XOUT/P2.7/CA7

5

3

I/O Output terminal of crystal oscillator/general-purpose digital I/O pin/

comparator_A+, CA7 input

RST/NMI

TEST

7

1

5

I

Reset or nonmaskable interrupt input

22

Selects test mode for JTAG pins on Port1. The device protection fuse

is connected to TEST.

V

2

4

23

Supply voltage

CC

2

Ground reference

SS

QFN Pad

NA

Package Pad

NA QFN package pad connection to V recommended.

SS

†

TDO or TDI is selected via JTAG instruction.

NOTE: If XOUT/P2.7/CA7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output

driver connection to this pad after reset.

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SLAS439 − SEPTEMBER 2004

short-form description

CPU

Program Counter

Stack Pointer

PC/R0

The MSP430 CPU has a 16-bit RISC architecture

that is highly transparent to the application. All

operations, other than program-flow instructions,

are performed as register operations in

conjunction with seven addressing modes for

source operand and four addressing modes for

destination operand.

SP/R1

Status Register

SR/CG1/R2

Constant Generator

CG2/R3

R4

General-Purpose Register

The CPU is integrated with 16 registers that

provide reduced instruction execution time. The

register-to-register operation execution time is

one cycle of the CPU clock.

R5

R6

R7

Four of the registers, R0 to R3, are dedicated as

program counter, stack pointer, status register,

and constant generator respectively. The

remaining registers are general-purpose

registers.

R8

R9

Peripherals are connected to the CPU using data,

address, and control buses, and can be handled

with all instructions.

R10

R11

instruction set

R12

R13

The instruction set consists of 51 instructions with

three formats and seven address modes. Each

instruction can operate on word and byte data.

Table 1 shows examples of the three types of

instruction formats; the address modes are listed

in Table 2.

R14

R15

Table 1. Instruction Word Formats

Dual operands, source-destination

Single operands, destination only

Relative jump, un/conditional

e.g. ADD R4,R5

R4 + R5 −−−> R5

e.g. CALL

e.g. JNE

R8

PC −−>(TOS), R8−−> PC

Jump-on-equal bit = 0

Table 2. Address Mode Descriptions

ADDRESS MODE

Register

S

D

SYNTAX

EXAMPLE

MOV R10,R11

MOV 2(R5),6(R6)

OPERATION

F

MOV Rs,Rd

R10 −−> R11

Indexed

MOV X(Rn),Y(Rm)

MOV EDE,TONI

MOV &MEM,&TCDAT

MOV @Rn,Y(Rm)

M(2+R5)−−> M(6+R6)

M(EDE) −−> M(TONI)

M(MEM) −−> M(TCDAT)

M(R10) −−> M(Tab+R6)

Symbolic (PC relative)

Absolute

Indirect

MOV @R10,Tab(R6)

MOV @R10+,R11

MOV #45,TONI

Indirect

autoincrement

M(R10) −−> R11

R10 + 2−−> R10

F

MOV @Rn+,Rm

Immediate

MOV #X,TONI

#45 −−> M(TONI)

NOTE: S = source

D = destination

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SLAS439 − SEPTEMBER 2004

operating modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt

event can wake up the device from any of the five low-power modes, service the request and restore back to

the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

D

Active mode AM;

All clocks are active

Low-power mode 0 (LPM0);

−

CPU is disabled

ACLK and SMCLK remain active. MCLK is disabled

D

Low-power mode 1 (LPM1);

−

CPU is disabled

ACLK and SMCLK remain active. MCLK is disabled

DCO’s dc-generator is disabled if DCO not used in active mode

Low-power mode 2 (LPM2);

−

CPU is disabled

MCLK and SMCLK are disabled

DCO’s dc-generator remains enabled

ACLK remains active

D

Low-power mode 3 (LPM3);

−

CPU is disabled

MCLK and SMCLK are disabled

DCO’s dc-generator is disabled

ACLK remains active

Low-power mode 4 (LPM4);

−

CPU is disabled

ACLK is disabled

MCLK and SMCLK are disabled

DCO’s dc-generator is disabled

Crystal oscillator is stopped

5

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SLAS439 − SEPTEMBER 2004

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh−0FFE0h.

The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g. flash is not programmed) the CPU will

go into LPM4 immediately.

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM INTERRUPT

WORD ADDRESS

PRIORITY

Power-up

External reset

Watchdog

PORIFG

RSTIFG

WDTIFG

KEYV

Reset

0FFFEh

15, highest

Flash key violation

PC out-of-range (see Note 1)

(see Note 2)

NMIIFG

OFIFG

ACCVIFG

NMI

Oscillator fault

Flash memory access violation

(non)-maskable,

(non)-maskable

0FFFCh

14

(see Notes 2 & 4)

0FFFAh

0FFF8h

0FFF6h

0FFF4h

0FFF2h

13

12

11

10

9

Comparator_A+

Watchdog Timer

Timer_A3

CAIFG

WDTIFG

maskable

TACCR0 CCIFG (see Note 3)

TACCR1 CCIFG.

TACCR2 CCIFG

Timer_A3

maskable

0FFF0h

8

TAIFG (see Notes 2 & 3)

0FFEEh

0FFECh

0FFEAh

0FFE8h

7

6

5

4

I/O Port P2

(eight flags)

P2IFG.0 to P2IFG.7

(see Notes 2 & 3)

maskable

0FFE6h

0FFE4h

3

2

I/O Port P1

(eight flags)

P1IFG.0 to P1IFG.7

(see Notes 2 & 3)

0FFE2h

0FFE0h

1

0, lowest

NOTES: 1. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h−01FFh).

2. Multiple source flags

3. Interrupt flags are located in the module

4. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.

Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.

6

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SLAS439 − SEPTEMBER 2004

special function registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits

not allocated to a functional purpose are not physically present in the device. Simple software access is provided

with this arrangement.

interrupt enable 1 and 2

7

6

5

4

3

2

1

0

Address

0h

OFIE

WDTIE

ACCVIE

NMIIE

rw-0

WDTIE:

Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer

is configured in interval timer mode.

OFIE:

Oscillator fault enable

NMIIE:

ACCVIE:

(Non)maskable interrupt enable

Flash access violation interrupt enable

7

6

5

4

3

2

1

0

Address

01h

interrupt flag register 1 and 2

7

6

5

4

3

2

1

0

Address

02h

NMIIFG

RSTIFG

PORIFG

OFIFG

WDTIFG

rw-0

rw-(0)

rw-1

rw-(0)

rw-(1)

WDTIFG:

Set on Watchdog Timer overflow (in watchdog mode) or security key violation.

Reset on V power-up or a reset condition at RST/NMI pin in reset mode.

Flag set on oscillator fault

CC

OFIFG:

RSTIFG:

External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on V

power−up

CC

PORIFG:

NMIIFG:

Power−On interrupt flag. Set on V

Set via RST/NMI-pin

power−up.

CC

7

6

5

4

3

2

1

0

Address

03h

Legend

rw:

Bit can be read and written.

rw-0,1:

rw-(0,1):

Bit can be read and written. It is Reset or Set by PUC.

Bit can be read and written. It is Reset or Set by POR.

SFR bit is not present in device

7

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SLAS439 − SEPTEMBER 2004

memory organization

MSP430F2101

MSP430F2111

MSP430F2121

MSP430F2131

Memory

Size

1KB Flash

2KB Flash

4KB Flash

8KB Flash

Main: interrupt vector

Main: code memory

Flash

0FFFFh−0FFE0h

0FFFFh−0FC00h

0FFFFh−0FFE0h

0FFFFh−0F800h

0FFFFh−0FFE0h

0FFFFh−0F000h

0FFFFh−0FFE0h

0FFFFh−0E000h

Information memory

Boot memory

RAM

Size

Flash

256 Byte

010FFh − 01000h

256 Byte

010FFh − 01000h

256 Byte

010FFh − 01000h

256 Byte

010FFh − 01000h

Size

ROM

1KB

0FFFh − 0C00h

1KB

0FFFh − 0C00h

1KB

0FFFh − 0C00h

1KB

0FFFh − 0C00h

Size

128 Byte

256 Byte

027Fh − 0200h

02FFh − 0200h

Peripherals

16-bit

8-bit

8-bit SFR

01FFh − 0100h

0FFh − 010h

0Fh − 00h

01FFh − 0100h

0FFh − 010h

0Fh − 00h

01FFh − 0100h

0FFh − 010h

0Fh − 00h

01FFh − 0100h

0FFh − 010h

0Fh − 00h

bootstrap loader (BSL)

The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial

interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete

description of the features of the BSL and its implementation, see the Application report Features of the MSP430

Bootstrap Loader, Literature Number SLAA089.

BSL Function

Data Transmit

Data Receive

DW, PW & DGV Package Pins

14 - P1.1

RGE Package Pins

14 - P1.1

10 - P2.2

8 - P2.2

flash memory

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The

CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

D

Flash memory has n segments of main memory and four segments of information memory (A to D) of 64

bytes each. Each segment in main memory is 512 bytes in size.

D

Segments 0 to n may be erased in one step, or each segment may be individually erased.

Segments A to D can be erased individually, or as a group with segments 0−n.

Segments A to D are also called information memory.

D

Segment A contains calibration data. After reset segment A is protected against programming or erasing.

It can be unlocked but care should be taken not to erase this segment if the calibration data is required.

8

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SLAS439 − SEPTEMBER 2004

peripherals

Peripherals are connected to the CPU through data, address, and control busses and can be handled using

all instructions. For complete module descriptions, refer to the MSP430x2xx Family User’s Guide.

oscillator and system clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal

oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock

module is designed to meet the requirements of both low system cost and low-power consumption. The internal

DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic clock module provides the

following clock signals:

D

Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.

Main clock (MCLK), the system clock used by the CPU.

Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.

DCO Calibration Data (provided from factory in flash info memory segment A)

DCO Frequency

Calibration Register

CALBC1_1MHz

CALDCO_1MHz

CALBC1_8MHz

CALDCO_8MHz

CALBC1_12MHz

CALDCO_12MHz

CALBC1_16MHz

CALDCO_16MHz

Size

byte

Address

010FFh

010FEh

010FDh

010FCh

010FBh

010FAh

010F9h

010F8h

1 MHz

8 MHz

12 MHz

16 MHz

brownout

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on

and power off.

digital I/O

There are two 8-bit I/O ports implemented—ports P1 and P2:

D

All individual I/O bits are independently programmable.

Any combination of input, output, and interrupt conditions is possible.

Edge-selectable interrupt input capability for all the eight bits of port P1 and P2.

Read/write access to port-control registers is supported by all instructions.

Each I/O has an individually programmable pull−up/pull−down resistor.

WDT+ watchdog timer

The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a

software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog

function is not needed in an application, the module can be configured as an interval timer and can generate

interrupts at selected time intervals.

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SLAS439 − SEPTEMBER 2004

comparator_A+

The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,

battery-voltage supervision, and monitoring of external analog signals.

timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple

capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare

registers.

Timer_A3 Signal Connections

Input

Pin Number

Device

Input Signal

Module

Input Name

Module

Block

Module

Output Signal

Output

Pin Number

DW, PW, DGV

RGE

DW, PW DGV

RGE

13 - P1.0

TACLK

ACLK

SMCLK

INCLK

TA0

TACLK

ACLK

Timer

CCR0

CCR1

CCR2

NA

TA0

TA1

TA2

SMCLK

INCLK

CCI0A

CCI0B

GND

9 - P2.1

14 - P1.1

10 - P2.2

7 - P2.1

14 - P1.1

8 - P2.2

14 - P1.1

18 - P1.5

14 - P1.1

18 - P1.5

TA0

V

SS

V

CC

15 - P1.2

16 - P1.3

15 - P1.2

16 - P1.3

TA1

CCI1A

CCI1B

GND

11 - P2.3

15 - P1.2

19 - P1.6

10 - P2.3

15 - P1.2

20 - P1.6

CAOUT (internal)

V

SS

V

CC

V

CC

TA2

CCI2A

CCI2B

GND

12 - P2.4

16 - P1.3

20 - P1.7

11 - P2.4

16 - P1.3

21 - P1.7

ACLK (internal)

V

SS

V

CC

V

CC

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SLAS439 − SEPTEMBER 2004

peripheral file map

PERIPHERALS WITH WORD ACCESS

Timer_A

Reserved

Capture/compare register

Timer_A register

Reserved

Capture/compare control

Timer_A control

Timer_A interrupt vector

017Eh

017Ch

017Ah

0178h

0176h

0174h

0172h

0170h

016Eh

016Ch

016Ah

0168h

0166h

0164h

0162h

0160h

012Eh

TACCR2

TACCR1

TACCR0

TAR

TACCTL2

TACCTL1

TACCTL0

TACTL

TAIV

Flash Memory

Flash control 3

Flash control 2

Flash control 1

FCTL3

FCTL2

FCTL1

012Ch

012Ah

0128h

Watchdog

Watchdog/timer control

WDTCTL

0120h

PERIPHERALS WITH BYTE ACCESS

Comparator_A

Comparator_A port disable

Comparator_A control 2

Comparator_A control 1

CAPD

CACTL2

CACTL1

05Bh

05Ah

059h

Basic Clock

Port P2

Basic clock system control 3

Basic clock system control 2

Basic clock system control 1

DCO clock frequency control

BCSCTL3 053h

BCSCTL2 058h

BCSCTL1 057h

DCOCTL

056h

Port P2 resistor enable

Port P2 selection

Port P2 interrupt enable

Port P2 interrupt edge select

Port P2 interrupt flag

Port P2 direction

P2REN

P2SEL

P2IE

P2IES

P2IFG

P2DIR

P2OUT

P2IN

02Fh

02Eh

02Dh

02Ch

02Bh

02Ah

029h

028h

Port P2 output

Port P2 input

Port P1

Port P1 resistor enable

Port P1 selection

Port P1 interrupt enable

Port P1 interrupt edge select

Port P1 interrupt flag

Port P1 direction

P1REN

P1SEL

P1IE

P1IES

P1IFG

P1DIR

P1OUT

P1IN

027h

026h

025h

024h

023h

022h

021h

020h

Port P1 output

Port P1 input

Special Function

SFR interrupt flag 2

SFR interrupt flag 1

SFR interrupt enable 2

SFR interrupt enable 1

IFG2

IFG1

IE2

003h

002h

001h

000h

IE1

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SLAS439 − SEPTEMBER 2004

†

absolute maximum ratings

Voltage applied at V

to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V

CC

SS

Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V +0.3 V

Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA

CC

Storage temperature, T (unprogrammed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C

stg

Storage temperature, T (programmed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C

stg

NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended

operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

2. All voltages referenced to V . The JTAG fuse-blow voltage, V , is allowed to exceed the absolute maximum rating. The voltage

SS

FB

is applied to the TEST pin when blowing the JTAG fuse.

3. Higher temperature may be applied during board soldering process according to the current JEDEC J−STD−020 specification with

peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

recommended operating conditions

MIN

1.8

NOM

MAX UNITS

Supply voltage during program execution, V

CC

MSP430F21x1

3.6

V

Supply voltage during program/erase flash memory, V

CC

2.2

Supply voltage, V

SS

0

V

Operating free-air temperature range, T

MSP430F21x1

−40

dc

85

6

°C

A

V

= 1.8 V,

CC

Duty Cycle = 50% 10%

V

= 2.2 V,

CC

Duty Cycle = 50% 10%

dc

8

V

= 2.7 V,

CC

Duty Cycle = 50% 10%

12

Processor frequency f

SYSTEM

(Maximum MCLK frequency)

MHz

V

= 3.0 V,

TBD,

>12MHz

CC

Duty Cycle = 50% 10%

V

= 3.3 V,

TBD,

>12MHz

CC

Duty Cycle = 50% 10%

V

CC

= 3.6 V,

TBD,

>12MHz

Duty Cycle = 50% 10%

16 MHz

Supply voltage

range, ’x21x1, during

program execution

TBD

12 MHz

6 MHz

Supply voltage range,

’x21x1, during flash

memory programming

1.8 V 2.2 V 2.7 V 3.3 V 3.6 V

Supply Voltage, V

NOTE: Minimum processor frequency is defined by system clock. Flash

program or erase operations require a minimum V of 2.2 V.

CC

Figure 1. Frequency vs Supply Voltage, MSP430x21x1

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SLAS439 − SEPTEMBER 2004

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

supply current (into V ) excluding external current (see Notes 1 and 2)

CC

PARAMETER

TEST CONDITIONS

= f = 1MHz,

VCC

MIN

TYP MAX

UNIT

f

= f

ACLK

DCO MCLK SMCLK

= 32,768Hz,

2.2 V

3 V

200

300

250

350

Active mode

current

I

µA

ACTIVE

Program executes in flash

CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0

Low-power mode

0 current, (LPM0)

see Note 3

f

= 0MHz, f = 1MHz,

= 32,768Hz,

= f

2.2 V

3 V

32

55

11

17

45

70

14

22

MCLK

ACLK

DCO SMCLK

I

µA

LPM0

CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0

Low-power mode

1 current, (LPM2)

see Note 4

f

= f

MCLK SMCLK

= 0MHz, f = 1MHz,

DCO

= 32,768Hz,

2.2 V

3 V

f

LPM2

ACLK

CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0

T

= −40°C

= 25°C

= 85°C

= −40°C

= 25°C

= 85°C

= −40°C

= 25°C

= 85°C

0.7

1.0

0.9

1.5

0.1

0.8

TBD

A

T

A

2.2 V

3 V

Low-power mode

2 current, (LPM3)

see Note 4

f

= f = 0MHz,

= f

= 32,768Hz,

DCO MCLK SMCLK

T

A

f

ACLK

I

µA

LPM3

CPUOFF = 1, SCG0 = 1, SCG1 = 1,

OSCOFF = 0

T

A

T

A

T

A

f

= f = f = 0MHz,

= 32,768Hz,

T

A

DCO MCLK SMCLK

Low-power mode

4 current, (LPM4)

see Note 5

f

ACLK

T

A

I

2.2 V/3 V

LPM4

CPUOFF = 1, SCG0 = 1, SCG1 = 1,

OSCOFF = 1

T

A

NOTES: 1. All inputs are tied to 0 V or V . Outputs do not source or sink any current.

CC

2. The currents are characterized with a KDS Daishinku DT−38 (6 pF) crystal and CAPx = 1.

3. Current for brownout and WDT clocked by SMCLK included.

4. Current for brownout and WDT clocked by ACLK included.

5. Current for brownout included.

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SLAS439 − SEPTEMBER 2004

typical supply current (into V ) characteristics

CC

TBD

V

CC

− Supply Voltage − V

Figure 2. Active mode current vs V

CC

TBD

DCO Frequency − MHz

Figure 3. Active mode current vs DCO frequency

14

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SLAS439 − SEPTEMBER 2004

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

Schmitt-trigger inputs − Ports P1 and P2

PARAMETER

TEST CONDITIONS

MIN

0.45

1.00

1.35

0.25

0.55

0.75

0.2

TYP

MAX

0.75

1.65

2.25

0.55

1.20

1.65

1.0

UNIT

V

CC

V

= 2.2 V

V

IT+

Positive-going input threshold voltage

CC

= 3 V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 2.2 V

= 3 V

V

Negative-going input threshold voltage

IT−

= 2.2 V

= 3 V

Input voltage hysteresis (V

− V

)

V

hys

IT+

IT−

0.3

1.0

For pull−up: V = V

For pull−down: V = V

IN

;

IN SS

R

C

Pull−up/pull−down resistor

Input Capacitance

TBD

W

Pull

I

CC

V

IN

= V

SS

or V

CC

TBD

pF

inputs − Ports P1 and P2

PARAMETER

TEST CONDITIONS

VCC

2.2 V

3 V

MIN

50

TYP

MAX

UNIT

Port P1, P2: P1.x to P2.x, External trigger puls

width to set interrupt flag, (see Note 1)

t

External interrupt timing

ns

(int)

30

NOTES: 1. An external signal sets the interrupt flag every time the minimum interrupt puls width t

(int)

is met. It may be set even with trigger signals

shorter than t

.

(int)

leakage current − Ports P1 and P2

PARAMETER

TEST CONDITIONS

VCC

2.2 V/3 V

MIN

TYP

MAX

UNIT

I

High-impedance leakage current

see Notes 1 and 2

50

nA

lkg(Px.x)

NOTES: 1. The leakage current is measured with V

or V

CC

applied to the corresponding pin(s), unless otherwise noted.

SS

2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pull−up/pull−down resistor

is disabled.

15

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SLAS439 − SEPTEMBER 2004

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

outputs − Ports P1 and P2

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

I

= −1.5 mA (see Notes 1 and 3) 2.2 V

= −6 mA (see Notes 2 and 3) 2.2 V

= −1.5 mA (see Notes 1 and 3) 3 V

= −6 mA (see Notes 2 and 3) 3 V

= 1.5 mA (see Notes 1 and 3) 2.2 V

V

−0.25

V

(OHmax)

(OLmax)

CC

V

−0.6

CC

−0.25

V

High-level output voltage

V

OH

OL

V

CC

V

−0.6

CC

V

+0.25

SS

= 6 mA (see Notes 2 and 3)

= 1.5 mA (see Notes 1 and 3) 3 V

= 6 mA (see Notes 2 and 3) 3 V

2.2 V

V

+0.6

SS

V

Low-level output voltage

Output capacitance

V

SS

+0.25

V

+0.6

SS

C

TBD

pF

O

NOTES: 1. The maximum total current, I

voltage drop specified.

and I

, for all outputs combined, should not exceed 12 mA to hold the maximum

OHmax

OLmax

2. The maximum total current, I

voltage drop specified.

, for all outputs combined, should not exceed 48 mA to hold the maximum

OHmax

OLmax

3. One output loaded at a time.

output frequency − Ports P1 and P2

PARAMETER

TEST CONDITIONS

VCC

2.2 V

3 V

MIN

TYP

MAX

10

UNIT

MHz

Port output frequency Px.y (TBD), C = 20 pF, R = 1 kOhm

(with load)

L

f

Px.y

(see Note 1 and 2)

12

2.2 V

3 V

12

Clock output

frequency

P2.0/ACLK, P1.4/SMCLK, C = 20 pF

L

Port_CLK

(see Note 2)

16

NOTES: 1. A resistive divider with 2 times 0.5 kW between V

and V

is used as load. The output is connected to the center tap of the divider.

at the specified toggle frequency.

CC

SS

2. The output voltage reaches at least 10% and 90% V

CC

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SLAS439 − SEPTEMBER 2004

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

outputs − Ports P1 and P2 (continued)

TYPICAL LOW-LEVEL OUTPUT CURRENT

vs

LOW-LEVEL OUTPUT VOLTAGE

16

14

12

10

8

25

20

15

10

5

V

CC

P1.0

= 2.2 V

T

= 25°C

V

CC

P1.0

= 3 V

A

T

= 25°C

A

T

= 85°C

A

T

= 85°C

A

6

4

2

0

0.0

0

0.0

0.5

1.0

1.5

2.0

2.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

V

OL

− Low-Level Output Voltage − V

V

OL

− Low-Level Output Voltage − V

Figure 4

Figure 5

TYPICAL HIGH-LEVEL OUTPUT CURRENT

vs

HIGH-LEVEL OUTPUT VOLTAGE

0

−2

0

−5

V

CC

P1.0

= 2.2 V

V

CC

P1.0

= 3 V

−4

−10

−15

−20

−25

−30

−6

−8

T

A

= 85°C

−10

−12

−14

T

A

= 85°C

T

A

= 25°C

T

A

= 25°C

0.0

0.5

OH

1.0

1.5

2.0

2.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

V

− High-Level Output Voltage − V

V

OH

− High-Level Output Voltage − V

Figure 6

Figure 7

NOTE: One output loaded at a time.

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SLAS439 − SEPTEMBER 2004

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

Timer_A

PARAMETER

TEST CONDITIONS

Internal: SMCLK, ACLK;

VCC

MIN

TYP

MAX

UNIT

2.2 V

10

f

t

Timer_A clock frequency

MHz

External: TACLK, INCLK;

Duty Cycle = 50% 10%

TA

3 V

16

2.2 V

3 V

50

30

Timer_A, capture timing

TA0, TA1, TA2

ns

TA,cap

Comparator_A+ (see Note 1)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

25

MAX UNIT

2.2 V

3 V

40

µA

60

I

CAON=1, CARSEL=0, CAREF=0

(DD)

45

CAON=1, CARSEL=0,

CAREF=1/2/3, no load at

P2.3/CA0/TA1 and P2.4/CA1/TA2

2.2 V

3 V

30

45

50

µA

71

(Refladder/RefDiode)

Common-mode input

voltage

V

CAON =1

2.2 V/3 V

0

V

CC

−1

V

(IC)

PCA0=1, CARSEL=1, CAREF=1,

No load at P2.3/CA0/TA1 and

P2.4/CA1/TA2

Voltage @ 0.25 V

CC

node

V

0.23

0.24

0.48

0.25

0.5

(Ref025)

V

CC

PCA0=1, CARSEL=1, CAREF=2,

No load at P2.3/CA0/TA1 and

P2.4/CA1/TA2

Voltage @ 0.5V

node

CC

V

2.2 V/3 V

0.47

(Ref050)

(RefVT)

V

CC

PCA0=1, CARSEL=1, CAREF=3,

No load at P2.3/CA0/TA1 and

P2.4/CA1/TA2, T = 85°C

2.2 V

3 V

390

400

480

490

540

550

V

(see Figure 8 and Figure 9)

mV

A

V

Offset voltage

See Note 2

2.2 V/3 V

2.2 V

3 V

−30

0

30

1.4

mV

(offset)

Input hysteresis

CAON=1

0.7

210

150

1.9

hys

160

90

300

240

3.4

T

= 25°C, Overdrive 10 mV,

A

ns

µs

ns

µs

Without filter: CAF=0

t

(response LH)

2.2 V

3 V

1.4

0.9

130

80

T

= 25°C, Overdrive 10 mV,

A

With filter: CAF=1

1.5

2.6

2.2 V

3 V

210

150

300

240

T

= 25°C, Overdrive 10 mV,

A

Without filter: CAF=0

t

(response HL)

2.2 V

3 V

1.4

0.9

1.9

1.5

3.4

2.6

T

= 25°C, Overdrive 10 mV,

A

With filter: CAF=1

NOTES: 1. The leakage current for the Comparator_A terminals is identical to I

specification.

lkg(Px.x)

2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.

The two successive measurements are then summed together.

18

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SLAS439 − SEPTEMBER 2004

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

typical characteristics

650

600

550

500

450

400

650

600

550

500

450

400

V

= 2.2 V

V

CC

= 3 V

CC

Typical

−45

−25

−5

15

35

55

75

95

−45

−25

−5

15

35

55

75

95

T

A

− Free-Air Temperature − °C

T

A

− Free-Air Temperature − °C

Figure 9. V

vs Temperature, V

= 2.2 V

Figure 8. V

vs Temperature, V

= 3 V

(RefVT)

CC

(RefVT)

CC

typical resistance between CA+ and CA− with CASHORT = 1

TBD

V

CC

− Supply Voltage − V

Figure 10. Short resistance vs V

CC

19

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SLAS439 − SEPTEMBER 2004

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

0 V

V

CC

0

1

CAF

CAON

To Internal

Modules

Low Pass Filter

0

1

0

1

+

_

V+

V−

CAOUT

Set CAIFG

Flag

τ ≈ 2.0 µs

Figure 11. Block Diagram of Comparator_A Module

V

CAOUT

Overdrive

V−

400 mV

V+

t

(response)

Figure 12. Overdrive Definition

POR/brownout reset (BOR) (see Note 1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

µs

t

2000

d(BOR)

V

dV /dt ≤ 3 V/s (see Figure 13)

CC

0.7 × V

(B_IT−)

V

CC(start)

Brownout

V

dV /dt ≤ 3 V/s (see Figure 13 through Figure 15)

CC

dV /dt ≤ 3 V/s (see Figure 13)

CC

1.71

180

V

(B_IT−)

(see Note 2)

70

2

130

mV

hys(B_IT−)

Pulse length needed at RST/NMI pin to accepted reset internally,

t

µs

(reset)

V

CC

= 2.2 V/3 V

NOTES: 1. The current consumption of the brownout module is already included in the I

current consumption data. The voltage level V

(B_IT−)

CC

+ V

is ≤ 1.8V.

2. During power up, the CPU begins code execution following a period of t

hys(B_IT−)

after V

CC

= V

(B_IT−)

+ V . The default

hys(B_IT−)

d(BOR)

CC(min)

DCO settings must not be changed until V

operating frequency.

≥ V

, where V

is the minimum supply voltage for the desired

CC

CC(min)

20

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SLAS439 − SEPTEMBER 2004

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

typical characteristics

V

CC

V

hys(B_IT−)

V

(B_IT−)

V

CC(start)

1

0

t

d(BOR)

Figure 13. POR/Brownout Reset (BOR) vs Supply Voltage

V

t

CC

pw

2

3 V

V

= 3 V

CC

Typical Conditions

1.5

1

V

CC(min)

0.5

0

0.001

1

1000

1 ns

− Pulse Width − µs

t

− Pulse Width − µs

t

pw

Figure 14. V

Level With a Square Voltage Drop to Generate a POR/Brownout Signal

(CC)min

V

t

CC

pw

2

3 V

V

= 3 V

CC

Typical Conditions

1.5

1

V

CC(min)

0.5

t = t

f

r

0

0.001

1

1000

t

r

f

t

− Pulse Width − µs

t

− Pulse Width − µs

pw

Figure 15. V

Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal

CC(min)

21

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SLAS439 − SEPTEMBER 2004

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

main DCO characteristics

D

All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14

overlaps RSELx = 15.

D

DCO control bits DCOx have a step size as defined by parameter S

.

DCO

D

Modulation control bits MODx select how often f

is used within the period of 32 DCOCLK

DCO(RSEL,DCO+1)

cycles. The frequency f

to:

is used for the remaining cycles. The frequency is an average equal

DCO(RSEL,DCO)

32 f_{DCO(RSEL,DCO)} f_{DCO(RSEL,DCO)1)}

f_average

+

MOD f_{DCO(RSEL,DCO)})(32*MOD) f_{DCO(RSEL,DCO)1)}

DCO frequency

PARAMETER

TEST CONDITIONS

RSELx = 0, DCOx = 3, MODx = 0

VCC

2.2 V/3 V

MIN

0.08

0.10

0.14

0.21

0.29

0.41

0.58

0.81

1.14

1.67

2.35

2.94

4.15

5.70

8.25

10.9

16.0

TYP

MAX

0.12

0.15

0.20

0.29

0.40

0.56

0.77

1.07

1.54

2.27

3.25

4.07

5.67

7.45

11.3

16.5

23.0

1.4

UNIT

MHz

f

DCO(0,3)

DCO(1,3)

DCO(2,3)

DCO(3,3)

DCO(4,3)

DCO(5,3)

DCO(6,3)

DCO(7,3)

DCO(8,3)

DCO(9,3)

DCO(10,3)

DCO(11,3)

DCO(12,3)

DCO(13,3)

DCO(14,3)

DCO(15,3)

DCO(15,7)

RSELx = 1, DCOx = 3, MODx = 0

RSELx = 2, DCOx = 3, MODx = 0

RSELx = 3, DCOx = 3, MODx = 0

RSELx = 4, DCOx = 3, MODx = 0

RSELx = 5, DCOx = 3, MODx = 0

RSELx = 6, DCOx = 3, MODx = 0

RSELx = 7, DCOx = 3, MODx = 0

RSELx = 8, DCOx = 3, MODx = 0

RSELx = 9, DCOx = 3, MODx = 0

RSELx = 10, DCOx = 3, MODx = 0

RSELx = 11, DCOx = 3, MODx = 0

RSELx = 12, DCOx = 3, MODx = 0

RSELx = 13, DCOx = 3, MODx = 0

RSELx = 14, DCOx = 3, MODx = 0

RSELx = 15, DCOx = 3, MODx = 0

RSELx = 15, DCOx = 7, MODx = 0

2.2 V/3 V

S

= f

/f

RSEL

DCO

RSEL DCO(RSEL+1,DCO) DCO(RSEL,DCO)

ratio

%

S

S = f /f

DCO DCO(RSEL,DCO+1) DCO(RSEL,DCO)

1.05

45

1.10

50

1.12

Duty Cycle

Measured at P1.4/SMCLK

2.2 V/3 V

55

22

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SLAS439 − SEPTEMBER 2004

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

DCO drift

Temperature drift (Box Method),

RSELx = 0, DCOx = 3, MODx = 0

D

2.2 V/3 V

TBD

%

T(0,3)

T(7,3)

T(15,3)

V(0,3)

T(7,3)

T(15,3)

T(0,3)

T(7,3)

T(15,3)

T

= −40°C − +85°C

A

(see Note 1)

Temperature drift (Box Method),

RSELx = 7, DCOx = 3, MODx = 0

2.2 V/3 V

T

= −40°C − +85°C

A

(see Note 1)

Temperature drift (Box Method),

RSELx = 15, DCOx = 3, MODx = 0

2.2 V/3 V

T

= −40°C − +85°C

A

(see Note 1)

Supply voltage drift (Box Method),

RSELx = 0, DCOx = 3, MODx = 0

1.8 V − 3.6 V

T

= 25°C

A

(see Note 1)

Supply voltage drift (Box Method),

RSELx = 7, DCOx = 3, MODx = 0

T

= 25°C

A

(see Note 1)

Supply voltage drift (Box Method),

RSELx = 15, DCOx = 3, MODx = 0

T

= 25°C

A

(see Note 1)

Total drift (Box Method),

RSELx = 0, DCOx = 3, MODx = 0

T

= −40°C − +85°C

A

(see Note 1)

Total drift (Box Method),

RSELx = 7, DCOx = 3, MODx = 0

T

= −40°C − +85°C

A

(see Note 1)

Total drift (Box Method),

RSELx = 15, DCOx = 3, MODx = 0

T

= −40°C − +85°C

A

(see Note 1)

NOTE 1: These parameters are not production tested.

23

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SLAS439 − SEPTEMBER 2004

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

wake-up from lower power modes (LPM3/4)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

f

= f

, RSELx = 3,

, RSELx = 7,

, RSELx = 11,

, RSELx = 15,

DCO DCO(3,3)

2.2 V/3 V

7

DCOx = 3

f

= f

DCO DCO(7,3)

DCOx = 3

2.2 V/3 V

2

1.5

1.0

DCO clock wake−up time from LPM3/4

(see Note 1)

t

µs

Clock,LPM3/4

CPU,LPM3/4

f

= f

DCO DCO(11,3)

DCOx = 3

f

= f

DCO DCO(15,3)

DCOx = 3

1/f

MCLK

+

CPU wake−up time from LPM3/4

(see Note 2)

t

Clock,LPM3/4

NOTES: 1. The DCO clock wake−up time is measured from the edge of an external wake−up signal (e.g. port interrupt) to the first clock edge

observable externally on a clock pin (MCLK or SMCLK).

2. Parameter applicable only if DCOCLK is used for MCLK.

typical wake−up time characteristics

TBD

DCO Frequency − MHz

Figure 16. Clock wake−up time vs DCO frequency

24

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SLAS439 − SEPTEMBER 2004

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

crystal oscillator, LFXT1

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

LFXT1 oscillator crystal

f

frequency, LF mode 0,

1

XTS = 0, LFXT1Sx = 0 or 1

32,768

Hz

LFXT1,LF

LFXT1 oscillator crystal

frequency, HF mode 0

f

XTS = 1, LFXT1Sx = 0

XTS = 1, LFXT1Sx = 1

XTS = 1, LFXT1Sx = 2

0.4

1

4

MHz

LFXT1,HF0

LFXT1,HF1

LFXT1,HF2

LFXT1 oscillator crystal

frequency, HF mode 1

LFXT1 oscillator crystal

frequency, HF mode 2

2

16

LFXT1 oscillator logic

f

level square wave input XTS = 0, LFXT1Sx = 3

frequency, LF mode

10,000

32,768

50,000

Hz

LFXT1,LF,logic

LFXT1,HF,logic

LFXT1 oscillator logic

level square wave input XTS = 1, LFXT1Sx = 3

frequency, HF mode

f

0.4

20

16

MHz

Supported ESR for LF

XTS = 0, LFXT1Sx = 0 or 1

crystals

ESR

100

kW

W

LF

XTS = 0, LFXT1Sx = 0,

500

100

50

f

= 1 MHz, C = 32 pF

L

LFXT1,HF

XTS = 0, LFXT1Sx = 1

= 4 MHz, C = 32 pF

Supported ESR for HF

crystals (refer to

Figure 17 and

W

ESR

HF

f

LFXT1,HF

XTS = 0, LFXT1Sx = 2

= 16 MHz, C = 32 pF

L

Figure 18)

W

f

LFXT1,HF

L

XTS = 0, XCAPx = 0

XTS = 0, XCAPx = 1

XTS = 0, XCAPx = 2

XTS = 0, XCAPx = 3

XTS = 1 (see Note 2)

XTS = 0, XCAPx = 0

XTS = 0, XCAPx = 1

XTS = 0, XCAPx = 2

XTS = 0, XCAPx = 3

XTS = 1 (see Note 2)

XTS = 0, Measured at P1.4/ACLK,

2

11

17

22

2

pF

Input capacitance

(see Note 1)

C

XIN

2

11

17

22

2

Output capacitance

(see Note 1)

XOUT

LF mode

HF mode

2.2 V/ 3 V

30

35

50

70

65

%

f

= 32,768 Hz

LFXT1,LF

XTS = 1, Measured at P1.4/ACLK,

= 10 MHz

Duty Cycle

f

LFXT1,HF

XTS = 1, Measured at P1.4/ACLK,

= 16 MHz

40

60

%

f

LFXT1,HF

Oscillator fault

frequency, LF mode

XTS = 0, LFXT1Sx = 3

(see Note 3)

f

TBD

0.05

10,000

0.25

Hz

MHz

Fault,LF

Oscillator fault

frequency, HF mode

XTS = 1, LFXT1Sx = 3

(see Note 3)

Fault,HF

NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF).

2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

3. Measured with logic level input frequency but also applies to operation with crystals.

25

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SLAS439 − SEPTEMBER 2004

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

typical operating areas for oscillator LFXT1 in HF mode (XTS = 1)

TBD

Crystal Frequency − kHz

Figure 17. ESR with Safety Factor (SF) = 3 vs Crystal Frequency, C = 32 pF

L

TBD

Crystal Frequency − kHz

Figure 18. ESR with Safety Factor (SF) = 3 vs Crystal Frequency, C = 15 pF

L

26

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SLAS439 − SEPTEMBER 2004

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

Flash Memory

TEST

CONDITIONS

PARAMETER

VCC

MIN

NOM

MAX

UNIT

V

CC(PGM/

ERASE)

Program and Erase supply voltage

Flash Timing Generator frequency

2.2

3.6

V

f

I

t

257

476

5

kHz

mA

FTG

Supply current from V

during program

during erase

2.7 V/ 3.6 V

3

PGM

CC

7

mA

ERASE

CPT

CC

Cumulative program time

see Note 1

4

ms

Cumulative mass erase time

Program/Erase endurance

Data retention duration

20

ms

CMErase

4

10

5

10

cycles

years

t

T = 25°C

J

100

Retention

t

Word or byte program time

30

25

Word

st

Block program time for 1 byte or word

Block, 0

Block program time for each additional byte or word

Block program end-sequence wait time

Mass erase time

18

Block, 1-63

Block, End

Mass Erase

Seg Erase

see Note 2

t

FTG

6

10593

4819

Segment erase time

NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming

methods: individual word/byte write and block write modes.

2. These values are hardwired into the Flash Controller’s state machine (t

= 1/f ).

FTG

RAM

PARAMETER

MIN NOM

MAX

UNIT

V

CPU halted (see Note 1)

1.6

V

(RAMh)

NOTE 1: This parameter defines the minimum supply voltage V

when the data in the program memory RAM remains unchanged. No program

execution should happen during this supply voltage condition.

CC

JTAG Interface

TEST

CONDITIONS

PARAMETER

VCC

MIN NOM

MAX

UNIT

2.2 V

3 V

0

5

10

90

MHz

kΩ

f

TCK input frequency

see Note 1

TCK

R

Internal pull-down resistance on TEST

may be restricted to meet the timing requirements of the module selected.

2.2 V/ 3 V

25

60

Internal

NOTES: 1. f

TCK

JTAG Fuse (see Note 1)

TEST

CONDITIONS

PARAMETER

VCC

MIN NOM

MAX

UNIT

V

Supply voltage during fuse-blow condition

Voltage level on TEST for fuse-blow

Supply current into TEST during fuse blow

Time to blow fuse

T

A

= 25°C

2.5

6

V

CC(FB)

7

100

1

FB

I

t

mA

ms

FB

NOTES: 1. Once the fuse is blown, no further access to the JTAG/Test and emulation feature is possible and is switched to bypass mode.

27

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SLAS439 − SEPTEMBER 2004

APPLICATION INFORMATION

Port P1 pin schematic: P1.0 to P1.3, input/output with Schmitt-trigger

PxSEL.x

CAPD.x

PxDIR.x

0

Direction

1

0: Input

Module Direction

1: Output

PxOUT.x

0

1

Module Output

P1.0/TACLK

P1.1/TA0

P1.2/TA1

P1.3/TA2

Bus

Keeper

PxIN.x

Module Input

EN

Interrupt

Logic

Set PxIFG.x

PRIMARY FUNCTION

SECONDARY FUNCTION

GPIO

Module IO

Analog IO

JTAG

Control Bits/Signals

input

0†

output

input

output

P1SEL.x

0

1

0

1

N/A

P1DIR.x

0†

Pin Name (P1.x)

P1.0/TACLK

P1.1/TA0

P1.0 input†

P1.1 input†

P1.2 input†

P1.3 input†

P1.0 output

P1.1 output

P1.2 output

P1.3 output

Timer_A3.TACLK

Timer_A3.CCI0A

Timer_A3.CCI1A

Timer_A3.CCI2A

DV

N/A

SS

Timer_A3.TA0

Timer_A3.TA1

Timer_A3.TA2

P1.2/TA1

P1.3/TA2

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable.

2. X: Don’t care.

28

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SLAS439 − SEPTEMBER 2004

APPLICATION INFORMATION

Port P1 pin schematic: P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features

PxREN.x

PxOUT.x

PxSEL.x

DV

0

1

SS

CC

PxDIR.x

0

1

Direction

0: Input

Module Direction

1: Output

PxOUT.x

0

1

Module Output

P1.4/SMCLK/TCK

P1.5/TA0/TMS

P1.6/TA1/TDI

Bus

Keeper

PxIN.x

P1.7/TA2/TDO/TDI

Module Input

EN

Set PxIFG.x

To JTAG

Interrupt

Logic

From TEST pad

From JTAG

From JTAG (TDO)

P1.7/TA2/TDO/TDI only

To JTAG pads

TEST

JTAG

Fuse

DV

TEST pad

SS

PRIMARY FUNCTION

SECONDARY FUNCTION

GPIO

Module IO

Analog IO

JTAG

Control Bits/Signals

P1SEL.x

input

0†

output

input

output

0

1

0

1

0

1

0

N/A

X

1

P1DIR.x

0†

TEST (from pin)

Pin Name (P1.x)

P1.4/SMCLK/TCK

P1.5/TA0/TMS

P1.6/TA1/TDI/TCLK

P1.7/TA2/TDO/TDI

0†

P1.4 input†

P1.5 input†

P1.6 input†

P1.7 input†

P1.4 output

P1.5 output

P1.6 output

P1.7 output

N/A

SMCLK

N/A

TCK

TMS

Timer_A3.TA0

Timer_A3.TA1

Timer_A3.TA2

TDI/TCLK‡

TDO/TDI‡

†

Default after reset (PUC/POR)

Function controlled by JTAG

NOTES: 1. N/A: Not available or not applicable.

2. X: Don’t care.

29

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLAS439 − SEPTEMBER 2004

APPLICATION INFORMATION

Port P2 pin schematic: P2.0 to P2.5, input/output with Schmitt-trigger

P2OUT.x

CAPD.x

P2REN.x

P2SEL.x

DV

0

1

SS

CC

P2DIR.x

0

Direction

Module Direction

1

0: Input

1: Output

P2OUT.x

0

1

Module Output

P2.0/ACLK/CA2

P2.1/INCLK/CA3

P2.2/CAOUT/TA0/CA4

P2.3/TA1/CA0

Bus

Keeper

P2IN.x

Module Input

EN

P2.4/TA2/CA1

P2.5/CA5

EN

Interrupt

Logic

Set P2IFG.x

From Comparator

To Comparator

PRIMARY FUNCTION

GPIO

SECONDARY FUNCTION

Module IO

Analog IO

JTAG

Control Bits/Signals

P2SEL.x

input

0†

output

input

output

0

1

0

1

0

1

0

X

1

N/A

P2DIR.x

0†

CAPD.x

0†

Pin Name (P2.x)

P2.0/ACLK/CA2

P2.1/INCLK/CA3

P2.2/CAOUT/TA0/CA4

P2.3/TA1/CA0

P2.4/TA2/CA1

P2.5/CA5

P2.0 input†

P2.1 input†

P2.2 input†

P2.3 input†

P2.4 input†

P2.5 input†

P2.0 output

P2.1 output

P2.2 output

P2.3 output

P2.4 output

P2.5 output

N/A

ACLK

CA2

CA3

CA4

CA0

CA1

CA5

N/A

Timer_A3.INCLK

DV

SS

Timer_A3.CCI0B

Comparator_A.OUT

Timer_A3.TA1

Timer_A3.TA2

N/A

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable.

2. X: Don’t care.

30

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ

SLAS439 − SEPTEMBER 2004

APPLICATION INFORMATION

Port P2 pin schematic: P2.6, input/output with Schmitt-trigger and crystal oscillator input

P2OUT.x

P2REN.x

P2SEL.x

CAPD.x

DV

0

1

SS

CC

P2DIR.x

DV

0

Direction

1

0: Input

1: Output

SS

P2OUT.x

P2IN.x

XIN/P2.6/CA6

Bus

Keeper

EN

Interrupt

Logic

Set P2IFG.x

From Comparator

To Comparator

LFXT1 Oscillator

OSCOFF

1

0

LFXT1CLK

BCSCTL3.LFXT1S = 11

XOUT

PRIMARY FUNCTION

GPIO

SECONDARY FUNCTION

Module IO

output

N/A

Analog IO

JTAG

Control Bits/Signals

P2SEL.x

input

0

output

input

1†

X

0

1

0

X

1

N/A

P2DIR.x

0†

N/A

CAPD.x

0†

X

N/A

Pin Name (P2.x)

P2.6/XIN/CA6

P2.6 input

P2.6 output

XIN†

N/A

CA6

N/A

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable.

2. X: Don’t care.

31

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ

SLAS439 − SEPTEMBER 2004

APPLICATION INFORMATION

Port P2 pin schematic: P2.7, input/output with Schmitt-trigger and crystal oscillator output

P2OUT.x

P2REN.x

P2SEL.x

CAPD.x

DV

0

1

SS

CC

P2DIR.x

DV

0

Direction

1

0: Input

1: Output

SS

P2OUT.x

P2IN.x

XOUT/P2.7/CA7

Bus

Keeper

EN

Interrupt

Logic

Set P2IFG.x

From Comparator

To Comparator

LFXT1 Oscillator

OSCOFF

From P2.6/XIN/CA6

1

0

LFXT1CLK

XIN

BCSCTL3.LFXT1S = 11

PRIMARY FUNCTION

GPIO

SECONDARY FUNCTION

Module IO

Analog IO

JTAG

Control Bits/Signals

P2SEL.x

input

0

output

input

N/A

output

0

1

0

1†

X

0

X

1

N/A

P2DIR.x

0†

CAPD.x

0†

X

Pin Name (P2.x)

XOUT/P2.7/CA7

P2.7 input

P2.7 output

N/A

XOUT†

CA7

N/A

†

Default after reset (PUC/POR)

NOTES: 1. N/A: Not available or not applicable.

2. X: Don’t care.

3. If the pin XOUT/P2.7/CA7 is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection

to this pin after reset.

32

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ

SLAS439 − SEPTEMBER 2004

JTAG fuse check mode

MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of

the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check

current, I , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care

TF

must be taken to avoid accidentally activating the fuse check mode and increasing overall system power

consumption.

When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense

currents are terminated.

Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS

is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode.

After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse

check mode has the potential to be activated.

The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see

Figure 19). Therefore, the additional current flow can be prevented by holding the TMS pin high (default

condition).

Time TMS Goes Low After POR

TMS

I

TF

I

TEST

Figure 19. Fuse Check Mode Current, MSP430F21x1

NOTE:

The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader

access key is used. Also, see the bootstrap loader section for more information.

33

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢈ

ꢋ

ꢀ

ꢉ

ꢊ

ꢌ

ꢁ

ꢉ

ꢍ

ꢎ

ꢏ

ꢐ

ꢀ

ꢉ

ꢑ

ꢒ

ꢓꢑ

ꢓꢎ

ꢔ

ꢒ

ꢓꢐ

ꢐꢋ

ꢒ

SLAS439 − SEPTEMBER 2004

MECHANICAL DATA

DW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

16 PIN SHOWN

0.050 (1,27)

16

0.020 (0,51)

0.014 (0,35)

0.010 (0,25)

M

9

0.419 (10,65)

0.400 (10,15)

0.010 (0,25) NOM

0.299 (7,59)

0.293 (7,45)

Gage Plane

0.010 (0,25)

1

8

0°−ā8°

0.050 (1,27)

0.016 (0,40)

A

Seating Plane

0.004 (0,10)

0.012 (0,30)

0.004 (0,10)

0.104 (2,65) MAX

PINS **

16

20

24

0.610

DIM

0.410

0.510

A MAX

(10,41) (12,95) (15,49)

0.400

0.500

0.600

A MIN

(10,16) (12,70) (15,24)

4040000/D 02/98

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).

D. Falls within JEDEC MS-013

34

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ

SLAS439 − SEPTEMBER 2004

MECHANICAL DATA

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°−ā8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

A MAX

A MIN

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

35

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢈ

ꢋ

ꢀ

ꢉ

ꢊ

ꢌ

ꢁ

ꢉ

ꢍ

ꢎ

ꢏ

ꢐ

ꢀ

ꢉ

ꢑ

ꢒ

ꢓꢑ

ꢓꢎ

ꢔ

ꢒ

ꢓꢐ

ꢐꢋ

ꢒ

SLAS439 − SEPTEMBER 2004

MECHANICAL DATA

DGV (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23

0,13

M

0,07

0,40

24

13

0,16 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°−ā8°

0,75

1

12

0,50

A

Seating Plane

0,08

0,15

0,05

1,20 MAX

PINS **

14

16

20

24

38

48

56

DIM

A MAX

3,70

3,50

3,70

3,50

5,10

4,90

5,10

4,90

7,90

7,70

9,80

9,60

11,40

11,20

A MIN

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.

D. Falls within JEDEC: 24/48 Pins − MO-153

14/16/20/56 Pins − MO-194

36

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ

SLAS439 − SEPTEMBER 2004

MECHANICAL DATA

RGE (S-PQFP-N24)

PLASTIC QUAD FLATPACK

4,15

3,85

4,15

3,85

Pin 1 Index Area

Top and Bottom

1,00

0,80

0,20 REF.

Seating Plane

0,05

0,00

0,08

2,55 MAX SQ.

0,50

24X

0,50

7

0,30

1

6

24

19

12

Exposed Thermal Die Pad

(See Note D)

0,30

18

2,50

13

24X

0,18

0,10

4204104/B 11/02

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Quad Flatpack, No-leads, (QFN) package configuration.

D. The package thermal performance may be enhanced by bonding the thermal die pad to an external thermal plane.

E. Falls within JEDEC M0-220.

37

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

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TI assumes no liability for applications assistance or customer product design. Customers are responsible for

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Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

www.ti.com/audio

Data Converters

dataconverter.ti.com

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www.ti.com/automotive

DSP

dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	MSP430F2101IPW
厂家：	TEXAS INSTRUMENTS
描述：	MIXED SIGNAL MICROCONTROLLER 混合信号微控制器微控制器
文件：	总38页 (文件大小：546K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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