MSP430F2254IYFFT [TI]
MIXED SIGNAL MICROCONTROLLER; 混合信号微控制器
| 型号： | MSP430F2254IYFFT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MIXED SIGNAL MICROCONTROLLER |
| 文件： | 总95页 (文件大小：1891K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
MIXED SIGNAL MICROCONTROLLER
1
FEATURES
23
•
Low Supply Voltage Range: 1.8 V to 3.6 V
•
Two Configurable Operational Amplifiers
(MSP430F22x4 Only)
•
Ultra-Low Power Consumption
•
•
Brownout Detector
–
–
–
Active Mode: 270 µA at 1 MHz, 2.2 V
Standby Mode: 0.7 µA
Serial Onboard Programming, No External
Programming Voltage Needed, Programmable
Code Protection by Security Fuse
Off Mode (RAM Retention): 0.1 µA
•
•
•
Ultra-Fast Wake-Up From Standby Mode in
Less Than 1 µs
•
•
•
Bootstrap Loader
On-Chip Emulation Module
Family Members Include:
16-Bit RISC Architecture, 62.5-ns Instruction
Cycle Time
–
–
–
–
–
–
MSP430F2232
Basic Clock Module Configurations
–
–
8KB + 256B Flash Memory
512B RAM
–
Internal Frequencies up to 16 MHz With
Four Calibrated Frequencies to ±1%
–
Internal Very-Low-Power Low-Frequency
Oscillator
MSP430F2252
–
–
16KB + 256B Flash Memory
512B RAM
–
–
–
–
–
32-kHz Crystal
High-Frequency (HF) Crystal up to 16 MHz
Resonator
MSP430F2272
–
–
32KB + 256B Flash Memory
1KB RAM
External Digital Clock Source
External Resistor
MSP430F2234
•
•
•
16-Bit Timer_A With Three Capture/Compare
Registers
–
–
8KB + 256B Flash Memory
512B RAM
16-Bit Timer_B With Three Capture/Compare
Registers
MSP430F2254
–
–
16KB + 256B Flash Memory
512B RAM
Universal Serial Communication Interface
–
Enhanced UART Supporting Auto-Baudrate
Detection (LIN)
MSP430F2274
–
–
32KB + 256B Flash Memory
1KB RAM
–
–
–
IrDA Encoder and Decoder
Synchronous SPI
I2C™
•
•
Available in a 38-Pin Thin Shrink Small-Outline
Package (TSSOP) (DA), 40-Pin QFN Package
(RHA), and 49-Pin Ball Grid Array Package
(YFF) (See Table 1)
•
10-Bit 200-ksps Analog-to-Digital (A/D)
Converter With Internal Reference, Sample-
and-Hold, Autoscan, and Data Transfer
Controller
For Complete Module Descriptions, See the
MSP430x2xx Family User's Guide (SLAU144)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
MSP430 is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION
The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.
The MSP430F22x4/MSP430F22x2 series is an ultra-low-power mixed signal microcontroller with two built-in 16-
bit timers, a universal serial communication interface, 10-bit A/D converter with integrated reference and data
transfer controller (DTC), two general-purpose operational amplifiers in the MSP430F22x4 devices, and 32 I/O
pins.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data for display or for transmission to a host system. Stand-alone radio-frequency (RF) sensor front
ends are another area of application.
Table 1. Available Options
PACKAGED DEVICES(1)(2)
TA
PLASTIC 49-PIN BGA
(YFF)
PLASTIC 38-PIN TSSOP
(DA)
PLASTIC 40-PIN QFN
(RHA)
MSP430F2232IYFF
MSP430F2252IYFF
MSP430F2272IYFF
MSP430F2234IYFF
MSP430F2254IYFF
MSP430F2274IYFF
MSP430F2232IDA
MSP430F2252IDA
MSP430F2272IDA
MSP430F2234IDA
MSP430F2254IDA
MSP430F2274IDA
MSP430F2232TDA
MSP430F2252TDA
MSP430F2272TDA
MSP430F2234TDA
MSP430F2254TDA
MSP430F2274TDA
MSP430F2232IRHA
MSP430F2252IRHA
MSP430F2272IRHA
MSP430F2234IRHA
MSP430F2254IRHA
MSP430F2274IRHA
MSP430F2232TRHA
MSP430F2252TRHA
MSP430F2272TRHA
MSP430F2234TRHA
MSP430F2254TRHA
MSP430F2274TRHA
-40°C to 85°C
-40°C to 105°C
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Development Tool Support
All MSP430™ microcontrollers include an Embedded Emulation Module (EEM) that allows advanced debugging
and programming through easy-to-use development tools. Recommended hardware options include:
•
Debugging and Programming Interface
–
–
MSP-FET430UIF (USB)
MSP-FET430PIF (Parallel Port)
•
•
Debugging and Programming Interface with Target Board
MSP-FET430U38 (DA package)
Production Programmer
MSP-GANG430
–
–
2
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
MSP430F22x2 Device Pinout, DA Package
TEST/SBWTCK
DVCC
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI
2
P2.5/ROSC
3
P1.5/TA0/TMS
DVSS
4
P1.4/SMCLK/TCK
P1.3/TA2
XOUT/P2.7
5
XIN/P2.6
6
P1.2/TA1
RST/NMI/SBWTDIO
P2.0/ACLK/A0
P2.1/TAINCLK/SMCLK/A1
P2.2/TA0/A2
7
P1.1/TA0
8
P1.0/TACLK/ADC10CLK
P2.4/TA2/A4/VREF+/VeREF+
P2.3/TA1/A3/VREF−/VeREF−
P3.7/A7
9
10
11
12
13
14
15
16
17
18
19
P3.0/UCB0STE/UCA0CLK/A5
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
AVSS
P3.6/A6
P3.5/UCA0RXD/UCA0SOMI
P3.4/UCA0TXD/UCA0SIMO
P4.7/TBCLK
AVCC
P4.6/TBOUTH/A15
P4.5/TB2/A14
P4.0/TB0
P4.1/TB1
P4.4/TB1/A13
P4.2/TB2
P4.3/TB0/A12
MSP430F22x4 Device Pinout, DA Package
TEST/SBWTCK
DVCC
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
P1.7/TA2/TDO/TDI
2
P1.6/TA1/TDI
P2.5/ROSC
3
P1.5/TA0/TMS
DVSS
4
P1.4/SMCLK/TCK
XOUT/P2.7
5
P1.3/TA2
XIN/P2.6
6
P1.2/TA1
RST/NMI/SBWTDIO
P2.0/ACLK/A0/OA0I0
P2.1/TAINCLK/SMCLK/A1/OA0O
P2.2/TA0/A2/OA0I1
P3.0/UCB0STE/UCA0CLK/A5
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
AVSS
7
P1.1/TA0
8
P1.0/TACLK/ADC10CLK
P2.4/TA2/A4/VREF+/VeREF+/OA1I0
P2.3/TA1/A3/VREF−/VeREF−/OA1I1/OA1O
P3.7/A7/OA1I2
9
10
11
12
13
14
15
16
17
18
19
P3.6/A6/OA0I2
P3.5/UCA0RXD/UCA0SOMI
P3.4/UCA0TXD/UCA0SIMO
P4.7/TBCLK
AVCC
P4.6/TBOUTH/A15/OA1I3
P4.5/TB2/A14/OA0I3
P4.4/TB1/A13/OA1O
P4.3/TB0/A12/OA0O
P4.0/TB0
P4.1/TB1
P4.2/TB2
Copyright © 2006–2012, Texas Instruments Incorporated
3
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
MSP430F22x2 Device Pinout, RHA Package
39 38 37 36 35 34 33 32
DVSS
XOUT/P2.7
1
2
3
4
5
6
7
8
9
10
30 P1.1/TA0
29 P1.0/TACLK/ADC10CLK
28 P2.4/TA2/A4/VREF+/VeREF+
27 P2.3/TA1/A3/VREF−/VeREF−
26 P3.7/A7
XIN/P2.6
DVSS
RST/NMI/SBWTDIO
P2.0/ACLK/A0
25 P3.6/A6
P2.1/TAINCLK/SMCLK/A1
P2.2/TA0/A2
24 P3.5/UCA0RXD/UCA0SOMI
23 P3.4/UCA0TXD/UCA0SIMO
22 P4.7/TBCLK
P3.0/UCB0STE/UCA0CLK/A5
P3.1/UCB0SIMO/UCB0SDA
21 P4.6/TBOUTH/A15
12 13 14 15 16 17 18 19
4
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
MSP430F22x4 Device Pinout, RHA Package
39 38 37 36 35 34 33 32
DVSS
XOUT/P2.7
1
2
3
4
5
6
7
8
9
10
30 P1.1/TA0
29 P1.0/TACLK/ADC10CLK
28 P2.4/TA2/A4/VREF+/VeREF+/OA1I0
27 P2.3/TA1/A3/VREF−/VeREF−/OA1I1/OA1O
26 P3.7/A7/OA1I2
XIN/P2.6
DVSS
RST/NMI/SBWTDIO
P2.0/ACLK/A0/OA0I0
P2.1/TAINCLK/SMCLK/A1/OA0O
P2.2/TA0/A2/OA0I1
P3.0/UCB0STE/UCA0CLK/A5
P3.1/UCB0SIMO/UCB0SDA
25 P3.6/A6/OA0I2
24 P3.5/UCA0RXD/UCA0SOMI
23 P3.4/UCA0TXD/UCA0SIMO
22 P4.7/TBCLK
21 P4.6/TBOUTH/A15/OA1I3
12 13 14 15 16 17 18 19
Copyright © 2006–2012, Texas Instruments Incorporated
5
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
MSP430F22x4, MSP430F22x2 Device Pinout, YFF Package
A1
B1
C1
D1
E1
F1
G1
A2
B2
C2
D2
E2
F2
G2
A3
B3
C3
D3
E3
F3
G3
A4
B4
A5
B5
C5
D5
E5
F5
G5
A6
B6
C6
D6
E6
F6
G6
A7
B7
C7
D7
E7
F7
G7
C4
TOP VIEW
D4
E4
F4
G4
Package Dimensions
The package dimensions for this YFF package are shown in Table 2. See the package drawing at the end of this
data sheet for more details.
Table 2. YFF Package Dimensions
PACKAGED DEVICES
D
E
MSP430F22x2
MSP430F22x4
3.33 ± 0.03 mm 3.49 ± 0.03 mm
6
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
MSP430F22x2 Functional Block Diagram
VCC
VSS
P1.x/P2.x
2x8
P3.x/P4.x
2x8
XIN
XOUT
ADC10
10−Bit
Ports P1/P2
ACLK
Flash
RAM
Ports P3/P4
Basic Clock
System+
2x8 I/O
Interrupt
capability,
pull−up/down
resistors
SMCLK
32kB
16kB
8kB
1kB
512B
512B
12
2x8 I/O
pull−up/down
resistors
Channels,
Autoscan,
DTC
MCLK
MAB
16MHz
CPU
incl. 16
Registers
MDB
Emulation
(2BP)
Timer_B3
USCI_A0:
UART/LIN,
IrDA, SPI
Watchdog
WDT+
Timer_A3
JTAG
Interface
Brownout
Protection
3 CC
Registers,
Shadow
Reg
3 CC
Registers
USCI_B0:
SPI, I2C
15/16−Bit
Spy−Bi Wire
RST/NMI
MSP430F22x4 Functional Block Diagram
VCC
VSS
P1.x/P2.x
2x8
P3.x/P4.x
2x8
XIN
XOUT
ADC10
10−Bit
Ports P1/P2
ACLK
Flash
RAM
Ports P3/P4
Basic Clock
System+
OA0, OA1
2x8 I/O
Interrupt
capability,
pull−up/down
resistors
SMCLK
32kB
16kB
8kB
1kB
512B
512B
12
2x8 I/O
pull−up/down
resistors
Channels,
Autoscan,
DTC
2 Op Amps
MCLK
MAB
16MHz
CPU
incl. 16
Registers
MDB
Emulation
(2BP)
Timer_B3
USCI_A0:
UART/LIN,
IrDA, SPI
Watchdog
WDT+
Timer_A3
JTAG
Interface
Brownout
Protection
3 CC
Registers,
Shadow
Reg
3 CC
Registers
USCI_B0:
SPI, I2C
15/16−Bit
Spy−Bi Wire
RST/NMI
Copyright © 2006–2012, Texas Instruments Incorporated
7
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Table 3. Terminal Functions, MSP430F22x2
TERMINAL
NO.
DA
I/O
I/O
I/O
DESCRIPTION
NAME
YFF
RHA
General-purpose digital I/O pin
P1.0/TACLK/ADC10CLK
P1.1/TA0
F2
31
32
29
Timer_A, clock signal TACLK input
ADC10, conversion clock
General-purpose digital I/O pin
G2
30
Timer_A, capture: CCI0A input, compare: OUT0 output
BSL transmit
General-purpose digital I/O pin
P1.2/TA1
P1.3/TA2
E2
G1
33
34
31
32
I/O
I/O
Timer_A, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
Timer_A, capture: CCI2A input, compare: OUT2 output
General-purpose digital I/O pin
P1.4/SMCLK/TCK
P1.5/TA0/TMS
F1
E1
E3
D2
A4
35
36
37
38
8
33
34
35
36
6
I/O
I/O
I/O
I/O
I/O
SMCLK signal output
Test Clock input for device programming and test
General-purpose digital I/O pin
Timer_A, compare: OUT0 output
Test Mode Select input for device programming and test
General-purpose digital I/O pin
P1.6/TA1/TDI/TCLK
P1.7/TA2/TDO/TDI(1)
P2.0/ACLK/A0
Timer_A, compare: OUT1 output
Test Data Input or Test Clock Input for programming and test
General-purpose digital I/O pin
Timer_A, compare: OUT2 output
Test Data Output or Test Data Input for programming and test
General-purpose digital I/O pin
ACLK output
ADC10, analog input A0
General-purpose digital I/O pin
Timer_A, clock signal at INCLK
P2.1/TAINCLK/SMCLK/A1
P2.2/TA0/A2
B4
A5
F3
9
7
8
I/O
I/O
I/O
SMCLK signal output
ADC10, analog input A1
General-purpose digital I/O pin
10
29
Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output
ADC10, analog input A2
General-purpose digital I/O pin
Timer_A, capture CCI1B input, compare: OUT1 output
ADC10, analog input A3
P2.3/TA1/A3/VREF-/ VeREF-
27
Negative reference voltage input
General-purpose digital I/O pin
Timer_A, compare: OUT2 output
P2.4/TA2/A4/VREF+/ VeREF+
G3
30
28
I/O
ADC10, analog input A4
Positive reference voltage output or input
General-purpose digital I/O pin
P2.5/ROSC
XIN/P2.6
C2
A2
3
6
40
3
I/O
I/O
Input for external DCO resistor to define DCO frequency
Input terminal of crystal oscillator
General-purpose digital I/O pin
(1) TDO or TDI is selected via JTAG instruction.
8
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Table 3. Terminal Functions, MSP430F22x2 (continued)
TERMINAL
NO.
DA
I/O
DESCRIPTION
NAME
YFF
RHA
Output terminal of crystal oscillator
General-purpose digital I/O pin(2)
XOUT/P2.7
A1
5
2
I/O
General-purpose digital I/O pin
USCI_B0 slave transmit enable
P3.0/UCB0STE/UCA0CLK/
A5
B5
11
9
I/O
USCI_A0 clock input/output
ADC10, analog input A5
General-purpose digital I/O pin
P3.1/UCB0SIMO/
UCB0SDA
A6
A7
B6
G6
G5
12
13
14
25
26
10
11
12
23
24
I/O
I/O
I/O
I/O
I/O
USCI_B0 SPI mode: slave in/master out
USCI_B0 I2C mode: SDA I2C data
General-purpose digital I/O pin
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
USCI_B0 SPI mode: slave out/master in
USCI_B0 I2C mode: SCL I2C clock
General-purpose digital I/O pin
USCI_B0 clock input/output
USCI_A0 slave transmit enable
General-purpose digital I/O pin
P3.4/UCA0TXD/
UCA0SIMO
USCI_A0 UART mode: transmit data output
USCI_A0 SPI mode: slave in/master out
General-purpose digital I/O pin
P3.5/UCA0RXD/
UCA0SOMI
USCI_A0 UART mode: receive data input
USCI_A0 SPI mode: slave out/master in
General-purpose digital I/O pin
P3.6/A6
F4
G4
D6
D7
E6
27
28
17
18
19
25
26
15
16
17
I/O
I/O
I/O
I/O
I/O
ADC10 analog input A6
General-purpose digital I/O pin
P3.7/A7
ADC10 analog input A7
General-purpose digital I/O pin
P4.0/TB0
P4.1/TB1
P4.2/TB2
Timer_B, capture: CCI0A input, compare: OUT0 output
General-purpose digital I/O pin
Timer_B, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
Timer_B, capture: CCI2A input, compare: OUT2 output
General-purpose digital I/O pin
P4.3/TB0/A12
P4.4/TB1/A13
P4.5/TB2/A14
P4.6/TBOUTH/A15
E7
F7
F6
G7
20
21
22
23
18
19
20
21
I/O
I/O
I/O
I/O
Timer_B, capture: CCI0B input, compare: OUT0 output
ADC10 analog input A12
General-purpose digital I/O pin
Timer_B, capture: CCI1B input, compare: OUT1 output
ADC10 analog input A13
General-purpose digital I/O pin
Timer_B, compare: OUT2 output
ADC10 analog input A14
General-purpose digital I/O pin
Timer_B, switch all TB0 to TB3 outputs to high impedance
ADC10 analog input A15
(2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
Copyright © 2006–2012, Texas Instruments Incorporated
9
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Table 3. Terminal Functions, MSP430F22x2 (continued)
TERMINAL
NO.
DA
I/O
DESCRIPTION
NAME
YFF
RHA
General-purpose digital I/O pin
P4.7/TBCLK
F5
B3
24
7
22
I/O
I
Timer_B, clock signal TBCLK input
Reset or nonmaskable interrupt input
RST/NMI/SBWTDIO
TEST/SBWTCK
5
Spy-Bi-Wire test data input/output during programming and test
Selects test mode for JTAG pins on Port 1. The device protection fuse is
connected to TEST.
D1
1
37
I
Spy-Bi-Wire test clock input during programming and test
C1,
D3,
D4,
DVCC
AVCC
2
38, 39
14
Digital supply voltage
E4, E5
C6,
C7,
D5
16
Analog supply voltage
Digital ground reference
A3,
B1,
B2,
C3,
C4
DVSS
4
1, 4
B7,
C5
AVSS
15
13
Analog ground reference
QFN Pad
NA
NA
Pad
NA
QFN package pad; connection to DVSS recommended.
10
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Table 4. Terminal Functions, MSP430F22x4
TERMINAL
NO.
DA
I/O
I/O
I/O
DESCRIPTION
NAME
YFF
RHA
General-purpose digital I/O pin
P1.0/TACLK/ADC10CLK
P1.1/TA0
F2
31
32
29
Timer_A, clock signal TACLK input
ADC10, conversion clock
General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: OUT0 output
BSL transmit
G2
30
General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
Timer_A, capture: CCI2A input, compare: OUT2 output
General-purpose digital I/O pin
SMCLK signal output
P1.2/TA1
P1.3/TA2
E2
G1
33
34
31
32
I/O
I/O
P1.4/SMCLK/TCK
P1.5/TA0/TMS
F1
E1
E3
D2
35
36
37
38
33
34
35
36
I/O
I/O
I/O
I/O
Test Clock input for device programming and test
General-purpose digital I/O pin
Timer_A, compare: OUT0 output
Test Mode Select input for device programming and test
General-purpose digital I/O pin
Timer_A, compare: OUT1 output
Test Data Input or Test Clock Input for programming and test
General-purpose digital I/O pin
Timer_A, compare: OUT2 output
Test Data Output or Test Data Input for programming and test
General-purpose digital I/O pin
ACLK output
P1.6/TA1/TDI/TCLK
P1.7/TA2/TDO/TDI(1)
P2.0/ACLK/A0/OA0I0
A4
B4
A5
8
9
6
7
8
I/O
I/O
I/O
ADC10, analog input A0
OA0, analog input IO
General-purpose digital I/O pin
Timer_A, clock signal at INCLK
SMCLK signal output
P2.1/TAINCLK/SMCLK/
A1/OA0O
ADC10, analog input A1
OA0, analog output
General-purpose digital I/O pin
Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output
ADC10, analog input A2
P2.2/TA0/A2/OA0I1
10
OA0, analog input I1
General-purpose digital I/O pin
Timer_A, capture CCI1B input, compare: OUT1 output
ADC10, analog input A3
P2.3/TA1/A3/ VREF-/VeREF-
OA1I1/OA1O
/
F3
29
27
I/O
Negative reference voltage input
OA1, analog input I1
OA1, analog output
(1) TDO or TDI is selected via JTAG instruction.
Copyright © 2006–2012, Texas Instruments Incorporated
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Table 4. Terminal Functions, MSP430F22x4 (continued)
TERMINAL
NO.
DA
I/O
DESCRIPTION
NAME
YFF
RHA
General-purpose digital I/O pin
Timer_A, compare: OUT2 output
ADC10, analog input A4
P2.4/TA2/A4/
VREF+/VeREF+/OA1I0
G3
30
28
I/O
Positive reference voltage output or input
OA1, analog input I/O
General-purpose digital I/O pin
P2.5/ROSC
XIN/P2.6
C2
A2
A1
3
6
5
40
3
I/O
I/O
I/O
Input for external DCO resistor to define DCO frequency
Input terminal of crystal oscillator
General-purpose digital I/O pin
Output terminal of crystal oscillator
General-purpose digital I/O pin(2)
General-purpose digital I/O pin
XOUT/P2.7
2
USCI_B0 slave transmit enable
USCI_A0 clock input/output
P3.0/UCB0STE/UCA0CLK/
A5
B5
11
9
I/O
ADC10, analog input A5
General-purpose digital I/O pin
P3.1/UCB0SIMO/
UCB0SDA
A6
A7
B6
G6
G5
F4
G4
12
13
14
25
26
27
28
10
11
12
23
24
25
26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
USCI_B0 SPI mode: slave in/master out
USCI_B0 I2C mode: SDA I2C data
General-purpose digital I/O pin
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
USCI_B0 SPI mode: slave out/master in
USCI_B0 I2C mode: SCL I2C clock
General-purpose digital I/O pin
USCI_B0 clock input/output
USCI_A0 slave transmit enable
General-purpose digital I/O pin
P3.4/UCA0TXD/
UCA0SIMO
USCI_A0 UART mode: transmit data output
USCI_A0 SPI mode: slave in/master out
General-purpose digital I/O pin
P3.5/UCA0RXD/
UCA0SOMI
USCI_A0 UART mode: receive data input
USCI_A0 SPI mode: slave out/master in
General-purpose digital I/O pin
P3.6/A6/OA0I2
P3.7/A7/OA1I2
ADC10 analog input A6
OA0 analog input I2
General-purpose digital I/O pin
ADC10 analog input A7
OA1 analog input I2
General-purpose digital I/O pin
P4.0/TB0
P4.1/TB1
P4.2/TB2
D6
D7
E6
17
18
19
15
16
17
I/O
I/O
I/O
Timer_B, capture: CCI0A input, compare: OUT0 output
General-purpose digital I/O pin
Timer_B, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
Timer_B, capture: CCI2A input, compare: OUT2 output
(2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
12
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MSP430F22x4
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SLAS504G –JULY 2006–REVISED AUGUST 2012
Table 4. Terminal Functions, MSP430F22x4 (continued)
TERMINAL
NO.
DA
I/O
DESCRIPTION
NAME
YFF
RHA
General-purpose digital I/O pin
Timer_B, capture: CCI0B input, compare: OUT0 output
ADC10 analog input A12
P4.3/TB0/A12/OA0O
P4.4/TB1/A13/OA1O
P4.5/TB2/A14/OA0I3
P4.6/TBOUTH/A15/OA1I3
E7
F7
F6
G7
20
21
22
23
18
I/O
OA0 analog output
General-purpose digital I/O pin
Timer_B, capture: CCI1B input, compare: OUT1 output
ADC10 analog input A13
19
20
21
I/O
I/O
I/O
OA1 analog output
General-purpose digital I/O pin
Timer_B, compare: OUT2 output
ADC10 analog input A14
OA0 analog input I3
General-purpose digital I/O pin
Timer_B, switch all TB0 to TB3 outputs to high impedance
ADC10 analog input A15
OA1 analog input I3
General-purpose digital I/O pin
Timer_B, clock signal TBCLK input
Reset or nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
P4.7/TBCLK
F5
B3
24
7
22
5
I/O
I
RST/NMI/SBWTDIO
Selects test mode for JTAG pins on Port 1. The device protection fuse is
connected to TEST.
TEST/SBWTCK
D1
1
37
I
Spy-Bi-Wire test clock input during programming and test
C1,
D3,
D4,
DVCC
AVCC
2
38, 39
14
Digital supply voltage
E4, E5
C6,
C7,
D5
16
Analog supply voltage
Digital ground reference
A3,
B1,
B2,
C3,
C4
DVSS
4
1, 4
B7,
C5
AVSS
15
13
Analog ground reference
QFN Pad
NA
NA
Pad
NA
QFN package pad; connection to DVSS recommended.
Copyright © 2006–2012, Texas Instruments Incorporated
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SHORT-FORM DESCRIPTION
Program Counter
Stack Pointer
PC/R0
CPU
The MSP430™ CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
R4
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-to-
register operation execution time is one cycle of the
CPU clock.
R5
R6
R7
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator respectively. The remaining
registers are general-purpose registers.
R8
R9
Peripherals are connected to the CPU using data,
address, and control buses and can be handled with
all instructions.
R10
R11
Instruction Set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 5 shows examples of the three types of
instruction formats; Table 6 shows the address
modes.
R12
R13
R14
R15
Table 5. Instruction Word Formats
INSTRUCTION FORMAT
Dual operands, source-destination
EXAMPLE
ADD R4,R5
CALL R8
JNE
OPERATION
R4 + R5 → R5
Single operands, destination only
PC → (TOS), R8 → PC
Relative jump, unconditional/conditional
Jump-on-equal bit = 0
Table 6. Address Mode Descriptions
(1)
(2)
ADDRESS MODE
Register
S
D
SYNTAX
MOV Rs,Rd
EXAMPLE
OPERATION
R10 → R11
✓
✓
MOV R10,R11
Indexed
✓
✓
✓
✓
✓
✓
✓
MOV X(Rn),Y(Rm)
MOV EDE,TONI
MOV &MEM,&TCDAT
MOV @Rn,Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
M(R10) → M(Tab+R6)
Symbolic (PC relative)
Absolute
Indirect
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
M(R10) → R11
R10 + 2 → R10
Indirect autoincrement
Immediate
✓
✓
MOV @Rn+,Rm
MOV #X,TONI
#45 → M(TONI)
(1) S = source
(2) D = destination
14
Copyright © 2006–2012, Texas Instruments Incorporated
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MSP430F22x4
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Operating Modes
The MSP430 microcontrollers have one active mode and five software-selectable low-power modes of operation.
An interrupt event can wake up the device from any of the five low-power modes, service the request, and
restore back to the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
•
Active mode (AM)
All clocks are active.
Low-power mode 0 (LPM0)
–
•
–
–
CPU is disabled.
ACLK and SMCLK remain active. MCLK is disabled.
•
•
Low-power mode 1 (LPM1)
–
–
CPU is disabled ACLK and SMCLK remain active. MCLK is disabled.
DCO dc-generator is disabled if DCO not used in active mode.
Low-power mode 2 (LPM2)
–
–
–
–
CPU is disabled.
MCLK and SMCLK are disabled.
DCO dc-generator remains enabled.
ACLK remains active.
•
•
Low-power mode 3 (LPM3)
–
–
–
–
CPU is disabled.
MCLK and SMCLK are disabled.
DCO dc-generator is disabled.
ACLK remains active.
Low-power mode 4 (LPM4)
–
–
–
–
–
CPU is disabled.
ACLK is disabled.
MCLK and SMCLK are disabled.
DCO dc-generator is disabled.
Crystal oscillator is stopped.
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Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed), the
CPU goes into LPM4 immediately after power up.
Table 7. Interrupt Vector Addresses
SYSTEM
INTERRUPT
INTERRUPT SOURCE
INTERRUPT FLAG
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog
PORIFG
RSTIFG
WDTIFG
KEYV(2)
Reset
0FFFEh
31, highest
Flash key violation
PC out-of-range(1)
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
(non)-maskable,
(non)-maskable,
(non)-maskable
0FFFCh
30
ACCVIFG(2)(3)
Timer_B3
TBCCR0 CCIFG(4)
maskable
0FFFAh
0FFF8h
29
28
TBCCR1 and TBCCR2 CCIFGs,
TBIFG(2)(4)
Timer_B3
maskable
0FFF6h
0FFF4h
0FFF2h
27
26
25
Watchdog Timer
Timer_A3
WDTIFG
maskable
maskable
TACCR0 CCIFG (see Note 3)
TACCR1 CCIFG
TACCR2 CCIFG
TAIFG(2)(4)
Timer_A3
maskable
0FFF0h
24
USCI_A0/USCI_B0 Receive
USCI_A0/USCI_B0 Transmit
ADC10
UCA0RXIFG, UCB0RXIFG(2)
UCA0TXIFG, UCB0TXIFG(2)
ADC10IFG(4)
maskable
maskable
maskable
0FFEEh
0FFECh
0FFEAh
0FFE8h
23
22
21
20
I/O Port P2
(eight flags)
P2IFG.0 to P2IFG.7(2)(4)
P1IFG.0 to P1IFG.7(2)(4)
maskable
maskable
0FFE6h
0FFE4h
19
18
I/O Port P1
(eight flags)
0FFE2h
0FFE0h
17
16
15
(5)
(6)
0FFDEh
0FFDCh to 0FFC0h
14 to 0, lowest
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address range.
(2) Multiple source flags
(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
(4) Interrupt flags are located in the module.
(5) This location is used as bootstrap loader security key (BSLSKEY).
A 0AA55h at this location disables the BSL completely.
A zero (0h) disables the erasure of the flash if an invalid password is supplied.
(6) The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
16
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MSP430F22x4
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Special Function Registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw
Bit can be read and written.
rw-0, 1
rw-(0), (1)
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device.
Table 8. Interrupt Enable 1
Address
00h
7
6
5
4
3
2
1
0
ACCVIE
rw-0
NMIIE
rw-0
OFIE
rw-0
WDTIE
rw-0
WDTIE
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval
timer mode.
OFIE
Oscillator fault interrupt enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
NMIIE
ACCVIE
Table 9. Interrupt Enable 2
Address
7
6
5
4
3
2
1
0
01h
UCB0TXIE
rw-0
UCB0RXIE
rw-0
UCA0TXIE
rw-0
UCA0RXIE
rw-0
UCA0RXIE
UCA0TXIE
UCB0RXIE
UCB0TXIE
USCI_A0 receive-interrupt enable
USCI_A0 transmit-interrupt enable
USCI_B0 receive-interrupt enable
USCI_B0 transmit-interrupt enable
Table 10. Interrupt Flag Register 1
Address
02h
7
6
5
4
3
2
1
0
NMIIFG
rw-0
RSTIFG
rw-(0)
PORIFG
rw-(1)
OFIFG
rw-1
WDTIFG
rw-(0)
WDTIFG
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
OFIFG
Flag set on oscillator fault
RSTIFG
PORIFG
NMIIFG
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up.
Power-on reset interrupt flag. Set on VCC power up.
Set via RST/NMI pin
Table 11. Interrupt Flag Register 2
Address
03h
7
6
5
4
3
2
1
0
UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG
rw-1 rw-0 rw-1 rw-0
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
USCI_A0 receive-interrupt flag
USCI_A0 transmit-interrupt flag
USCI_B0 receive-interrupt flag
USCI_B0 transmit-interrupt flag
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Memory Organization
Table 12. Memory Organization
MSP430F223x
MSP430F225x
MSP430F227x
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
8KB Flash
0FFFFh-0FFC0h
0FFFFh-0E000h
16KB Flash
0FFFFh-0FFC0h
0FFFFh-0C000h
32KB Flash
0FFFFh-0FFC0h
0FFFFh-08000h
Size
Flash
256 Byte
010FFh-01000h
256 Byte
010FFh-01000h
256 Byte
010FFh-01000h
Information memory
Boot memory
RAM
Size
ROM
1KB
0FFFh-0C00h
1KB
0FFFh-0C00h
1KB
0FFFh-0C00h
512 Byte
03FFh-0200h
512 Byte
03FFh-0200h
1KB
05FFh-0200h
Size
16-bit
8-bit
8-bit SFR
01FFh-0100h
0FFh-010h
0Fh-00h
01FFh-0100h
0FFh-010h
0Fh-00h
01FFh-0100h
0FFh-010h
0Fh-00h
Peripherals
Bootstrap Loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap
Loader User’s Guide (SLAU319).
Table 13. BSL Function Pins
BSL FUNCTION
Data transmit
Data receive
DA PACKAGE PINS
32 - P1.1
RHA PACKAGE PINS
30 - P1.1
YFF PACKAGE PINS
G3 - P1.1
10 - P2.2
8 - P2.2
A5 - P2.2
Flash Memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
•
Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
•
•
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
•
Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It
can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is
required.
18
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator, an internal digitally-controlled oscillator (DCO), and
a high-frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low
system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in
less than 1 µs. The basic clock module provides the following clock signals:
•
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, or the internal very-
low-power LF oscillator.
•
•
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
Table 14. DCO Calibration Data
(Provided From Factory in Flash Information Memory Segment A)
DCO FREQUENCY
CALIBRATION REGISTER
CALBC1_1MHZ
SIZE
byte
byte
byte
byte
byte
byte
byte
byte
ADDRESS
010FFh
010FEh
010FDh
010FCh
010FBh
010FAh
010F9h
010F8h
1 MHz
CALDCO_1MHZ
CALBC1_8MHZ
8 MHz
12 MHz
16 MHz
CALDCO_8MHZ
CALBC1_12MHZ
CALDCO_12MHZ
CALBC1_16MHZ
CALDCO_16MHZ
Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
Digital I/O
There are four 8-bit I/O ports implemented—ports P1, P2, P3, and P4:
•
•
•
•
•
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt condition is possible.
Edge-selectable interrupt input capability for all eight bits of port P1 and P2.
Read/write access to port-control registers is supported by all instructions.
Each I/O has an individually programmable pullup/pulldown resistor.
Because there are only three I/O pins implemented from port P2, bits [5:1] of all port P2 registers read as 0, and
write data is ignored.
Watchdog Timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be disabled or configured as an interval timer and can generate interrupts at
selected time intervals.
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Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 15. Timer_A3 Signal Connections
INPUT PIN NUMBER
RHA
DEVICE
INPUT
SIGNAL
MODULE
INPUT
NAME
MODULE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
RHA
MODULE
BLOCK
DA
YFF
DA
YFF
31 - P1.0
29 - P1.0
F2 - P1.0
TACLK
ACLK
SMCLK
TAINCLK
TA0
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
CCR0
CCR1
CCR2
NA
9 - P2.1
32 - P1.1
10 - P2.2
7 - P2.1
30 - P1.1
8 - P2.2
B4 - P2.1
G2 - P1.1
A5 - P2.2
TA0
TA1
TA2
32 - P1.1
10 - P2.2
36 - P1.5
30 - P1.1
8 - P2.2
G2 - P1.1
A5 - P2.2
E1 - P1.5
TA0
VSS
34 - P1.5
VCC
VCC
33 - P1.2
29 - P2.3
31 - P1.2
27 - P2.3
E2 - P1.2
F3 - P2.3
TA1
CCI1A
CCI1B
GND
33 - P1.2
29 - P2.3
37 - P1.6
31 - P1.2
27 - P2.3
35 - P1.6
E2 - P1.2
F3 - P2.3
E3 - P1.6
TA1
VSS
VCC
VCC
34 - P1.3
32 - P1.3
G1 - P1.3
TA2
CCI2A
34 - P1.3
30 - P2.4
38 - P1.7
32 - P1.3
28 - P2.4
36 - P1.7
G1 - P1.3
G3 - P2.4
D2 - P1.7
ACLK
(internal)
CCI2B
VSS
VCC
GND
VCC
20
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MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Timer_B3
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 16. Timer_B3 Signal Connections
INPUT PIN NUMBER
RHA
DEVICE
INPUT
SIGNAL
MODULE
INPUT
NAME
MODULE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
RHA
MODULE
BLOCK
DA
YFF
DA
YFF
24 - P4.7
22 - P4.7
F5 - P4.7
TBCLK
ACLK
SMCLK
TBCLK
TB0
TBCLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
CCR0
CCR1
CCR2
NA
24 - P4.7
17 - P4.0
20 - P4.3
22 - P4.7
15 - P4.0
18 - P4.3
F5 - P4.7
D6 - P4.0
E7 - P4.3
TB0
TB1
TB2
17 - P4.0
20 - P4.3
15 - P4.0
18 - P4.3
D6 - P4.0
E7 - P4.3
TB0
VSS
VCC
VCC
18 - P4.1
21 - P4.4
16 - P4.1
19 - P4.4
D7 - P4.1
F7 - P4.4
TB1
CCI1A
CCI1B
GND
18 - P4.1
21 - P4.4
16 - P4.1
19 - P4.4
D7 - P4.1
F7 - P4.4
TB1
VSS
VCC
VCC
19 - P4.2
17 - P4.2
E6 - P4.2
TB2
CCI2A
19 - P4.2
22 - P4.5
17 - P4.2
20 - P4.5
E6 - P4.2
F6 - P4.5
ACLK
(internal)
CCI2B
VSS
VCC
GND
VCC
Universal Serial Communications Interface (USCI)
The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols such as UART,
enhanced UART with automatic baudrate detection (LIN), and IrDA.
USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.
USCI_B0 provides support for SPI (3 or 4 pin) and I2C.
ADC10
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion
result handling allowing ADC samples to be converted and stored without any CPU intervention.
Copyright © 2006–2012, Texas Instruments Incorporated
21
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Operational Amplifier (OA) (MSP430F22x4 only)
The MSP430F22x4 has two configurable low-current general-purpose operational amplifiers. Each OA input and
output terminal is software-selectable and offer a flexible choice of connections for various applications. The OA
op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion.
Table 17. OA0 Signal Connections
ANALOG INPUT PIN NUMBER
DEVICE INPUT SIGNAL
MODULE INPUT NAME
DA
RHA
6 - A0
YFF
8 - A0
B4 - A0
B5 - A2
B5 - A2
F4 - A6
F6 - A14
OA0I0
OA0I1
OA0I1
OA0I2
OA0I3
OAxI0
OA0I1
OAxI1
OAxIA
OAxIB
10 - A2
10 - A2
27 - A6
22 - A14
8 - A2
8 - A2
25 - A6
20 - A14
Table 18. OA1 Signal Connections
ANALOG INPUT PIN NUMBER
DEVICE INPUT SIGNAL
MODULE INPUT NAME
DA
RHA
28 - A4
8 - A2
YFF
30 - A4
10 - A2
29 - A3
28 - A7
23 - A15
G3 - A4
B5 - A2
F3 - A3
G4 - A7
G7 - A15
OA1I0
OA0I1
OA1I1
OA1I2
OA1I3
OAxI0
OA0I1
OAxI1
OAxIA
OAxIB
27 - A3
26 - A7
21 - A15
22
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Peripheral File Map
Table 19. Peripherals With Word Access
MODULE
ADC10
REGISTER NAME
SHORT NAME
ADDRESS
OFFSET
ADC data transfer start address
ADC memory
ADC10SA
ADC10MEM
ADC10CTL1
ADC10CTL0
ADC10AE0
ADC10AE1
ADC10DTC1
ADC10DTC0
TBCCR2
TBCCR1
TBCCR0
TBR
1BCh
1B4h
ADC control register 1
ADC control register 0
ADC analog enable 0
ADC analog enable 1
ADC data transfer control register 1
ADC data transfer control register 0
Capture/compare register
Capture/compare register
Capture/compare register
Timer_B register
1B2h
1B0h
04Ah
04Bh
049h
048h
Timer_B
0196h
0194h
0192h
0190h
0186h
0184h
0182h
0180h
011Eh
0176h
0174h
0172h
0170h
0166h
0164h
0162h
0160h
012Eh
012Ch
012Ah
0128h
0120h
Capture/compare control
Capture/compare control
Capture/compare control
Timer_B control
TBCCTL2
TBCCTL1
TBCCTL0
TBCTL
Timer_B interrupt vector
Capture/compare register
Capture/compare register
Capture/compare register
Timer_A register
TBIV
Timer_A
TACCR2
TACCR1
TACCR0
TAR
Capture/compare control
Capture/compare control
Capture/compare control
Timer_A control
TACCTL2
TACCTL1
TACCTL0
TACTL
Timer_A interrupt vector
Flash control 3
TAIV
Flash Memory
FCTL3
Flash control 2
FCTL2
Flash control 1
FCTL1
Watchdog Timer+
Watchdog/timer control
WDTCTL
Copyright © 2006–2012, Texas Instruments Incorporated
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MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Table 20. Peripherals With Byte Access
MODULE
REGISTER NAME
SHORT NAME
ADDRESS
OFFSET
0C3h
0C2h
0C1h
0C0h
06Fh
06Eh
06Dh
06Bh
06Ah
069h
068h
011Ah
0118h
067h
066h
065h
064h
063h
062h
061h
060h
05Fh
05Eh
05Dh
053h
058h
057h
056h
011h
01Fh
01Eh
01Dh
01Ch
010h
01Bh
01Ah
019h
018h
02Fh
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
OA1 (MSP430F22x4 only)
OA0 (MSP430F22x4 only)
USCI_B0
Operational Amplifier 1 control register 1
Operational Amplifier 1 control register 1
Operational Amplifier 0 control register 1
Operational Amplifier 0 control register 1
USCI_B0 transmit buffer
USCI_B0 receive buffer
USCI_B0 status
OA1CTL1
OA1CTL0
OA0CTL1
OA0CTL0
UCB0TXBUF
UCB0RXBUF
UCB0STAT
UCB0BR1
UCB0BR0
UCB0CTL1
UCB0CTL0
UCB0SA
UCB0OA
UCA0TXBUF
UCA0RXBUF
UCA0STAT
UCA0MCTL
UCA0BR1
UCA0BR0
UCA0CTL1
UCA0CTL0
UCA0IRRCTL
UCA0IRTCTL
UCA0ABCTL
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
P4REN
USCI_B0 bit rate control 1
USCI_B0 bit rate control 0
USCI_B0 control 1
USCI_B0 control 0
USCI_B0 I2C slave address
USCI_B0 I2C own address
USCI_A0 transmit buffer
USCI_A0 receive buffer
USCI_A0 status
USCI_A0
USCI_A0 modulation control
USCI_A0 baud rate control 1
USCI_A0 baud rate control 0
USCI_A0 control 1
USCI_A0 control 0
USCI_A0 IrDA receive control
USCI_A0 IrDA transmit control
USCI_A0 auto baud rate control
Basic clock system control 3
Basic clock system control 2
Basic clock system control 1
DCO clock frequency control
Port P4 resistor enable
Port P4 selection
Basic Clock System+
Port P4
P4SEL
Port P4 direction
P4DIR
Port P4 output
P4OUT
Port P4 input
P4IN
Port P3
Port P2
Port P3 resistor enable
Port P3 selection
P3REN
P3SEL
Port P3 direction
P3DIR
Port P3 output
P3OUT
Port P3 input
P3IN
Port P2 resistor enable
Port P2 selection
P2REN
P2SEL
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
P2IE
P2IES
P2IFG
Port P2 direction
P2DIR
Port P2 output
P2OUT
Port P2 input
P2IN
24
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Table 20. Peripherals With Byte Access (continued)
MODULE
REGISTER NAME
SHORT NAME
ADDRESS
OFFSET
Port P1
Port P1 resistor enable
P1REN
P1SEL
P1IE
027h
026h
025h
024h
023h
022h
021h
020h
003h
002h
001h
000h
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
P1IES
P1IFG
P1DIR
P1OUT
P1IN
Port P1 output
Port P1 input
Special Function
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
IFG2
IFG1
IE2
IE1
Copyright © 2006–2012, Texas Instruments Incorporated
25
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Absolute Maximum Ratings(1)
Voltage applied at VCC to VSS
-0.3 V to 4.1 V
-0.3 V to VCC + 0.3 V
±2 mA
(2)
Voltage applied to any pin
Diode current at any device terminal
Unprogrammed device
Programmed device
-55°C to 150°C
-55°C to 150°C
(3)
Storage temperature, Tstg
(1) Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditionsis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
(3) Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak
reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
Recommended Operating Conditions(1)(2)
MIN NOM
MAX UNIT
During program
execution
1.8
3.6
3.6
V
VCC
Supply voltage
AVCC = DVCC = VCC
AVSS = DVSS = VSS
During program/erase
flash memory
2.2
V
V
VSS
TA
Supply voltage
0
I version
T version
-40
-40
dc
85
105
Operating free-air temperature
°C
VCC = 1.8 V, Duty cycle = 50% ±10%
(maximum MCLK frequency)(1)(2) VCC = 2.7 V, Duty cycle = 50% ±10%
4.15
Processor frequency
fSYSTEM
dc
12 MHz
16
(see Figure 1)
VCC ≥ 3.3 V, Duty cycle = 50% ±10%
dc
(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend:
16 MHz
Supply voltage range,
during flash memory
programming
12 MHz
Supply voltage range,
during program execution
7.5 MHz
4.15 MHz
1.8 V
2.2 V
2.7 V
3.3 V 3.6 V
Supply Voltage −V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 1. Operating Area
26
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
(1)(2)
Active Mode Supply Current (into DVCC + AVCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX UNIT
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32768 Hz,
2.2 V
270
390
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
Active mode (AM)
current (1 MHz)
IAM,1MHz
µA
3 V
390
240
340
550
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32768 Hz,
2.2 V
3.3 V
Program executes in RAM,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
Active mode (AM)
current (1 MHz)
IAM,1MHz
µA
fMCLK = fSMCLK = fACLK = 32768 Hz/8 =
4096 Hz,
fDCO = 0 Hz,
Program executes in flash,
SELMx = 11, SELS = 1,
DIVMx = DIVSx = DIVAx = 11,
CPUOFF = 0, SCG0 = 1, SCG1 = 0,
OSCOFF = 0
-40°C to
85°C
5
6
9
2.2 V
3 V
105°C
18
µA
10
Active mode (AM)
current (4 kHz)
IAM,4kHz
-40°C to
85°C
105°C
20
85
-40°C to
85°C
60
72
fMCLK = fSMCLK = fDCO(0, 0) ≈ 100 kHz,
fACLK = 0 Hz,
Program executes in flash,
RSELx = 0, DCOx = 0, CPUOFF = 0,
SCG0 = 0, SCG1 = 0, OSCOFF = 1
2.2 V
3 V
105°C
95
Active mode (AM)
current (100 kHz)
IAM,100kHz
µA
-40°C to
85°C
95
105°C
105
(1) All inputs are tied to 0 V or VCC . Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
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MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
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Typical Characteristics - Active-Mode Supply Current (Into DVCC + AVCC)
ACTIVE-MODE CURRENT
vs
ACTIVE-MODE CURRENT
SUPPLY VOLTAGE
TA = 25°C
vs
DCO FREQUENCY
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
5.0
4.0
3.0
2.0
1.0
0.0
f
f
= 16 MHz
= 12 MHz
DCO
DCO
T
= 85 °C
A
T
A
= 25 °C
V
CC
= 3 V
f
= 8 MHz
DCO
T
= 85 °C
= 25 °C
A
T
A
V
CC
= 2.2 V
f
= 1 MHz
DCO
1.5
2.0
2.5
3.0
3.5
4.0
0.0
4.0
8.0
12.0
16.0
V
CC
− Supply Voltage − V
f
DCO
− DCO Frequency − MHz
Figure 2.
Figure 3.
28
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MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
(1)(2)
Low-Power-Mode Supply Currents (Into VCC ) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX UNIT
fMCLK = 0 MHz,
2.2 V
75
90
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0,
SCG1 = 0, OSCOFF = 0
Low-power mode 0
ILPM0,1MHz
µA
(LPM0) current(3)
3 V
90
120
fMCLK = 0 MHz,
fSMCLK = fDCO(0, 0) ≈ 100 kHz,
fACLK = 0 Hz,
RSELx = 0, DCOx = 0,
CPUOFF = 1, SCG0 = 0,
SCG1 = 0, OSCOFF = 1
2.2 V
3 V
37
41
48
Low-power mode 0
(LPM0) current(3)
ILPM0,100kHz
µA
65
-40°C to
85°C
fMCLK = fSMCLK = 0 MHz,
fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0,
SCG1 = 1, OSCOFF = 0
22
25
29
2.2 V
3 V
105°C
31
Low-power mode 2
(LPM2) current(4)
ILPM2
µA
-40°C to
85°C
32
105°C
-40°C
25°C
34
1.4
1.4
3.3
0.7
0.7
2.4
5
2.2 V
3 V
85°C
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 32768 Hz,
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 0
105°C
-40°C
25°C
10
µA
1.5
Low-power mode 3
(LPM3) current(4)
ILPM3,LFXT1
0.9
0.9
2.6
6
1.5
3.8
12
1
85°C
105°C
-40°C
25°C
0.4
0.5
1.8
4.5
0.5
0.6
2.1
5.5
0.1
0.1
1.5
4.5
1
2.2 V
3 V
85°C
2.9
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from internal LF oscillator
(VLO),
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 0
105°C
-40°C
25°C
9
µA
1.2
Low-power mode 3
current, (LPM3)(4)
ILPM3,VLO
1.2
3.3
11
85°C
105°C
-40°C
25°C
0.5
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 1
0.5
µA
3
Low-power mode 4
(LPM4) current(5)
2.2 V/
3 V
ILPM4
85°C
105°C
9
(1) All inputs are tied to 0 V or VCC . Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
(3) Current for brownout and WDT clocked by SMCLK included.
(4) Current for brownout and WDT clocked by ACLK included.
(5) Current for brownout included.
Copyright © 2006–2012, Texas Instruments Incorporated
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MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
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MAX UNIT
Schmitt-Trigger Inputs (Ports P1, P2, P3, P4, and RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
0.45 VCC
1
TYP
0.75 VCC
1.65
VIT+
Positive-going input threshold voltage
2.2 V
3 V
V
1.35
2.25
0.25 VCC
0.55
0.55 VCC
VIT-
Negative-going input threshold voltage
2.2 V
3 V
1.20
1.65
1
V
V
0.75
2.2 V
3 V
0.1
Vhys
Input voltage hysteresis (VIT+ - VIT-)
0.3
1
For pullup: VIN = VSS
For pulldown: VIN = VCC
,
RPull
CI
Pullup/pulldown resistor
Input capacitance
3 V
20
35
5
50
kΩ
VIN = VSS or VCC
pF
Inputs (Ports P1, P2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Port P1, P2: P1.x to P2.x, External trigger
pulse width to set interrupt flag(1)
t(int)
External interrupt timing
2.2 V, 3 V
20
ns
(1) An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set even with trigger signals
shorter than t(int)
.
Leakage Current (Ports P1, P2, P3, and P4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
±50 nA
(1) (2)
Ilkg(Px.y)
High-impedance leakage current
2.2 V, 3 V
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
30
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MSP430F22x4
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SLAS504G –JULY 2006–REVISED AUGUST 2012
Outputs (Ports P1, P2, P3, and P4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
VCC - 0.25
VCC - 0.6
VCC - 0.25
VCC - 0.6
VSS
MAX
VCC
UNIT
(1)
IOH(max) = -1.5 mA
2.2 V
(2)
IOH(max) = -6 mA
VCC
VOH
High-level output voltage
V
IOH(max) = -1.5 mA(1)
IOH(max) = -6 mA(2)
IOL(max) = 1.5 mA(1)
IOL(max) = 6 mA(2)
IOL(max) = 1.5 mA(1)
IOL(max) = 6 mA(2)
VCC
3 V
2.2 V
3 V
VCC
VSS + 0.25
VSS + 0.6
VSS + 0.25
VSS + 0.6
VSS
VOL
Low-level output voltage
V
VSS
VSS
(1) The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop
specified.
(2) The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
Output Frequency (Ports P1, P2, P3, and P4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2.2 V
3 V
MIN
TYP
MAX UNIT
10
P1.4/SMCLK, CL = 20 pF,
fPx.y
Port output frequency (with load)
MHz
12
RL = 1 kΩ against VCC/2(1)(2)
2.2 V
3 V
12
fPort_CLK
Clock output frequency
P2.0/ACLK, P1.4/SMCLK, CL = 20 pF(2)
MHz
16
(1) Alternatively, a resistive divider with two 2-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap
of the divider.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Copyright © 2006–2012, Texas Instruments Incorporated
31
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
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Typical Characteristics - Outputs
One output loaded at a time.
TYPICAL LOW-LEVEL OUTPUT CURRENT
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
25.0
20.0
15.0
10.0
5.0
50.0
40.0
30.0
20.0
10.0
0.0
V
CC
= 2.2 V
T
A
= 25°C
V = 3 V
CC
P4.5
P4.5
T
A
= 25°C
= 85°C
T
A
= 85°C
T
A
0.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OL
− Low-Level Output V oltage − V
V
OL
− Low-Level Output V oltage − V
Figure 4.
Figure 5.
TYPICAL HIGH-LEVEL OUTPUT CURRENT
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
vs
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
0.0
−5.0
0.0
−10.0
−20.0
−30.0
−40.0
−50.0
V
= 2.2 V
V
= 3 V
CC
CC
P4.5
P4.5
−10.0
−15.0
−20.0
−25.0
T
= 85°C
A
T
A
= 85°C
T = 25°C
A
T
A
= 25°C
1.5
0.0
0.5
1.0
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OH
− High-Level Output V oltage − V
V
OH
− High-Level Output V oltage − V
Figure 6.
Figure 7.
32
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
(1) (2)
POR/Brownout Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
0.7 ×
V(B_IT-)
VCC(start)
See Figure 8
dVCC /dt ≤ 3 V/s
V
V(B_IT-)
See Figure 8 through Figure 10
See Figure 8
dVCC /dt ≤ 3 V/s
dVCC /dt ≤ 3 V/s
1.71
210
V
Vhys(B_IT-)
td(BOR)
70
2
130
mV
µs
See Figure 8
2000
Pulse length needed at RST/NMI pin
to accepted reset internally
t(reset)
3 V
µs
+
(1) The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-)
Vhys(B_IT-) is ≤ 1.8 V.
(2) During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-) . The default DCO settings
must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency.
V
CC
V
hys(B_IT−)
V
(B_IT−)
V
CC(start)
1
0
t
d(BOR)
Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage
Copyright © 2006–2012, Texas Instruments Incorporated
33
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Typical Characteristics - POR/Brownout Reset (BOR)
V
t
CC
pw
2
3 V
V
= 3 V
Typical Conditions
CC
1.5
1
V
CC(drop)
0.5
0
0.001
1
1000
1 ns
1 ns
− Pulse Width − µs
t
− Pulse Width − µs
t
pw
pw
Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
V
t
CC
pw
2
1.5
1
3 V
V
= 3 V
CC
Typical Conditions
V
CC(drop)
0.5
t = t
f
r
0
0.001
1
1000
t
t
r
f
t
− Pulse Width − µs
t
− Pulse Width − µs
pw
pw
Figure 10. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
34
Copyright © 2006–2012, Texas Instruments Incorporated
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MSP430F22x4
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SLAS504G –JULY 2006–REVISED AUGUST 2012
Main DCO Characteristics
•
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
•
•
DCO control bits DCOx have a step size as defined by parameter SDCO .
Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
32 × f
× f
DCO(RSEL,DCO)
DCO(RSEL,DCO+1)
f
=
average
MOD × f
+ (32 – MOD) × f
DCO(RSEL,DCO+1)
DCO(RSEL,DCO)
DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
RSELx < 14
VCC
MIN
1.8
TYP
MAX UNIT
3.6
VCC
Supply voltage range
RSELx = 14
2.2
3.6
3.6
V
RSELx = 15
3.0
fDCO(0,0)
fDCO(0,3)
fDCO(1,3)
fDCO(2,3)
fDCO(3,3)
fDCO(4,3)
fDCO(5,3)
fDCO(6,3)
fDCO(7,3)
fDCO(8,3)
fDCO(9,3)
fDCO(10,3)
fDCO(11,3)
fDCO(12,3)
fDCO(13,3)
fDCO(14,3)
fDCO(15,3)
fDCO(15,7)
DCO frequency (0, 0)
DCO frequency (0, 3)
DCO frequency (1, 3)
DCO frequency (2, 3)
DCO frequency (3, 3)
DCO frequency (4, 3)
DCO frequency (5, 3)
DCO frequency (6, 3)
DCO frequency (7, 3)
DCO frequency (8, 3)
DCO frequency (9, 3)
DCO frequency (10, 3)
DCO frequency (11, 3)
DCO frequency (12, 3)
DCO frequency (13, 3)
DCO frequency (14, 3)
DCO frequency (15, 3)
DCO frequency (15, 7)
RSELx = 0, DCOx = 0, MODx = 0
RSELx = 0, DCOx = 3, MODx = 0
RSELx = 1, DCOx = 3, MODx = 0
RSELx = 2, DCOx = 3, MODx = 0
RSELx = 3, DCOx = 3, MODx = 0
RSELx = 4, DCOx = 3, MODx = 0
RSELx = 5, DCOx = 3, MODx = 0
RSELx = 6, DCOx = 3, MODx = 0
RSELx = 7, DCOx = 3, MODx = 0
RSELx = 8, DCOx = 3, MODx = 0
RSELx = 9, DCOx = 3, MODx = 0
RSELx = 10, DCOx = 3, MODx = 0
RSELx = 11, DCOx = 3, MODx = 0
RSELx = 12, DCOx = 3, MODx = 0
RSELx = 13, DCOx = 3, MODx = 0
RSELx = 14, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 7, MODx = 0
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
3 V
0.06
0.07
0.10
0.14
0.20
0.28
0.39
0.54
0.80
1.10
1.60
2.50
3.00
4.30
6.00
8.60
12.0
16.0
0.14 MHz
0.17 MHz
0.20 MHz
0.28 MHz
0.40 MHz
0.54 MHz
0.77 MHz
1.06 MHz
1.50 MHz
2.10 MHz
3.00 MHz
4.30 MHz
5.50 MHz
7.30 MHz
9.60 MHz
13.9 MHz
18.5 MHz
26.0 MHz
3 V
Frequency step between
range RSEL and RSEL+1
SRSEL
SDCO
SRSEL = fDCO(RSEL+1,DCO) /fDCO(RSEL,DCO)
2.2 V, 3 V
1.55 ratio
1.12 ratio
Frequency step between tap
DCO and DCO+1
SDCO = fDCO(RSEL,DCO+1) /fDCO(RSEL,DCO)
Measured at P1.4/SMCLK
2.2 V, 3 V
2.2 V, 3 V
1.05
40
1.08
50
Duty cycle
60
%
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MSP430F22x4
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MAX UNIT
Calibrated DCO Frequencies - Tolerance at Calibration
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
Frequency tolerance at calibration
25°C
3 V
-1
±0.2
+1
%
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
fCAL(1MHz)
fCAL(8MHz)
fCAL(12MHz)
fCAL(16MHz)
1-MHz calibration value
8-MHz calibration value
12-MHz calibration value
16-MHz calibration value
25°C
25°C
25°C
25°C
3 V
3 V
3 V
3 V
0.990
7.920
11.88
15.84
1
8
1.010 MHz
8.080 MHz
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
12 12.12 MHz
16 16.16 MHz
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
Calibrated DCO Frequencies - Tolerance Over Temperature 0°C to 85°C
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
UNIT
1-MHz tolerance over
temperature
0°C to 85°C
3 V
-2.5
±0.5
+2.5
%
8-MHz tolerance over
temperature
0°C to 85°C
0°C to 85°C
0°C to 85°C
3 V
3 V
3 V
-2.5
-2.5
-3
±1.0
±1.0
±2.0
+2.5
+2.5
%
%
%
12-MHz tolerance over
temperature
16-MHz tolerance over
temperature
+3
2.2 V
3 V
0.97
0.975
0.97
7.76
7.8
1
1
1.03
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
fCAL(1MHz)
1-MHz calibration value
8-MHz calibration value
0°C to 85°C
0°C to 85°C
1.025 MHz
1.03
3.6 V
2.2 V
3 V
1
8
8.4
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
fCAL(8MHz)
8
8.2 MHz
8.24
3.6 V
2.2 V
3 V
7.6
8
11.7
11.7
11.7
15.52
12
12
12
12.3
BCSCTL1 = CALBC1_12MHZ,
fCAL(12MHz) 12-MHz calibration value DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
0°C to 85°C
0°C to 85°C
12.3 MHz
12.3
3.6 V
3 V
BCSCTL1 = CALBC1_16MHZ,
fCAL(16MHz) 16-MHz calibration value DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
16 16.48
16 16.48
MHz
3.6 V
15
36
Copyright © 2006–2012, Texas Instruments Incorporated
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MSP430F22x4
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SLAS504G –JULY 2006–REVISED AUGUST 2012
Calibrated DCO Frequencies - Tolerance Over Supply Voltage VCC
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
-3
TYP
±2
MAX UNIT
1-MHz tolerance over VCC
8-MHz tolerance over VCC
12-MHz tolerance over VCC
16-MHz tolerance over VCC
25°C
25°C
25°C
25°C
1.8 V to 3.6 V
1.8 V to 3.6 V
2.2 V to 3.6 V
3 V to 3.6 V
+3
+3
+3
+3
%
%
%
%
-3
±2
-3
±2
-6
±2
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
fCAL(1MHz)
1-MHz calibration value
8-MHz calibration value
25°C
25°C
25°C
25°C
1.8 V to 3.6 V
1.8 V to 3.6 V
2.2 V to 3.6 V
3 V to 3.6 V
0.97
7.76
11.64
15
1
8
1.03 MHz
8.24 MHz
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
fCAL(8MHz)
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
fCAL(12MHz) 12-MHz calibration value
fCAL(16MHz) 16-MHz calibration value
12 12.36 MHz
16 16.48 MHz
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
Calibrated DCO Frequencies - Overall Tolerance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX UNIT
1-MHz tolerance
overall
I: -40°C to 85°C
T: -40°C to 105°C
1.8 V to 3.6 V
-5
±2
±2
±2
±3
+5
+5
+5
+6
%
%
%
%
8-MHz tolerance
overall
I: -40°C to 85°C
T: -40°C to 105°C
1.8 V to 3.6 V
2.2 V to 3.6 V
3 V to 3.6 V
-5
-5
-6
12-MHz
tolerance overall
I: -40°C to 85°C
T: -40°C to 105°C
16-MHz
tolerance overall
I: -40°C to 85°C
T: -40°C to 105°C
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
1-MHz
calibration value
I: -40°C to 85°C
T: -40°C to 105°C
fCAL(1MHz)
fCAL(8MHz)
fCAL(12MHz)
fCAL(16MHz)
1.8 V to 3.6 V
1.8 V to 3.6 V
2.2 V to 3.6 V
3 V to 3.6 V
0.95
7.6
1
8
1.05 MHz
8.4 MHz
12.6 MHz
17 MHz
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
8-MHz
calibration value
I: -40°C to 85°C
T: -40°C to 105°C
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
12-MHz
calibration value
I: -40°C to 85°C
T: -40°C to 105°C
11.4
15
12
16
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
16-MHz
calibration value
I: -40°C to 85°C
T: -40°C to 105°C
Copyright © 2006–2012, Texas Instruments Incorporated
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MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
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Typical Characteristics - Calibrated 1-MHz DCO Frequency
CALIBRATED 1-MHz FREQUENCY
CALIBRATED 1-MHz FREQUENCY
vs
vs
TEMPERATURE
SUPPLY VOLTAGE
1.03
1.02
1.01
1.00
0.99
0.98
0.97
1.03
1.02
1.01
1.00
0.99
0.98
0.97
V
V
= 1.8 V
= 2.2 V
CC
T
= 105 °C
A
T
= 85 °C
A
CC
V
CC
= 3.0 V
T
= 25 °C
A
T
A
= −40°C
V
CC
= 3.6 V
−50.0 −25.0
0.0
25.0
50.0
75.0 100.0
1.5
2.0
2.5
3.0
3.5
4.0
T
A
− Temperature − °C
V
CC
− Supply Voltage − V
Figure 11.
Figure 12.
38
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Wake-Up From Lower-Power Modes (LPM3/4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ
2
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ
2.2 V, 3 V
1.5
µs
1
DCO clock wake-up time
from LPM3/4
tDCO,LPM3/4
(1)
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ
3 V
1
CPU wake-up time from
LPM3/4
1 / fMCLK
tClock,LPM3/4
+
tCPU,LPM3/4
(2)
(1) The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock
edge observable externally on a clock pin (MCLK or SMCLK).
(2) Parameter applicable only if DCOCLK is used for MCLK.
Typical Characteristics - DCO Clock Wake-Up Time From LPM3/4
CLOCK WAKE-UP TIME FROM LPM3
vs
DCO FREQUENCY
10.00
RSELx = 0...11
RSELx = 12...15
1.00
0.10
0.10
1.00
10.00
DCO Frequency − MHz
Figure 13.
Copyright © 2006–2012, Texas Instruments Incorporated
39
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
(1)
DCO With External Resistor ROSC
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
DCOR = 1,
2.2 V
1.8
fDCO,ROSC
DCO output frequency with ROSC
RSELx = 4, DCOx = 3, MODx = 0,
TA = 25°C
MHz
3 V
1.95
±0.1
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
DT
DV
Temperature drift
Drift with VCC
2.2 V, 3 V
%/°C
%/V
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
2.2 V, 3 V
10
(1) ROSC = 100 kΩ. Metal film resistor, type 0257, 0.6 W with 1% tolerance and TK = ±50 ppm/°C.
Typical Characteristics - DCO With External Resistor ROSC
DCO FREQUENCY
DCO FREQUENCY
vs
ROSC
vs
ROSC
VCC = 2.2 V, TA = 25°C
VCC = 3 V, TA = 25°C
10.00
1.00
0.10
0.01
10.00
1.00
0.10
0.01
RSELx = 4
RSELx = 4
10.00
100.00
1000.00
10000.00
10.00
100.00
1000.00
10000.00
R
OSC
− External Resistor − kW
R
OSC
− External Resistor − kW
Figure 14.
Figure 15.
DCO FREQUENCY
vs
DCO FREQUENCY
vs
TEMPERATURE
VCC = 3 V
SUPPLY VOLTAGE
TA = 25°C
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
R
OSC
= 100k
R
= 100k
OSC
R
R
= 270k
= 1M
R
= 270k
= 1M
OSC
OSC
R
OSC
OSC
−50.0 −25.0
0.0
25.0
50.0
75.0 100.0
2.0
2.5
3.0
3.5
4.0
T
A
− Temperature −
C
V
CC
− Supply Voltage − V
Figure 16.
Figure 17.
40
Copyright © 2006–2012, Texas Instruments Incorporated
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MSP430F22x4
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SLAS504G –JULY 2006–REVISED AUGUST 2012
Crystal Oscillator LFXT1, Low-Frequency Mode(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
LFXT1 oscillator crystal
frequency, LF mode 0, 1
fLFXT1,LF
XTS = 0, LFXT1Sx = 0 or 1
1.8 V to 3.6 V
32768
Hz
LFXT1 oscillator logic level
fLFXT1,LF,logic
square wave input frequency, XTS = 0, LFXT1Sx = 3
LF mode
1.8 V to 3.6 V 10000
32768 50000
Hz
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
500
200
Oscillation allowance for
LF crystals
OALF
kΩ
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
XTS = 0, XCAPx = 0
XTS = 0, XCAPx = 1
XTS = 0, XCAPx = 2
XTS = 0, XCAPx = 3
1
5.5
8.5
11
Integrated effective load
capacitance, LF mode(2)
CL,eff
pF
XTS = 0, Measured at P2.0/ACLK,
fLFXT1,LF = 32768 Hz
Duty cycle, LF mode
2.2 V, 3 V
2.2 V, 3 V
30
10
50
70
%
Oscillator fault frequency,
LF mode(3)
fFault,LF
XTS = 0, LFXT1Sx = 3(4)
10000
Hz
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the crystal that is used.
(3) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(4) Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLO frequency
VLO frequency temperature drift
VLO frequency supply voltage drift
TA
VCC
MIN
TYP
MAX UNIT
-40°C to 85°C
105°C
4
12
20
fVLO
2.2 V, 3 V
kHz
22
I: -40°C to 85°C
T: -40°C to 105°C
(1)
dfVLO/dT
2.2 V, 3 V
0.5
4
%/°C
%/V
(2)
dfVLO/dVCC
25°C
1.8 V to 3.6 V
(1) Calculated using the box method:
I version: [MAX(-40...85°C) - MIN(-40...85°C)]/MIN(-40...85°C)/[85°C - (-40°C)]
T version: [MAX(-40...105°C) - MIN(-40...105°C)]/MIN(-40...105°C)/[105°C - (-40°C)]
(2) Calculated using the box method: [MAX(1.8...3.6 V) - MIN(1.8...3.6 V)]/MIN(1.8...3.6 V)/(3.6 V - 1.8 V)
Copyright © 2006–2012, Texas Instruments Incorporated
41
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
MAX UNIT
Crystal Oscillator LFXT1, High-Frequency Mode(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
LFXT1 oscillator crystal
frequency, HF mode 0
fLFXT1,HF0
fLFXT1,HF1
XTS = 1, LFXT1Sx = 0
XTS = 1, LFXT1Sx = 1
1.8 V to 3.6 V
0.4
1
MHz
MHz
LFXT1 oscillator crystal
frequency, HF mode 1
1.8 V to 3.6 V
1
4
1.8 V to 3.6 V
2.2 V to 3.6 V
3 V to 3.6 V
2
2
10
LFXT1 oscillator crystal
frequency, HF mode 2
fLFXT1,HF2
XTS = 1, LFXT1Sx = 2
12 MHz
2
16
1.8 V to 3.6 V
2.2 V to 3.6 V
3 V to 3.6 V
0.4
0.4
0.4
10
LFXT1 oscillator logic-level
square-wave input frequency, HF XTS = 1, LFXT1Sx = 3
mode
fLFXT1,HF,logic
12 MHz
16
XTS = 1, LFXT1Sx = 0,
fLFXT1,HF = 1 MHz,
CL,eff = 15 pF
2700
800
Oscillation allowance for HF
crystals (see Figure 18 and
Figure 19)
XTS = 1, LFXT1Sx = 1,
fLFXT1,HF = 4 MHz,
CL,eff = 15 pF
OAHF
Ω
XTS = 1, LFXT1Sx = 2,
fLFXT1,HF = 16 MHz,
CL,eff = 15 pF
300
1
Integrated effective load
capacitance, HF mode(2)
CL,eff
XTS = 1(3)
pF
XTS = 1,
Measured at P2.0/ACLK,
fLFXT1,HF = 10 MHz
40
50
60
Duty cycle, HF mode
2.2 V, 3 V
2.2 V, 3 V
%
XTS = 1,
Measured at P2.0/ACLK,
fLFXT1,HF = 16 MHz
XTS = 1, LFXT1Sx = 3(5)
40
30
50
60
fFault,HF
Oscillator fault frequency(4)
300 kHz
(1) To improve EMI on the XT1 oscillator the following guidelines should be observed:
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should
always match the specification of the used crystal.
(3) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(4) Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
(5) Measured with logic-level input frequency, but also applies to operation with crystals.
42
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1)
OSCILLATION ALLOWANCE
vs
OSCILLATOR SUPPLY CURRENT
vs
CRYSTAL FREQUENCY
CL,eff = 15 pF, TA = 25°C
CRYSTAL FREQUENCY
CL,eff = 15 pF, TA = 25°C
800.0
700.0
600.0
500.0
400.0
300.0
200.0
100.0
0.0
100000.00
LFXT1Sx = 3
10000.00
1000.00
100.00
10.00
LFXT1Sx = 3
LFXT1Sx = 2
LFXT1Sx = 2
LFXT1Sx = 1
LFXT1Sx = 1
8.0
0.10
1.00
10.00
100.00
0.0
4.0
12.0
16.0
20.0
Crystal Frequency − MHz
Crystal Frequency − MHz
Figure 18.
Figure 19.
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
2.2 V
10
fTA
Timer_A clock frequency
Timer_A capture timing
External: TACLK, INCLK
Duty cycle = 50% ± 10%
MHz
3 V
16
tTA,cap
TA0, TA1, TA2
2.2 V, 3 V
20
ns
Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
2.2 V
10
fTB
Timer_B clock frequency
Timer_B capture timing
External: TACLK, INCLK
Duty cycle = 50% ± 10%
MHz
3 V
16
tTB,cap
TB0, TB1, TB2
2.2 V, 3 V
20
ns
Copyright © 2006–2012, Texas Instruments Incorporated
43
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
External: UCLK
fUSCI
USCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ± 10%
BITCLK clock frequency
(equals baud rate in MBaud)
fBITCLK
tτ
2.2 V, 3 V
1
MHz
ns
2.2 V
3 V
50
50
150
100
600
600
UART receive deglitch time(1)
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode)(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Figure 20 and Figure 21)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
SMCLK, ACLK
Duty cycle = 50% ± 10%
fUSCI
USCI input clock frequency
fSYSTEM MHz
2.2 V
3 V
110
75
0
tSU,MI
SOMI input data setup time
SOMI input data hold time
SIMO output data valid time
ns
ns
2.2 V
3 V
tHD,MI
0
2.2 V
3 V
30
ns
20
UCLK edge to SIMO valid,
CL = 20 pF
tVALID,MO
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
USCI (SPI Slave Mode)(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Figure 22 and Figure 23)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
tSTE,LEAD
tSTE,LAG
tSTE,ACC
STE lead time, STE low to clock
STE lag time, Last clock to STE high
STE access time, STE low to SOMI data out
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
50
ns
ns
ns
10
50
50
STE disable time, STE high to SOMI high
impedance
tSTE,DIS
tSU,SI
2.2 V, 3 V
ns
ns
2.2 V
3 V
20
15
10
10
SIMO input data setup time
SIMO input data hold time
SOMI output data valid time
2.2 V
3 V
tHD,SI
ns
2.2 V
3 V
75
50
110
ns
UCLK edge to SOMI valid,
CL = 20 pF
tVALID,SO
75
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached slave.
44
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
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SLAS504G –JULY 2006–REVISED AUGUST 2012
1/f
UCxCLK
CKPL=0
CKPL=1
UCLK
t
t
t
LO/HI
LO/HI
SU,MI
t
HD,MI
SOMI
SIMO
t
VALID,MO
Figure 20. SPI Master Mode, CKPH = 0
1/f
UCxCLK
CKPL=0
CKPL=1
UCLK
t
t
LO/HI
LO/HI
t
HD,MI
t
SU,MI
SOMI
SIMO
t
VALID,MO
Figure 21. SPI Master Mode, CKPH = 1
Copyright © 2006–2012, Texas Instruments Incorporated
45
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
t
t
STE,LEAD
STE,LAG
STE
1/f
UCxCLK
CKPL=0
CKPL=1
UCLK
t
t
t
LO/HI
LO/HI
SU,SI
t
HD,SI
SIMO
SOMI
t
t
t
STE,ACC
VALID,SO
STE,DIS
Figure 22. SPI Slave Mode, CKPH = 0
t
t
STE,LEAD
STE,LAG
STE
1/f
UCxCLK
CKPL=0
CKPL=1
UCLK
t
t
LO/HI
LO/HI
t
HD,SI
t
SU,SI
SIMO
SOMI
t
t
t
STE,ACC
VALID,SO
STE,DIS
Figure 23. SPI Slave Mode, CKPH = 1
46
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 24)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
External: UCLK
fUSCI
USCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ± 10%
fSCL
SCL clock frequency
2.2 V, 3 V
2.2 V, 3 V
0
4
400 kHz
µs
f
SCL ≤ 100 kHz
fSCL > 100 kHz
SCL ≤ 100 kHz
fSCL > 100 kHz
tHD,STA
Hold time (repeated) START
0.6
4.7
0.6
0
f
tSU,STA
Setup time for a repeated START
2.2 V, 3 V
µs
tHD,DAT
tSU,DAT
tSU,STO
Data hold time
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V
ns
ns
µs
Data setup time
Setup time for STOP
250
4
50
50
150
100
600
ns
tSP
Pulse width of spikes suppressed by input filter
3 V
600
t
t t
SU,STA HD,STA
HD,STA
SDA
SCL
1/f
SCL
t
SP
t
t
SU,STO
SU,DAT
t
HD,DAT
Figure 24. I2C Mode Timing
Copyright © 2006–2012, Texas Instruments Incorporated
47
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
MAX UNIT
10-Bit ADC, Power Supply and Input Range Conditions(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
Analog supply voltage
range
VCC
VSS = 0 V
2.2
3.6
V
V
All Ax terminals,
Analog inputs selected in
ADC10AE register
Analog input voltage
range(2)
VAx
0
VCC
fADC10CLK = 5 MHz,
ADC10ON = 1, REFON = 0,
2.2 V
3 V
0.52
0.6
1.05
I: -40°C to 85°C
T: -40°C to 105°C
IADC10 ADC10 supply current(3) ADC10SHT0 = 1,
ADC10SHT1 = 0,
mA
mA
1.2
ADC10DIV = 0
fADC10CLK = 5 MHz,
ADC10ON = 0, REF2_5V = 0,
REFON = 1, REFOUT = 0
2.2 V, 3 V
3 V
0.25
0.4
0.4
Reference supply
current, reference buffer
disabled(4)
I: -40°C to 85°C
T: -40°C to 105°C
IREF+
fADC10CLK = 5 MHz,
ADC10ON = 0, REF2_5V = 1,
REFON = 1, REFOUT = 0
0.25
1.1
fADC10CLK = 5 MHz
-40°C to 85°C
105°C
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
1.4
1.8
0.7
0.8
Reference buffer supply
ADC10ON = 0, REFON = 1,
REF2_5V = 0, REFOUT = 1,
ADC10SR = 0
IREFB,0 current with
mA
mA
ADC10SR = 0(4)
fADC10CLK = 5 MHz,
-40°C to 85°C
105°C
0.5
Reference buffer supply
ADC10ON = 0, REFON = 1,
REF2_5V = 0, REFOUT = 1,
ADC10SR = 1
IREFB,1 current with
ADC10SR = 1(4)
Only one terminal Ax selected at
a time
I: -40°C to 85°C
T: -40°C to 105°C
CI
RI
Input capacitance
27
pF
Input MUX ON
resistance
I: -40°C to 85°C
T: -40°C to 105°C
0 V ≤ VAx ≤ VCC
2.2 V, 3 V
2000
Ω
(1) The leakage current is defined in the leakage current table with Px.x/Ax parameter.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR-for valid conversion results.
(3) The internal reference supply current is not included in current consumption parameter IADC10
.
(4) The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
48
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
10-Bit ADC, Built-In Voltage Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VREF+ ≤ 1 mA, REF2_5V = 0
VCC
MIN
2.2
TYP
MAX
UNIT
I
I
I
I
I
Positive built-in
reference analog
supply voltage range
VCC,REF+
VREF+ ≤ 0.5 mA, REF2_5V = 1
VREF+ ≤ 1 mA, REF2_5V = 1
2.8
2.9
V
VREF+ ≤ IVREF+max, REF2_5V = 0
VREF+ ≤ IVREF+max, REF2_5V = 1
2.2 V, 3 V
3 V
1.41
2.35
1.5
2.5
1.59
2.65
±0.5
±1
Positive built-in
reference voltage
VREF+
V
2.2 V
3 V
Maximum VREF+
load current
ILD,VREF+
mA
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≈ 0.75 V,
REF2_5V = 0
2.2 V, 3 V
3 V
±2
±2
VREF+ load
regulation
LSB
ns
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≈ 1.25 V,
REF2_5V = 1
IVREF+ = 100 µA to 900 µA,
Ax ≈ 0.5 x VREF+
ADC10SR = 0
400
VREF+ load
regulation response
time
V
,
3 V
Error of conversion result
≤1 LSB
ADC10SR = 1
2000
Maximum
I
VREF+ ≤ ±1 mA,
CVREF+
TCREF+
tREFON
capacitance at pin
2.2 V, 3 V
2.2 V, 3 V
3.6 V
100
±100
30
pF
ppm/°C
µs
REFON = 1, REFOUT = 1
(1)
VREF+
Temperature
coefficient(2)
IVREF+ = constant with
0 mA ≤ IVREF+ ≤ 1 mA
Settling time of
internal reference
voltage(3)
IVREF+ = 0.5 mA, REF2_5V = 0,
REFON = 0 to 1
IVREF+ = 0.5 mA,
REF2_5V = 0,
REFON = 1,
ADC10SR = 0
ADC10SR = 1
ADC10SR = 0
ADC10SR = 1
1
2.5
2
2.2 V
3 V
REFBURST = 1
Settling time of
tREFBURST
µs
reference buffer(3)
IVREF+ = 0.5 mA,
REF2_5V = 1,
REFON = 1,
4.5
REFBURST = 1
(1) The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA 2/A4/VREF+/ VeREF+ (REFOUT = 1),
must be limited; the reference buffer may become unstable otherwise.
(2) Calculated using the box method:
I temperature: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
T temperature: (MAX(-40 to 105°C) – MIN(-40 to 105°C)) / MIN(-40 to 105°C) / (105°C – (–40°C))
(3) The condition is that the error in a conversion started after tREFON or tRefBuf is less than ±0.5 LSB.
Copyright © 2006–2012, Texas Instruments Incorporated
49
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
MAX UNIT
10-Bit ADC, External Reference(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
VeREF+ > VeREF-
SREF1 = 1, SREF0 = 0
,
1.4
VCC
Positive external reference input
voltage range(2)
VeREF+
V
V
eREF-≤ VeREF+ ≤ VCC - 0.15 V,
1.4
0
3
SREF1 = 1, SREF0 = 1(3)
Negative external reference input
voltage range(4)
VeREF-
VeREF+ > VeREF-
1.2
VCC
±1
V
V
Differential external reference
input voltage range
ΔVeREF = VeREF+ - VeREF-
(5)
ΔVeREF
VeREF+ > VeREF-
1.4
0 V ≤ VeREF+ ≤ VCC
SREF1 = 1, SREF0 = 0
,
IVeREF+
Static input current into VeREF+
Static input current into VeREF-
2.2 V, 3 V
2.2 V, 3 V
µA
µA
0 V ≤ VeREF+ ≤ VCC - 0.15 V ≤ 3 V,
0
SREF1 = 1, SREF0 = 1(3)
IVeREF-
0 V ≤ VeREF-≤ VCC
±1
(1) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) Under this condition, the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply
current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
(4) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(5) The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
10-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
0.45
0.45
TYP
MAX UNIT
ADC10SR = 0
ADC10SR = 1
6.3
ADC10 input clock
frequency
For specified performance of
ADC10 linearity parameters
fADC10CLK
fADC10OSC
2.2 V, 3 V
MHz
1.5
ADC10 built-in oscillator ADC10DIVx = 0, ADC10SSELx = 0,
2.2 V, 3 V
2.2 V, 3 V
3.7
6.3 MHz
frequency
fADC10CLK = fADC10OSC
ADC10 built-in oscillator, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
2.06
3.51
µs
tCONVERT
Conversion time
fADC10CLK from ACLK, MCLK or SMCLK,
13 × ADC10DIVx ×
1 / fADC10CLK
ADC10SSELx ≠ 0
Turn on settling time of
the ADC(1)
tADC10ON
100
ns
(1) The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
50
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
10-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Integral linearity error
Differential linearity error
Offset error
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
±1 LSB
±1 LSB
±1 LSB
EI
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
ED
EO
Source impedance RS < 100 Ω
SREFx = 010, unbuffered external reference,
VeREF+ = 1.5 V
2.2 V
3 V
±1.1
±1.1
±1.1
±1.1
±2
±2
SREFx = 010, unbuffered external reference,
VeREF+ = 2.5 V
±2
EG
Gain error
LSB
±4
SREFx = 011, buffered external reference(1)
VeREF+ = 1.5 V
,
2.2 V
3 V
SREFx = 011, buffered external reference(1)
VeREF+ = 2.5 V
,
±3
±5
SREFx = 010, unbuffered external reference,
VeREF+ = 1.5 V
2.2 V
3 V
SREFx = 010, unbuffered external reference,
VeREF+ = 2.5 V
±2
±5
ET
Total unadjusted error
LSB
±7
SREFx = 011, buffered external reference(1)
VeREF+ = 1.5 V
,
2.2 V
3 V
±2
SREFx = 011, buffered external reference(1)
VeREF+ = 2.5 V
,
±2
±6
(1) The reference buffer offset adds to the gain and total unadjusted error.
(1)
10-Bit ADC, Temperature Sensor and Built-In VMID
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2.2 V
MIN
TYP
40
MAX UNIT
120
µA
Temperature sensor supply
current(1)
REFON = 0, INCHx = 0Ah,
TA = 25°C
ISENSOR
3 V
60
160
TCSENSOR
ADC10ON = 1, INCHx = 0Ah(2)
ADC10ON = 1, INCHx = 0Ah(2)
2.2 V, 3 V
3.44
-100
3.55
3.66 mV/°C
VOffset,Sensor
Sensor offset voltage
100
mV
Temperature sensor voltage at
TA = 105°C (T version only)
1265
1365
1465
Temperature sensor voltage at TA = 85°C
Temperature sensor voltage at TA = 25°C
Temperature sensor voltage at TA = 0°C
1195
985
1295
1085
995
1395
1185
1095
VSENSOR
Sensor output voltage(3)
2.2 V, 3 V
2.2 V, 3 V
mV
895
Sample time required if
channel 10 is selected(4)
ADC10ON = 1, INCHx = 0Ah,
Error of conversion result ≤ 1 LSB
tSENSOR(sample)
IVMID
30
µs
2.2 V
3 V
N/A
N/A
Current into divider at
channel 11(4)
ADC10ON = 1, INCHx = 0Bh
µA
2.2 V
3 V
1.06
1.46
1.1
1.5
1.14
1.54
ADC10ON = 1, INCHx = 0Bh,
VMID
VCC divider at channel 11
V
VMID ≈ 0.5 × VCC
2.2 V
3 V
1400
1220
Sample time required if
channel 11 is selected(5)
ADC10ON = 1, INCHx = 0Bh,
Error of conversion result ≤ 1 LSB
tVMID(sample)
ns
(1) The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high).When REFON = 1, ISENSOR is included in IREF+.When REFON = 0, ISENSOR applies during conversion of the temperature sensor
input (INCH = 0Ah).
(2) The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor ( 273 + T [°C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV]
(3) Results based on characterization and/or production test, not TCSensor or VOffset,sensor
.
(4) No additional current is needed. The VMID is used during sampling.
(5) The on time, tVMID(on), is included in the sampling time, tVMID(sample); no additional on time is needed.
Copyright © 2006–2012, Texas Instruments Incorporated
51
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
MAX UNIT
Operational Amplifier (OA) Supply Specifications (MSP430F22x4 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
VCC
Supply voltage range
2.2
3.6
290
190
80
V
Fast Mode
180
110
50
ICC
Supply current(1)
Medium Mode
Slow Mode
2.2 V, 3 V
2.2 V, 3 V
µA
dB
PSRR Power-supply rejection ratio
Noninverting
70
(1) Corresponding pins configured as OA inputs and outputs, respectively.
Operational Amplifier (OA) Input/Output Specifications (MSP430F22x4 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
-0.1
-5
TYP
MAX
UNIT
VI/P
Input voltage range
VCC - 1.2
V
TA = -40 to +55°C
±0.5
±5
5
20
50
Input leakage
current(1) (2)
Ilkg
TA = +55 to +85°C
TA = +85 to +105°C
Fast Mode
2.2 V, 3 V
-20
-50
nA
50
80
Medium Mode
Slow Mode
fV(I/P) = 1 kHz
140
30
Voltage noise
density, I/P
Vn
nV/√Hz
Fast Mode
Medium Mode
Slow Mode
fV(I/P) = 10 kHz
50
65
VIO
Offset voltage, I/P
2.2 V, 3 V
2.2 V, 3 V
±10
mV
Offset temperature
drift, I/P(3)
±10
µV/°C
Offset voltage drift
with supply, I/P
0.3 V ≤ VIN ≤ VCC - 1.0 V
ΔVCC ≤ ±10%, TA = 25°C
2.2 V, 3 V
2.2 V, 3 V
±1.5
mV/V
V
Fast Mode, ISOURCE ≤ -500 µA
Slow Mode, ISOURCE ≤ -150 µA
Fast Mode, ISOURCE ≤ 500 µA
Slow Mode, ISOURCE ≤ 150 µA
VCC - 0.2
VCC - 0.1
VSS
VCC
VCC
0.2
High-level output
voltage, O/P
VOH
Low-level output
voltage, O/P
VOL
2.2 V, 3 V
V
VSS
0.1
RLoad = 3 kΩ, CLoad = 50 pF,
VO/P(OAx) < 0.2 V
Output resistance(4) RLoad = 3 kΩ, CLoad = 50 pF,
150
150
0.1
70
250
250
4
RO/P(OAx)
2.2 V, 3 V
2.2 V, 3 V
Ω
(see Figure 25)
VO/P(OAx) > VCC - 1.2 V
RLoad = 3 kΩ, CLoad = 50 pF,
0.2 V ≤ VO/P(OAx) ≤ VCC - 0.2 V
Common-mode
rejection ratio
CMRR
Noninverting
dB
(1) ESD damage can degrade input current leakage.
(2) The input bias current is overridden by the input leakage current.
(3) Calculated using the box method
(4) Specification valid for voltage-follower OAx configuration
52
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
R
O/P(OAx)
Max
R
C
Load
I
Load
AV
CC
OAx
2
O/P(OAx)
Min
Load
0.2V
AV
−0.2V
CC
V
AV
OUT
CC
Figure 25. OAx Output Resistance Tests
Operational Amplifier (OA) Dynamic Specifications (MSP430F22x4 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
1.2
0.8
0.3
100
60
MAX UNIT
Fast Mode
SR
Slew rate
Medium Mode
Slow Mode
V/µs
Open-loop voltage gain
Phase margin
dB
deg
dB
φm
CL = 50 pF
CL = 50 pF
Gain margin
20
Noninverting, Fast Mode,
RL = 47 kΩ, CL = 50 pF
2.2
1.4
Gain-bandwidth product
(see Figure 26 and Figure 27)
Noninverting, Medium Mode,
RL = 300 kΩ, CL = 50 pF
GBW
2.2 V, 3 V
MHz
Noninverting, Slow Mode,
RL = 300 kΩ, CL = 50 pF
0.5
10
ten(on) Enable time on
ten(off) Enable time off
ton, noninverting, Gain = 1
2.2 V, 3 V
2.2 V, 3 V
20
1
µs
µs
TYPICAL OPEN-LOOP GAIN
TYPICAL PHASE
vs
vs
FREQUENCY
FREQUENCY
140
120
100
80
0
−50
Fast Mode
Fast Mode
60
−100
−150
−200
−250
40
Medium Mode
20
Medium Mode
0
Slow Mode
−20
−40
−60
−80
Slow Mode
1
10
100
1000
10000
100000
1
10
100
1000
10000
100000
Input Frequency − kHz
Input Frequency − kHz
Figure 26.
Figure 27.
Copyright © 2006–2012, Texas Instruments Incorporated
53
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
MAX UNIT
Operational Amplifier OA Feedback Network, Resistor Network (MSP430F22x4 Only)(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Total resistance of resistor string
Unit resistor of resistor string(2)
TEST CONDITIONS
VCC
MIN
76
TYP
96
6
Rtotal
Runit
128
8
kΩ
kΩ
4.8
(1) A single resistor string is composed of 4 Runit + 4 Runit + 2 Runit + 2 Runit + 1 Runit + 1 Runit + 1 Runit + 1 Runit = 16 Runit = Rtotal
.
(2) For the matching (that is, the relative accuracy) of the unit resistors on a device, see the gain and level specifications of the respective
configurations.
Operational Amplifier (OA) Feedback Network, Comparator Mode (OAFCx = 3) (MSP430F22x4
Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
OAFBRx = 1, OARRIP = 0
OAFBRx = 2, OARRIP = 0
OAFBRx = 3, OARRIP = 0
OAFBRx = 4, OARRIP = 0
OAFBRx = 5, OARRIP = 0
OAFBRx = 6, OARRIP = 0
OAFBRx = 7, OARRIP = 0
OAFBRx = 1, OARRIP = 1
OAFBRx = 2, OARRIP = 1
OAFBRx = 3, OARRIP = 1
OAFBRx = 4, OARRIP = 1
OAFBRx = 5, OARRIP = 1
OAFBRx = 6, OARRIP = 1
OAFBRx = 7, OARRIP = 1
Fast Mode, Overdrive 10 mV
Fast Mode, Overdrive 100 mV
Fast Mode, Overdrive 500 mV
Medium Mode, Overdrive 10 mV
Medium Mode, Overdrive 100 mV
Medium Mode, Overdrive 500 mV
Slow Mode, Overdrive 10 mV
Slow Mode, Overdrive 100 mV
Slow Mode, Overdrive 500 mV
VCC
MIN
0.245
0.495
0.619
TYP
MAX UNIT
0.25 0.255
0.5 0.505
0.625 0.631
N/A(1)
N/A(1)
N/A(1)
N/A(1)
VLevel Comparator level
2.2 V, 3 V
VCC
0.061
0.122
0.184
0.245
0.367
0.495
0.0625 0.065
0.125 0.128
0.1875 0.192
0.25 0.255
0.375 0.383
0.5 0.505
N/A(1)
40
4
3
60
6
tPLH
tPHL
,
Propagation delay
(low-high and high-low)
2.2 V, 3 V
µs
5
160
20
15
(1) The level is not available due to the analog input voltage range of the operational amplifier.
54
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Operational Amplifier (OA) Feedback Network, Noninverting Amplifier Mode (OAFCx = 4)
(MSP430F22x4 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
OAFBRx = 0
VCC
MIN
0.998
1.328
1.985
2.638
3.94
TYP
1
MAX UNIT
1.002
1.340
2.017
2.696
4.06
OAFBRx = 1
OAFBRx = 2
OAFBRx = 3
OAFBRx = 4
OAFBRx = 5
OAFBRx = 6
OAFBRx = 7
1.334
2.001
2.667
4
G
Gain
2.2 V, 3 V
5.22
5.33
7.97
15.8
-60
5.44
7.76
8.18
15
16.6
2.2 V
3 V
THD
tSettle
Total harmonic distortion/nonlinearity
Settling time(1)
All gains
dB
-70
All power modes
2.2 V, 3 V
7
12
µs
(1) The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The
settling time of the amplifier itself might be faster.
Operational Amplifier (OA) Feedback Network, Inverting Amplifier Mode (OAFCx = 6)
(MSP430F22x4 Only)(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
OAFBRx = 1
VCC
MIN
-0.345
-1.023
-1.712
-3.1
TYP
-0.335
-1.002
-1.668
-3
MAX UNIT
-0.325
-0.979
-1.624
-2.9
OAFBRx = 2
OAFBRx = 3
OAFBRx = 4
OAFBRx = 5
OAFBRx = 6
OAFBRx = 7
G
Gain
2.2 V, 3 V
-4.51
-7.37
-16.3
-4.33
-6.97
-14.8
-60
-4.15
-6.57
-13.1
2.2 V
3 V
THD
tSettle
Total harmonic distortion/nonlinearity
Settling time(2)
All gains
dB
-70
All power modes
2.2 V, 3 V
7
12
µs
(1) This includes the 2 OA configuration "inverting amplifier with input buffer". Both OA needs to be set to the same power mode OAPMx.
(2) The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The
settling time of the amplifier itself might be faster.
Copyright © 2006–2012, Texas Instruments Incorporated
55
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.2
TYP
MAX
3.6
476
5
UNIT
V
VCC (PGM/ERASE) Program and erase supply voltage
fFTG
Flash timing generator frequency
Supply current from VCC during program
Supply current from VCC during erase
Cumulative program time(1)
257
kHz
mA
IPGM
2.2 V, 3.6 V
2.2 V, 3.6 V
2.2 V, 3.6 V
2.2 V, 3.6 V
1
1
IERASE
tCPT
7
mA
10
ms
tCMErase
Cumulative mass erase time
20
104
100
ms
Program/Erase endurance
105
cycles
years
tFTG
tFTG
tRetention
tWord
Data retention duration
TJ = 25°C
(2)
Word or byte program time
30
25
(2)
(2)
tBlock, 0
Block program time for first byte or word
Block program time for each additional
byte or word
tBlock, 1-63
18
tFTG
(2)
(2)
(2)
tBlock, End
tMass Erase
tSeg Erase
Block program end-sequence wait time
Mass erase time
6
10593
4819
tFTG
tFTG
tFTG
Segment erase time
(1) The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
(2) These values are hardwired into the flash controller's state machine (tFTG = 1/fFTG).
RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
CPU halted
MIN
MAX UNIT
(1)
V(RAMh)
RAM retention supply voltage
1.6
V
(1) This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
56
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
0
TYP
MAX UNIT
fSBW
Spy-Bi-Wire input frequency
Spy-Bi-Wire low clock pulse length
2.2 V, 3 V
2.2 V, 3 V
20 MHz
tSBW,Low
0.025
15
µs
Spy-Bi-Wire enable time
tSBW,En
tSBW,Ret
2.2 V, 3 V
1
µs
(TEST high to acceptance of first clock edge(1)
)
Spy-Bi-Wire return to normal operation time
TCK input frequency(2)
2.2 V, 3 V
2.2 V
15
0
100
5
µs
MHz
fTCK
3 V
0
10 MHz
90 kΩ
RInternal
Internal pulldown resistance on TEST
2.2 V, 3 V
25
60
(1) Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before
applying the first SBWCLK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
JTAG Fuse(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Supply voltage during fuse-blow condition
Voltage level on TEST for fuse blow
Supply current into TEST during fuse blow
Time to blow fuse
TEST CONDITIONS
TA = 25°C
MIN
2.5
6
MAX UNIT
VCC(FB)
VFB
V
7
100
1
V
IFB
mA
ms
tFB
(1) Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to
bypass mode.
Copyright © 2006–2012, Texas Instruments Incorporated
57
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
APPLICATION INFORMATION
Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger
Pad Logic
P1REN.x
DVSS
DVCC
0
1
1
P1DIR.x
0
1
Direction
0: Input
1: Output
0
1
P1OUT.x
Module X OUT
P1.0/TACLK/ADC10CLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1SEL.x
P1IN.x
EN
D
Module X IN
P1IRQ.x
P1IE.x
EN
Q
Set
P1IFG.x
Interrupt
Edge
Select
P1SEL.x
P1IES.x
Table 21. Port P1 (P1.0 to P1.3) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
P1.0(1)
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
P1.0/TACLK/ADC10CLK
0
Timer_A3.TACLK
ADC10CLK
P1.1(1) (I/O)
0
1
I: 0; O: 1
P1.1/TA0
P1.2/TA1
P1.3/TA2
1
2
3
Timer_A3.CCI0A
Timer_A3.TA0
P1.2(1) (I/O)
0
1
I: 0; O: 1
Timer_A3.CCI1A
Timer_A3.TA1
P1.3(1) (I/O)
0
1
I: 0; O: 1
Timer_A3.CCI2A
Timer_A3.TA2
0
1
(1) Default after reset (PUC/POR)
58
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Port P1 Pin Schematic: P1.4 to P1.6, Input/Output With Schmitt Trigger and In-System Access
Features
Pad Logic
P1REN.x
DVSS
DVCC
0
1
1
P1DIR.x
0
1
Direction
0: Input
1: Output
0
1
P1OUT.x
Module X OUT
P1.4/SMCLK/TCK
P1.5/TA0/TMS
P1.6/TA1/TDI
Bus
Keeper
P1SEL.x
P1IN.x
EN
EN
D
Module X IN
P1IRQ.x
P1IE.x
EN
Q
Set
P1IFG.x
Interrupt
Edge
Select
P1SEL.x
P1IES.x
To JTAG
From JTAG
Table 22. Port P1 (P1.4 to P1.6) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
4-Wire JTAG
P1.4(2) (I/O)
SMCLK
I: 0; O: 1
0
1
X
0
1
X
0
1
X
0
0
1
0
0
1
0
0
1
P1.4/SMCLK/TCK
P1.5/TA0/TMS
4
1
TCK
X
P1.5(2) (I/O)
Timer_A3.TA0
TMS
P1.6(2) (I/O)
Timer_A3.TA1
TDI/TCLK(3)
I: 0; O: 1
5
6
1
X
I: 0; O: 1
P1.6/TA1/TDI/TCLK
(1) X = Don't care
1
X
(2) Default after reset (PUC/POR)
(3) Function controlled by JTAG
Copyright © 2006–2012, Texas Instruments Incorporated
59
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Port P1 Pin Schematic: P1.7, Input/Output With Schmitt Trigger and In-System Access Features
Pad Logic
P1REN.7
DVSS
DVCC
0
1
1
P1DIR.7
0
1
Direction
0: Input
1: Output
0
1
P1OUT.7
Module X OUT
P1.7/TA2/TDO/TDI
Bus
Keeper
P1SEL.7
P1IN.7
EN
EN
D
Module X IN
P1IRQ.7
P1IE.7
EN
Q
Set
P1IFG.7
Interrupt
Edge
Select
P1SEL.7
P1IES.7
To JTAG
From JTAG
From JTAG
From JTAG (TDO)
Table 23. Port P1 (P1.7) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
I: 0; O: 1
P1SEL.x
4-Wire JTAG
P1.7(2) (I/O)
0
1
0
0
1
P1.7/TA2/TDO/TDI
(1) X = Don't care
7
Timer_A3.TA2
TDO/TDI(3)
1
X
X
(2) Default after reset (PUC/POR)
(3) Function controlled by JTAG
60
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Port P2 Pin Schematic: P2.0, P2.2, Input/Output With Schmitt Trigger
Pad Logic
To ADC10
INCHx = y
ADC10AE0.y
P2REN.x
DVSS
DVCC
0
1
1
P2DIR.x
0
1
Direction
0: Input
1: Output
0
1
P2OUT.x
Module X OUT
P2.0/ACLK/A0/OA0I0
P2.2/TA0/A2/OA0I1
Bus
Keeper
P2SEL.x
P2IN.x
EN
EN
D
Module X IN
P2IRQ.x
P2IE.x
EN
Q
Set
P2IFG.x
Interrupt
Edge
Select
P2SEL.x
P2IES.x
+
OA0
−
Table 24. Port P2 (P2.0, P2.2) Pin Functions
CONTROL BITS/SIGNALS(1)
Pin Name (P2.x)
x
y
FUNCTION
P2DIR.x
P2SEL.x
ADC10AE0.y
P2.0(2) (I/O)
I: 0; O: 1
0
1
X
0
1
1
X
0
0
1
0
0
0
1
P2.0/ACLK/A0/OA0I0
0
2
0
ACLK
1
A0/OA0I0(3)
P2.2(2) (I/O)
Timer_A3.CCI0B
Timer_A3.TA0
A2/OA0I1(3)
X
I: 0; O: 1
0
1
X
P2.2/TA0/A2/OA0I1
(1) X = Don't care
2
(2) Default after reset (PUC/POR)
(3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Copyright © 2006–2012, Texas Instruments Incorporated
61
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Port P2 Pin Schematic: P2.1, Input/Output With Schmitt Trigger
Pad Logic
To ADC10
INCHx = 1
ADC10AE0.1
P2REN.1
DVSS
DVCC
0
1
1
P2DIR.1
0
1
Direction
0: Input
1: Output
P2OUT.1
0
1
Module X OUT
P2.1/TAINCLK/SMCLK/
A1/OA0O
Bus
Keeper
P2SEL.1
P2IN.1
EN
EN
D
Module X IN
P2IRQ.1
P2IE.1
EN
Q
Set
P2IFG.1
+
1
OA0
Interrupt
Edge
Select
P2SEL.1
P2IES.1
−
OAADCx
OAFCx
OAPMx
(OAADCx = 10 or OAFCx = 000) and OAPMx> 00
To OA0 Feedback Network
1
Table 25. Port P2 (P2.1) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P2.x)
x
y
FUNCTION
P2DIR.x
I: 0; O: 1
P2SEL.x
ADC10AE0.y
P2.1(2) (I/O)
0
1
1
X
0
0
0
1
Timer_A3.INCLK
SMCLK
A1/OA0O(3)
0
1
X
P2.1/TAINCLK/SMCLK/
A1/OA0O
1
1
(1) X = Don't care
(2) Default after reset (PUC/POR)
(3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
62
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Port P2 Pin Schematic: P2.3, Input/Output With Schmitt Trigger
SREF2
VSS
Pad Logic
0
1
To ADC10 V
R−
To ADC10
INCHx = 3
ADC10AE0.3
P2REN.3
P2DIR.3
DVSS
DVCC
0
1
1
0
1
Direction
0: Input
1: Output
0
1
P2OUT.3
Module X OUT
P2.3/TA1/
A3/VREF−/VeREF−/
OA1I1/OA1O
Bus
Keeper
P2SEL.3
P2IN.3
EN
EN
D
Module X IN
P2IRQ.3
P2IE.3
EN
Q
Set
P2IFG.3
Interrupt
Edge
Select
P2SEL.3
P2IES.3
+
1
OA1
−
OAADCx
OAFCx
OAPMx
(OAADCx = 10 or OAFCx = 000) and OAPMx> 00
To OA1 Feedback Network
1
Copyright © 2006–2012, Texas Instruments Incorporated
63
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Table 26. Port P2 (P2.3) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P2.x)
x
y
FUNCTION
P2DIR.x
P2SEL.x
ADC10AE0.y
P2.3(2) (I/O)
I: 0; O: 1
0
1
1
X
0
0
0
1
Timer_A3.CCI1B
0
1
X
P2.3/TA1/A3/VREF-
/VeREF-/ OA1I1/OA1O
3
3
Timer_A3.TA1
A3/VREF-/VeREF-/OA1I1/OA1O(3)
(1) X = Don't care
(2) Default after reset (PUC/POR)
(3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
64
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Port P2 Pin Schematic: P2.4, Input/Output With Schmitt Trigger
Pad Logic
To/fromADC10
positive reference
To ADC10
INCHx = 4
ADC10AE0.4
P2REN.4
DVSS
DVCC
0
1
1
P2DIR.4
0
1
Direction
0: Input
1: Output
0
1
P2OUT.4
Module X OUT
P2.4/TA2/
A4/VREF+/VeREF+/
OA1I0
Bus
Keeper
P2SEL.4
P2IN.4
EN
EN
D
Module X IN
P2IRQ.4
P2IE.4
EN
Q
Set
P2IFG.4
Interrupt
Edge
Select
P2SEL.4
+
P2IES.4
OA1
−
Table 27. Port P2 (P2.4) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P2.x)
x
y
FUNCTION
P2DIR.x
P2SEL.x
ADC10AE0.y
P2.4(2) (I/O)
I: 0; O: 1
0
1
X
0
0
1
P2.4/TA2/A4/VREF+
VeREF+/ OA1I0
/
4
4
Timer_A3.TA2
A4/VREF+/VeREF+/OA1I0(3)
1
X
(1) X = Don't care
(2) Default after reset (PUC/POR)
(3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Copyright © 2006–2012, Texas Instruments Incorporated
65
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Port P2 Pin Schematic: P2.5, Input/Output With Schmitt Trigger and External ROSC for DCO
Pad Logic
To DCO
DCOR
P2REN.x
DVSS
DVCC
0
1
1
P2DIR.x
0
1
Direction
0: Input
1: Output
0
1
P2OUT.x
Module X OUT
P2.5/ROSC
Bus
Keeper
P2SEL.x
P2IN.x
EN
EN
D
Module X IN
P2IRQ.x
P2IE.x
EN
Q
Set
P2IFG.x
Interrupt
Edge
Select
P2SEL.x
P2IES.x
Table 28. Port P2 (P2.5) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
I: 0; O: 1
P2SEL.x
DCOR
P2.5(2) (I/O)
N/A(3)
0
1
1
X
0
0
0
1
0
1
P2.5/ROSC
5
DVSS
ROSC
X
(1) X = Don't care
(2) Default after reset (PUC/POR)
(3) N/A = Not available or not applicable
66
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger and Crystal Oscillator Input
BCSCTL3.LFXT1Sx = 11
LFXT1 Oscillator
P2.7/XOUT
LFXT1 off
0
1
LFXT1CLK
Pad Logic
P2SEL.7
P2REN.6
DVSS
0
1
1
DVCC
P2DIR.6
0
1
Direction
0: Input
1: Output
0
1
P2OUT.6
Module X OUT
P2.6/XIN
Bus
Keeper
P2SEL.6
P2IN.6
EN
EN
D
Module X IN
P2IRQ.6
P2IE.6
EN
Set
Q
P2IFG.6
P2SEL.6
Interrupt
Edge
Select
P2IES.6
Table 29. Port P2 (P2.6) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
I: 0; O: 1
X
P2SEL.x
P2.6 (I/O)
XIN(2)
0
1
P2.6/XIN
6
(1) X = Don't care
(2) Default after reset (PUC/POR)
Copyright © 2006–2012, Texas Instruments Incorporated
67
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger and Crystal Oscillator Output
BCSCTL3.LFXT1Sx = 11
LFXT1 Oscillator
LFXT1 off
0
1
LFXT1CLK
From P2.6/XIN
P2.6/XIN
Pad Logic
P2SEL.6
P2REN.7
DVSS
0
1
1
DVCC
P2DIR.7
0
1
Direction
0: Input
1: Output
0
1
P2OUT.7
Module X OUT
P2.7/XOUT
Bus
Keeper
P2SEL.7
P2IN.7
EN
EN
D
Module X IN
P2IRQ.7
P2IE.7
EN
Set
Q
P2IFG.7
P2SEL.7
Interrupt
Edge
Select
P2IES.7
Table 30. Port P2 (P2.7) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
I: 0; O: 1
X
P2SEL.x
P2.7 (I/O)
XOUT(2) (3)
0
1
XOUT/P2.7
7
(1) X = Don't care
(2) Default after reset (PUC/POR)
(3) If the pin XOUT/P2.7 is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection to this
pin after reset.
68
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Port P3 Pin Schematic: P3.0, Input/Output With Schmitt Trigger
Pad Logic
To ADC10
INCHx = 5
ADC10AE0.5
P3REN.0
DVSS
DVCC
0
1
1
P3DIR.0
0
1
Direction
0: Input
1: Output
USCI Direction
Control
0
1
P3OUT.0
Module X OUT
P3.0/UCB0STE/UCA0CLK/A5
Bus
Keeper
P3SEL.0
P3IN.0
EN
EN
D
Module X IN
Table 31. Port P3 (P3.0) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P1.x)
x
y
FUNCTION
P3DIR.x
P3SEL.x
ADC10AE0.y
P3.0(2) (I/O)
UCB0STE/UCA0CLK(3) (4)
A5(5)
I: 0; O: 1
0
1
X
0
0
1
P3.0/UCB0STE/
UCA0CLK/A5
0
5
X
X
(1) X = Don't care
(2) Default after reset (PUC/POR)
(3) The pin direction is controlled by the USCI module.
(4) UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI_B0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
(5) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Copyright © 2006–2012, Texas Instruments Incorporated
69
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Port P3 Pin Schematic: P3.1 to P3.5, Input/Output With Schmitt Trigger
Pad Logic
DVSS
P3REN.x
DVSS
DVCC
0
1
1
P3DIR.x
0
1
Direction
0: Input
1: Output
USCI Direction
Control
0
1
P3OUT.x
Module X OUT
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
Bus
Keeper
P3SEL.x
P3IN.x
EN
EN
D
Module X IN
Table 32. Port P3 (P3.1 to P3.5) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P3.x)
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
x
1
2
3
4
5
FUNCTION
P3DIR.x
P3SEL.x
P3.1(2) (I/O)
I: 0; O: 1
0
1
0
1
0
1
0
1
0
1
UCB0SIMO/UCB0SDA(3)
P3.2(2) (I/O)
X
I: 0; O: 1
UCB0SOMI/UCB0SCL(3)
P3.3(2) (I/O)
X
I: 0; O: 1
UCB0CLK/UCA0STE(3) (4)
P3.4(2) (I/O)
X
I: 0; O: 1
X
UCA0TXD/UCA0SIMO(3)
P3.5(2) (I/O)
I: 0; O: 1
X
P3.5/UCA0RXD/UCA0SOMI
(1) X = Don't care
UCA0RXD/UCA0SOMI(3)
(2) Default after reset (PUC/POR)
(3) The pin direction is controlled by the USCI module.
(4) UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI_A0 is forced to
3-wire SPI mode even if 4-wire SPI mode is selected.
70
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Port P3 Pin Schematic: P3.6 to P3.7, Input/Output With Schmitt Trigger
Pad Logic
To ADC10
INCHx = y
ADC10AE0.y
P3REN.x
DVSS
DVCC
0
1
1
P3DIR.x
0
1
Direction
0: Input
1: Output
DVSS
0
1
P3OUT.x
Module X OUT
P3.6/A6/OA0I2
P3.7/A7/OA1I2
Bus
Keeper
P3SEL.x
P3IN.x
EN
EN
D
Module X IN
+
OA0/1
−
Table 33. Port P3 (P3.6, P3.7) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P3.x)
x
6
7
y
FUNCTION
P3DIR.x
P3SEL.x
ADC10AE0.y
P3.6(2) (I/O)
A6/OA0I2(3)
P3.7(2) (I/O)
A7/OA1I2(3)
I: 0; O: 1
0
X
0
0
1
0
1
P3.6/A6/OA0I2
6
7
X
I: 0; O: 1
X
P3.7/A7/OA1I2
X
(1) X = Don't care
(2) Default after reset (PUC/POR)
(3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Copyright © 2006–2012, Texas Instruments Incorporated
71
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Port P4 Pin Schematic: P4.0 to P4.2, Input/Output With Schmitt Trigger
Timer_B OutputTristate Logic
P4.6/TBOUTH/A15/OA1I3
P4SEL.6
Pad Logic
P4DIR.6
ADC10AE1.7
P4REN.x
DVSS
DVCC
0
1
1
P4DIR.x
0
1
Direction
0: Input
1: Output
0
1
P4OUT.x
Module X OUT
P4.0/TB0
P4.1/TB1
P4.2/TB2
Bus
Keeper
P4SEL.x
P4IN.x
EN
EN
D
Module X IN
Table 34. Port P4 (P4.0 to P4.2) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x
P4SEL.x
P4.0(1) (I/O)
I: 0; O: 1
0
1
1
0
1
1
0
1
1
P4.0/TB0
0
1
2
Timer_B3.CCI0A
Timer_B3.TB0
P4.1(1) (I/O)
0
1
I: 0; O: 1
P4.1/TB1
P4.2/TB2
Timer_B3.CCI1A
Timer_B3.TB1
P4.2(1) (I/O)
0
1
I: 0; O: 1
Timer_B3.CCI2A
Timer_B3.TB2
0
1
(1) Default after reset (PUC/POR)
72
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Port P4 Pin Schematic: P4.3 to P4.4, Input/Output With Schmitt Trigger
Timer_B OutputTristate Logic
P4.6/TBOUTH/A15/OA1I3
P4SEL.6
P4DIR.6
ADC10AE1.7
Pad Logic
To ADC10
†
INCHx = 8+y
ADC10AE1.y
P4REN.x
DVSS
DVCC
0
1
1
P4DIR.x
0
1
Direction
0: Input
1: Output
P4OUT.x
0
1
Module X OUT
P4.3/TB0/A12/OA0O
P4.4/TB1/A13/OA1O
Bus
Keeper
P4SEL.x
P4IN.x
EN
EN
D
Module X IN
+
1
OA0/1
−
OAADCx
OAPMx
OAADCx = 01 and OAPMx> 00
To OA0/1 Feedback Network
1
†If OAADCx = 11 and not OAFCx = 000, the ADC input A12 or A13 is internally connected to the OA0 or OA1 output,
respectively, and the connections from the ADC and the operational amplifiers to the pad are disabled.
Copyright © 2006–2012, Texas Instruments Incorporated
73
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Table 35. Port P4 (P4.3 to P4.4) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P4.x)
x
y
FUNCTION
P4DIR.x
P4SEL.x
ADC10AE1.y
P4.3(2) (I/O)
I: 0; O: 1
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
Timer_B3.CCI0B
Timer_B3.TB0
A12/OA0O(3)
P4.4(2) (I/O)
0
P4.3/TB0/A12/OA0O
3
4
1
X
I: 0; O: 1
Timer_B3.CCI1B
Timer_B3.TB1
A13/OA1O(3)
0
1
X
P4.4/TB1/A13/OA1O
(1) X = Don't care
4
5
(2) Default after reset (PUC/POR)
(3) Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
74
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Port P4 Pin Schematic: P4.5, Input/Output With Schmitt Trigger
Timer_B OutputTristate Logic
P4.6/TBOUTH/A15/OA1I3
P4SEL.6
P4DIR.6
ADC10AE1.7
Pad Logic
To ADC10
INCHx = 14
ADC10AE1.6
P4REN.5
DVSS
DVCC
0
1
1
P4DIR.5
0
1
Direction
0: Input
1: Output
P4OUT.5
0
1
Module X OUT
P4.5/TB3/A14/OA0I3
Bus
Keeper
P4SEL.5
P4IN.5
EN
EN
D
Module X IN
+
OA0
−
Table 36. Port P4 (P4.5) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P4.x)
x
y
FUNCTION
P4DIR.x
P4SEL.x
ADC10AE1.y
P4.5(2) (I/O)
I: 0; O: 1
0
1
X
0
0
1
P4.5/TB3/A14/OA0I3
(1) X = Don't care
5
6
Timer_B3.TB2
A14/OA0I3(3)
1
X
(2) Default after reset (PUC/POR)
(3) Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Copyright © 2006–2012, Texas Instruments Incorporated
75
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Port P4 Pin Schematic: P4.6, Input/Output With Schmitt Trigger
Pad Logic
To ADC10
INCHx = 15
ADC10AE1.7
P4REN.6
DVSS
DVCC
0
1
1
P4DIR.6
0
1
Direction
0: Input
1: Output
0
1
P4OUT.6
Module X OUT
P4.6/TBOUTH/
A15/OA1I3
Bus
Keeper
P4SEL.6
P4IN.6
EN
EN
D
Module X IN
+
OA1
−
Table 37. Port P4 (P4.6) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P4.x)
x
y
FUNCTION
P4DIR.x
I: 0; O: 1
P4SEL.x
ADC10AE1.y
P4.6(2) (I/O)
0
1
1
X
0
0
0
1
TBOUTH
DVSS
A15/OA1I3(3)
0
1
P4.6/TBOUTH/A15/OA1I3
(1) X = Don't care
6
7
X
(2) Default after reset (PUC/POR)
(3) Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
76
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Port P4 Pin Schematic: P4.7, Input/Output With Schmitt Trigger
Pad Logic
DVSS
P4REN.x
DVSS
DVCC
0
1
1
P4DIR.x
0
1
Direction
0: Input
1: Output
0
1
P4OUT.x
Module X OUT
P4.7/TBCLK
Bus
Keeper
P4SEL.x
P4IN.x
EN
EN
D
Module X IN
Table 38. Port P4 (Pr.7) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x
P4SEL.x
P4.7(1) (I/O)
I: 0; O: 1
0
1
1
P4.7/TBCLK
7
Timer_B3.TBCLK
DVSS
0
1
(1) Default after reset (PUC/POR)
Copyright © 2006–2012, Texas Instruments Incorporated
77
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
JTAG Fuse Check Mode
MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the
fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care
must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense
currents are terminated.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is
being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode.
After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse
check mode has the potential to be activated.
The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state (see
Figure 28). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
I
TF
I
TEST
Figure 28. Fuse Check Mode Current
NOTE
The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit
bootloader access key is used. Also, see the Bootstrap Loader section for more
information.
78
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
REVISION HISTORY
Literature
Summary
Number
SLAS504
SLAS504A
Preliminary data sheet release
Production data sheet release
Updated specification and added characterization graphs
Updated/corrected port pin schematics
SLAS504B
SLAS504C
SLAS504D
Maximum low-power mode supply current limits decreased
Added note concerning fUCxCLK to USCI SPI parameters
Added Development Tool Support section (page 2)
Changed Tstg for programmed devices from "-40°C to 105°C" to "-55°C to 105°C" (page 23)
Corrected pin names in "Port P3 pin schematic: P3.0" and "Port P3 (P3.0) pin functions" (page 68)
Corrected pin names in "Port P3 pin schematic: P3.1 to P3.5" and "Port P3 (P3.1 to P3.5) pin functions" (page 69)
Corrected signal names in "Port P2 pin schematic: P2.5, input/output" (page 65) (D1)
Corrected values in "x" column in "Port P3 (P3.1 to P3.5) pin functions" (page 69) (D2)
SLAS504E
SLAS504F
Added information for YFF package
Correct signal names for P3.6 and P3.7 in MSP430F22x2 pinouts – DA package, RHA package
Changed Storage temperature range limit in Absolute Maximum Ratings
Corrected Test Conditions in Crystal Oscillator LFXT1, High-Frequency Mode
Corrected signal names in Port P1 (P1.0 to P1.3) Pin Functions
Corrected typo in note 1 on Crystal Oscillator LFXT1, High-Frequency Mode table
SLAS504G
Terminal Functions tables, Corrected description of VREF-/VeREF-pins.
Added note on TCREF+ in 10-Bit ADC, Built-In Voltage Reference.
Copyright © 2006–2012, Texas Instruments Incorporated
79
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
MSP430F2232IDA
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
TSSOP
TSSOP
VQFN
DA
38
38
40
40
49
49
38
38
40
40
38
38
40
40
49
49
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
SNAGCU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
M430F2232
MSP430F2232IDAR
MSP430F2232IRHAR
MSP430F2232IRHAT
MSP430F2232IYFFR
MSP430F2232IYFFT
MSP430F2232TDA
MSP430F2232TDAR
MSP430F2232TRHAR
MSP430F2232TRHAT
MSP430F2234IDA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DA
RHA
RHA
YFF
YFF
DA
2000
2500
250
Green (RoHS
& no Sb/Br)
-40 to 85
M430F2232
Green (RoHS
& no Sb/Br)
-40 to 85
M430
F2232
VQFN
Green (RoHS
& no Sb/Br)
-40 to 85
M430
F2232
DSBGA
DSBGA
TSSOP
TSSOP
VQFN
2500
250
Green (RoHS
& no Sb/Br)
M430F2232
M430F2232
M430F2232T
M430F2232T
Green (RoHS
& no Sb/Br)
SNAGCU
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
SNAGCU
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 85
-40 to 85
-40 to 85
-40 to 85
DA
2000
2500
250
Green (RoHS
& no Sb/Br)
RHA
RHA
DA
Green (RoHS
& no Sb/Br)
M430
F2232T
VQFN
Green (RoHS
& no Sb/Br)
M430
F2232T
TSSOP
TSSOP
VQFN
40
Green (RoHS
& no Sb/Br)
M430F2234
MSP430F2234IDAR
MSP430F2234IRHAR
MSP430F2234IRHAT
MSP430F2234IYFFR
MSP430F2234IYFFT
MSP430F2234TDA
DA
2000
2500
250
Green (RoHS
& no Sb/Br)
M430F2234
RHA
RHA
YFF
YFF
DA
Green (RoHS
& no Sb/Br)
M430
F2234
VQFN
Green (RoHS
& no Sb/Br)
M430
F2234
DSBGA
DSBGA
TSSOP
2500
250
Green (RoHS
& no Sb/Br)
M430F2234
M430F2234
M430F2234T
Green (RoHS
& no Sb/Br)
SNAGCU
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
-40 to 105
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 105
-40 to 105
-40 to 105
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
MSP430F2234TDAR
MSP430F2234TRHAR
MSP430F2234TRHAT
MSP430F2252IDA
ACTIVE
TSSOP
VQFN
DA
38
40
40
38
38
40
40
49
49
38
38
40
40
38
38
40
40
49
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
SNAGCU
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-1-260C-UNLIM
M430F2234T
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
RHA
RHA
DA
2500
250
Green (RoHS
& no Sb/Br)
M430
F2234T
VQFN
Green (RoHS
& no Sb/Br)
M430
F2234T
TSSOP
TSSOP
VQFN
40
Green (RoHS
& no Sb/Br)
M430F2252
MSP430F2252IDAR
MSP430F2252IRHAR
MSP430F2252IRHAT
MSP430F2252IYFFR
MSP430F2252IYFFT
MSP430F2252TDA
MSP430F2252TDAR
MSP430F2252TRHAR
MSP430F2252TRHAT
MSP430F2254IDA
DA
2000
2500
250
Green (RoHS
& no Sb/Br)
-40 to 85
M430F2252
RHA
RHA
YFF
YFF
DA
Green (RoHS
& no Sb/Br)
-40 to 85
M430
F2252
VQFN
Green (RoHS
& no Sb/Br)
-40 to 85
M430
F2252
DSBGA
DSBGA
TSSOP
TSSOP
VQFN
2500
250
Green (RoHS
& no Sb/Br)
M430F2252
M430F2252
M430F2252T
M430F2252T
Green (RoHS
& no Sb/Br)
SNAGCU
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
SNAGCU
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 85
-40 to 85
-40 to 85
-40 to 85
DA
2000
2500
250
Green (RoHS
& no Sb/Br)
RHA
RHA
DA
Green (RoHS
& no Sb/Br)
M430
F2252T
VQFN
Green (RoHS
& no Sb/Br)
M430
F2252T
TSSOP
TSSOP
VQFN
40
Green (RoHS
& no Sb/Br)
M430F2254
MSP430F2254IDAR
MSP430F2254IRHAR
MSP430F2254IRHAT
MSP430F2254IYFFR
DA
2000
2500
250
Green (RoHS
& no Sb/Br)
M430F2254
RHA
RHA
YFF
Green (RoHS
& no Sb/Br)
M430
F2254
VQFN
Green (RoHS
& no Sb/Br)
M430
F2254
DSBGA
2500
Green (RoHS
& no Sb/Br)
M430F2254
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
MSP430F2254IYFFT
MSP430F2254TDA
MSP430F2254TDAR
MSP430F2254TRHAR
MSP430F2254TRHAT
MSP430F2272IDA
ACTIVE
DSBGA
TSSOP
TSSOP
VQFN
YFF
49
38
38
40
40
38
38
40
40
49
49
38
38
40
40
38
38
40
250
Green (RoHS
& no Sb/Br)
SNAGCU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
SNAGCU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
M430F2254
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DA
DA
40
Green (RoHS
& no Sb/Br)
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 85
-40 to 85
-40 to 85
-40 to 85
M430F2254T
M430F2254T
2000
2500
250
Green (RoHS
& no Sb/Br)
RHA
RHA
DA
Green (RoHS
& no Sb/Br)
M430
F2254T
VQFN
Green (RoHS
& no Sb/Br)
M430
F2254T
TSSOP
TSSOP
VQFN
40
Green (RoHS
& no Sb/Br)
M430F2272
MSP430F2272IDAR
MSP430F2272IRHAR
MSP430F2272IRHAT
MSP430F2272IYFFR
MSP430F2272IYFFT
MSP430F2272TDA
MSP430F2272TDAR
MSP430F2272TRHAR
MSP430F2272TRHAT
MSP430F2274IDA
DA
2000
2500
250
Green (RoHS
& no Sb/Br)
M430F2272
RHA
RHA
YFF
YFF
DA
Green (RoHS
& no Sb/Br)
M430
F2272
VQFN
Green (RoHS
& no Sb/Br)
M430
F2272
DSBGA
DSBGA
TSSOP
TSSOP
VQFN
2500
250
Green (RoHS
& no Sb/Br)
M430F2272
M430F2272
M430F2272T
M430F2272T
Green (RoHS
& no Sb/Br)
SNAGCU
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 85
-40 to 85
-40 to 85
DA
2000
2500
250
Green (RoHS
& no Sb/Br)
RHA
RHA
DA
Green (RoHS
& no Sb/Br)
M430
F2272T
VQFN
Green (RoHS
& no Sb/Br)
M430
F2272T
TSSOP
TSSOP
VQFN
40
Green (RoHS
& no Sb/Br)
M430F2274
MSP430F2274IDAR
MSP430F2274IRHAR
DA
2000
2500
Green (RoHS
& no Sb/Br)
M430F2274
RHA
Green (RoHS
& no Sb/Br)
M430
F2274
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
MSP430F2274IRHAT
MSP430F2274IYFFR
MSP430F2274IYFFT
MSP430F2274TDA
ACTIVE
VQFN
DSBGA
DSBGA
TSSOP
TSSOP
VQFN
RHA
40
49
49
38
38
40
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
SNAGCU
Level-3-260C-168 HR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
M430
F2274
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
YFF
YFF
DA
2500
250
Green (RoHS
& no Sb/Br)
M430F2274
Green (RoHS
& no Sb/Br)
SNAGCU
M430F2274
M430F2274T
M430F2274T
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
-40 to 105
-40 to 105
-40 to 105
-40 to 105
MSP430F2274TDAR
MSP430F2274TRHAR
MSP430F2274TRHAT
DA
2000
2500
250
Green (RoHS
& no Sb/Br)
RHA
RHA
Green (RoHS
& no Sb/Br)
M430
F2274T
VQFN
Green (RoHS
& no Sb/Br)
M430
F2274T
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF MSP430F2274 :
Enhanced Product: MSP430F2274-EP
•
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430F2232IDAR
MSP430F2232IRHAR
MSP430F2232IRHAT
MSP430F2232IYFFR
MSP430F2232IYFFT
MSP430F2232TRHAR
MSP430F2232TRHAT
MSP430F2234IDAR
MSP430F2234IRHAR
MSP430F2234IRHAT
MSP430F2234IYFFR
MSP430F2234IYFFT
MSP430F2234TRHAR
MSP430F2252IDAR
MSP430F2252IRHAR
MSP430F2252IRHAT
MSP430F2252IYFFR
MSP430F2252IYFFT
TSSOP
VQFN
DA
38
40
40
49
49
40
40
38
40
40
49
49
40
38
40
40
49
49
2000
2500
250
330.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
330.0
180.0
330.0
180.0
330.0
330.0
330.0
180.0
330.0
180.0
24.4
16.4
16.4
12.4
12.4
16.4
16.4
24.4
16.4
16.4
12.4
12.4
16.4
24.4
16.4
16.4
12.4
12.4
8.6
6.3
6.3
3.5
3.5
6.3
6.3
8.6
6.3
6.3
3.5
3.5
6.3
8.6
6.3
6.3
3.5
3.5
13.0
6.3
6.3
3.7
3.7
6.3
6.3
13.0
6.3
6.3
3.7
3.7
6.3
13.0
6.3
6.3
3.7
3.7
1.8
1.5
12.0
12.0
12.0
8.0
24.0
16.0
16.0
12.0
12.0
16.0
16.0
24.0
16.0
16.0
12.0
12.0
16.0
24.0
16.0
16.0
12.0
12.0
Q1
Q2
Q2
Q2
Q2
Q2
Q2
Q1
Q2
Q2
Q2
Q2
Q2
Q1
Q2
Q2
Q2
Q2
RHA
RHA
YFF
YFF
RHA
RHA
DA
VQFN
1.5
DSBGA
DSBGA
VQFN
2500
250
0.81
0.81
1.5
8.0
2500
250
12.0
12.0
12.0
12.0
12.0
8.0
VQFN
1.5
TSSOP
VQFN
2000
2500
250
1.8
RHA
RHA
YFF
YFF
RHA
DA
1.5
VQFN
1.5
DSBGA
DSBGA
VQFN
2500
250
0.81
0.81
1.5
8.0
2500
2000
2500
250
12.0
12.0
12.0
12.0
8.0
TSSOP
VQFN
1.8
RHA
RHA
YFF
YFF
1.5
VQFN
1.5
DSBGA
DSBGA
2500
250
0.81
0.81
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2012
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430F2252TRHAR
MSP430F2252TRHAT
MSP430F2254IDAR
MSP430F2254IRHAR
MSP430F2254IRHAT
MSP430F2254IYFFR
MSP430F2254IYFFT
MSP430F2254TRHAR
MSP430F2254TRHAT
MSP430F2272IDAR
MSP430F2272IRHAR
MSP430F2272IRHAT
MSP430F2272IYFFR
MSP430F2272IYFFT
MSP430F2272TRHAR
MSP430F2272TRHAT
MSP430F2274IRHAR
MSP430F2274IRHAT
MSP430F2274IYFFR
MSP430F2274IYFFT
MSP430F2274TRHAR
MSP430F2274TRHAT
VQFN
VQFN
TSSOP
VQFN
VQFN
DSBGA
DSBGA
VQFN
VQFN
TSSOP
VQFN
VQFN
DSBGA
DSBGA
VQFN
VQFN
VQFN
VQFN
DSBGA
DSBGA
VQFN
VQFN
RHA
RHA
DA
40
40
38
40
40
49
49
40
40
38
40
40
49
49
40
40
40
40
49
49
40
40
2500
250
330.0
180.0
330.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
16.4
16.4
24.4
16.4
16.4
12.4
12.4
16.4
16.4
24.4
16.4
16.4
12.4
12.4
16.4
16.4
16.4
16.4
12.4
12.4
16.4
16.4
6.3
6.3
8.6
6.3
6.3
3.5
3.5
6.3
6.3
8.6
6.3
6.3
3.5
3.5
6.3
6.3
6.3
6.3
3.5
3.5
6.3
6.3
6.3
6.3
13.0
6.3
6.3
3.7
3.7
6.3
6.3
13.0
6.3
6.3
3.7
3.7
6.3
6.3
6.3
6.3
3.7
3.7
6.3
6.3
1.5
1.5
12.0
12.0
12.0
12.0
12.0
8.0
16.0
16.0
24.0
16.0
16.0
12.0
12.0
16.0
16.0
24.0
16.0
16.0
12.0
12.0
16.0
16.0
16.0
16.0
12.0
12.0
16.0
16.0
Q2
Q2
Q1
Q2
Q2
Q2
Q2
Q2
Q2
Q1
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
2000
2500
250
1.8
RHA
RHA
YFF
YFF
RHA
RHA
DA
1.5
1.5
2500
250
0.81
0.81
1.5
8.0
2500
250
12.0
12.0
12.0
12.0
12.0
8.0
1.5
2000
2500
250
1.8
RHA
RHA
YFF
YFF
RHA
RHA
RHA
RHA
YFF
YFF
RHA
RHA
1.5
1.5
2500
250
0.81
0.81
1.5
8.0
2500
250
12.0
12.0
12.0
12.0
8.0
1.5
2500
250
1.5
1.5
2500
250
0.81
0.81
1.5
8.0
2500
250
12.0
12.0
1.5
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSP430F2232IDAR
MSP430F2232IRHAR
MSP430F2232IRHAT
MSP430F2232IYFFR
MSP430F2232IYFFT
MSP430F2232TRHAR
MSP430F2232TRHAT
MSP430F2234IDAR
MSP430F2234IRHAR
MSP430F2234IRHAT
MSP430F2234IYFFR
MSP430F2234IYFFT
MSP430F2234TRHAR
MSP430F2252IDAR
MSP430F2252IRHAR
MSP430F2252IRHAT
MSP430F2252IYFFR
MSP430F2252IYFFT
MSP430F2252TRHAR
MSP430F2252TRHAT
TSSOP
VQFN
DA
38
40
40
49
49
40
40
38
40
40
49
49
40
38
40
40
49
49
40
40
2000
2500
250
367.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
367.0
210.0
367.0
210.0
367.0
367.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
367.0
185.0
367.0
185.0
367.0
367.0
367.0
185.0
367.0
185.0
367.0
185.0
45.0
38.0
35.0
35.0
35.0
38.0
35.0
45.0
38.0
35.0
35.0
35.0
38.0
45.0
38.0
35.0
35.0
35.0
38.0
35.0
RHA
RHA
YFF
YFF
RHA
RHA
DA
VQFN
DSBGA
DSBGA
VQFN
2500
250
2500
250
VQFN
TSSOP
VQFN
2000
2500
250
RHA
RHA
YFF
YFF
RHA
DA
VQFN
DSBGA
DSBGA
VQFN
2500
250
2500
2000
2500
250
TSSOP
VQFN
RHA
RHA
YFF
YFF
RHA
RHA
VQFN
DSBGA
DSBGA
VQFN
2500
250
2500
250
VQFN
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2012
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSP430F2254IDAR
MSP430F2254IRHAR
MSP430F2254IRHAT
MSP430F2254IYFFR
MSP430F2254IYFFT
MSP430F2254TRHAR
MSP430F2254TRHAT
MSP430F2272IDAR
MSP430F2272IRHAR
MSP430F2272IRHAT
MSP430F2272IYFFR
MSP430F2272IYFFT
MSP430F2272TRHAR
MSP430F2272TRHAT
MSP430F2274IRHAR
MSP430F2274IRHAT
MSP430F2274IYFFR
MSP430F2274IYFFT
MSP430F2274TRHAR
MSP430F2274TRHAT
TSSOP
VQFN
DA
38
40
40
49
49
40
40
38
40
40
49
49
40
40
40
40
49
49
40
40
2000
2500
250
367.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
45.0
38.0
35.0
35.0
35.0
38.0
35.0
45.0
38.0
35.0
35.0
35.0
38.0
35.0
38.0
35.0
35.0
35.0
38.0
35.0
RHA
RHA
YFF
YFF
RHA
RHA
DA
VQFN
DSBGA
DSBGA
VQFN
2500
250
2500
250
VQFN
TSSOP
VQFN
2000
2500
250
RHA
RHA
YFF
YFF
RHA
RHA
RHA
RHA
YFF
YFF
RHA
RHA
VQFN
DSBGA
DSBGA
VQFN
2500
250
2500
250
VQFN
VQFN
2500
250
VQFN
DSBGA
DSBGA
VQFN
2500
250
2500
250
VQFN
Pack Materials-Page 4
D: Max = 3.518 mm, Min =3.458 mm
E: Max = 3.36 mm, Min = 3.3 mm
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