MSP430F4250 [TI]
MIXED SIGNAL MICROCONTROLLER; 混合信号微控制器
| 型号： | MSP430F4250 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MIXED SIGNAL MICROCONTROLLER |
| 文件： | 总57页 (文件大小：909K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
D
D
Low Supply-Voltage Range, 1.8 V to 3.6 V
D
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
Ultralow-Power Consumption:
Active Mode: 250 µA at 1 MHz, 2.2 V
Standby Mode: 1.1 µA
Off Mode (RAM Retention): 0.1 µA
Five Power Saving Modes
D
D
Integrated LCD Driver with Contrast
Control for Up to 56 Segments
D
D
D
D
MSP430x42x0 Family Members Include:
MSP430F4250: 16KB+256B Flash Memory
256B RAM
MSP430F4260: 24KB+256B Flash Memory
256B RAM
Wake-Up From Standby Mode in less
than 6 µs
16-Bit RISC Architecture,
125-ns Instruction Cycle Time
16-Bit Sigma-Delta A/D Converter With
Internal Reference and Five Differential
Analog Inputs
MSP430F4270: 32KB+256B Flash Memory
256B RAM
D
D
For Complete Module Descriptions, See
The MSP430x4xx Family User’s Guide,
Literature Number SLAU056
D
D
12-Bit D/A Converter
16-Bit Timer_A With Three
Capture/Compare Registers
For Additional Device Information, See The
MSP430F42x0 Device Erratasheet,
Literature Number SLAZ022
D
Brownout Detector
Bootstrap Loader
D
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6µs.
The MSP430F42x0 is a microcontroller configuration with a 16-bit timer, a high performance 16-bit sigma-delta
A/D converter, 12-bit D/A converter, 32 I/O pins, and a liquid crystal display driver.
Typical applications for this device include analog and digital sensor systems, digital motor control, remote
controls, thermostats, digital timers, hand-held meters, etc.
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
PLASTIC 48-PIN SSOP
(DL)
PLASTIC 48-PIN QFN
(RGZ)
MSP430F4250IDL
MSP430F4260IDL
MSP430F4270IDL
MSP430F4250IRGZ
MSP430F4260IRGZ
MSP430F4270IRGZ
−40°C to 85°C
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢂ
ꢂ
ꢒ
ꢓ
ꢥ
ꢌ
ꢠ
ꢕ
ꢑ
ꢞ
ꢔ
ꢟ
ꢉ
ꢙ
ꢓ
ꢗ
ꢎ
ꢘ
ꢌ
ꢏ
ꢔ
ꢏ
ꢖ
ꢗ
ꢡ
ꢘ
ꢙ
ꢟ
ꢚ
ꢛ
ꢜ
ꢜ
ꢝ
ꢝ
ꢖ
ꢖ
ꢙ
ꢙ
ꢗ
ꢗ
ꢖ
ꢞ
ꢞ
ꢢ
ꢟ
ꢠ
ꢚ
ꢚ
ꢡ
ꢡ
ꢗ
ꢝ
ꢜ
ꢛ
ꢞ
ꢞ
ꢙ
ꢘ
ꢢ
ꢔꢡ
ꢠ
ꢣ
ꢞ
ꢤ
ꢖ
ꢟ
ꢜ
ꢞ
ꢝ
ꢖ
ꢝ
ꢙ
ꢚ
ꢗ
ꢠ
ꢥ
ꢜ
ꢗ
ꢝ
ꢝ
ꢡ
ꢞ
ꢦ
Copyright 2005, Texas Instruments Incorporated
ꢚ
ꢙ
ꢟ
ꢝ
ꢙ
ꢚ
ꢛ
ꢝ
ꢙ
ꢞ
ꢢ
ꢖ
ꢘ
ꢖ
ꢟ
ꢡ
ꢚ
ꢝ
ꢧ
ꢝ
ꢡ
ꢚ
ꢙ
ꢘ
ꢈ
ꢜ
ꢉ
ꢗ
ꢛ
ꢡ
ꢞ
ꢝ
ꢜ
ꢗ
ꢥ
ꢜ
ꢚ
ꢥ
ꢨ
ꢜ
ꢝ ꢡ ꢞ ꢝꢖ ꢗꢪ ꢙꢘ ꢜ ꢤꢤ ꢢꢜ ꢚ ꢜ ꢛ ꢡ ꢝ ꢡ ꢚ ꢞ ꢦ
ꢚ
ꢚ
ꢜ
ꢗ
ꢝ
ꢩ
ꢦ
ꢂ
ꢚ
ꢙ
ꢥ
ꢠ
ꢟ
ꢝ
ꢖ
ꢙ
ꢗ
ꢢ
ꢚ
ꢙ
ꢟ
ꢡ
ꢞ
ꢞꢖ
ꢗ
ꢪ
ꢥ
ꢙ
ꢡ
ꢞ
ꢗ
ꢙ
ꢝ
ꢗ
ꢡ
ꢟ
ꢡ
ꢞ
ꢞ
ꢜ
ꢚ
ꢖ
ꢤ
ꢩ
ꢖ
ꢗ
ꢟ
ꢤ
ꢠ
ꢥ
ꢡ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
pin designation, MSP430F42x0
DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
TDO/TDI
TDI/TCLK
TMS
TCK
RST/NMI
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P2.0/S13
P2.1/S12
P2.2/S11
P2.3/S10
P2.4/S9
P2.5/S8
P2.6/S7
P2.7/S6
S5
DV
CC
DV
SS
XIN
XOUT
MSP430F42x0IDL
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AV
SS
CC
AV
V
REF
P6.0/A0+
P6.1/A0−
P6.2/A1+
P6.3/A1−
P5.7/S4
P5.6/S3
P5.5/S2
P5.0/S1
P6.4
P6.5
P6.6
P6.7
P5.1/S0
LCDCAP/R23
LCDREF/R13
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1/A4−
P1.3/TA2/A4+
P1.7/A2+
P1.6/A2−
P1.5/TACLK/ACLK/A3+
P1.4/A3−/DAC0
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
pin designation, MSP430F42x0 (continued)
RGZ PACKAGE
(TOP VIEW)
47 46 45 44 43 42 41 40 39 38
P2.2/S11
36
DV
1
SS
XIN
2
35 P2.3/S10
P2.4/S9
33 P2.5/S8
P2.6/S7
31 P2.7/S6
S5
29 P5.7/S4
P5.6/S3
27 P5.5/S2
P5.0/S1
25 P5.1/S0
3
34
XOUT
AV
SS
4
5
32
AV
CC
6
V
REF
MSP430F42x0IRGZ
P6.0/A0+
7
30
8
P6.1/A0−
P6.2/A1+
9
28
10
11
12
P6.3/A1−
P6.4
26
P6.5
14 15 16 17 18 19 20 21 22 23
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
MSP430F42x0 functional block diagram
P1
P5
XIN XOUT
DV
RST/NMI
DAC12
P2
P6
DV
AV
AV
SS
CC
SS
CC
8
8
8
8
Oscillator
FLL+
ACLK
32KB Flash 256B RAM
24KB Flash
16KB Flash
SD16_A
16-Bit
I/O Port 1/2 I/O Port 5/6
16 I/Os,
with
16 I/Os
SMCLK
12-Bit
1 Channel
Voltage out
Interrupt
Capability
MCLK
MAB,
4 Bit
Test
MAB,16-Bit
JTAG
CPU
MCB
Incl. 16 Reg.
Bus
Conv
MDB, 16-Bit
MDB, 8 Bit
4
TMS
TCK
Watchdog
Timer+
Timer_A3
3 CC Reg
POR
Brownout
Basic
Timer 1
LCD_A
56
Segments
TDI/TCLK
TDO/TDI
15/16-Bit
1 Interrupt
Vector
1,2,3,4 MUX
f
LCD
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
MSP430F42x0 Terminal Functions
TERMINAL
DL
DESCRIPTION
NAME
RGZ
NO.
I/O
NO.
TDO/TDI
1
43
44
45
46
47
48
1
I/O
Test data output port. TDO/TDI data output or programming data input terminal
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
Test mode select. TMS is used as an input port for device programming and test.
Test clock. TCK is the clock input port for device programming and test.
General-purpose digital I/O / reset input or nonmaskable interrupt input port
Digital supply voltage, positive terminal
TDI/TCLK
TMS
2
I
I
I
I
3
TCK
4
RST/NMI
5
DV
DV
6
CC
SS
7
Digital supply voltage, negative terminal
XIN
8
2
I
Input terminal of crystal oscillator XT1
XOUT
9
3
O
Output terminal of crystal oscillator XT1
AV
AV
10
11
12
13
14
15
16
17
18
19
20
21
22
4
Analog supply voltage, negative terminal
SS
5
Analog supply voltage, positive terminal
CC
V
REF
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Analog reference voltage
P6.0/A0+
P6.1/A0−
P6.2/A1+
P6.3/A1−
P6.4
7
General-purpose digital I/O / analog input A0+
General-purpose digital I/O / analog input A0−
General-purpose digital I/O / analog input A1+
General-purpose digital I/O / analog input A1−
General-purpose digital I/O
8
9
10
11
12
13
14
15
16
P6.5
General-purpose digital I/O
P6.6
General-purpose digital I/O
P6.7
General-purpose digital I/O
P1.7/A2+
P1.6/A2−
General-purpose digital I/O / analog input A2+
General-purpose digital I/O / analog input A2−
General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8) / analog input A3+
P1.5/TACLK/ACLK/A3+
P1.4/A3−/DAC0
23
24
25
17
18
19
I/O
I/O
I/O
General-purpose digital I/O / analog input A3− / DAC12 output
General-purpose digital I/O / Timer_A, Capture: CCI2A, compare: Out2 output /
analog input A4+
P1.3/TA2/A4+
General-purpose digital I/O / Timer_A, Capture: CCI1A, compare: Out1 output /
analog input A4−
P1.2/TA1/A4−
26
27
20
21
I/O
I/O
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0B / MCLK output. Note: TA0 is only an
input on this pin / BSL Receive
P1.1/TA0/MCLK
General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL
Transmit
P1.0/TA0
28
29
22
23
LCDREF/R13
External LCD reference voltage input / input port of third most positive analog LCD level (V4
or V3)
LCDCAP/R23
30
24
Capacitor connection for LCD charge pump /
input port of second most positive analog LCD level (V2)
P5.1/S0
P5.0/S1
P5.5/S2
P5.6/S3
P5.7/S4
S5
31
32
33
34
35
36
37
38
25
26
27
28
29
30
31
32
I/O
I/O
I/O
I/O
I/O
O
General-purpose digital I/O / LCD segment output 0
General-purpose digital I/O / LCD segment output 1
General-purpose digital I/O / LCD segment output 2
General-purpose digital I/O / LCD segment output 3
General-purpose digital I/O / LCD segment output 4
LCD segment output 5
P2.7/S6
P2.6/S7
I/O
I/O
General-purpose digital I/O / LCD segment output 6
General-purpose digital I/O / LCD segment output 7
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
MSP430F42x0 Terminal Functions (Continued)
TERMINAL
DL
DESCRIPTION
NAME
RGZ
NO.
I/O
NO.
37
38
39
40
41
42
43
44
45
46
47
48
P2.7/S6
P2.6/S7
P2.5/S8
P2.4/S9
P2.3/S10
P2.2/S11
P2.1/S12
P2.0/S13
COM0
31
32
33
34
35
36
37
38
39
40
41
42
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
General-purpose digital I/O / LCD segment output 6
General-purpose digital I/O / LCD segment output 7
General-purpose digital I/O / LCD segment output 8
General-purpose digital I/O / LCD segment output 9
General-purpose digital I/O / LCD segment output 10
General-purpose digital I/O / LCD segment output 11
General-purpose digital I/O / LCD segment output 12
General-purpose digital I/O / LCD segment output 13
Common output, COM0−3 are used for LCD backplanes.
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.2/COM1
P5.3/COM2
P5.4/COM3
QFN Pad
I/O
I/O
I/O
NA None NA QFN package pad connection to DV
SS
recommended.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
short-form description
CPU
Program Counter
Stack Pointer
PC/R0
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
R4
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
R5
R6
R7
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
R8
R9
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
R10
R11
instruction set
R12
R13
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
R14
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
e.g. ADD R4,R5
R4 + R5 −−−> R5
e.g. CALL
e.g. JNE
R8
PC −−>(TOS), R8−−> PC
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
Register
S
D
SYNTAX
MOV Rs,Rd
EXAMPLE
MOV R10,R11
MOV 2(R5),6(R6)
OPERATION
F
F
F
F
F
F
F
F
F
R10 —> R11
Indexed
MOV X(Rn),Y(Rm)
MOV EDE,TONI
MOV & MEM, & TCDAT
MOV @Rn,Y(Rm)
M(2+R5)—> M(6+R6)
M(EDE) —> M(TONI)
M(MEM) —> M(TCDAT)
M(R10) —> M(Tab+R6)
Symbolic (PC relative)
Absolute
Indirect
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
Indirect
autoincrement
M(R10) —> R11
R10 + 2—> R10
F
F
MOV @Rn+,Rm
Immediate
MOV #X,TONI
#45 —> M(TONI)
NOTE: S = source
D = destination
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D
D
Active mode AM;
All clocks are active
Low-power mode 0 (LPM0);
−
−
CPU is disabled
ACLK and SMCLK remain active, MCLK is available to modules
FLL+ Loop control remains active
D
D
Low-power mode 1 (LPM1);
−
CPU is disabled
ACLK and SMCLK remain active, MCLK is available to modules
FLL+ Loop control is disabled
Low-power mode 2 (LPM2);
−
CPU is disabled
MCLK and FLL+ loop control and DCOCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D
D
Low-power mode 3 (LPM3);
−
CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
Low-power mode 4 (LPM4);
−
CPU is disabled
ACLK is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 3. Interrupt Sources, Flags, and Vectors of MSP430F42x0 Configuration
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
PRIORITY
Power-Up
External Reset
Reset
0FFFEh
15, highest
Watchdog
Flash Memory
WDTIFG
KEYV
PC Out-of-Range (see Note 4)
(see Note 1)
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh
0FFFAh
0FFF8h
14
13
12
SD16CCTLx SD16OVIFG,
SD16CCTLx SD16IFG
(see Notes 1 and 2)
SD16_A
Maskable
Maskable
0FFF6h
0FFF4h
0FFF2h
0FFF0h
0FFEEh
0FFECh
11
10
9
Watchdog Timer
WDTIFG
8
7
Timer_A3
Timer_A3
TACCR0 CCIFG0 (see Note 2)
Maskable
Maskable
6
TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG (see Notes 1 and 2)
0FFEAh
5
I/O Port P1 (Eight Flags)
DAC12
P1IFG.0 to P1IFG.7 (see Notes 1 and 2)
Maskable
Maskable
0FFE8h
0FFE6h
4
3
DAC12_0IFG
(see Note 2)
0FFE4h
0FFE2h
0FFE0h
2
1
I/O Port P2 (Eight Flags)
Basic Timer1
P2IFG.0 to P2IFG.7 (see Notes 1 and 2)
BTIFG
Maskable
Maskable
0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot
disable it.
4. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h-01FFh).
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
special function registers
The MSP430 special function registers(SFR) are located in the lowest address space, and are organized as
byte mode registers. SFRs should be accessed with byte instructions.
interrupt enable registers 1 and 2
7
6
5
4
3
2
1
0
Address
0h
ACCVIE
NMIIE
OFIE
WDTIE
rw–0
rw–0
rw–0
rw–0
WDTIE:
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as a general-purpose timer.
OFIE:
Oscillator-fault-interrupt enable
Nonmaskable-interrupt enable
Flash access violation interrupt enable
NMIIE:
ACCVIE:
7
BTIE
6
5
4
3
2
1
0
Address
01h
rw–0
BTIE:
Basic timer interrupt enable
interrupt flag registers 1 and 2
7
6
5
4
3
2
1
0
Address
02h
NMIIFG
OFIFG
WDTIFG
rw–0
rw–1
rw–(0)
WDTIFG:
Set on watchdog timer overflow (in watchdog mode) or security key violation
Reset on V power-on or a reset condition at the RST/NMI pin in reset mode
CC
OFIFG:
Flag set on oscillator fault
Set via RST/NMI pin
NMIIFG:
7
6
5
4
3
2
1
0
Address
03h
BTIFG
rw–0
BTIFG:
Basic timer flag
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
module enable registers 1 and 2
7
6
5
5
4
4
3
3
2
2
1
1
0
0
Address
04h
7
6
Address
05h
Legend: rw:
Bit Can Be Read and Written
rw–0,1:
rw–(0,1):
Bit Can Be Read and Written. It Is Reset or Set by PUC.
Bit Can Be Read and Written. It Is Reset or Set by POR.
SFR Bit Not Present in Device
memory organization
MSP430F4250
MSP430F4260
24KB
MSP430F4270
Memory
Size
16KB
32KB
Main: interrupt vector
Main: code memory
Flash
Flash
0FFFFh − 0FFE0h
0FFFFh − 0C000h
0FFFFh − 0FFE0h
0FFFFh − 0A000h
0FFFFh − 0FFE0h
0FFFFh − 08000h
Information memory
Boot memory
RAM
Size
Flash
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Size
ROM
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
Size
256 Byte
256 Byte
256 Byte
02FFh − 0200h
02FFh − 0200h
02FFh − 0200h
Peripherals
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.
BSL Function
Data Transmit
Data Receive
DL Package Pins
28 − P1.0
RGZ Package Pins
22 − P1.0
27 − P1.1
21 − P1.1
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D
Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
D
D
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A and B can be erased individually, or as a group with segments 0−n.
Segments A and B are also called information memory.
D
New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
16KB
24KB
32KB
Segment 0
w/ Interrupt Vectors
0FFFFh
0FFFFh
0FFFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
Segment 1
Segment 2
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
Main
Memory
0C400h
0C3FFh
0A400h
0A3FFh
08400h
083FFh
Segment n-1
Segment n†
0C200h
0C1FFh
0A200h
0A1FFh
08200h
081FFh
0C000h
010FFh
0A000h
010FFh
08000h
010FFh
Segment A
Segment B
Information
Memory
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01000h
01000h
01000h
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide, Literature
Number SLAU056.
oscillator and system clock
The clock system in the MSP430F42x0 family of devices is supported by the FLL+ module that includes support
for a 32768 Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency
crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and
low-power consumption. The FLL+ features digital frequency locked loop (FLL) hardware which in conjunction
with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.
The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The FLL+ module
provides the following clock signals:
D
D
D
D
Auxiliary clock (ACLK), sourced from a 32768 Hz watch crystal or a high frequency crystal.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.
brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on
and power-off. The CPU begins code execution after the brownout circuit releases the device reset. However,
may not have ramped to V at that time. The user must insure the default FLL+ settings are not
V
CC
CC(min)
CC(min)
changed until V
reaches V
.
CC
digital I/O
There are four 8-bit I/O ports implemented—ports P1, P2, P5 and P6:
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
Basic Timer1
The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts.
LCD driver with regulated charge pump
The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2−MUX, 3−MUX, and 4−MUX LCDs are supported by this peripheral.
The module can provide a LCD voltage independent of the supply voltage via an integrated charge pump.
Furthermore it is possible to control the level of the LCD voltage and thus contrast in software.
watchdog timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number
DL RGZ
Output Pin Number
DL RGZ
Device Input
Signal
Module
Input Name
Module
Block
Module Output
Signal
23 - P1.5 17 - P1.5
TACLK
ACLK
SMCLK
TACLK
TA0
TACLK
ACLK
Timer
CCR0
CCR1
CCR2
NA
TA0
TA1
TA2
SMCLK
INCLK
CCI0A
CCI0B
GND
23 - P1.5 17 - P1.5
28 - P1.0 22 - P1.0
27 - P1.1 21 - P1.1
28 - P1.0 22 - P1.0
26 - P1.2 20 - P1.2
25 - P1.3 19 - P1.3
TA0
DV
DV
SS
V
CC
CC
26 - P1.2 20 - P1.2
26 - P1.2 20 - P1.2
TA1
TA1
CCI1A
CCI1B
GND
DV
SS
DV
V
CC
CC
25 - P1.3 19 - P1.3
TA2
ACLK (internal)
CCI2A
CCI2B
GND
DV
SS
CC
DV
V
CC
SD16_A
The SD16_A module supports 16-bit analog-to-digital conversions. The module implements a 16-bit
sigma-delta core and reference generator. In addition to external analog inputs, an internal V
temperature sensor are also available.
sense and
CC
DAC12
The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit mode.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog timer control
Watchdog
WDTCTL
TACCR2
TACCR1
TACCR0
TAR
0120h
0176h
0174h
0172h
0170h
0166h
0164h
0162h
0160h
012Eh
012Ch
012Ah
0128h
01C8h
01C0h
0100h
0102h
0110h
0112h
Timer_A3
Capture/compare register 2
Capture/compare register 1
Capture/compare register 0
Timer_A register
Capture/compare control 2
Capture/compare control 1
Capture/compare control 0
Timer_A control
TACCTL2
TACCTL1
TACCTL0
TACTL
Timer_A interrupt vector
Flash control 3
TAIV
Flash
FCTL3
Flash control 2
FCTL2
Flash control 1
FCTL1
DAC12
DAC12_0 data
DAC12_0DAT
DAC12_0CTL
SD16CTL
SD16CCTL0
SD16IV
DAC12_0 control
SD16_A
(see also:
Peripherals with
Byte Access)
General Control
Channel 0 Control
Interrupt vector word register
Channel 0 conversion memory
SD16MEM0
PERIPHERALS WITH BYTE ACCESS
SD16_A
(see also:
Peripherals with
Word Access)
Channel 0 Input Control
SD16INCTL0
SD16AE
0B0h
0B7h
Analog Enable
LCD_A
LCD Voltage Control 1
LCD Voltage Control 0
LCD Voltage Port Control 1
LCD Voltage Port Control 0
LCD memory 20
:
LCDAVCTL1
LCDAVCTL0
LCDAPCTL1
LCDAPCTL0
LCDM20
:
0AFh
0AEh
0ADh
0ACh
0A4h
:
LCD memory 16
LCD memory 15
:
LCDM16
LCDM15
:
0A0h
09Fh
:
LCD memory 1
LCDM1
091h
090h
LCD control and mode
LCDACTL
FLL+Clock
FLL+ Control 1
FLL_CTL1
FLL_CTL0
SCFQCTL
SCFI1
054h
053h
052h
051h
050h
FLL+ Control 0
System clock frequency control
System clock frequency integrator
System clock frequency integrator
SCFI0
Basic Timer1
BT counter 2
BT counter 1
BT control
BTCNT2
BTCNT1
BTCTL
047h
046h
040h
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Port P6
Port P5
Port P2
Port P6 selection
Port P6 direction
P6SEL
037h
036h
035h
034h
033h
032h
031h
030h
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
026h
025h
024h
023h
022h
021h
020h
005h
004h
003h
002h
001h
000h
P6DIR
P6OUT
P6IN
Port P6 output
Port P6 input
Port P5 selection
Port P5 direction
P5SEL
P5DIR
P5OUT
P5IN
Port P5 output
Port P5 input
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt-edge select
Port P2 interrupt flag
Port P2 direction
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
Port P2 output
Port P2 input
Port P1
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt-edge select
Port P1 interrupt flag
Port P1 direction
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
Port P1 output
Port P1 input
Special functions
SFR module enable 2
SFR module enable 1
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
ME2
ME1
IFG2
IFG1
IE2
IE1
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Voltage applied at V
to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V
CC
SS
Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA
+ 0.3 V
CC
Storage temperature, T : (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
stg
(programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to V
The JTAG fuse-blow voltage, V , is allowed to exceed the absolute maximum rating. The voltage is applied
SS.
FB
to the TDI/TCLK pin when blowing the JTAG fuse.
recommended operating conditions
MIN
NOM
MAX UNITS
Supply voltage during program execution,
1.8
3.6
3.6
V
V
V
(AV
CC
= DV
CC
= V )
CC
CC
Supply voltage during flash memory programming,
2.5
V
CC
(AV
CC
= DV
= V )
CC
CC
Supply voltage, V
(AV
SS
= DV
SS
= V
)
0
0
V
SS
SS
Operating free-air temperature range, T
−40
85
°C
A
LF selected,
XTS_FLL=0
Watch crystal
Ceramic resonator
Crystal
32.768
kHz
kHz
kHz
XT1 selected,
XTS_FLL=1
LFXT1 crystal frequency, f
(see Note 1)
(LFXT1)
450
8000
8000
XT1 selected,
XTS_FLL=1
1000
Ceramic resonator
Crystal
450
1000
DC
8000
8000
4.15
8
XT2 crystal frequency, f
(XT2)
kHz
V
V
= 1.8 V
= 3.6 V
CC
Processor frequency (signal MCLK), f
(System)
MHz
DC
CC
NOTES: 1. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
f
(MHz)
System
8 MHz
Supply voltage range,
MSP430F42x0, during
program execution
Supply voltage range, MSP430F42x0,
during flash memory programming
4.15 MHz
1.8
3
3.6
2.5
Supply Voltage − V
Figure 1. Frequency vs Supply Voltage, typical characteristic
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AV
+ DV
excluding external current
CC
CC
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
Active mode, (see Note 1)
V
V
= 2.2 V
= 3 V
250
370
CC
f
= f = 1 MHz,
(MCLK) (SMCLK)
I
T
A
= −40°C to 85°C
µA
(AM)
f
= 32,768 Hz
(ACLK)
400
520
CC
XTS=0, SELM=(0,1)
V
V
= 2.2 V
= 3 V
55
95
70
Low-power mode, (LPM0)
(see Note 1)
CC
I
I
T
= −40°C to 85°C
= −40°C to 85°C
µA
µA
(LPM0)
A
110
CC
Low-power mode, (LPM2),
f(MCLK) = f (SMCLK) = 0 MHz,
f(ACLK) = 32,768 Hz, SCG0 = 0 (see Note 2)
V
= 2.2 V
= 3 V
11
17
14
22
CC
CC
T
A
(LPM2)
V
T
= −40°C
= 25°C
= 60°C
= 85°C
= −40°C
= 25°C
= 60°C
= 85°C
1.0
1.1
2.0
3.5
1.8
1.6
2.5
4.2
2.5
2.0
2.0
3.0
6.0
2.8
2.7
3.5
7.5
3.5
A
Low-power mode, (LPM3)
T
A
f
= f
= 0 MHz,
= 32,768 Hz, SCG0 = 1
(MCLK) (SMCLK)
V
V
= 2.2 V
CC
T
A
f
(ACLK)
Basic Timer1 enabled , ACLK selected
LCD_A enabled, LCDCPEN = 0:
T
A
I
I
I
µA
µA
µA
(LPM3)
(LPM3)
(LPM4)
T
A
(static mode ; f /32)
= f
LCD (ACLK)
T
A
(see Note 2 and Note 3)
= 3 V
CC
T
A
T
A
Low-power mode, (LPM3)
T
A
= −40°C
= 25°C
= 85°C
= −40°C
= 25°C
f
= f
= 0 MHz,
= 32,768 Hz, SCG0 = 1
(MCLK) (SMCLK)
T
A
2.5
3.8
2.9
2.9
3.5
6.0
4.0
4.0
V
V
= 2.2 V
= 3 V
CC
f
(ACLK)
Basic Timer1 enabled , ACLK selected
LCD_A enabled, LCDCPEN = 0:
T
A
T
A
(4-mux mode; f
(see Note 2 and Note 3)
= f
/32)
LCD (ACLK)
T
A
CC
T
= 85°C
= −40°C
= 25°C
= 60°C
= 85°C
= −40°C
= 25°C
= 60°C
= 85°C
4.4
0.1
0.1
0.7
1.7
0.1
0.1
0.8
1.9
7.5
0.5
0.5
1.1
3.0
0.8
0.8
1.2
3.5
A
T
A
T
A
V
CC
V
CC
= 2.2 V
T
A
Low-power mode, (LPM4)
T
A
f
f
= 0 MHz, f
(SMCLK)
= 0 Hz, SCG0 = 1 (see Note 2)
= 0 MHz,
(MCLK)
(ACLK)
T
A
T
A
= 3 V
T
A
T
A
NOTES: 1. Timer_A is clocked by f
= 1 MHz. All inputs are tied to 0 V or to V . Outputs do not source or sink any current.
(DCOCLK)
CC
2. All inputs are tied to 0 V or to V . Outputs do not source or sink any current.
CC
3. The LPM3 currents are characterized with a Micro Crystal CC4V−T1A (9pF) crystal and OSCCAPx=01h.
Current consumption of active mode versus system frequency, F-version:
I
= I
[1 MHz] × f
[MHz]
(AM)
(AM)
(System)
Current consumption of active mode versus supply voltage, F-version:
= I + 175 µA/V × (V – 3 V)
I
(AM)
(AM) [3 V]
CC
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SCHMITT-trigger inputs − Ports P1, P2, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER
TEST CONDITIONS
MIN
1.1
1.5
0.4
0.9
0.3
0.5
TYP
MAX
1.55
1.98
0.9
UNIT
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.2 V
= 3 V
V
IT+
V
IT−
V
hys
Positive-going input threshold voltage
V
= 2.2 V
= 3 V
Negative-going input threshold voltage
V
V
1.3
= 2.2 V
= 3 V
1.1
Input voltage hysteresis (V
IT+
− V )
IT−
1
inputs Px.x, TAx
PARAMETER
TEST CONDITIONS
V
MIN
62
TYP
MAX
UNIT
CC
2.2 V
3 V
Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag, (see Note 1)
t
t
f
f
External interrupt timing
Timer_A capture timing
ns
(int)
50
2.2 V
3 V
62
TA0, TA1, TA2
ns
(cap)
50
2.2 V
3 V
8
10
8
Timer_A clock frequency
externally applied to pin
TACLK, INCLK: t
= t
MHz
MHz
(TAext)
(H) (L)
2.2 V
3 V
Timer_A, clock frequency
SMCLK or ACLK signal selected
(TAint)
10
NOTES: 1. The external signal sets the interrupt flag every time the minimum t
(int)
parameters are met. It may be set even with trigger signals
shorter than t
.
(int)
leakage current − Ports P1, P2, P5, and P6 (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Leakage
current
I
Port Px
V
(Px.y)
(see Note 2)
V
CC
= 2.2 V/3 V
50
nA
lkg(Px.y)
NOTES: 1. The leakage current is measured with V
2. The port pin must be selected as input.
or V
CC
applied to the corresponding pin(s), unless otherwise noted.
SS
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1, P2, P5, and P6
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
I
I
I
I
I
I
I
= −1.5 mA,
= −6 mA,
= −1.5 mA,
= −6 mA,
= 1.5 mA,
= 6 mA,
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.2 V,
= 2.2 V,
= 3 V,
See Note 1
See Note 2
See Note 1
See Note 2
See Note 1
See Note 2
See Note 1
See Note 2
V
−0.25
V
V
V
V
OH(max)
OH(max)
OH(max)
OH(max)
OL(max)
OL(max)
OL(max)
OL(max)
CC
CC
CC
CC
CC
V
−0.6
CC
−0.25
V
High-level output voltage
V
OH
OL
V
CC
= 3 V,
V
−0.6
CC
= 2.2 V,
= 2.2 V,
= 3 V,
V
V
+0.25
SS
SS
SS
SS
SS
V
V
V
V
+0.6
SS
V
Low-level output voltage
V
= 1.5 mA,
= 6 mA,
V
SS
+0.25
= 3 V,
V
+0.6
SS
NOTES: 1. The maximum total current, I
specified voltage drop.
and I
for all outputs combined, should not exceed 12 mA to satisfy the maximum
OH(max)
OL(max),
OL(max),
2. The maximum total current, I
specified voltage drop.
and I
for all outputs combined, should not exceed 48 mA to satisfy the maximum
OH(max)
output frequency
PARAMETER
TEST CONDITIONS
= 2.2 V / 3 V
MIN
TYP
MAX
UNIT
MHz
MHz
C
= 20 pF,
L
L
f
f
(x = 1, 2, 5, 6; 0 ≤ y ≤ 7)
V
CC
DC
f
f
(Px.y)
System
I
L
=
1.5 mA
P1.1/TA0/MCLK
C
= 20 pF
(MCLK)
System
60%
f = f
(MCLK) (XT1)
40%
P1.1/TA0/MCLK,
t
Duty cycle of output frequency
C
V
= 20 pF,
50%−
15 ns
50%+
15 ns
(Xdc)
L
f = f
(MCLK) (DCOCLK)
50%
= 2.2 V / 3 V
CC
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1, P2, P5, and P6 (continued)
TYPICAL LOW-LEVEL OUTPUT CURRENT
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
V
CC
P1.0
= 2.2 V
V
CC
P1.0
= 3 V
T
= −40°C
A
T
= −40°C
A
T
= 25°C
A
T
= 25°C
A
T
A
= 85°C
T
= 85°C
A
0
0.0
0
0.0
0.5
1.0
1.5
2.0
2.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OL
− Low-Level Output Voltage − V
V
OL
− Low-Level Output Voltage − V
Figure 2
Figure 3
TYPICAL HIGH-LEVEL OUTPUT CURRENT
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
vs
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
0
−5
0
V
= 2.2 V
V
= 3 V
CC
P1.0
CC
P1.0
−5
−10
−15
−20
−25
−30
−35
−40
−45
−50
−10
−15
−20
−25
T
A
= 85°C
T = 25°C
A
T
A
= 85°C
T
A
= 25°C
T
A
= −40°C
T
= −40°C
A
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OH
− High-Level Output Voltage − V
V
OH
− High-Level Output Voltage − V
Figure 4
Figure 5
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER
PARAMETER
TEST CONDITIONS
f = 1 MHz
MIN
TYP
MAX
UNIT
6
6
6
f = 2 MHz
f = 3 MHz
t
Delay time
V
CC
= 2.2 V/3 V
µs
d(LPM3)
RAM
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VRAMh
CPU halted (see Note 1)
1.6
V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
LCD_A
PARAMETER
TEST CONDITIONS
VCC
MIN
2.2
4.7
TYP
MAX UNIT
Charge pump enabled
(LCDCPEN = 1; VLCDx > 0000)
V
Supply Voltage Range
3.6
V
CC(LCD)
Charge pump enabled
(LCDCPEN = 1; VLCDx > 0000)
C
Capacitor on LCDCAP (see Note 1)
Average Supply Current (see Note 2)
µF
LCD
V
=3V; LCDCPEN = 1;
LCD(typ)
VLCDx= 1000, all segments on
= f /32
f
I
2.2 V
3.8
µA
LCD ACLK
no LCD connected (see Note 3)
= 25°C
CC(LCD)
LCD
T
A
f
LCD frequency
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
1.1 kHz
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VLCDx = 0000
VLCDx = 0001
VLCDx = 0010
VLCDx = 0011
VLCDx = 0100
VLCDx = 0101
VLCDx = 0110
VLCDx = 0111
VLCDx = 1000
VLCDx = 1001
VLCDx = 1010
VLCDx = 1011
VLCDx = 1100
VLCDx = 1101
VLCDx = 1110
VLCDx = 1111
VCC
2.60
2.66
2.72
2.78
2.84
2.90
2.96
3.02
3.08
3.14
3.20
3.26
3.32
3.38
3.44
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
3.60
10
V
V
= 3V; LCDCPEN = 1;
LCD
VLCDx = 1000, I
R
LCD Driver Output impedance
2.2 V
kΩ
LCD
=
10µA
LOAD
NOTES: 1. Enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device.
2. Refer to the supply current specifications I for additional current specifications with the LCD_A module active.
(LPM3)
3. Connecting an actual display will increase the current consumption depending on the size of the LCD.
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
POR/brownout reset (BOR) (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
µs
t
2000
d(BOR)
V
dV /dt ≤ 3 V/s (see Figure 6)
CC
0.7 × V
(B_IT−)
V
CC(start)
Brownout
V
V
dV /dt ≤ 3 V/s (see Figure 6 through Figure 8)
CC
dV /dt ≤ 3 V/s (see Figure 6)
CC
1.71
180
V
(B_IT−)
(see Note 2)
70
2
130
mV
hys(B_IT−)
Pulse length needed at RST/NMI pin to accepted reset internally,
t
µs
(reset)
V
CC
= 2.2 V/3 V
NOTES: 1. The current consumption of the brownout module is already included in the I
current consumption data. The voltage level V
(B_IT−)
CC
+ V
is ≤ 1.8V.
2. During power up, the CPU begins code execution following a period of t
hys(B_IT−)
after V
CC
= V
(B_IT−)
+ V . The default
hys(B_IT−)
d(BOR)
FLL+ settings must not be changed until V
CC
≥ V
CC(min)
, where V
is the minimum supply voltage for the desired
CC(min)
operating frequency. See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout.
typical characteristics
V
CC
V
hys(B_IT−)
V
(B_IT−)
V
CC(start)
1
0
t
d(BOR)
Figure 6. POR/Brownout Reset (BOR) vs Supply Voltage
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
typical characteristics (continued)
V
t
CC
pw
2
3 V
V
= 3 V
CC
Typical Conditions
1.5
1
V
CC(min)
0.5
0
0.001
1
1000
1 ns
1 ns
− Pulse Width − µs
t
− Pulse Width − µs
t
pw
pw
Figure 7. V
Level With a Square Voltage Drop to Generate a POR/Brownout Signal
(CC)min
V
t
CC
pw
2
3 V
V
= 3 V
CC
Typical Conditions
1.5
1
V
CC(min)
0.5
0
t = t
f
r
0.001
1
1000
t
t
r
f
t
− Pulse Width − µs
t
− Pulse Width − µs
pw
pw
Figure 8. V
Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
CC(min)
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
DCO
PARAMETER
TEST CONDITIONS
V
MIN
TYP
1
MAX
UNIT
CC
f
N
=01E0h, FN_8=FN_4=FN_3=FN_2=0, D = 2; DCOPLUS= 0
(DCO)
2.2 V/3 V
2.2 V
3 V
MHz
(DCOCLK)
0.3
0.3
2.5
2.7
0.7
0.8
5.7
6.5
1.2
1.3
9
0.65
0.7
5.6
6.1
1.3
1.5
10.8
12.1
2
1.25
1.3
10.5
11.3
2.3
2.5
18
f
f
f
f
f
f
f
f
f
f
FN_8=FN_4=FN_3=FN_2=0 ; DCOPLUS = 1
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
(DCO2)
2.2 V
3 V
FN_8=FN_4=FN_3=FN_2=0; DCOPLUS = 1, (see Note 1)
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1
(DCO27)
(DCO2)
(DCO27)
(DCO2)
(DCO27)
(DCO2)
(DCO27)
(DCO2)
(DCO27)
2.2 V
3 V
2.2 V
3 V
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1, (see Note 1)
FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1
FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1, (see Note 1)
FN_8=0, FN_4= 1, FN_3= FN_2=x; DCOPLUS = 1
FN_8=0, FN_4=1, FN_3= FN_2=x; DCOPLUS = 1, (see Note 1)
FN_8=1, FN_4=FN_3=FN_2=x; DCOPLUS = 1
20
2.2 V
3 V
3
2.2
15.5
17.9
2.8
3.4
21.5
26.6
4.2
6.3
32
3.5
25
2.2 V
3 V
10.3
1.8
2.1
13.5
16
28.5
4.2
5.2
33
2.2 V
3 V
2.2 V
3 V
41
2.2 V
3 V
2.8
4.2
21
6.2
9.2
46
2.2 V
3 V
FN_8=1,FN_4=FN_3=FN_2=x; DCOPLUS = 1, (see Note 1)
Step size between adjacent DCO taps:
30
46
70
1 < TAP ≤ 20
TAP = 27
2.2 V
3 V
1.06
1.07
–0.2
–0.2
1.11
1.17
–0.4
–0.4
S
n
S
n
= f
/ f
, (see Figure 10 for taps 21 to 27)
DCO(Tap n+1) DCO(Tap n)
–0.3
–0.3
Temperature drift, N
(DCO)
= 01E0h, FN_8=FN_4=FN_3=FN_2=0
D = 2; DCOPLUS = 0, (see Note 2)
D
D
%/C
t
Drift with V variation, N = 01E0h, FN_8=FN_4=FN_3=FN_2=0
CC (DCO)
0
5
15
%/V
V
D = 2; DCOPLUS = 0 (see Note 2)
NOTES: 1. Do not exceed the maximum system frequency.
2. This parameter is not production tested.
f
f
(DCO)
(DCO)
f
f
5
(DCO3V)
(DCO20 C)
1.0
1.0
0
1.8
2.4
3.0
3.6
−40
−20
0
20
40
60
85
V
CC
− V
T
A
− °C
Figure 9. DCO Frequency vs Supply Voltage V
and vs Ambient Temperature
CC
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
1.17
Max
1.11
1.07
1.06
Min
1
20
27
DCO Tap
Figure 10. DCO Tap Step Size
Legend
Tolerance at Tap 27
DCO Frequency
Adjusted by Bits
9
2
5
to 2 in SCFI1 {N }
{DCO}
Tolerance at Tap 2
Overlapping DCO Ranges:
Uninterrupted Frequency Range
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_3=x
FN_4=x
FN_8=1
Figure 11. Five Overlapping DCO Ranges Controlled by FN_x Bits
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
MIN
TYP
0
MAX
UNIT
OSCCAPx = 0h, V
OSCCAPx = 1h, V
OSCCAPx = 2h, V
OSCCAPx = 3h, V
OSCCAPx = 0h, V
OSCCAPx = 1h, V
OSCCAPx = 2h, V
OSCCAPx = 3h, V
= 2.2 V / 3 V
= 2.2 V / 3 V
= 2.2 V / 3 V
= 2.2 V / 3 V
= 2.2 V / 3 V
= 2.2 V / 3 V
= 2.2 V / 3 V
= 2.2 V / 3 V
CC
CC
CC
CC
CC
CC
CC
CC
10
14
18
0
Integrated input capacitance
(see Note 4)
C
C
pF
XIN
10
14
18
Integrated output capacitance
(see Note 4)
pF
V
XOUT
V
V
V
0.2×V
CC
IL
SS
0.8×V
Input levels at XIN
V
CC
= 2.2 V/3 V (see Note 3)
V
CC
IH
CC
NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is
(C x C ) / (C + C ). This is independent of XTS_FLL.
XIN
XOUT XIN XOUT
2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.
− Keep as short of a trace as possible between the ’F42x0 and the crystal.
− Design a good ground plane around the oscillator pins.
− Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
− Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
− Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
− If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
− Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or
resonator.
4. External capacitance is recommended for precision real-time clock applications; OSCCAPx = 0h.
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16_A, power supply and recommended operating conditions
PARAMETER
TEST CONDITIONS
V
CC
MIN
2.5
TYP
MAX
3.6
UNIT
Analog supply
voltage
AV
AV
= DV
= DV
CC
SS
CC
SS
AV
CC
V
= 0V
SD16BUFx = 00; GAIN: 1,2
3 V
3 V
3 V
650
950
1100
1550
SD16LP = 0,
= 1 MHz,
SD16OSR = 256
SD16BUFx = 00; GAIN: 4,8,16
SD16BUFx = 00; GAIN: 32
730
f
SD16
1050
Analog supply
current including
internal reference
SD16LP = 1,
SD16BUFx = 00; GAIN: 1
SD16BUFx = 00; GAIN: 32
3 V
3 V
620
700
930
f
= 0.5 MHz,
ISD16
µA
SD16
1060
SD16OSR = 256
SD16BUFx = 01; GAIN: 1
SD16BUFx = 10; GAIN: 1
SD16BUFx = 11; GAIN: 1
3 V
3 V
3 V
850
1130
1130
SD16LP = 0,
f
= 1 MHz,
SD16
SD16OSR = 256
Analog front-end
input clock
frequency
SD16LP = 0 (Low power mode disabled)
SD16LP = 1 (Low power mode enabled)
3 V
3 V
0.03
0.03
1
1.1
f
MHz
SD16
0.5
SD16_A, input range
PARAMETER
TEST CONDITIONS
Bipolar Mode, SD16UNI = 0
Unipolar Mode, SD16UNI = 1
SD16GAINx = 1
V
CC
MIN
TYP
MAX
UNIT
mV
−V
/2GAIN
REF
+V
+V
/2GAIN
REF
Differential full scale
input voltage range
V
ID,FSR
0
/2GAIN
REF
mV
500
SD16GAINx = 2
250
125
62
Differential input
voltage range for
specified
performance
(see Note 1)
SD16GAINx = 4
V
ID
SD16REFON=1
mV
SD16GAINx = 8
SD16GAINx = 16
SD16GAINx = 32
31
15
SD16GAINx = 1
SD16GAINx = 32
3 V
3 V
200
75
f
= 1MHz,
SD16
SD16BUFx = 00
kΩ
Input impedance
(one input pin
Z
I
f
= 1MHz,
SD16
SD16BUFx = 01
to AV
)
SS
SD16GAINx = 1
3 V
>10
MΩ
SD16GAINx = 1
SD16GAINx = 32
3 V
3 V
300
100
400
150
f
= 1MHz,
SD16
SD16BUFx = 00
kΩ
Differential
Input impedance
(IN+ to IN−)
Z
ID
f
= 1MHz,
SD16
SD16GAINx = 1
3 V
>10
MΩ
SD16BUFx > 00
SD16BUFx = 00
SD16BUFx > 00
SD16BUFx = 00
SD16BUFx > 00
AV -0.1V
AV
CC
SS
Absolute input
voltage range
V
V
V
V
I
AV
SS
AV −1.2V
CC
AV -0.1V
AV
CC
SS
Common-mode
input voltage range
IC
AV
SS
AV −1.2V
CC
NOTES: 1. The analog input range depends on the reference voltage applied to V
. If V is sourced externally, the full-scale range
REF
REF
is defined by V
= +(V
/2)/GAIN and V
= −(V /2)/GAIN. The analog input range should not exceed 80% of
REF
FSR+
REF
FSR−
V
or V .
FSR−
FSR+
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16_A, performance (f
= 30kHz, SD16REFON = 1, SD16BUFx = 01)
SD16
PARAMETER
TEST CONDITIONS
V
MIN
TYP
84
MAX
UNIT
CC
SD16GAINx = 1,Signal Amplitude = 500mV
SD16OSRx = 256
3 V
3 V
SD16GAINx = 1,Signal Amplitude = 500mV
Signal-to-Noise +
Distortion Ratio
84
SINAD
f
IN
= 2.8Hz
dB
SD16OSRx = 512
SD16GAINx = 1,Signal Amplitude = 500mV
SD16OSRx = 1024
3 V
3 V
3 V
84
1.00
15
Nominal Gain
SD16GAINx = 1; SD16OSRx = 1024
0.97
1.02
Gain Temperature
Drift
dG/dT
SD16GAINx = 1; SD16OSRx = 1024 (see Note 1)
ppm/_C
Gain Supply
Voltage Drift
SD16GAINx = 1; SD16OSRx = 1024; V
(see Note 2)
= 2.5V - 3.6V
CC
dG/dV
CC
0.35
%/V
NOTES: 1. Calculated using the box method: (MAX(−40...85_C) − MIN(−40...85_C))/MIN(−40...85_C)/(85C − (−40_C))
2. Calculated using the box method: (MAX(2.5...3.6V) − MIN(2.5...3.6V))/MIN(2.5...3.6V)/(3.6V − 2.5V)
SD16_A, performance (f
= 1MHz, SD16OSRx = 256, SD16REFON = 1, SD16BUFx = 00)
SD16
PARAMETER
TEST CONDITIONS
SD16GAINx = 1,Signal Amplitude = 500mV
SD16GAINx = 2,Signal Amplitude = 250mV
SD16GAINx = 4,Signal Amplitude = 125mV
SD16GAINx = 8,Signal Amplitude = 62mV
SD16GAINx = 16,Signal Amplitude = 31mV
SD16GAINx = 32,Signal Amplitude = 15mV
SD16GAINx = 1
V
MIN
83.5
81.5
76
TYP
85
MAX
UNIT
CC
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
84
79.5
76.5
73
Signal-to-Noise +
Distortion Ratio
f
= 50Hz,
IN
100Hz
SINAD
dB
73
69
62
69
0.97
1.90
3.76
7.36
1.00
1.96
3.86
7.62
1.02
2.02
3.96
7.84
SD16GAINx = 2
SD16GAINx = 4
Nominal Gain
(see Note 1)
G
SD16GAINx = 8
SD16GAINx = 16
14.56 15.04 15.52
SD16GAINx = 32
27.20 28.35 29.76
SD16GAINx = 1
0.2
1.5
Offset Error
(see Note 1)
E
OS
%FSR
SD16GAINx = 32
Offset Error Temper-
ature Coefficient
(see Note 1)
SD16GAINx = 1
3 V
3 V
4
20
ppm
FSR/_C
dE /dT
OS
SD16GAINx = 32
20
100
SD16GAINx = 1, Common-mode input signal:
3 V
3 V
3 V
>90
>75
>80
V
ID
= 500 mV, f = 50 Hz, 100 Hz
IN
Common-Mode
Rejection Ratio
CMRR
PSRR
dB
dB
SD16GAINx = 32, Common-mode input signal:
= 16 mV, f = 50 Hz, 100 Hz
V
ID
IN
Power Supply
Rejection Ratio
SD16GAINx = 1
NOTES: 1. Not production tested, limits characterized.
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16_A, temperature sensor
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
Sensor temperature
coefficient
TC
See Note 1
See Note 1
1.18
1.32
1.46 mV/K
Sensor
V
Sensor offset voltage
−100
435
355
320
100
515
435
400
mV
mV
Offset,sensor
Temperature sensor voltage at T = 85°C
3 V
3 V
3 V
475
395
360
A
Sensor output voltage
(see Note 3)
Temperature sensor voltage at T = 25°C
V
A
Sensor
Temperature sensor voltage at T = 0°C (see Note 1)
A
NOTES: 1. Not production tested, limits characterized.
2. The following formula can be used to calculate the temperature sensor output voltage:
V
= TC
( 273 + T [°C] ) + V
[mV]
Sensor,typ
Sensor
Offset,sensor
3. Results based on characterization and/or production test, not TC
or V .
Offset,sensor
Sensor
SD16_A, built-in voltage reference
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
Internal reference
voltage
V
REF
SD16REFON = 1, SD16VMIDON = 0
3 V
1.14
1.20
1.26
V
Reference supply
current
I
SD16REFON = 1, SD16VMIDON = 0
SD16REFON = 1, SD16VMIDON = 0
3 V
3 V
175
260
µA
REF
TC
Temperature coefficient
18
50 ppm/K
nF
C
V
V
load capacitance
SD16REFON = 1, SD16VMIDON = 0 (see Note 1)
100
REF
REF
maximum load
REF(I)
I
SD16REFON = 1; SD16VMIDON = 0
3 V
200
nA
LOAD
current
SD16REFON = 0−>1; SD16VMIDON = 0;
t
Turn on time
3 V
3 V
5
ms
ON
C
= 100nF
REF
SD16REFON = 1; SD16VMIDON = 0
PSRR
Line regulation
10
uV/V
NOTES: 1. There is no capacitance required on V
voltage noise.
. However, a capacitance of at least 100nF is recommended to reduce any reference
REF
SD16_A, reference output buffer
PARAMETER
TEST CONDITIONS
V
MIN
TYP
1.2
MAX
UNIT
CC
Reference buffer output
V
SD16REFON = 1, SD16VMIDON = 1
3 V
V
REF,BUF
voltage
Reference Supply +
Reference output buffer
quiescent current
I
SD16REFON = 1, SD16VMIDON = 1
3 V
385
600
µA
REF,BUF
Required load
capacitance on V
REF
C
SD16REFON = 1, SD16VMIDON = 1
SD16REFON = 1, SD16VMIDON = 1
470
nF
mA
mV
µs
REF(O)
Maximum load current
on V
I
3 V
3 V
3 V
1
LOAD,Max
REF
Maximum voltage varia-
tion vs. load current
|I
| = 0 to 1mA
−15
+15
LOAD
SD16REFON = 0−>1; SD16VMIDON = 1;
t
Turn on time
100
ON
C
= 470nF
REF
SD16_A, external reference input
PARAMETER
TEST CONDITIONS
V
MIN
1.0
TYP
1.25
MAX
1.5
UNIT
V
CC
V
Input voltage range
Input current
SD16REFON = 0
SD16REFON = 0
3 V
REF(I)
I
3 V
50
nA
REF(I)
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, supply specifications
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
AV
AV
DV
,
CC =
CC
SS
AV
CC
Analog supply voltage
2.20
3.60
V
= DV
=0 V
SS
DAC12AMPx=2, DAC12IR=0,
DAC12_xDAT=0800h
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
50
50
110
110
DAC12AMPx=2, DAC12IR=1,
DAC12_xDAT=0800h, V
= AV
= AV
= AV
Supply Current
REF,DAC12
CC
CC
CC
I
µA
DD
(see Notes 1 and 2)
DAC12AMPx=5, DAC12IR=1,
DAC12_xDAT=0800h, V
200
700
440
REF,DAC12
DAC12AMPx=7, DAC12IR=1,
1500
DAC12_xDAT=0800h, V
REF,DAC12
Power supply
DAC12_xDAT = 800h, V
= 1.2V
REF,DAC12
PSRR
rejection ratio
2.7V
70
dB
∆AV
CC
= 100mV
(see Notes 3 and 4)
NOTES: 1. No load at the output pin assuming that the control bits for the shared pins are set properly.
2. Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input
specifications.
3. PSRR = 20*log{∆AV /∆V
}.
is applied externally. The internal reference is not used.
CC DAC12_xOUT
4.
V
REF
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (see Figure 12)
PARAMETER
TEST CONDITIONS
(12-bit Monotonic)
V = 1.2V
V
MIN
TYP
MAX
UNIT
CC
Resolution
12
bits
Integral nonlinearity
(see Note 1)
REF,DAC12
DAC12AMPx = 7, DAC12IR = 1
INL
2.7V
2.7V
2.0
0.4
8.0
1.0
LSB
LSB
Differential nonlinearity
(see Note 1)
V
= 1.2V
REF,DAC12
DAC12AMPx = 7, DAC12IR = 1
DNL
Offset voltage w/o
calibration
V
= 1.2V
REF,DAC12
DAC12AMPx = 7, DAC12IR = 1
2.7V
2.7V
2.7V
20
E
O
(see Notes 1, 2)
mV
Offset voltage with
calibration
V
= 1.2V
REF,DAC12
DAC12AMPx = 7, DAC12IR = 1
2.5
(see Notes 1, 2)
Offset error
d
/d
/d
E(O)
T
temperature coefficient
(see Note 1)
30
10
µV/C
E
Gain error (see Note 1)
V
= 1.2V
2.7V
2.7V
3.50 % FSR
G
REF,DAC12
Gain temperature
ppm of
FSR/°C
d
E(G)
T
coefficient (see Note 1)
DAC12AMPx=2
2.7V
2.7V
2.7V
100
Time for offset calibration
(see Note 3)
DAC12AMPx=3,5
DAC12AMPx=4,6,7
32
6
t
ms
Offset_Cal
NOTES: 1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and
“b” of the first order equation: y = a + b*x. V = E + (1 + E ) * (V /4095) * DAC12_xDAT, DAC12IR = 1.
DAC12_xOUT REF,DAC12
O
G
2. The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON
3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx
={0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may
effect accuracy and is not recommended.
DAC V
OUT
DAC Output
V
R+
R
=
Load
Ideal transfer
function
AV
CC
2
Offset Error
Positive
Gain Error
C
= 100pF
Load
Negative
DAC Code
Figure 12. Linearity Test Load Conditions and Gain/Offset Definition
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (continued)
TYPICAL INL ERROR
vs
DIGITAL INPUT DATA
4
V
= 2.2 V, V = 1.2V
REF
CC
DAC12AMPx = 7
DAC12IR = 1
3
2
1
0
−1
−2
−3
−4
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT − Digital Code
TYPICAL DNL ERROR
vs
DIGITAL INPUT DATA
2.0
1.5
V
= 2.2 V, V = 1.2V
REF
CC
DAC12AMPx = 7
DAC12IR = 1
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT − Digital Code
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, output specifications
PARAMETER
TEST CONDITIONS
No Load, V = AV
V
CC
MIN
TYP
MAX
UNIT
,
REF,DAC12 CC
DAC12_xDAT = 0h, DAC12IR = 1,
2.2V/3V
2.2V/3V
2.2V/3V
0
0.005
DAC12AMPx = 7
No Load, V
REF,DAC12
= AV ,
CC
DAC12_xDAT = 0FFFh, DAC12IR = 1,
AV −0.05
CC
AV
Output voltage
CC
DAC12AMPx = 7
range
V
O
V
(see Note 1,
Figure 15)
R
= 3 kΩ, V
Load REF,DAC12
= AV
CC
,
,
DAC12_xDAT = 0h, DAC12IR = 1,
0
0.1
DAC12AMPx = 7
R
= 3 kΩ, V
Load REF,DAC12
= AV
CC
DAC12_xDAT = 0FFFh, DAC12IR = 1,
2.2V/3V
2.2V/3V
AV −0.13
CC
AV
CC
DAC12AMPx = 7
Max DAC12
C
100
pF
L(DAC12)
load capacitance
2.2V
3V
−0.5
−1.0
+0.5
+1.0
Max DAC12
load current
I
mA
L(DAC12)
R
= 3 kΩ, V
< 0.3 V,
Load O/P(DAC12)
2.2V/3V
2.2V/3V
2.2V/3V
150
150
1
250
250
4
DAC12AMPx = 2, DAC12_xDAT = 0h
R
V
= 3 kΩ,
Load
Output
> AV −0.3 V
CC
R
Ω
Resistance
(see Figure 15)
O/P(DAC12)
O/P(DAC12)
DAC12_xDAT = 0FFFh
R
= 3 kΩ,
Load
0.3V ≤ V
≤ AV
CC
− 0.3V
O/P(DAC12)
NOTES: 1. Data is valid after the offset calibration of the output amplifier.
R
O/P(DAC12_x)
Max
R
Load
I
Load
AV
CC
DAC12
2
C
= 100pF
O/P(DAC12_x)
Min
Load
0.3
AV
−0.3V
V
CC
OUT
AV
CC
Figure 15. DAC12_x Output Resistance Tests
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
12-bit DAC, reference input specifications
PARAMETER
Reference input
TEST CONDITIONS
DAC12IR=0, (see Notes 1 and 2)
DAC12IR=1, (see Notes 3 and 4)
DAC12IR=0 , (see Note 5)
DAC12IR=1
V
MIN
TYP
MAX
UNIT
CC
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
AV /3 AV +0.2
CC CC
V
V
REF
voltage range
AV
CC
AV +0.2
CC
20
40
MΩ
kΩ
Reference input
resistance
Ri
(VREF)
48
56
NOTES: 1. For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AV ).
CC
2. The maximum voltage applied at reference input voltage terminal V
3. For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AV ).
= [AV
− V ] / [3*(1 + E )].
REF
CC
E(O) G
CC
4. The maximum voltage applied at reference input voltage terminal V
5. Characterized, not production tested
= [AV
CC
− V ] / (1 + E ).
E(O) G
REF
12-bit DAC, dynamic specifications; V
= AV , DAC12IR = 1 (see Figure 16 and Figure 17)
CC
REF,DAC12
PARAMETER
TEST CONDITIONS
DAC12AMPx=0 → {2, 3, 4}
DAC12AMPx=0 → {5, 6}
DAC12AMPx=0 → 7
DAC12AMPx=2
V
MIN
TYP
60
15
6
MAX
120
30
UNIT
CC
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
DAC12_xDAT = 800h,
DAC12 on-
Error
V(O)
(see Note 1,Figure 16)
< 0.5 LSB
t
t
t
µs
ON
time
12
100
40
15
5
200
80
Settling
DAC12_xDAT =
DAC12AMPx=3,5
DAC12AMPx=4,6,7
DAC12AMPx=2
µs
µs
S(FS)
S(C-C)
time,full-scale 80h→ F7Fh→ 80h
30
DAC12_xDAT =
Settling time,
DAC12AMPx=3,5
DAC12AMPx=4,6,7
DAC12AMPx=2
2
3F8h→ 408h→ 3F8h
code to code
BF8h→ C08h→ BF8h
1
0.05
0.35
1.5
0.12
0.7
2.7
10
10
15
DAC12_xDAT =
DAC12AMPx=3,5
DAC12AMPx=4,6,7
DAC12AMPx=2
SR
Slew Rate
V/µs
nV-s
80h→ F7Fh→ 80h
DAC12_xDAT =
DAC12AMPx=3,5
DAC12AMPx=4,6,7
Glitch energy: full-scale
80h→ F7Fh→ 80h
NOTES: 1. R
and C
Load
connected to AV
SS
(not AV /2) in Figure 16.
CC
Load
2. Slew rate applies to output voltage steps >= 200mV.
Conversion 1
Conversion 2
Conversion 3
+/− 1/2 LSB
V
+/− 1/2 LSB
DAC Output
OUT
Glitch
Energy
R
= 3 kΩ
Load
I
Load
AV
CC
2
C
= 100pF
Load
R
O/P(DAC12.x)
t
t
settleHL
settleLH
Figure 16. Settling Time and Glitch Energy Testing
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
Conversion 1
Conversion 2
Conversion 3
90%
V
OUT
90%
10%
10%
t
t
SRHL
SRLH
Figure 17. Slew Rate Testing
12-bit DAC, dynamic specifications continued (T = 25°C unless otherwise noted)
A
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
2.2V/3V
2.2V/3V
2.2V/3V
40
3-dB bandwidth,
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
180
550
BW
−3dB
kHz
V
=1.5V, V =0.1V
AC PP
DC
(see Figure 18)
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
NOTES: 1. R
= 3 kΩ, C = 100 pF
LOAD
LOAD
R
= 3 kΩ
Load
I
Load
Ve
REF+
AV
CC
DAC12_x
2
DACx
AC
DC
C
= 100pF
Load
Figure 18. Test Conditions for 3-dB Bandwidth Specification
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
Flash Memory
TEST
CONDITIONS
PARAMETER
V
CC
MIN NOM
MAX
UNIT
V
CC(PGM/
ERASE)
Program and Erase supply voltage
Flash Timing Generator frequency
2.5
3.6
V
f
I
I
t
t
257
476
5
kHz
mA
FTG
Supply current from DV
Supply current from DV
during program
during erase
2.5V/3.6V
2.5V/3.6V
2.5V/3.6V
2.5V/3.6V
3
PGM
CC
3
7
mA
ERASE
CPT
CC
Cumulative program time
see Note 1
see Note 2
10
ms
Cumulative mass erase time
Program/Erase endurance
Data retention duration
200
ms
CMErase
4
10
5
10
cycles
years
t
T = 25°C
J
100
Retention
t
t
t
t
t
t
Word or byte program time
35
30
Word
st
Block program time for 1 byte or word
Block, 0
Block program time for each additional byte or word
Block program end-sequence wait time
Mass erase time
21
Block, 1-63
Block, End
Mass Erase
Seg Erase
see Note 3
t
FTG
6
5297
4819
Segment erase time
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64−byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/f
FTG
,max = 5297x1/476kHz). To
achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controller’s state machine (t
FTG
= 1/f
FTG
).
JTAG Interface
TEST
CONDITIONS
PARAMETER
V
CC
MIN NOM
MAX
UNIT
2.2 V
3 V
0
0
5
10
90
MHz
MHz
kΩ
f
TCK input frequency
see Note 1
TCK
R
Internal pull-up resistance on TMS, TCK, TDI/TCLK see Note 2
may be restricted to meet the timing requirements of the module selected.
2.2 V/ 3 V
25
60
Internal
NOTES: 1. f
TCK
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG Fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
V
CC
MIN NOM
MAX
UNIT
V
V
Supply voltage during fuse-blow condition
Voltage level on TDI/TCLK for fuse-blow: F versions
Supply current into TDI/TCLK during fuse blow
Time to blow fuse
T
A
= 25°C
2.5
6
V
V
CC(FB)
7
100
1
FB
I
t
mA
ms
FB
FB
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
input/output schematics
Port P1 pin schematic: P1.0, P1.1, input/output with Schmitt−trigger
Pad Logic
DV
SS
DV
SS
DV
SS
P1DIR.x
0
1
Direction
0: Input
1: Output
0
1
P1OUT.x
Module X OUT
P1.0/TA0
P1.1/TA0/MCLK
Bus
P1SEL.x
Keeper
EN
P1IN.x
EN
D
Module X IN
P1IE.x
EN
P1IRQ.x
Q
Set
P1IFG.x
Interrupt
Edge
P1SEL.x
P1IES.x
Select
Note: x = 0,1
Port P1 (P1.0, P1.1) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
P1.0/TA0
X
FUNCTION
P1DIR.x
P1SEL.x
0
P1.0† Input/Output
Timer_A3.CCI0A
Timer_A3.TA0
P1.1† Input/Output
Timer_A3.CCI0B
MCLK
0/1
0
0
1
1
0
1
1
1
P1.1/TA0/MCLK
1
0/1
0
1
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P1 pin schematic: P1.2, input/output with Schmitt−trigger and analog functions
INCH=4
Pad Logic
0
1
AV
SS
A4−
SD16AE.x
P1DIR.x
0
1
Direction
0: Input
1: Output
P1OUT.x
0
1
Module X OUT
P1.2/TA1/A4−
Bus
P1SEL.x
Keeper
EN
P1IN.x
EN
D
Module X IN
P1IE.x
EN
P1IRQ.x
Q
Set
P1IFG.x
Interrupt
Edge
P1SEL.x
P1IES.x
Select
Note: x = 2
Port P1 (P1.2) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
P1DIR.x
P1SEL.x
SD16AE.x
P1.2/TA1/A4−
2
P1.2† Input/Output
Timer_A3.CCI1A
Timer_A3.TA1
0/1
0
0
1
1
X
0
0
0
1
1
A4− (see Notes 3, 4)
X
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the SD16AE.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. Negative input to SD16_A (A4−) connected to V
SS
if corresponding SD16AE.x bit is cleared.
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P1 pin schematic: P1.3, P1.5, P1.7, input/output with Schmitt−trigger and analog functions
INCH=y
Pad Logic
Ay+
SD16AE.x
P1DIR.x
0
1
Direction
0: Input
1: Output
0
1
P1OUT.x
Module X OUT
P1.3/TA2/A4+
P1.5/TACLK/ACLK/A3+
P1.7/A2+
Bus
P1SEL.x
Keeper
EN
P1IN.x
Module X IN
P1IRQ.x
EN
D
P1IE.x
EN
Q
Set
P1IFG.x
Interrupt
Edge
P1SEL.x
P1IES.x
Select
Note: x = 3,5,7
y = 4,3,2
40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P1 (P1.3, P1.5, P1.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
P1DIR.x
P1SEL.x
SD16AE.x
P1.3/TA2/A4+
3
P1.3† Input/Output
Timer_A3.CCI2A
Timer_A3.TA2
0/1
0
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
1
A4+ (see Note 3)
P1.5† Input/Output
X
P1.5/TACLK/ACLK/A3+
P1.7/A2+
5
7
0/1
0
Timer_A3.TACLK/INCLK
ACLK
1
A3+ (see Note 3)
P1.5† Input/Output
N/A
X
0/1
0
DVSS
1
A2+ (see Note 3)
X
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the SD16AE.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P1 pin schematic: P1.4, input/output with Schmitt−trigger and analog functions
INCH=3
A3−
Pad Logic
0
1
AV
SS
SD16AE.x
DAC12OPS
’1’ if DAC12AMPx>0
P1DIR.x
P1OUT.x
0
1
Direction
0: Input
1: Output
0
1
DV
SS
P1.4/A3−/DAC0
Bus
P1SEL.x
P1IN.x
Keeper
EN
DAC12OPS
P1IE.x
EN
DAC0
P1IRQ.x
Q
Set
P1IFG.x
Interrupt
Edge
P1SEL.x
P1IES.x
Select
Note: x = 4
Port P1 (P1.4) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
P1DIR.x
P1SEL.x
SD16AE.x
DAC12OPS
P1.4/A3−/DAC0
4
P1.4† Input/Output
N/A
0/1
0
0
1
0
0
0
1
X
0
0
0
0
1
DVSS
1
1
A3− (see Notes 3, 4)
DAC0 (see Note 5)
X
X
X
X
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the SD16AE.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. Negative input to SD16_A (A3−) connected to AV
if corresponding SD16AE.x bit is cleared.
SS
5. Setting the DAC12OPS bit also disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
42
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P1 pin schematic: P1.6, input/output with Schmitt−trigger and analog functions
INCH=2
Pad Logic
0
1
AV
SS
A2−
SD16AE.x
P1DIR.x
0
1
Direction
0: Input
1: Output
P1OUT.x
DV
0
1
SS
P1.6/A2−
Bus
P1SEL.x
Keeper
EN
P1IN.x
P1IE.x
EN
P1IRQ.x
Q
Set
P1IFG.x
Interrupt
Edge
P1SEL.x
P1IES.x
Select
Note: x = 6
Port P1 (P1.6) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
P1.6/A2−
X
FUNCTION
P1DIR.x
P1SEL.x
SD16AE.x
6
P1.6† Input/Output
N/A
0/1
0
0
1
1
X
0
0
0
1
DVSS
1
A2− (see Notes 3, 4)
X
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the SD16AE.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. Negative input to SD16_A (A2−) connected to AV
SS
if corresponding SD16AE.x bit is cleared.
43
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P2 pin schematic: P2.0 to P2.7, input/output with Schmitt−trigger, LCD and analog functions
Pad Logic
LCDS4/8/12
Segment Sy
DV
SS
P2DIR.x
0
1
Direction
0: Input
1: Output
0
1
P2OUT.x
DV
SS
P2.0/S13
P2.1/S12
P2.2/S11
P2.3/S10
P2.4/S9
P2.5/S8
P2.6/S7
P2.7/S6
Bus
P2SEL.x
Keeper
EN
P2IN.x
P2IE.x
EN
P2IRQ.x
Q
Set
P2IFG.x
Interrupt
Edge
P2SEL.x
P2IES.x
Select
Note: x = 0 to 7
y = 13 to 6
44
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P2 (P2.0 to P2.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.X)
P2.0/S13
X
FUNCTION
P2DIR.x
P2SEL.x
LCDS12
0
P2.0† Input/Output
0/1
0
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
N/A
DVSS
1
S13
X
P2.1/S12
P2.2/S11
P2.3/S10
P2.4/S9
P2.5/S8
P2.6/S7
P2.7/S6
1
2
3
4
5
6
7
P2.1† Input/Output
0/1
0
N/A
DVSS
1
S12
X
P2.2† Input/Output
0/1
0
N/A
DVSS
1
S11
X
P2.3† Input/Output
0/1
0
N/A
DVSS
1
S10
X
P2.4† Input/Output
0/1
0
N/A
DVSS
1
S9
X
P2.5† Input/Output
0/1
0
N/A
DVSS
1
S8
X
P2.6† Input/Output
0/1
0
N/A
DVSS
1
S7
X
P2.7† Input/Output
0/1
0
N/A
DVSS
S6
1
X
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
45
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P5 pin schematic: P5.0, P5.1, P5.5 to P5.7, input/output with Schmitt−trigger and LCD
functions
Pad Logic
LCDS0/4
Segment Sy
DV
SS
P5DIR.x
0
1
Direction
0: Input
1: Output
0
1
P5OUT.x
DV
SS
P5.0/S1
P5.1/S0
P5.5/S2
P5.6/S3
P5.7/S4
Bus
P5SEL.x
Keeper
EN
P5IN.x
Note: x = 0,1,5,6,7
y = 1,0,2,3,4
46
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P5 (P5.0, P5.1, P5.5, P5.6) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P5.X)
P5.0/S1
X
FUNCTION
P5DIR.x
P5SEL.x
LCDS0
0
P5.0† Input/Output
0/1
0
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
N/A
DVSS
1
S1
X
P5.1/S0
P5.5/S2
P5.6/S3
1
5
6
P5.1† Input/Output
0/1
0
N/A
DVSS
1
S0
X
P5.5† Input/Output
0/1
0
N/A
DVSS
1
S2
X
P5.6† Input/Output
0/1
0
N/A
DVSS
S3
1
X
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
Port P5 (P5.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P5.X)
P5.7/S4
X
FUNCTION
P5DIR.x
P5SEL.x
LCDS4
7
P5.7† Input/Output
0/1
0
0
1
1
X
0
0
0
1
N/A
DVSS
S4
1
X
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
47
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P5 pin schematic: P5.2 to P5.4, input/output with Schmitt−trigger and LCD functions
Pad Logic
LCD Signal
DV
SS
P5DIR.x
0
1
Direction
0: Input
1: Output
P5OUT.x
DV
0
1
SS
P5.2/COM1
P5.3/COM2
P5.4/COM3
Bus
P5SEL.x
Keeper
EN
P5IN.x
Note: x = 2 to 4
Port P5 (P5.2 to P5.4) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P5.X)
X
FUNCTION
P5DIR.x
P5SEL.x
P5.2/COM1
2
P5.2† Input/Output
COM1
0/1
X
0
1
0
1
0
1
P5.3/COM2
P5.4/COM3
3
4
P5.3† Input/Output
COM2
0/1
X
P5.4† Input/Output
COM3
0/1
X
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
48
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P6 pin schematic: P6.0, P6.2, input/output with Schmitt−trigger and analog functions
#
INCH=0/1
Pad Logic
#
Ay+
P6DIR.x
0
1
Direction
0: Input
1: Output
0
1
P6OUT.x
DV
SS
P6.0/A0+
P6.2/A1+
Bus
P6SEL.x
Keeper
EN
P6IN.x
Note: x = 0,2
y = 0,1
#
Signal from or to SD16
Port P6 (P6.0, P6.2) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X)
P6.0/A0+
X
FUNCTION
P6DIR.x
P6SEL.x
0
P6.0† Input/Output
A0+ (see Note 3)
P6.2† Input/Output
A1+ (see Note 3)
0/1
X
0
1
0
1
P6.2/A1+
2
0/1
X
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
49
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P6 pin schematic: P6.1, P6.3, input/output with Schmitt−trigger and analog functions
#
INCH=0/1
Pad Logic
#
Ay−
P6DIR.x
0
1
Direction
0: Input
1: Output
0
1
P6OUT.x
DV
SS
P6.1/A0−
P6.3/A1−
Bus
P6SEL.x
Keeper
EN
P6IN.x
Note: x = 1,3
y = 0,1
#
Signal from or to SD16
Port P6 (P6.1, P6.3) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X)
P6.1/A0−
X
FUNCTION
P6DIR.x
P6SEL.x
1
P6.1† Input/Output
A0− (see Note 3)
P6.3† Input/Output
A1− (see Note 3)
0/1
X
0
1
0
1
P6.3/A1−
3
0/1
X
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
50
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
Port P6 pin schematic: P6.4 to P6.7, input/output with Schmitt−trigger and analog functions
Pad Logic
P6DIR.x
0
1
Direction
0: Input
1: Output
0
1
P6OUT.x
DV
SS
P6.4
P6.5
P6.6
P6.7
Bus
P6SEL.x
Keeper
EN
P6IN.x
Note: x = 4 to 7
Port P6 (P6.4 to P6.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X)
P6.4
X
FUNCTION
P6DIR.x
P6SEL.x
4
P6.4† Input/Output
0/1
0
0
1
1
0
1
1
0
1
1
0
1
1
N/A
DVSS
1
P6.5
P6.6
P6.7
5
6
7
P6.5† Input/Output
0/1
0
N/A
DVSS
1
P6.6† Input/Output
0/1
0
N/A
DVSS
1
P6.7† Input/Output
0/1
0
N/A
DVSS
1
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
51
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈꢅ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output
TDO
Controlled by JTAG
Controlled by JTAG
TDO/TDI
JTAG
Controlled
DV
CC
by JTAG
TDI
Burn and Test
Fuse
TDI/TCLK
CC
Test
and
DV
TMS
TCK
Emulation
Module
TMS
DV
CC
TCK
RST/NMI
Tau ~ 50 ns
Brownout
D
U
S
G
D
U
S
TCK
G
52
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢃ ꢇꢈ ꢅ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS455C − MARCH 2005 − REVISED AUGUST 2005
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current (I
) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be
(TF)
taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see
Figure 19). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition). The JTAG pins are terminated internally and therefore do not require external termination.
Time TMS Goes Low After POR
TMS
I
(TF)
I
TDI/TCLK
Figure 19. Fuse Check Mode Current
53
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
30-Aug-2005
PACKAGING INFORMATION
Orderable Device
MSP430F4250IDL
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DL
48
48
48
48
48
48
48
48
48
48
48
48
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
MSP430F4250IDLR
MSP430F4250IRGZR
MSP430F4250IRGZT
MSP430F4260IDL
SSOP
QFN
DL
RGZ
RGZ
DL
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP
SSOP
QFN
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
MSP430F4260IDLR
MSP430F4260IRGZR
MSP430F4260IRGZT
MSP430F4270IDL
DL
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
RGZ
RGZ
DL
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP
SSOP
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
MSP430F4270IDLR
MSP430F4270IRGZR
MSP430F4270IRGZT
DL
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
RGZ
RGZ
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明