MSP430F46161IPZ [TI]
MIXED SIGNAL MICROCONTROLLER; 混合信号微控制器
| 型号： | MSP430F46161IPZ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MIXED SIGNAL MICROCONTROLLER |
| 文件： | 总92页 (文件大小：1366K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
SLAS675 − OCTOBER 2009
D
D
Low Supply Voltage Range: 1.8 V to 3.6 V
D
D
Universal Serial Communication Interface
− Enhanced UART Supporting
Auto-Baudrate Detection
Ultralow-Power Consumption:
− Active Mode: 400 µA at 1 MHz, 2.2 V
− Standby Mode: 1.3 µA
− Off Mode (RAM Retention): 0.22 µA
Five Power-Saving Modes
− IrDA Encoder and Decoder
− Synchronous SPI
TM
− I2C
D
D
Serial Onboard Programming,
Programmable Code Protection by Security
Fuse
Wake-Up From Standby Mode in Less
Than 6 µs
16-Bit RISC Architecture, Extended
Memory, 125-ns Instruction Cycle Time
D
D
D
Brownout Detector
Family Members Include:
− MSP430x4616, MSP430x46161 :
D
D
Three Channel Internal DMA
†
12-Bit A/D Converter With Internal
Reference, Sample-and-Hold and Autoscan
Feature (MSP430x461x only)
92KB+256B Flash or ROM Memory
4KB RAM
†
− MSP430x4617, MSP430x46171 :
D
D
16-Bit Timer_A With Three
Capture/Compare Registers
92KB+256B Flash or ROM Memory,
8KB RAM
− MSP430x4618, MSP430x46181 :
†
16-Bit Timer_B With Seven
Capture/Compare-With-Shadow Registers
116KB+256B Flash or ROM Memory,
8KB RAM
D
D
On-Chip Comparator
†
− MSP430x4619, MSP430x46191 :
Supply Voltage Supervisor/Monitor With
Programmable Level Detection
120KB+256B Flash or ROM Memory,
4KB RAM
D
D
Basic Timer With Real Time Clock Feature
D
For Complete Module Descriptions, Refer
to the MSP430x4xx Family User’s Guide
Integrated LCD Driver up to 160 Segments
With Regulated Charge Pump
†
The MSP430F461x1 devices are identical to the MSP430F461x
devices, with the exception that the ADC12 module is not
implemented.
D
Serial Communication Interface (USART1),
Select Asynchronous UART or
Synchronous SPI by Software
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The devices feature
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6 µs.
The MSP430x461x(1) series are microcontroller configurations with two 16-bit timers, a high-performance
12-bit A/D converter (MSP430x461x only), one universal serial communication interface (USCI), one universal
synchronous/asynchronous communication interface (USART), DMA, 80 I/O pins, and a liquid crystal display
(LCD) driver with regulated charge pump.
Typical applications for this device include portable medical applications and e-meter applications.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2009, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
{
AVAILABLE OPTIONS
PACKAGED DEVICES
PLASTIC 100-PIN TQFP (PZ)
}
T
A
MSP430F4616IPZ
MSP430F46161IPZ
MSP430F46171IPZ
MSP430F46181IPZ
MSP430F46191IPZ
MSP430F4617IPZ
MSP430F4618IPZ
MSP430F4619IPZ
−40°C to 85°C
†
‡
For the most current package and ordering information, see the Package Option
Addendum at the end of this document, or see the TI web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at
www.ti.com/packaging.
DEVELOPMENT TOOL SUPPORT
All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging
and programming through easy to use development tools. Recommended hardware options include the
following:
D
Debugging and Programming Interface
−
−
MSP-FET430UIF (USB)
MSP-FET430PIF (Parallel Port)
D
D
D
Debugging and Programming Interface with Target Board
MSP-FET430U100
Stand-Alone Target Board
MSP-TS430PZ100
Production Programmer
MSP-GANG430
−
−
−
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
pin designation, MSP430x461xIPZ
1
2
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DV
P2.4/UCA0TXD
P2.5/UCA0RXD
P2.6/CAOUT
P2.7/ADC12CLK/DMAE0
P3.0/UCB0STE
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK
P3.4/TB3
CC1
P6.3/A3
P6.4/A4
P6.5/A5
3
4
5
P6.6/A6
P6.7/A7/SVSIN
VREF+
6
7
8
XIN
XOUT
VeREF+
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P3.5/TB4
VREF−/VeREF−
P5.1/S0/A12
P5.0/S1/A13
P10.7/S2/A14
P10.6/S3/A15
P10.5/S4
P10.4/S5
P10.3/S6
P10.2/S7
P10.1/S8
P10.0/S9
P9.7/S10
P9.6/S11
P3.6/TB5
P3.7/TB6
P4.0/UTXD1
MSP430x4616IPZ
MSP430x4617IPZ
MSP430x4618IPZ
MSP430x4619IPZ
P4.1/URXD1
DV
DV
SS2
CC2
LCDCAP/R33
P5.7/R23
P5.6/LCDREF/R13
P5.5/R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P9.5/S12
P9.4/S13
P4.2/STE1/S39
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
pin designation, MSP430x461x1IPZ
1
2
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DV
P2.4/UCA0TXD
P2.5/UCA0RXD
P2.6/CAOUT
CC1
P6.3
P6.4
P6.5
3
4
P2.7/DMAE0
5
P6.6
P3.0/UCB0STE
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK
P3.4/TB3
6
P6.7/SVSIN
Reserved
XIN
7
8
XOUT
DV
DV
P5.1/S0
P5.0/S1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P3.5/TB4
SS
P3.6/TB5
P3.7/TB6
P4.0/UTXD1
SS
MSP430x46161IPZ
MSP430x46171IPZ
MSP430x46181IPZ
MSP430x46191IPZ
P10.7/S2
P10.6/S3
P10.5/S4
P10.4/S5
P10.3/S6
P10.2/S7
P10.1/S8
P10.0/S9
P9.7/S10
P9.6/S11
P9.5/S12
P9.4/S13
P4.1/URXD1
DV
DV
SS2
CC2
LCDCAP/R33
P5.7/R23
P5.6/LCDREF/R13
P5.5/R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/STE1/S39
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
MSP430x461x functional block diagram
XIN/ XOUT/
XT2IN XT2OUT
P3. x/P4.x
P5. x/P6.x
P7.x/P8.x
P9.x/P10.x
DVCC1/2 DVSS1/2
AVCC
AVSS
P1.x/P2.x
2x8
2
2
4x8
4x8/2x16
Flash(F)
ROM(C)
ACLK
RAM
Ports
P3/P4
P5/P6
Ports
P7/P8
P9/P10
Oscillators
FLL+
ADC12
12−Bit
Ports P1/P2
4kB
8kB
8kB
4kB
Comparator
_A
SMCLK
120kB
116kB
92kB
2x8 I/O
Interrupt
capability
12
Channels
4x8 I/O
4x8/2x16 I/O
MCLK
92kB
MAB
8MHz
CPUX
DMA
Controller
incl. 16
Registers
3 Channels
MDB
Enhanced
Emulation
(F only)
Hardware
Multiplier
Timer_B7
USCI_A0:
UART,
LCD_A
USART1
Brownout
Protection
Watchdog
WDT+
Timer_A3
Basic Timer
&
Real−Time
Clock
7 CC
Registers,
Shadow
Reg
IrDA, SPI
MPY,
MPYS,
MAC,
160
Segments
1, 2,3,4 Mux
UART, SPI
JTAG
Interface
3 CC
Registers
USCI_B0:
SPI, I2C
SVS/SVM
15/16−Bit
MACS
RST/NMI
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
MSP430x461x1 functional block diagram
XIN/ XOUT/
XT2IN XT2OUT
P3. x/P4.x
P5. x/P6.x
P7.x/P8.x
P9.x/P10.x
DVCC1/2 DVSS1/2
AVCC
AVSS
P1.x/P2.x
2x8
2
2
4x8
4x8/2x16
Flash(F)
ROM(C)
ACLK
RAM
Ports
P3/P4
P5/P6
Ports
P7/P8
P9/P10
Oscillators
FLL+
Ports P1/P2
4kB
8kB
8kB
4kB
Comparator
_A
SMCLK
120kB
116kB
92kB
2x8 I/O
Interrupt
capability
4x8 I/O
4x8/2x16 I/O
MCLK
92kB
MAB
8MHz
CPUX
DMA
Controller
incl. 16
Registers
3 Channels
MDB
Enhanced
Emulation
(F only)
Hardware
Multiplier
Timer_B7
USCI_A0:
UART,
LCD_A
USART1
Brownout
Protection
Watchdog
WDT+
Timer_A3
Basic Timer
&
Real−Time
Clock
7 CC
Registers,
Shadow
Reg
IrDA, SPI
MPY,
MPYS,
MAC,
160
Segments
1, 2,3,4 Mux
UART, SPI
JTAG
Interface
3 CC
Registers
USCI_B0:
SPI, I2C
SVS/SVM
15/16−Bit
MACS
RST/NMI
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
MSP430x461x Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
Digital supply voltage, positive terminal
NO.
1
DV
CC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
2
I/O General-purpose digital I/O / analog input a3—12-bit ADC
I/O General-purpose digital I/O / analog input a4—12-bit ADC
I/O General-purpose digital I/O / analog input a5—12-bit ADC
I/O General-purpose digital I/O / analog input a6—12-bit ADC
3
4
5
General-purpose digital I/O / analog input a7—12-bit ADC / analog input to brownout,
supply voltage supervisor
P6.7/A7/SVSIN
6
I/O
V
7
8
O
I
Output of positive terminal of the reference voltage in the ADC
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
Output terminal of crystal oscillator XT1
REF+
XIN
XOUT
9
O
Ve
REF+
10
I/O Input for an external reference voltage to the ADC
Negative terminal for the ADC reference voltage for both sources, the internal reference
voltage, or an external applied reference voltage
V
REF−
/Ve
11
I
REF−
P5.1/S0/A12 (see Note 1)
P5.0/S1/A13 (see Note 1)
P10.7/S2/A14 (see Note 1)
P10.6/S3/A15 (see Note 1)
P10.5/S4
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
I/O General-purpose digital I/O / LCD segment output 0 / analog input a12 − 12−bit ADC
I/O General-purpose digital I/O / LCD segment output 1 / analog input a13 − 12−bit ADC
I/O General-purpose digital I/O / LCD segment output 2 / analog input a14 − 12−bit ADC
I/O General-purpose digital I/O / LCD segment output 3 / analog input a15 − 12−bit ADC
I/O General-purpose digital I/O / LCD segment output 4
P10.4/S5
I/O General-purpose digital I/O / LCD segment output 5
P10.3/S6
I/O General-purpose digital I/O / LCD segment output 6
P10.2/S7
I/O General-purpose digital I/O / LCD segment output 7
P10.1/S8
I/O General-purpose digital I/O / LCD segment output 8
P10.0/S9
I/O General-purpose digital I/O / LCD segment output 9
P9.7/S10
I/O General-purpose digital I/O / LCD segment output 10
I/O General-purpose digital I/O / LCD segment output 11
I/O General-purpose digital I/O / LCD segment output 12
I/O General-purpose digital I/O / LCD segment output 13
I/O General-purpose digital I/O / LCD segment output 14
I/O General-purpose digital I/O / LCD segment output 15
I/O General-purpose digital I/O / LCD segment output 16
I/O General-purpose digital I/O / LCD segment output 17
I/O General-purpose digital I/O / LCD segment output 18
I/O General-purpose digital I/O / LCD segment output 19
I/O General-purpose digital I/O / LCD segment output 20
I/O General-purpose digital I/O / LCD segment output 21
I/O General-purpose digital I/O / LCD segment output 22
P9.6/S11
P9.5/S12
P9.4/S13
P9.3/S14
P9.2/S15
P9.1/S16
P9.0/S17
P8.7/S18
P8.6/S19
P8.5/S20
P8.4/S21
P8.3/S22
NOTE 1: Segments S0 through S3 are disabled when the LCD charge pump feature is enabled (LCDCPEN = 1) and cannot be used together
with the LCD charge pump. In addition, when using segments S0 through S3 with an external LCD voltage supply, V
≤ AV
.
LCD
CC
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
NO.
35
36
37
38
39
40
41
P8.2/S23
P8.1/S24
P8.0/S25
P7.7/S26
P7.6/S27
P7.5/S28
P7.4/S29
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O / LCD segment output 23
General-purpose digital I/O / LCD segment output 24
General-purpose digital I/O / LCD segment output 25
General-purpose digital I/O / LCD segment output 26
General-purpose digital I/O / LCD segment output 27
General-purpose digital I/O / LCD segment output 28
General-purpose digital I/O / LCD segment output 29
General-purpose digital I/O / external clock input − USCI_A0/UART or SPI mode, clock output
− USCI_A0/SPI mode / LCD segment 30
P7.3/UCA0CLK/S30
42
I/O
P7.2/UCA0SOMI/S31
P7.1/UCA0SIMO/S32
43
44
I/O
I/O
General-purpose digital I/O / slave out/master in of USCI_A0/SPI mode / LCD segment output 31
General-purpose digital I/O / slave in/master out of USCI_A0/SPI mode / LCD segment output 32
General-purpose digital I/O / slave transmit enable—USCI_A0/SPI mode / LCD segment
output 33
P7.0/UCA0STE/S33
P4.7/UCA0RXD/S34
P4.6/UCA0TXD/S35
P4.5/UCLK1/S36
45
46
47
48
I/O
I/O
I/O
I/O
General-purpose digital I/O / receive data in − USCI_A0/UART or IrDA mode / LCD segment
output 34
General-purpose digital I/O / transmit data out − USCI_A0/UART or IrDA mode / LCD segment
output 35
General-purpose digital I/O / external clock input − USART1/UART or SPI mode, clock output
− USART1/SPI MODE / LCD segment output 36
P4.4/SOMI1/S37
P4.3/SIMO1/S38
49
50
I/O
I/O
General-purpose digital I/O / slave out/master in of USART1/SPI mode / LCD segment output 37
General-purpose digital I/O / slave in/master out of USART1/SPI mode / LCD segment output 38
General-purpose digital I/O / slave transmit enable—USART1/SPI mode / LCD segment
output 39
P4.2/STE1/S39
51
I/O
COM0
52
53
54
55
56
O
COM0−3 are used for LCD backplanes.
P5.2/COM1
P5.3/COM2
P5.4/COM3
P5.5/R03
I/O
I/O
I/O
I/O
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
General-purpose digital I/O / Input port of lowest analog LCD level (V5)
General-purpose digital I/O / External reference voltage input for regulated LCD voltage / Input
port of third most positive analog LCD level (V4 or V3)
P5.6/LCDREF/R13
57
I/O
P5.7/R23
58
59
60
61
62
63
I/O
I
General-purpose digital I/O / Input port of second most positive analog LCD level (V2)
LCD capacitor connection / Input/output port of most positive analog LCD level (V1)
Digital supply voltage, positive terminal
LCDCAP/R33
DV
DV
CC2
SS2
Digital supply voltage, negative terminal
P4.1/URXD1
P4.0/UTXD1
I/O
I/O
General-purpose digital I/O / receive data in—USART1/UART mode
General-purpose digital I/O / transmit data out—USART1/UART mode
General-purpose digital I/O / Timer_B7 CCR6. Capture: CCI6A/CCI6B input, compare: Out6
output
P3.7/TB6
P3.6/TB5
P3.5/TB4
64
65
66
I/O
I/O
I/O
General-purpose digital I/O / Timer_B7 CCR5. Capture: CCI5A/CCI5B input, compare: Out5
output
General-purpose digital I/O / Timer_B7 CCR4. Capture: CCI4A/CCI4B input, compare: Out4
output
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
NO.
P3.4/TB3
67
I/O General-purpose digital I/O / Timer_B7 CCR3. Capture: CCI3A/CCI3B input, compare: Out3 output
General-purpose digital I/O / external clock input—USCI_B0/UART or SPI mode, clock
output—USCI_B0/SPI mode
P3.3/UCB0CLK
68
69
I/O
P3.2/UCB0SOMI/
UCB0SCL
General-purpose digital I/O / slave out/master in of USCI_B0/SPI mode /I2C clock—USCI_B0/I2C
mode
I/O
P3.1/UCB0SIMO/
UCB0SDA
General-purpose digital I/O / slave in/master out of USCI_B0/SPI mode, I2C data—USCI_B0/I2C
mode
70
71
72
I/O
P3.0/UCB0STE
I/O General-purpose digital I/O / slave transmit enable—USCI_B0/SPI mode
P2.7/ADC12CLK/
DMAE0
I/O General-purpose digital I/O / conversion clock—12-bit ADC / DMA Channel 0 external trigger
P2.6/CAOUT
P2.5/UCA0RXD
P2.4/UCA0TXD
P2.3/TB2
73
74
75
76
77
78
79
80
81
I/O General-purpose digital I/O / Comparator_A output
I/O General-purpose digital I/O / receive data in—USCI_A0/UART or IrDA mode
I/O General-purpose digital I/O / transmit data out—USCI_A0/UART or IrDA mode
I/O General-purpose digital I/O / Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output
I/O General-purpose digital I/O / Timer_B7 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output
I/O General-purpose digital I/O / Timer_B7 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output
I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output
I/O General-purpose digital I/O / Comparator_A input
P2.2/TB1
P2.1/TB0
P2.0/TA2
P1.7/CA1
P1.6/CA0
I/O General-purpose digital I/O / Comparator_A input
General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by 1, 2, 4,
or 8)
P1.5/TACLK/ACLK
P1.4/TBCLK/SMCLK
P1.3/TBOUTH/SVSOUT
P1.2/TA1
82
83
84
85
86
I/O
I/O General-purpose digital I/O / input clock TBCLK—Timer_B7 / submain system clock SMCLK output
General-purpose digital I/O / switch all PWM digital output ports to high impedance—Timer_B7 TB0
to TB6 / SVS: output of SVS comparator
I/O
I/O General-purpose digital I/O / Timer_A, Capture: CCI1A input, compare: Out1 output
General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK output.
Note: TA0 is only an input on this pin / BSL receive
P1.1/TA0/MCLK
I/O
P1.0/TA0
XT2OUT
XT2IN
87
88
89
90
91
92
93
94
95
96
97
98
99
I/O General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL transmit
O
I
Output terminal of crystal oscillator XT2
Input port for crystal oscillator XT2. Only standard crystals can be connected.
TDO/TDI
TDI/TCLK
TMS
I/O Test data output port. TDO/TDI data output or programming data input terminal
I
I
I
I
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
Test mode select. TMS is used as an input port for device programming and test.
Test clock. TCK is the clock input port for device programming and test.
Reset input or nonmaskable interrupt input port
TCK
RST/NMI
P6.0/A0
P6.1/A1
P6.2/A2
I/O General-purpose digital I/O / analog input a0—12-bit ADC
I/O General-purpose digital I/O / analog input a1—12-bit ADC
I/O General-purpose digital I/O / analog input a2—12-bit ADC
AV
Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, comparator_A, port 1
Digital supply voltage, negative terminal
SS
DV
SS1
Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_A, port 1;
AV
100
CC
must not power up prior to DV
/DV
.
CC1
CC2
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
MSP430x461x1 Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
Digital supply voltage, positive terminal
NO.
1
DV
CC1
P6.3
2
I/O General-purpose digital I/O
I/O General-purpose digital I/O
I/O General-purpose digital I/O
I/O General-purpose digital I/O
P6.4
3
P6.5
4
P6.6
5
P6.7/SVSIN
Reserved
XIN
6
I/O General-purpose digital I/O / analog input to brownout, supply voltage supervisor
7
O
I
Reserved, do not connect externally
8
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
Output terminal of crystal oscillator XT1
XOUT
9
O
DV
DV
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
I/O Connect to DV
SS
SS
SS
SS
I
Connect to DV
P5.1/S0 (see Note 2)
P5.0/S1 (see Note 2)
P10.7/S2 (see Note 2)
P10.6/S3 (see Note 2)
P10.5/S4
I/O General-purpose digital I/O / LCD segment output 0
I/O General-purpose digital I/O / LCD segment output 1
I/O General-purpose digital I/O / LCD segment output 2
I/O General-purpose digital I/O / LCD segment output 3
I/O General-purpose digital I/O / LCD segment output 4
I/O General-purpose digital I/O / LCD segment output 5
I/O General-purpose digital I/O / LCD segment output 6
I/O General-purpose digital I/O / LCD segment output 7
I/O General-purpose digital I/O / LCD segment output 8
I/O General-purpose digital I/O / LCD segment output 9
I/O General-purpose digital I/O / LCD segment output 10
I/O General-purpose digital I/O / LCD segment output 11
I/O General-purpose digital I/O / LCD segment output 12
I/O General-purpose digital I/O / LCD segment output 13
I/O General-purpose digital I/O / LCD segment output 14
I/O General-purpose digital I/O / LCD segment output 15
I/O General-purpose digital I/O / LCD segment output 16
I/O General-purpose digital I/O / LCD segment output 17
I/O General-purpose digital I/O / LCD segment output 18
I/O General-purpose digital I/O / LCD segment output 19
I/O General-purpose digital I/O / LCD segment output 20
I/O General-purpose digital I/O / LCD segment output 21
I/O General-purpose digital I/O / LCD segment output 22
P10.4/S5
P10.3/S6
P10.2/S7
P10.1/S8
P10.0/S9
P9.7/S10
P9.6/S11
P9.5/S12
P9.4/S13
P9.3/S14
P9.2/S15
P9.1/S16
P9.0/S17
P8.7/S18
P8.6/S19
P8.5/S20
P8.4/S21
P8.3/S22
NOTE 2: Segments S0 through S3 are disabled when the LCD charge pump feature is enabled (LCDCPEN = 1) and cannot be used together
with the LCD charge pump. In addition, when using segments S0 through S3 with an external LCD voltage supply, V
≤ AV
.
LCD
CC
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
NO.
35
36
37
38
39
40
41
P8.2/S23
P8.1/S24
P8.0/S25
P7.7/S26
P7.6/S27
P7.5/S28
P7.4/S29
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O / LCD segment output 23
General-purpose digital I/O / LCD segment output 24
General-purpose digital I/O / LCD segment output 25
General-purpose digital I/O / LCD segment output 26
General-purpose digital I/O / LCD segment output 27
General-purpose digital I/O / LCD segment output 28
General-purpose digital I/O / LCD segment output 29
General-purpose digital I/O / external clock input − USCI_A0/UART or SPI mode, clock output
− USCI_A0/SPI mode / LCD segment 30
P7.3/UCA0CLK/S30
42
I/O
P7.2/UCA0SOMI/S31
P7.1/UCA0SIMO/S32
43
44
I/O
I/O
General-purpose digital I/O / slave out/master in of USCI_A0/SPI mode / LCD segment output 31
General-purpose digital I/O / slave in/master out of USCI_A0/SPI mode / LCD segment output 32
General-purpose digital I/O / slave transmit enable—USCI_A0/SPI mode / LCD segment
output 33
P7.0/UCA0STE/S33
P4.7/UCA0RXD/S34
P4.6/UCA0TXD/S35
P4.5/UCLK1/S36
45
46
47
48
I/O
I/O
I/O
I/O
General-purpose digital I/O / receive data in − USCI_A0/UART or IrDA mode / LCD segment
output 34
General-purpose digital I/O / transmit data out − USCI_A0/UART or IrDA mode / LCD segment
output 35
General-purpose digital I/O / external clock input − USART1/UART or SPI mode, clock output
− USART1/SPI MODE / LCD segment output 36
P4.4/SOMI1/S37
P4.3/SIMO1/S38
49
50
I/O
I/O
General-purpose digital I/O / slave out/master in of USART1/SPI mode / LCD segment output 37
General-purpose digital I/O / slave in/master out of USART1/SPI mode / LCD segment output 38
General-purpose digital I/O / slave transmit enable—USART1/SPI mode / LCD segment
output 39
P4.2/STE1/S39
51
I/O
COM0
52
53
54
55
56
O
COM0−3 are used for LCD backplanes.
P5.2/COM1
P5.3/COM2
P5.4/COM3
P5.5/R03
I/O
I/O
I/O
I/O
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
General-purpose digital I/O / Input port of lowest analog LCD level (V5)
General-purpose digital I/O / External reference voltage input for regulated LCD voltage / Input
port of third most positive analog LCD level (V4 or V3)
P5.6/LCDREF/R13
57
I/O
P5.7/R23
58
59
60
61
62
63
I/O
I
General-purpose digital I/O / Input port of second most positive analog LCD level (V2)
LCD capacitor connection / Input/output port of most positive analog LCD level (V1)
Digital supply voltage, positive terminal
LCDCAP/R33
DV
DV
CC2
SS2
Digital supply voltage, negative terminal
P4.1/URXD1
P4.0/UTXD1
I/O
I/O
General-purpose digital I/O / receive data in—USART1/UART mode
General-purpose digital I/O / transmit data out—USART1/UART mode
General-purpose digital I/O / Timer_B7 CCR6. Capture: CCI6A/CCI6B input, compare: Out6
output
P3.7/TB6
P3.6/TB5
P3.5/TB4
64
65
66
I/O
I/O
I/O
General-purpose digital I/O / Timer_B7 CCR5. Capture: CCI5A/CCI5B input, compare: Out5
output
General-purpose digital I/O / Timer_B7 CCR4. Capture: CCI4A/CCI4B input, compare: Out4
output
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
NO.
P3.4/TB3
67
I/O General-purpose digital I/O / Timer_B7 CCR3. Capture: CCI3A/CCI3B input, compare: Out3 output
General-purpose digital I/O / external clock input—USCI_B0/UART or SPI mode, clock
output—USCI_B0/SPI mode
P3.3/UCB0CLK
68
69
I/O
P3.2/UCB0SOMI/
UCB0SCL
General-purpose digital I/O / slave out/master in of USCI_B0/SPI mode /I2C clock—USCI_B0/I2C
mode
I/O
P3.1/UCB0SIMO/
UCB0SDA
General-purpose digital I/O / slave in/master out of USCI_B0/SPI mode, I2C data—USCI_B0/I2C
mode
70
71
72
I/O
P3.0/UCB0STE
I/O General-purpose digital I/O / slave transmit enable—USCI_B0/SPI mode
P2.7/ADC12CLK/
DMAE0
I/O General-purpose digital I/O / conversion clock—12-bit ADC / DMA Channel 0 external trigger
P2.6/CAOUT
P2.5/UCA0RXD
P2.4/UCA0TXD
P2.3/TB2
73
74
75
76
77
78
79
80
81
I/O General-purpose digital I/O / Comparator_A output
I/O General-purpose digital I/O / receive data in—USCI_A0/UART or IrDA mode
I/O General-purpose digital I/O / transmit data out—USCI_A0/UART or IrDA mode
I/O General-purpose digital I/O / Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output
I/O General-purpose digital I/O / Timer_B7 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output
I/O General-purpose digital I/O / Timer_B7 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output
I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output
I/O General-purpose digital I/O / Comparator_A input
P2.2/TB1
P2.1/TB0
P2.0/TA2
P1.7/CA1
P1.6/CA0
I/O General-purpose digital I/O / Comparator_A input
General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by 1, 2, 4,
or 8)
P1.5/TACLK/ACLK
P1.4/TBCLK/SMCLK
P1.3/TBOUTH/SVSOUT
P1.2/TA1
82
83
84
85
86
I/O
I/O General-purpose digital I/O / input clock TBCLK—Timer_B7 / submain system clock SMCLK output
General-purpose digital I/O / switch all PWM digital output ports to high impedance—Timer_B7 TB0
to TB6 / SVS: output of SVS comparator
I/O
I/O General-purpose digital I/O / Timer_A, Capture: CCI1A input, compare: Out1 output
General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK output.
Note: TA0 is only an input on this pin / BSL receive
P1.1/TA0/MCLK
I/O
P1.0/TA0
XT2OUT
XT2IN
TDO/TDI
TDI/TCLK
TMS
87
88
89
90
91
92
93
94
95
96
97
98
99
I/O General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL transmit
O
I
Output terminal of crystal oscillator XT2
Input port for crystal oscillator XT2. Only standard crystals can be connected.
I/O Test data output port. TDO/TDI data output or programming data input terminal
I
I
I
I
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
Test mode select. TMS is used as an input port for device programming and test.
Test clock. TCK is the clock input port for device programming and test.
Reset input or nonmaskable interrupt input port
TCK
RST/NMI
P6.0
I/O General-purpose digital I/O
P6.1
I/O General-purpose digital I/O
P6.2
I/O General-purpose digital I/O
AV
Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, comparator_A, port 1
Digital supply voltage, negative terminal
SS
DV
SS1
Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_A, port 1;
AV
100
CC
must not power up prior to DV
/DV
.
CC1
CC2
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture that is
highly transparent to the application. All operations, other
than program-flow instructions, are performed as register
operations in conjunction with seven addressing modes for
source operand and four addressing modes for destination
operand.
Program Counter
Stack Pointer
PC/R0
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
R4
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-to-register
operation execution time is one cycle of the CPU clock.
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
R5
Four of the registers, R0 to R3, are dedicated as program
counter, stack pointer, status register, and constant
generator respectively. The remaining registers are
general-purpose registers.
R6
R7
Peripherals are connected to the CPU using data, address,
and control buses, and can be handled with all instructions.
R8
R9
The MSP430x461x(1) device family uses the MSP430X
CPU and is completely backward compatible with the
MSP430 CPU. For a complete description of the MSP430X
CPU, see the MSP430x4xx Family User’s Guide.
R10
R11
instruction set
The instruction set consists of the original 51 instructions
with three formats and seven address modes and additional
instructions for the expanded address range. Each
instruction can operate on word and byte data. Table 1
shows examples of the three types of instruction formats;
Table 2 shows the address modes.
R12
R13
R14
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
e.g., ADD R4,R5
R4 + R5 −−−> R5
e.g., CALL
e.g., JNE
R8
PC −−>(TOS), R8−−> PC
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
Register
S
D
SYNTAX
MOV Rs,Rd
EXAMPLE
MOV R10,R11
MOV 2(R5),6(R6)
OPERATION
F
F
F
F
F
F
F
F
F
R10 —> R11
Indexed
MOV X(Rn),Y(Rm)
MOV EDE,TONI
MOV & MEM, & TCDAT
MOV @Rn,Y(Rm)
M(2+R5)—> M(6+R6)
M(EDE) —> M(TONI)
M(MEM) —> M(TCDAT)
M(R10) —> M(Tab+R6)
Symbolic (PC relative)
Absolute
Indirect
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
Indirect
autoincrement
M(R10) —> R11
R10 + 2—> R10
F
MOV @Rn+,Rm
Immediate
F
MOV #X,TONI
#45 —> M(TONI)
NOTE: S = source
D = destination
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
operating modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D
Active mode (AM)
All clocks are active
Low-power mode 0 (LPM0)
−
D
−
−
−
CPU is disabled
ACLK and SMCLK remain active, MCLK is disabled
FLL+ loop control remains active
D
D
Low-power mode 1 (LPM1)
−
−
−
CPU is disabled
FLL+ loop control is disabled
ACLK and SMCLK remain active, MCLK is disabled
Low-power mode 2 (LPM2)
−
−
−
−
CPU is disabled
MCLK, FLL+ loop control and DCOCLK are disabled
DCO’s dc generator remains enabled
ACLK remains active
D
D
Low-power mode 3 (LPM3)
−
−
−
−
CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc generator is disabled
ACLK remains active
Low-power mode 4 (LPM4)
−
−
−
−
−
CPU is disabled
ACLK is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc generator is disabled
Crystal oscillator is stopped
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
interrupt vector addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FFC0h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 3. Interrupt Sources, Flags, and Vectors
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
PRIORITY
Power-Up
External Reset
Watchdog
WDTIFG
KEYV
(see Note 1 and 5)
Reset
0FFFEh
31, highest
Flash Memory
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1, 2, and 5)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh
30
Timer_B7
TBCCR0 CCIFG0 (see Note 2)
Maskable
0FFFAh
0FFF8h
29
28
TBCCR1 CCIFG1 ... TBCCR6 CCIFG6,
TBIFG (see Notes 1 and 2)
Timer_B7
Maskable
Comparator_A
Watchdog Timer+
CAIFG
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
0FFF6h
0FFF4h
0FFF2h
0FFF0h
0FFEEh
0FFECh
27
26
25
24
23
22
WDTIFG
USCI_A0/USCI_B0 Receive
USCI_A0/USCI_B0 Transmit
ADC12 (see Note 6)
Timer_A3
UCA0RXIFG, UCB0RXIFG (see Note 1)
UCA0TXIFG, UCB0TXIFG (see Note 1)
ADC12IFG (see Notes 1 and 2)
TACCR0 CCIFG0 (see Note 2)
TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG (see Notes 1 and 2)
Timer_A3
Maskable
0FFEAh
21
I/O Port P1 (Eight Flags)
USART1 Receive
USART1 Transmit
I/O Port P2 (Eight Flags)
Basic Timer1/RTC
DMA
P1IFG.0 to P1IFG.7 (see Notes 1 and 2)
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
0FFE8h
0FFE6h
0FFE4h
0FFE2h
0FFE0h
0FFDEh
20
19
18
17
16
15
URXIFG1
UTXIFG1
P2IFG.0 to P2IFG.7 (see Notes 1 and 2)
BTIFG
DMA0IFG, DMA1IFG, DMA2IFG
(see Notes 1 and 2)
Reserved
Reserved
Reserved
Maskable
0FFDCh
0FFDAh
...
14
13
...
Reserved (see Note 4)
0FFC0h
0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh).
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
4. The interrupt vectors at addresses 0FFDAh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
5. Access and key violations, KEYV and ACCVIFG, only applicable to F devices.
6. ADC12 is not implemented in MSP430x461x1 devices.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
special function registers (SFRs)
The MSP430 SFRs are located in the lowest address space and are organized as byte mode registers. SFRs
should be accessed with byte instructions.
interrupt enable 1 and 2
7
6
5
4
3
2
1
0
Address
0h
ACCVIE
NMIIE
OFIE
WDTIE
rw–0
rw–0
rw–0
rw–0
WDTIE
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as a general-purpose timer.
OFIE
Oscillator-fault-interrupt enable
Nonmaskable-interrupt enable
Flash access violation interrupt enable
NMIIE
ACCVIE
7
6
5
4
3
2
1
0
Address
01h
BTIE
UTXIE1
URXIE1
UCB0TXIE
UCB0RXIE
UCA0TXIE UCA0RXIE
rw–0 rw–0
rw–0
rw–0
rw–0
rw–0
rw–0
UCA0RXIE
UCA0TXIE
UCB0RXIE
UCB0TXIE
URXIE1
USCI_A0 receive-interrupt enable
USCI_A0 transmit-interrupt enable
USCI_B0 receive-interrupt enable
USCI_B0 transmit-interrupt enable
USART1 UART and SPI receive-interrupt enable
USART1 UART and SPI transmit-interrupt enable
Basic timer interrupt enable
UTXIE1
BTIE
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
interrupt flag register 1 and 2
7
6
5
4
3
2
1
0
Address
02h
NMIIFG
OFIFG
WDTIFG
rw–0
rw–1
rw–(0)
WDTIFG:
Set on watchdog timer overflow (in watchdog mode) or security key violation
Reset on V power-on or a reset condition at the RST/NMI pin in reset mode
CC
OFIFG:
Flag set on oscillator fault
Set via RST/NMI pin
NMIIFG:
7
6
5
4
3
2
1
0
Address
03h
UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG
rw–0 rw–0
UTXIFG1
URXIFG1
BTIFG
rw–0
rw–0
rw–0
rw–1
rw–0
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
URXIFG0:
UTXIFG0:
USCI_A0 receive-interrupt flag
USCI_A0 transmit-interrupt flag
USCI_B0 receive-interrupt flag
USCI_B0 transmit-interrupt flag
USART1: UART and SPI receive flag
USART1: UART and SPI transmit flag
Basic timer flag
BTIFG:
module enable registers 1 and 2
7
6
5
4
4
3
3
2
2
1
1
0
0
Address
04h
7
6
5
Address
05h
UTXE1
URXE1
USPIE1
rw–0
rw–0
URXE1:
USART1: UART mode receive enable
USART1: UART mode transmit enable
UTXE1:
USPIE1:
USART1: SPI mode transmit and receive enable
Legend
rw:
Bit can be read and written.
rw-0,1:
rw-(0,1):
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
memory organization
MSP430F4616
MSP430F46161
MSP430F4617
MSP430F46171
MSP430F4618
MSP430F46181
MSP430F4619
MSP430F46191
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
92KB
0FFFFh − 0FFC0h
018FFFh − 002100h
92KB
0FFFFh − 0FFC0h
019FFFh − 003100h
116KB
0FFFFh − 0FFC0h
01FFFFh − 003100h
120KB
0FFFFh − 0FFC0h
01FFFFh − 002100h
RAM (Total)
Size
Size
Size
4KB
8KB
8KB
4KB
020FFh − 01100h
030FFh − 01100h
030FFh − 01100h
020FFh − 01100h
Extended
2KB
6KB
6KB
2KB
020FFh − 01900h
030FFh − 01900h
030FFh − 01900h
020FFh − 01900h
Mirrored
2KB
2KB
2KB
2KB
018FFh − 01100h
018FFh − 01100h
018FFh − 01100h
018FFh − 01100h
Information memory
Boot memory
Size
Flash
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Size
1KB
1KB
1KB
1KB
ROM
0FFFh − 0C00h
0FFFh − 0C00h
0FFFh − 0C00h
0FFFh − 0C00h
RAM
Size
2KB
2KB
2KB
2KB
(mirrored at
018FFh − 01100h)
09FFh − 0200h
09FFh − 0200h
09FFh − 0200h
09FFh − 0200h
Peripherals
16 bit
8 bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
bootstrap loader (BSL)
The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access
to the MSP430 memory via the BSL is protected by user-defined password. A bootstrap loader security key is
provided at address 0FFBEh to disable the BSL completely or to disable the erasure of the flash if an invalid
password is supplied. The BSL is optional for ROM-based devices. For complete description of the features of
the BSL and its implementation, see the application report Features of the MSP430 Bootstrap Loader, literature
number SLAA089.
BSLKEY
00000h
DESCRIPTION
Erasure of flash disabled if an invalid password is supplied
BSL disabled
0AA55h
any other value
BSL enabled
BSL FUNCTION
PZ PACKAGE PINS
87/A7 − P1.0
Data Transmit
Data Receive
86/E7 − P1.1
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D
Flash memory has n segments of main memory and two segments of information memory (A and B) of
128 bytes each. Each segment in main memory is 512 bytes in size.
D
D
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A and B can be erased individually, or as a group with segments 0 to n.
Segments A and B are also called information memory.
D
New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, literature number
SLAU056.
DMA controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to
or from a peripheral.
oscillator and system clock
The clock system in the MSP430x461x(1) family of devices is supported by the FLL+ module, which includes
support for a 32768-Hz watch crystal oscillator, an internal digitally controlled oscillator (DCO), and a high
frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system
cost and low power consumption. The FLL+ features digital frequency locked loop (FLL) hardware that, in
conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch
crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The
FLL+ module provides the following clock signals:
D
D
D
D
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal
Main clock (MCLK), the system clock used by the CPU
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on
and power-off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, V may not
CC
have ramped to V
at that time. The user must insure the default FLL+ settings are not changed until V
CC(min)
CC
reaches V
. If desired, the SVS circuit can be used to determine when V reaches V
.
CC(min)
CC
CC(min)
digital I/O
There are ten 8-bit I/O ports implemented—ports P1 through P10:
D
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
Ports P7/P8 and P9/P10 can be accessed word-wise as ports PA and PB respectively.
Basic Timer1 and Real-Time Clock (RTC)
The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. Basic Timer1 is extended to provide an integrated real-time clock
(RTC). An internal calendar compensates for months with less than 31 days and includes leap-year correction.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
LCD_A drive with regulated charge pump
The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump.
Furthermore it is possible to control the level of the LCD voltage and, thus, contrast by software.
watchdog timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
universal serial communication interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols like UART,
enhanced UART with automatic baudrate detection, and IrDA.
The USCI_A0 module provides support for SPI (3 or 4 pin), UART, enhanced UART and IrDA.
The USCI_B0 module provides support for SPI (3 or 4 pin) and I2C.
USART1
The hardware universal synchronous/asynchronous receive transmit (USART) peripheral module is used for
serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART
communication protocols, using double-buffered transmit and receive channels.
hardware multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16 16,
16 8, 8 16, and 8 8 bit operations. The module is capable of supporting signed and unsigned multiplication,
as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_A3 SIGNAL CONNECTIONS
INPUT PIN
NUMBER
OUTPUT PIN
NUMBER
MODULE
OUTPUT
SIGNAL
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
MODULE
BLOCK
PZ
PZ
82/B9 - P1.5
TACLK
ACLK
SMCLK
TACLK
TA0
TACLK
ACLK
Timer
CCR0
CCR1
CCR2
NA
TA0
TA1
TA2
SMCLK
INCLK
CCI0A
CCI0B
GND
82/B9 - P1.5
87/A7 - P1.0
86/E7 - P1.1
87/A7 - P1.0
TA0
DV
SS
CC
DV
V
CC
85/D7 - P1.2
79/A10 - P2.0
TA1
CAOUT (internal)
CCI1A
CCI1B
GND
85/D7 - P1.2
ADC12 (internal)
DV
SS
CC
DV
V
CC
TA2
ACLK (internal)
CCI2A
CCI2B
GND
79/A10 - P2.0
DV
SS
CC
DV
V
CC
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
Timer_B7
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_B7 SIGNAL CONNECTIONS
MODULE
OUTPUT
SIGNAL
INPUT PIN NUMBER
OUTPUT PIN NUMBER
PZ
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
MODULE
BLOCK
PZ
83/B8 - P1.4
TBCLK
ACLK
SMCLK
TBCLK
TB0
TBCLK
ACLK
Timer
CCR0
CCR1
CCR2
CCR3
CCR4
CCR5
CCR6
NA
SMCLK
INCLK
CCI0A
CCI0B
GND
83/B8 - P1.4
78/D8 - P2.1
78/D8 - P2.1
78/D8 - P2.1
TB0
ADC12 (internal)
TB0
TB1
TB2
TB3
TB4
TB5
TB6
DV
DV
SS
CC
V
CC
77/E8 - P2.2
77/E8 - P2.2
TB1
TB1
CCI1A
CCI1B
GND
77/E8 - P2.2
ADC12 (internal)
DV
SS
CC
DV
V
CC
76/A11 - P2.3
76/A11 - P2.3
TB2
TB2
CCI2A
CCI2B
GND
76/A11 - P2.3
67/E12 - P3.4
66/G9 - P3.5
65/F11 - P3.6
64/F12 - P3.7
DV
DV
SS
CC
V
CC
67/E12 - P3.4
67/E12 - P3.4
TB3
TB3
CCI3A
CCI3B
GND
DV
DV
SS
CC
V
CC
66/G9 - P3.5
66/G9 - P3.5
TB4
TB4
CCI4A
CCI4B
GND
DV
DV
SS
CC
V
CC
65/F11 - P3.6
65/F11 - P3.6
TB5
TB5
CCI5A
CCI5B
GND
DV
DV
SS
CC
V
CC
64/F12 - P3.7
TB6
ACLK (internal)
CCI6A
CCI6B
GND
DV
SS
CC
DV
V
CC
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
Comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
ADC12 (MSP430x461x Only)
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without
any CPU intervention.
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog timer control
Watchdog+
Timer_B7
WDTCTL
TBCCR6
TBCCR5
TBCCR4
TBCCR3
TBCCR2
TBCCR1
TBCCR0
TBR
0120h
019Eh
019Ch
019Ah
0198h
0196h
0194h
0192h
0190h
018Eh
018Ch
018Ah
0188h
0186h
0184h
0182h
0180h
011Eh
0176h
0174h
0172h
0170h
0166h
0164h
0162h
0160h
012Eh
013Eh
013Ch
013Ah
0138h
0136h
0134h
0132h
0130h
012Ch
012Ah
0128h
Capture/compare register 6
Capture/compare register 5
Capture/compare register 4
Capture/compare register 3
Capture/compare register 2
Capture/compare register 1
Capture/compare register 0
Timer_B register
Capture/compare control 6
Capture/compare control 5
Capture/compare control 4
Capture/compare control 3
Capture/compare control 2
Capture/compare control 1
Capture/compare control 0
Timer_B control
TBCCTL6
TBCCTL5
TBCCTL4
TBCCTL3
TBCCTL2
TBCCTL1
TBCCTL0
TBCTL
Timer_B interrupt vector
Capture/compare register 2
Capture/compare register 1
Capture/compare register 0
Timer_A register
TBIV
Timer_A3
TACCR2
TACCR1
TACCR0
TAR
Capture/compare control 2
Capture/compare control 1
Capture/compare control 0
Timer_A control
TACCTL2
TACCTL1
TACCTL0
TACTL
Timer_A interrupt vector
Sum extend
TAIV
Hardware
Multiplier
SUMEXT
RESHI
Result high word
Result low word
RESLO
OP2
Second operand
Multiply signed + accumulate/operand1
Multiply + accumulate/operand1
Multiply signed/operand1
Multiply unsigned/operand1
Flash control 3
MACS
MAC
MPYS
MPY
Flash
(F devices only)
FCTL3
Flash control 2
FCTL2
Flash control 1
FCTL1
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
peripheral file map (continued)
PERIPHERALS WITH WORD ACCESS (CONTINUED)
DMA
DMA module control 0
DMACTL0
DMACTL1
DMAIV
0122h
0124h
0126h
01D0h
01D2h
01D6h
01DAh
01DCh
01DEh
01E2h
01E6h
01E8h
01EAh
01EEh
01F2h
DMA module control 1
DMA interrupt vector
DMA Channel 0
DMA channel 0 control
DMA0CTL
DMA0SA
DMA0DA
DMA0SZ
DMA1CTL
DMA1SA
DMA1DA
DMA1SZ
DMA2CTL
DMA2SA
DMA2DA
DMA2SZ
DMA channel 0 source address
DMA channel 0 destination address
DMA channel 0 transfer size
DMA channel 1 control
DMA Channel 1
DMA Channel 2
DMA channel 1 source address
DMA channel 1 destination address
DMA channel 1 transfer size
DMA channel 2 control
DMA channel 2 source address
DMA channel 2 destination address
DMA channel 2 transfer size
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
peripheral file map (continued)
PERIPHERALS WITH WORD ACCESS (CONTINUED)
Conversion memory 15
ADC12
ADC12MEM15 015Eh
ADC12MEM14 015Ch
ADC12MEM13 015Ah
ADC12MEM12 0158h
ADC12MEM11 0156h
ADC12MEM10 0154h
Conversion memory 14
Conversion memory 13
Conversion memory 12
Conversion memory 11
Conversion memory 10
Conversion memory 9
Conversion memory 8
Conversion memory 7
Conversion memory 6
Conversion memory 5
Conversion memory 4
Conversion memory 3
Conversion memory 2
Conversion memory 1
Conversion memory 0
Interrupt-vector-word register
Inerrupt-enable register
Inerrupt-flag register
Control register 1
See also Peripherals
With Byte Access
(MSP430x461x only)
ADC12MEM9
ADC12MEM8
ADC12MEM7
ADC12MEM6
ADC12MEM5
ADC12MEM4
ADC12MEM3
ADC12MEM2
ADC12MEM1
ADC12MEM0
ADC12IV
0152h
0150h
014Eh
014Ch
014Ah
0148h
0146h
0144h
0142h
0140h
01A8h
01A6h
01A4h
01A2h
01A0h
03Eh
ADC12IE
ADC12IFG
ADC12CTL1
ADC12CTL0
PASEL
Control register 0
Port PA
Port PB
Port PA selection
Port PA direction
PADIR
03Ch
Port PA output
PAOUT
03Ah
Port PA input
PAIN
038h
Port PB selection
PBSEL
00Eh
Port PB direction
PBDIR
00Ch
Port PB output
PBOUT
00Ah
Port PB input
PBIN
008h
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
LCD_A
LCD Voltage Control 1
LCD Voltage Control 0
LCD Voltage Port Control 1
LCD Voltage Port Control 0
LCD memory 20
:
LCDAVCTL1
LCDAVCTL0
LCDAPCTL1
LCDAPCTL0
LCDM20
:
0AFh
0AEh
0ADh
0ACh
0A4h
:
LCD memory 16
LCD memory 15
:
LCDM16
LCDM15
:
0A0h
09Fh
:
LCD memory 1
LCDM1
091h
090h
LCD control and mode
LCDCTL
ADC12
ADC memory-control register 15
ADC memory-control register 14
ADC memory-control register 13
ADC memory-control register 12
ADC memory-control register 11
ADC memory-control register 10
ADC memory-control register 9
ADC memory-control register 8
ADC memory-control register 7
ADC memory-control register 6
ADC memory-control register 5
ADC memory-control register 4
ADC memory-control register 3
ADC memory-control register 2
ADC memory-control register 1
ADC memory-control register 0
Transmit buffer
ADC12MCTL15 08Fh
ADC12MCTL14 08Eh
ADC12MCTL13 08Dh
ADC12MCTL12 08Ch
ADC12MCTL11 08Bh
ADC12MCTL10 08Ah
(Memory control
registers require byte
access)
(MSP430x461x only)
ADC12MCTL9
ADC12MCTL8
ADC12MCTL7
ADC12MCTL6
ADC12MCTL5
ADC12MCTL4
ADC12MCTL3
ADC12MCTL2
ADC12MCTL1
ADC12MCTL0
U1TXBUF
089h
088h
087h
086h
085h
084h
083h
082h
081h
080h
07Fh
07Eh
07Dh
07Ch
07Bh
07Ah
079h
078h
USART1
Receive buffer
U1RXBUF
Baud rate
U1BR1
Baud rate
U1BR0
Modulation control
U1MCTL
Receive control
U1RCTL
Transmit control
U1TCTL
USART control
U1CTL
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
USCI
USCI I2C Slave Address
USCI I2C Own Address
USCI Synchronous Transmit Buffer
USCI Synchronous Receive Buffer
USCI Synchronous Status
USCI I2C Interrupt Enable
USCI Synchronous Bit Rate 1
USCI Synchronous Bit Rate 0
USCI Synchronous Control 1
USCI Synchronous Control 0
USCI Transmit Buffer
UCBI2CSA
UCBI2COA
UCBTXBUF
UCBRXBUF
UCBSTAT
UCBI2CIE
UCBBR1
011Ah
0118h
06Fh
06Eh
06Dh
06Ch
06Bh
06Ah
069h
068h
067h
066h
065h
064h
063h
062h
061h
060h
05Fh
05Eh
05Dh
05Bh
05Ah
059h
056h
054h
053h
052h
051h
050h
04Fh
04Eh
04Dh
04Ch
047h
046h
045h
UCBBR0
UCBCTL1
UCBCTL0
UCATXBUF
UCARXBUF
UCASTAT
UCAMCTL
UCABR1
USCI Receive Buffer
USCI Status
USCI Modulation Control
USCI Baud Rate 1
USCI Baud Rate 0
UCABR0
USCI Control 1
UCACTL1
UCACTL0
UCAIRRCTL
UCAIRTCTL
UCAABCTL
CAPD
USCI Control 0
USCI IrDA Receive Control
USCI IrDA Transmit Control
USCI LIN Control
Comparator_A
Comparator_A port disable
Comparator_A control 2
Comparator_A control 1
CACTL2
CACTL1
BrownOUT, SVS
FLL+Clock
SVS control register (Reset by brownout signal) SVSCTL
FLL+ Control 1
FLL_CTL1
FLL_CTL0
SCFQCTL
SCFI1
FLL+ Control 0
System clock frequency control
System clock frequency integrator
System clock frequency integrator
Real Time Clock Year High Byte
Real Time Clock Year Low Byte
Real Time Clock Month
Real Time Clock Day of Month
Basic Timer1 Counter 2
Basic Timer1 Counter 1
Real Time Counter 4
SCFI0
RTC (Basic Timer 1)
RTCYEARH
RTCYEARL
RTCMON
RTCDAY
BTCNT2
BTCNT1
RTCNT4
(RTCDOW)
RTCNT3
(RTCHOUR)
RTCNT2
(RTCMIN)
RTCNT1
(RTCSEC)
RTCCTL
BTCTL
(Real Time Clock Day of Week)
Real Time Counter 3
044h
043h
042h
(Real Time Clock Hour)
Real Time Counter 2
(Real Time Clock Minute)
Real Time Counter 1
(Real Time Clock Second)
Real Time Clock Control
Basic Timer1 Control
041h
040h
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Port P10 selection P10SEL
Port P10
Port P9
Port P8
Port P7
Port P6
Port P5
Port P4
Port P3
Port P2
00Fh
00Dh
00Bh
009h
00Eh
00Ch
00Ah
008h
03Fh
03Dh
03Bh
039h
03Eh
03Ch
03Ah
038h
037h
036h
035h
034h
033h
032h
031h
030h
01Fh
01Eh
01Dh
01Ch
01Bh
01Ah
019h
018h
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
026h
025h
024h
023h
022h
021h
020h
Port P10 direction
Port P10 output
Port P10 input
P10DIR
P10OUT
P10IN
P9SEL
P9DIR
P9OUT
P9IN
Port P9 selection
Port P9 direction
Port P9 output
Port P9 input
Port P8 selection
Port P8 direction
Port P8 output
P8SEL
P8DIR
P8OUT
P8IN
Port P8 input
Port P7 selection
Port P7 direction
Port P7 output
P7SEL
P7DIR
P7OUT
P7IN
Port P7 input
Port P6 selection
Port P6 direction
Port P6 output
P6SEL
P6DIR
P6OUT
P6IN
Port P6 input
Port P5 selection
Port P5 direction
Port P5 output
P5SEL
P5DIR
P5OUT
P5IN
Port P5 input
Port P4 selection
Port P4 direction
Port P4 output
P4SEL
P4DIR
P4OUT
P4IN
Port P4 input
Port P3 selection
Port P3 direction
Port P3 output
P3SEL
P3DIR
P3OUT
P3IN
Port P3 input
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt-edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
Port P2 input
Port P1
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt-edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
Port P1 input
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Special functions
SFR module enable 2
SFR module enable 1
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
ME2
ME1
IFG2
IFG1
IE2
005h
004h
003h
002h
001h
000h
IE1
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Voltage range applied at V to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V
CC
SS
Voltage range applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.3 V
CC
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA
Storage temperature range, T
:
stg
Unprogrammed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Programmed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to V The JTAG fuse-blow voltage, V , is allowed to exceed the absolute maximum rating. The voltage is applied
SS.
FB
to the TDI/TCLK pin when blowing the JTAG fuse.
recommended operating conditions
MIN
NOM
MAX UNITS
Supply voltage during program execution (see Note 1),
MSP430x461x(1)
MSP430F461x(1)
1.8
3.6
3.6
V
V
V
CC
(AV = DV
= V
)
CC
CC1/2
CC
Supply voltage during flash memory programming (see Note 1),
(AV = DV = V
2.7
2
V
CC
)
CC
CC
CC1/2
Supply voltage during program execution,
SVS enabled and PORON = 1 (see Note 1 and Note 2),
MSP430x461x(1)
3.6
V
V
CC
(AV = DV
= V
)
CC
CC1/2
CC
Supply voltage (see Note 1), V (AV = DV
= V )
SS
0
0
V
SS
SS
SS1/2
Operating free-air temperature range, T
MSP430x461x(1)
Watch crystal
−40
85
°C
A
LF selected, XTS_FLL = 0
32.768
LFXT1 crystal frequency, f
(see Note 2)
(LFXT1)
XT1 selected, XTS_FLL = 1 Ceramic resonator
XT1 selected, XTS_FLL = 1 Crystal
Ceramic resonator
450
1000
450
1000
DC
8000
8000
8000
8000
3.0
kHz
kHz
MHz
XT2 crystal frequency, f
(XT2)
Crystal
V
CC
V
CC
V
CC
= 1.8 V
= 2.0 V
= 3.6 V
DC
4.6
Processor frequency (signal MCLK), f
(System)
DC
8.0
NOTES: 1. It is recommended to power AV and DV from the same source. A maximum difference of 0.3 V between AV and DV can
CC
CC
CC
CC
be tolerated during power up and operation.
2. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply
voltage. POR is going inactive when the supply voltage is raised above the minimum supply voltage plus the hysteresis of the SVS
circuitry.
3. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
f
(MHz)
System
8.0 MHz
Supply voltage range,
MSP430x461x(1), during
program execution
Supply voltage range, MSP430F461x(1),
during flash memory programming
4.6 MHz
3.0 MHz
1.8 2.0
2.7
3
3.6
Supply Voltage − V
Figure 1. Frequency vs Supply Voltage, Typical Characteristic
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AV + DV excluding external current
CC
CC
PARAMETER
TEST CONDITIONS
V
MIN
TYP
280
470
400
600
45
MAX
370
580
480
740
70
UNIT
CC
2.2 V
3 V
Active mode (see Note 1 and Note 4)
C461x(1)
T = −40°C to 85°C
A
µA
f
f
= f
= 1 MHz,
(MCLK)
(SMCLK)
= 32,768 Hz
XTS=0, SELM=(0,1)
(F461x(1): Program executes from flash)
I
(ACLK)
(AM)
2.2 V
3 V
F461x(1)
x461x(1)
T = −40°C to 85°C
A
µA
µA
2.2 V
3 V
Low-power mode (LPM0)
(see Note 1 and Note 4)
I
I
T = −40°C to 85°C
A
(LPM0)
75
110
Low-power mode (LPM2),
2.2 V
3 V
11
17
20
24
f
f
= f
= 0 MHz,
T = −40°C to 85°C
A
µA
(MCLK)
(ACLK)
(SMCLK)
(LPM2)
= 32,768 Hz, SCG0 = 0 (see Note 2 and Note 4)
T = −40°C
1.3
1.3
2.22
6.5
1.9
1.9
2.5
7.5
1.5
1.5
2.8
7.2
2.5
2.5
3.2
8.5
0.13
0.22
0.9
4.3
0.13
0.3
1.1
5.0
4.0
4.0
A
Low-power mode (LPM3)
T = 25°C
A
f
f
= f
= 0 MHz,
(MCLK)
(SMCLK)
2.2 V
3 V
T = 60°C
A
6.5
= 32,768 Hz, SCG0 = 1
(ACLK)
Basic Timer1 enabled, ACLK selected
LCD_A enabled, LCDCPEN = 0;
T = 85°C
A
15.0
5.0
I
I
I
µA
(LPM3)
(LPM3)
(LPM4)
T = −40°C
A
(static mode; f
= f
(ACLK)
/32)
LCD
T = 25°C
A
5.0
(see Note 2 and Note 3 and Note 4)
T = 60°C
A
7.5
T = 85°C
A
18.0
5.5
T = −40°C
A
Low-power mode (LPM3)
T = 25°C
A
5.5
f
f
= f
= 0 MHz,
(MCLK)
(SMCLK)
2.2 V
3 V
T = 60°C
A
7.0
= 32,768 Hz, SCG0 = 1
(ACLK)
Basic Timer1 enabled, ACLK selected
LCD_A enabled, LCDCPEN = 0;
T = 85°C
A
17.0
6.5
µA
T = −40°C
A
(4−mux mode; f
= f
(ACLK)
/32)
LCD
T = 25°C
A
6.5
(see Note 2 and Note 3 and Note 4)
T = 60°C
A
8.0
T = 85°C
A
20.0
1.0
T = −40°C
A
T = 25°C
A
1.0
2.2 V
3 V
T = 60°C
A
2.5
Low-power mode (LPM4)
T = 85°C
A
12.5
1.6
f
f
= 0 MHz, f
= 0 Hz, SCG0 = 1
= 0 MHz,
(MCLK)
(SMCLK)
µA
T = −40°C
A
(ACLK)
(see Note 2 and Note 4)
T = 25°C
A
1.6
T = 60°C
A
3.0
T = 85°C
A
15.0
NOTES: 1. Timer_B is clocked by f
= f = 1 MHz. All inputs are tied to 0 V or to V . Outputs do not source or sink any current.
(DCO) CC
(DCOCLK)
2. All inputs are tied to 0 V or to V . Outputs do not source or sink any current.
CC
3. The LPM3 currents are characterized with a Micro Crystal CC4V−T1A (9 pF) crystal and OSCCAPx = 1h.
4. Current for brownout included.
Current consumption of active mode versus system frequency, F version:
I
= I
[1 MHz] × f
[MHz]
(AM)
(AM)
(System)
Current consumption of active mode versus supply voltage, F version:
= I + 200 µA/V × (V – 3 V)
I
(AM)
(AM) [3 V]
CC
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Schmitt-trigger inputs − Ports P1 to P10, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
PARAMETER
V
MIN
1.1
1.5
0.4
0.9
0.3
0.5
TYP
MAX
1.55
1.98
0.9
UNIT
CC
2.2 V
3 V
V
IT+
V
IT−
V
hys
Positive-going input threshold voltage
V
2.2 V
3 V
Negative-going input threshold voltage
V
V
1.3
2.2 V
3 V
1.1
Input voltage hysteresis (V − V
)
IT−
IT+
1
inputs Px.x, TAx, TBx
PARAMETER
TEST CONDITIONS
V
MIN
62
TYP
MAX
UNIT
CC
2.2 V
3 V
Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag, (see Note 1)
t
t
External interrupt timing
ns
(int)
50
TA0, TA1, TA2
2.2 V
3 V
62
Timer_A, Timer_B capture
timing
ns
(cap)
TB0, TB1, TB2, TB3, TB4, TB5, TB6
50
Timer_A, Timer_B clock
frequency externally applied
to pin
f
f
2.2 V
3 V
8
(TAext)
TACLK, TBCLK, INCLK: t = t
MHz
(H)
(L)
10
(TBext)
f
f
2.2 V
3 V
8
(TAint)
Timer_A, Timer_B clock
frequency
SMCLK or ACLK signal selected
MHz
10
(TBint)
NOTES: 1. The external signal sets the interrupt flag every time the minimum t
parameters are met. It may be set even with trigger signals
(int)
shorter than t
.
(int)
leakage current − Ports P1 to P10 (see Note 1)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
V
(see Note 2)
(Px.y)
I
Leakage current
Port Px
2.2 V/3 V
50
nA
lkg(Px.y)
(1 ≤ x ≤ 10, 0 ≤ y ≤ 7)
NOTES: 1. The leakage current is measured with V or V applied to the corresponding pin(s), unless otherwise noted.
SS
CC
2. The port pin must be selected as input.
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1 to P10
PARAMETER
TEST CONDITIONS
= −1.5 mA (see Note 1)
= −6 mA (see Note 2)
= −1.5 mA (see Note 1)
= −6 mA (see Note 2)
= 1.5 mA (see Note 1)
= 6 mA (see Note 2)
= 1.5 mA, (see Note 1)
= 6 mA (see Note 2)
V
MIN
TYP
MAX
UNIT
CC
I
I
I
I
I
I
I
I
2.2 V
2.2 V
3 V
V
−0.25
V
CC
V
CC
V
CC
V
CC
OH(max)
OH(max)
OH(max)
OH(max)
OL(max)
OL(max)
OL(max)
OL(max)
CC
V
−0.6
CC
V
OH
High-level output voltage
V
V
CC
−0.25
3 V
V
−0.6
CC
2.2 V
2.2 V
3 V
V
SS
V
SS
V
SS
V
SS
V
+0.25
SS
V
+0.6
SS
V
OL
Low-level output voltage
V
V
SS
+0.25
3 V
V
+0.6
SS
NOTES: 1. The maximum total current, I
specified voltage drop.
and I
for all outputs combined, should not exceed 12 mA to satisfy the maximum
OH(max)
OL(max),
2. The maximum total current, I
specified voltage drop.
and I
for all outputs combined, should not exceed 48 mA to satisfy the maximum
OH(max)
OL(max),
output frequency
PARAMETER
TEST CONDITIONS
MIN
DC
DC
TYP
MAX
10
UNIT
MHz
MHz
V
CC
CC
= 2.2 V
= 3 V
C = 20 pF,
I = 1.5 mA
L
L
f
(1 ≤ x ≤ 10, 0 ≤ y ≤ 7)
(Px.y)
V
12
f
f
f
P1.1/TA0/MCLK,
(MCLK)
(SMCLK)
(ACLK)
V
V
= 2.2 V
= 3 V
10
MHz
MHz
CC
P1.4/TBCLK/SMCLK,
P1.5/TACLK/ACLK
C = 20 pF
L
DC
40%
30%
12
60%
70%
CC
f
f
f
f
= f
(LFXT1)
= f
(LFXT1)
= f
(LFXT1)
= f
= f
(ACLK)
(ACLK)
(ACLK)
(MCLK)
(XT1)
P1.5/TACLK/ACLK,
C = 20 pF
(LF)
L
V
CC
= 2.2 V / 3 V
50%
50%
= f
40%
60%
(XT1)
(DCOCLK)
P1.1/TA0/MCLK,
t
Duty cycle of output frequency
C = 20 pF,
(Xdc)
50%−
15 ns
50%+
15 ns
L
f
f
f
= f
(MCLK)
V
CC
= 2.2 V / 3 V
= f
(XT2)
40%
60%
(SMCLK)
(SMCLK)
P1.4/TBCLK/SMCLK,
C = 20 pF,
50%−
15 ns
50%+
15 ns
L
= f
(DCOCLK)
50%
V
CC
= 2.2 V / 3 V
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics − outputs
TYPICAL LOW-LEVEL OUTPUT CURRENT
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
25.0
20.0
15.0
10.0
5.0
50.0
40.0
30.0
20.0
10.0
0.0
V
P2.0
= 2.2 V
T
= 25°C
= 85°C
V
P2.0
= 3 V
CC
A
CC
T
= 25°C
= 85°C
A
T
A
T
A
0.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OL
− Low-Level Output Voltage − V
V
OL
− Low-Level Output Voltage − V
Figure 2
Figure 3
TYPICAL HIGH-LEVEL OUTPUT CURRENT
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
vs
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
0.0
−5.0
0.0
−10.0
−20.0
−30.0
−40.0
−50.0
V
P2.0
= 2.2 V
CC
V
P2.0
= 3 V
CC
−10.0
−15.0
−20.0
−25.0
T
= 85°C
A
T
A
= 85°C
T
A
= 25°C
T
= 25°C
A
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OH
− High-Level Output Voltage − V
V
OH
− High-Level Output Voltage − V
Figure 4
Figure 5
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
wake-up LPM3
PARAMETER
TEST CONDITIONS
f = 1 MHz
V
MIN
TYP
MAX
UNIT
CC
6
6
6
f = 2 MHz
t
Delay time
2.2 V/3 V
µs
d(LPM3)
f = 3 MHz
RAM
PARAMETER
TEST CONDITIONS
CPU halted (see Note 1)
MIN
TYP
MAX
UNIT
VRAMh
1.6
V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
LCD_A
PARAMETER
TEST CONDITIONS
Charge pump enabled
MIN
TYP
MAX
UNIT
V
CC
V
Supply voltage (see Note 2)
2.2
3.6
V
CC(LCD)
(LCDCPEN = 1; VLCDx > 0000)
V
=3 V; LCDCPEN = 1,
LCD(typ)
VLCDx= 1000; all segments on,
f
f
/32,
I
Supply current (see Note 2 )
2.2 V
3
µA
LCD = ACLK
CC(LCD)
no LCD connected (see Note 4)
T = 25°C
A
Capacitor on LCDCAP
(see Note 1 and Note 3)
Charge pump enabled
(LCDCPEN = 1; VLCDx > 0000)
C
4.7
µF
LCD
f
LCD frequency
1.1
kHz
LCD
VLCDx = 0000
VLCDx = 0001
VLCDx = 0010
VLCDx = 0011
VLCDx = 0100
VLCDx = 0101
VLCDx = 0110
VLCDx = 0111
VLCDx = 1000
VLCDx = 1001
VLCDx = 1010
VLCDx = 1011
VLCDx = 1100
VLCDx = 1101
VLCDx = 1110
VLCDx = 1111
V
CC
2.60
2.66
2.72
2.78
2.84
2.90
2.96
3.02
3.08
3.14
3.20
3.26
3.32
3.38
3.44
V
LCD voltage (see Note 3)
V
LCD
3.60
10
V
LCD
=3 V; CPEN = 1;
R
LCD driver output impedance
2.2 V
kΩ
LCD
VLCDx = 1000, I
= ꢀ 10 µΑ
LOAD
NOTES: 1. Enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device.
2. Refer to the supply current specifications I for additional current specifications with the LCD_A module active.
(LPM3)
3. Segments S0 through S3 are disabled when the LCD charge pump feature is enabled (LCDCPEN = 1) and cannot be used together
with the LCD charge pump. In addition, when using segments S0 through S3 with an external LCD voltage supply, V
4. Connecting an actual display will increase the current consumption depending on the size of the LCD.
≤ AV
.
LCD
CC
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Comparator_A (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
25
MAX
40
UNIT
V
V
= 2.2 V
= 3 V
CC
I
CAON=1, CARSEL=0, CAREF=0
µA
(CC)
45
30
60
50
CC
CAON=1, CARSEL=0, CAREF=1/2/3,
No load at P1.6/CA0 and
P1.7/CA1
V
= 2.2 V
= 3 V
CC
CC
I
µA
(Refladder/RefDiode)
V
45
71
Voltage @ 0.25 V
node
node
PCA0=1, CARSEL=1, CAREF=1,
No load at P1.6/CA0 and P1.7/CA1
CC
V
V
V
V
= 2.2 V / 3 V
= 2.2V / 3 V
0.23
0.47
0.24
0.25
(Ref025)
CC
V
CC
Voltage @ 0.5 V
PCA0=1, CARSEL=1, CAREF=2,
No load at P1.6/CA0 and P1.7/CA1
CC
0.48
0.5
(Ref050)
CC
V
CC
PCA0=1, CARSEL=1, CAREF=3,
No load at P1.6/CA0 and P1.7/CA1;
T = 85°C
A
V
V
= 2.2 V
= 3 V
390
400
480
490
540
550
CC
V
V
mV
V
(RefVT)
CC
Common-mode input
voltage range
CAON=1
V
CC
= 2.2 V / 3 V
0
V
−1
30
IC
CC
V −V
p
Offset voltage
See Note 2
CAON = 1
VCC = 2.2 V / 3 V
−30
0
mV
mV
S
V
hys
Input hysteresis
V
= 2.2 V / 3 V
= 2.2 V
= 3 V
0.7
210
150
1.9
1.4
300
240
3.4
CC
CC
CC
CC
CC
CC
CC
CC
CC
V
160
80
T = 25°C,
A
ns
µs
ns
µs
Overdrive 10 mV, without filter: CAF = 0
V
t
(response LH)
(response HL)
V
= 2.2 V
= 3 V
1.4
0.9
130
80
T = 25°C
A
Overdrive 10 mV, with filter: CAF = 1
V
1.5
2.6
V
= 2.2 V
= 3 V
210
150
1.9
300
240
3.4
T = 25°C
A
Overdrive 10 mV, without filter: CAF = 0
V
t
V
V
= 2.2 V
= 3 V
1.4
0.9
T = 25°C,
A
Overdrive 10 mV, with filter: CAF = 1
1.5
2.6
NOTES: 1. The leakage current for the Comparator_A terminals is identical to I
specification.
lkg(Px.x)
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
typical characteristics
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
650
650
600
550
500
450
400
V
CC
= 3 V
V
CC
= 2.2 V
600
550
500
450
400
Typical
Typical
−45
−25
−5
15
35
55
75
95
−45
−25
−5
15
35
55
75
95
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 6. V
vs Temperature
Figure 7. V
vs Temperature
(RefVT)
(RefVT)
0 V
V
CC
0
1
CAF
CAON
To Internal
Modules
Low-Pass Filter
0
1
0
1
+
_
V+
V−
CAOUT
Set CAIFG
Flag
τ ≈ 2 µs
Figure 8. Block Diagram of Comparator_A Module
V
CAOUT
Overdrive
V−
400 mV
V+
t
(response)
Figure 9. Overdrive Definition
40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
POR/brownout reset (BOR) (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
0.7 × V
MAX
UNIT
µs
t
2000
d(BOR)
V
dV /dt ≤ 3 V/s (see Figure 10)
V
CC(start)
CC
(B_IT−)
Brownout
V
V
dV /dt ≤ 3 V/s (see Figure 10 through Figure 12)
1.79
210
V
(B_IT−)
CC
(see Notes 2 and 3)
dV /dt ≤ 3 V/s (see Figure 10)
CC
70
2
130
mV
hys(B_IT−)
Pulse length needed at RST/NMI pin to accepted reset
t
µs
(reset)
internally, V = 2.2 V/3 V
CC
NOTES: 1. The current consumption of the brownout module is already included in the I current consumption data.
CC
2. The voltage level V
+ V
is ≤ 1.89V.
(B_IT−)
hys(B_IT−)
3. During power up, the CPU begins code execution following a period of t
after V = V
+ V . The default
hys(B_IT−)
d(BOR)
CC
(B_IT−)
FLL+ settings must not be changed until V ≥ V
, where V
is the minimum supply voltage for the desired
CC
CC(min)
CC(min)
operating frequency. See the MSP430x4xx Family User’s Guide for more information on the brownout/SVS circuit.
typical characteristics
V
CC
V
hys(B_IT−)
V
(B_IT−)
V
CC(start)
1
0
t
d(BOR)
Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage
V
t
CC
pw
2
3 V
V
CC
= 3 V
Typical Conditions
1.5
1
V
CC(drop)
0.5
0
0.001
1
1000
1 ns
1 ns
− Pulse Width − µs
t
− Pulse Width − µs
t
pw
pw
Figure 11. V
Level With a Square Voltage Drop to Generate a POR/Brownout Signal
CC(drop)
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
typical characteristics (continued)
V
t
CC
pw
2
3 V
V
CC
= 3 V
1.5
1
Typical Conditions
V
CC(drop)
0.5
0
t = t
f
r
0.001
1
1000
t
t
r
f
t
− Pulse Width − µs
t
− Pulse Width − µs
pw
pw
Figure 12. V
Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
CC(drop)
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply voltage supervisor/monitor (SVS) (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
150
2000
150
12
UNIT
dV /dt > 30 V/ms (see Figure 13)
5
CC
t
µs
(SVSR)
dV /dt ≤ 30 V/ms
CC
t
t
SVS on, switch from VLD = 0 to VLD ≠ 0, V = 3 V
20
µs
µs
V
d(SVSon)
CC
‡
VLD ≠ 0
settle
V
VLD ≠ 0, V /dt ≤ 3 V/s (see Figure 13)
1.55
120
1.7
(SVSstart)
CC
VLD = 1
70
155
mV
V
V
/dt ≤ 3 V/s (see Figure 13)
V
V
(SVS_IT−)
x 0.016
CC
(SVS_IT−)
x 0.001
VLD = 2 .. 14
V
hys(SVS_IT−)
/dt ≤ 3 V/s (see Figure 13), external voltage applied
CC
VLD = 15
4.4
20
mV
on A7
VLD = 1
VLD = 2
VLD = 3
VLD = 4
VLD = 5
VLD = 6
VLD = 7
VLD = 8
VLD = 9
VLD = 10
VLD = 11
VLD = 12
VLD = 13
VLD = 14
1.8
1.9
2.1
2.05
2.23
2.35
2.46
2.58
2.69
2.84
2.97
3.10
3.26
3.39
1.94
2.05
2.14
2.24
2.33
2.46
2.58
2.69
2.83
2.94
3.11
3.24
3.43
2.2
2.3
2.4
2.5
2.65
2.8
V
CC
/dt ≤ 3 V/s (see Figure 13)
V
V
(SVS_IT−)
2.9
3.05
3.2
†
3.35
3.58
†
3.5
3.73
†
†
3.7
3.96
V
on A7
/dt ≤ 3 V/s (see Figure 13), external voltage applied
CC
VLD = 15
1.1
1.2
10
1.3
15
I
CC(SVS)
VLD ≠ 0, V = 2.2 V/3 V
µA
CC
(see Note 4)
†
‡
The recommended operating voltage range is limited to 3.6 V.
is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere
t
settle
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 4: The current consumption of the SVS module is not included in the I current consumption data.
CC
42
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
typical characteristics
Software Sets VLD>0:
SVS is Active
V
CC
V
hys(SVS_IT−)
V
(SVS_IT−)
V
(SVSstart)
V
hys(B_IT−)
V
(B_IT−)
V
CC(start)
Brown-
Out
Brownout
Region
Region
Brownout
1
0
t
t
SVS
d(BOR)
d(BOR)
Out
SVS Circuit is Active From VLD > to V < V(
CC
B_IT−)
1
0
t
t
d(SVSon)
d(SVSR)
Set POR
1
undefined
0
Figure 13. SVS Reset (SVSR) vs Supply Voltage
V
CC
t
pw
3 V
2
1.5
1
Rectangular Drop
V
CC(drop)
Triangular Drop
1 ns
1 ns
0.5
V
t
CC
pw
3 V
0
1
10
100
1000
V
t
− Pulse Width − µs
pw
CC(drop)
t = t
f
r
t
t
r
f
t − Pulse Width − µs
Figure 14. V
With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
CC(drop)
43
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
DCO
PARAMETER
TEST CONDITIONS
V
MIN
TYP
1
MAX
UNIT
CC
f
N
=01Eh, FN_8=FN_4=FN_3=FN_2=0, D = 2; DCOPLUS= 0
(DCO)
2.2 V/3 V
2.2 V
3 V
MHz
(DCOCLK)
0.3
0.3
2.5
2.7
0.7
0.8
5.7
6.5
1.2
1.3
9
0.65
0.7
5.6
6.1
1.3
1.5
10.8
12.1
2
1.25
1.3
10.5
11.3
2.3
2.5
18
f
f
f
f
f
f
f
f
f
f
FN_8=FN_4=FN_3=FN_2=0 ; DCOPLUS = 1
FN_8=FN_4=FN_3=FN_2=0; DCOPLUS = 1
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1
FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1
FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1
FN_8=0, FN_4= 1, FN_3= FN_2=x; DCOPLUS = 1
FN_8=0, FN_4=1, FN_3= FN_2=x; DCOPLUS = 1
FN_8=1, FN_4=FN_3=FN_2=x; DCOPLUS = 1
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
(DCO=2)
2.2 V
3 V
(DCO=27)
(DCO=2)
(DCO=27)
(DCO=2)
(DCO=27)
(DCO=2)
(DCO=27)
(DCO=2)
(DCO=27)
2.2 V
3 V
2.2 V
3 V
20
2.2 V
3 V
3
2.2
15.5
17.9
2.8
3.4
21.5
26.6
4.2
6.3
32
3.5
25
2.2 V
3 V
10.3
1.8
2.1
13.5
16
28.5
4.2
5.2
33
2.2 V
3 V
2.2 V
3 V
41
2.2 V
3 V
2.8
4.2
21
6.2
9.2
46
2.2 V
3 V
FN_8=1,FN_4=FN_3=FN_2=x; DCOPLUS = 1
Step size between adjacent DCO taps:
30
46
70
1 < TAP ≤ 20
TAP = 27
2.2 V
3 V
1.06
1.07
–0.2
–0.2
1.11
1.17
–0.4
–0.4
S
n
S = f
n
/ f (see Figure 16 for taps 21 to 27)
DCO(Tap n+1) DCO(Tap n)
–0.3
–0.3
Temperature drift, N
D = 2; DCOPLUS = 0
= 01Eh, FN_8=FN_4=FN_3=FN_2=0
(DCO)
D
D
%/_C
t
Drift with V variation, N
= 01Eh, FN_8=FN_4=FN_3=FN_2=0
CC
(DCO)
0
5
15
%/V
V
D = 2; DCOPLUS = 0
f
f
(DCO)
(DCO)
f
f
5
(DCO3V)
(DCO20 C)
1.0
1.0
0
1.8
2.4
3.0
3.6
V
−40
−20
0
20
40
60
85
− V
T − °C
A
CC
Figure 15. DCO Frequency vs Supply Voltage V and vs Ambient Temperature
CC
44
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
1.17
Max
1.11
1.07
1.06
Min
1
20
27
DCO Tap
Figure 16. DCO Tap Step Size
Legend
Tolerance at Tap 27
DCO Frequency
Adjusted by Bits
9
5
2 to 2 in SCFI1 {N
}
{DCO}
Tolerance at Tap 2
Overlapping DCO Ranges:
Uninterrupted Frequency Range
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_3=x
FN_4=x
FN_8=1
Figure 17. Five Overlapping DCO Ranges Controlled by FN_x Bits
45
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
OSCCAPx = 0h
OSCCAPx = 1h
OSCCAPx = 2h
OSCCAPx = 3h
OSCCAPx = 0h
OSCCAPx = 1h
OSCCAPx = 2h
OSCCAPx = 3h
V
MIN
TYP
0
MAX
UNIT
CC
2.2 V / 3 V
2.2 V / 3 V
2.2 V / 3 V
2.2 V / 3 V
2.2 V / 3 V
2.2 V / 3 V
2.2 V / 3 V
2.2 V / 3 V
10
14
18
0
C
Integrated input capacitance (see Note 4)
pF
XIN
10
14
18
C
V
Integrated output capacitance (see Note 4)
Input levels at XIN
pF
V
XOUT
V
SS
0.2×V
CC
IL
See Note 3
2.2 V/3 V
V
IH
0.8×V
V
CC
CC
NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is
(C x C ) / (C + C ). This is independent of XTS_FLL.
XIN
XOUT
XIN
XOUT
2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.
− Keep the trace between the MSP430 device and the crystal as short as possible.
− Design a good ground plane around the oscillator pins.
− Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
− Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
− Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
− If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
− Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.
4. External capacitance is recommended for precision real-time clock applications; OSCCAPx = 0h.
crystal oscillator, XT2 oscillator (see Note 1)
PARAMETER
TEST CONDITIONS
= 2.2 V/3 V
MIN
TYP
2
MAX
UNIT
pF
pF
V
C
C
V
Integrated input capacitance
Integrated output capacitance
V
V
XT2IN
CC
= 2.2 V/3 V
2
XT2OUT
CC
V
SS
0.2 × V
CC
IL
Input levels at XT2IN
V
CC
= 2.2 V/3 V (see Note 2)
V
IH
0.8 × V
V
CC
V
CC
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
46
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (UART mode)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
External: UCLK
f
USCI input clock frequency
f
MHz
USCI
SYSTEM
Duty Cycle = 50% 10%
BITCLK clock frequency
(equals Baudrate in MBaud)
f
t
2.2V /3 V
1
MHz
ns
BITCLK
2.2 V
3 V
50
50
150
100
600
600
UART receive deglitch time
(see Note 1)
τ
NOTE 1: Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI master mode) (see Figure 18 and Figure 19)
PARAMETER
TEST CONDITIONS
SMCLK, ACLK
Duty Cycle = 50% 10%
V
MIN
TYP
MAX UNIT
CC
f
t
t
t
USCI input clock frequency
f
MHz
ns
USCI
SYSTEM
2.2 V
3 V
110
75
0
SOMI input data setup time
SOMI input data hold time
SIMO output data valid time
SU,MI
2.2 V
3 V
ns
HD,MI
0
2.2 V
3 V
30
20
UCLK edge to SIMO valid;
C = 20 pF
L
ns
VALID,MO
USCI (SPI slave mode) (see Figure 20 and Figure 21)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX UNIT
STE lead time
STE low to clock
t
t
t
t
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
50
ns
STE,LEAD
STE,LAG
STE,ACC
STE,DIS
STE lag time
Last clock to STE high
10
ns
ns
ns
STE access time
STE low to SOMI data out
50
50
STE disable time
STE high to SOMI high impedance
2.2 V
3 V
20
15
10
10
t
t
t
SIMO input data setup time
SIMO input data hold time
SOMI output data valid time
ns
SU,SI
2.2 V
3 V
ns
HD,SI
2.2 V
3 V
75
50
110
UCLK edge to SOMI valid;
C = 20 pF
L
ns
VALID,SO
75
47
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH tLOW/HIGH
tSU,MI
tHD,MI
SOMI
SIMO
tVALID,MO
Figure 18. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLOW/HIGH tLOW/HIGH
tHD,MI
tSU,MI
SOMI
SIMO
tVALID,MO
Figure 19. SPI Master Mode, CKPH = 1
48
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLOW/HIGH tLOW/HIGH
tSU,SIMO
tHD,SIMO
SIMO
SOMI
tACC
tVALID,SOMI
tDIS
Figure 20. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
CKPL=1
UCLK
tLOW/HIGH tLOW/HIGH
tHD,SI
tSU,SI
SIMO
SOMI
tACC
tVALID,SO
tDIS
Figure 21. SPI Slave Mode, CKPH = 1
49
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (I2C mode) (see Figure 22)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX UNIT
MHz
Internal: SMCLK, ACLK
External: UCLK
f
USCI input clock frequency
f
SYSTEM
USCI
Duty Cycle = 50% 10%
f
t
SCL clock frequency
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V
0
4.0
0.6
4.7
0.6
0
400 kHz
SCL
f
f
f
f
≤ 100kHz
> 100kHz
≤ 100kHz
> 100kHz
SCL
SCL
SCL
SCL
Hold time (repeated) START
µs
HD,STA
t
Set−up time for a repeated START
µs
SU,STA
t
t
t
Data hold time
ns
HD,DAT
SU,DAT
SU,STO
Data set−up time
Set−up time for STOP
250
4.0
50
ns
µs
150
100
600
Pulse width of spikes suppressed by
input filter
t
SP
ns
3 V
50
600
tHD
tSU
tHD
tBUF
,STA
,STA
,STA
SDA
tLOW
tHIGH
tSP
SCL
tSU ,DAT
tSU
,STO
tHD
,DAT
Figure 22. I2C Mode Timing
USART1 (see Note 1)
PARAMETER
TEST CONDITIONS
V
MIN
200
150
TYP MAX
UNIT
CC
SYNC = 0, UART mode 2.2 V
SYNC = 0, UART mode 3 V
430
280
800
500
t
τ
( )
USART1 deglitch time
ns
NOTE 1: The signal applied to the USART1 receive signal/terminal (URXD1) should meet the timing requirements of t to ensure that the URXS
(τ
)
flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t . The operating conditions to
(τ
)
set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the
URXD1 line.
50
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, power supply and input range conditions (see Note 1)
PARAMETER
TEST CONDITIONS
AV and DV are connected together,
MIN TYP
MAX
UNIT
CC
CC
AV
Analog supply voltage
AV and DV are connected together,
2.2
3.6
V
CC
SS
SS
V
(AVSS)
= V
= 0 V
(DVSS)
All external Ax terminals. Analog inputs
selected in ADC12MCTLx register and P6Sel.x=1,
Analog input voltage
range (see Note 2)
V
0
V
AVCC
V
(P6.x/Ax)
V
(AVSS)
≤ V ≤ V
Ax (AVCC)
Operating supply current
f
= 5.0 MHz,
V
V
= 2.2 V
= 3 V
0.65
0.8
1.3
1.6
ADC12CLK
CC
into AV terminal
ADC12ON = 1, REFON = 0,
SHT0=0, SHT1=0, ADC12DIV=0
I
mA
mA
CC
ADC12
REF+
(see Note 3)
CC
f
= 5.0 MHz,
ADC12CLK
ADC12ON = 0,
REFON = 1, REF2_5V = 1
V
= 3 V
0.5
0.8
CC
Operating supply current
I
into AV terminal
CC
f
= 5.0 MHz,
V
V
= 2.2 V
= 3 V
0.5
0.5
0.8
0.8
ADC12CLK
CC
(see Note 4)
ADC12ON = 0,
REFON = 1, REF2_5V = 0
mA
CC
Only one terminal can be selected
at one time, Ax
C
R
Input capacitance
V
V
= 2.2 V
= 3 V
40
pF
I
I
CC
Input MUX ON resistance 0V ≤ V ≤ V
2000
Ω
Ax
AVCC
CC
NOTES: 1. The leakage current is defined in the leakage current table with Ax parameter.
2. The analog input voltage range must be within the selected reference voltage range V to V for valid conversion results.
R+
R−
3. The internal reference supply current is not included in current consumption parameter I
.
ADC12
4. The internal reference current is supplied via terminal AV . Consumption is independent of the ADC12ON control bit, unless a
CC
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
12-bit ADC, external reference (see Note 1)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
Positive external
reference voltage input
V
V
> V
> V
> V
/V
(see Note 2)
(see Note 3)
(see Note 4)
1.4
V
V
eREF+
eREF+
REF− eREF−
AVCC
Negative external
reference voltage input
V
V
V
eREF+
/V
REF− eREF−
0
1.2
V
V
REF− / eREF−
(V
−
Differential external
reference voltage input
eREF+
V
eREF+
/V
1.4
V
AVCC
REF− eREF−
V
V
)
REF−/ eREF−
I
Input leakage current
Input leakage current
0V ≤V
≤ V
V
V
= 2.2 V/3 V
= 2.2 V/3 V
1
1
µA
µA
VeREF+
eREF+
AVCC
CC
I
0V ≤ V
≤ V
VREF−/VeREF−
eREF− AVCC
CC
NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, C , is also
I
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
51
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, built-in reference
PARAMETER
TEST CONDITIONS
REF2_5V = 1 for 2.5 V,
max ≤ I ≤ I
V
MIN TYP
MAX
UNIT
CC
3 V
2.4
1.44
2.2
2.5
1.5
2.6
Positive built-in
reference voltage
output
I
min
VREF+ VREF+
VREF+
V
REF+
V
REF2_5V = 0 for 1.5 V,
max ≤ I ≤ I
2.2 V/3 V
1.56
I
min
VREF+
VREF+ VREF+
REF2_5V = 0, I max ≤ I
VREF+ VREF+
AV minimum
CC
≤ I min
VREF+
voltage, Positive
built-in reference
active
AV
V
CC(min)
REF2_5V = 1, I
min ≥ I
min ≥ I
≥ −0.5mA
≥ −1mA
2.8
2.9
VREF+
VREF+
REF2_5V = 1, I
VREF+
VREF+
2.2 V
3 V
0.01
0.01
−0.5
−1
Load current out of
I
mA
VREF+
V
REF+
terminal
I
= 500 µA +/− 100 µA,
2.2 V
3 V
2
2
VREF+
Analog input voltage ~0.75 V;
REF2_5V = 0
LSB
Load-current
regulation V
terminal
I
REF+
L(VREF)+
I
= 500 µA 100 µA,
VREF+
Analog input voltage ~1.25 V,
REF2_5V = 1
3 V
2
LSB
Load current
regulation V
terminal
I
C
=100 µA → 900 µA,
=5 µF, ax ~0.5 x V ,
REF+
VREF+
I
3 V
20
ns
REF+
VREF+
DL(VREF) +
Error of conversion result ≤ 1 LSB
Capacitance at pin
REFON =1,
C
2.2 V/3 V
2.2 V/3 V
5
10
µF
VREF+
V
REF+
(see Note 1)
0 mA ≤ I
≤ I
max
VREF+
VREF+
Temperature
coefficient of built-in
reference
I
is a constant in the range of
VREF+
T
REF+
100 ppm/°C
0 mA ≤ I
≤ 1 mA
VREF+
Settle time of internal
reference voltage
(see Figure 23 and
Note 2)
I
V
= 0.5 mA, C
= 10 µF,
VREF+
VREF+
17
ms
t
REFON
= 1.5 V, V
= 2.2 V
REF+
AVCC
NOTES: 1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses
two capacitors between pins V
and AV and V
/V
and AV : 10 µF tantalum and 100 nF ceramic.
REF+
SS
REF− eREF−
SS
2. The condition is that the error in a conversion started after t
capacitive load.
is less than 0.5 LSB. The settling time depends on the external
REFON
52
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
C
VREF+
100 µF
t
≈ .66 x C
[ms] with C
in µF
REFON
VREF+
VREF+
10 µF
1 µF
0
10 ms
1 ms
100 ms
t
REFON
Figure 23. Typical Settling Time of Internal Reference t
vs External Capacitor on V
+
REF
REFON
53
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
DV
DV
From
Power
Supply
CC1/2
+
−
SS1/2
10 µF 100 nF
AV
CC
SS
+
−
MSP430FG461x
AV
10 µF 100 nF
Apply External Reference [V
or Use Internal Reference [V
]
eREF+
V
REF+
or V
eREF+
]
REF+
+
−
10 µF 100 nF
Apply
V
REF
−/V
eREF−
External
Reference
+
−
10 µF 100 nF
Figure 24. Supply Voltage and Reference Voltage Design V
V
External Supply
REF−/ eREF−
DV
From
Power
Supply
CC1/2
SS1/2
+
−
DV
10 µF 100 nF
AV
CC
SS
+
−
MSP430FG461x
AV
10 µF 100 nF
Apply External Reference [V
or Use Internal Reference [V
]
eREF+
V
REF+
or V
]
eREF+
REF+
+
−
10 µF 100 nF
Reference Is Internally
Switched to AV
V
/V
REF− eREF−
SS
Figure 25. Supply Voltage and Reference Voltage Design V
V
= AV , Internally Connected
REF−/ eREF− SS
54
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, timing parameters
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
For specified performance of ADC12
linearity parameters
f
f
2.2V/3 V
2.2 V/ 3 V
2.2 V/ 3 V
0.45
5
6.3
MHz
ADC12CLK
Internal ADC12
oscillator
ADC12DIV=0,
3.7
5
6.3
MHz
µs
ADC12OSC
f
=f
ADC12CLK ADC12OSC
C
≥ 5 µF, Internal oscillator,
VREF+
2.06
3.51
f
= 3.7 MHz to 6.3 MHz
ADC12OSC
t
Conversion time
CONVERT
External f
from ACLK,
13×ADC12DIV×
ADC12CLK
µs
MCLK, or SMCLK, ADC12SSEL ≠ 0
1/f
ADC12CLK
Turn on settling time of
the ADC
t
t
See Note 1
100
ns
ADC12ON
R = 400 Ω, R = 1000 Ω,
3 V
1220
1400
S
I
Sampling time
ns
C = 30 pF, τ = [R + R ] x C ,
Sample
I
S
I
I
2.2 V
(see Note 2)
NOTES: 1. The condition is that the error in a conversion started after t
settled.
is less than 0.5 LSB. The reference and input signal are already
ADC12ON
2. Approximately ten Tau (τ) are needed to get an error of less than 0.5 LSB:
n+1
t
= ln(2 ) x (R + R ) x C + 800 ns where n = ADC resolution = 12, R = external source resistance.
Sample
S
I
I
S
12-bit ADC, linearity parameters
PARAMETER
TEST CONDITIONS
V
MIN TYP
MAX
2
UNIT
CC
1.4 V ≤ (V
− V
− V
/V
/V
) min ≤ 1.6 V
eREF+
REF− eREF−
E
E
Integral linearity error
2.2 V/3 V
2.2 V/3 V
LSB
I
1.6 V < (V
/V
) min ≤ [V
]
1.7
eREF+
REF− eREF−
AVCC
Differential linearity
error
(V
C
− V
)
≤ (V
− V
/V
),
),
eREF+
REF− eREF− min
eREF+
REF− eREF−
1
LSB
LSB
D
= 10 µF (tantalum) and 100 nF (ceramic)
VREF+
(V
eREF+
− V
/V
)
≤ (V
− V /V
REF− eREF−
REF− eREF− min
eREF+
E
O
Internal impedance of source R < 100 Ω,
2.2 V/3 V
2
4
Offset error
Gain error
S
C
= 10 µF (tantalum) and 100 nF (ceramic)
VREF+
(V
C
− V
/V
)
≤ (V
− V /V
),
),
eREF+
REF− eREF− min
eREF+
REF− eREF−
E
E
2.2 V/3 V
2.2 V/3 V
1.1
2
2
5
LSB
LSB
G
= 10 µF (tantalum) and 100 nF (ceramic)
VREF+
(V
C
− V
/V
)
≤ (V
− V /V
REF− eREF−
Total unadjusted
error
eREF+
VREF+
REF− eREF− min
eREF+
T
= 10 µF (tantalum) and 100 nF (ceramic)
55
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, temperature sensor and built-in V
MID
TEST CONDITIONS
PARAMETER
V
MIN
TYP
MAX
120
UNIT
CC
2.2 V
3 V
40
60
Operating supply current into REFON = 0, INCH = 0Ah,
I
µA
SENSOR
AV terminal (see Note 1)
ADC12ON=NA, T = 25_C
CC
A
160
ADC12ON = 1, INCH = 0Ah,
T = 0°C
A
2.2 V/
3 V
V
See Note 2
986
mV
SENSOR
2.2 V/
3 V
TC
ADC12ON = 1, INCH = 0Ah
3.55 3%
mV/°C
SENSOR
Sample time required if
channel 10 is selected
(see Note 3)
2.2 V
3 V
30
30
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
t
µs
SENSOR(sample)
VMID
2.2 V
3 V
NA
NA
Current into divider at
channel 11 (see Note 4)
I
ADC12ON = 1, INCH = 0Bh
ADC12ON = 1, INCH = 0Bh,
µA
2.2 V
3 V
1.1
1.1 0.04
V
AV divider at channel 11
V
MID
CC
V
MID
is ~0.5 x V
AVCC
1.5 1.50 0.04
Sample time required if
channel 11 is selected
(see Note 5)
2.2 V 1400
3 V 1220
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
t
ns
VMID(sample)
NOTES: 1. The sensor current I
is consumed if (ADC12ON = 1 and REFON=1), or (ADC12ON=1 AND INCH=0Ah and sample signal
SENSOR
is high). When REFON = 1, I
is already included in I
.
SENSOR
REF+
2. The temperature sensor offset can be as much as 20_C. A single-point calibration is recommended in order to minimize the offset
error of the built-in temperature sensor.
3. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t
SENSOR(on)
4. No additional current is needed. The V
is used during sampling.
MID
5. The on-time t
is included in the sampling time t ; no additional on time is needed.
VMID(sample)
VMID(on)
56
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
flash memory
TEST
CONDITIONS
PARAMETER
V
CC
MIN
TYP
MAX
UNIT
V
CC(PGM/
ERASE)
Program and Erase supply voltage
Flash Timing Generator frequency
2.7
3.6
V
f
I
I
257
476
5
kHz
mA
mA
FTG
Supply current from DV during program
2.7 V/3.6 V
2.7 V/3.6 V
3
3
PGM
CC
Supply current from DV during erase
See Note 3
See Note 4
See Note 1
7
ERASE
CC
Supply current from DV during global mass
CC
I
2.7 V/3.6 V
6
14
10
mA
GMERASE
erase
t
t
Cumulative program time
Cumulative mass erase time
Program/Erase endurance
Data retention duration
Word or byte program time
2.7 V/3.6 V
2.7 V/3.6 V
ms
ms
CPT
20
CMErase
4
5
10
10
cycles
years
t
t
t
T = 25°C
J
100
Retention
30
25
Word
st
Block program time for 1 byte or word
Block, 0
Block program time for each additional byte or
word
t
18
Block, 1-63
See Note 2
t
FTG
t
t
t
t
Block program end-sequence wait time
Mass erase time
6
10593
10593
4819
Block, End
Mass Erase
Global Mass Erase
Seg Erase
Global mass erase time
Segment erase time
NOTES: 6. The cumulative program time must not be exceeded during a block-write operation. This parameter is only relevant if the block write
feature is used.
2. These values are hardwired into the Flash Controller’s state machine (t
3. Lower 64-KB or upper 64-KB Flash memory erased.
4. All Flash memory erased.
= 1/f ).
FTG
FTG
JTAG interface
TEST
CONDITIONS
PARAMETER
V
CC
MIN
TYP
MAX
UNIT
2.2 V
3 V
0
0
5
10
90
MHz
MHz
kΩ
f
TCK input frequency
See Note 1
TCK
R
Internal pull-up resistance on TMS, TCK, TDI/TCLK See Note 2
may be restricted to meet the timing requirements of the module selected.
2.2 V/ 3 V
25
60
Internal
NOTES: 1. f
TCK
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
V
V
Supply voltage during fuse-blow condition
Voltage level on TDI/TCLK for fuse-blow: F versions
Supply current into TDI/TCLK during fuse blow
Time to blow fuse
T = 25°C
A
2.5
6
V
V
CC(FB)
7
100
1
FB
I
t
mA
ms
FB
FB
NOTE 1: Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
57
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
APPLICATION INFORMATION
input/output schematics
port P1, P1.0 to P1.5, input/output with Schmitt trigger
Pad Logic
DV
DV
SS
SS
DV
SS
P1DIR.x
0
1
Direction
0: Input
1: Output
P1OUT.x
0
1
Module X OUT
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
Bus
Keeper
P1SEL.x
EN
P1IN.x
EN
D
Module X IN
P1IE.x
EN
P1IRQ.x
Q
Set
P1IFG.x
Interrupt
Edge
Select
P1SEL.x
P1IES.x
Note: x = 0,1,2,3,4,5
58
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P1 (P1.0 to P1.5) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
P1.0/TA0
X
FUNCTION
P1DIR.x
P1SEL.x
0
P1.0 (I/O)
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
Timer_A3.CCI0A
Timer_A3.TA0
P1.1 (I/O)
0
1
P1.1/TA0/MCLK
1
2
3
4
5
I: 0; O: 1
Timer_A3.CCI0B
MCLK
0
1
P1.2/TA1
P1.2 (I/O)
I: 0; O: 1
Timer_A3.CCI1A
Timer_A3.TA1
P1.3 (I/O)
0
1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
I: 0; O: 1
Timer_B7.TBOUTH
SVSOUT
0
1
P1.4 (I/O)
I: 0; O: 1
Timer_B7.TBCLK
SMCLK
0
1
P1.5 (I/O)
I: 0; O: 1
Timer_A3.TACLK
ACLK
0
1
59
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P1, P1.6, P1.7, input/output with Schmitt trigger
Pad Logic
DV
DV
SS
SS
CAPD.x
P1DIR.x
0
1
Direction
0: Input
1: Output
P1OUT.x
0
1
Module X OUT
P1.6/CA0
P1.7/CA1
Bus
Keeper
P1SEL.x
EN
P1IN.x
EN
D
Module X IN
P2CA0
P1IE.x
EN
P1IRQ.x
Comp_A
0
1
Q
CA0
CA1
Set
P1IFG.x
+
−
Interrupt
Edge
P1SEL.x
P1IES.x
0
1
Select
Note: x = 6,7
P2CA1
port P1 (P1.6 and P1.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
CAPD.x
P1DIR.x
I: 0; O: 1
X
P1SEL.x
P1.6/CA0
6
P1.6 (I/O)
CA0
0
1
0
1
0
X
0
P1.7/CA1
7
P1.7 (I/O)
CA1
I: 0; O: 1
X
X
NOTE 1: X: Don’t care.
60
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P2, P2.0 to P2.3, P2.6 to P2.7, input/output with Schmitt trigger
Pad Logic
DV
DV
SS
SS
TBOUTH
P2DIR.x
0
1
Direction
0: Input
1: Output
P2OUT.x
0
1
Module X OUT
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
P2.6/CAOUT
P2.7/ADC12CLK/DMAE0
Bus
Keeper
P2SEL.x
EN
P2IN.x
EN
D
Module X IN
P2IE.x
EN
P2IRQ.x
Q
Set
P2IFG.x
Interrupt
Edge
Select
P2SEL.x
P2IES.x
Note: x = 0,1,2,3,6,7
61
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P2 (P2.0, P2.1, P2.2, P2.3, P2.6 and P2.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.X)
P2.0/TA2
X
FUNCTION
P2DIR.x
P2SEL.x
0
P2.0 (I/O)
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
1
Timer_A3.CCI2A
Timer_A3.TA2
P2.1 (I/O)
0
1
P2.1/TB0
P2.2/TB1
P2.3/TB3
1
2
3
I: 0; O: 1
Timer_B7.CCI0A and Timer_B7.CCI0B
Timer_B7.TB0 (see Note 1)
P2.2 (I/O)
0
1
I: 0; O: 1
Timer_B7.CCI1A and Timer_B7.CCI1B
Timer_B7.TB1 (see Note 1)
P2.3 (I/O)
0
1
I: 0; O: 1
Timer_B7.CCI2A and Timer_B7.CCI2B
Timer_B7.TB3 (see Note 1)
P2.6 (I/O)
0
1
P2.6/CAOUT
6
7
I: 0; O: 1
CAOUT
1
P2.7/ADC12CLK/DMAE0
P2.7 (I/O)
I: 0; O: 1
ADC12CLK (MSP430F461x only)
DMAE0
1
0
NOTE 1: Setting TBOUTH causes all Timer_B outputs to be set to high impedance.
62
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P2, P2.4 to P2.5, input/output with Schmitt trigger
Pad Logic
DV
DV
SS
SS
DV
SS
P2DIR.x
0
1
Direction
0: Input
1: Output
Direction control
from Module X
P2OUT.x
0
1
Module X OUT
P2.4/UCA0TXD
P2.5/UCA0RXD
Bus
Keeper
EN
P2SEL.x
P2IN.x
EN
D
Module X IN
P2IE.x
EN
P2IRQ.x
Q
Set
P2IFG.x
Interrupt
Edge
Select
P2SEL.x
P2IES.x
Note: x = 4,5
port P2 (P2.4 and P2.5) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.X)
X
FUNCTION
P2DIR.x
I: 0; O: 1
X
P2SEL.x
P2.4/UCA0TXD
4
P2.4 (I/O)
0
1
0
1
USCI_A0.UCA0TXD (see Note 1, 2)
P2.5 (I/O)
P2.5/UCA0RXD
5
I: 0; O: 1
X
USCI_A0.UCA0RXD (see Note 1, 2)
NOTES: 1. X: Don’t care.
2. When in USCI mode, P2.4 is set to output, P2.5 is set to input.
63
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P3, P3.0 to P3.3, input/output with Schmitt trigger
Pad Logic
DV
DV
SS
SS
DV
SS
P3DIR.x
0
1
Direction
0: Input
1: Output
P3OUT.x
0
1
Module X OUT
P3.0/UCB0STE
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK
Bus
Keeper
P3SEL.x
P3IN.x
EN
EN
D
Module X IN
Note: x = 0,1,2,3
port P3 (P3.0 to P3.3) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P3.X)
X
FUNCTION
P3DIR.x
I: 0; O: 1
X
P3SEL.x
P3.0/UCB0STE
0
P3.0 (I/O)
0
1
0
1
0
1
0
1
UCB0STE (see Notes 1, 2)
P3.1 (I/O)
P3.1/UCB0SIMO/
UCB0SDA
1
2
3
I: 0; O: 1
X
UCB0SIMO/UCB0SDA (see Notes 1, 2, 3)
P3.2 (I/O)
P3.2/UCB0SOMI/
UCB0SCL
I: 0; O: 1
X
UCB0SOMI/UCB0SCL (see Notes 1, 2, 3)
P3.3 (I/O)
P3.3/UCB0CLK
I: 0; O: 1
X
UCB0CLK (see Notes 1, 2)
NOTES: 1. X: Don’t care.
2. The pin direction is controlled by the USCI module.
3. In case the I2C functionality is selected the output drives only the logical 0 to V level.
SS
64
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P3, P3.4 to P3.7, input/output with Schmitt trigger
Pad Logic
DV
DV
SS
SS
TBOUTH
P3DIR.x
0
1
Direction
0: Input
1: Output
P3OUT.x
0
1
Module X OUT
P3.4/TB3
P3.5/TB4
Bus
P3SEL.x
P3IN.x
P3.6/TB5
Keeper
P3.7/TB6
EN
EN
D
Module X IN
Note: x = 4,5,6,7
port P3 (P3.4 to P3.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P3.X)
X
FUNCTION
P3DIR.x
P3SEL.x
P3.4/TB3
4
P3.4 (I/O)
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
Timer_B7.CCI3A and Timer_B7.CCI3B
Timer_B7.TB3 (see Note 1)
P3.5 (I/O)
0
1
P3.5/TB4
P3.6/TB5
P3.7/TB6
5
6
7
I: 0; O: 1
Timer_B7.CCI4A and Timer_B7.CCI4B
Timer_B7.TB4 (see Note 1)
P3.6 (I/O)
0
1
I: 0; O: 1
Timer_B7.CCI5A and Timer_B7.CCI5B
Timer_B7.TB5 (see Note 1)
P3.7 (I/O)
0
1
I: 0; O: 1
Timer_B7.CCI6A and Timer_B7.CCI6B
Timer_B7.TB6 (see Note 1)
0
1
NOTE 1: Setting TBOUTH causes all Timer_B outputs to be set to high impedance.
65
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P4, P4.0 to P4.1, input/output with Schmitt trigger
Pad Logic
DV
SS
DV
SS
DV
SS
P4DIR.x
0
1
Direction
0: Input
1: Output
Direction control
from Module X
0
1
P4OUT.x
Module X OUT
P4.1/URXD1
P4.0/UTXD1
Bus
Keeper
P4SEL.x
EN
P4IN.x
Module X IN
Note: x = 0,1
EN
D
port P4 (P4.0 to P4.1) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P4.X)
X
FUNCTION
P4DIR.x
I: 0; O: 1
X
P4SEL.x
P4.0/UTXD1
0
P4.0 (I/O)
0
1
0
1
USART1.UTXD1 (see Notes 1, 2)
P4.1 (I/O)
P4.1/URXD1
1
I: 0; O: 1
X
USART1.URXD1 (see Notes 1, 2)
NOTES: 1. X: Don’t care.
2. When in USART1 mode, P4.0 is set to output, P4.1 is set to input.
66
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P4, P4.2 to P4.7, input/output with Schmitt trigger
Pad Logic
LCDS32/36
Segment Sy
DV
SS
P4DIR.x
0
1
Direction
0: Input
1: Output
Direction control
from Module X
0
1
P4OUT.x
Module X OUT
P4.7/UCA0RXD/S34
P4.6/UCA0TXD/S35
P4.5/UCLK1/S36
P4.4/SOMI1/S37
P4.3/SIMO1/S38
P4.2/STE1/S39
Bus
Keeper
P4SEL.x
EN
P4IN.x
EN
D
Module X IN
Note :x = 2,3,4,5,6,7
= 34,35,36,37,38,39
y
67
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P4 (P4.2 to P4.5) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P4.X)
X
FUNCTION
P4DIR.x
P4SEL.x
LCDS36
P4.2/STE1/S39
2
P4.2 (I/O)
I: 0; O: 1
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
USART1.STE1
S39 (see Note 1)
P4.3 (I/O)
X
X
P4.3/SIMO/S38
3
4
5
6
7
I: 0; O: 1
USART1.SIMO1 (see Notes 1, 2)
S38 (see Note 1)
X
X
P4.4/SOMI/S37
P4.4 (I/O)
I: 0; O: 1
USART1.SOMI1 (see Notes 1, 2)
S37 (see Note 1)
X
X
P4.5/SOMI/S36
P4.5 (I/O)
I: 0; O: 1
USART1.UCLK1 (see Notes 1, 2)
S36 (see Note 1)
X
X
P4.6/UCA0TXD/S35
P4.7/UCA0RXD/S34
P4.6 (I/O)
I: 0; O: 1
USCI_A0.UCA0TXD (see Notes 1, 3)
S35 (see Note 1)
X
X
P4.7 (I/O)
I: 0; O: 1
USCI_A0.UCA0RXD (see Notes 1, 3)
S34 (see Note 1)
X
X
NOTES: 1. X: Don’t care.
2. The pin direction is controlled by the USART1 module.
3. When in USCI mode, P4.6 is set to output, P4.7 is set to input.
68
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P5, P5.0, input/output with Schmitt trigger
#
INCH=13
Pad Logic
#
A13
LCDS0
Segment Sy
P5DIR.x
0
1
Direction
0: Input
1: Output
0
1
P5OUT.x
DV
SS
P5.0/S1/A13
Bus
Keeper
P5SEL.x
P5IN.x
EN
Note:x = 0
y = 1
# = Signal from or to ADC12
(MSP430x461x only)
port P5 (P5.0) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P5.X)
X
FUNCTION
P5DIR.x
P5SEL.x
INCHx
LCDS0
P5.0/S1/A13
0
P5.0 (I/O) (see Note 1)
I: 0; O: 1
0
1
0
1
X
13
X
0
X
1
1
A13 (MSP430x461x only, see Notes 1, 3)
S1 enabled (see Note 1)
X
X
X
S1 disabled (see Note 1)
X
NOTES: 1. X: Don’t care.
2. N/A: Not available or not applicable.
3. Setting the P5SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
69
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P5, P5.1, input/output with Schmitt trigger
#
INCH=12
Pad Logic
#
A12
LCDS0
Segment Sy
DVSS
P5DIR.x
0
1
Direction
0: Input
1: Output
0
1
P5OUT.x
DV
SS
P5.1/S0/A12
Bus
Keeper
P5SEL.x
P5IN.x
EN
Note:x = 1
y = 0
# = Signal from or to ADC12
(MSP430x461x only)
port P5 (P5.1) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P5.X)
X
FUNCTION
P5DIR.x
P5SEL.x
INCHx
LCDS0
P5.1/S0/A12
1
P5.1 (I/O) (see Note 1)
I: 0; O: 1
0
1
0
X
12
X
0
0
1
A12 (MSP430x461x only, see Notes 1, 2)
S0 enabled (see Note 1)
X
X
S0 disabled
(see Note 1)
X
1
X
1
NOTES: 1. X: Don’t care.
2. Setting the P5SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
70
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P5, P5.2 to P5.4, input/output with Schmitt trigger
Pad Logic
LCD Signal
DV
SS
P5DIR.x
P5OUT.x
0
1
Direction
0: Input
1: Output
0
1
DV
SS
P5.2/COM1
P5.3/COM2
P5.4/COM3
Bus
Keeper
P5SEL.x
EN
P5IN.x
Note: x = 2,3,4
port P5 (P5.2 to P5.4) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P5.X)
X
FUNCTION
P5DIR.x
I: 0; O: 1
X
P5SEL.x
P5.2/COM1
2
P5.2 (I/O)
0
1
0
1
0
1
COM1 (see Note 1)
P5.3 (I/O)
P5.3/COM2
3
4
I: 0; O: 1
X
COM2 (see Note 1)
P5.4 (I/O)
P5.4/COM3
I: 0; O: 1
X
COM3 (see Note 1)
NOTE 1: X: Don’t care.
71
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P5, P5.5 to P5.7, input/output with Schmitt trigger
Pad Logic
LCD Signal
DV
SS
P5DIR.x
P5OUT.x
0
1
Direction
0: Input
1: Output
0
1
DV
SS
P5.5/R03
P5.6/LCDREF/R13
P5.7/R03
Bus
Keeper
P5SEL.x
EN
P5IN.x
Note:x = 5,6,7
port P5 (P5.5 to P5.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P5.X)
X
FUNCTION
P5DIR.x
I: 0; O: 1
X
P5SEL.x
P5.5/R03
5
P5.5 (I/O)
0
1
0
1
0
1
R03 (see Note 1)
P5.6 (I/O)
P5.6/LCDREF/R13
P5.7/R03
6
7
I: 0; O: 1
X
R13 or LCDREF (see Notes 1, 2)
P5.7 (I/O)
I: 0; O: 1
X
R03 (see Note 1)
NOTES: 1. X: Don’t care.
2. External reference for the LCD_A charge pump is applied when VLCDREFx = 01. Otherwise R13 is selected.
72
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P6, P6.0, P6.2, and P6.4, input/output with Schmitt trigger
#
INCH=0/2/4
Pad Logic
#
Ay
P6DIR.x
0
1
Direction
0: Input
1: Output
P6.0/A0
P6.2/A2
P6.4/A4
0
1
P6OUT.x
DV
SS
Bus
Keeper
P6SEL.x
EN
P6IN.x
Note:x = 0, 2, 4
y = 0, 1
# = Signal from or to ADC12
(MSP430x461x only)
port P6 (P6.0, P6.2, and P6.4) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X)
X
FUNCTION
P6DIR.x
P6SEL.x
INCHx
P6.0/A0
0
P6.0 (I/O) (see Note 1)
I: 0; O: 1
0
1
0
1
0
1
X
0
X
2
X
4
A0 (MSP430x461x only, see Notes 1, 3)
P6.2 (I/O) (see Note 1)
X
I: 0; O: 1
X
P6.2/A2
P6.4/A4
2
4
A2 (MSP430x461x only, see Notes 1, 3)
P6.4 (I/O) (see Note 1)
I: 0; O: 1
X
A4 (MSP430x461x only, see Notes 1, 3)
NOTES: 1. X: Don’t care.
2. N/A: Not available or not applicable.
3. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
73
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P6, P6.1, P6.3, and P6.5 input/output with Schmitt trigger
#
INCH=1/3/5
Pad Logic
#
Ay
P6DIR.x
0
1
Direction
0:Input
1:Output
P6.1/A1
P6.3/A3
P6.5/A5
0
1
P6OUT.x
DV
SS
Bus
Keeper
P6SEL.x
P6IN.x
EN
Note:x = 1, 3, 5
y = 0, 1, 2
# = Signal from or to ADC12
(MSP430x461x only)
port P6 (P6.1, P6.3, and P6.5) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X)
X
FUNCTION
P6DIR.x
P6SEL.x
INCHx
P6.1/A1
1
P6.1 (I/O) (see Note 1)
I: 0; O: 1
0
1
0
1
0
1
X
1
X
3
X
5
A1 (MSP430x461x only, see Notes 1, 3)
P6.3 (I/O) (see Note 1)
X
I: 0; O: 1
X
P6.3/A3
P6.5/A5
3
5
A3 (MSP430x461x only, see Notes 1, 3)
P6.5 (I/O) (see Note 1)
I: 0; O: 1
X
A5 (MSP430x461x only, see Notes 1, 3)
NOTES: 1. X: Don’t care.
2. N/A: Not available or not applicable.
3. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
74
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P6, P6.6, input/output with Schmitt trigger
#
INCH=6
Pad Logic
#
A6
P6DIR.x
P6OUT.x
0
1
Direction
0: Input
1: Output
P6.6/A6
0
1
DV
SS
Bus
Keeper
P6SEL.x
P6IN.x
EN
Note:x = 6
# = Signal from or to ADC12
(MSP430x461 only)
port P6 (P6.6) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X)
X
FUNCTION
P6DIR.x
I: 0; O: 1
X
P6SEL.x
INCHx
P6.6/A6
6
P6.6 (I/O) (see Note 1)
0
1
X
6
A6 (MSP430x461x only, see Notes 1, 2)
NOTES: 1. X: Don’t care.
2. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
75
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P6, P6.7, input/output with Schmitt trigger
To SVS Mux
#
INCH=7
Pad Logic
#
A7
P6DIR.x
P6OUT.x
0
1
Direction
0: Input
1: Output
0
1
DV
SS
P6.7/A7/SVSIN
Bus
Keeper
P6SEL.x
VLD =15
EN
P6IN.x
Note:x = 7
# = Signal from or to ADC12
(MSP430x461x only)
port P6 (P6.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X)
X
FUNCTION
P6DIR.x
P6SEL.x
INCHx
P6.7/A7/SVSIN
7
P6.7 (I/O) (see Note 1)
I: 0; O: 1
0
1
1
X
7
0
A7 (MSP430x461x only, see Notes 1, 2)
SVSIN (see Notes 1,3)
X
0
NOTES: 1. X: Don’t care.
2. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
3. Setting VLDx = 15 will also cause the external SVSIN to be used. In this case, the P6SEL.x bit is a do not care.
76
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P7, P7.0 to P7.3, input/output with Schmitt trigger
Pad Logic
LCDS28/32
Segment Sy
DV
SS
P7DIR.x
0
1
Direction
0: Input
1: Output
Direction control
from Module X
0
1
P7OUT.x
Module X OUT
P7.3/UCA0CLK/S30
P7.2/UCA0SOMI/S31
P7.1/UCA0SIMO/S32
P7.0/UCA0STE/S33
Bus
Keeper
P7SEL.x
P7IN.x
EN
EN
D
Module X IN
Note:x = 0, 1, 2, 3
y = 30, 31, 32, 33
77
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P7 (P7.0 to P7.1) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P7.X)
X
FUNCTION
P7DIR.x
P7SEL.x
LCDS32
P7.0/UCA0STE/S33
0
P7.0 (I/O)
I: 0; O: 1
0
1
X
0
1
X
0
1
X
0
1
X
0
0
1
0
0
1
0
0
1
0
0
1
USCI_A0.UCA0STE (see Notes 1, 2)
S33 (see Note 1)
X
X
P7.1/UCA0SIMO/S32
P7.2/UCA0SOMI/S31
P7.3/UCA0CLK/S30
1
2
3
P7.1 (I/O)
I: 0; O: 1
USCI_A0.UCA0SIMO (see Notes 1, 2)
S32 (see Note 1)
X
X
P7.2 (I/O)
I: 0; O: 1
USCI_A0.UCA0SOMI (see Notes 1, 3)
S31 (see Note 1)
X
X
P7.3 (I/O)
I: 0; O: 1
USCI_A0.UCA0CLK (see Notes 1, 3)
S30 (see Note 1)
X
X
NOTES: 1. X: Don’t care.
2. The pin direction is controlled by the USCI module.
3. The pin direction is controlled by the USCI module.
78
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P7, P7.4 to P7.7, input/output with Schmitt trigger
Pad Logic
LCDS24/28
Segment Sy
DV
SS
P7DIR.x
0
1
Direction
0: Input
1: Output
0
1
P7OUT.x
DV
SS
P7.7/S26
Bus
Keeper
P7SEL.x
P7IN.x
P7.6/S27
P7.5/S28
P7.4/S29
EN
Note:x = 4, 5, 6, 7
y = 26, 27, 28, 29
port P7 (P7.4 to P7.5) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P7.X)
X
FUNCTION
P7DIR.x
I: 0; O: 1
X
P7SEL.x
LCDS28
P7.4/S29
4
P7.4 (I/O)
0
X
0
0
1
0
1
0
1
0
1
S29 (see Note 1)
P7.5 (I/O)
P7.5/S28
5
6
7
I: 0; O: 1
X
S28 (see Note 1)
P7.6 (I/O)
X
0
P7.6/S27
I: 0; O: 1
X
S27 (see Note 1)
P7.7 (I/O)
X
0
P7.7/S26
I: 0; O: 1
X
S26 (see Note 1)
X
NOTE 1: X: Don’t care.
79
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P8, P8.0 to P8.7, input/output with Schmitt trigger
Pad Logic
LCDS16/20/24
Segment Sy
DV
SS
P8DIR.x
P8OUT.x
0
1
Direction
0: Input
1: Output
0
1
DV
SS
P8.7/S18
P8.6/S19
P8.5/S20
P8.4/S21
P8.3/S22
P8.2/S23
P8.1/S24
P8.0/S25
Bus
Keeper
P8SEL.x
P8IN.x
EN
Note: x = 0,1,2,3,4,5,6,7
y= 25,24,23,22,21,20,19,18
80
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P8 (P8.0 to P8.1) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P8.X)
X
FUNCTION
P8DIR.x
P8SEL.x
LCDS16
P8.0/S18
0
P8.0 (I/O)
I: 0; O: 1
0
X
0
0
1
0
1
0
1
0
1
0
1
0
1
S18 (see Note 1)
P8.0 (I/O)
X
P8.1/S19
P8.2/S20
0
2
3
4
5
I: 0; O: 1
S19 (see Note 1)
P8.2 (I/O)
X
X
0
I: 0; O: 1
S20 (see Note 1)
P8.3 (I/O)
X
X
0
P8.3/S21
I: 0; O: 1
S21 (see Note 1)
P8.4 (I/O)
X
I: 0; O: 1
X
X
0
P8.4/S22
S22 (see Note 1)
P8.5 (I/O)
X
0
P8.5/S23
I: 0; O: 1
X
S23 (see Note 1)
X
NOTE 1: X: Don’t care.
port P8 (P8.6 to P8.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P8.X)
X
FUNCTION
P8DIR.x
P8SEL.x
LCDS24
P8.6/S24
6
P8.6 (I/O)
I: 0; O: 1
0
X
0
0
1
0
1
S24 (see Note 1)
P8.7 (I/O)
X
I: 0; O: 1
X
P8.7/S25
7
S25 (see Note 1)
X
NOTE 1: X: Don’t care.
81
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MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P9, P9.0 to P9.7, input/output with Schmitt trigger
Pad Logic
LCDS8/12/16
Segment Sy
DV
SS
P9DIR.x
0
1
Direction
0:Input
1:Output
0
1
P9OUT.x
DV
SS
P9.7/S10
P9.6/S11
P9.5/S12
P9.4/S13
P9.3/S14
P9.2/S15
P9.1/S16
P9.0/S17
Bus
Keeper
P9SEL.x
P9IN.x
EN
Note: x = 0,1,2,3,4,5,6,7
y= 17,16,15,14,13,12,11,10
82
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P9 (P9.0 to P9.1) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P9.X)
X
FUNCTION
P9DIR.x
P9SEL.x
LCDS16
P9.0/S17
0
P9.0 (I/O)
I: 0; O: 1
0
X
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
S17 (see Note 1)
P9.1 (I/O)
X
P9.1/S16
P9.2/S20
1
2
3
4
5
6
7
I: 0; O: 1
S16 (see Note 1)
P9.2 (I/O)
X
X
0
I: 0; O: 1
S15 (see Note 1)
P9.3 (I/O)
X
X
0
P9.3/S21
I: 0; O: 1
S14 (see Note 1)
P9.4 (I/O)
X
X
0
P9.4/S22
I: 0; O: 1
S13 (see Note 1)
P9.5 (I/O)
X
X
0
P9.5/S23
I: 0; O: 1
S12 (see Note 1)
P9.6 (I/O)
X
I: 0; O: 1
X
X
0
P9.6/S24
S11 (see Note 1)
P9.7 (I/O)
X
0
P9.7/S25
I: 0; O: 1
X
S10 (see Note 1)
X
NOTE 1: X: Don’t care.
83
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MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P10, P10.0 to P10.5, input/output with Schmitt trigger
Pad Logic
LCDS4/8
Segment Sy
DV
SS
P10DIR.x
P10OUT.x
0
1
Direction
0: Input
1: Output
0
1
DV
SS
P10.5/S4
P10.4/S5
P10.3/S6
P10.2/S7
P10.1/S8
P10.0/S9
Bus
Keeper
P10SEL.x
P10IN.x
EN
Note:x = 0,1,2,3,4,5
y= 9,8,7,6,5,4
port P10 (P10.0 to P10.1) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P10.X)
X
FUNCTION
P10DIR.x
P10SEL.x
LCDS8
P10.0/S8
0
P10.0 (I/O)
I: 0; O: 1
0
X
0
0
1
0
1
0
1
0
1
0
1
0
1
S8 (see Note 1)
P10.1 (I/O)
X
P10.1/S7
P10.2/S7
1
2
3
4
5
I: 0; O: 1
S7 (see Note 1)
P10.2 (I/O)
X
X
0
I: 0; O: 1
S7 (see Note 1)
P10.3 (I/O)
X
X
0
P10.3/S6
I: 0; O: 1
S6 (see Note 1)
P10.4 (I/O)
X
I: 0; O: 1
X
X
0
P10.4/S5
S5 (see Note 1)
P10.5 (I/O)
X
0
P10.5/S4
I: 0; O: 1
X
S4 (see Note 1)
X
NOTE 1: X: Don’t care.
84
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P10, P10.6, input/output with Schmitt trigger
#
INCH=15
Pad Logic
#
A15
LCDS0
Segment Sy
P10DIR.x
P10OUT.x
0
1
Direction
0: Input
1: Output
0
1
DV
SS
P10.6/S3/A15
Bus
Keeper
P10SEL.x
EN
P10IN.x
Note: x = 6
= 3
y
# = Signal from or to ADC12
(MSP430x461x only)
port P10 (P10.6) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P10.X)
X
FUNCTION
P10DIR.x
P10SEL.x
INCHx
LCDS0
P10.6/S3/A15
6
P5.0 (I/O) (see Note 1)
I: 0; O: 1
0
1
0
1
X
15
X
0
0
1
1
A15 (MSP430x461x only, see Notes 1, 3)
S3 enabled (see Note 1)
X
X
X
S3 disabled (see Note 1)
X
NOTES: 1. X: Don’t care.
2. N/A: Not available or not applicable.
3. Setting the P10SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
85
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MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
port P10, P10.7, input/output with Schmitt trigger
#
INCH=14
Pad Logic
#
A14
LCDS0
Segment Sy
P10DIR.x
P10OUT.x
0
1
Direction
0: Input
1: Output
0
1
DV
SS
P10.7/S2/A14
Bus
Keeper
P10SEL.x
P10IN.x
EN
Note:x =7
y = 2
# = Signal from or to ADC12
(MSP430x461x only)
port P10 (P10.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P10.X)
X
FUNCTION
P10DIR.x
P10SEL.x
INCHx
LCDS0
P10.7/S2/A14
7
P10.7 (I/O) (see Note 1)
I: 0; O: 1
0
1
0
1
X
14
X
0
0
1
1
A14 (MSP430x461x only, see Notes 1, 3)
S2 enabled (see Note 1)
X
X
X
S2 disabled (see Note 1)
X
NOTES: 1. X: Don’t care.
2. N/A: Not available or not applicable.
3. Setting the P10SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
86
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output
TDO
Controlled by JTAG
Controlled by JTAG
TDO/TDI
JTAG
Controlled
by JTAG
DV
CC
TDI
Burn and Test
Fuse
TDI/TCLK
CC
Test
and
DV
TMS
TCK
Emulation
Module
TMS
DV
CC
TCK
RST/NMI
Tau ~ 50 ns
D
U
S
Brownout
G
D
U
S
TCK
G
87
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MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current (I
) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be
(TF)
taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see
Figure 26). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition). The JTAG pins are terminated internally and therefore do not require external termination.
Time TMS Goes Low After POR
TMS
I
(TF)
I
TDI/TCLK
Figure 26. Fuse Check Mode Current
88
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MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
Data Sheet Revision History
Literature
Number
Summary
SLAS675
Production Data data sheet release
NOTE: Page and figure numbers refer to the respective document revision.
89
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
5-Oct-2009
PACKAGING INFORMATION
Orderable Device
MSP430F46161IPZR
MSP430F4616IPZR
MSP430F46171IPZR
MSP430F4617IPZR
MSP430F46181IPZR
MSP430F4618IPZR
MSP430F46191IPZR
MSP430F4619IPZR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PREVIEW
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
LQFP
PZ
100
100
100
100
100
100
100
100
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
PZ
PZ
PZ
PZ
PZ
PZ
PZ
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
M
0,08
51
50
76
26
100
0,13 NOM
1
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
0,25
16,20
SQ
0,05 MIN
0°–7°
15,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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