MSP430F5309IZXH_技术文档

MSP430F530x, MSP430F5310

www.ti.com

SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

MIXED SIGNAL MICROCONTROLLER

1

FEATURES

•

Low Supply-Voltage Range, 1.8 V to 3.6 V

•

Unified Clock System

•

Ultra-Low Power Consumption

–

FLL Control Loop for Frequency

Stabilization

–

Active Mode (AM)

All System Clocks Active

Low-Power/Low-Frequency Internal Clock

Source (VLO)

–

195 µA/MHz at 8 MHz, 3 V, Flash

Program Execution (Typical)

Low-Frequency Trimmed Internal Reference

Source (REFO)

115 µA/MHz at 8 MHz, 3 V, RAM Program

Execution (Typical)

–

32-kHz Watch Crystals (XT1)

–

Standby Mode (LPM3)

High-Frequency Crystals up to 32 MHz

(XT2)

–

Real-Time Clock With Crystal,

Watchdog, and Supply Supervisor

Operational, Full RAM Retention, Fast

Wake-Up:

•

16-Bit Timer TA0, Timer_A With Five

Capture/Compare Registers

16-Bit Timer TA1, Timer_A With Three

Capture/Compare Registers

1.9 µA at 2.2 V, 2.1 µA at 3 V (Typical)

–

Low-Power Oscillator (VLO),

16-Bit Timer TA2, Timer_A With Three

Capture/Compare Registers

General-Purpose Counter, Watchdog,

and Supply Supervisor Operational, Full

RAM Retention, Fast Wake-Up:

1.4 µA at 3 V (Typical)

16-Bit Timer TB0, Timer_B With Seven

Capture/Compare Shadow Registers

Two Universal Serial Communication

Interfaces

–

Off Mode (LPM4)

Full RAM Retention, Supply Supervisor

Operational, Fast Wake-Up:

1.1 µA at 3 V (Typical)

–

USCI_A0 and USCI_A1 Each Supporting

–

Enhanced UART Supporting

Auto-Baudrate Detection

Shutdown Mode (LPM4.5)

0.18 µA at 3 V (Typical)

–

IrDA Encoder and Decoder

Synchronous SPI

•

Wake-Up From Standby Mode in Less Than

5 µs

USCI_B0 and USCI_B1 Each Supporting

16-Bit RISC Architecture, Extended Memory,

Up to 25-MHz System Clock

–

I²C^TM

Synchronous SPI

Flexible Power Management System

•

Integrated 3.3-V Power System

–

Fully Integrated LDO With Programmable

Regulated Core Supply Voltage

10-Bit Analog-to-Digital (A/D) Converter With

Window Comparator

–

Supply Voltage Supervision, Monitoring,

and Brownout

•

Comparator

Hardware Multiplier Supporting 32-Bit

Operations

•

Serial Onboard Programming, No External

Programming Voltage Needed

•

Three Channel Internal DMA

Basic Timer With Real-Time Clock Feature

Family Members are summarized in

For Complete Module Descriptions, See the

MSP430x5xx/MSP430x6xx Family User's Guide

(SLAU208)

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

MSP430F530x, MSP430F5310

SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

www.ti.com

DESCRIPTION

The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low-power

modes is optimized to achieve extended battery life in portable measurement applications. The device features a

powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.

The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 5 µs.

The MSP430F5310, MSP430F5309, and MSP430F5308 devices are microcontroller configurations with 3.3-V

LDO, four 16-bit timers, a high-performance 10-bit analog-to-digital converter (ADC), two universal serial

communication interfaces (USCI), hardware multiplier, DMA, real-time clock module with alarm capabilities and

31 or 47 I/O pins.

The MSP430F5304 device is a configuration 3.3-V LDO, four 16-bit timers, a high-performance 10-bit

analog-to-digital converter (ADC), two universal serial communication interfaces (USCI), hardware multiplier,

DMA, real-time clock module with alarm capabilities, and 31 I/O pins.

Typical applications for this device include analog and digital sensor systems, digital motor control, remote

controls, thermostats, digital timers, hand-held meters, etc.

Table 1. Family Members

USCI

PROGRAM

MEMORY

(KB)

SRAM

(KB)

ADC10_A

(CH)

Comp_B

(CH)

PACKAGE

TYPE

(1)

(2)

CHANNEL A: CHANNEL B:

UART/LIN/

DEVICE

Timer_A

5, 3, 3

Timer_B

I/O

SPI/I²C

IrDA/SPI

64 RGC,

80 ZQE

10 ext / 2 int

6 ext / 2 int

10 ext / 2 int

6 ext / 2 int

10 ext / 2 int

6 ext / 2 int

8

4

8

4

8

4

-

47

31

47

31

47

31

MSP430F5310

MSP430F5309

32

24

6

7

2

48 PT,

48 RGZ

64 RGC,

80 ZQE

5, 3, 3

48 PT,

48 RGZ,

64 RGC,

80 ZQE

MSP430F5308

MSP430F5304

16

8

6

5, 3, 3

7

2

1

2

1

48 PT,

48 RGZ,

48 PT,

48 RGZ

(1) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM

output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first

instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

(2) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM

output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first

instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

(1)

Table 2. Ordering Information

(2)

PACKAGED DEVICES

T_A

PLASTIC 64-PIN VQFN

(RGC)

PLASTIC 80-BALL BGA

(ZQE)

PLASTIC 48-PIN VQFN

(RGZ)

PLASTIC 48-PIN LQFP

(PT)

MSP430F5310IRGC

MSP430F5309IRGC

MSP430F5308IRGC

MSP430F5310IZQE

MSP430F5309IZQE

MSP430F5308IZQE

MSP430F5310IRGZ

MSP430F5309IRGZ

MSP430F5308IRGZ

MSP430F5304IRGZ

MSP430F5310IPT

MSP430F5309IPT

MSP430F5308IPT

MSP430F5304IPT

–40°C to 85°C

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/package.

2

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SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

Functional Block Diagram – MSP430F5310IRGC, MSP430F5309IRGC, MSP430F5308IRG,

MSP430F5310IZQE, MSP430F5309IZQE, MSP430F5308IZQE

PA

PB

PC

AV_CCAV_SS

XIN XOUT

DV_CCDV_SSV_CORE

RST/NMI

P1.x P2.x P3.x P4.x P5.x P6.x

XT2IN

SYS

REF

COMP_B

ADC10_A

ACLK

Power

Management

I/O Ports

P1/P2

2×8 I/Os

Interrupt

& Wakeup

I/O Ports

P3/P4

1×5 I/Os

1×8 I/Os

I/O Ports

P5/P6

1×6 I/Os

1×8 I/Os

Unified

Clock

System

32KB

24KB

16KB

Watchdog

10 Bit

200 KSPS

6KB

XT2OUT

SMCLK

Port Map

Control

(P4)

LDO

SVM/SVS

Brownout

12 Channels

(10 ext/ 2int)

Window

RAM

Flash

MCLK

PA

1×16 I/Os

PB

1×13 I/Os

PC

1×14 I/Os

Comparator

MAB

MDB

CPUXV2

and

Working

Registers

DMA

3 Channel

EEM

(S:3+1)

USCI0,1

PU Port

LDO

TA0

TA1

TA2

TB0

JTAG/

SBW

Interface

Ax: UART,

IrDA, SPI

RTC_A

MPY32

CRC16

Timer_A

5 CC

Registers

Timer_A

3 CC

Registers

Timer_A

3 CC

Registers

Timer_B

7 CC

Registers

Bx: SPI, I2C

PU.0, PU.1

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MSP430F530x, MSP430F5310

SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

www.ti.com

Pin Designation – MSP430F5310IRGC, MSP430F5309IRGC, MSP430F5308IRGC

RGC PACKAGE

(TOP VIEW)

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

P4.7/PM_NONE

P4.6/PM_NONE

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P6.0/CB0/A0

P6.1/CB1/A1

P6.2/CB2/A2

P6.3/CB3/A3

P6.4/CB4/A4

P6.5/CB5/A5

P6.6/CB6/A6

P6.7/CB7/A7

P5.0/A8/VeREF+

P5.1/A9/VeREF−

AV_CC1

2

3

P4.5/PM_UCA1RXD/PM_UCA1SOMI

P4.4/PM_UCA1TXD/PM_UCA1SIMO

P4.3/PM_UCB1CLK/PM_UCA1STE

P4.2/PM_UCB1SOMI/PM_UCB1SCL

P4.1/PM_UCB1SIMO/PM_UCB1SDA

P4.0/PM_UCB1STE/PM_UCA1CLK

DV_CC2

4

5

6

7

MSP430F530xIRGC

MSP430F5310IRGC

8

9

DV_SS2

10

11

12

13

14

15

16

P3.4/UCA0RXD/UCA0SOMI

P3.3/UCA0TXD/UCA0SIMO

P3.2/UCB0CLK/UCA0STE

P3.1/UCB0SOMI/UCB0SCL

P3.0/UCB0SIMO/UCB0SDA

P2.7/UCB0STE/UCA0CLK

P5.4/XIN

P5.5/XOUT

AV_SS1

DV_CC1

DV_SS1

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Note: Power Pad connection to

V_ssrecommended

A0.3

A0.4

A1.0

A1.2

A1.1

P1.4/T

P1.5/T

P1.7/T

P2.1/T

P2.0/T

A1CLK/CBOUT

A2CLK/SMCLK

P1.6/T

P2.2/T

4

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SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

Pin Designation – MSP430F5310IZQE, MSP430F5309IZQE, MSP430F5308IZQE

ZQE PACKAGE

(TOP VIEW)

A1

B1

C1

D1

E1

F1

G1

H1

J1

A2

B2

C2

D2

E2

F2

G2

H2

J2

A3

B3

A4

B4

C4

D4

E4

F4

G4

H4

J4

A5

B5

C5

D5

E5

F5

G5

H5

J5

A6

B6

C6

D6

E6

F6

G6

H6

J6

A7

B7

C7

D7

E7

F7

G7

H7

J7

A8

B8

C8

D8

E8

F8

G8

H8

J8

A9

B9

C9

D9

E9

F9

G9

H9

J9

D3

E3

F3

G3

H3

J3

Functional Block Diagram – MSP430F5310IRGZ, MSP430F5309IRGZ, MSP430F5308IRGZ,

MSP430F5310IPT, MSP430F5309IPT, MSP430F5308IPT

PA

PB

PC

AV_CCAV_SS

XIN XOUT

DV_CCDV_SSV_CORE

RST/NMI

P1.x P2.x P3.x P4.x P5.x P6.x

XT2IN

SYS

REF

COMP_B

ADC10_A

ACLK

Power

Management

I/O Ports

P1/P2

I/O Ports

P4

1×8 I/Os

I/O Ports

P5/P6

1×6 I/Os

1×4 I/Os

Unified

Clock

System

32KB

24KB

16KB

Watchdog

10 Bit

200 KSPS

6KB

XT2OUT

1×8 I/Os

1×1 I/Os

Interrupt

& Wakeup

PA

SMCLK

Port Map

Control

(P4)

LDO

SVM/SVS

Brownout

8 Channels

(6 ext/ 2 int)

Window

RAM

Flash

MCLK

PB

1×8 I/Os

PC

1×10 I/Os

1×9 I/Os

Comparator

MAB

MDB

CPUXV2

and

Working

Registers

DMA

3 Channel

EEM

(S:3+1)

USCI0,1

PU Port

LDO

TA0

TA1

TA2

TB0

JTAG/

SBW

Interface

Ax: UART,

IrDA, SPI

RTC_A

MPY32

CRC16

Timer_A

5 CC

Registers

Timer_A

3 CC

Registers

Timer_A

3 CC

Registers

Timer_B

7 CC

Registers

Bx: SPI, I2C

PU.0, PU.1

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MSP430F530x, MSP430F5310

SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

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Pin Designation – MSP430F5310IRGZ, MSP430F5309IRGZ, MSP430F5308IRGZ,

MSP430F5310IPT, MSP430F5309IPT, MSP430F5308IPT

RGZ & PT PACKAGE

(TOP VIEW)

48 47 46 45 44 43 42 41 40 39 38 37

1

36

35

34

33

32

31

30

29

28

27

26

25

P4.7/PM_NONE

P4.6/PM_NONE

P6.0/CB0/A0

P6.1/CB1/A1

P6.2/CB2/A2

P6.3/CB3/A3

P5.0/A8/VeREF+

P5.1/A9/VeREF-

AVCC1

2

3

4

P4.5/PM_UCA1RXD/PM_UCA1SOMI

P4.4/PM_UCA1TXD/PM_UCA1SIMO

P4.3/PM_UCB1CLK/PM_UCA1STE

P4.2/PM_UCB1SOMI/PM_UCB1SCL

P4.1/PM_UCB1SIMO/PM_UCB1SDA

P4.0/PM_UCB1STE/PM_UCA1CLK

DVCC2

5

6

MSP430F530x

MSP430F5310

7

8

P5.4/XIN

9

P5.5/XOUT

AVSS1

10

11

12

DVSS2

DVCC1

PJ.3/TCK

DVSS1

PJ.2/TMS

13 14 15 16 17 18 19 20 21 22 23 24

Note: for RGZ package Power Pad

connection to V_ssrecommended

6

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SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

Functional Block Diagram – MSP430F5304IRGZ, MSP430F5304IPT

PA

PB

PC

AV_CCAV_SS

XIN XOUT

DV_CCDV_SSV_CORE

RST/NMI

P1.x P2.x P3.x P4.x P5.x P6.x

XT2IN

SYS

REF

ADC10_A

ACLK

Power

Management

I/O Ports

P1/P2

I/O Ports

P4

1×8 I/Os

I/O Ports

P5/P6

1×6 I/Os

1×4 I/Os

Unified

Clock

System

Watchdog

10 Bit

200 KSPS

6KB

8KB

XT2OUT

1×8 I/Os

1×1 I/Os

Interrupt

& Wakeup

PA

SMCLK

Port Map

Control

(P4)

Flash

LDO

SVM/SVS

Brownout

8 Channels

(6 int/ 2 ext)

Window

RAM

MCLK

PB

1×8 I/Os

PC

1×10 I/Os

1×9 I/Os

Comparator

MAB

MDB

CPUXV2

and

Working

Registers

DMA

3 Channel

EEM

(S:3+1)

USCI0

PU Port

LDO

TA0

TA1

TA2

TB0

JTAG/

SBW

Interface

Ax: UART,

IrDA, SPI

RTC_A

MPY32

CRC16

Timer_A

5 CC

Registers

Timer_A

3 CC

Registers

Timer_A

3 CC

Registers

Timer_B

7 CC

Registers

Bx: SPI, I2C

PU.0, PU.1

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MSP430F530x, MSP430F5310

SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

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Pin Designation – MSP430F5304IRGZ, MSP430F5304IPT

RGZ & PT PACKAGE

(TOP VIEW)

48 47 46 45 44 43 42 41 40 39 38 37

1

36

P4.7/PM_NONE

P4.6/PM_NONE

P6.0/A0

P6.1/A1

2

35

34

33

32

31

30

29

28

27

26

25

3

4

P6.2/A2

P4.5/PM_UCA1RXD/PM_UCA1SOMI

P4.4/PM_UCA1TXD/PM_UCA1SIMO

P4.3/PM_UCB1CLK/PM_UCA1STE

P4.2/PM_UCB1SOMI/PM_UCB1SCL

P4.1/PM_UCB1SIMO/PM_UCB1SDA

P4.0/PM_UCB1STE/PM_UCA1CLK

DVCC2

P6.3/A3

5

P5.0/A8/VeREF+

P5.1/A9/VeREF-

AVCC1

6

MSP430F5304

7

8

P5.4/XIN

9

P5.5/XOUT

AVSS1

10

11

12

DVSS2

DVCC1

PJ.3/TCK

DVSS1

PJ.2/TMS

13 14 15 16 17 18 19 20 21 22 23 24

Note: for RGZ package Power Pad

connection to V_ssrecommended

8

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Table 3. Terminal Functions

TERMINAL

NO.

I/O

DESCRIPTION

(1)

NAME

RGZ

/PT

RGC

ZQE

General-purpose digital I/O

P6.4/CB4/A4

P6.5/CB5/A5

P6.6/CB6/A6

P6.7/CB7/A7

5

N/A

5

C1

D2

D1

D3

E1

E2

I/O Comparator_B input CB4 (not available on RGZ or PT package devices)

Analog input A4 – ADC (not available on RGZ or PT package devices)

General-purpose digital I/O

I/O Comparator_B input CB5 (not available on RGZ or PT package devices)

Analog input A5 – ADC (not available on RGZ or PT package devices)

6

7

General-purpose digital I/O

I/O Comparator_B input CB6 (not available on RGZ or PT package devices)

Analog input A6 – ADC (not available on RGZ or PT package devices)

General-purpose digital I/O

I/O Comparator_B input CB7 (not available on RGZ or PT package devices)

Analog input A7 – ADC (not available on RGZ or PT package devices)

8

General-purpose digital I/O

I/O Analog input A8 – ADC

P5.0/A8/VeREF+

P5.1/A9/VeREF-

9

Input for an external reference voltage to the ADC

General-purpose digital I/O

I/O Analog input A9 – ADC

10

6

Negative terminal for an externally provided ADC reference

AVCC1

11

12

7

8

F2

F1

Analog power supply

General-purpose digital I/O

I/O

P5.4/XIN

Input terminal for crystal oscillator XT1

General-purpose digital I/O

I/O

P5.5/XOUT

13

9

G1

Output terminal of crystal oscillator XT1

AVSS1

DVCC1

DVSS1

14

15

16

10

11

12

G2

H1

J1

Analog ground supply

Digital power supply

Digital ground supply

Regulated core power supply output (internal use only, no external current

loading)

(2)

VCORE

17

18

13

14

J2

General-purpose digital I/O with port interrupt

TA0 clock signal TA0CLK input ; ACLK output (divided by 1, 2, 4, or 8)

P1.0/TA0CLK/ACLK

P1.1/TA0.0

H2

I/O

General-purpose digital I/O with port interrupt

I/O TA0 CCR0 capture: CCI0A input, compare: Out0 output

BSL transmit output

19

20

15

16

H3

J3

General-purpose digital I/O with port interrupt

I/O TA0 CCR1 capture: CCI1A input, compare: Out1 output

BSL receive input

P1.2/TA0.1

General-purpose digital I/O with port interrupt

TA0 CCR2 capture: CCI2A input, compare: Out2 output

P1.3/TA0.2

P1.4/TA0.3

P1.5/TA0.4

21

22

23

17

18

19

G4

H4

J4

I/O

General-purpose digital I/O with port interrupt

TA0 CCR3 capture: CCI3A input compare: Out3 output

I/O

General-purpose digital I/O with port interrupt

TA0 CCR4 capture: CCI4A input, compare: Out4 output

I/O

General-purpose digital I/O with port interrupt

I/O TA1 clock signal TA1CLK input

Comparator_B output

P1.6/TA1CLK/CBOUT

24

20

G5

General-purpose digital I/O with port interrupt

TA1 CCR0 capture: CCI0A input, compare: Out0 output

P1.7/TA1.0

P2.0/TA1.1

P2.1/TA1.2

25

26

27

21

22

H5

J5

I/O

General-purpose digital I/O with port interrupt

TA1 CCR1 capture: CCI1A input, compare: Out1 output

I/O

General-purpose digital I/O with port interrupt

TA1 CCR2 capture: CCI2A input, compare: Out2 output

N/A

G6

I/O

(1) I = input, O = output, N/A = not available

(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended

capacitor value, C_VCORE

.

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MSP430F530x, MSP430F5310

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Table 3. Terminal Functions (continued)

TERMINAL

NO.

I/O

DESCRIPTION

(1)

NAME

RGZ

/PT

RGC

28

ZQE

J6

General-purpose digital I/O with port interrupt

TA2 clock signal TA2CLK input ; SMCLK output

P2.2/TA2CLK/SMCLK

P2.3/TA2.0

N/A

I/O

General-purpose digital I/O with port interrupt

TA2 CCR0 capture: CCI0A input, compare: Out0 output

29

H6

J7

General-purpose digital I/O with port interrupt

TA2 CCR1 capture: CCI1A input, compare: Out1 output

P2.4/TA2.1

30

General-purpose digital I/O with port interrupt

TA2 CCR2 capture: CCI2A input, compare: Out2 output

P2.5/TA2.2

31

J8

General-purpose digital I/O with port interrupt

P2.6/RTCCLK/DMAE0

32

33

N/A

J9

I/O RTC clock output for calibration

DMA external trigger input

General-purpose digital I/O

Slave transmit enable – USCI_B0 SPI mode

Clock signal input – USCI_A0 SPI slave mode

P2.7/UCB0STE/UCA0CLK

H7

I/O

Clock signal output – USCI_A0 SPI master mode

General-purpose digital I/O

P3.0/UCB0SIMO/UCB0SDA

P3.1/UCB0SOMI/UCB0SCL

34

35

N/A

H8

H9

I/O Slave in, master out – USCI_B0 SPI mode

I2C data – USCI_B0 I2C mode

General-purpose digital I/O

I/O Slave out, master in – USCI_B0 SPI mode

I2C clock – USCI_B0 I2C mode

General-purpose digital I/O

Clock signal input – USCI_B0 SPI slave mode

Clock signal output – USCI_B0 SPI master mode

P3.2/UCB0CLK/UCA0STE

36

N/A

G8

I/O

Slave transmit enable – USCI_A0 SPI mode

General-purpose digital I/O

P3.3/UCA0TXD/UCA0SIMO

P3.4/UCA0RXD/UCA0SOMI

37

38

N/A

G9

G7

I/O Transmit data – USCI_A0 UART mode

Slave in, master out – USCI_A0 SPI mode

General-purpose digital I/O

I/O Receive data – USCI_A0 UART mode

Slave out, master in – USCI_A0 SPI mode

General-purpose digital I/O with reconfigurable port mapping secondary

function

I/O Default mapping: Slave transmit enable – USCI_B1 SPI mode

Default mapping: Clock signal input – USCI_A1 SPI slave mode

Default mapping: Clock signal output – USCI_A1 SPI master mode

P4.0/PM_UCB1STE/

PM_UCA1CLK

41

29

E8

General-purpose digital I/O with reconfigurable port mapping secondary

P4.1/PM_UCB1SIMO/

PM_UCB1SDA

function

42

43

30

31

E7

D9

I/O

Default mapping: Slave in, master out – USCI_B1 SPI mode

Default mapping: I2C data – USCI_B1 I2C mode

General-purpose digital I/O with reconfigurable port mapping secondary

function

Default mapping: Slave out, master in – USCI_B1 SPI mode

P4.2/PM_UCB1SOMI/

PM_UCB1SCL

I/O

Default mapping: I2C clock – USCI_B1 I2C mode

General-purpose digital I/O with reconfigurable port mapping secondary

function

I/O Default mapping: Clock signal input – USCI_B1 SPI slave mode

Default mapping: Clock signal output – USCI_B1 SPI master mode

Default mapping: Slave transmit enable – USCI_A1 SPI mode

P4.3/PM_UCB1CLK/

PM_UCA1STE

44

32

D8

DVSS2

DVCC2

39

40

27

28

F9

E9

Digital ground supply

Digital power supply

General-purpose digital I/O with reconfigurable port mapping secondary

P4.4/PM_UCA1TXD/

PM_UCA1SIMO

function

45

33

D7

I/O

Default mapping: Transmit data – USCI_A1 UART mode

Default mapping: Slave in, master out – USCI_A1 SPI mode

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Table 3. Terminal Functions (continued)

TERMINAL

NO.

I/O

DESCRIPTION

(1)

NAME

RGZ

/PT

RGC

ZQE

General-purpose digital I/O with reconfigurable port mapping secondary

function

Default mapping: Receive data – USCI_A1 UART mode

Default mapping: Slave out, master in – USCI_A1 SPI mode

P4.5/PM_UCA1RXD/

PM_UCA1SOMI

46

34

35

C9

I/O

General-purpose digital I/O with reconfigurable port mapping secondary

I/O function

Default mapping: no secondary function.

P4.6/PM_NONE

47

C8

C7

General-purpose digital I/O with reconfigurable port mapping secondary

I/O function

P4.7/PM_NONE

VSSU

48

49

36

37

Default mapping: no secondary function.

B8,

B9

PU ground supply

PU.0

NC

50

51

52

53

54

55

56

38

39

40

41

42

43

44

A9

B7

A8

A7

A6

B6

A5

I/O General-purpose digital I/O - controlled by PU control register

I/O No connect.

PU.1

LDOI

LDOO

NC

I/O General-purpose digital I/O - controlled by PU control register

LDO input

LDO output

No connect.

AVSS2

Analog ground supply

General-purpose digital I/O

I/O

P5.2/XT2IN

P5.3/XT2OUT

TEST/SBWTCK

PJ.0/TDO

57

58

59

60

61

62

63

45

46

47

23

24

25

26

B5

B4

A4

C5

C4

A3

B3

Input terminal for crystal oscillator XT2

General-purpose digital I/O

I/O

Output terminal of crystal oscillator XT2

Test mode pin – select digital I/O on JTAG pins

Spy-bi-wire input clock

I

General-purpose digital I/O

I/O

Test data output port

General-purpose digital I/O

I/O

PJ.1/TDI/TCLK

PJ.2/TMS

Test data input or test clock input

General-purpose digital I/O

Test mode select

I/O

General-purpose digital I/O

Test clock

PJ.3/TCK

I/O

Reset input active low

I/O Non-maskable interrupt input

Spy-bi-wire data input/output

RST/NMI/SBWTDIO

P6.0/CB0/A0

64

1

48

1

A2

A1

B2

B1

General-purpose digital I/O

I/O Comparator_B input CB0 (not available on '5304 device)

Analog input A0 – ADC

General-purpose digital I/O

I/O Comparator_B input CB1 (not available on '5304 device)

Analog input A1 – ADC

P6.1/CB1/A1

2

General-purpose digital I/O

I/O Comparator_B input CB2 (not available on '5304 device)

Analog input A2 – ADC

P6.2/CB2/A2

3

General-purpose digital I/O

P6.3/CB3/A3

4

C2

I/O Comparator_B input CB3 (not available on '5304 device)

Analog input A3 – ADC

(3)

Reserved

QFN Pad

N/A N/A

QFN package pad. Connection to V_SSrecommended (not available on PT

package devices)

Pad Pad N/A

(3) C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground.

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SHORT-FORM DESCRIPTION

CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,

other than program-flow instructions, are performed as register operations in conjunction with seven addressing

modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register

operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant

generator, respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all

instructions.

The instruction set consists of the original 51 instructions with three formats and seven address modes and

additional instructions for the expanded address range. Each instruction can operate on word and byte data.

Program Counter

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R4

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15

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Operating Modes

The MSP430 has one active mode and six software selectable low-power modes of operation. An interrupt event

can wake up the device from any of the low-power modes, service the request, and restore back to the

low-power mode on return from the interrupt program.

The following seven operating modes can be configured by software:

•

Active mode (AM)

All clocks are active

Low-power mode 0 (LPM0)

–

•

–

CPU is disabled

ACLK and SMCLK remain active, MCLK is disabled

FLL loop control remains active

•

Low-power mode 1 (LPM1)

–

CPU is disabled

FLL loop control is disabled

ACLK and SMCLK remain active, MCLK is disabled

Low-power mode 2 (LPM2)

–

CPU is disabled

MCLK and FLL loop control and DCOCLK are disabled

DCO's dc-generator remains enabled

ACLK remains active

•

Low-power mode 3 (LPM3)

–

CPU is disabled

MCLK, FLL loop control, and DCOCLK are disabled

DCO's dc generator is disabled

ACLK remains active

Low-power mode 4 (LPM4)

–

CPU is disabled

ACLK is disabled

MCLK, FLL loop control, and DCOCLK are disabled

DCO's dc generator is disabled

Crystal oscillator is stopped

Complete data retention

•

Low-power mode 4.5 (LPM4.5)

–

Internal regulator disabled

No data retention

Wakeup from RST/NMI, P1, and P2.

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Interrupt Vector Addresses

The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The

vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 4. Interrupt Sources, Flags, and Vectors

SYSTEM

INTERRUPT

WORD

ADDRESS

INTERRUPT SOURCE

INTERRUPT FLAG

PRIORITY

System Reset

Power-Up

External Reset

Watchdog Timeout, Password

Violation

(1) (2)

WDTIFG, KEYV (SYSRSTIV)

Reset

0FFFEh

63, highest

Flash Memory Password Violation

System NMI

PMM

Vacant Memory Access

JTAG Mailbox

SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,

VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,

(Non)maskable

0FFFCh

0FFFAh

62

61

(1)

JMBOUTIFG (SYSSNIV)

User NMI

NMI

Oscillator Fault

NMIIFG, OFIFG, ACCVIFG, BUSIFG (SYSUNIV)

(1) (2)

Flash Memory Access Violation

(1) (3)

Comp_B

TB0

Comparator B interrupt flags (CBIV)

Maskable

0FFF8h

0FFF6h

60

59

(3)

TB0CCR0 CCIFG0

TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,

TB0

Maskable

0FFF4h

0FFF2h

58

57

(1) (3)

TB0IFG (TB0IV)

Watchdog Timer_A Interval Timer

Mode

WDTIFG

(1) (3)

USCI_A0 Receive/Transmit

USCI_B0 Receive/Transmit

ADC10_A

UCA0RXIFG, UCA0TXIFG (UCA0IV)

Maskable

0FFF0h

0FFEEh

0FFECh

0FFEAh

56

55

54

53

(1) (3)

UCB0RXIFG, UCB0TXIFG (UCAB0IV)

(1) (3) (4)

ADC10IFG0

(3)

TA0

TA0CCR0 CCIFG0

TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,

TA0

Maskable

0FFE8h

52

(1) (3)

TA0IFG (TA0IV)

LDO-PWR

DMA

LDOOFFIG, LDOONIFG, LDOOVLIFG

Maskable

0FFE6h

0FFE4h

0FFE2h

51

50

49

(1) (3)

DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)

(3)

TA1

TA1CCR0 CCIFG0

TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,

TA1

Maskable

0FFE0h

48

(1) (3)

TA1IFG (TA1IV)

(1) (3)

I/O Port P1

USCI_A1 Receive/Transmit

USCI_B1 Receive/Transmit

TA2

P1IFG.0 to P1IFG.7 (P1IV)

Maskable

0FFDEh

0FFDCh

0FFDAh

0FFD8h

47

46

45

44

(1) (3)

UCA1RXIFG, UCA1TXIFG (UCA1IV)

(1) (3)

UCB1RXIFG, UCB1TXIFG (UCB1IV)

(3)

TA2CCR0 CCIFG0

TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,

TA2

Maskable

0FFD6h

0FFD4h

0FFD2h

43

42

41

(1) (3)

TA2IFG (TA2IV)

(1) (3)

I/O Port P2

RTC_A

P2IFG.0 to P2IFG.7 (P2IV)

RTCRDYIFG, RTCTEVIFG, RTCAIFG,

(1) (3)

RT0PSIFG, RT1PSIFG (RTCIV)

0FFD0h

⋮

40

(5)

Reserved

⋮

0FF80h

0, lowest

(1) Multiple source flags

(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.

(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

(3) Interrupt flags are located in the module.

(4) Only on devices with ADC, otherwise reserved.

(5) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain

compatibility with other devices, it is recommended to reserve these locations.

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Memory Organization

(1)

Table 5. Memory Organization

MSP430F5304

MSP430F5308

MSP430F5309

MSP430F5310

Memory (flash)

Total Size

8 KB

16 KB

24 KB

32 KB

Main: interrupt vector

Main: code memory

00FFFFh–00FF80h

00FFFFh-00E000h

00FFFFh–00FF80h

00FFFFh-00C000h

00FFFFh–00FF80h

00FFFFh-00A000h

00FFFFh–00FF80h

00FFFFh-008000h

Sector 1

Sector 0

Sector 7

Info A

2 KB

0033FFh–002C00h

2 KB

0033FFh–002C00h

2 KB

0033FFh–002C00h

2 KB

0033FFh–002C00h

2 KB

002BFFh–002400h

2 KB

002BFFh–002400h

2 KB

002BFFh–002400h

2 KB

002BFFh–002400h

RAM

2 KB

0023FFh–001C00h

2 KB

0023FFh–001C00h

2 KB

0023FFh–001C00h

2 KB

0023FFh–001C00h

128 B

0019FFh–001980h

Info B

128 B

00197Fh–001900h

Information memory

(flash)

Info C

Info D

BSL 3

BSL 2

BSL 1

BSL 0

Size

128 B

0018FFh–001880h

128 B

0018FFh–001880h

128 B

0018FFh–001880h

128 B

0018FFh–001880h

128 B

00187Fh–001800h

128 B

00187Fh–001800h

128 B

00187Fh–001800h

128 B

00187Fh–001800h

512 B

0017FFh–001600h

512 B

0017FFh–001600h

512 B

0017FFh–001600h

512 B

0017FFh–001600h

512 B

0015FFh–001400h

512 B

0015FFh–001400h

512 B

0015FFh–001400h

512 B

0015FFh–001400h

Bootstrap loader (BSL)

memory (flash)

512 B

0013FFh–001200h

512 B

0013FFh–001200h

512 B

0013FFh–001200h

512 B

0013FFh–001200h

512 B

0011FFh–001000h

512 B

0011FFh–001000h

512 B

0011FFh–001000h

512 B

0011FFh–001000h

4 KB

000FFFh–0h

4 KB

000FFFh–0h

4 KB

000FFFh–0h

4 KB

000FFFh–0h

Peripherals

(1) N/A = Not available

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Bootstrap Loader (BSL)

The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the

device memory via the BSL is protected by user-defined password. Usage of the UART BSL requires external

access to the six pins shown in Table 6.For complete description of the features of the BSL and its

implementation, see MSP430 Programming Via the Bootstrap Loader, literature number SLAU319.

Table 6. BSL Functions

DEVICE SIGNAL

BSL FUNCTION

Entry sequence signal

Data transmit

RST/NMI/SBWTDIO

TEST/SBWTCK

P1.1

P1.2

VCC

VSS

Data receive

Power supply

Ground supply

JTAG Operation

JTAG Standard Interface

The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving

data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the

JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430

development tools and device programmers. The JTAG pin requirements are shown in Table 7. For further

details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's

Guide, literature number SLAU278.

Table 7. JTAG Pin Requirements and Functions

DEVICE SIGNAL

PJ.3/TCK

DIRECTION

FUNCTION

JTAG clock input

JTAG state control

JTAG data input/TCLK input

JTAG data output

Enable JTAG pins

External reset

IN

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

IN

OUT

IN

TEST/SBWTCK

RST/NMI/SBWTDIO

VCC

IN

Power supply

VSS

Ground supply

Spy-Bi-Wire Interface

In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface.

Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire

interface pin requirements are shown in Table 8. For further details on interfacing to development tools and

device programmers, see the MSP430 Hardware Tools User's Guide, literature number SLAU278.

Table 8. Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL

TEST/SBWTCK

RST/NMI/SBWTDIO

VCC

DIRECTION

IN

FUNCTION

Spy-Bi-Wire clock input

Spy-Bi-Wire data input/output

Power supply

IN, OUT

VSS

Ground supply

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Flash Memory

The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the

CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the

flash memory include:

•

Flash memory has n segments of main memory and four segments of information memory (A to D) of

128 bytes each. Each segment in main memory is 512 bytes in size.

•

Segments 0 to n may be erased in one step, or each segment may be individually erased.

Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also

called information memory.

•

Segment A can be locked separately.

RAM Memory

The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,

however all data is lost. Features of the RAM memory include:

•

RAM memory has n sectors. The size of a sector can be found in the Memory Organization section.

Each sector 0 to n can be completely disabled, however data retention is lost.

Each sector 0 to n automatically enters low power retention mode when possible.

Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all

instructions. For complete module descriptions, see the MSP430x5xx/MSP430x6xx Family User's Guide,

literature number SLAU208.

Digital I/O

There are up to six 8-bit I/O ports implemented: For 64 pin options, P1, P2, P4, and P6 are complete, P5 is

reduced to 6-bit I/O, and P3 is reduced to 5-bit I/O. For 48 pin options, P6 is reduced to 4-bit I/O, P2 is reduced

to 1-bit I/O, and P3 is completely removed. Port PJ contains four individual I/O ports, common to all devices.

•

All individual I/O bits are independently programmable.

Any combination of input, output, and interrupt conditions is possible.

Pullup or pulldown on all ports is programmable.

Drive strength on all ports is programmable.

Edge-selectable interrupt and LPM4.5 wakeup input capability is available for all bits of ports P1 and P2.

Read/write access to port-control registers is supported by all instructions.

Ports can be accessed byte-wise (P1 through P6) or word-wise in pairs (PA through PC).

Port Mapping Controller

The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4.

Table 9. Port Mapping, Mnemonics and Functions

Value

PxMAPy Mnemonic

PM_NONE

Input Pin Function

Output Pin Function

DVSS

0

None

PM_CBOUT0

PM_TB0CLK

-

Comparator_B output

1

2

TB0 clock input

PM_ADC10CLK

PM_DMAE0

-

ADC10CLK

SVM output

DMAE0 input

-

PM_SVMOUT

3

TB0 high impedance input

TB0OUTH

PM_TB0OUTH

4

5

6

PM_TB0CCR0A

PM_TB0CCR1A

PM_TB0CCR2A

TB0 CCR0 capture input CCI0A

TB0 CCR1 capture input CCI1A

TB0 CCR2 capture input CCI2A

TB0 CCR0 compare output Out0

TB0 CCR1 compare output Out1

TB0 CCR2 compare output Out2

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Table 9. Port Mapping, Mnemonics and Functions (continued)

Value

PxMAPy Mnemonic

PM_TB0CCR3A

PM_TB0CCR4A

PM_TB0CCR5A

PM_TB0CCR6A

PM_UCA1RXD

PM_UCA1SOMI

PM_UCA1TXD

PM_UCA1SIMO

PM_UCA1CLK

PM_UCB1STE

PM_UCB1SOMI

PM_UCB1SCL

PM_UCB1SIMO

PM_UCB1SDA

PM_UCB1CLK

PM_UCA1STE

PM_CBOUT1

Input Pin Function

Output Pin Function

7

8

TB0 CCR3 capture input CCI3A

TB0 CCR4 capture input CCI4A

TB0 CCR5 capture input CCI5A

TB0 CCR6 capture input CCI6A

TB0 CCR3 compare output Out3

TB0 CCR4 compare output Out4

TB0 CCR5 compare output Out5

TB0 CCR6 compare output Out6

9

10

USCI_A1 UART RXD (Direction controlled by USCI - input)

USCI_A1 SPI slave out master in (direction controlled by USCI)

USCI_A1 UART TXD (Direction controlled by USCI - output)

USCI_A1 SPI slave in master out (direction controlled by USCI)

USCI_A1 clock input/output (direction controlled by USCI)

USCI_B1 SPI slave transmit enable (direction controlled by USCI)

USCI_B1 SPI slave out master in (direction controlled by USCI)

USCI_B1 I2C clock (open drain and direction controlled by USCI)

USCI_B1 SPI slave in master out (direction controlled by USCI)

USCI_B1 I2C data (open drain and direction controlled by USCI)

USCI_B1 clock input/output (direction controlled by USCI)

USCI_A1 SPI slave transmit enable (direction controlled by USCI)

11

12

13

14

15

16

17

18

19

None

Comparator_B output

MCLK

PM_MCLK

PM_RTCCLK

RTCCLK output

PM_UCA0RXD

PM_UCA0SOMI

PM_UCA0TXD

PM_UCA0SIMO

PM_UCA0CLK

PM_UCB0STE

PM_UCB0SOMI

PM_UCB0SCL

PM_UCB0SIMO

PM_UCB0SDA

PM_UCB0CLK

PM_UCA0STE

Reserved

USCI_A0 UART RXD (Direction controlled by USCI - input)

USCI_A0 SPI slave out master in (direction controlled by USCI)

USCI_A0 UART TXD (Direction controlled by USCI - output)

USCI_A0 SPI slave in master out (direction controlled by USCI)

USCI_A0 clock input/output (direction controlled by USCI)

USCI_B0 SPI slave transmit enable (direction controlled by USCI)

USCI_B0 SPI slave out master in (direction controlled by USCI)

USCI_B0 I2C clock (open drain and direction controlled by USCI)

USCI_B0 SPI slave in master out (direction controlled by USCI)

USCI_B0 I2C data (open drain and direction controlled by USCI)

USCI_B0 clock input/output (direction controlled by USCI)

USCI_A0 SPI slave transmit enable (direction controlled by USCI)

20

21

22

23

24

25

26 - 30

None

DVSS

Disables the output driver as well as the input Schmitt-trigger to prevent

parasitic cross currents when applying analog signals.

(1)

31 (0FFh)

PM_ANALOG

(1) The value of the PMPAP_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are

ignored resulting in a read out value of 31.

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Table 10. Default Mapping

PxMAPy Mnemonic

Input Pin Function

Output Pin Function

USCI_B1 SPI slave transmit enable (direction controlled by USCI)

USCI_A1 clock input/output (direction controlled by USCI)

P4.0/P4MAP0

P4.1/P4MAP1

P4.2/P4MAP2

P4.3/P4MAP3

P4.4/P4MAP4

P4.5/P4MAP5

PM_UCB1STE/PM_UCA1CLK

USCI_B1 SPI slave in master out (direction controlled by USCI)

USCI_B1 I2C data (open drain and direction controlled by USCI)

PM_UCB1SIMO/PM_UCB1SDA

PM_UCB1SOMI/PM_UCB1SCL

PM_UCB1CLK/PM_UCA1STE

PM_UCA1TXD/PM_UCA1SIMO

PM_UCA1RXD/PM_UCA1SOMI

USCI_B1 SPI slave out master in (direction controlled by USCI)

USCI_B1 I2C clock (open drain and direction controlled by USCI)

USCI_A1 SPI slave transmit enable (direction controlled by USCI)

USCI_B1 clock input/output (direction controlled by USCI)

USCI_A1 UART TXD (Direction controlled by USCI - output)

USCI_A1 SPI slave in master out (direction controlled by USCI)

USCI_A1 UART RXD (Direction controlled by USCI - input)

USCI_A1 SPI slave out master in (direction controlled by USCI)

P4.6/P4MAP6

P4.7/P4MAP7

PM_NONE

None

DVSS

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Oscillator and System Clock

The clock system in the MSP430F530x family of devices is supported by the Unified Clock System (UCS)

module that includes support for a 32-kHz watch crystal oscillator (XT1 LF mode; XT1 HF mode not supported),

an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO),

an integrated internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator XT2. The UCS

module is designed to meet the requirements of both low system cost and low power consumption. The UCS

module features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator,

stabilizes the DCO frequency to a programmable multiple of the selected FLL reference frequency. The internal

DCO provides a fast turn-on clock source and stabilizes in less than 5 µs. The UCS module provides the

following clock signals:

•

Auxiliary clock (ACLK), sourced from a 32 kHz watch crystal (XT1), a high-frequency crystal (XT2), the

internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally

controlled oscillator (DCO).

•

Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made

available to ACLK.

Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by

same sources made available to ACLK.

ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.

Power Management Module (PMM)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains

programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor

(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is

implemented to provide the proper internal reset signal to the device during power-on and power-off. The

SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply

voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not

automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.

Hardware Multiplier

The multiplication operation is supported by a dedicated peripheral module. The module performs operations with

32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication

as well as signed and unsigned multiply and accumulate operations.

Real-Time Clock (RTC_A)

The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated

real-time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers

that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Calendar

mode integrates an internal calendar which compensates for months with less than 31 days and includes leap

year correction. The RTC_A also supports flexible alarm functions and offset-calibration hardware.

Watchdog Timer (WDT_A)

The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a

software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog

function is not needed in an application, the module can be configured as an interval timer and can generate

interrupts at selected time intervals.

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System Module (SYS)

The SYS module handles many of the system functions within the device. These include power-on reset and

power-up clear handling, NMI source selection and management, reset interrupt vector generators, bootstrap

loader entry mechanisms, as well as configuration management (device descriptors). It also includes a data

exchange mechanism via JTAG called a JTAG mailbox that can be used in the application.

Table 11. System Module Interrupt Vector Registers

INTERRUPT VECTOR REGISTER

SYSRSTIV , System Reset

ADDRESS

INTERRUPT EVENT

No interrupt pending

Brownout (BOR)

RST/NMI (POR)

PMMSWBOR (BOR)

Wakeup from LPMx.5

Security violation (BOR)

SVSL (POR)

VALUE

00h

PRIORITY

019Eh

02h

Highest

04h

06h

08h

0Ah

0Ch

SVSH (POR)

0Eh

SVML_OVP (POR)

SVMH_OVP (POR)

PMMSWPOR (POR)

WDT timeout (PUC)

WDT password violation (PUC)

KEYV flash password violation (PUC)

FLL unlock (PUC)

Peripheral area fetch (PUC)

PMM password violation (PUC)

Reserved

10h

12h

14h

16h

18h

1Ah

1Ch

1Eh

20h

22h to 3Eh

00h

Lowest

Highest

SYSSNIV , System NMI

019Ch

No interrupt pending

SVMLIFG

02h

SVMHIFG

04h

SVSMLDLYIFG

SVSMHDLYIFG

VMAIFG

06h

08h

0Ah

JMBINIFG

0Ch

JMBOUTIFG

0Eh

SVMLVLRIFG

10h

SVMHVLRIFG

12h

Reserved

14h to 1Eh

00h

Lowest

Highest

SYSUNIV, User NMI

019Ah

No interrupt pending

NMIFG

02h

OFIFG

04h

ACCVIFG

06h

Reserved

08h

Reserved

0Ah to 1Eh

Lowest

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DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU intervention. For

example, the DMA controller can be used to move data from the ADC10_A conversion register to RAM. Using

the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system

power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or

from a peripheral.

(1)

Table 12. DMA Trigger Assignments

Channel

Trigger

0

1

2

0

DMAREQ

1

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TA2CCR0 CCIFG

TA2CCR2 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

Reserved

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TA2CCR0 CCIFG

TA2CCR2 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

Reserved

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TA2CCR0 CCIFG

TA2CCR2 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

Reserved

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Reserved

UCA0RXIFG

UCA0TXIFG

UCB0RXIFG

UCB0TXIFG

UCA1RXIFG

UCA1TXIFG

UCB1RXIFG

UCB1TXIFG

UCA0RXIFG

UCA0TXIFG

UCB0RXIFG

UCB0TXIFG

UCA1RXIFG

UCA1TXIFG

UCB1RXIFG

UCB1TXIFG

UCA0RXIFG

UCA0TXIFG

UCB0RXIFG

UCB0TXIFG

UCA1RXIFG

UCA1TXIFG

UCB1RXIFG

UCB1TXIFG

(2)

ADC10IFG0

Reserved

reserved

MPY ready

DMA2IFG

DMAE0

Reserved

reserved

MPY ready

DMA0IFG

DMAE0

Reserved

reserved

MPY ready

DMA1IFG

DMAE0

(1) If a reserved trigger source is selected, no Trigger1 is generated.

(2) Only on devices with ADC. Reserved on devices without ADC.

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Universal Serial Communication Interface (USCI)

The USCI modules are used for serial data communication. The USCI module supports synchronous

communication protocols such as SPI (3 or 4 pin) and I²C, and asynchronous communication protocols such as

UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions,

A and B.

The USCI_An module provides support for SPI (3 pin or 4 pin), UART, enhanced UART, or IrDA.

The USCI_Bn module provides support for SPI (3 pin or 4 pin) or I2C.

The MSP430F53xx series includes one or two complete USCI modules.

TA0

TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. It can support multiple

capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may

be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 13. TA0 Signal Connections

INPUT PIN NUMBER

DEVICE

INPUT

SIGNAL

MODULE

INPUT

SIGNAL

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

OUTPUT PIN NUMBER

RGC/ZQE RGZ, PT

MODULE

BLOCK

RGC/ZQE

RGZ, PT

18/H2-P1.0

14-P1.0

TA0CLK

TACLK

ACLK

(internal)

ACLK

Timer

CCR0

NA

SMCLK

(internal)

SMCLK

18/H2-P1.0

19/H3-P1.1

14-P1.0

15-P1.1

TA0CLK

TA0.0

DV_SS

TACLK

CCI0A

CCI0B

GND

19/H3-P1.1

20/J3-P1.2

15-P1.1

16-P1.2

TA0

TA0.0

DV_SS

DV_CC

V_CC

20/J3-P1.2

16-P1.2

17-P1.3

TA0.1

CCI1A

ADC10 (internal) ADC10 (internal)

(1)

CBOUT

(internal)

CCI1B

ADC10SHSx =

{1}

ADC10SHSx =

{1}

CCR1

CCR2

TA1

TA2

TA0.1

TA0.2

DV_SS

DV_CC

TA0.2

GND

V_CC

21/G4-P1.3

CCI2A

21/G4-P1.3

17-P1.3

ACLK

(internal)

CCI2B

DV_SS

DV_CC

TA0.3

DV_SS

DV_CC

TA0.4

DV_SS

DV_CC

GND

V_CC

22/H4-P1.4

23/J4-P1.5

18-P1.4

19-P1.5

CCI3A

CCI3B

GND

V_CC

22/H4-P1.4

23/J4-P1.5

18-P1.4

19-P1.5

CCR3

CCR4

TA3

TA4

TA0.3

TA0.4

CCI4A

CCI4B

GND

V_CC

(1) Only on devices with ADC.

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TA1

TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple

capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may

be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 14. TA1 Signal Connections

INPUT PIN NUMBER

DEVICE

INPUT

SIGNAL

MODULE

INPUT

SIGNAL

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

OUTPUT PIN NUMBER

MODULE

BLOCK

RGC/ZQE

RGZ, PT

RGC/ZQE

RGZ, PT

24/G5-P1.6

20-P1.6

TA1CLK

TACLK

ACLK

(internal)

ACLK

Timer

NA

SMCLK

(internal)

SMCLK

24/G5-P1.6

25/H5-P1.7

20-P1.6

21-P1.7

TA1CLK

TA1.0

DV_SS

TACLK

CCI0A

CCI0B

GND

25/H5-P1.7

26/J5-P2.0

21-P1.7

22-P2.0

CCR0

CCR1

TA0

TA1

TA1.0

TA1.1

DV_SS

DV_CC

V_CC

26/J5-P2.0

27/G6-P2.1

22-P2.0

TA1.1

CCI1A

CBOUT

(internal)

CCI1B

DV_SS

DV_CC

TA1.2

GND

V_CC

CCI2A

27/G6-P2.1

ACLK

(internal)

CCI2B

CCR2

TA2

TA1.2

DV_SS

DV_CC

GND

V_CC

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TA2

TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple

capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may

be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 15. TA2 Signal Connections

INPUT PIN NUMBER

DEVICE

INPUT

SIGNAL

MODULE

INPUT

SIGNAL

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

OUTPUT PIN NUMBER

MODULE

BLOCK

RGC/ZQE

RGZ, PT

RGC/ZQE

RGZ, PT

28/J6-P2.2

TA2CLK

TACLK

ACLK

(internal)

ACLK

Timer

NA

SMCLK

(internal)

SMCLK

28/J6-P2.2

29/H6-P2.3

TA2CLK

TA2.0

DV_SS

TACLK

CCI0A

CCI0B

GND

29/H6-P2.3

30/J7-P2.4

CCR0

CCR1

TA0

TA1

TA2.0

TA2.1

DV_SS

DV_CC

V_CC

30/J7-P2.4

31/J8-P2.5

TA2.1

CCI1A

CBOUT

(internal)

CCI1B

DV_SS

DV_CC

TA2.2

GND

V_CC

CCI2A

31/J8-P2.5

ACLK

(internal)

CCI2B

CCR2

TA2

TA2.2

DV_SS

DV_CC

GND

V_CC

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TB0

TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. It can support multiple

capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may

be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 16. TB0 Signal Connections

INPUT PIN NUMBER

DEVICE

INPUT

SIGNAL

MODULE

INPUT

SIGNAL

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

OUTPUT PIN NUMBER

MODULE

BLOCK

(1)

RGC/ZQE

RGZ, PT

RGC/ZQE

RGZ, PT

TB0CLK

TBCLK

ACLK

(internal)

ACLK

Timer

CCR0

NA

SMCLK

(internal)

SMCLK

TBCLK

TB0CLK

ADC10 (internal) ADC10 (internal)

(2)

TB0.0

CCI0A

ADC10SHSx =

{2}

ADC10SHSx =

{2}

TB0

TB0.0

DV_SS

DV_CC

CCI0B

GND

V_CC

ADC10 (internal) ADC10 (internal)

TB0.1

CCI1A

ADC10SHSx =

{3}

ADC10SHSx =

{3}

CBOUT

(internal)

CCR1

TB1

TB0.1

CCI1B

DV_SS

DV_CC

TB0.2

DV_SS

DV_CC

TB0.3

DV_SS

DV_CC

TB0.4

DV_SS

DV_CC

TB0.5

DV_SS

DV_CC

TB0.6

GND

V_CC

CCI2A

CCI2B

GND

CCR2

CCR3

CCR4

CCR5

TB2

TB3

TB4

TB5

TB0.2

TB0.3

TB0.4

TB0.5

V_CC

CCI3A

CCI3B

GND

V_CC

CCI4A

CCI4B

GND

V_CC

CCI5A

CCI5B

GND

V_CC

CCI6A

ACLK

(internal)

CCI6B

CCR6

TB6

TB0.6

DV_SS

DV_CC

GND

V_CC

(1) Timer functions selectable via the port mapping controller.

(2) Only on devices with ADC.

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Comparator_B

The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions,

battery voltage supervision, and monitoring of external analog signals.

ADC10_A

The ADC10_A module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR

core, sample select control, reference generator and a conversion result buffer. A window comparator with a

lower and upper limit allows CPU independent result monitoring with three window comparator interrupt flags.

CRC16

The CRC16 module produces a signature based on a sequence of entered data values and can be used for data

checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.

REF Voltage Reference

The reference module (REF) is responsible for generation of all critical reference voltages that can be used by

the various analog peripherals in the device.

LDO and Port U

The integrated 3.3V power system incorporates an integrated 3.3V LDO regulator that allows the entire MSP430

microcontroller to be powered from nominal 5V LDOI when it is made available for the system. Alternatively, the

power system can supply power only to other components within the system, or it can be unused altogether. The

Port U Pins (PU.0/PU.1) function as general-purpose high-current I/O pins. These pins can only be configured

together as either both inputs or bout outputs. Port U is supplied by the LDOO rail. If the 3.3V LDO is not being

used in the system (disabled), the LDOO pin can be supplied externally.

Embedded Emulation Module (EEM) (S Version)

The Embedded Emulation Module (EEM) supports real-time in-system debugging. The S version of the EEM

implemented on all devices has the following features:

•

Three hardware triggers/breakpoints on memory access

One hardware trigger/breakpoint on CPU register write access

Up to four hardware triggers can be combined to form complex triggers/breakpoints

One cycle counter

Clock control on module level

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Peripheral File Map

Table 17. Peripherals

OFFSET ADDRESS

RANGE

MODULE NAME

BASE ADDRESS

Special Functions (see Table 18)

PMM (see Table 19)

0100h

0120h

0140h

0150h

0158h

015Ch

0160h

0180h

01B0h

01C0h

01E0h

0200h

0220h

0240h

0320h

0340h

0380h

03C0h

0400h

04A0h

04C0h

0500h

0510h

0520h

0530h

05C0h

05E0h

0600h

0620h

0740h

08C0h

0900h

000h - 01Fh

000h - 00Fh

000h - 007h

000h - 001h

000h - 01Fh

000h - 001h

000h - 002h

000h - 007h

000h - 01Fh

000h - 00Bh

000h - 01Fh

000h - 02Eh

000h - 01Bh

000h - 02Fh

000h - 00Fh

000h - 00Ah

000h - 01Fh

000h - 00Fh

000h - 014h

Flash Control (see Table 20)

CRC16 (see Table 21)

RAM Control (see Table 22)

Watchdog (see Table 23)

UCS (see Table 24)

SYS (see Table 25)

Shared Reference (see Table 26)

Port Mapping Control (see Table 27)

Port Mapping Port P4 (see Table 27)

Port P1/P2 (see Table 28)

Port P3/P4 (see Table 29)

Port P5/P6 (see Table 30)

Port PJ (see Table 31)

TA0 (see Table 32)

TA1 (see Table 33)

TB0 (see Table 34)

TA2 (see Table 35)

Real-Time Clock (RTC_A) (see Table 36)

32-bit Hardware Multiplier (see Table 37)

DMA General Control (see Table 38)

DMA Channel 0 (see Table 38)

DMA Channel 1 (see Table 38)

DMA Channel 2 (see Table 38)

USCI_A0 (see Table 39)

USCI_B0 (see Table 40)

USCI_A1 (see Table 41)

USCI_B1 (see Table 42)

ADC10_A (see Table 43)

Comparator_B (see Table 44)

LDO-PWR and Port U configuration (see Table 45)

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Table 18. Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION

REGISTER

SFRIE1

OFFSET

SFR interrupt enable

SFR interrupt flag

00h

02h

04h

SFRIFG1

SFR reset pin control

SFRRPCR

Table 19. PMM Registers (Base Address: 0120h)

REGISTER DESCRIPTION

REGISTER

PMMCTL0

OFFSET

PMM Control 0

00h

02h

04h

06h

0Ch

0Eh

10h

PMM control 1

PMMCTL1

SVSMHCTL

SVSMLCTL

PMMIFG

SVS high side control

SVS low side control

PMM interrupt flags

PMM interrupt enable

PMM Power mode 5 control

PMMIE

PMM5CTL

Table 20. Flash Control Registers (Base Address: 0140h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Flash control 1

Flash control 3

Flash control 4

FCTL1

FCTL3

FCTL4

00h

04h

06h

Table 21. CRC16 Registers (Base Address: 0150h)

REGISTER DESCRIPTION

REGISTER

CRC16DI

OFFSET

CRC data input

00h

02h

04h

06h

CRC data input reverse byte

CRC initialization and result

CRC result reverse byte

CRCDIRB

CRCINIRES

CRCRESR

Table 22. RAM Control Registers (Base Address: 0158h)

REGISTER DESCRIPTION

REGISTER

RCCTL0

OFFSET

RAM control 0

00h

Table 23. Watchdog Registers (Base Address: 015Ch)

REGISTER DESCRIPTION

REGISTER

WDTCTL

Watchdog timer control

Table 24. UCS Registers (Base Address: 0160h)

REGISTER DESCRIPTION

REGISTER

UCSCTL0

UCS control 0

UCS control 1

UCS control 2

UCS control 3

UCS control 4

UCS control 5

UCS control 6

UCS control 7

UCS control 8

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

UCSCTL1

UCSCTL2

UCSCTL3

UCSCTL4

UCSCTL5

UCSCTL6

UCSCTL7

UCSCTL8

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Table 25. SYS Registers (Base Address: 0180h)

REGISTER DESCRIPTION

REGISTER

SYSCTL

OFFSET

System control

00h

02h

06h

08h

0Ah

0Ch

0Eh

18h

1Ah

1Ch

1Eh

Bootstrap loader configuration area

JTAG mailbox control

SYSBSLC

SYSJMBC

SYSJMBI0

SYSJMBI1

SYSJMBO0

SYSJMBO1

SYSBERRIV

SYSUNIV

JTAG mailbox input 0

JTAG mailbox input 1

JTAG mailbox output 0

JTAG mailbox output 1

Bus Error vector generator

User NMI vector generator

System NMI vector generator

Reset vector generator

SYSSNIV

SYSRSTIV

Table 26. Shared Reference Registers (Base Address: 01B0h)

REGISTER DESCRIPTION

REGISTER

REFCTL

OFFSET

Shared reference control

00h

Table 27. Port Mapping Registers

(Base Address of Port Mapping Control: 01C0h, Port P4: 01E0h)

REGISTER DESCRIPTION

REGISTER

PMAPPWD

Port mapping password register

Port mapping control register

Port P4.0 mapping register

Port P4.1 mapping register

Port P4.2 mapping register

Port P4.3 mapping register

Port P4.4 mapping register

Port P4.5 mapping register

Port P4.6 mapping register

Port P4.7 mapping register

00h

02h

00h

01h

02h

03h

04h

05h

06h

07h

PMAPCTL

P4MAP0

P4MAP1

P4MAP2

P4MAP3

P4MAP4

P4MAP5

P4MAP6

P4MAP7

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Table 28. Port P1/P2 Registers (Base Address: 0200h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P1 input

P1IN

00h

02h

04h

06h

08h

0Ah

0Eh

18h

1Ah

1Ch

01h

03h

05h

07h

09h

0Bh

1Eh

19h

1Bh

1Dh

Port P1 output

Port P1 direction

P1OUT

P1DIR

P1REN

P1DS

P1SEL

P1IV

Port P1 pullup/pulldown enable

Port P1 drive strength

Port P1 selection

Port P1 interrupt vector word

Port P1 interrupt edge select

Port P1 interrupt enable

Port P1 interrupt flag

P1IES

P1IE

P1IFG

P2IN

Port P2 input

Port P2 output

P2OUT

P2DIR

P2REN

P2DS

P2SEL

P2IV

Port P2 direction

Port P2 pullup/pulldown enable

Port P2 drive strength

Port P2 selection

Port P2 interrupt vector word

Port P2 interrupt edge select

Port P2 interrupt enable

Port P2 interrupt flag

P2IES

P2IE

P2IFG

Table 29. Port P3/P4 Registers (Base Address: 0220h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P3 input

P3IN

00h

02h

04h

06h

08h

0Ah

01h

03h

05h

07h

09h

0Bh

Port P3 output

P3OUT

P3DIR

P3REN

P3DS

Port P3 direction

Port P3 pullup/pulldown enable

Port P3 drive strength

Port P3 selection

P3SEL

P4IN

Port P4 input

Port P4 output

P4OUT

P4DIR

P4REN

P4DS

Port P4 direction

Port P4 pullup/pulldown enable

Port P4 drive strength

Port P4 selection

P4SEL

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Table 30. Port P5/P6 Registers (Base Address: 0240h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P5 input

P5IN

00h

02h

04h

06h

08h

0Ah

01h

03h

05h

07h

09h

0Bh

Port P5 output

Port P5 direction

P5OUT

P5DIR

P5REN

P5DS

Port P5 pullup/pulldown enable

Port P5 drive strength

Port P5 selection

P5SEL

P6IN

Port P6 input

Port P6 output

P6OUT

P6DIR

P6REN

P6DS

Port P6 direction

Port P6 pullup/pulldown enable

Port P6 drive strength

Port P6 selection

P6SEL

Table 31. Port J Registers (Base Address: 0320h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port PJ input

PJIN

00h

02h

04h

06h

08h

Port PJ output

PJOUT

PJDIR

PJREN

PJDS

Port PJ direction

Port PJ pullup/pulldown enable

Port PJ drive strength

Table 32. TA0 Registers (Base Address: 0340h)

REGISTER DESCRIPTION

REGISTER

TA0CTL

OFFSET

TA0 control

00h

02h

04h

06h

08h

0Ah

10h

12h

14h

16h

18h

1Ah

20h

2Eh

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

Capture/compare control 3

Capture/compare control 4

TA0 counter register

TA0CCTL0

TA0CCTL1

TA0CCTL2

TA0CCTL3

TA0CCTL4

TA0R

Capture/compare register 0

Capture/compare register 1

Capture/compare register 2

Capture/compare register 3

Capture/compare register 4

TA0 expansion register 0

TA0 interrupt vector

TA0CCR0

TA0CCR1

TA0CCR2

TA0CCR3

TA0CCR4

TA0EX0

TA0IV

32

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Table 33. TA1 Registers (Base Address: 0380h)

REGISTER DESCRIPTION

REGISTER

OFFSET

TA1 control

TA1CTL

00h

02h

04h

06h

10h

12h

14h

16h

20h

2Eh

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

TA1 counter register

TA1CCTL0

TA1CCTL1

TA1CCTL2

TA1R

Capture/compare register 0

Capture/compare register 1

Capture/compare register 2

TA1 expansion register 0

TA1 interrupt vector

TA1CCR0

TA1CCR1

TA1CCR2

TA1EX0

TA1IV

Table 34. TB0 Registers (Base Address: 03C0h)

REGISTER DESCRIPTION

REGISTER

TB0CTL

OFFSET

TB0 control

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

12h

14h

16h

18h

1Ah

1Ch

1Eh

20h

2Eh

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

Capture/compare control 3

Capture/compare control 4

Capture/compare control 5

Capture/compare control 6

TB0 register

TB0CCTL0

TB0CCTL1

TB0CCTL2

TB0CCTL3

TB0CCTL4

TB0CCTL5

TB0CCTL6

TB0R

Capture/compare register 0

Capture/compare register 1

Capture/compare register 2

Capture/compare register 3

Capture/compare register 4

Capture/compare register 5

Capture/compare register 6

TB0 expansion register 0

TB0 interrupt vector

TB0CCR0

TB0CCR1

TB0CCR2

TB0CCR3

TB0CCR4

TB0CCR5

TB0CCR6

TB0EX0

TB0IV

Table 35. TA2 Registers (Base Address: 0400h)

REGISTER DESCRIPTION

REGISTER

TA2CTL

OFFSET

TA2 control

00h

02h

04h

06h

10h

12h

14h

16h

20h

2Eh

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

TA2 counter register

TA2CCTL0

TA2CCTL1

TA2CCTL2

TA2R

Capture/compare register 0

Capture/compare register 1

Capture/compare register 2

TA2 expansion register 0

TA2 interrupt vector

TA2CCR0

TA2CCR1

TA2CCR2

TA2EX0

TA2IV

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Table 36. Real-Time Clock Registers (Base Address: 04A0h)

REGISTER DESCRIPTION

REGISTER

RTCCTL0

OFFSET

RTC control 0

00h

01h

02h

03h

08h

0Ah

0Ch

0Dh

0Eh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

RTC control 1

RTCCTL1

RTC control 2

RTCCTL2

RTC control 3

RTCCTL3

RTC prescaler 0 control

RTC prescaler 1 control

RTC prescaler 0

RTC prescaler 1

RTC interrupt vector word

RTCPS0CTL

RTCPS1CTL

RTCPS0

RTCPS1

RTCIV

RTC seconds/counter register 1

RTC minutes/counter register 2

RTC hours/counter register 3

RTC day of week/counter register 4

RTC days

RTCSEC/RTCNT1

RTCMIN/RTCNT2

RTCHOUR/RTCNT3

RTCDOW/RTCNT4

RTCDAY

RTC month

RTCMON

RTC year low

RTCYEARL

RTCYEARH

RTCAMIN

RTC year high

RTC alarm minutes

RTC alarm hours

RTCAHOUR

RTCADOW

RTCADAY

RTC alarm day of week

RTC alarm days

34

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Table 37. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

16-bit operand 1 – multiply

MPY

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

12h

14h

16h

18h

1Ah

1Ch

1Eh

20h

22h

24h

26h

28h

2Ah

2Ch

16-bit operand 1 – signed multiply

16-bit operand 1 – multiply accumulate

16-bit operand 1 – signed multiply accumulate

16-bit operand 2

MPYS

MAC

MACS

OP2

16 × 16 result low word

RESLO

RESHI

16 × 16 result high word

16 × 16 sum extension register

SUMEXT

MPY32L

MPY32H

MPYS32L

MPYS32H

MAC32L

MAC32H

MACS32L

MACS32H

OP2L

32-bit operand 1 – multiply low word

32-bit operand 1 – multiply high word

32-bit operand 1 – signed multiply low word

32-bit operand 1 – signed multiply high word

32-bit operand 1 – multiply accumulate low word

32-bit operand 1 – multiply accumulate high word

32-bit operand 1 – signed multiply accumulate low word

32-bit operand 1 – signed multiply accumulate high word

32-bit operand 2 – low word

32-bit operand 2 – high word

OP2H

32 × 32 result 0 – least significant word

32 × 32 result 1

RES0

RES1

32 × 32 result 2

RES2

32 × 32 result 3 – most significant word

MPY32 control register 0

RES3

MPY32CTL0

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Table 38. DMA Registers (Base Address DMA General Control: 0500h,

DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)

REGISTER DESCRIPTION

REGISTER

DMA0CTL

OFFSET

DMA channel 0 control

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Ah

DMA channel 0 source address low

DMA channel 0 source address high

DMA channel 0 destination address low

DMA channel 0 destination address high

DMA channel 0 transfer size

DMA0SAL

DMA0SAH

DMA0DAL

DMA0DAH

DMA0SZ

DMA channel 1 control

DMA1CTL

DMA1SAL

DMA1SAH

DMA1DAL

DMA1DAH

DMA1SZ

DMA channel 1 source address low

DMA channel 1 source address high

DMA channel 1 destination address low

DMA channel 1 destination address high

DMA channel 1 transfer size

DMA channel 2 control

DMA2CTL

DMA2SAL

DMA2SAH

DMA2DAL

DMA2DAH

DMA2SZ

DMA channel 2 source address low

DMA channel 2 source address high

DMA channel 2 destination address low

DMA channel 2 destination address high

DMA channel 2 transfer size

DMA module control 0

DMACTL0

DMACTL1

DMACTL2

DMACTL3

DMACTL4

DMAIV

DMA module control 1

DMA module control 2

DMA module control 3

DMA module control 4

DMA interrupt vector

Table 39. USCI_A0 Registers (Base Address: 05C0h)

REGISTER DESCRIPTION

REGISTER

UCA0CTL1

OFFSET

USCI control 0

00h

01h

06h

07h

08h

0Ah

0Ch

0Eh

10h

12h

13h

1Ch

1Dh

1Eh

USCI control 1

UCA0CTL0

UCA0BR0

USCI baud rate 0

USCI baud rate 1

UCA0BR1

USCI modulation control

USCI status

UCA0MCTL

UCA0STAT

UCA0RXBUF

UCA0TXBUF

UCA0ABCTL

UCA0IRTCTL

UCA0IRRCTL

UCA0IE

USCI receive buffer

USCI transmit buffer

USCI LIN control

USCI IrDA transmit control

USCI IrDA receive control

USCI interrupt enable

USCI interrupt flags

USCI interrupt vector word

UCA0IFG

UCA0IV

36

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Table 40. USCI_B0 Registers (Base Address: 05E0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI synchronous control 0

USCI synchronous control 1

USCI synchronous bit rate 0

USCI synchronous bit rate 1

USCI synchronous status

USCI synchronous receive buffer

USCI synchronous transmit buffer

USCI I2C own address

UCB0CTL1

UCB0CTL0

UCB0BR0

UCB0BR1

UCB0STAT

UCB0RXBUF

UCB0TXBUF

UCB0I2COA

UCB0I2CSA

UCB0IE

00h

01h

06h

07h

0Ah

0Ch

0Eh

10h

12h

1Ch

1Dh

1Eh

USCI I2C slave address

USCI interrupt enable

USCI interrupt flags

UCB0IFG

USCI interrupt vector word

UCB0IV

Table 41. USCI_A1 Registers (Base Address: 0600h)

REGISTER DESCRIPTION

REGISTER

UCA1CTL1

OFFSET

USCI control 0

00h

01h

06h

07h

08h

0Ah

0Ch

0Eh

10h

12h

13h

1Ch

1Dh

1Eh

USCI control 1

UCA1CTL0

UCA1BR0

USCI baud rate 0

USCI baud rate 1

UCA1BR1

USCI modulation control

USCI status

UCA1MCTL

UCA1STAT

UCA1RXBUF

UCA1TXBUF

UCA1ABCTL

UCA1IRTCTL

UCA1IRRCTL

UCA1IE

USCI receive buffer

USCI transmit buffer

USCI LIN control

USCI IrDA transmit control

USCI IrDA receive control

USCI interrupt enable

USCI interrupt flags

USCI interrupt vector word

UCA1IFG

UCA1IV

Table 42. USCI_B1 Registers (Base Address: 0620h)

REGISTER DESCRIPTION

REGISTER

UCB1CTL1

OFFSET

USCI synchronous control 0

USCI synchronous control 1

USCI synchronous bit rate 0

USCI synchronous bit rate 1

USCI synchronous status

USCI synchronous receive buffer

USCI synchronous transmit buffer

USCI I2C own address

00h

01h

06h

07h

0Ah

0Ch

0Eh

10h

12h

1Ch

1Dh

1Eh

UCB1CTL0

UCB1BR0

UCB1BR1

UCB1STAT

UCB1RXBUF

UCB1TXBUF

UCB1I2COA

UCB1I2CSA

UCB1IE

USCI I2C slave address

USCI interrupt enable

USCI interrupt flags

UCB1IFG

USCI interrupt vector word

UCB1IV

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Table 43. ADC10_A Registers (Base Address: 0740h)

REGISTER DESCRIPTION

REGISTER

ADC10CTL0

OFFSET

ADC10_A Control register 0

ADC10_A Control register 1

ADC10_A Control register 2

00h

02h

04h

06h

08h

0Ah

12h

1Ah

1Ch

1Eh

ADC10CTL1

ADC10CTL2

ADC10LO

ADC10_A Window Comparator Low Threshold

ADC10_A Window Comparator High Threshold

ADC10_A Memory Control Register 0

ADC10_A Conversion Memory Register

ADC10_A Interrupt Enable

ADC10HI

ADC10MCTL0

ADC10MEM0

ADC10IE

ADC10_A Interrupt Flags

ADC10IGH

ADC10IV

ADC10_A Interrupt Vector Word

Table 44. Comparator_B Registers (Base Address: 08C0h)

REGISTER DESCRIPTION

REGISTER

CBCTL0

OFFSET

Comp_B control register 0

Comp_B control register 1

Comp_B control register 2

Comp_B control register 3

Comp_B interrupt register

00h

02h

04h

06h

0Ch

0Eh

CBCTL1

CBCTL2

CBCTL3

CBINT

Comp_B interrupt vector word

CBIV

Table 45. LDO and Port U Configuration Registers (Base Address: 0900h)

REGISTER DESCRIPTION

REGISTER

LDOKEYPID

OFFSET

LDO key/ID register

PU port control

00h

04h

08h

PUCTL

LDO power control

LDOPWRCTL

38

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(1)

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

Voltage applied at V_CCto V_SS

–0.3 V to 4.1 V

–0.3 V to V_CC+ 0.3 V

±2 mA

(2)

Voltage applied to any pin (excluding VCORE, LDOI)

Diode current at any device pin

(3)

Storage temperature range, T_stg

–55°C to 150°C

95°C

Maximum junction temperature, T_J

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V_SS. VCORE is for internal device use only. No external DC loading or voltage should be applied.

(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

(1)

Thermal Packaging Characteristics

PARAMETER

VALUE

30

UNIT

VQFN (RGC)

VQFN (RGZ)

LQFP (PT)

28.6

62.8

55.5

15.6

14.4

18.2

21.2

1.6

(2)

θ_JA

Junction-to-ambient thermal resistance, still air

°C/W

BGA (ZQE)

VQFN (RGC)

VQFN (RGZ)

LQFP (PT)

(3)

θ_JC(TOP)

θ_JC(BOTTOM)

θ_JB

Junction-to-case (top) thermal resistance

°C/W

BGA (ZQE)

VQFN (RGC)

VQFN (RGZ)

LQFP (PT)

1.6

(4)

Junction-to-case (bottom) thermal resistance

N/A

8.9

BGA (ZQE)

VQFN (RGC)

VQFN (RGZ)

LQFP (PT)

5.5

(5)

Junction-to-board thermal resistance

28.3

19.3

BGA (ZQE)

(1) N/A = not applicable

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard

test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(5) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

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MAX UNIT

Recommended Operating Conditions

MIN NOM

PMMCOREVx = 0

1.8

2.0

2.2

2.4

0

3.6

V

PMMCOREVx = 0, 1

PMMCOREVx = 0, 1, 2

PMMCOREVx = 0, 1, 2, 3

Supply voltage during program execution and flash

V_CC

(1)

programming(AV_CC= DV_CC1/2= DV_CC

)

V

V_SS

T_A

Supply voltage (AV_SS= DV_SS1/2= DV_SS

Operating free-air temperature

Operating junction temperature

Capacitor at VCORE

)

V

I version

–40

-40

470

85

°C

nF

T_J

C_VCORE

C_DVCC

C_VCORE

/

Capacitor ratio of DVCC to VCORE

10

PMMCOREVx = 0,

1.8 V ≤ V_CC≤ 3.6 V

(default condition)

0

8.0

PMMCOREVx = 1,

2.0 V ≤ V_CC≤ 3.6 V

Processor frequency (maximum MCLK frequency) ⁽²⁾(see

Figure 1)

0

12.0

20.0

25.0

f_SYSTEM

MHz

PMMCOREVx = 2,

2.2 V ≤ V_CC≤ 3.6 V

PMMCOREVx = 3,

2.4 V ≤ V_CC≤ 3.6 V

(1) It is recommended to power AV_CCand DV_CCfrom the same source. A maximum difference of 0.3 V between AV_CCand DV_CCcan be

tolerated during power up and operation.

(2) Modules may have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.

25

3

20

2, 3

2

12

8

1, 2

1, 2, 3

1

0

0, 1

0, 1, 2

0, 1, 2, 3

0

1.8

2.0

2.2

2.4

3.6

Supply Voltage - V

The numbers within the fields denote the supported PMMCOREVx settings.

Figure 1. Maximum System Frequency

40

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Electrical Characteristics

Active Mode Supply Current Into V_CCExcluding External Current

(1) (2) (3)

over recommended operating free-air temperature (unless otherwise noted)

FREQUENCY (f_DCO= f_MCLK= f_SMCLK

)

EXECUTION

MEMORY

PARAMETER

V_CC

PMMCOREVx

1 MHz

8 MHz 12 MHz 20 MHz

25 MHz

UNIT

TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX

0

1

2

3

0

1

2

3

0.25 0.27 1.55 1.68

0.28

0.30

0.32

1.74

1.91

2.09

2.58 2.78

2.84

I_{AM, Flash}

Flash

RAM

3 V

mA

4.68 5.06

5.13

3.10

6.0

3.9

6.5

4.3

0.17 0.19 0.91 1.00

0.19

0.20

0.21

1.03

1.16

1.24

1.54 1.67

1.73

I_{AM, RAM}

3 V

mA

2.84 3.11

3.1

1.87

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load

capacitance are chosen to closely match the required 12.5 pF.

(3) Characterized with program executing typical data processing. LDO disabled (LDOEN = 0).

f_ACLK= 32786 Hz, f_DCO= f_MCLK= f_SMCLKat specified frequency.

XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.

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Low-Power Mode Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1) (2)

-40°C

TYP MAX

25°C

TYP MAX

77 85

60°C

TYP MAX

80

85°C

TYP MAX

80

PARAMETER

V_CC

PMMCOREVx

UNIT

2.2 V

3 V

0

3

0

3

0

1

2

0

1

2

3

0

1

2

3

0

1

2

3

73

79

97

105

11

(3) (4)

(5) (4)

Low-power mode 0

Low-power mode 2

µA

LPM0,1MHz

83

6.5

92

8

88

7.5

7.9

2.6

2.7

2.9

2.8

2.9

3.0

3.1

1.9

2.0

2.1

2.2

1.8

2.0

2.1

2.2

0.26

95

8

2.2 V

3 V

6.5

7.0

1.60

1.65

1.75

1.8

1.9

2.0

1.1

1.2

1.3

0.9

1.1

1.2

1.3

0.15

I_LPM2

7.0

9

8.9

3.4

3.6

3.8

3.6

3.8

4.0

2.7

2.8

2.9

3.0

2.5

2.6

2.7

2.8

0.45

13

1.90

2.00

2.15

2.1

2.2 V

Low-power mode 3,

crystal mode

I_LPM3,XT1LF

2.6

6.0

µA

(6) (4)

2.3

3 V

2.4

2.5

3.0

1.8

6.5

5.0

1.3

1.4

Low-power mode 3,

VLO mode⁽⁷⁾⁽⁴⁾

I_LPM3,VLO

3 V

1.5

2.0

1.5

5.5

4.8

1.1

1.2

I_LPM4

Low-power mode 4⁽⁸⁾⁽⁴⁾

Low-power mode 4.5⁽⁹⁾

3 V

µA

1.2

1.3

1.6

5.0

0.8

I_LPM4.5

0.18

0.35

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load

capacitance are chosen to closely match the required 12.5 pF.

(3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); f_ACLK= 32768 Hz, f_MCLK= 0 MHz, f_SMCLK= f_DCO= 1 MHz

LDO disabled (LDOEN = 0).

(4) Current for brownout, high side supervisor (SVS_H) normal mode included. Low side supervisor and monitors disabled (SVS_L, SVM_L).

High side monitor disabled (SVM_H). RAM retention enabled.

(5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); f_ACLK= 32768 Hz, f_MCLK= 0 MHz, f_SMCLK= f_DCO= 0 MHz; DCO setting = 1

MHz operation, DCO bias generator enabled.

LDO disabled (LDOEN = 0)

(6) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); f_ACLK= 32768 Hz, f_MCLK= f_SMCLK= f_DCO= 0 MHz

LDO disabled (LDOEN = 0)

(7) Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); f_ACLK= f_VLO, f_MCLK= f_SMCLK= f_DCO= 0 MHz

LDO disabled (LDOEN = 0)

(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); f_DCO= f_ACLK= f_MCLK= f_SMCLK= 0 MHz

LDO disabled (LDOEN = 0)

(9) Internal regulator disabled. No data retention.

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5); f_DCO= f_ACLK= f_MCLK= f_SMCLK= 0 MHz

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SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

(1)

Schmitt-Trigger Inputs – General Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

1.8 V

3 V

MIN

0.80

1.50

0.45

0.75

0.3

TYP

MAX UNIT

1.40

V

V_IT+

V_IT–

V_hys

Positive-going input threshold voltage

2.10

1.8 V

3 V

1.00

V

Negative-going input threshold voltage

1.65

1.8 V

3 V

0.85

V

Input voltage hysteresis (V_IT+– V_IT–

)

0.4

1.0

For pullup: V_IN= V_SS

For pulldown: V_IN= V_CC

R_Pull

C_I

Pullup/pulldown resistor

Input capacitance

20

35

5

50

kΩ

V_IN= V_SSor V_CC

pF

(1) Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).

(1)

Inputs – Ports P1 and P2

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

Port P1, P2: P1.x to P2.x, External trigger pulse width to

set interrupt flag

(2)

t_(int)

External interrupt timing

2.2 V/3 V

20

ns

(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.

(2) An external signal sets the interrupt flag every time the minimum interrupt pulse width t_(int)is met. It may be set by trigger signals shorter

than t_(int)

.

Leakage Current – General Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

(1) (2)

V_CC

MIN

MAX UNIT

±50 nA

I_lkg(Px.x)

High-impedance leakage current

1.8 V/3 V

(1) The leakage current is measured with V_SSor V_CCapplied to the corresponding pin(s), unless otherwise noted.

(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is

disabled.

Outputs – General Purpose I/O (Full Drive Strength)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

_CC– 0.25

_CC– 0.60

_CC– 0.25

_CC– 0.60

MAX UNIT

(1)

I_(OHmax)= –3 mA

V

V_CC

1.8 V

(2)

I_(OHmax)= –10 mA

V_CC

V_OH

High-level output voltage

V

(1)

I_(OHmax)= –5 mA

V_CC

3 V

1.8 V

3 V

(2)

I_(OHmax)= –15 mA

V_CC

(1)

I_(OLmax)= 3 mA

V_SSV_SS+ 0.25

(2)

I_(OLmax)= 10 mA

V_SSV_SS+ 0.60

V_SSV_SS+ 0.25

V_SSV_SS+ 0.60

Low-level output voltage

V

OL

(1)

I_(OLmax)= 5 mA

I_(OLmax)= 15 mA

(2)

(1) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop

specified.

(2) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage

drop specified.

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MSP430F530x, MSP430F5310

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Outputs – General Purpose I/O (Reduced Drive Strength)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

V_CC

MIN

_CC– 0.25

_CC– 0.60

_CC– 0.25

_CC– 0.60

MAX UNIT

(2)

I_(OHmax)= –1 mA

V

V_CC

1.8 V

(3)

(2)

(3)

I_(OHmax)= –3 mA

I_(OHmax)= –2 mA

I_(OHmax)= –6 mA

V_CC

V_OH

High-level output voltage

V

V_CC

3 V

1.8 V

3 V

V_CC

(2)

I_(OLmax)= 1 mA

I_(OLmax)= 3 mA

I_(OLmax)= 2 mA

I_(OLmax)= 6 mA

V_SSV_SS+ 0.25

V_SSV_SS+ 0.60

V_SSV_SS+ 0.25

V_SSV_SS+ 0.60

(3)

V_OL

Low-level output voltage

V

(2)

(3)

(1) Selecting reduced drive strength may reduce EMI.

(2) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop

specified.

(3) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage

drop specified.

Output Frequency – General Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX UNIT

(1)(2)

V

CC

= 1.8 V

16

PMMCOREVx = 0

Port output frequency

(with load)

f_Px.y

MHz

25

V_CC= 3 V

PMMCOREVx = 3

V_CC= 1.8 V

PMMCOREVx = 0

ACLK

SMCLK

MCLK

16

f_{Port_CLK}

Clock output frequency

MHz

25

V_CC= 3 V

PMMCOREVx = 3

(2)

C_L= 20 pF

(1) A resistive divider with 2 × R1 between V_CCand V_SSis used as load. The output is connected to the center tap of the divider. For full

drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. C_L= 20 pF is connected to the output to V_SS

.

(2) The output voltage reaches at least 10% and 90% V_CCat the specified toggle frequency.

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Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TYPICAL LOW-LEVEL OUTPUT CURRENT

vs

LOW-LEVEL OUTPUT VOLTAGE

8.0

7.0

6.0

5.0

4.0

3.0

2.0

1.0

0.0

25.0

20.0

15.0

10.0

5.0

T_A= 25°C

V_CC= 3.0 V

V_CC= 1.8 V

Px.y

T_A= 25°C

T_A= 85°C

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

V_OL– Low-Level Output Voltage – V

Figure 2.

Figure 3.

TYPICAL HIGH-LEVEL OUTPUT CURRENT

vs

HIGH-LEVEL OUTPUT VOLTAGE

0.0

-1.0

-2.0

-3.0

-4.0

-5.0

-6.0

-7.0

-8.0

0.0

-5.0

V_CC= 1.8 V

Px.y

V_CC= 3.0 V

Px.y

-10.0

-15.0

-20.0

-25.0

T_A= 85°C

T_A= 25°C

T_A= 85°C

T_A= 25°C

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

V_OH– High-Level Output Voltage – V

Figure 4.

Figure 5.

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MSP430F530x, MSP430F5310

SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

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MAX UNIT

(1)

Crystal Oscillator, XT1, Low-Frequency Mode

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 1,

T_A= 25°C

0.075

Differential XT1 oscillator crystal

f_OSC= 32768 Hz, XTS = 0,

ΔI_DVCC.LF

current consumption from lowest XT1BYPASS = 0, XT1DRIVEx = 2,

3 V

0.170

µA

drive setting, LF mode

T_A= 25°C

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 3,

T_A= 25°C

0.290

XT1 oscillator crystal frequency,

LF mode

f_XT1,LF0

XTS = 0, XT1BYPASS = 0

32768

Hz

XT1 oscillator logic-level

square-wave input frequency,

LF mode

(2) (3)

f_XT1,LF,SW

XTS = 0, XT1BYPASS = 1

10 32.768

210

50 kHz

XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 0,

f_XT1,LF= 32768 Hz, C_L,eff= 6 pF

Oscillation allowance for

OA_LF

kΩ

(4)

LF crystals

XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 1,

f_XT1,LF= 32768 Hz, C_L,eff= 12 pF

300

(6)

XTS = 0, XCAPx = 0

2

5.5

XTS = 0, XCAPx = 1

XTS = 0, XCAPx = 2

XTS = 0, XCAPx = 3

Integrated effective load

capacitance, LF mode

C_L,eff

pF

(5)

8.5

12.0

XTS = 0, Measured at ACLK,

f_XT1,LF= 32768 Hz

Duty cycle LF mode

30

10

70

%

Oscillator fault frequency,

(8)

f_Fault,LF

XTS = 0

10000

Hz

(7)

LF mode

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 0,

T_A= 25°C,

1000

500

C_L,eff= 6 pF

t_START,LF

Startup time, LF mode

3 V

ms

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 3,

T_A= 25°C,

C_L,eff= 12 pF

(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.

(a) Keep the trace between the device and the crystal as short as possible.

(b) Design a good ground plane around the oscillator pins.

(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.

(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

(2) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in

the Schmitt-trigger Inputs section of this datasheet.

(3) Maximum frequency of operation of the entire device cannot be exceeded.

(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the

XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following

guidelines, but should be evaluated based on the actual crystal selected for the application:

(a) For XT1DRIVEx = 0, C_{L,ef f}≤ 6 pF.

(b) For XT1DRIVEx = 1, 6 pF ≤ C_{L,ef f}≤ 9 pF.

(c) For XT1DRIVEx = 2, 6 pF ≤ C_{L,ef f}≤ 10 pF.

(d) For XT1DRIVEx = 3, C_{L,ef f}≥ 6 pF.

(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a

correct setup, the effective load capacitance should always match the specification of the used crystal.

(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(8) Measured with logic-level input frequency but also applies to operation with crystals.

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Crystal Oscillator, XT2

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1) (2)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

f_OSC= 4 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 0, T_A= 25°C

200

f_OSC= 12 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 1, T_A= 25°C

260

325

450

XT2 oscillator crystal current

consumption

I_DVCC.XT2

3 V

µA

f_OSC= 20 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 2, T_A= 25°C

f_OSC= 32 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 3, T_A= 25°C

XT2 oscillator crystal

frequency, mode 0

(3)

f_XT2,HF0

f_XT2,HF1

f_XT2,HF2

f_XT2,HF3

XT2DRIVEx = 0, XT2BYPASS = 0

4

8

MHz

XT2 oscillator crystal

frequency, mode 1

(3)

XT2DRIVEx = 1, XT2BYPASS = 0

16 MHz

24 MHz

32 MHz

XT2 oscillator crystal

frequency, mode 2

(3)

XT2DRIVEx = 2, XT2BYPASS = 0

16

24

XT2 oscillator crystal

frequency, mode 3

(3)

XT2DRIVEx = 3, XT2BYPASS = 0

XT2 oscillator logic-level

f_XT2,HF,SWsquare-wave input frequency,

bypass mode

(4) (3)

XT2BYPASS = 1

0.7

32 MHz

XT2DRIVEx = 0, XT2BYPASS = 0,

f_XT2,HF0= 6 MHz, C_L,eff= 15 pF

450

320

200

XT2DRIVEx = 1, XT2BYPASS = 0,

f_XT2,HF1= 12 MHz, C_L,eff= 15 pF

Oscillation allowance for

HF crystals

OA_HF

Ω

(5)

XT2DRIVEx = 2, XT2BYPASS = 0,

f_XT2,HF2= 20 MHz, C_L,eff= 15 pF

XT2DRIVEx = 3, XT2BYPASS = 0,

f_XT2,HF3= 32 MHz, C_L,eff= 15 pF

f_OSC= 6 MHz,

XT2BYPASS = 0, XT2DRIVEx = 0,

T_A= 25°C, C_L,eff= 15 pF

0.5

0.3

t_START,HF

Startup time

3 V

ms

pF

f_OSC= 20 MHz

XT2BYPASS = 0, XT2DRIVEx = 2,

T_A= 25°C, C_L,eff= 15 pF

Integrated effective load

capacitance, HF mode

C_L,eff

1

(6) (1)

Duty cycle

Measured at ACLK, f_XT2,HF2= 20 MHz

40

30

50

60

%

(7)

(8)

f_Fault,HF

Oscillator fault frequency

XT2BYPASS = 1

300 kHz

(1) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

(2) To improve EMI on the XT2 oscillator the following guidelines should be observed.

(a) Keep the traces between the device and the crystal as short as possible.

(b) Design a good ground plane around the oscillator pins.

(c) Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.

(d) Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.

(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.

(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

(3) This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device

operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.

(4) When XT2BYPASS is set, the XT2 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined

in the Schmitt-trigger Inputs section of this datasheet.

(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.

(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a

correct setup, the effective load capacitance should always match the specification of the used crystal.

(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(8) Measured with logic-level input frequency but also applies to operation with crystals.

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Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

VLO frequency

VLO frequency temperature drift

TEST CONDITIONS

V_CC

MIN

TYP

9.4

0.5

4

MAX UNIT

14 kHz

%/°C

f_VLO

Measured at ACLK

1.8 V to 3.6 V

6

(1)

(2)

df_VLO/d_T

Measured at ACLK

df_VLO/dV_CCVLO frequency supply voltage drift

Duty cycle

%/V

40

50

60

%

(1) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))

(2) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)

Internal Reference, Low-Frequency Oscillator (REFO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

3

MAX UNIT

I_REFO

REFO oscillator current consumption T_A= 25°C

1.8 V to 3.6 V

3 V

µA

REFO frequency calibrated

Measured at ACLK

32768

Hz

f_REFO

Full temperature range

±3.5

%

REFO absolute tolerance calibrated

REFO frequency temperature drift

T_A= 25°C

±1.5

(1)

df_REFO/d_T

Measured at ACLK

1.8 V to 3.6 V

0.01

1.0

50

%/°C

(2)

df_REFO/dV_CC

REFO frequency supply voltage drift Measured at ACLK

%/V

Duty cycle

Measured at ACLK

40%/60% duty cycle

40

60

%

t_START

REFO startup time

25

µs

(1) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))

(2) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)

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DCO Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

DCORSELx = 0, DCOx = 0, MODx = 0

DCORSELx = 0, DCOx = 31, MODx = 0

DCORSELx = 1, DCOx = 0, MODx = 0

DCORSELx = 1, DCOx = 31, MODx = 0

DCORSELx = 2, DCOx = 0, MODx = 0

DCORSELx = 2, DCOx = 31, MODx = 0

DCORSELx = 3, DCOx = 0, MODx = 0

DCORSELx = 3, DCOx = 31, MODx = 0

DCORSELx = 4, DCOx = 0, MODx = 0

DCORSELx = 4, DCOx = 31, MODx = 0

DCORSELx = 5, DCOx = 0, MODx = 0

DCORSELx = 5, DCOx = 31, MODx = 0

DCORSELx = 6, DCOx = 0, MODx = 0

DCORSELx = 6, DCOx = 31, MODx = 0

DCORSELx = 7, DCOx = 0, MODx = 0

DCORSELx = 7, DCOx = 31, MODx = 0

MIN

0.07

0.70

0.15

1.47

0.32

3.17

0.64

6.07

1.3

TYP

MAX UNIT

0.20 MHz

1.70 MHz

0.36 MHz

3.45 MHz

0.75 MHz

7.38 MHz

1.51 MHz

14.0 MHz

3.2 MHz

f_DCO(0,0)

f_DCO(0,31)

f_DCO(1,0)

f_DCO(1,31)

f_DCO(2,0)

f_DCO(2,31)

f_DCO(3,0)

f_DCO(3,31)

f_DCO(4,0)

f_DCO(4,31)

f_DCO(5,0)

f_DCO(5,31)

f_DCO(6,0)

f_DCO(6,31)

f_DCO(7,0)

f_DCO(7,31)

DCO frequency (0, 0)

DCO frequency (0, 31)

DCO frequency (1, 0)

DCO frequency (1, 31)

DCO frequency (2, 0)

DCO frequency (2, 31)

DCO frequency (3, 0)

DCO frequency (3, 31)

DCO frequency (4, 0)

DCO frequency (4, 31)

DCO frequency (5, 0)

DCO frequency (5, 31)

DCO frequency (6, 0)

DCO frequency (6, 31)

DCO frequency (7, 0)

DCO frequency (7, 31)

12.3

2.5

28.2 MHz

6.0 MHz

23.7

4.6

54.1 MHz

10.7 MHz

88.0 MHz

19.6 MHz

135 MHz

39.0

8.5

60

Frequency step between range

DCORSEL and DCORSEL + 1

S_DCORSEL

S_RSEL= f_{DCO(DCORSEL+1,DCO)}/f_{DCO(DCORSEL,DCO)}

1.2

2.3 ratio

Frequency step between tap

DCO and DCO + 1

S_DCO

S_DCO= f_{DCO(DCORSEL,DCO+1)}/f_{DCO(DCORSEL,DCO)}

Measured at SMCLK

1.02

40

1.12 ratio

Duty cycle

df_DCO/dT

df_DCO/dV_CC

50

0.1

1.9

60

%

DCO frequency temperature drift

f_DCO= 1 MHz,

%/°C

%/V

(1)

(2)

DCO frequency voltage drift

f_DCO= 1 MHz

(1) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))

(2) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)

Typical DCO Frequency, V_CC= 3.0 V,T_A= 25°C

100

10

DCOx = 31

1

DCOx = 0

0.1

0

1

2

3

4

5

6

7

DCORSEL

Figure 6. Typical DCO frequency

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MAX UNIT

PMM, Brown-Out Reset (BOR)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

| dDV_CC/d_t| < 3 V/s

MIN

TYP

BOR_Hon voltage,

DV_CCfalling level

V(DV_CC_BOR_IT–)

1.45

1.50

V

BOR_Hoff voltage,

DV_CCrising level

V(DV_CC_BOR_IT+)

V(DV_CC_BOR_hys)

0.80

60

1.30

BOR_Hhysteresis

250 mV

Pulse length required at

RST/NMI pin to accept a

reset

t_RESET

2

µs

PMM, Core Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Core voltage, active mode,

PMMCOREV = 3

V_CORE3(AM)

V_CORE2(AM)

V_CORE1(AM)

V_CORE0(AM)

V_CORE3(LPM)

V_CORE2(LPM)

V_CORE1(LPM)

V_CORE0(LPM)

2.4 V ≤ DV_CC≤ 3.6 V

1.90

V

Core voltage, active mode,

PMMCOREV = 2

2.2 V ≤ DV_CC≤ 3.6 V

2.0 V ≤ DV_CC≤ 3.6 V

1.8 V ≤ DV_CC≤ 3.6 V

2.4 V ≤ DV_CC≤ 3.6 V

2.2 V ≤ DV_CC≤ 3.6 V

2.0 V ≤ DV_CC≤ 3.6 V

1.8 V ≤ DV_CC≤ 3.6 V

1.80

1.60

1.40

1.94

1.84

1.64

1.44

V

Core voltage, active mode,

PMMCOREV = 1

Core voltage, active mode,

PMMCOREV = 0

Core voltage, low-current mode,

PMMCOREV = 3

Core voltage, low-current mode,

PMMCOREV = 2

Core voltage, low-current mode,

PMMCOREV = 1

Core voltage, low-current mode,

PMMCOREV = 0

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PMM, SVS High Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SVSHE = 0, DV_CC= 3.6 V

MIN

TYP

0

MAX UNIT

nA

I_(SVSH)

SVS current consumption SVSHE = 1, DV_CC= 3.6 V, SVSHFP = 0

SVSHE = 1, DV_CC= 3.6 V, SVSHFP = 1

200

1.5

µA

SVSHE = 1, SVSHRVL = 0

1.57

1.79

1.98

2.10

1.62

1.88

2.07

2.20

2.32

2.52

2.90

1.68

1.88

2.08

2.18

1.74

1.94

2.14

2.30

2.40

2.70

3.10

1.78

SVSHE = 1, SVSHRVL = 1

1.98

V

(1)

V_{(SVSH_IT–)}

SVS_Hon voltage level

SVSHE = 1, SVSHRVL = 2

SVSHE = 1, SVSHRVL = 3

SVSHE = 1, SVSMHRRL = 0

SVSHE = 1, SVSMHRRL = 1

SVSHE = 1, SVSMHRRL = 2

2.21

2.31

1.85

2.07

2.28

SVSHE = 1, SVSMHRRL = 3

2.42

V

(1)

V_{(SVSH_IT+)}

SVS_Hoff voltage level

SVSHE = 1, SVSMHRRL = 4

SVSHE = 1, SVSMHRRL = 5

SVSHE = 1, SVSMHRRL = 6

SVSHE = 1, SVSMHRRL = 7

SVSHE = 1, dV_DVCC/dt = 10 mV/µs,

2.55

2.88

3.23

2.5

20

SVSHFP = 1

t_pd(SVSH)

SVS_Hpropagation delay

µs

SVSHE = 1, dV_DVCC/dt = 1 mV/µs,

SVSHFP = 0

SVSHE = 0 → 1

SVSHFP = 1

12.5

100

t_(SVSH)

SVS_Hon/off delay time

SVSHE = 0 → 1

SVSHFP = 0

dV_DVCC/dt

DV_CCrise time

0

1000

V/s

(1) The SVS_Hsettings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage

Supervisor chapter in the MSP430x5xx/MSP430x6xx Family User's Guide (SLAU208) on recommended settings and usage.

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PMM, SVM High Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SVMHE = 0, DV_CC= 3.6 V

MIN

TYP

0

MAX UNIT

nA

I_(SVMH)

SVM_Hcurrent consumption

SVMHE= 1, DV_CC= 3.6 V, SVMHFP = 0

SVMHE = 1, DV_CC= 3.6 V, SVMHFP = 1

SVMHE = 1, SVSMHRRL = 0

SVMHE = 1, SVSMHRRL = 1

SVMHE = 1, SVSMHRRL = 2

SVMHE = 1, SVSMHRRL = 3

SVMHE = 1, SVSMHRRL = 4

SVMHE = 1, SVSMHRRL = 5

SVMHE = 1, SVSMHRRL = 6

SVMHE = 1, SVSMHRRL = 7

SVMHE = 1, SVMHOVPE = 1

200

1.5

µA

1.85

1.62

1.88

2.07

2.20

2.32

2.52

2.90

1.74

1.94

2.14

2.30

2.40

2.70

3.10

3.75

2.07

2.28

2.42

(1)

V_(SVMH)

SVM_Hon/off voltage level

2.55

2.88

3.23

V

SVMHE = 1, dV_DVCC/dt = 10 mV/µs,

SVMHFP = 1

2.5

20

t_pd(SVMH)

SVM_Hpropagation delay

SVM_Hon/off delay time

µs

SVMHE = 1, dV_DVCC/dt = 1 mV/µs,

SVMHFP = 0

SVMHE = 0 → 1

SVMHFP = 1

12.5

100

t_(SVMH)

SVMHE = 0 → 1

SVMHFP = 0

(1) The SVM_Hsettings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage

Supervisor chapter in the MSP430x5xx/MSP430x6xx Family User's Guide (SLAU208) on recommended settings and usage.

PMM, SVS Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SVSLE = 0, PMMCOREV = 2

MIN

TYP

0

MAX UNIT

nA

I_(SVSL)

SVS_Lcurrent consumption

SVSLE = 1, PMMCOREV = 2, SVSLFP = 0

SVSLE = 1, PMMCOREV = 2, SVSLFP = 1

200

2.0

µA

SVSLE = 1, dV_CORE/dt = 10 mV/µs,

SVSLFP = 1

2.5

20

t_pd(SVSL)

SVS_Lpropagation delay

SVS_Lon/off delay time

µs

SVSLE = 1, dV_CORE/dt = 1 mV/µs,

SVSLFP = 0

SVSLE = 0 → 1

SVSLFP = 1

12.5

100

t_(SVSL)

SVSLE = 0 → 1

SVSLFP = 0

PMM, SVM Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SVMLE = 0, PMMCOREV = 2

MIN

TYP

0

MAX UNIT

nA

µA

µs

I_(SVML)

SVM_Lcurrent consumption

SVMLE= 1, PMMCOREV = 2, SVMLFP = 0

SVMLE= 1, PMMCOREV = 2, SVMLFP = 1

SVMLE = 1, dV_CORE/dt = 10 mV/µs, SVMLFP = 1

SVMLE = 1, dV_CORE/dt = 1 mV/µs, SVMLFP = 0

SVMLE = 0 → 1, SVMLFP = 1

200

1.5

2.5

20

t_pd(SVML)

SVM_Lpropagation delay

SVM_Lon/off delay time

12.5

100

t_(SVML)

µs

SVMLE = 0 → 1, SVMLFP = 0

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Wake-Up from Low Power Modes and Reset

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Wake-up time from LPM2,

LPM3, or LPM4 to active

mode

PMMCOREV = SVSMLRRL = n,

where n = 0, 1, 2, or 3,

SVSLFP = 1

f

_MCLK≥ 4.0 MHz

_MCLK< 4.0 MHz

5

t_WAKE-UP-FAST

µs

(1)

f

6

Wake-up time from LPM2,

LPM3 or LPM4 to active

mode

PMMCOREV = SVSMLRRL = n,

where n = 0, 1, 2, or 3,

SVSLFP = 0

t_WAKE-UP-SLOW

150

165

µs

(2)

Wake-up time from LPM4.5

to active mode

t_WAKE-UP-LPM5

t_{WAKE-UP-RESET}

2

3

ms

(3)

Wake-up time from RST or

BOR event to active mode

(3)

(1) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance

mode of the low side supervisor (SVS_L) and low side monitor (SVM_L). Fastest wakeup times are possible with SVS_Land SVM_Lin full

performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVS_Land SVM_Lwhile

operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the

MSP430x5xx/MSP430x6xx Family User's Guide (SLAU208).

(2) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance

mode of the low side supervisor (SVS_L) and low side monitor (SVM_L). In this case, the SVS_Land SVM_Lare in normal mode (low current)

mode when operating in AM, LPM0, and LPM1. Various options are available for SVS_Land SVM_Lwhile operating in LPM2, LPM3, and

LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx/MSP430x6xx Family User's

Guide (SLAU208).

(3) This value represents the time from the wakeup event to the reset vector execution.

Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK

f_TA

Timer_A input clock frequency

External: TACLK

1.8 V/3 V

25 MHz

Duty cycle = 50% ± 10%

All capture inputs.

t_TA,cap

Timer_A capture timing

Minimum pulse width required for

capture.

1.8 V/3 V

20

ns

Timer_B

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK

f_TB

Timer_B input clock frequency

External: TBCLK

1.8 V/3 V

25 MHz

Duty cycle = 50% ± 10%

All capture inputs.

t_TB,cap

Timer_B capture timing

Minimum pulse width required for

capture.

1.8 V/3 V

20

ns

USCI (UART Mode) - recommended operating conditions

PARAMETER

CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK

External: UCLK

f_USCI

USCI input clock frequency

f_SYSTEMMHz

Duty cycle = 50% ± 10%

BITCLK clock frequency

(equals baud rate in MBaud)

f_BITCLK

1

MHz

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MAX UNIT

USCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

2.2 V

3 V

MIN

50

TYP

600

ns

(1)

t_τ

UART receive deglitch time

50

600

(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are

correctly recognized their width should exceed the maximum specification of the deglitch time.

USCI (SPI Master Mode) - recommended operating conditions

PARAMETER

CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK

Duty cycle = 50% ± 10%

f_USCI

USCI input clock frequency

f_SYSTEMMHz

USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(see Note ⁽¹⁾, Figure 7 and Figure 8)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

SMCLK, ACLK

Duty cycle = 50% ± 10%

f_USCI

USCI input clock frequency

f_SYSTEMMHz

1.8 V

3 V

55

38

30

25

0

PMMCOREV = 0

ns

t_SU,MI

SOMI input data setup time

SOMI input data hold time

SIMO output data valid time

SIMO output data hold time

2.4 V

3 V

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

1.8 V

3 V

0

t_HD,MI

2.4 V

3 V

0

1.8 V

3 V

20

ns

18

UCLK edge to SIMO valid,

C_L= 20 pF, PMMCOREV = 0

(2)

t_VALID,MO

2.4 V

3 V

16

ns

15

UCLK edge to SIMO valid,

C_L= 20 pF, PMMCOREV = 3

1.8 V

3 V

-10

-8

C_L= 20 pF, PMMCOREV = 0

C_L= 20 pF, PMMCOREV = 3

ns

(3)

t_HD,MO

2.4 V

3 V

-10

-8

(1) f_UCxCLK= 1/2t_LO/HIwith t_LO/HI≥ max(t_{VALID,MO(USCI)}+ t_SU,SI(Slave), t_SU,MI(USCI)+ t_{VALID,SO(Slave)}).

For the slave's parameters t_SU,SI(Slave)and t_{VALID,SO(Slave)}see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing

diagrams in Figure 7 and Figure 8.

(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data

on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in

Figure 7 and Figure 8.

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1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_LO/HI

t_SU,MI

t_HD,MI

SOMI

t_HD,MO

t_VALID,MO

SIMO

Figure 7. SPI Master Mode, CKPH = 0

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_LO/HI

t_HD,MI

t_SU,MI

SOMI

t_HD,MO

t_VALID,MO

SIMO

Figure 8. SPI Master Mode, CKPH = 1

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USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(see Note ⁽¹⁾, Figure 9 and Figure 10)

PARAMETER

TEST CONDITIONS

V_CC

1.8 V

3 V

MIN

11

8

TYP

MAX UNIT

PMMCOREV = 0

ns

t_STE,LEAD

t_STE,LAG

t_STE,ACC

t_STE,DIS

t_SU,SI

STE lead time, STE low to clock

2.4 V

3 V

7

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

ns

6

1.8 V

3 V

3

STE lag time, Last clock to STE high

2.4 V

3 V

3

1.8 V

3 V

66

ns

50

STE access time, STE low to SOMI data out

2.4 V

3 V

36

ns

30

1.8 V

3 V

30

ns

23

STE disable time, STE high to SOMI high

impedance

2.4 V

3 V

16

ns

13

1.8 V

3 V

5

2

5

ns

SIMO input data setup time

SIMO input data hold time

2.4 V

3 V

1.8 V

3 V

t_HD,SI

2.4 V

3 V

ns

UCLK edge to SOMI valid,

C_L= 20 pF

PMMCOREV = 0

1.8 V

76

ns

3 V

2.4 V

3 V

60

(2)

t_VALID,SO

SOMI output data valid time

UCLK edge to SOMI valid,

C_L= 20 pF

PMMCOREV = 3

44

ns

40

1.8 V

3 V

18

12

10

8

C_L= 20 pF

PMMCOREV = 0

ns

(3)

t_HD,SO

SOMI output data hold time

2.4 V

3 V

C_L= 20 pF

PMMCOREV = 3

(1) f_UCxCLK= 1/2t_LO/HIwith t_LO/HI≥ max(t_{VALID,MO(Master)}+ t_SU,SI(USCI), t_{SU,MI(Master)}+ t_{VALID,SO(USCI)}).

For the master's parameters t_{SU,MI(Master)}and t_{VALID,MO(Master)}see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing

diagrams in Figure 7 and Figure 8.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in

Figure 7 and Figure 8.

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t_STE,LAG

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t_STE,LEAD

STE

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_SU,SI

t_LO/HI

t_HD,SI

SIMO

t_HD,SO

t_VALID,SO

t_STE,ACC

t_STE,DIS

SOMI

Figure 9. SPI Slave Mode, CKPH = 0

t_STE,LEAD

t_STE,LAG

STE

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_LO/HI

t_HD,SI

t_SU,SI

SIMO

t_HD,MO

t_VALID,SO

t_STE,ACC

t_STE,DIS

SOMI

Figure 10. SPI Slave Mode, CKPH = 1

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USCI (I2C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 11)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK

External: UCLK

f_USCI

USCI input clock frequency

f_SYSTEMMHz

Duty cycle = 50% ± 10%

f_SCL

SCL clock frequency

2.2 V/3 V

0

4.0

0.6

4.7

0.6

0

400 kHz

f

_SCL≤ 100 kHz

_SCL> 100 kHz

_SCL≤ 100 kHz

_SCL> 100 kHz

t_HD,STA

Hold time (repeated) START

µs

t_SU,STA

Setup time for a repeated START

2.2 V/3 V

µs

t_HD,DAT

t_SU,DAT

Data hold time

Data setup time

2.2 V/3 V

ns

250

4.0

0.6

50

f_SCL≤ 100 kHz

_SCL> 100 kHz

t_SU,STO

Setup time for STOP

2.2 V/3 V

µs

f

2.2 V

3 V

600

ns

t_SP

Pulse width of spikes suppressed by input filter

50

600

t_HD,STA

t_SU,STA

t_HD,STA

t_BUF

SDA

SCL

t_LOW

t_HIGH

t_SP

t_SU,DAT

t_SU,STO

t_HD,DAT

Figure 11. I2C Mode Timing

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10-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

AV_CCand DV_CCare connected together,

AV_SSand DV_SSare connected together,

V_(AVSS)= V_(DVSS)= 0 V

AV_CC

V_(Ax)

Analog supply voltage

1.8

3.6

V

All ADC10_A pins: P1.0 to P1.5 and P3.6 and

P3.7 terminals

(2)

Analog input voltage range

0

AV_CC

100

f_ADC10CLK= 5 MHz, ADC10ON = 1, REFON =

0,

SHT0 = 0, SHT1 = 0, ADC10DIV = 0,

ADC10SREF = 00

2.2 V

3 V

60

75

Operating supply current into

AV_CCterminal. REF module

and reference buffer off.

µA

110

f_ADC10CLK= 5 MHz, ADC10ON = 1, REFON =

1,

SHT0 = 0, SHT1 = 0, ADC10DIV = 0,

ADC10SREF = 01

Operating supply current into

AV_CCterminal. REF module

on, reference buffer on.

3 V

113

105

150

I_{ADC10_A}

f_ADC10CLK= 5 MHz, ADC10ON = 1, REFON =

0,

SHT0 = 0, SHT1 = 0, ADC10DIV = 0,

ADC10SREF = 10, VEREF = 2.5 V

Operating supply current into

AV_CCterminal. REF module

off, reference buffer on.

140

110

f_ADC10CLK= 5 MHz, ADC10ON = 1, REFON =

0,

SHT0 = 0, SHT1 = 0, ADC10DIV = 0,

ADC10SREF = 11, VEREF = 2.5 V

Operating supply current into

AV_CCterminal. REF module

off, reference buffer off.

3 V

70

Only one terminal Ax can be selected at one

time from the pad to the ADC10_A capacitor

array including wiring and pad.

C_I

R_I

Input capacitance

2.2 V

3.5

pF

AV_CC> 2.0V, 0 V ≤ V_Ax≤ AV_CC

36

96

Input MUX ON resistance

kΩ

1.8V < AV_CC< 2.0V, 0 V ≤ V_Ax≤ AV_CC

(1) The leakage current is defined in the leakage current table with P6.x/Ax parameter.

(2) The analog input voltage range must be within the selected reference voltage range V_R+to V_R–for valid conversion results. The external

reference voltage requires decoupling capacitors. See ⁽⁾

.

10-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

For specified performance of ADC10_A linearity

parameters

f_ADC10CLK

f_ADC10OSC

2.2 V/3 V

0.45

5

5.5 MHz

Internal ADC10_A

oscillator

ADC10DIV = 0, f_ADC10CLK= f_ADC10OSC

2.2 V/3 V

4.2

2.4

4.8

5.4 MHz

(1)

REFON = 0, Internal oscillator, 12 ADC10CLK

cycles, 10-bit mode

3.0

f_ADC10OSC= 4 MHz to 5 MHz

t_CONVERT

Conversion time

µs

External f_ADC10CLKfrom ACLK, MCLK or SMCLK,

(2)

ADC10SSEL ≠ 0

Turn on settling time of

the ADC

(3)

t_ADC10ON

t_Sample

See

100

ns

(4)

R_S= 1000 Ω, R_I= 96 kΩ, C_I= 3.5 pF

1.8 V

3 V

3

1

µs

Sampling time

(4)

R_S= 1000 Ω, R_I= 36 kΩ, C_I= 3.5 pF

(1) The ADC10OSC is sourced directly from MODOSC inside the UCS.

(2) 12 × ADC10DIV × 1/f_ADC10CLK

(3) The condition is that the error in a conversion started after t_ADC10ONis less than ±0.5 LSB. The reference and input signal are already

settled.

(4) Approximately eight Tau (τ) are needed to get an error of less than ±0.5 LSB

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MSP430F530x, MSP430F5310

SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

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MAX UNIT

10-Bit ADC, Linearity Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

1.4 V ≤ (V_eREF+– V_eREF–)min ≤ 1.6 V

1.6 V < (V_eREF+– V_eREF–)min ≤ V_AVCC

V_CC

MIN

TYP

±1.0

LSB

±1.0

Integral

linearity error

E_I

2.2 V/3 V

Differential

linearity error

(V_eREF+– V_eREF–)min ≤ (V_eREF+– V_eREF–),

C_VREF+= 20 pF

E_D

E_O

E_G

E_T

2.2 V/3 V

±1.0 LSB

±2.0 LSB

(V_eREF+– V_eREF–)min ≤ (V_eREF+– V_eREF–),

Internal impedance of source R_S< 100 Ω, C_VeREF+= 20 pF

Offset error

Gain error

(V_eREF+– V_eREF–)min ≤ (V_eREF+– V_eREF–),

C_VREF+= 20 pF

Total unadjusted

error

(V_eREF+– V_eREF–)min ≤ (V_eREF+– V_eREF–),

C_VREF+= 20 pF

±1.0

REF, External Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Positive external

reference voltage input

(2)

V_eREF+

V

_eREF+> V_eREF–

1.4

AV_CC

1.2

V

Negative external

reference voltage input

(3)

V_eREF–

_eREF+> V_eREF–

0

(V_eREF+

–

Differential external

reference voltage input

(4)

_eREF+> V_eREF–

1.4

AV_CC

V_eREF–

)

1.4 V ≤ V_eREF+≤ V_AVCC, V_eREF–= 0 V,

f_ADC10CLK= 5 MHz, ADC10SHTx = 0x0001,

Conversion rate 200 ksps

±8.5

±26

±1

I_VeREF+

I_VeREF–

Static input current

2.2 V/3 V

µA

1.4 V ≤ V_eREF+≤ V_AVCC, V_eREF–= 0 V,

f_ADC10CLK= 5 MHZ, ADC10SHTX = 0x1000,

Conversion rate 20 ksps

Capacitance at V_eREF+/-

terminal

(5)

C_VREF+/-

10

µF

(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, C_I, is also

the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the

recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.

(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced

accuracy requirements.

(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced

accuracy requirements.

(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with

reduced accuracy requirements.

(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VeREF to decouple the dynamic current required for an external

reference source if it is used for the ADC10_A. See also the MSP430x5xx/MSP430x6xx Family User's Guide (SLAU208).

60

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REF, Built-In Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

REFVSEL = {2} for 2.5 V

REFON = 1

3 V

2.51 ±1.5%

1.99 ±1.5%

1.5 ±1.5%

Positive built-in reference

voltage

REFVSEL = {1} for 2.0 V

REFON = 1

V_REF+

3 V

V

REFVSEL = {0} for 1.5 V

REFON = 1

2.2 V/ 3 V

REFVSEL = {0} for 1.5 V

REFVSEL = {1} for 2.0 V

REFVSEL = {2} for 2.5 V

2.2

2.7

AV_CCminimum voltage,

Positive built-in reference

active

AV_CC(min)

f_ADC10CLK= 5.0 MHz

REFON = 1, REFBURST = 0,

REFVSEL = {2} for 2.5 V

3 V

18

24

21

µA

f_ADC10CLK= 5.0 MHz

REFON = 1, REFBURST = 0,

REFVSEL = {1} for 2.0 V

Operating supply current

into AV_CCterminal

I_REF+

15.5

(2)

f_ADC10CLK= 5.0 MHz

REFON = 1, REFBURST = 0,

REFVSEL = {0} for 1.5V

13.5

30

21

50

Temperature coefficient of

built-in reference

I_VREF+= 0 A

REFVSEL = (0, 1, 2}, REFON = 1

ppm/

°C

TC_REF+

I_SENSOR

(3)

2.2 V

3 V

20

22

Operating supply current

REFON = 0, INCH = 0Ah,

ADC10ON = N A, T_A= 30°C

µA

mV

V

(4)

into AV_CCterminal

2.2 V

3 V

770

1.1

1.5

ADC10ON = 1, INCH = 0Ah,

T_A= 30°C

(5)

V_SENSOR

See

2.2 V

3 V

1.06

1.46

1.14

1.54

ADC10ON = 1, INCH = 0Bh,

V_MIDis ~0.5 × V_AVCC

V_MID

t_{SENSOR(sample)}

t_VMID(sample)

AV_CCdivider at channel 11

Sample time required if

ADC10ON = 1, INCH = 0Ah,

Error of conversion result ≤ 1 LSB

30

1

µs

(6)

channel 10 is selected

Sample time required if

channel 11 is selected

ADC10ON = 1, INCH = 0Bh,

Error of conversion result ≤ 1 LSB

(7)

AV_CC= AV_{CC (min)}- AV_CC(max)

T_A= 25 °C

REFVSEL = (0, 1, 2}, REFON = 1

Power supply rejection ratio

(dc)

PSRR_DC

120

µV/V

AV_CC= AV_{CC (min)}- AV_CC(max)

Power supply rejection ratio T_A= 25 °C

PSRR_AC

t_SETTLE

6.4

75

mV/V

(ac)

f = 1 kHz, ΔVpp = 100 mV

REFVSEL = (0, 1, 2}, REFON = 1

Settling time of reference

voltage

AV_CC= AV_{CC (min)}- AV_CC(max)

REFVSEL = (0, 1, 2}, REFON = 0 → 1

µs

(8)

(1) The leakage current is defined in the leakage current table with P6.x/Ax parameter.

(2) The internal reference current is supplied via terminal AV_CC. Consumption is independent of the ADC10ON control bit, unless a

conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.

(3) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C)/(85°C – (–40°C)).

(4) The sensor current I_SENSORis consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is

high). When REFON = 1, I_SENSORis already included in I_REF+

.

(5) The temperature sensor offset can be as much as ±20°C. A single-point calibration is recommended in order to minimize the offset error

of the built-in temperature sensor.

(6) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t_SENSOR(on)

(7) The on-time t_VMID(on)is included in the sampling time t_VMID(sample); no additional on time is needed.

(8) The condition is that the error in a conversion started after t_REFONis less than ±0.5 LSB.

.

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MSP430F530x, MSP430F5310

SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

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Comparator B

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

V_CC

Supply voltage

1.8

3.6

40

50

65

17

0.5

V

1.8 V

2.2 V

Comparator operating

supply current into AV_CC

Excludes reference

resistor ladder.

CBPWRMD = 00, CBON = 1, CBRSx = 00

30

40

.

I_{AVCC_COMP}

3 V

µA

CBPWRMD = 01, CBON = 1, CBRSx = 00

CBPWRMD = 10, CBON = 1, CBRSx = 00

2.2/3 V

10

0.1

CBREFACC = 0, CBREFLx = 01,

CBRSx = 10, REFON = 0, CBON = 0

Quiescent current of

2.2/3 V

10

17

22

µA

V

resistor ladder into AV_CC

Including REF module

current.

.

I_{AVCC_REF}

CBREFACC = 1, CBREFLx = 01,

CBRSx = 10, REFON = 0, CBON = 0

Common mode input

range

V_IC

V_OFFSET

C_IN

0

V_CC-1

CBPWRMD = 00

±20

±10

mV

pF

kΩ

MΩ

ns

Input offset voltage

Input capacitance

CBPWRMD = 01, 10

5

3

ON - switch closed

4

R_SIN

Series input resistance

OFF - switch opened

50

CBPWRMD = 00, CBF = 0

CBPWRMD = 01, CBF = 0

CBPWRMD = 10, CBF = 0

450

600

50

Propagation delay,

response time

t_PD

ns

µs

CBPWRMD = 00, CBON = 1, CBF = 1,

CBFDLY = 00

0.35

0.6

1.0

1.8

0.6

1.0

1.8

3.4

1

1.0

1.8

3.4

6.5

2

µs

CBPWRMD = 00, CBON = 1, CBF = 1,

CBFDLY = 01

Propagation delay with

filter active

t_PD,filter

CBPWRMD = 00, CBON = 1, CBF = 1,

CBFDLY = 10

CBPWRMD = 00, CBON = 1, CBF = 1,

CBFDLY = 11

CBON = 0 to CBON = 1

CBPWRMD = 00, 01

t_{EN_CMP}

Comparator enable time

CBON = 0 to CBON = 1

CBPWRMD = 10

1.5

Resistor reference enable

time

t_{EN_REF}

CBON = 0 to CBON = 1

1

1.5

VIN ×

(n+0.5)

/32

VIN ×

(n+1) (n+1.5)

/32 /32

VIN ×

Reference voltage for a

given tap

VIN = reference into resistor ladder.

n = 0 to 31

V_{CB_REF}

V

62

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Ports PU.0 and PU.1

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

V_LDOO= 3.3 V ± 10%, I_OH= -25 mA.

Refer to Figure 13 for typical

characteristics.

V_OH

V_OL

V_IH

V_IL

High-level output voltage

2.4

V

V_LDOO= 3.3 V ± 10%, I_OL= 25 mA.

Refer to Figure 12 for typical

characteristics.

Low-level output voltage

High-level input voltage

Low-level input voltage

0.4

0.8

V

V_LDOO= 3.3 V ± 10%

Refer to Figure 14 for typical

characteristics.

2.0

V_LDOO= 3.3 V ± 10%

Refer to Figure 14 for typical

characteristics.

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MSP430F530x, MSP430F5310

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TYPICAL LOW-LEVEL OUTPUT CURRENT

vs

LOW-LEVEL OUTPUT VOLTAGE

90

80

70

60

50

40

30

20

10

V_CC= 3.0 V

T_A= 25 ºC

V_CC= 3.0 V

T_A= 85 ºC

V_CC= 1.8 V

T_A= 25 ºC

V_CC= 1.8 V

T_A= 85 ºC

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

1.2

V_OL- Low-Level Output Voltage - V

Figure 12. Ports PU.0, PU.1 Typical Low-Level Output Characteristics

TYPICAL HIGH-LEVEL OUTPUT CURRENT

vs

HIGH-LEVEL OUTPUT VOLTAGE

0

-10

-20

-30

V_CC= 1.8 V

T_A= 85 ºC

-40

-50

V_CC= 3.0 V

-60

T_A= 85 ºC

V_CC= 1.8 V

-70

T_A= 25 ºC

V_CC= 3.0 V

T_A= 25 ºC

-80

-90

0.5

1

1.5

2

2.5

3

V_OH- High-Level Output Voltage - V

Figure 13. Ports PU.0, PU.1 Typical High-Level Output Characteristics

TYPICAL PU.0, PU.1 INPUT THRESHOLD

2.0

T_A= 25 °C, 85 °C

1.8

V_IT+, postive-going input threshold

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

V_IT-, negative-going input threshold

1.8

2.2

2.6

3

3.4

- V

LDOO Supply Voltage, V_LDOO

Figure 14. Ports PU.0, PU.1 Typical Input Threshold Characteristics

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LDO-PWR (LDO Power System)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

V_LAUNCH

V_LDOI

LDO input detection threshold

LDO input voltage

3.75

5.5

V

3.76

V_LDO

LDO output voltage

3.3

±9%

LDOO terminal input voltage with

LDO disabled.

V_{LDO_EXT}

I_LDOO

LDO disabled.

1.8

60

3.6

20

V

Maximum external current from

LDOO terminal.

LDO is on.

mA

µF

nF

LDO current overload detection

I_DET

100

(1)

LDOI terminal recommended

capacitance

C_LDOI

4.7

LDOO terminal recommended

capacitance

C_LDOO

t_ENABLE

220

Within 2%. Recommended

capacitances.

Settling time V_LDO

.

2

ms

(1) A current overload will be detected when the total current supplied from the LDO exceeds this value.

Flash Memory

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEST

CONDITIONS

PARAMETER

MIN

TYP

MAX UNIT

DV_{CC(PGM/ERASE)}Program and erase supply voltage

1.8

3.6

200

5

V

ns

t_READMARGIN

I_PGM

Read access time during margin mode

Supply current from DV_CCduring program

Supply current from DV_CCduring erase

Supply current from DV_CCduring mass erase or bank erase

Cumulative program time

3

2

mA

ms

I_ERASE

6.5

2.5

16

I_MERASE, I_BANK

t_CPT

(1)

See

Program/erase endurance

10⁴

100

64

10⁵

cycles

years

µs

t_Retention

t_Word

Data retention duration

T_J= 25°C

(2)

Word or byte program time

See

85

65

(2)

t_{Block, 0}

Block program time for first byte or word

See

49

µs

Block program time for each additional byte or word, except for last

byte or word

(2)

t_{Block, 1–(N–1)}

t_{Block, N}

See

37

55

23

49

73

32

µs

(2)

Block program time for last byte or word

See

Erase time for segment, mass erase, and bank erase when

available.

(2)

t_Erase

See

ms

(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming

methods: individual word/byte write and block write modes.

(2) These values are hardwired into the flash controller's state machine.

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MSP430F530x, MSP430F5310

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JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEST

CONDITIONS

PARAMETER

MIN

TYP

MAX UNIT

f_SBW

Spy-Bi-Wire input frequency

2.2 V/3 V

0

20 MHz

t_SBW,Low

Spy-Bi-Wire low clock pulse length

2.2 V/3 V

0.025

15

µs

Spy-Bi-Wire enable time (TEST high to acceptance of first clock

edge)

t_{SBW, En}

t_SBW,Rst

2.2 V/3 V

1

µs

(1)

Spy-Bi-Wire return to normal operation time

15

0

100

5

µs

2.2 V

3 V

MHz

(2)

f_TCK

TCK input frequency - 4-wire JTAG

0

10 MHz

80 kΩ

R_internal

Internal pulldown resistance on TEST

2.2 V/3 V

45

60

(1) Tools accessing the Spy-Bi-Wire interface need to wait for the t_SBW,Entime after pulling the TEST/SBWTCK pin high before applying the

first SBWTCK clock edge.

(2) f_TCKmay be restricted to meet the timing requirements of the module selected.

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INPUT/OUTPUT SCHEMATICS

Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger

Pad Logic

P1REN.x

DV_SS

DV_CC

0

1

P1DIR.x

0

1

Direction

0: Input

1: Output

From module

P1OUT.x

0

1

From module

P1.0/TA0CLK/ACLK

P1.1/TA0.0

P1.2/TA0.1

P1.3/TA0.2

P1.4/TA0.3

P1DS.x

0: Low drive

1: High drive

P1SEL.x

P1IN.x

P1.5/TA0.4

P1.6/TA1CLK/CBOUT

P1.7/TA1.0

EN

D

To module

P1IRQ.x

P1IE.x

EN

Q

P1IFG.x

Set

P1SEL.x

P1IES.x

Interrupt

Edge

Select

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Table 46. Port P1 (P1.0 to P1.7) Pin Functions

CONTROL BITS/SIGNALS

PIN NAME (P1.x)

x

FUNCTION

P1DIR.x

P1SEL.x

P1.0/TA0CLK/ACLK

0

P1.0 (I/O)

TA0CLK

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

ACLK

1

P1.1/TA0.0

1

2

3

4

5

6

7

P1.1 (I/O)

TA0.CCI0A

TA0.0

I: 0; O: 1

0

1

P1.2/TA0.1

P1.2 (I/O)

TA0.CCI1A

TA0.1

I: 0; O: 1

0

1

P1.3/TA0.2

P1.3 (I/O)

TA0.CCI2A

TA0.2

I: 0; O: 1

0

1

P1.4/TA0.3

P1.4 (I/O)

TA0.CCI3A

TA0.3

I: 0; O: 1

0

1

P1.5/TA0.4

P1.5 (I/O)

TA0.CCI4A

TA0.4

I: 0; O: 1

0

1

P1.6/TA1CLK/CBOUT

P1.7/TA1.0

P1.6 (I/O)

TA1CLK

I: 0; O: 1

0

CBOUT comparator B

P1.7 (I/O)

TA1.CCI0A

TA1.0

1

I: 0; O: 1

0

1

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Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger

Pad Logic

P2REN.x

DV_SS

DV_CC

0

1

P2DIR.x

0

1

Direction

0: Input

1: Output

From module

P2OUT.x

0

1

From module

P2.0/TA1.1

P2.1/TA1.2

P2.2/TA2CLK/SMCLK

P2.3/TA2.0

P2.4/TA2.1

P2DS.x

0: Low drive

1: High drive

P2SEL.x

P2IN.x

P2.5/TA2.2

P2.6/RTCCLK/DMAE0

P2.7/UB0STE/UCA0CLK

EN

D

To module

P2IE.x

EN

Q

P2IFG.x

Set

P2SEL.x

P2IES.x

Interrupt

Edge

Select

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Table 47. Port P2 (P2.0 to P2.7) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P2.x)

P2.0/TA1.1

x

FUNCTION

P2DIR.x

P2SEL.x

0

P2.0 (I/O)

TA1.CCI1A

TA1.1

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

P2.1/TA1.2

1

2

3

4

5

6

7

P2.1 (I/O)

TA1.CCI2A

TA1.2

I: 0; O: 1

0

1

P2.2/TA2CLK/SMCLK

P2.3/TA2.0

P2.2 (I/O)

TA2CLK

I: 0; O: 1

0

SMCLK

1

P2.3 (I/O)

TA2.CCI0A

TA2.0

I: 0; O: 1

0

1

P2.4/TA2.1

P2.4 (I/O)

TA2.CCI1A

TA2.1

I: 0; O: 1

0

1

P2.5/TA2.2

P2.5 (I/O)

TA2.CCI2A

TA2.2

I: 0; O: 1

0

1

P2.6/RTCCLK/DMAE0

P2.6 (I/O)

DMAE0

I: 0; O: 1

0

RTCCLK

P2.7 (I/O)

UCB0STE/UCA0CLK^{(2) (3)}

1

I: 0; O: 1

X

P2.7/UCB0STE/UCA0CLK

(1) X = Don't care

(2) The pin direction is controlled by the USCI module.

(3) UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI A0/B0 is forced

to 3-wire SPI mode if 4-wire SPI mode is selected.

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Port P3, P3.0 to P3.4, Input/Output With Schmitt Trigger

Pad Logic

P3REN.x

DV_SS

DV_CC

0

1

P3DIR.x

0

1

Direction

0: Input

1: Output

From module

P3OUT.x

0

1

From module

P3.0/UCB0SIMO/UCB0SDA

P3.1/UCB0SOMI/UCB0SCL

P3.2/UCB0CLK/UCA0STE

P3.3/UCA0TXD/UCA0SIMO

P3.4/UCA0RXD/UCA0SOMI

P3DS.x

0: Low drive

1: High drive

P3SEL.x

P3IN.x

EN

D

To module

Table 48. Port P3 (P3.0 to P3.7) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P3.x)

x

FUNCTION

P3DIR.x

P3SEL.x

P3.0/UCB0SIMO/UCB0SDA

0

1

2

3

4

P3.0 (I/O)

UCB0SIMO/UCB0SDA^{(2) (3)}

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

X

P3.1/UCB0SOMI/UCB0SCL

P3.2/UCB0CLK/UCA0STE

P3.3/UCA0TXD/UCA0SIMO

P3.4/UCA0RXD/UCA0SOMI

P3.1 (I/O)

I: 0; O: 1

UCB0SOMI/UCB0SCL^{(2) (3)}

P3.2 (I/O)

UCB0CLK/UCA0STE^{(2) (4)}

X

I: 0; O: 1

X

I: 0; O: 1

X

P3.3 (I/O)

UCA0TXD/UCA0SIMO⁽²⁾

P3.4 (I/O)

UCA0RXD/UCA0SOMI⁽²⁾

I: 0; O: 1

X

(1) X = Don't care

(2) The pin direction is controlled by the USCI module.

(3) If the I2C functionality is selected, the output drives only the logical 0 to V_SSlevel.

(4) UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI A0/B0 is forced

to 3-wire SPI mode if 4-wire SPI mode is selected.

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MSP430F530x, MSP430F5310

SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

www.ti.com

Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger

Pad Logic

P4REN.x

DV_SS

DV_CC

0

1

P4DIR.x

0

1

Direction

0: Input

1: Output

from Port Mapping Control

P4OUT.x

0

1

from Port Mapping Control

P4.0/P4MAP0

P4.1/P4MAP1

P4.2/P4MAP2

P4.3/P4MAP3

P4.4/P4MAP4

P4.5/P4MAP5

P4.6/P4MAP6

P4.7/P4MAP7

P4DS.x

0: Low drive

1: High drive

P4SEL.x

P4IN.x

EN

D

to Port Mapping Control

72

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Table 49. Port P4 (P4.0 to P4.7) Pin Functions

CONTROL BITS/SIGNALS

PIN NAME (P4.x)

x

FUNCTION

P4DIR.x⁽¹⁾

P4SEL.x

P4MAPx

P4.0/P4MAP0

P4.1/P4MAP1

P4.2/P4MAP2

P4.3/P4MAP3

P4.4/P4MAP4

P4.5/P4MAP5

P4.6/P4MAP6

P4.7/P4MAP7

0

P4.0 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

≤ 30

X

Mapped secondary digital function

P4.1 (I/O)

X

1

2

3

4

5

6

7

I: 0; O: 1

Mapped secondary digital function

P4.2 (I/O)

X

≤ 30

X

I: 0; O: 1

Mapped secondary digital function

P4.3 (I/O)

X

≤ 30

X

I: 0; O: 1

Mapped secondary digital function

P4.4 (I/O)

X

≤ 30

X

I: 0; O: 1

Mapped secondary digital function

P4.5 (I/O)

X

≤ 30

X

I: 0; O: 1

Mapped secondary digital function

P4.6 (I/O)

X

I: 0; O: 1

X

≤ 30

X

Mapped secondary digital function

P4.7 (I/O)

≤ 30

X

I: 0; O: 1

X

Mapped secondary digital function

≤ 30

(1) The direction of some mapped secondary functions are controlled directly by the module. See Table 9 for specific direction control

information of mapped secondary functions.

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MSP430F530x, MSP430F5310

SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

www.ti.com

Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger

Pad Logic

to/from Reference

to ADC10

INCHx = x

P5REN.x

DV_SS

DV_CC

0

1

P5DIR.x

0

1

P5OUT.x

0

1

From module

P5.0/(A8/VeREF+)

P5.1/(A9/VeREF–)

P5DS.x

0: Low drive

1: High drive

P5SEL.x

P5IN.x

Bus

Keeper

EN

D

To module

Table 50. Port P5 (P5.0 and P5.1) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P5.x)

x

FUNCTION

P5DIR.x

I: 0; O: 1

X

P5SEL.x

P5.0/A8/VeREF+⁽²⁾

0

P5.0 (I/O)⁽³⁾

A8/VeREF+⁽⁴⁾

P5.1 (I/O)⁽³⁾

A9/VeREF–⁽⁶⁾

0

1

0

1

P5.1/A9/VeREF–⁽⁵⁾

1

I: 0; O: 1

X

(1) X = Don't care

(2) VeREF+ available on devices with ADC10_A.

(3) Default condition

(4) Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC10_A when available.

(5) VeREF- available on devices with ADC10_A.

(6) Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC10_A when available.

74

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SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

Port P5, P5.2, Input/Output With Schmitt Trigger

Pad Logic

To XT2

P5REN.2

DV_SS

DV_CC

0

1

P5DIR.2

0

1

P5OUT.2

0

1

Module X OUT

P5.2/XT2IN

P5DS.2

0: Low drive

1: High drive

P5SEL.2

P5IN.2

Bus

Keeper

EN

D

Module X IN

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MSP430F530x, MSP430F5310

SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

www.ti.com

Port P5, P5.3, Input/Output With Schmitt Trigger

Pad Logic

To XT2

P5REN.3

DV_SS

DV_CC

0

1

P5DIR.3

0

1

P5OUT.3

0

1

Module X OUT

P5.3/XT2OUT

P5DS.3

0: Low drive

1: High drive

P5SEL.3

P5IN.3

Bus

Keeper

EN

D

Module X IN

Table 51. Port P5 (P5.2, P5.3) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P5.x)

x

FUNCTION

P5DIR.x

P5SEL.2

P5SEL.3

XT2BYPASS

P5.2/XT2IN

2

P5.2 (I/O)

I: 0; O: 1

0

1

0

1

X

0

1

X

0

1

XT2IN crystal mode⁽²⁾

XT2IN bypass mode⁽²⁾

P5.3 (I/O)

XT2OUT crystal mode⁽³⁾

P5.3 (I/O)⁽³⁾

X

P5.3/XT2OUT

3

I: 0; O: 1

X

(1) X = Don't care

(2) Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal

mode or bypass mode.

(3) Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as

general-purpose I/O.

76

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SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

Port P5, P5.4 and P5.5 Input/Output With Schmitt Trigger

Pad Logic

to XT1

P5REN.4

DV_SS

DV_CC

0

1

P5DIR.4

0

1

P5OUT.4

0

1

Module X OUT

P5.4/XIN

P5DS.4

0: Low drive

1: High drive

P5SEL.4

P5IN.4

Bus

Keeper

EN

D

Module X IN

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MSP430F530x, MSP430F5310

SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

www.ti.com

Pad Logic

to XT1

P5REN.5

DV_SS

DV_CC

0

1

P5DIR.5

0

1

P5OUT.5

0

1

Module X OUT

P5.5/XOUT

P5DS.5

0: Low drive

1: High drive

P5SEL.5

XT1BYPASS

P5IN.5

Bus

Keeper

EN

D

Module X IN

Table 52. Port P5 (P5.4 and P5.5) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P7.x)

P5.4/XIN

x

FUNCTION

P5DIR.x

P5SEL.4

P5SEL.5

XT1BYPASS

4

P5.4 (I/O)

I: 0; O: 1

0

1

0

1

X

0

1

X

0

1

XIN crystal mode⁽²⁾

XIN bypass mode⁽²⁾

P5.5 (I/O)

XOUT crystal mode⁽³⁾

P5.5 (I/O)⁽³⁾

X

P5.5/XOUT

5

I: 0; O: 1

X

(1) X = Don't care

(2) Setting P5SEL.4 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P5.4 is configured for crystal

mode or bypass mode.

(3) Setting P5SEL.4 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.5 can be used as

general-purpose I/O.

78

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SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger

Pad Logic

to ADC10

INCHx = x

to Comparator_B

from Comparator_B

CBPD.x

P6REN.x

DVSS

DVCC

0

1

P6DIR.x

0

1

Direction

0: Input

1: Output

P6OUT.x

0

1

From module

P6.0/CB0/(A0)

P6.1/CB1/(A1)

P6.2/CB2/(A2)

P6.3/CB3/(A3)

P6.4/CB4/(A4)

P6.5/CB5/(A5)

P6.6/CB6/(A6)

P6.7/CB7/(A7)

P6DS.x

0: Low drive

1: High drive

P6SEL.x

P6IN.x

Bus

Keeper

EN

D

To module

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MSP430F530x, MSP430F5310

SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

www.ti.com

Table 53. Port P6 (P6.0 to P6.7) Pin Functions

CONTROL BITS/SIGNALS

PIN NAME (P6.x)

P6.0/CB0/(A0)

x

FUNCTION

P6DIR.x

P6SEL.x

CBPD

0

P6.0 (I/O)

I: 0; O: 1

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

A0 (only on devices with ADC)

CB0⁽¹⁾

X

1

X

P6.1/CB1/(A1)

P6.2/CB2/(A2)

P6.3/CB3/(A3)

P6.4/CB4/(A4)

P6.5/CB5/(A5)

P6.6/CB6/(A6)

P6.7/CB7/(A7)

1

2

3

4

5

6

7

P6.1 (I/O)

I: 0; O: 1

0

A1 (only on devices with ADC)

CB1⁽¹⁾

X

1

X

P6.2 (I/O)

I: 0; O: 1

0

A2 (only on devices with ADC)

CB2⁽¹⁾

X

1

X

P6.3 (I/O)

I: 0; O: 1

0

A3 (only on devices with ADC)

CB3⁽¹⁾

X

1

X

P6.4 (I/O)

I: 0; O: 1

0

A4 (only on devices with ADC)

CB4⁽¹⁾

X

1

X

P6.5 (I/O)

I: 0; O: 1

0

A5 (only on devices with ADC)

CB5⁽¹⁾

X

1

X

P6.6 (I/O)

I: 0; O: 1

0

A6 (only on devices with ADC)

CB6⁽¹⁾

X

1

X

P6.7 (I/O)

I: 0; O: 1

0

A7 (only on devices with ADC)

CB7⁽¹⁾

X

1

(1) Setting the CBPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input

buffer for that pin, regardless of the state of the associated CBPD.x bit.

80

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SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

Port PU.0, PU.1 Ports

LDOO

VSSU

Pad Logic

PUOPE

PU.0

PUOUT0

PUIN0

PUIPE

PUIN1

PUOUT1

PU.1

Table 54. Port PU.0, PU.1 Output Functions⁽¹⁾

CONTROL BITS

PIN NAME

PUOPE

PUOUT1

PUOUT0

PU.1/DM

Output disabled

Output low

PU.0/DP

Output disabled

Output low

0

1

X

0

1

X

0

1

0

1

Output low

Output high

Output low

Output high

(1) PU.1 and PU.0 inputs and outputs are supplied from LDOO. LDOO can be generated by the device

using the integrated 3.3-V LDO when enabled. LDOO can also be supplied externally when the 3.3-V

LDO is not being used and is disabled.

Table 55. Port PU.0, PU.1 Input Functions⁽¹⁾

CONTROL BITS

PIN NAME

PUIPE

PU.1/DM

PU.0/DP

0

1

Input disabled

Input enabled

Input disabled

Input enabled

(1) PU.1 and PU.0 inputs and outputs are supplied from LDOO. LDOO

can be generated by the device using the integrated 3.3-V LDO

when enabled. LDOO can also be supplied externally when the

3.3-V LDO is not being used and is disabled.

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MSP430F530x, MSP430F5310

SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

www.ti.com

Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output

Pad Logic

PJREN.0

0

1

DV_SS

DV_CC

1

PJDIR.0

DVCC

0

1

PJOUT.0

0

1

From JTAG

PJ.0/TDO

PJDS.0

0: Low drive

1: High drive

From JTAG

PJIN.0

EN

D

Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output

Pad Logic

PJREN.x

0

1

DV_SS

DV_CC

1

PJDIR.x

DVSS

0

1

PJOUT.x

0

1

From JTAG

PJ.1/TDI/TCLK

PJ.2/TMS

PJ.3/TCK

PJDS.x

0: Low drive

1: High drive

From JTAG

PJIN.x

EN

D

To JTAG

82

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SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

Table 56. Port PJ (PJ.0 to PJ.3) Pin Functions

CONTROL BITS/

SIGNALS⁽¹⁾

PIN NAME (PJ.x)

x

FUNCTION

PJDIR.x

PJ.0/TDO

0

PJ.0 (I/O)⁽²⁾

TDO⁽³⁾

I: 0; O: 1

X

PJ.1/TDI/TCLK

PJ.2/TMS

1

2

3

PJ.1 (I/O)⁽²⁾

TDI/TCLK^{(3) (4)}

PJ.2 (I/O)⁽²⁾

TMS^{(3) (4)}

PJ.3 (I/O)⁽²⁾

TCK^{(3) (4)}

I: 0; O: 1

X

I: 0; O: 1

X

PJ.3/TCK

I: 0; O: 1

X

(1) X = Don't care

(2) Default condition

(3) The pin direction is controlled by the JTAG module.

(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.

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MSP430F530x, MSP430F5310

SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

www.ti.com

DEVICE DESCRIPTORS

Table 57 list the complete contents of the device descriptor tag-length-value (TLV) structure for each device type.

(1)

Table 57. Device Descriptor Table

'F5308

RGC

'F5308

RGZ

'F5309

RGC

'F5309

RGZ

'F5310

RGC

'F5310

RGZ

'F5304

SIZE

(bytes)

DESCRIPTION

ADDRESS

VALUE

06h

VALUE

06h

VALUE

06h

VALUE

06h

VALUE

06h

VALUE

06h

VALUE

06h

Info Block

Info length

CRC length

01A00h

01A01h

01A02h

01A04h

01A05h

01A06h

01A07h

01A08h

01A09h

01A0Ah

01A0Eh

01A10h

01A12h

1

2

1

4

2

06h

CRC value

per unit

12h

per unit

13h

per unit

13h

per unit

14h

per unit

14h

per unit

15h

per unit

15h

Device ID

81h

Hardware revision

Firmware revision

Die Record Tag

Die Record length

Lot/Wafer ID

Die X position

Die Y position

Test results

per unit

08h

per unit

08h

per unit

08h

per unit

08h

per unit

08h

per unit

08h

per unit

08h

Die Record

0Ah

per unit

ADC10

Calibration

ADC10 Calibration Tag

01A14h

1

13h

ADC10 Calibration length

ADC Gain Factor

ADC Offset

01A15h

01A16h

01A18h

1

2

10h

per unit

ADC 1.5-V Reference

Temp. Sensor 30°C

01A1Ah

01A1Ch

01A1Eh

01A20h

01A22h

01A24h

2

per unit

ADC 1.5-V Reference

Temp. Sensor 85°C

ADC 2.0-V Reference

Temp. Sensor 30°C

ADC 2.0-V Reference

Temp. Sensor 85°C

ADC 2.5-V Reference

Temp. Sensor 30°C

ADC 2.5-V Reference

Temp. Sensor 85°C

REF

Calibration

REF Calibration Tag

01A26h

01A27h

01A28h

1

2

12h

06h

12h

06h

12h

06h

12h

06h

12h

06h

12h

06h

12h

06h

REF Calibration length

REF 1.5-V Reference

Factor

per unit

REF 2.0-V Reference

Factor

01A2Ah

01A2Ch

01A2Eh

01A2Fh

2

1

2

per unit

02h

per unit

02h

per unit

02h

per unit

02h

per unit

02h

per unit

02h

per unit

02h

REF 2.5-V Reference

Factor

Peripheral

Descriptor

Peripheral Descriptor Tag

Peripheral Descriptor

Length

5Ch

60h

61h

60h

08h

8Ah

08h

8Ah

08h

8Ah

08h

8Ah

08h

8Ah

08h

8Ah

08h

8Ah

Memory 1

Memory 2

Memory 3

Memory 4

0Ch

86h

0Ch

86h

0Ch

86h

0Ch

86h

0Ch

86h

0Ch

86h

0Ch

86h

0Eh

2Dh

0Eh

2Dh

0Eh

2Dh

0Eh

2Dh

0Eh

2Dh

0Eh

2Dh

0Eh

2Dh

2Ah

70h

2Ah

60h

2Ah

60h

2Ah

50h

2Ah

50h

2Ah

40h

2Ah

40h

(1) N/A = Not applicable

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Table 57. Device Descriptor Table ⁽¹⁾(continued)

'F5308

RGC

'F5308

RGZ

'F5309

RGC

'F5309

RGZ

'F5310

RGC

'F5310

RGZ

'F5304

VALUE

8Eh

SIZE

(bytes)

DESCRIPTION

ADDRESS

VALUE

91h

8Eh

91h

8Eh

Memory 5

2/1

90h

92h

delimiter

1

00h

1Eh

00h

20h

00h

20h

00h

20h

00h

20h

00h

20h

00h

20h

Peripheral count

00h

23h

00h

23h

00h

23h

00h

23h

00h

23h

00h

23h

00h

23h

MSP430CPUXV2

JTAG

2

00h

09h

00h

09h

00h

09h

00h

09h

00h

09h

00h

09h

00h

09h

00h

0Fh

00h

0Fh

00h

0Fh

00h

0Fh

00h

0Fh

00h

0Fh

00h

0Fh

SBW

00h

03h

00h

03h

00h

03h

00h

03h

00h

03h

00h

03h

00h

03h

EEM-S

TI BSL

SFR

00h

FCh

00h

FCh

00h

FCh

00h

FCh

00h

FCh

00h

FCh

00h

FCh

10h

41h

10h

41h

10h

41h

10h

41h

10h

41h

10h

41h

10h

41h

02h

30h

02h

30h

02h

30h

02h

30h

02h

30h

02h

30h

02h

30h

PMM

02h

38h

02h

38h

02h

38h

02h

38h

02h

38h

02h

38h

02h

38h

FCTL

01h

3Ch

01h

3Ch

01h

3Ch

01h

3Ch

01h

3Ch

01h

3Ch

01h

3Ch

CRC16

CRC16_RB

RAMCTL

WDT_A

UCS

00h

3Dh

00h

3Dh

00h

3Dh

00h

3Dh

00h

3Dh

00h

3Dh

00h

3Dh

00h

44h

00h

44h

00h

44h

00h

44h

00h

44h

00h

44h

00h

44h

00h

40h

00h

40h

00h

40h

00h

40h

00h

40h

00h

40h

00h

40h

01h

48h

01h

48h

01h

48h

01h

48h

01h

48h

01h

48h

01h

48h

02h

42h

02h

42h

02h

42h

02h

42h

02h

42h

02h

42h

02h

42h

SYS

03h

A0h

03h

A0h

03h

A0h

03h

A0h

03h

A0h

03h

A0h

03h

A0h

REF

01h

10h

01h

10h

01h

10h

01h

10h

01h

10h

01h

10h

01h

10h

Port Mapping

Port 1/2

Port 3/4

Port 5/6

JTAG

04h

51h

04h

51h

04h

51h

04h

51h

04h

51h

04h

51h

04h

51h

02h

52h

02h

52h

02h

52h

02h

52h

02h

52h

02h

52h

02h

52h

02h

53h

02h

53h

02h

53h

02h

53h

02h

53h

02h

53h

02h

53h

0Eh

5Fh

0Eh

5Fh

0Eh

5Fh

0Eh

5Fh

0Eh

5Fh

0Eh

5Fh

0Eh

5Fh

02h

62h

02h

62h

02h

62h

02h

62h

02h

62h

02h

62h

02h

62h

TA0

04h

61h

04h

61h

04h

61h

04h

61h

04h

61h

04h

61h

04h

61h

TA1

04h

67h

04h

67h

04h

67h

04h

67h

04h

67h

04h

67h

04h

67h

TB0

04h

61h

04h

61h

04h

61h

04h

61h

04h

61h

04h

61h

04h

61h

TA2

0Ah

68h

0Ah

68h

0Ah

68h

0Ah

68h

0Ah

68h

0Ah

68h

0Ah

68h

RTC

02h

85h

02h

85h

02h

85h

02h

85h

02h

85h

02h

85h

02h

85h

MPY32

DMA-3

USCI_A/B

04h

47h

04h

47h

04h

47h

04h

47h

04h

47h

04h

47h

04h

47h

10h

90h

0Ch

90h

0Ch

90h

0Ch

90h

0Ch

90h

0Ch

90h

0Ch

90h

Submit Documentation Feedback

85

MSP430F530x, MSP430F5310

SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

www.ti.com

Table 57. Device Descriptor Table ⁽¹⁾(continued)

'F5308

RGC

'F5308

RGZ

'F5309

RGC

'F5309

RGZ

'F5310

RGC

'F5310

RGZ

'F5304

VALUE

N/A

SIZE

(bytes)

DESCRIPTION

ADDRESS

VALUE

04h

90h

04h

90h

04h

90h

04h

90h

04h

90h

04h

90h

USCI_A/B

ADC10_A

COMP_B

LDO

2

14h

D3h

14h

D3h

14h

D3h

14h

D3h

14h

D3h

14h

D3h

14h

D3h

18h

A8h

18h

A8h

18h

A8h

18h

A8h

18h

A8h

18h

A8h

N/A

1Ch

5Ch

04h

5Ch

04h

5Ch

04h

5Ch

04h

5Ch

04h

5Ch

04h

5Ch

Interrupts

COMP_B

TB0.CCIFG0

TB0.CCIFG1..6

WDTIFG

1

01h

64h

65h

40h

01h

D0h

60h

61h

5Ch

46h

62h

63h

50h

92h

93h

66h

67h

51h

68h

00h

A8h

64h

65h

40h

90h

91h

D0h

60h

61h

5Ch

46h

62h

63h

50h

92h

93h

66h

67h

51h

68h

00h

A8h

64h

65h

40h

90h

91h

D0h

60h

61h

5Ch

46h

62h

63h

50h

92h

93h

66h

67h

51h

68h

00h

A8h

64h

65h

40h

90h

91h

D0h

60h

61h

5Ch

46h

62h

63h

50h

92h

93h

66h

67h

51h

68h

00h

A8h

64h

65h

40h

90h

91h

D0h

60h

61h

5Ch

46h

62h

63h

50h

92h

93h

66h

67h

51h

68h

00h

A8h

64h

65h

40h

90h

91h

D0h

60h

61h

5Ch

46h

62h

63h

50h

92h

93h

66h

67h

51h

68h

00h

A8h

64h

65h

40h

90h

91h

D0h

60h

61h

5Ch

46h

62h

63h

50h

92h

93h

66h

67h

51h

68h

00h

USCI_A0

USCI_B0

ADC10_A

TA0.CCIFG0

TA0.CCIFG1..4

LDO-PWR

DMA

TA1.CCIFG0

TA1.CCIFG1..2

P1

USCI_A1

USCI_B1

TA1.CCIFG0

TA1.CCIFG1..2

P2

RTC_A

delimiter

86

Submit Documentation Feedback

MSP430F530x, MSP430F5310

www.ti.com

SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011

REVISION HISTORY

REVISION

COMMENTS

SLAS677

Product Preview release

Production Data release

Released BGA package

SLAS677A

Corrected V_{CB_REF}min and max values by swapping them as they were backward

Added I_{USB_LDO}and I_{VBUS_DETECT}to USB-PWR table

SLAS677B

Added QFN thermal pad connection to pinout drawing and terminal function table

Added LDO and Port U description

Updated pin diagrams to show A8 and A9 muxed with P5.0/VeREF+ and P5.1/VeREF- pins, respectively

Updated t_{EN_REF}typ value; changed from 0.3 to 1

Submit Documentation Feedback

87

MECHANICAL DATA

MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996

PT (S-PQFP-G48)

PLASTIC QUAD FLATPACK

0,27

0,17

M

0,08

0,50

36

25

37

24

48

13

0,13 NOM

1

12

5,50 TYP

7,20

SQ

6,80

Gage Plane

9,20

SQ

8,80

0,25

0,05 MIN

0°–7°

1,45

1,35

0,75

0,45

Seating Plane

0,10

1,60 MAX

4040052/C 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

D. This may also be a thermally enhanced plastic package with leads conected to the die pads.

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型号：	MSP430F5309IZXH
厂家：	TEXAS INSTRUMENTS
描述：	具有 24KB 闪存、6KB SRAM、10 位 ADC、比较器、DMA、UART/SPI/I2C 和硬件乘法器的 25MHz MCU \| ZXH \| 80 \| -40 to 85 静态存储器比较器闪存
文件：	总99页 (文件大小：1242K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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