MSP430F5326IZXHR_技术文档

MSP430F5329, MSP430F5328, MSP430F5327, MSP430F5326, MSP430F5325, MSP430F5324

MSP430F5329, MSP430F5328, MSP430F5327, _SM_LS_ASP₆4₇3_8G0F_–5_A3_U2_G6_U,_SM_TS₂₀P₁4₀3_–0_RF_E5_V3_IS2_E5_D, _SM_ES_PTP_E4_M3_B0_EF_R5₂3₀2₂4₀

SLAS678G – AUGUST 2010 – REVISED SEPTEMBER 2020

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MSP430F532x Mixed-Signal Microcontrollers

– 32-kHz watch crystals (XT1)

– High-frequency crystals up to 32 MHz (XT2)

16-bit timer TA0, Timer_A with five capture/

compare registers

16-bit timer TA1, Timer_A with three capture/

compare registers

16-bit timer TA2, Timer_A with three capture/

compare registers

16-bit timer TB0, Timer_B with seven capture/

compare shadow registers

Two universal serial communication interfaces

(USCIs)

– USCI_A0 and USCI_A1 each support:

1 Features

•

Low supply voltage range:

•

3.6 V down to 1.8 V

•

Ultra-low power consumption

– Active mode (AM):

all system clocks active

290 µA/MHz at 8 MHz, 3 V, flash program

execution (typical)

150 µA/MHz at 8 MHz, 3 V, RAM program

execution (typical)

– Standby mode (LPM3):

real-time clock (RTC) with crystal, watchdog,

and supply supervisor operational, full RAM

retention, fast wakeup:

1.9 µA at 2.2 V, 2.1 µA at 3 V (typical)

low-power oscillator (VLO), general-purpose

counter, watchdog, and supply supervisor

operational, full RAM retention, fast wakeup:

1.4 µA at 3 V (typical)

•

Enhanced UART supports automatic baud-

rate detection

•

IrDA encoder and decoder

Synchronous SPI

– USCI_B0 and USCI_B1 each support:

•

I²C

– Off mode (LPM4):

Synchronous SPI

full RAM retention, supply supervisor

operational, fast wakeup:

1.1 µA at 3 V (typical)

•

Integrated 3.3-V power system

12-bit analog-to-digital converter (ADC) with

internal reference, sample-and-hold, and autoscan

feature

– Shutdown mode (LPM4.5):

0.18 µA at 3 V (typical)

Wake up from standby mode in 3.5 µs (typical)

16-bit RISC architecture, extended memory, up to

25-MHz system clock

Flexible power-management system

– Fully integrated LDO with programmable

regulated core supply voltage

– Supply voltage supervision, monitoring, and

brownout

•

Comparator

•

Hardware multiplier supports 32-bit operations

Serial onboard programming, no external

programming voltage needed

3-channel internal DMA

Basic timer with RTC feature

Device Comparison summarizes the available

family members

•

2 Applications

•

Unified clock system

– FLL control loop for frequency stabilization

– Low-power low-frequency internal clock source

(VLO)

•

Analog and Digital Sensor Systems

Data Loggers

General-Purpose Applications

– Low-frequency trimmed internal reference

source (REFO)

3 Description

The TI MSP430^™family of ultra-low-power microcontrollers consists of several devices featuring different sets of

peripherals targeted for various applications. The architecture, combined with extensive low-power modes is

optimized to achieve extended battery life in portable measurement applications. The device features a powerful

16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The

digitally controlled oscillator (DCO) allows the devices to wake up from low-power modes to active mode in

3.5 µs (typical).

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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MSP430F5324

MSP430F5329, MSP430F5328, MSP430F5327, MSP430F5326, MSP430F5325, MSP430F5324

SLAS678G – AUGUST 2010 – REVISED SEPTEMBER 2020

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The MSP430F5329, MSP430F5327, and MSP430F5325 are microcontroller configurations with an integrated

3.3-V LDO, four 16-bit timers, a high-performance 12-bit ADC, two USCIs, a hardware multiplier, DMA, an RTC

module with alarm capabilities, and 63 I/O pins.

The MSP430F5328, MSP430F5326, and MSP430F5324 include all of these peripherals but have 47 I/O pins.

Typical applications include analog and digital sensor systems, data loggers, and various general-purpose

applications.

For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's Guide.

Device Information

PART NUMBER⁽¹⁾

MSP430F5329IPN

PACKAGE

BODY SIZE⁽²⁾

12 mm × 12 mm

9 mm × 9 mm

5 mm × 5 mm

LQFP (80)

MSP430F5328IRGC

MSP430F5328IZXH

MSP430F5328IZQE⁽³⁾

VQFN (64)

nFBGA (80)

MicroStar Junior^™BGA (80)

(1) For the most current part, package, and ordering information, see the Package Option Addendum

in Section 11, or see the TI website at www.ti.com.

(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the

Mechanical Data in Section 11.

(3) All orderable part numbers in the ZQE (MicroStar Junior BGA) package have been changed to a

status of Last Time Buy. Visit the Product life cycle page for details on this status.

2

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SLAS678G – AUGUST 2010 – REVISED SEPTEMBER 2020

4 Functional Block Diagrams

Figure 4-1 shows the functional block diagram for the F5329, F5327, and F5325 devices in the PN package.

PA

PB

PC

PD

LDOO LDOI

XIN XOUT

DVCC DVSS VCORE AVCC AVSS

RST/NMI

PU.0,

PU.1

P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x

XT2IN

SYS

ACLK

Power

Management

I/O Ports

P1, P2

2×8 I/Os

Interrupt

and Wakeup

I/O Ports

P3, P4

2×8 I/Os

I/O Ports

P5, P6

2×8 I/Os

I/O Ports

P7, P8

1×8 I/Os

1×3 I/Os

Unified

Clock

System

Watchdog

128KB

96KB

64KB

32KB

8KB+2KB

6KB+2KB

4KB+2KB

XT2OUT

PU Port

LDO

SMCLK

Port Map

Control

(P4)

LDO

SVM, SVS

Brownout

MCLK

PA

1×16 I/Os

PB

1×16 I/Os

PC

1×16 I/Os

PD

1×11 I/Os

Flash

RAM

MAB

MDB

CPUXV2

and

Working

Registers

DMA

3 Channel

EEM

(L: 8+2)

ADC12_A

USCI0,1

TA2

TB0

12 Bit

200 ksps

TA0

TA1

USCI_Ax:

UART,

IrDA, SPI

JTAG,

SBW

Interface

REF

COMP_B

RTC_A

MPY32

CRC16

Timer_A

5 CC

Registers

Timer_A

3 CC

Registers

Timer_A

3 CC

Registers

Timer_B

7 CC

Registers

12 Channels

16 Channels

(14 ext, 2 int)

Autoscan

USCI_Bx:

SPI, I²C

Functional Block Diagram – MSP430F5329IPN, MSP430F5327IPN, MSP430F5325IPN

Figure 4-1 shows the functional block diagram for the F5328, F5326, and F5324 devices in the ZXH, ZQE, or

RGC package.

PA

PB

PC

LDOO LDOI

XIN XOUT

DVCC DVSS VCORE AVCC AVSS

RST/NMI

PU.0,

PU.1

P1.x P2.x P3.x P4.x P5.x P6.x

XT2IN

SYS

ACLK

Power

Management

I/O Ports

P1, P2

2×8 I/Os

Interrupt

& Wakeup

I/O Ports

P3, P4

1×5 I/Os

1×8 I/Os

I/O Ports

P5, P6

1×6 I/Os

1×8 I/Os

Unified

Clock

System

Watchdog

128KB

96KB

64KB

32KB

8KB+2KB

6KB+2KB

4KB+2KB

XT2OUT

PU Port

LDO

SMCLK

Port Map

Control

(P4)

LDO

SVM/SVS

Brownout

MCLK

PA

1×16 I/Os

PB

1×13 I/Os

PC

1×14 I/Os

Flash

RAM

MAB

MDB

CPUXV2

and

Working

Registers

DMA

3 Channel

EEM

(L: 8+2)

ADC12_A

USCI0,1

TA2

TB0

12 Bit

200 ksps

TA0

TA1

USCI_Ax:

UART,

IrDA, SPI

JTAG,

SBW

Interface

REF

COMP_B

RTC_A

MPY32

CRC16

Timer_A

5 CC

Registers

Timer_A

3 CC

Registers

Timer_A

3 CC

Registers

Timer_B

7 CC

Registers

8 Channels

12 Channels

(10 ext, 2 int)

Autoscan

USCI_Bx:

SPI, I²C

Functional Block Diagram – MSP430F5328IRGC, MSP430F5326IRGC, MSP430F5324IRGC,

MSP430F5328IZXH, MSP430F5326IZXH, MSP430F5324IZXH, MSP430F5328IZQE, MSP430F5326IZQE,

MSP430F5324IZQE

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MSP430F5329, MSP430F5328, MSP430F5327, MSP430F5326, MSP430F5325, MSP430F5324

SLAS678G – AUGUST 2010 – REVISED SEPTEMBER 2020

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Functional Block Diagrams............................................ 3

5 Revision History.............................................................. 5

6 Device Comparison.........................................................7

6.1 Related Products........................................................ 7

7 Terminal Configuration and Functions..........................8

7.1 Pin Diagrams.............................................................. 8

7.2 Signal Descriptions................................................... 11

8 Specifications................................................................ 17

8.1 Absolute Maximum Ratings...................................... 17

8.2 ESD Ratings............................................................. 17

8.3 Recommended Operating Conditions.......................18

8.4 Active Mode Supply Current Into V_CCExcluding

8.23 PMM, SVM High Side............................................. 32

8.24 PMM, SVS Low Side...............................................33

8.25 PMM, SVM Low Side..............................................33

8.26 Wake-up Times From Low-Power Modes and

Reset...........................................................................34

8.27 Timer_A...................................................................34

8.28 Timer_B...................................................................34

8.29 USCI (UART Mode) Clock Frequency.................... 35

8.30 USCI (UART Mode)................................................ 35

8.31 USCI (SPI Master Mode) Clock Frequency............ 35

8.32 USCI (SPI Master Mode)........................................ 35

8.33 USCI (SPI Slave Mode).......................................... 37

8.34 USCI (I²C Mode).....................................................39

8.35 12-Bit ADC, Power Supply and Input Range

Conditions................................................................... 40

8.36 12-Bit ADC, Timing Parameters..............................40

8.37 12-Bit ADC, Linearity Parameters Using an

External Current.......................................................... 18

8.5 Low-Power Mode Supply Currents (Into V_CC

)

Excluding External Current..........................................20

8.6 Thermal Resistance Characteristics......................... 21

8.7 Schmitt-Trigger Inputs – General-Purpose I/O

(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to

P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7,

External Reference Voltage or AVCC as

Reference Voltage.......................................................41

8.38 12-Bit ADC, Linearity Parameters Using the

Internal Reference Voltage..........................................41

8.39 12-Bit ADC, Temperature Sensor and Built-In

P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)......................... 21

8.8 Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to

P2.7)............................................................................21

8.9 Leakage Current – General-Purpose I/O (P1.0 to

P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)

(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to

P8.2, PJ.0 to PJ.3, RST/NMI)......................................22

8.10 Outputs – General-Purpose I/O (Full Drive

Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to

P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7,

P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3).................... 22

8.11 Outputs – General-Purpose I/O (Reduced Drive

Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to

V_MID............................................................................42

8.40 REF, External Reference........................................ 43

8.41 REF, Built-In Reference.......................................... 44

8.42 Comparator B..........................................................45

8.43 Ports PU.0 and PU.1...............................................45

8.44 LDO-PWR (LDO Power System)............................47

8.45 Flash Memory......................................................... 48

8.46 JTAG and Spy-Bi-Wire Interface.............................48

9 Detailed Description......................................................49

9.1 CPU ......................................................................... 49

9.2 Operating Modes...................................................... 50

9.3 Interrupt Vector Addresses....................................... 51

9.4 Memory Organization................................................52

9.5 Bootloader (BSL)...................................................... 53

9.6 JTAG Operation........................................................ 53

9.7 Flash Memory .......................................................... 54

9.8 RAM .........................................................................54

9.9 Peripherals................................................................54

9.10 Input/Output Diagrams............................................78

9.11 Device Descriptors................................................101

10 Device and Documentation Support........................104

10.1 Getting Started and Next Steps............................ 104

10.2 Device Nomenclature............................................104

10.3 Tools and Software............................................... 106

10.4 Documentation Support........................................ 108

10.5 Related Links........................................................ 109

10.6 Support Resources............................................... 110

10.7 Trademarks........................................................... 110

10.8 Electrostatic Discharge Caution............................110

10.9 Export Control Notice............................................110

10.10 Glossary..............................................................110

11 Mechanical, Packaging, and Orderable

P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7,

P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3).................... 22

8.12 Output Frequency – General-Purpose I/O (P1.0

to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)

(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to

P8.2, PJ.0 to PJ.3)...................................................... 23

8.13 Typical Characteristics – Outputs, Reduced

Drive Strength (PxDS.y = 0)........................................24

8.14 Typical Characteristics – Outputs, Full Drive

Strength (PxDS.y = 1)................................................. 25

8.15 Crystal Oscillator, XT1, Low-Frequency Mode........26

8.16 Crystal Oscillator, XT2............................................ 27

8.17 Internal Very-Low-Power Low-Frequency

Oscillator (VLO)...........................................................28

8.18 Internal Reference, Low-Frequency Oscillator

(REFO)........................................................................28

8.19 DCO Frequency......................................................29

8.20 PMM, Brownout Reset (BOR).................................30

8.21 PMM, Core Voltage.................................................30

8.22 PMM, SVS High Side..............................................31

Information...................................................................111

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SLAS678G – AUGUST 2010 – REVISED SEPTEMBER 2020

5 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from revision F to revision G

Changes from September 24, 2019 to September 11, 2020

Page

•

Updated the numbering for sections, tables, figures, and cross-references throughout the document..............1

Added nFBGA package (ZXH) information throughout document......................................................................1

Added note about status change for all orderable part numbers in the ZQE package in Device Information ... 1

Changed the MAX value of the I_ERASEand I_MERASE, I_BANKparameters in Section 8.45, Flash Memory ......... 48

Changes from revision E to revision F

Changes from September 26, 2018 to September 23, 2019

Page

•

Added the note "TI recommends connecting the exposed thermal pad to V_SS" to Figure 7-2, 64-Pin RGC

Package (Top View) – MSP430F5328IRGC, MSP430F5326IRGC, MSP430F5324IRGC ................................8

•

Added a row for the QFN thermal pad to Section 7.2, Signal Descriptions ..................................................... 11

Changes from revision D to revision E

Changes from February 27, 2013 to September 25, 2018

Page

•

Changes throughout to document structure and organization, including addition of section numbering............1

Added Section 2, Applications ...........................................................................................................................1

Added Device Information table..........................................................................................................................1

Added Section 4 and moved all functional block diagrams to it..........................................................................3

Added Section 6.1, Related Products ................................................................................................................7

Added signal names to the ZQE pinout..............................................................................................................8

Added "Port U is supplied by the LDOO rail" to the PU.0 and PU.1 descriptions in Section 7.2, Signal

Descriptions ..................................................................................................................................................... 11

Added note to RST/NMI/SBWTDIO pin............................................................................................................ 11

Added typical conditions statements at the beginning of Section 8, Specifications .........................................17

Added Section 8.2, ESD Ratings .....................................................................................................................17

Added note to C_VCORE..................................................................................................................................... 18

Moved Section 8.6, Thermal Resistance Characteristics ................................................................................ 21

Added note to R_Pull.......................................................................................................................................... 21

Changed the TYP value of the C_L,effparameter with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1

pF in Section 8.15, Crystal Oscillator, XT1, Low-Frequency Mode ................................................................. 26

Changed the MIN value of the V_{(DVCC_BOR_hys)}parameter from 60 mV to 50 mV in Section 8.20, PMM,

Brownout Reset (BOR) ....................................................................................................................................30

Updated notes (1) and (2) and added note (3) in Section 8.26, Wake-up Times From Low-Power Modes and

Reset ............................................................................................................................................................... 34

Removed ADC12DIV from the formula for the TYP value in the second row of the t_CONVERTparameter in

Section 8.36, 12-Bit ADC, Timing Parameters, because ADC12CLK is after division..................................... 40

For the t_{EN_CMP}parameter in Section 8.42, Comparator_B: Changed the Test Condition of the first row from

"CBPWRMD = 00, 01, 10" to "CBPWRMD = 00, 01"; Added a second row with Test Conditions of

•

"CBPWRMD = 10" and MAX value of 100 µs...................................................................................................45

Changed all instances of "bootstrap loader" to "bootloader" throughout document ........................................ 53

Corrected spelling of NMIIFG in Table 9-8, System Module Interrupt Vector Registers ..................................57

Changed Table 9-56, Port PU.0, PU.1 Functions ............................................................................................ 98

•

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MSP430F5329, MSP430F5328, MSP430F5327, MSP430F5326, MSP430F5325, MSP430F5324

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•

Added Section 10, Device and Documentation Support, and moved Device Nomenclature, ESD Caution, and

Trademarks sections to it................................................................................................................................104

Replaced former Tools Support section with Section 10.3, Tools and Software ............................................106

Added Section 11, Mechanical, Packaging, and Orderable Information ........................................................ 111

•

Changes from initial release to revision D

REVISION

DESCRIPTION

Section 7.2, Changed ACLK description (added dividers up to 32)

Table 9-6, Corrected typo in PM_ANALOG note

Table 9-8, Changed SYSRSTIV interrupt event at 1Ch to Reserved

Section 9.9.1, Changed description of the number of I/Os in each port for the different package options

Section 8.3, Added test conditions for typical characteristics

SLAS678D

February 2013

Section 8.3, Added note regarding interaction between minimum VCC and SVS

Section 8.19, Added note (1)

Section 8.37, Changed note regarding decoupling capacitors on VREF+ and VREF- pins

Section 8.39, Changed t_{SENSOR(sample)}MIN value to 100 µs, Changed note (2)

Section 8.45, Changed values of I_ERASEand I_MERASE

Table 9-45, Table 9-46, Corrected notes regarding USCI CLK functions taking precedence over USCI STE functions

SLAS678C

November 2011

Added Section 9.11

SLAS678B

October 2011

Production Data release

Updated Product Preview release

Product Preview release

SLAS678A

August 2011

SLAS678

August 2010

6

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SLAS678G – AUGUST 2010 – REVISED SEPTEMBER 2020

6 Device Comparison

Table 6-1 summarizes the available family members.

Table 6-1. Device Comparison

USCI

CHANNEL A:

UART, IrDA,

SPI

FLASH

(KB)

SRAM

(KB)

ADC12_A

(Ch)

Comp_B

(Ch)

PACKAGE

DEVICE⁽¹⁾

Timer_A⁽²⁾Timer_B⁽³⁾

I/O

(4)

CHANNEL B:

SPI, I²C

MSP430F5329

MSP430F5328

MSP430F5327

MSP430F5326

MSP430F5325

MSP430F5324

128

96

10

8

5, 3, 3

7

2

14 ext, 2 int

10 ext, 2 int

14 ext, 2 int

10 ext, 2 int

14 ext, 2 int

10 ext, 2 int

12

8

63

47

63

47

63

47

80 PN

64 RGC,

80 ZXH,

80 ZQE

12

8

80 PN

64 RGC,

80 ZXH,

80 ZQE

96

8

64

6

12

8

80 PN

64 RGC,

80 ZXH,

80 ZQE

64

6

(1) For the most current package and ordering information, see the Package Option Addendum in Section 11, or see the TI website at

www.ti.com.

(2) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and

PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first

instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

(3) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and

PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first

instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

(4) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/

packaging.

6.1 Related Products

For information about other devices in this family of products or related products, see the following links.

Products for TI microcontrollers

TI's low-power and high-performance MCUs, with wired and wireless connectivity options, are optimized for a

broad range of applications.

Products for MSP430 ultra-low-power microcontrollers

One platform. One ecosystem. Endless possibilities.

Companion products for MSP430F5329

Review products that are frequently purchased or used in conjunction with this product.

Reference designs

Find reference designs leveraging the best in TI technology – from analog and power management to embedded

processors.

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SLAS678G – AUGUST 2010 – REVISED SEPTEMBER 2020

www.ti.com

7 Terminal Configuration and Functions

7.1 Pin Diagrams

Figure 7-1 shows the pinout for the F5329, F5327, and F5325 devices in the 80-pin PN package.

1

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

P7.7/TB0CLK/MCLK

P7.6/TB0.4

P6.4/CB4/A4

P6.5/CB5/A5

2

3

P7.5/TB0.3

P6.6/CB6/A6

4

P7.4/TB0.2

P6.7/CB7/A7

P7.0/CB8/A12

P7.1/CB9/A13

5

P5.7/TB0.1

6

P5.6/TB0.0

P4.7/PM_NONE

P4.6/PM_NONE

P7.2/CB10/A14

P7.3/CB11/A15

P5.0/A8/VREF+/VeREF+

P5.1/A9/VREF−/VeREF−

AVCC1

7

8

P4.5/PM_UCA1RXD/PM_UCA1SOMI

P4.4/PM_UCA1TXD/PM_UCA1SIMO

DVCC2

9

MSP430F5329IPN

MSP430F5327IPN

MSP430F5325IPN

10

11

12

13

14

15

16

17

18

19

20

DVSS2

P5.4/XIN

P5.5/XOUT

AVSS1

P4.3/PM_UCB1CLK/PM_UCA1STE

P4.2/PM_UCB1SOMI/PM_UCB1SCL

P4.1/PM_UCB1SIMO/PM_UCB1SDA

P4.0/PM_UCB1STE/PM_UCA1CLK

P3.7/TB0OUTH/SVMOUT

P3.6/TB0.6

P8.0

P8.1

P8.2

DVCC1

DVSS1

VCORE

P3.5/TB0.5

P3.4/UCA0RXD/UCA0SOMI

A0.3

A0.4

A1.0

P1.4/T

P1.5/T

P1.7/T

A2CLK/SMCLK

A1CLK/CBOUT

P2.2/T

P1.6/T

Figure 7-1. 80-Pin PN Package (Top View) – MSP430F5329IPN, MSP430F5327IPN, MSP430F5325IPN

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SLAS678G – AUGUST 2010 – REVISED SEPTEMBER 2020

Figure 7-2 shows the pinout for the F5328, F5326, and F5324 devices in the 64-pin RGC package.

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

P4.7/PM_NONE

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P6.0/CB0/A0

P6.1/CB1/A1

P4.6/PM_NONE

2

3

P4.5/PM_UCA1RXD/PM_UCA1SOMI

P4.4/PM_UCA1TXD/PM_UCA1SIMO

P4.3/PM_UCB1CLK/PM_UCA1STE

P4.2/PM_UCB1SOMI/PM_UCB1SCL

P4.1/PM_UCB1SIMO/PM_UCB1SDA

P4.0/PM_UCB1STE/PM_UCA1CLK

DVCC2

P6.2/CB2/A2

4

P6.3/CB3/A3

P6.4/CB4/A4

5

P6.5/CB5/A5

6

P6.6/CB6/A6

7

MSP430F5328IRGC

MSP430F5326IRGC

MSP430F5324IRGC

P6.7/CB7/A7

8

P5.0/A8/VREF+/VeREF+

P5.1/A9/VREF−/VeREF−

AVCC1

9

DVSS2

10

11

12

13

14

15

16

P3.4/UCA0RXD/UCA0SOMI

P3.3/UCA0TXD/UCA0SIMO

P3.2/UCB0CLK/UCA0STE

P3.1/UCB0SOMI/UCB0SCL

P3.0/UCB0SIMO/UCB0SDA

P2.7/UCB0STE/UCA0CLK

P5.4/XIN

P5.5/XOUT

AVSS1

DVCC1

DVSS1

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

A1.1

A0.3

A0.4

A1.0

A1.2

P2.0/T

P1.4/T

P1.5/T

P1.7/T

P2.1/T

A2CLK/SMCLK

A1CLK/CBOUT

P2.2/T

P1.6/T

TI recommends connecting the exposed thermal pad to V_SS

.

Figure 7-2. 64-Pin RGC Package (Top View) – MSP430F5328IRGC, MSP430F5326IRGC,

MSP430F5324IRGC

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Figure 7-3 shows the pinout for the F5328, F5326, and F5324 devices in the 80-pin ZXH or ZQE package. This

figure shows the default signal name for each pin; see Section 7.2 for additional signals.

P6.0

A1

RST

A2

PJ.2

A3

TEST AVSS2 LDOO LDOI

PU.1

A8

PU.0

A9

A4

A5

A6

A7

P6.2

B1

P6.1

B2

PJ.3

B3

P5.3

B4

P5.2

B5

NC

B6

NC

B7

VSSU VSSU

B8

B9

P6.4

C1

P6.3

C2

PJ.1

C4

PJ.0 Reserved P4.7

C5 C6

C7

P4.6

C8

P4.5

C9

P6.6

D1

P6.5

D2

P6.7 Reserved Reserved Reserved P4.4

D3 D4 D7

D5 D6

P4.3

D8

P4.2

D9

P5.0

E1

P5.1 Reserved Reserved Reserved Reserved P4.1

E2 E3 E4 E7

E5 E6

P4.0 DVCC2

E8 E9

P5.4 AVCC1 Reserved Reserved Reserved Reserved Reserved Reserved DVSS2

F1

F2

F3

F4

F5

F6

F7

F8

F9

P5.5 AVSS1 Reserved P1.3

P1.6

G5

P2.1

G6

P3.4

G7

P3.2

G8

P3.3

G9

G1

DVCC1 P1.0

H1 H2

G2

G3

G4

P1.1

H3

P1.4

H4

P1.7

H5

P2.3

H6

P2.7

H7

P3.0

H8

P3.1

H9

DVSS1 VCORE P1.2

J1 J2 J3

P1.5

J4

P2.0

J5

P2.2

J6

P2.4

J7

P2.5

J8

P2.6

J9

Figure 7-3. 80-Pin ZXH or ZQE Package (Top View) – MSP430F5328IZXH, MSP430F5326IZXH,

MSP430F5324IZXH, MSP430F5328IZQE, MSP430F5326IZQE, MSP430F5324IZQE

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7.2 Signal Descriptions

Table 7-1 describes the signals for all device variants and package options.

Table 7-1. Signal Descriptions

TERMINAL

NO.

I/O⁽¹⁾

DESCRIPTION

NAME

ZXH,

ZQE

PN

RGC

General-purpose digital I/O

Comparator_B input CB4

Analog input A4 for ADC

P6.4/CB4/A4

1

5

C1

D2

I/O

General-purpose digital I/O

Comparator_B input CB5

Analog input A5 for ADC

P6.5/CB5/A5

P6.6/CB6/A6

P6.7/CB7/A7

P7.0/CB8/A12

P7.1/CB9/A13

2

3

4

5

6

7

General-purpose digital I/O

Comparator_B input CB6

Analog input A6 for ADC

D1

General-purpose digital I/O

Comparator_B input CB7

Analog input A7 for ADC

8

D3

General-purpose digital I/O (not available on F5328, F5326, F5324 devices)

Comparator_B input CB8 (not available on F5328, F5326, F5324 devices)

Analog input A12 for ADC (not available on F5328, F5326, F5324 devices)

N/A

General-purpose digital I/O (not available on F5328, F5326, F5324 devices)

Comparator_B input CB9 (not available on F5328, F5326, F5324 devices)

Analog input A13 for ADC (not available on F5328, F5326, F5324 devices)

General-purpose digital I/O (not available on F5328, F5326, F5324 devices)

Comparator_B input CB10 (not available on F5328, F5326, F5324

devices)

P7.2/CB10/A14

7

8

9

N/A

9

N/A

E1

I/O

Analog input A14 for ADC (not available on F5328, F5326, F5324 devices)

General-purpose digital I/O (not available on F5328, F5326, F5324 devices)

Comparator_B input CB11 (not available on F5328, F5326, F5324 devices)

Analog input A15 for ADC (not available on F5328, F5326, F5324 devices)

P7.3/CB11/A15

General-purpose digital I/O

Analog input A8 for ADC

P5.0/A8/VREF+/VeREF+

Output of reference voltage to the ADC

Input for an external reference voltage to the ADC

General-purpose digital I/O

Analog input A9 for ADC

P5.1/A9/VREF-/VeREF-

10

E2

I/O

Negative terminal for the ADC reference voltage for both sources, the internal

reference voltage, or an external applied reference voltage

AVCC1

11

12

11

12

F2

F1

Analog power supply

General-purpose digital I/O

Input terminal for crystal oscillator XT1

P5.4/XIN

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Table 7-1. Signal Descriptions (continued)

TERMINAL

NO.

I/O⁽¹⁾

DESCRIPTION

NAME

ZXH,

ZQE

PN

RGC

General-purpose digital I/O

P5.5/XOUT

13

G1

I/O

Output terminal of crystal oscillator XT1

AVSS1

P8.0

14

15

16

17

18

19

14

N/A

15

G2

N/A

H1

Analog ground supply

I/O

General-purpose digital I/O

Digital power supply

P8.1

P8.2

DVCC1

DVSS1

16

J1

Digital ground supply

Regulated core power supply output (internal use only, no external current

loading)

VCORE⁽²⁾

20

17

18

J2

General-purpose digital I/O with port interrupt

TA0 clock signal TA0CLK input

P1.0/TA0CLK/ACLK

21

H2

I/O

ACLK output (divided by 1, 2, 4, 8, 16, or 32)

General-purpose digital I/O with port interrupt

TA0 CCR0 capture: CCI0A input, compare: Out0 output

BSL transmit output

P1.1/TA0.0

P1.2/TA0.1

22

23

19

20

H3

J3

General-purpose digital I/O with port interrupt

TA0 CCR1 capture: CCI1A input, compare: Out1 output

BSL receive input

General-purpose digital I/O with port interrupt

P1.3/TA0.2

P1.4/TA0.3

P1.5/TA0.4

24

25

26

21

22

23

G4

H4

J4

I/O

TA0 CCR2 capture: CCI2A input, compare: Out2 output

General-purpose digital I/O with port interrupt

TA0 CCR3 capture: CCI3A input compare: Out3 output

General-purpose digital I/O with port interrupt

TA0 CCR4 capture: CCI4A input, compare: Out4 output

General-purpose digital I/O with port interrupt

TA1 clock signal TA1CLK input

Comparator_B output

P1.6/TA1CLK/CBOUT

27

24

G5

I/O

General-purpose digital I/O with port interrupt

P1.7/TA1.0

28

29

30

31

32

33

25

26

27

28

29

30

H5

J5

I/O

TA1 CCR0 capture: CCI0A input, compare: Out0 output

General-purpose digital I/O with port interrupt

P2.0/TA1.1

TA1 CCR1 capture: CCI1A input, compare: Out1 output

General-purpose digital I/O with port interrupt

P2.1/TA1.2

G6

J6

TA1 CCR2 capture: CCI2A input, compare: Out2 output

General-purpose digital I/O with port interrupt

TA2 clock signal TA2CLK input ; SMCLK output

P2.2/TA2CLK/SMCLK

P2.3/TA2.0

General-purpose digital I/O with port interrupt

H6

J7

TA2 CCR0 capture: CCI0A input, compare: Out0 output

General-purpose digital I/O with port interrupt

P2.4/TA2.1

TA2 CCR1 capture: CCI1A input, compare: Out1 output

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Table 7-1. Signal Descriptions (continued)

TERMINAL

NO.

I/O⁽¹⁾

DESCRIPTION

NAME

ZXH,

ZQE

PN

RGC

General-purpose digital I/O with port interrupt

P2.5/TA2.2

34

31

J8

I/O

TA2 CCR2 capture: CCI2A input, compare: Out2 output

General-purpose digital I/O with port interrupt

RTC clock output for calibration

DMA external trigger input

P2.6/RTCCLK/DMAE0

35

36

32

33

J9

General-purpose digital I/O with port interrupt

Slave transmit enable – USCI_B0 SPI mode

Clock signal input – USCI_A0 SPI slave mode

Clock signal output – USCI_A0 SPI master mode

P2.7/UCB0STE/

UCA0CLK

H7

I/O

General-purpose digital I/O

P3.0/UCB0SIMO/

UCB0SDA

Slave in, master out – USCI_B0 SPI mode

I²C data – USCI_B0 I²C mode

37

38

34

35

H8

H9

I/O

General-purpose digital I/O

P3.1/UCB0SOMI/

UCB0SCL

Slave out, master in – USCI_B0 SPI mode

I²C clock – USCI_B0 I²C mode

General-purpose digital I/O

Clock signal input – USCI_B0 SPI slave mode

Clock signal output – USCI_B0 SPI master mode

Slave transmit enable – USCI_A0 SPI mode

P3.2/UCB0CLK/

UCA0STE

39

36

G8

I/O

General-purpose digital I/O

P3.3/UCA0TXD/

UCA0SIMO

Transmit data – USCI_A0 UART mode

Slave in, master out – USCI_A0 SPI mode

40

41

37

38

G9

G7

I/O

General-purpose digital I/O

P3.4/UCA0RXD/

UCA0SOMI

Receive data – USCI_A0 UART mode

Slave out, master in – USCI_A0 SPI mode

General-purpose digital I/O (not available on F5328, F5326, F5324 devices)

TB0 CCR5 capture: CCI5A input, compare: Out5 output

P3.5/TB0.5

P3.6/TB0.6

42

43

N/A

I/O

General-purpose digital I/O (not available on F5328, F5326, F5324 devices)

TB0 CCR6 capture: CCI6A input, compare: Out6 output

General-purpose digital I/O (not available on F5328, F5326, F5324 devices)

Switch all PWM outputs high-impedance input – TB0 (not available on F5328,

F5326, F5324 devices)

P3.7/TB0OUTH/

SVMOUT

44

45

N/A

41

N/A

E8

I/O

SVM output (not available on F5328, F5326, F5324 devices)

General-purpose digital I/O with reconfigurable port mapping secondary

function

P4.0/PM_UCB1STE/

PM_UCA1CLK

Default mapping: Slave transmit enable – USCI_B1 SPI mode

Default mapping: Clock signal input – USCI_A1 SPI slave mode

Default mapping: Clock signal output – USCI_A1 SPI master mode

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Table 7-1. Signal Descriptions (continued)

TERMINAL

NO.

I/O⁽¹⁾

DESCRIPTION

NAME

ZXH,

ZQE

PN

RGC

General-purpose digital I/O with reconfigurable port mapping secondary

function

P4.1/PM_UCB1SIMO/

PM_UCB1SDA

46

42

E7

D9

I/O

Default mapping: Slave in, master out – USCI_B1 SPI mode

Default mapping: I²C data – USCI_B1 I²C mode

General-purpose digital I/O with reconfigurable port mapping secondary

function

P4.2/PM_UCB1SOMI/

PM_UCB1SCL

47

48

43

44

I/O

Default mapping: Slave out, master in – USCI_B1 SPI mode

Default mapping: I²C clock – USCI_B1 I²C mode

General-purpose digital I/O with reconfigurable port mapping secondary

function

P4.3/PM_UCB1CLK/

PM_UCA1STE

Default mapping: Clock signal input – USCI_B1 SPI slave mode

Default mapping: Clock signal output – USCI_B1 SPI master mode

Default mapping: Slave transmit enable – USCI_A1 SPI mode

D8

DVSS2

DVCC2

49

50

39

40

F9

E9

Digital ground supply

Digital power supply

General-purpose digital I/O with reconfigurable port mapping secondary

function

P4.4/PM_UCA1TXD/

PM_UCA1SIMO

51

52

45

46

D7

C9

I/O

Default mapping: Transmit data – USCI_A1 UART mode

Default mapping: Slave in, master out – USCI_A1 SPI mode

General-purpose digital I/O with reconfigurable port mapping secondary

function

P4.5/PM_UCA1RXD/

PM_UCA1SOMI

Default mapping: Receive data – USCI_A1 UART mode

Default mapping: Slave out, master in – USCI_A1 SPI mode

General-purpose digital I/O with reconfigurable port mapping secondary

function

P4.6/PM_NONE

P4.7/PM_NONE

P5.6/TB0.0

53

54

55

56

57

58

59

47

C8

C7

I/O

Default mapping: no secondary function.

General-purpose digital I/O with reconfigurable port mapping secondary

function

48

Default mapping: no secondary function.

General-purpose digital I/O (not available on F5328, F5326, F5324 devices)

N/A

TB0 CCR0 capture: CCI0A input, compare: Out0 output (not available on

F5328, F5326, F5324 devices)

General-purpose digital I/O (not available on F5328, F5326, F5324 devices)

P5.7/TB0.1

TB0 CCR1 capture: CCI1A input, compare: Out1 output (not available on

F5328, F5326, F5324 devices)

General-purpose digital I/O (not available on F5328, F5326, F5324 devices)

P7.4/TB0.2

TB0 CCR2 capture: CCI2A input, compare: Out2 output (not available on

F5328, F5326, F5324 devices)

General-purpose digital I/O (not available on F5328, F5326, F5324 devices)

P7.5/TB0.3

TB0 CCR3 capture: CCI3A input, compare: Out3 output (not available on

F5328, F5326, F5324 devices)

General-purpose digital I/O (not available on F5328, F5326, F5324 devices)

P7.6/TB0.4

TB0 CCR4 capture: CCI4A input, compare: Out4 output (not available on

F5328, F5326, F5324 devices)

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Table 7-1. Signal Descriptions (continued)

TERMINAL

PN

NO.

I/O⁽¹⁾

DESCRIPTION

NAME

ZXH,

ZQE

RGC

General-purpose digital I/O (not available on F5328, F5326, F5324 devices)

TB0 clock signal TBCLK input (not available on F5328, F5326, F5324

devices)

P7.7/TB0CLK/MCLK

60

N/A

I/O

MCLK output (not available on F5328, F5326, F5324 devices)

Port U ground supply

VSSU

PU.0

NC

61

62

63

64

49

50

51

52

B8, B9

A9

General-purpose digital I/O, controlled by PU control register, Port U is

supplied by the LDOO rail

I/O

B7

No connect

General-purpose digital I/O, controlled by PU control register, Port U is

supplied by the LDOO rail

PU.1

A8

LDOI

LDOO

NC

65

66

67

68

53

54

55

56

A7

A6

B6

A5

LDO input

LDO output

No connect

AVSS2

Analog ground supply

General-purpose digital I/O

Input terminal for crystal oscillator XT2

P5.2/XT2IN

69

70

71

72

73

74

75

57

58

59

60

61

62

63

B5

B4

A4

C5

C4

A3

B3

I/O

I

General-purpose digital I/O

P5.3/XT2OUT

TEST/SBWTCK⁽³⁾

PJ.0/TDO⁽⁴⁾

Output terminal of crystal oscillator XT2

Test mode pin – Selects four wire JTAG operation.

Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated

General-purpose digital I/O

JTAG test data output port

I/O

General-purpose digital I/O

PJ.1/TDI/TCLK⁽⁴⁾

PJ.2/TMS⁽⁴⁾

JTAG test data input or test clock input

General-purpose digital I/O

JTAG test mode select

General-purpose digital I/O

JTAG test clock

PJ.3/TCK⁽⁴⁾

Reset input active low⁽⁵⁾

RST/NMI/SBWTDIO⁽³⁾

P6.0/CB0/A0

76

77

78

79

64

1

A2

A1

B2

B1

I/O

Nonmaskable interrupt input

Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated.

General-purpose digital I/O

Comparator_B input CB0

Analog input A0 for ADC

General-purpose digital I/O

Comparator_B input CB1

Analog input A1 for ADC

P6.1/CB1/A1

2

General-purpose digital I/O

Comparator_B input CB2

Analog input A2 for ADC

P6.2/CB2/A2

3

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Table 7-1. Signal Descriptions (continued)

TERMINAL

NO.

I/O⁽¹⁾

DESCRIPTION

NAME

ZXH,

ZQE

PN

RGC

General-purpose digital I/O

Comparator_B input CB3

Analog input A3 for ADC

P6.3/CB3/A3

80

4

C2

I/O

C6,

D4,

D5,

D6, E3,

Reserved

N/A

N/A E4, E5,

E6, F3,

Reserved. Connect to ground.

F4, F5,

F6, F7,

F8, G3

The package thermal pad must be soldered to the printed circuit board for

Thermal pad

–

Pad

–

thermal and mechanical performance. TI recommends connection to V_SS

.

(1) I = input, O = output, N/A = not available

(2) VCORE is for internal use only. No external current loading is possible. VCORE should be connected only to the recommended

capacitor value, C_VCORE

.

(3) See Section 9.5 and Section 9.6 for use with BSL and JTAG functions, respectively.

(4) See Section 9.6 for use with JTAG function.

(5) When this pin is configured as reset, the internal pullup resistor is enabled by default.

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8 Specifications

All graphs in this section are for typical conditions, unless otherwise noted.

Typical (TYP) values are specified at V_CC= 3.3 V and T_A= 25°C, unless otherwise noted.

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

4.1

UNIT

V

Voltage applied at V_CCto V_SS

–0.3

Voltage applied to any pin (excluding VCORE, LDOI)⁽²⁾

V_CC+ 0.3

±2

V

Diode current at any device pin

mA

°C

(3)

Storage temperature, T_stg

–55

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V_SS. VCORE is for internal device use only. No external DC loading or voltage should be applied.

(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

8.2 ESD Ratings

VALUE

±1000

±250

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions. Pins listed as ±1000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions. Pins listed as ±250 V may actually have higher performance.

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8.3 Recommended Operating Conditions

MIN NOM

MAX UNIT

PMMCOREVx = 0

1.8

2.0

2.2

2.4

0

3.6

PMMCOREVx = 0, 1

3.6

V

3.6

Supply voltage during program execution and flash

V_CC

(1) (2)

programming (AVCCx = DVCCx = V_CC

)

PMMCOREVx = 0, 1, 2

PMMCOREVx = 0, 1, 2, 3

3.6

V

V_SS

T_A

Supply voltage (AVSSx = DVSSx = V_SS

Operating free-air temperature

)

–40

470

85

°C

nF

T_J

Operating junction temperature

C_VCORE

Recommended capacitor at VCORE⁽³⁾

C_DVCC

C_VCORE

/

Capacitor ratio of DVCC to VCORE

10

0

PMMCOREVx = 0,

1.8 V ≤ V_CC≤ 3.6 V

(default condition)

8.0

PMMCOREVx = 1,

2.0 V ≤ V_CC≤ 3.6 V

Processor frequency (maximum MCLK frequency)⁽⁴⁾

(see Figure 8-1)

0

12.0

20.0

25.0

f_SYSTEM

MHz

PMMCOREVx = 2,

2.2 V ≤ V_CC≤ 3.6 V

PMMCOREVx = 3,

2.4 V ≤ V_CC≤ 3.6 V

(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be

tolerated during power up and operation.

(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the threshold parameters in Section 8.22

for the exact values and further details.

(3) A capacitor tolerance of ±20% or better is required.

(4) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

25

3

20

2, 3

2

12

8

1, 2

1, 2, 3

1

0

0, 1

0, 1, 2

0, 1, 2, 3

0

1.8

2.0

2.2

2.4

3.6

Supply Voltage - V

NOTE: The numbers within the fields denote the supported PMMCOREVx settings.

Figure 8-1. Maximum System Frequency

18

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8.4 Active Mode Supply Current Into V_CCExcluding External Current

over recommended operating free-air temperature (unless otherwise noted)^{(1) (2) (3)}

FREQUENCY (f_DCO= f_MCLK= f_SMCLK

8 MHz 12 MHz 20 MHz

TYP MAX TYP MAX

)

EXECUTION

MEMORY

PARAMETER

V_CC

PMMCOREVx

1 MHz

25 MHz

TYP

UNIT

TYP

MAX

TYP

MAX

11.0

6.2

0

1

2

3

0

1

2

3

0.36

0.40

0.44

0.46

0.20

0.22

0.24

0.26

0.47

2.32

2.65

2.90

3.10

1.20

1.35

1.50

1.60

2.60

4.0

4.3

4.6

4.4

2.2

I_{AM, Flash}

Flash

3 V

mA

7.1

7.6

7.7

4.2

10.1

5.3

0.24

1.30

2.0

2.2

2.4

I_{AM, RAM}

RAM

3 V

mA

3.7

3.9

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external

load capacitance are chosen to closely match the required 12.5 pF.

(3) Characterized with program executing typical data processing. LDO disabled (LDOEN = 0).

f_ACLK= 32786 Hz, f_DCO= f_MCLK= f_SMCLKat specified frequency.

XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.

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8.5 Low-Power Mode Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)^{(1) (2)}

TEMPERATURE (T_A)

PARAMETER

V_CC

PMMCOREVx

–40°C

TYP MAX

73

25°C

TYP

60°C

TYP MAX

80

85°C

TYP

UNIT

MAX

85

MAX

97

2.2 V

3 V

0

3

0

3

0

1

2

0

1

2

3

0

1

2

3

0

1

2

3

77

83

85

95

I_LPM0,1MHzLow-power mode 0^{(3) (4)}

µA

79

92

88

105

17

2.2 V

3 V

6.5

7.0

1.90

2.00

2.15

2.1

2.3

2.4

2.5

1.4

1.5

1.6

1.1

1.2

1.3

0.18

12

10

11

I_LPM2

Low-power mode 2^{(5) (4)}

7.0

13

11

12

18

1.60

1.65

1.75

1.8

2.6

5.6

5.9

6.1

5.8

6.1

6.3

6.4

4.9

5.2

5.3

5.4

4.8

5.1

5.2

5.3

0.5

2.2 V

2.7

2.9

Low-power mode 3,

crystal mode^{(6) (4)}

I_LPM3,XT1LF

2.9

2.8

8.3

µA

1.9

2.9

3 V

2.0

3.0

2.0

3.9

2.7

3.1

9.3

7.4

1.1

1.9

1.1

2.0

Low-power mode 3,

VLO mode^{(7) (4)}

I_LPM3,VLO

3 V

1.2

2.1

1.3

3.0

1.5

2.2

8.5

7.3

0.9

1.8

1.1

2.0

I_LPM4

Low-power mode 4^{(8) (4)}

Low-power mode 4.5⁽⁹⁾

3 V

µA

1.2

2.1

1.3

1.6

2.2

8.1

1.0

I_LPM4.5

0.15

0.35

0.26

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external

load capacitance are chosen to closely match the required 12.5 pF.

(3) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), f_ACLK= 32768 Hz, f_MCLK= 0 MHz, f_SMCLK= f_DCO= 1 MHz

LDO disabled (LDOEN = 0).

(4) Current for brownout, high-side supervisor (SVS_H) normal mode included. Low-side supervisor (SVS_L) and low-side monitor (SVM_L)

disabled. High-side monitor (SVM_H) disabled. RAM retention enabled.

(5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), f_ACLK= 32768 Hz, f_MCLK= 0 MHz, f_SMCLK= f_DCO= 0 MHz, DCO setting

= 1-MHz operation, DCO bias generator enabled.)

LDO disabled (LDOEN = 0).

(6) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), f_ACLK= 32768 Hz, f_MCLK= f_SMCLK= f_DCO= 0 MHz

LDO disabled (LDOEN = 0).

(7) Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), f_ACLK= f_VLO, f_MCLK= f_SMCLK= f_DCO= 0 MHz

LDO disabled (LDOEN = 0).

(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), f_DCO= f_ACLK= f_MCLK= f_SMCLK= 0 MHz

LDO disabled (LDOEN = 0).

(9) Internal regulator disabled. No data retention.

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), f_DCO= f_ACLK= f_MCLK= f_SMCLK= 0 MHz

20

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SLAS678G – AUGUST 2010 – REVISED SEPTEMBER 2020

8.6 Thermal Resistance Characteristics

THERMAL METRIC

VALUE

70

UNIT

LQFP (PN)

VQFN (RGC)

BGA (ZQE)

LQFP (PN)

VQFN (RGC)

BGA (ZQE)

LQFP (PN)

VQFN (RGC)

BGA (ZQE)

LQFP (PN)

VQFN (RGC)

BGA (ZQE)

Low-K board (JESD51-3)

55

84

Rθ_JA

Junction-to-ambient thermal resistance, still air

°C/W

45

High-K board (JESD51-7)

25

46

12

Rθ_JCJunction-to-case thermal resistance

12

°C/W

30

22

Rθ_JB

Junction-to-board thermal resistance

6

20

8.7 Schmitt-Trigger Inputs – General-Purpose I/O

(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)

(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER⁽¹⁾

TEST CONDITIONS

V_CC

1.8 V

3 V

MIN

0.80

1.50

0.45

0.75

0.3

TYP

MAX UNIT

1.40

V

2.10

V_IT+Positive-going input threshold voltage

1.8 V

3 V

1.00

V

1.65

V_IT–Negative-going input threshold voltage

1.8 V

3 V

0.8

V

1.0

V_hysInput voltage hysteresis (V_IT+– V_IT–

)

0.4

For pullup: V_IN= V_SS

For pulldown: V_IN= V_CC

R_PullPullup or pulldown resistor⁽²⁾

20

35

5

50

kΩ

pF

C_I

Input capacitance

V_IN= V_SSor V_CC

(1) Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).

(2) Also applies to the RST pin when pullup or pulldown resistor is enabled.

8.8 Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER⁽¹⁾

TEST CONDITIONS

V_CC

MIN

MAX UNIT

t_(int)External interrupt timing⁽²⁾

External trigger pulse duration to set interrupt flag

2.2 V, 3 V

20

ns

(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.

(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t_(int)is met. It might be set by trigger signals

shorter than t_(int)

.

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8.9 Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to

P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

See ^{(1) (2)}

V_CC

MIN

MAX UNIT

I_lkg(Px.x)High-impedance leakage current

1.8 V, 3 V

±50 nA

(1) The leakage current is measured with V_SSor V_CCapplied to the corresponding pins, unless otherwise noted.

(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is

disabled.

8.10 Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to

P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see

Section 8.14)

PARAMETER

TEST CONDITIONS

I_(OHmax)= –3 mA⁽¹⁾

V_CC

MIN

V_CC– 0.25

V_CC– 0.60

V_CC– 0.25

V_CC– 0.60

MAX UNIT

V_CC

1.8 V

I_(OHmax)= –10 mA⁽²⁾

I_(OHmax)= –5 mA⁽¹⁾

I_(OHmax)= –15 mA⁽²⁾

I_(OLmax)= 3 mA⁽¹⁾

I_(OLmax)= 10 mA⁽²⁾

I_(OLmax)= 5 mA⁽¹⁾

I_(OLmax)= 15 mA⁽²⁾

V_CC

V_OHHigh-level output voltage

V

V_CC

3 V

1.8 V

3 V

V_CC

V_SSV_SS+ 0.25

V_SSV_SS+ 0.60

V_SSV_SS+ 0.25

V_SSV_SS+ 0.60

V_OLLow-level output voltage

V

(1) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage

drop specified.

(2) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage

drop specified.

8.11 Outputs – General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7,

P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾(see

Section 8.13)

PARAMETER

TEST CONDITIONS

I_(OHmax)= –1 mA⁽²⁾

V_CC

MIN

V_CC– 0.25

V_CC– 0.60

V_CC– 0.25

V_CC– 0.60

MAX UNIT

V_CC

1.8 V

I_(OHmax)= –3 mA⁽³⁾

I_(OHmax)= –2 mA⁽²⁾

I_(OHmax)= –6 mA⁽³⁾

I_(OLmax)= 1 mA⁽²⁾

I_(OLmax)= 3 mA⁽³⁾

I_(OLmax)= 2 mA⁽²⁾

I_(OLmax)= 6 mA⁽³⁾

V_CC

V_OHHigh-level output voltage

V

V_CC

3 V

1.8 V

3 V

V_CC

V_SSV_SS+ 0.25

V_SSV_SS+ 0.60

V_SSV_SS+ 0.25

V_SSV_SS+ 0.60

V_OLLow-level output voltage

V

(1) Selecting reduced drive strength may reduce EMI.

(2) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage

drop specified.

(3) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage

drop specified.

22

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8.12 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0

to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX UNIT

V_CC= 1.8 V, PMMCOREVx = 0

16

(1) (2)

f_Px.y

Port output frequency (with load)

MHz

25

V_CC= 3 V, PMMCOREVx = 3

V_CC= 1.8 V, PMMCOREVx = 0

V_CC= 3 V, PMMCOREVx = 3

16

ACLK, SMCLK, MCLK,

C_L= 20 pF⁽²⁾

f_{Port_CLK}Clock output frequency

MHz

25

(1) A resistive divider with 2 × R1 between V_CCand V_SSis used as load. The output is connected to the center tap of the divider. For full

drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. C_L= 20 pF is connected to the output to V_SS

.

(2) The output voltage reaches at least 10% and 90% V_CCat the specified toggle frequency.

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8.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

25.0

20.0

15.0

10.0

5.0

8.0

7.0

6.0

5.0

4.0

3.0

2.0

1.0

0.0

T_A= 25°C

T_A= 85°C

V_CC= 3.0 V

Px.y

V_CC= 1.8 V

Px.y

T_A= 25°C

T_A= 85°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

V_OL– Low-Level Output Voltage – V

Figure 8-3. Typical Low-Level Output Current vs

Low-Level Output Voltage

Figure 8-2. Typical Low-Level Output Current vs

Low-Level Output Voltage

0.0

V_CC= 1.8 V

V_CC= 3.0 V

Px.y

−1.0

−5.0

−2.0

−3.0

−4.0

−10.0

T_A= 85°C

−5.0

−15.0

T_A= 85°C

−6.0

T_A= 25°C

−20.0

T_A= 25°C

−7.0

−8.0

−25.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

V_OH– High-Level Output Voltage – V

Figure 8-4. Typical High-Level Output Current vs

High-Level Output Voltage

Figure 8-5. Typical High-Level Output Current vs

High-Level Output Voltage

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8.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

60.0

24

20

16

12

8

T_A= 25°C

T_A= 85°C

V_CC= 1.8 V

Px.y

V_CC= 3.0 V

Px.y

55.0

50.0

45.0

40.0

35.0

30.0

25.0

20.0

15.0

10.0

5.0

T_A= 25°C

T_A= 85°C

4

0.0

0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

V_OL– Low-Level Output Voltage – V

Figure 8-6. Typical Low-Level Output Current vs

Low-Level Output Voltage

Figure 8-7. Typical Low-Level Output Current vs

Low-Level Output Voltage

0.0

0

V_CC= 1.8 V

Px.y

V_CC= 3.0 V

−5.0

Px.y

−10.0

−15.0

−20.0

−25.0

−30.0

−35.0

−40.0

−4

−8

−12

−45.0

T_A= 85°C

−16

T_A= 85°C

−50.0

−55.0

T_A= 25°C

−60.0

T_A= 25°C

−20

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

V_OH– High-Level Output Voltage – V

Figure 8-8. Typical High-Level Output Current vs

High-Level Output Voltage

Figure 8-9. Typical High-Level Output Current vs

High-Level Output Voltage

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8.15 Crystal Oscillator, XT1, Low-Frequency Mode

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER⁽¹⁾

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 1,

T_A= 25°C

0.075

Differential XT1 oscillator crystal

ΔI_DVCC.LFcurrent consumption from lowest

drive setting, LF mode

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 2,

T_A= 25°C

3 V

0.170

µA

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 3,

T_A= 25°C

0.290

XT1 oscillator crystal frequency,

LF mode

f_XT1,LF0

XTS = 0, XT1BYPASS = 0

32768

Hz

XT1 oscillator logic-level square-

f_XT1,LF,SW

XTS = 0, XT1BYPASS = 1^{(2) (3)}

10 32.768

210

50 kHz

wave input frequency, LF mode

XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 0,

f_XT1,LF= 32768 Hz, C_L,eff= 6 pF

Oscillation allowance for

OA_LF

kΩ

LF crystals⁽⁴⁾

XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 1,

f_XT1,LF= 32768 Hz, C_L,eff= 12 pF

300

XTS = 0, XCAPx = 0⁽⁶⁾

XTS = 0, XCAPx = 1

XTS = 0, XCAPx = 2

XTS = 0, XCAPx = 3

1

5.5

Integrated effective load

C_L,eff

pF

capacitance, LF mode⁽⁵⁾

8.5

12.0

XTS = 0, Measured at ACLK,

f_XT1,LF= 32768 Hz

Duty cycle, LF mode

30%

10

70%

Oscillator fault frequency,

f_Fault,LF

XTS = 0⁽⁸⁾

10000

Hz

ms

LF mode⁽⁷⁾

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 0,

T_A= 25°C, C_L,eff= 6 pF

1000

500

t_START,LF

Start-up time, LF mode

3 V

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 3,

T_A= 25°C, C_L,eff= 12 pF

(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.

•

Keep the trace between the device and the crystal as short as possible.

Design a good ground plane around the oscillator pins.

Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.

If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.

(2) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square-wave with parametrics defined

in the Schmitt-Trigger Inputs section of this data sheet.

(3) Maximum frequency of operation of the entire device cannot be exceeded.

(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the

XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following

guidelines, but should be evaluated based on the actual crystal selected for the application:

•

For XT1DRIVEx = 0, C_L,eff≤ 6 pF

For XT1DRIVEx = 1, 6 pF ≤ C_L,eff≤ 9 pF

For XT1DRIVEx = 2, 6 pF ≤ C_L,eff≤ 10 pF

For XT1DRIVEx = 3, C_L,eff≥ 6 pF

(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the

effective load capacitance should always match the specification of the used crystal.

(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

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(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies between the MIN and MAX specifications might set the flag.

(8) Measured with logic-level input frequency but also applies to operation with crystals.

8.16 Crystal Oscillator, XT2

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)^{(1) (2)}

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

f_OSC= 4 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 0,

T_A= 25°C

200

f_OSC= 12 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 1,

T_A= 25°C

260

325

450

XT2 oscillator crystal current

consumption

I_DVCC.XT2

3 V

µA

f_OSC= 20 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 2,

T_A= 25°C

f_OSC= 32 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 3,

T_A= 25°C

XT2 oscillator crystal frequency,

mode 0

f_XT2,HF0

f_XT2,HF1

f_XT2,HF2

f_XT2,HF3

XT2DRIVEx = 0, XT2BYPASS = 0⁽³⁾

XT2DRIVEx = 1, XT2BYPASS = 0⁽³⁾

XT2DRIVEx = 2, XT2BYPASS = 0⁽³⁾

XT2DRIVEx = 3, XT2BYPASS = 0⁽³⁾

4

8

MHz

XT2 oscillator crystal frequency,

mode 1

16 MHz

24 MHz

32 MHz

XT2 oscillator crystal frequency,

mode 2

16

24

XT2 oscillator crystal frequency,

mode 3

XT2 oscillator logic-level square-

wave input frequency, bypass

mode

f_XT2,HF,SW

XT2BYPASS = 1^{(4) (3)}

0.7

32 MHz

XT2DRIVEx = 0, XT2BYPASS = 0,

f_XT2,HF0= 6 MHz, C_L,eff= 15 pF

450

320

200

XT2DRIVEx = 1, XT2BYPASS = 0,

f_XT2,HF1= 12 MHz, C_L,eff= 15 pF

Oscillation allowance for

HF crystals⁽⁵⁾

OA_HF

Ω

XT2DRIVEx = 2, XT2BYPASS = 0,

f_XT2,HF2= 20 MHz, C_L,eff= 15 pF

XT2DRIVEx = 3, XT2BYPASS = 0,

f_XT2,HF3= 32 MHz, C_L,eff= 15 pF

f_OSC= 6 MHz,

XT2BYPASS = 0, XT2DRIVEx = 0,

T_A= 25°C, C_L,eff= 15 pF

0.5

0.3

t_START,HF

Start-up time

3 V

ms

pF

f_OSC= 20 MHz,

XT2BYPASS = 0, XT2DRIVEx = 2,

T_A= 25°C, C_L,eff= 15 pF

Integrated effective load

C_L,eff

1

capacitance, HF mode^{(6) (1)}

Duty cycle, HF mode

Measured at ACLK, f_XT2,HF2= 20 MHz

XT2BYPASS = 1⁽⁸⁾

40%

30

50%

60%

300 kHz

f_Fault,HF

Oscillator fault frequency⁽⁷⁾

(1) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. In general, an effective load capacitance

of up to 18 pF can be supported.

(2) To improve EMI on the XT2 oscillator the following guidelines should be observed.

•

Keep the traces between the device and the crystal as short as possible.

Design a good ground plane around the oscillator pins.

Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.

Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.

Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.

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•

If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.

(3) This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device

operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.

(4) When XT2BYPASS is set, the XT2 circuit is automatically powered down. Input signal is a digital square-wave with parametrics defined

in the Schmitt-Trigger Inputs section of this data sheet.

(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.

(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the

effective load capacitance should always match the specification of the used crystal.

(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies between the MIN and MAX specifications might set the flag.

(8) Measured with logic-level input frequency but also applies to operation with crystals.

8.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

VLO frequency

VLO frequency temperature drift

TEST CONDITIONS

V_CC

MIN

TYP

9.4

0.5

4

MAX UNIT

14 kHz

%/°C

f_VLO

Measured at ACLK

1.8 V to 3.6 V

6

df_VLO/d_T

Measured at ACLK⁽¹⁾

Measured at ACLK⁽²⁾

Measured at ACLK

df_VLO/dV_CCVLO frequency supply voltage drift

Duty cycle

%/V

40%

50%

60%

(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))

(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

8.18 Internal Reference, Low-Frequency Oscillator (REFO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

I_REFO

REFO oscillator current consumption T_A= 25°C

1.8 V to 3.6 V

3 V

3

µA

REFO frequency calibrated

Measured at ACLK

32768

Hz

f_REFO

Full temperature range

T_A= 25°C

±3.5%

±1.5%

%/°C

%/V

REFO absolute tolerance calibrated

df_REFO/d_T

REFO frequency temperature drift

Measured at ACLK⁽¹⁾

Measured at ACLK⁽²⁾

Measured at ACLK

40%/60% duty cycle

1.8 V to 3.6 V

0.01

1.0

df_REFO/dV_CCREFO frequency supply voltage drift

Duty cycle

40%

50%

25

60%

t_START

REFO start-up time

µs

(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))

(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

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8.19 DCO Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

DCO frequency (0, 0)⁽¹⁾

DCO frequency (0, 31)⁽¹⁾

DCO frequency (1, 0)⁽¹⁾

DCO frequency (1, 31)⁽¹⁾

DCO frequency (2, 0)⁽¹⁾

DCO frequency (2, 31)⁽¹⁾

DCO frequency (3, 0)⁽¹⁾

DCO frequency (3, 31)⁽¹⁾

DCO frequency (4, 0)⁽¹⁾

DCO frequency (4, 31)⁽¹⁾

DCO frequency (5, 0)⁽¹⁾

DCO frequency (5, 31)⁽¹⁾

DCO frequency (6, 0)⁽¹⁾

DCO frequency (6, 31)⁽¹⁾

DCO frequency (7, 0)⁽¹⁾

DCO frequency (7, 31)⁽¹⁾

TEST CONDITIONS

DCORSELx = 0, DCOx = 0, MODx = 0

DCORSELx = 0, DCOx = 31, MODx = 0

DCORSELx = 1, DCOx = 0, MODx = 0

DCORSELx = 1, DCOx = 31, MODx = 0

DCORSELx = 2, DCOx = 0, MODx = 0

DCORSELx = 2, DCOx = 31, MODx = 0

DCORSELx = 3, DCOx = 0, MODx = 0

DCORSELx = 3, DCOx = 31, MODx = 0

DCORSELx = 4, DCOx = 0, MODx = 0

DCORSELx = 4, DCOx = 31, MODx = 0

DCORSELx = 5, DCOx = 0, MODx = 0

DCORSELx = 5, DCOx = 31, MODx = 0

DCORSELx = 6, DCOx = 0, MODx = 0

DCORSELx = 6, DCOx = 31, MODx = 0

DCORSELx = 7, DCOx = 0, MODx = 0

DCORSELx = 7, DCOx = 31, MODx = 0

MIN

0.07

0.70

0.15

1.47

0.32

3.17

0.64

6.07

1.3

TYP

MAX

0.20

1.70

0.36

3.45

0.75

7.38

1.51

14.0

3.2

UNIT

MHz

f_DCO(0,0)

f_DCO(0,31)

f_DCO(1,0)

f_DCO(1,31)

f_DCO(2,0)

f_DCO(2,31)

f_DCO(3,0)

f_DCO(3,31)

f_DCO(4,0)

f_DCO(4,31)

f_DCO(5,0)

f_DCO(5,31)

f_DCO(6,0)

f_DCO(6,31)

f_DCO(7,0)

f_DCO(7,31)

12.3

2.5

28.2

6.0

23.7

4.6

54.1

10.7

88.0

19.6

135

39.0

8.5

60

Frequency step between range DCORSEL

and DCORSEL + 1

S_DCORSEL

S_DCO

S_RSEL= f_{DCO(DCORSEL+1,DCO)}/f_{DCO(DCORSEL,DCO)}

S_DCO= f_{DCO(DCORSEL,DCO+1)}/f_{DCO(DCORSEL,DCO)}

1.2

2.3

ratio

Frequency step between tap DCO and

DCO + 1

1.02

40%

1.12

60%

Duty cycle

Measured at SMCLK

f_DCO= 1 MHz

50%

0.1

df_DCO/dT

DCO frequency temperature drift⁽²⁾

DCO frequency voltage drift⁽³⁾

%/°C

%/V

df_DCO/dV_CC

f_DCO= 1 MHz

1.9

(1) When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, f_DCO, should be set to reside within the

range of f_{DCO(n, 0),MAX}≤ f_DCO≤ f_{DCO(n, 31),MIN}, where f_{DCO(n, 0),MAX}represents the maximum frequency specified for the DCO frequency,

range n, tap 0 (DCOx = 0) and f_{DCO(n,31),MIN}represents the minimum frequency specified for the DCO frequency, range n, tap 31

(DCOx = 31). This ensures that the target DCO frequency resides within the range selected. If the actual f_DCOfrequency for the

selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the selected range is at its

minimum or maximum tap setting.

(2) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))

(3) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

100

V_CC= 3.0 V

T_A= 25°C

10

DCOx = 31

1

DCOx = 0

0.1

0

1

2

3

4

5

6

7

DCORSEL

Figure 8-10. Typical DCO Frequency

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8.20 PMM, Brownout Reset (BOR)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

| dDV_CC/d_t| < 3 V/s

MIN

TYP

MAX UNIT

V_{(DVCC_BOR_IT–)}

V_{(DVCC_BOR_IT+)}

V_{(DVCC_BOR_hys)}

t_RESET

BOR_Hon voltage, DV_CCfalling level

BOR_Hoff voltage, DV_CCrising level

BOR_Hhysteresis

1.45

1.50

250

V

0.80

50

2

1.30

mV

µs

Pulse duration required at RST/NMI pin to accept a reset

8.21 PMM, Core Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

2.4 V ≤ DV_CC≤ 3.6 V

2.2 V ≤ DV_CC≤ 3.6 V

2.0 V ≤ DV_CC≤ 3.6 V

1.8 V ≤ DV_CC≤ 3.6 V

2.4 V ≤ DV_CC≤ 3.6 V

2.2 V ≤ DV_CC≤ 3.6 V

2.0 V ≤ DV_CC≤ 3.6 V

1.8 V ≤ DV_CC≤ 3.6 V

MIN

TYP

1.90

1.80

1.60

1.40

1.94

1.84

1.64

1.44

MAX UNIT

V_CORE3(AM)

V_CORE2(AM)

V_CORE1(AM)

V_CORE0(AM)

Core voltage, active mode, PMMCOREV = 3

Core voltage, active mode, PMMCOREV = 2

Core voltage, active mode, PMMCOREV = 1

Core voltage, active mode, PMMCOREV = 0

V

V_CORE3(LPM) Core voltage, low-current mode, PMMCOREV = 3

V_CORE2(LPM) Core voltage, low-current mode, PMMCOREV = 2

V_CORE1(LPM) Core voltage, low-current mode, PMMCOREV = 1

V_CORE0(LPM) Core voltage, low-current mode, PMMCOREV = 0

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8.22 PMM, SVS High Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SVSHE = 0, DV_CC= 3.6 V

0

nA

I_(SVSH)

SVS current consumption

SVSHE = 1, DV_CC= 3.6 V, SVSHFP = 0

SVSHE = 1, DV_CC= 3.6 V, SVSHFP = 1

SVSHE = 1, SVSHRVL = 0

200

1.5

µA

1.57

1.79

1.98

2.10

1.62

1.88

2.07

2.20

2.32

2.52

2.90

1.68

1.88

2.08

2.18

1.74

1.94

2.14

2.30

2.40

2.70

3.10

1.78

SVSHE = 1, SVSHRVL = 1

1.98

V

V_{(SVSH_IT–)}SVS_Hon voltage level⁽¹⁾

SVSHE = 1, SVSHRVL = 2

2.21

SVSHE = 1, SVSHRVL = 3

2.31

1.85

2.07

2.28

SVSHE = 1, SVSMHRRL = 0

SVSHE = 1, SVSMHRRL = 1

SVSHE = 1, SVSMHRRL = 2

SVSHE = 1, SVSMHRRL = 3

SVSHE = 1, SVSMHRRL = 4

SVSHE = 1, SVSMHRRL = 5

SVSHE = 1, SVSMHRRL = 6

SVSHE = 1, SVSMHRRL = 7

2.42

V

V_{(SVSH_IT+)}SVS_Hoff voltage level⁽¹⁾

2.55

2.88

3.23

SVSHE = 1, dV_DVCC/dt = 10 mV/µs,

SVSHFP = 1

2.5

20

t_pd(SVSH)

SVS_Hpropagation delay

SVS_Hon or off delay time

µs

SVSHE = 1, dV_DVCC/dt = 1 mV/µs,

SVSHFP = 0

SVSHE = 0 → 1, dV_DVCC/dt = 10 mV/µs,

SVSHFP = 1

12.5

100

t_(SVSH)

µs

SVSHE = 0 → 1, dV_DVCC/dt = 1 mV/µs,

SVSHFP = 0

dV_DVCC/dt DV_CCrise time

0

1000 V/s

(1) The SVS_Hsettings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage

Supervisor chapter in the MSP430F5xx and MSP430F6xx Family User's Guide on recommended settings and use.

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8.23 PMM, SVM High Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SVMHE = 0, DV_CC= 3.6 V

0

nA

I_(SVMH)

SVM_Hcurrent consumption

SVMHE = 1, DV_CC= 3.6 V, SVMHFP = 0

SVMHE = 1, DV_CC= 3.6 V, SVMHFP = 1

SVMHE = 1, SVSMHRRL = 0

SVMHE = 1, SVSMHRRL = 1

SVMHE = 1, SVSMHRRL = 2

SVMHE = 1, SVSMHRRL = 3

SVMHE = 1, SVSMHRRL = 4

SVMHE = 1, SVSMHRRL = 5

SVMHE = 1, SVSMHRRL = 6

SVMHE = 1, SVSMHRRL = 7

SVMHE = 1, SVMHOVPE = 1

200

1.5

µA

1.85

1.62

1.88

2.07

2.20

2.32

2.52

2.90

1.74

1.94

2.14

2.30

2.40

2.70

3.10

3.75

2.07

2.28

2.42

V_(SVMH)

SVM_Hon or off voltage level⁽¹⁾

2.55

2.88

3.23

V

SVMHE = 1, dV_DVCC/dt = 10 mV/µs,

SVMHFP = 1

2.5

20

t_pd(SVMH)SVM_Hpropagation delay

µs

SVMHE = 1, dV_DVCC/dt = 1 mV/µs,

SVMHFP = 0

SVMHE = 0 → 1, dV_DVCC/dt = 10 mV/µs,

SVMHFP = 1

12.5

100

t_(SVMH)

SVM_Hon or off delay time

SVMHE = 0 → 1, dV_DVCC/dt = 1 mV/µs,

SVMHFP = 0

(1) The SVM_Hsettings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage

Supervisor chapter in the MSP430F5xx and MSP430F6xx Family User's Guide on recommended settings and use.

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8.24 PMM, SVS Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SVSLE = 0, PMMCOREV = 2

0

nA

µA

µs

I_(SVSL)

SVS_Lcurrent consumption

SVSLE = 1, PMMCOREV = 2, SVSLFP = 0

200

1.5

2.5

20

SVSLE = 1, PMMCOREV = 2, SVSLFP = 1

SVSLE = 1, dV_CORE/dt = 10 mV/µs, SVSLFP = 1

SVSLE = 1, dV_CORE/dt = 1 mV/µs, SVSLFP = 0

SVSLE = 0 → 1, dV_CORE/dt = 10 mV/µs, SVSLFP = 1

SVSLE = 0 → 1, dV_CORE/dt = 1 mV/µs, SVSLFP = 0

t_pd(SVSL)SVS_Lpropagation delay

12.5

100

t_(SVSL)

SVS_Lon or off delay time

µs

8.25 PMM, SVM Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SVMLE = 0, PMMCOREV = 2

0

nA

µA

µs

I_(SVML)

SVM_Lcurrent consumption

SVMLE = 1, PMMCOREV = 2, SVMLFP = 0

200

1.5

2.5

20

SVMLE = 1, PMMCOREV = 2, SVMLFP = 1

SVMLE = 1, dV_CORE/dt = 10 mV/µs, SVMLFP = 1

SVMLE = 1, dV_CORE/dt = 1 mV/µs, SVMLFP = 0

SVMLE = 0 → 1, dV_CORE/dt = 10 mV/µs, SVMLFP = 1

SVMLE = 0 → 1, dV_CORE/dt = 1 mV/µs, SVMLFP = 0

t_pd(SVML)SVM_Lpropagation delay

12.5

100

t_(SVML)

SVM_Lon or off delay time

µs

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8.26 Wake-up Times From Low-Power Modes and Reset

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

f_MCLK≥ 4.0 MHz

3.5

7.5

Wake-up time from LPM2,

LPM3, or LPM4 to active

mode⁽¹⁾

PMMCOREV = SVSMLRRL = n

(where n = 0, 1, 2, or 3),

SVSLFP = 1

t_WAKE-UP-FAST

µs

9

1.0 MHz < f_MCLK

< 4.0 MHz

4.5

Wake-up time from LPM2,

LPM3 or LPM4 to active

mode^{(2) (3)}

PMMCOREV = SVSMLRRL = n

(where n = 0, 1, 2, or 3),

SVSLFP = 0

t_WAKE-UP-SLOW

150

165

µs

Wake-up time from LPM4.5 to

active mode⁽⁴⁾

t_WAKE-UP-LPM5

t_{WAKE-UP-RESET}

2

3

ms

Wake-up time from RST or

BOR event to active mode⁽⁴⁾

(1) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the

performance mode of the low-side supervisor (SVS_L) and low-side monitor (SVM_L). t_WAKE-UP-FASTis possible with SVS_Land SVM_Lin

full performance mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode

Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx

Family User's Guide.

(2) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the

performance mode of the low-side supervisor (SVS_L) and low-side monitor (SVM_L). t_WAKE-UP-SLOWis set with SVS_Land SVM_Lin

normal mode (low current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode

Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx

Family User's Guide.

(3) The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by

the performance mode settings as for LPM2, LPM3, and LPM4.

(4) This value represents the time from the wake-up event to the reset vector execution.

8.27 Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

Internal: SMCLK or ACLK,

External: TACLK,

f_TA

Timer_A input clock frequency

1.8 V, 3 V

25 MHz

Duty cycle = 50% ±10%

All capture inputs, minimum pulse

duration required for capture

t_TA,capTimer_A capture timing

1.8 V, 3 V

20

ns

8.28 Timer_B

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

Internal: SMCLK or ACLK,

External: TBCLK,

f_TB

Timer_B input clock frequency

1.8 V, 3 V

25 MHz

Duty cycle = 50% ±10%

All capture inputs, minimum pulse

duration required for capture

t_TB,cap

Timer_B capture timing

1.8 V, 3 V

20

ns

34

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8.29 USCI (UART Mode) Clock Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX UNIT

Internal: SMCLK or ACLK,

External: UCLK,

f_USCI

USCI input clock frequency

f_SYSTEMMHz

Duty cycle = 50% ±10%

f_BITCLK

BITCLK clock frequency (equals baud rate in MBaud)

1

MHz

8.30 USCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

V_CC

2.2 V

3 V

MIN

MAX UNIT

50

600

ns

600

t_τ

UART receive deglitch time⁽¹⁾

50

(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To make sure that pulses are

correctly recognized, their duration should exceed the maximum specification of the deglitch time.

8.31 USCI (SPI Master Mode) Clock Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX UNIT

f_USCI

USCI input clock frequency

Internal: SMCLK or ACLK, Duty cycle = 50% ±10%

f_SYSTEMMHz

8.32 USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

(see Figure 8-11 and Figure 8-12)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

SMCLK or ACLK,

f_USCI

USCI input clock frequency

f_SYSTEMMHz

Duty cycle = 50% ±10%

PMMCOREV = 0

1.8 V

3 V

55

38

30

25

0

t_SU,MI

SOMI input data setup time

SOMI input data hold time

ns

2.4 V

3 V

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

1.8 V

3 V

0

t_HD,MI

ns

2.4 V

3 V

0

1.8 V

3 V

20

UCLK edge to SIMO valid,

C_L= 20 pF, PMMCOREV = 0

18

ns

16

t_VALID,MOSIMO output data valid time⁽²⁾

2.4 V

3 V

UCLK edge to SIMO valid,

C_L= 20 pF, PMMCOREV = 3

15

1.8 V

3 V

–10

–8

C_L= 20 pF, PMMCOREV = 0

C_L= 20 pF, PMMCOREV = 3

t_HD,MO

SIMO output data hold time⁽³⁾

ns

2.4 V

3 V

–10

–8

(1) f_UCxCLK= 1/2t_LO/HIwith t_LO/HI≥ max(t_{VALID,MO(USCI)}+ t_SU,SI(Slave), t_SU,MI(USCI)+ t_{VALID,SO(Slave)}

)

For the slave parameters t_SU,SI(Slave)and t_{VALID,SO(Slave)}, see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams

in Figure 8-11 and Figure 8-12.

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(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data

on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure

8-11 and Figure 8-12.

1/f_UCxCLK

CKPL = 0

UCLK

CKPL = 1

t_LO/HI

t_SU,MI

t_HD,MI

SOMI

SIMO

t_HD,MO

t_VALID,MO

Figure 8-11. SPI Master Mode, CKPH = 0

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_LO/HI

t_HD,MI

t_SU,MI

SOMI

SIMO

t_HD,MO

t_VALID,MO

Figure 8-12. SPI Master Mode, CKPH = 1

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8.33 USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

(see Figure 8-13 and Figure 8-14)

PARAMETER

TEST CONDITIONS

V_CC

1.8 V

3 V

MIN

11

8

MAX UNIT

PMMCOREV = 0

t_STE,LEADSTE lead time, STE low to clock

ns

2.4 V

3 V

7

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

6

1.8 V

3 V

3

t_STE,LAG

t_STE,ACC

t_STE,DIS

t_SU,SI

STE lag time, Last clock to STE high

ns

2.4 V

3 V

3

1.8 V

3 V

66

50

ns

36

STE access time, STE low to SOMI data out

2.4 V

3 V

30

1.8 V

3 V

23

ns

16

STE disable time, STE high to SOMI high

impedance

2.4 V

3 V

13

1.8 V

3 V

5

2

5

SIMO input data setup time

SIMO input data hold time

SOMI output data valid time⁽²⁾

SOMI output data hold time⁽³⁾

ns

2.4 V

3 V

1.8 V

3 V

t_HD,SI

ns

2.4 V

3 V

1.8 V

3 V

76

UCLK edge to SOMI valid,

C_L= 20 pF, PMMCOREV = 0

60

ns

44

t_VALID,SO

2.4 V

3 V

UCLK edge to SOMI valid,

C_L= 20 pF, PMMCOREV = 3

40

1.8 V

3 V

18

12

10

8

C_L= 20 pF, PMMCOREV = 0

C_L= 20 pF, PMMCOREV = 3

t_HD,SO

ns

2.4 V

3 V

(1) f_UCxCLK= 1/2t_LO/HIwith t_LO/HI≥ max(t_{VALID,MO(Master)}+ t_SU,SI(USCI), t_{SU,MI(Master)}+ t_{VALID,SO(USCI)}

)

For the master parameters t_{SU,MI(Master)}and t_{VALID,MO(Master)}, see the SPI parameters of the attached master.

(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams

in Figure 8-13 and Figure 8-14.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure

8-13 and Figure 8-14.

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t_STE,LEAD

t_STE,LAG

STE

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_SU,SI

t_LO/HI

t_HD,SI

SIMO

SOMI

t_HD,SO

t_VALID,SO

t_STE,ACC

t_STE,DIS

Figure 8-13. SPI Slave Mode, CKPH = 0

t_STE,LEAD

t_STE,LAG

STE

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_LO/HI

t_HD,SI

t_SU,SI

SIMO

SOMI

t_HD,MO

t_VALID,SO

t_STE,ACC

t_STE,DIS

Figure 8-14. SPI Slave Mode, CKPH = 1

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8.34 USCI (I²C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see

Figure 8-15)

PARAMETER

USCI input clock frequency

SCL clock frequency

TEST CONDITIONS

V_CC

MIN

MAX UNIT

Internal: SMCLK or ACLK,

External: UCLK,

Duty cycle = 50% ±10%

f_USCI

f_SCL

f_SYSTEMMHz

2.2 V, 3 V

0

4.0

0.6

4.7

0.6

0

400

kHz

µs

f_SCL≤ 100 kHz

f_SCL> 100 kHz

f_SCL≤ 100 kHz

f_SCL> 100 kHz

t_HD,STAHold time (repeated) START

t_SU,STA

Setup time for a repeated START

2.2 V, 3 V

µs

t_HD,DATData hold time

t_SU,DATData setup time

2.2 V, 3 V

ns

250

4.0

0.6

50

f_SCL≤ 100 kHz

f_SCL> 100 kHz

t_SU,STOSetup time for STOP

2.2 V, 3 V

µs

ns

2.2 V

3 V

600

t_SP

Pulse duration of spikes suppressed by input filter

50

t_HD,STA

t_SU,STA

t_HD,STA

t_BUF

SDA

SCL

t_LOW

t_HIGH

t_SP

t_SU,DAT

t_SU,STO

t_HD,DAT

Figure 8-15. I²C Mode Timing

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8.35 12-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

2.2

0

TYP

MAX UNIT

AVCC and DVCC are connected together,

AVSS and DVSS are connected together,

V_(AVSS)= V_(DVSS)= 0 V

AV_CC

Analog supply voltage

Analog input voltage range⁽²⁾

3.6

V

V_(Ax)

All ADC12 analog input pins Ax

f_ADC12CLK= 5.0 MHz⁽⁴⁾

AV_CC

155

V

2.2 V

3 V

125

150

Operating supply current into

AVCC terminal⁽³⁾

I_{ADC12_A}

µA

220

Only one terminal Ax can be selected at one

time

C_I

R_I

Input capacitance

2.2 V

20

25

pF

Ω

Input MUX ON resistance

0 V ≤ V_Ax≤ AVCC

10

200

1900

(1) The leakage current is specified by the digital I/O input leakage.

(2) The analog input voltage range must be within the selected reference voltage range V_R+to V_R–for valid conversion results. If the

reference voltage is supplied by an external source or if the internal reference voltage is used and REFOUT = 1, then decoupling

capacitors are required (see Section 8.40 and Section 8.41).

(3) The internal reference supply current is not included in current consumption parameter I_{ADC12_A}

(4) ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0

.

8.36 12-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

For specified performance of ADC12 linearity

parameters using an external reference

voltage or AVCC as reference⁽¹⁾

0.45

4.8

5.0

f_ADC12CLK

ADC conversion clock

For specified performance of ADC12 linearity 2.2 V, 3 V

parameters using the internal reference⁽²⁾

MHz

4.0

0.45

4.2

2.4

4.8

For specified performance of ADC12 linearity

parameters using the internal reference⁽³⁾

2.7

Internal ADC12

oscillator⁽⁴⁾

f_ADC12OSC

t_CONVERT

t_Sample

ADC12DIV = 0, f_ADC12CLK= f_ADC12OSC

2.2 V, 3 V

5.4 MHz

REFON = 0, Internal oscillator,

ADC12OSC used for ADC conversion clock

2.4

3.1

µs

Conversion time

Sampling time

External f_ADC12CLKfrom ACLK, MCLK, or

SMCLK, ADC12SSEL ≠ 0

13 ×

1 / f_ADC12CLK

R_S= 400 Ω, R_I= 1000 Ω, C_I= 20 pF,

τ = (R_S+ R_I) × C_I

2.2 V, 3 V

1000

ns

(5)

(1) REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0,

SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the

specified performance of the ADC12 linearity is ensured with f_ADC12CLKmaximum of 5.0 MHz.

(2) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1

(3) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when

using the ADC12OSC divided by 2.

(4) The ADC12OSC is sourced directly from MODOSC inside the UCS.

(5) Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB:

t_Sample= ln(2ⁿ⁺¹) × R_S+ R_I) × C_I+ 800 ns, where n = ADC resolution = 12, R_S= external source resistance

40

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8.37 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference

Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Integral linearity error⁽¹⁾

Differential linearity error⁽¹⁾

Offset error⁽³⁾

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

1.4 V ≤ dVREF ≤ 1.6 V⁽²⁾

±2.0

LSB

±1.7

E_I

2.2 V, 3 V

1.6 V < dVREF⁽²⁾

(2)

E_D

E_O

E_G

E_T

±1.0 LSB

dVREF ≤ 2.2 V⁽²⁾

±1.0

±1.4

±2.0

LSB

±2.0

dVREF > 2.2 V⁽²⁾

Gain error⁽³⁾

±2.0 LSB

(2)

dVREF ≤ 2.2 V⁽²⁾

dVREF > 2.2 V⁽²⁾

±3.5

LSB

±3.5

Total unadjusted error

(1) Parameters are derived using the histogram method.

(2) The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = V_R+– V_R-, V_R+< AVCC, V_R–

>

AVSS. Unless otherwise mentioned, dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω and two decoupling

capacitors, 10 µF and 100 nF, should be connected to VREF+ and VREF- to decouple the dynamic current. See also the MSP430F5xx

and MSP430F6xx Family User's Guide.

(3) Parameters are derived using a best fit curve.

8.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS⁽¹⁾

V_CC

MIN

TYP

MAX UNIT

ADC12SR = 0, REFOUT = 1

f_ADC12CLK≤ 4.0 MHz

f_ADC12CLK≤ 2.7 MHz

f_ADC12CLK≤ 4.0 MHz

f_ADC12CLK≤ 2.7 MHz

f_ADC12CLK≤ 4.0 MHz

f_ADC12CLK≤ 2.7 MHz

f_ADC12CLK≤ 4.0 MHz

f_ADC12CLK≤ 2.7 MHz

f_ADC12CLK≤ 4.0 MHz

f_ADC12CLK≤ 2.7 MHz

±1.7

LSB

±2.5

Integral linearity

error⁽²⁾

E_I

2.2 V, 3 V

ADC12SR = 0, REFOUT = 0

ADC12SR = 0, REFOUT = 1

ADC12SR = 0, REFOUT = 0

ADC12SR = 0, REFOUT = 1

ADC12SR = 0, REFOUT = 0

ADC12SR = 0, REFOUT = 1

ADC12SR = 0, REFOUT = 0

ADC12SR = 0, REFOUT = 1

ADC12SR = 0, REFOUT = 0

–1.0

+2.0

Differential

E_D

2.2 V, 3 V

+1.5 LSB

+2.5

linearity error⁽²⁾

±1.0

±2.0

LSB

±2.0

E_O

E_G

E_T

Offset error⁽³⁾

Gain error⁽³⁾

2.2 V, 3 V

±2.0 LSB

±1.5%⁽⁴⁾VREF

±3.5 LSB

±1.4

Total unadjusted

error

±1.5%⁽⁴⁾VREF

(1) The internal reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 1. dVREF = V_R+– V_R–

.

(2) Parameters are derived using the histogram method.

(3) Parameters are derived using a best fit curve.

(4) The gain error and total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In this

mode the reference voltage used by the ADC12_A is not available on a pin.

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8.39 12-Bit ADC, Temperature Sensor and Built-In V_MID

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER⁽¹⁾

TEST CONDITIONS

V_CC

2.2 V

3 V

MIN

TYP

680

2.25

MAX UNIT

ADC12ON = 1, INCH = 0Ah,

T_A= 0°C

V_SENSOR

See ⁽²⁾

mV

2.2 V

3 V

TC_SENSOR

ADC12ON = 1, INCH = 0Ah

mV/°C

µs

2.2 V

3 V

100

Sample time required if

channel 10 is selected⁽³⁾

ADC12ON = 1, INCH = 0Ah,

Error of conversion result ≤ 1 LSB

t_{SENSOR(sample)}

AV_CCdivider at channel 11,

V_AVCCfactor

0.48

0.5

0.52

V

ADC12ON = 1, INCH = 0Bh

AVCC AVCC AVCC

V_MID

2.2 V

3 V

1.06

1.44

1.1

1.5

1.14

1.56

AV_CCdivider at channel 11

V

Sample time required if

channel 11 is selected⁽⁴⁾

ADC12ON = 1, INCH = 0Bh,

Error of conversion result ≤ 1 LSB

t_VMID(sample)

2.2 V, 3 V

1000

ns

(1) The temperature sensor is provided by the REF module. See the REF module parametric, I_REF+, regarding the current consumption of

the temperature sensor.

(2) The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in

temperature sensor. The TLV structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference

voltage levels. The sensor voltage can be computed as V_SENSE= TC_SENSOR× (Temperature,°C) + V_SENSOR, where TC_SENSORand

V_SENSORcan be computed from the calibration values for higher accuracy. See also the MSP430F5xx and MSP430F6xx Family User's

Guide.

(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t_SENSOR(on)

(4) The on-time t_VMID(on)is included in the sampling time t_VMID(sample); no additional on time is needed.

.

1000

950

900

850

800

750

700

650

600

550

500

-40 -30 -20 -10

0 10 20 30 40 50 60 70 80

Ambient Temperature (°C)

Figure 8-16. Typical Temperature Sensor Voltage

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8.40 REF, External Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

1.4 AVCC

1.2

1.4 AVCC

MAX UNIT

Positive external reference voltage

input

(2)

V_eREF+

V_eREF+> V_REF–/V_eREF–

V

Negative external reference voltage

input

(3)

V_REF–/V_eREF–

V_eREF+> V_REF–/V_eREF–

0

(V_eREF+

–

Differential external reference

voltage input

(4)

V_eREF+> V_REF–/V_eREF–

1.4 V ≤ V_eREF+≤ V_AVCC

V_REF–/V_eREF–

)

,

V_eREF–= 0 V, f_ADC12CLK= 5 MHz,

ADC12SHTx = 1h,

Conversion rate 200 ksps

2.2 V, 3 V

–26

26

1

I_VeREF+,

I_{VREF-/VeREF–}

Static input current

µA

µF

1.4 V ≤ V_eREF+≤ V_AVCC

,

V_eREF–= 0 V, f_ADC12CLK= 5 MHz,

ADC12SHTx = 8h,

Conversion rate 20 ksps

–1

10

Capacitance at VREF+ or VREF-

terminal

(5)

C_VREF+/-

(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, C_i, is

also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the

recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.

(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced

accuracy requirements.

(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced

accuracy requirements.

(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with

reduced accuracy requirements.

(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external

reference source if it is used for the ADC12_A. See also the MSP430F5xx and MSP430F6xx Family User's Guide.

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8.41 REF, Built-In Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

REFVSEL = {2} for 2.5 V,

3 V

2.4625

2.50 2.5375

1.98 2.0097

1.49 1.5124

REFON = REFOUT = 1, I_VREF+= 0 A

Positive built-in reference voltage REFVSEL = {1} for 2.0 V,

V_REF+

3 V

1.9503

1.4677

V

output

REFON = REFOUT = 1, I_VREF+= 0 A

REFVSEL = {0} for 1.5 V,

REFON = REFOUT = 1, I_VREF+= 0 A

2.2 V, 3 V

REFVSEL = {0} for 1.5 V

REFVSEL = {1} for 2.0 V

REFVSEL = {2} for 2.5 V

2.2

2.3

2.8

AVCC minimum voltage, Positive

built-in reference active

AV_CC(min)

ADC12SR = 1⁽⁴⁾, REFON = 1, REFOUT = 0,

REFBURST = 0

3 V

70

0.45

210

100

0.75

310

1.7

µA

mA

µA

ADC12SR = 1⁽⁴⁾, REFON = 1, REFOUT = 1,

REFBURST = 0

Operating supply current into

AVCC terminal^{(2) (3)}

I_REF+

ADC12SR = 0⁽⁴⁾, REFON = 1, REFOUT = 0,

REFBURST = 0

ADC12SR = 0⁽⁴⁾, REFON = 1, REFOUT = 1,

REFBURST = 0

0.95

mA

REFVSEL = {0, 1, 2},

Load-current regulation, VREF+ I_VREF+= +10 µA or –1000 µA,

terminal⁽⁵⁾

AVCC = AVCC(min) for each reference level,

REFVSEL = {0, 1, 2}, REFON = REFOUT = 1

I_L(VREF+)

2500 µV/mA

C_VREF+

TC_REF+

Capacitance at VREF+ terminals REFON = REFOUT = 1

20

100

pF

I_VREF+= 0 A,

REFVSEL = {0, 1, 2}, REFON = 1,

REFOUT = 0 or 1

Temperature coefficient of built-in

30

50 ppm/ °C

300 µV/V

reference⁽⁶⁾

AV_CC= AV_CC(min)to AV_CC(max)

Power supply rejection ratio (DC) T_A= 25°C, REFVSEL = {0, 1, 2}, REFON = 1,

REFOUT = 0 or 1

,

PSRR_DC

PSRR_AC

120

AV_CC= AV_CC(min)to AV_CC(max)

,

T_A= 25°C, f = 1 kHz, ΔVpp = 100 mV,

REFVSEL = {0, 1, 2}, REFON = 1,

REFOUT = 0 or 1

Power supply rejection ratio (AC)

6.4

75

mV/V

AV_CC= AV_CC(min)to AV_CC(max)

,

REFVSEL = {0, 1, 2}, REFOUT = 0,

REFON = 0 → 1

Settling time of reference

voltage⁽⁷⁾

t_SETTLE

µs

AV_CC= AV_CC(min)to AV_CC(max)

C_VREF= C_VREF(max),

,

REFVSEL = {0, 1, 2}, REFOUT = 1,

REFON = 0 → 1

(1) The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers,

one smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal and is

used as the reference for the conversion and uses the larger buffer. When REFOUT = 0, the reference is used only as the reference

for the conversion and uses the smaller buffer.

(2) The internal reference current is supplied through the AVCC terminal. Consumption is independent of the ADC12ON control bit, unless

a conversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current

contribution of the larger buffer without external load.

(3) The temperature sensor is provided by the REF module. Its current is supplied through the AVCC terminal and is equivalent to I_REF+

with REFON =1 and REFOUT = 0.

(4) For devices without the ADC12, the parametrics with ADC12SR = 0 are applicable.

(5) Contribution is due only to the reference and buffer including package. This does not include resistance due to PCB trace and other

factors.

(6) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).

(7) The condition is that the error in a conversion started after t_REFONis less than ±0.5 LSB. The settling time depends on the external

capacitive load when REFOUT = 1.

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8.42 Comparator B

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

V_CC

Supply voltage

1.8

3.6

40

50

65

30

0.5

V

1.8 V

2.2 V

3 V

CBPWRMD = 00

30

40

Comparator operating supply

I_{AVCC_COMP}current into AVCC, Excludes

reference resistor ladder

µA

CBPWRMD = 01

CBPWRMD = 10

10

2.2 V, 3 V

0.1

Quiescent current of local reference

I_{AVCC_REF}

CBREFACC = 1, CBREFLx = 01

22

µA

V

voltage amplifier into AVCC

V_IC

Common mode input range

Input offset voltage

0

V_CC– 1

±20

CBPWRMD = 00

V_OFFSET

C_IN

mV

CBPWRMD = 01, 10

±10

Input capacitance

5

3

pF

kΩ

On (switch closed)

4

R_SIN

Series input resistance

Off (switch open)

30

MΩ

CBPWRMD = 00, CBF = 0

CBPWRMD = 01, CBF = 0

CBPWRMD = 10, CBF = 0

450

600

50

ns

µs

t_PD

Propagation delay, response time

Propagation delay with filter active

CBPWRMD = 00, CBON = 1,

CBF = 1, CBFDLY = 00

0.35

0.6

1.0

1.8

0.6

1.0

1.8

3.4

1

1.0

1.8

3.4

6.5

2

CBPWRMD = 00, CBON = 1,

CBF = 1, CBFDLY = 01

t_PD,filter

µs

CBPWRMD = 00, CBON = 1,

CBF = 1, CBFDLY = 10

CBPWRMD = 00, CBON = 1,

CBF = 1, CBFDLY = 11

CBON = 0 to CBON = 1,

CBPWRMD = 00, 01

t_{EN_CMP}

Comparator enable time

µs

CBON = 0 to CBON = 1,

CBPWRMD = 10

100

1.5

t_{EN_REF}

Resistor reference enable time

Reference voltage for a given tap

CBON = 0 to CBON = 1

1

µs

V

VIN ×

(n + 1)

/ 32

VIN = reference into resistor ladder

(n = 0 to 31)

V_{CB_REF}

8.43 Ports PU.0 and PU.1

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see

Figure 8-17 through Figure 8-19)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

V_LDOO= 3.3 V ±10%, I_OH= –25 mA,

See Figure 8-18 for typical characteristics

V_OH

V_OL

V_IH

V_IL

High-level output voltage

2.4

V

V_LDOO= 3.3 V ±10%, I_OL= 25 mA,

See Figure 8-17 for typical characteristics

Low-level output voltage

High-level input voltage

Low-level input voltage

0.4

V

V_LDOO= 3.3 V ±10%,

See Figure 8-19 for typical characteristics

2.0

V_LDOO= 3.3 V ±10%,

See Figure 8-19 for typical characteristics

0.8

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90

V_CC= 3.0 V

T_A= 25ºC

V_CC= 3.0 V

T_A= 85ºC

80

70

60

50

40

30

20

10

0

V_CC= 1.8 V

T_A= 25ºC

V_CC= 1.8 V

T_A= 85ºC

0

0.1 0.2 0.3 0.4 0.5

0.6 0.7 0.8 0.9

1

1.1 1.2

V_OL– Low-Level Output Voltage – V

Figure 8-17. Ports PU.0, PU.1 Typical Low-Level Output Current vs Low-Level Output Voltage

0

-10

-20

-30

V_CC= 1.8 V

T_A= 85ºC

-40

-50

V_CC= 3.0 V

T_A= 85ºC

-60

V_CC= 1.8 V

-70

T_A= 25ºC

V_CC= 3.0 V

T_A= 25ºC

-80

-90

0.5

1

1.5

2

2.5

3

V_OH– High-Level Output Voltage – V

Figure 8-18. Ports PU.0, PU.1 Typical High-Level Output Current vs High-Level Output Voltage

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2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

T_A= 25°C, 85°C

V_IT+, postive-going input threshold

V_IT–, negative-going input threshold

1.8

2.2

2.6 3

V_LDOO– LDOO Supply Voltage – V

3.4

Figure 8-19. Ports PU.0, PU.1 Typical Input Threshold

8.44 LDO-PWR (LDO Power System)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

3.76

1.8

TYP

MAX UNIT

V_LAUNCHLDO input detection threshold

3.75

5.5

V

V_LDOI

V_LDO

LDO input voltage

LDO output voltage

3.3

±9%

3.6

V

V_{LDO_EXT}LDOO terminal input voltage with LDO disabled

LDO disabled

V

I_LDOO

I_DET

C_LDOI

C_LDOO

Maximum external current from LDOO terminal

LDO current overload detection⁽¹⁾

LDO is on

20

mA

µF

nF

60

100

LDOI terminal recommended capacitance

LDOO terminal recommended capacitance

4.7

220

Within 2%, recommended

capacitances

t_ENABLE

Settling time V_LDO

2

ms

(1) A current overload is detected when the total current supplied from the LDO exceeds this value.

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8.45 Flash Memory

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

T_J

MIN

TYP

MAX UNIT

DV_{CC(PGM/ERASE)}Program or erase supply voltage

1.8

3.6

5

V

mA

I_PGM

Average supply current from DVCC during program

3

6

I_ERASE

Average supply current from DVCC during erase

Average supply current from DVCC during mass erase or bank erase

Cumulative program time⁽¹⁾

15

16

mA

I_MERASE, I_BANK

t_CPT

mA

ms

Program and erase endurance

10⁴

100

64

10⁵

cycles

years

µs

t_Retention

t_Word

Data retention duration

25°C

Word or byte program time⁽²⁾

85

65

t_{Block, 0}

Block program time for first byte or word⁽²⁾

49

µs

Block program time for each additional byte or word, except for last byte or

word⁽²⁾

t_{Block, 1–(N–1)}

37

49

µs

t_{Block, N}

t_Erase

Block program time for last byte or word⁽²⁾

55

23

73

32

µs

Erase time for segment, mass erase, and bank erase (when available)⁽²⁾

ms

MCLK frequency in marginal read mode

(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)

f_MCLK,MGR

0

1

MHz

(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming

methods: individual word or byte write and block write modes.

(2) These values are hardwired into the state machine of the flash controller.

8.46 JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

V_CC

MIN

TYP

MAX UNIT

f_SBW

Spy-Bi-Wire input frequency

2.2 V, 3 V

0

20 MHz

t_SBW,Low

t_{SBW, En}

t_SBW,Rst

Spy-Bi-Wire low clock pulse duration

0.025

15

1

µs

Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)⁽¹⁾

Spy-Bi-Wire return to normal operation time

15

0

100

5

2.2 V

3 V

f_TCK

TCK input frequency, 4-wire JTAG⁽²⁾

Internal pulldown resistance on TEST

MHz

kΩ

0

10

80

R_internal

2.2 V, 3 V

45

60

(1) Tools that access the Spy-Bi-Wire interface must wait for the t_SBW,Entime after pulling the TEST/SBWTCK pin high before applying the

first SBWTCK clock edge.

(2) f_TCKmay be restricted to meet the timing requirements of the module selected.

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9 Detailed Description

9.1 CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,

other than program-flow instructions, are performed as register operations in conjunction with seven addressing

modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register

operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as

program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are

general-purpose registers (see Figure 9-1).

Peripherals are connected to the CPU using data, address, and control buses. The peripherals can be managed

with all instructions.

The instruction set consists of the original 51 instructions with three formats and seven address modes and

additional instructions for the expanded address range. Each instruction can operate on word and byte data.

Program Counter

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R4

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15

Figure 9-1. Integrated CPU Registers

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9.2 Operating Modes

The MCU has one active mode and six software-selectable low-power modes of operation. An interrupt event

can wake up the device from any of the low-power modes, service the request, and restore back to the low-

power mode on return from the interrupt program.

Software can configure the following operating modes:

•

Active mode (AM)

– All clocks are active

•

Low-power mode 0 (LPM0)

– CPU is disabled

– ACLK and SMCLK remain active

– MCLK is disabled

– FLL loop control remains active

Low-power mode 1 (LPM1)

– CPU is disabled

– FLL loop control is disabled

– ACLK and SMCLK remain active

– MCLK is disabled

Low-power mode 2 (LPM2)

– CPU is disabled

– MCLK, FLL loop control, and DCOCLK are disabled

– DC generator of the DCO remains enabled

– ACLK remains active

Low-power mode 3 (LPM3)

– CPU is disabled

– MCLK, FLL loop control, and DCOCLK are disabled

– DC generator of the DCO is disabled

– ACLK remains active

•

Low-power mode 4 (LPM4)

– CPU is disabled

– ACLK is disabled

– MCLK, FLL loop control, and DCOCLK are disabled

– DC generator of the DCO is disabled

– Crystal oscillator is stopped

– Complete data retention

•

Low-power mode 4.5 (LPM4.5)

– Internal regulator disabled

– No data retention

– Wake-up input from RST/NMI, P1, and P2

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9.3 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table

9-1). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 9-1. Interrupt Sources, Flags, and Vectors

SYSTEM

INTERRUPT

WORD

ADDRESS

INTERRUPT SOURCE

INTERRUPT FLAG

PRIORITY

System Reset

Power up

External reset

Watchdog time-out, password

violation

WDTIFG, KEYV (SYSRSTIV)^{(1) (3)}

Reset

0FFFEh

63, highest

Flash memory password violation

PMM password violation

System NMI

PMM

Vacant memory access

JTAG mailbox

SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,

VLRLIFG, VLRHIFG, VMAIFG, JMBINIFG,

JMBOUTIFG (SYSSNIV)⁽¹⁾

(Non)maskable

0FFFCh

0FFFAh

62

61

User NMI

NMI

Oscillator fault

NMIIFG, OFIFG, ACCVIFG, BUSIFG (SYSUNIV)

(1) (3)

Flash memory access violation

Comp_B

TB0

Comparator B interrupt flags (CBIV)^{(1) (2)}

TB0CCR0 CCIFG0 ⁽²⁾

Maskable

0FFF8h

0FFF6h

60

59

TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,

TB0IFG (TB0IV)^{(1) (2)}

TB0

Maskable

0FFF4h

0FFF2h

58

57

Watchdog Timer_A interval timer

mode

WDTIFG

USCI_A0 receive or transmit

USCI_B0 receive or transmit

ADC12_A

UCA0RXIFG, UCA0TXIFG (UCA0IV)^{(1) (2)}

UCB0RXIFG, UCB0TXIFG (UCB0IV)^{(1) (2)}

ADC12IFG0 to ADC12IFG15 (ADC12IV)^{(1) (2) (5)}

TA0CCR0 CCIFG0⁽²⁾

Maskable

0FFF0h

0FFEEh

0FFECh

0FFEAh

56

55

54

53

TA0

TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,

TA0IFG (TA0IV)^{(1) (2)}

TA0

Maskable

0FFE8h

52

LDO-PWR

DMA

LDOOFFIG, LDOONIFG, LDOOVLIFG

DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)^{(1) (2)}

TA1CCR0 CCIFG0⁽²⁾

Maskable

0FFE6h

0FFE4h

0FFE2h

51

50

49

TA1

TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,

TA1IFG (TA1IV)^{(1) (2)}

TA1

Maskable

0FFE0h

48

I/O port P1

USCI_A1 receive or transmit

USCI_B1 receive or transmit

TA2

P1IFG.0 to P1IFG.7 (P1IV)^{(1) (2)}

UCA1RXIFG, UCA1TXIFG (UCA1IV)^{(1) (2)}

UCB1RXIFG, UCB1TXIFG (UCB1IV)^{(1) (2)}

TA2CCR0 CCIFG0⁽²⁾

Maskable

0FFDEh

0FFDCh

0FFDAh

0FFD8h

47

46

45

44

TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,

TA2IFG (TA2IV)^{(1) (2)}

TA2

Maskable

0FFD6h

0FFD4h

0FFD2h

43

42

41

I/O port P2

RTC_A

P2IFG.0 to P2IFG.7 (P2IV)^{(1) (2)}

RTCRDYIFG, RTCTEVIFG, RTCAIFG,

RT0PSIFG, RT1PSIFG (RTCIV)^{(1) (2)}

0FFD0h

⋮

40

Reserved

Reserved⁽⁴⁾

⋮

0FF80h

0, lowest

(1) Multiple source flags

(2) Interrupt flags are in the module.

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(3) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.

(Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it.

(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To

maintain compatibility with other devices, TI recommends reserving these locations.

(5) Only on devices with ADC, otherwise reserved.

9.4 Memory Organization

Table 9-2 summarizes the memory map for all devices.

Table 9-2. Memory Organization

MSP430F5325,

MSP430F5324

MSP430F5327,

MSP430F5326

MSP430F5329,

MSP430F5328

Memory (flash)

Main: interrupt vector

64KB

00FFFFh to 00FF80h

96KB

00FFFFh to 00FF80h

128KB

00FFFFh to 00FF80h

Total Size

Bank D

Bank C

Bank B

Bank A

Sector 3

Sector 2

Sector 1

Sector 0

Sector 7

Info A

32KB

0243FFh to 01C400h

N/A⁽¹⁾

N/A

32KB

01C3FFh to 014400h

32KB

01C3FFh to 014400h

N/A

Main: code memory

32KB

0143FFh to 00C400h

32KB

0143FFh to 00C400h

32KB

0143FFh to 00C400h

32KB

00C3FFh to 004400h

32KB

00C3FFh to 004400h

32KB

00C3FFh to 004400h

2 KB

N/A

0043FFh to 003C00h

2KB

003BFFh to 003400h

2KB

RAM

0033FFh to 002C00h

2KB

002BFFh to 002400h

2KB

0023FFh to 001C00h

128 B

0019FFh to 001980h

128 B

0019FFh to 001980h

128 B

0019FFh to 001980h

128 B

00197Fh to 001900h

128 B

00197Fh to 001900h

128 B

00197Fh to 001900h

Info B

Information memory (flash)

128 B

0018FFh to 001880h

128 B

0018FFh to 001880h

128 B

0018FFh to 001880h

Info C

128 B

00187Fh to 001800h

128 B

00187Fh to 001800h

128 B

00187Fh to 001800h

Info D

512 B

0017FFh to 001600h

512 B

0017FFh to 001600h

512 B

0017FFh to 001600h

BSL 3

512 B

0015FFh to 001400h

512 B

0015FFh to 001400h

512 B

0015FFh to 001400h

BSL 2

Bootloader (BSL) memory

(flash)

512 B

0013FFh to 001200h

512 B

0013FFh to 001200h

512 B

0013FFh to 001200h

BSL 1

512 B

0011FFh to 001000h

512 B

0011FFh to 001000h

512 B

0011FFh to 001000h

BSL 0

4KB

000FFFh to 0h

4KB

000FFFh to 0h

4KB

000FFFh to 0h

Peripherals

Size

(1) N/A = Not available.

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9.5 Bootloader (BSL)

The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the

device memory through the BSL is protected by an user-defined password. Use of the BSL requires four pins

(see Table 9-3). BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK

pins. For complete description of the features of the BSL and its implementation, see MSP430™ Flash Devices

Bootloader (BSL) User's Guide.

Table 9-3. BSL Pin Requirements and Functions

DEVICE SIGNAL

BSL FUNCTION

Entry sequence signal

Data transmit

RST/NMI/SBWTDIO

TEST/SBWTCK

P1.1

P1.2

VCC

VSS

Data receive

Power supply

Ground supply

9.6 JTAG Operation

9.6.1 JTAG Standard Interface

The MSP430 family supports the standard JTAG interface, which requires four signals for sending and receiving

data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin enables the JTAG signals.

In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430 development tools and

device programmers. Table 9-4 lists the JTAG pin requirements. For further details on interfacing to development

tools and device programmers, see the MSP430 Hardware Tools User's Guide. For complete description of the

features of the JTAG interface and its implementation, see MSP430 Programming With the JTAG Interface.

Table 9-4. JTAG Pin Requirements and Functions

DEVICE SIGNAL

DIRECTION

FUNCTION

JTAG clock input

JTAG state control

JTAG data input, TCLK input

JTAG data output

Enable JTAG pins

External reset

PJ.3/TCK

IN

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

IN

OUT

IN

TEST/SBWTCK

RST/NMI/SBWTDIO

VCC

IN

Power supply

VSS

Ground supply

9.6.2 Spy-Bi-Wire Interface

In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. Spy-

Bi-Wire can be used to interface with MSP430 development tools and device programmers. Table 9-5 lists the

Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and device

programmers, see the MSP430 Hardware Tools User's Guide. For complete description of the features of the

JTAG interface and its implementation, see MSP430 Programming With the JTAG Interface.

Table 9-5. Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL

TEST/SBWTCK

RST/NMI/SBWTDIO

VCC

DIRECTION

FUNCTION

Spy-Bi-Wire clock input

Spy-Bi-Wire data input/output

Power supply

IN

IN, OUT

VSS

Ground supply

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9.7 Flash Memory

The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the

CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the

flash memory include:

•

Flash memory has n segments of main memory and four segments of information memory (A to D) of

128 bytes each. Each segment in main memory is 512 bytes in size.

•

Segments 0 to n may be erased in one step, or each segment may be individually erased.

Segments A to D can be erased individually. Segments A to D are also called information memory.

Segment A can be locked separately.

9.8 RAM

The RAM is made up of n sectors. Each sector can be completely powered down to save leakage; however, all

data are lost. Features of the RAM include:

•

RAM has n sectors. The size of a sector can be found in Section 9.4.

Each sector 0 to n can be complete disabled; however, data retention is lost.

Each sector 0 to n automatically enters low-power retention mode when possible.

9.9 Peripherals

Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be managed

using all instructions. For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's

Guide.

9.9.1 Digital I/O

Up to eight 8-bit I/O ports are implemented: for 80-pin PN options, P1, P2, P3, P4, P5, P6, and P7 are complete,

and P8 is reduced to 3-bit I/O. For 80-pin ZXH or ZQE and 64-pin RGC options, P3 and P5 are reduced to 5-bit

I/O and 6-bit I/O, respectively, and P7 and P8 are completely removed. Port PJ contains four individual I/O ports,

common to all devices.

•

All individual I/O bits are independently programmable.

Any combination of input, output, and interrupt conditions is possible.

Pullup or pulldown on all ports is programmable.

Drive strength on all ports is programmable.

Edge-selectable interrupt and LPM4.5 wake-up input capability is available for all bits of ports P1 and P2.

Read and write access to port-control registers is supported by all instructions.

Ports can be accessed byte-wise (P1 through P8) or word-wise in pairs (PA through PD).

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9.9.2 Port Mapping Controller

The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4 (see

Table 9-6). Table 9-7 lists the default settings for all pins that support port mapping.

Table 9-6. Port Mapping Mnemonics and Functions

VALUE

PxMAPy MNEMONIC

INPUT PIN FUNCTION

OUTPUT PIN FUNCTION

DVSS

0

PM_NONE

None

PM_CBOUT0

PM_TB0CLK

–

Comparator_B output

–

1

2

3

TB0 clock input

PM_ADC12CLK

PM_DMAE0

–

ADC12CLK

DMAE0 input

–

PM_SVMOUT

PM_TB0OUTH

PM_TB0CCR0A

PM_TB0CCR1A

PM_TB0CCR2A

PM_TB0CCR3A

PM_TB0CCR4A

PM_TB0CCR5A

PM_TB0CCR6A

PM_UCA1RXD

PM_UCA1SOMI

PM_UCA1TXD

PM_UCA1SIMO

PM_UCA1CLK

PM_UCB1STE

PM_UCB1SOMI

PM_UCB1SCL

PM_UCB1SIMO

PM_UCB1SDA

PM_UCB1CLK

PM_UCA1STE

PM_CBOUT1

PM_MCLK

–

SVM output

TB0 high-impedance input TB0OUTH

TB0 CCR0 capture input CCI0A

TB0 CCR1 capture input CCI1A

TB0 CCR2 capture input CCI2A

TB0 CCR3 capture input CCI3A

TB0 CCR4 capture input CCI4A

TB0 CCR5 capture input CCI5A

TB0 CCR6 capture input CCI6A

–

4

5

TB0 CCR0 compare output Out0

TB0 CCR1 compare output Out1

TB0 CCR2 compare output Out2

TB0 CCR3 compare output Out3

TB0 CCR4 compare output Out4

TB0 CCR5 compare output Out5

TB0 CCR6 compare output Out6

6

7

8

9

10

USCI_A1 UART RXD (Direction controlled by USCI – input)

USCI_A1 SPI slave out master in (direction controlled by USCI)

USCI_A1 UART TXD (Direction controlled by USCI – output)

USCI_A1 SPI slave in master out (direction controlled by USCI)

USCI_A1 clock input/output (direction controlled by USCI)

USCI_B1 SPI slave transmit enable (direction controlled by USCI)

USCI_B1 SPI slave out master in (direction controlled by USCI)

USCI_B1 I²C clock (open drain and direction controlled by USCI)

USCI_B1 SPI slave in master out (direction controlled by USCI)

USCI_B1 I²C data (open drain and direction controlled by USCI)

USCI_B1 clock input/output (direction controlled by USCI)

USCI_A1 SPI slave transmit enable (direction controlled by USCI)

11

12

13

14

15

16

17

18

None

Comparator_B output

MCLK

19–30

Reserved

DVSS

Disables the output driver and the input Schmitt trigger to prevent parasitic

cross currents when applying analog signals.

31 (0FFh)⁽¹⁾

PM_ANALOG

(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are 5 bits wide, and the upper bits are ignored,

which results in a read value of 31.

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Table 9-7. Default Mapping

PxMAPy MNEMONIC

INPUT PIN FUNCTION

OUTPUT PIN FUNCTION

USCI_B1 SPI slave transmit enable (direction controlled by USCI)

USCI_A1 clock input/output (direction controlled by USCI)

P4.0/P4MAP0

PM_UCB1STE/PM_UCA1CLK

USCI_B1 SPI slave in master out (direction controlled by USCI)

USCI_B1 I²C data (open drain and direction controlled by USCI)

P4.1/P4MAP1

P4.2/P4MAP2

P4.3/P4MAP3

P4.4/P4MAP4

P4.5/P4MAP5

PM_UCB1SIMO/PM_UCB1SDA

PM_UCB1SOMI/PM_UCB1SCL

PM_UCB1CLK/PM_UCA1STE

PM_UCA1TXD/PM_UCA1SIMO

PM_UCA1RXD/PM_UCA1SOMI

USCI_B1 SPI slave out master in (direction controlled by USCI)

USCI_B1 I²C clock (open drain and direction controlled by USCI)

USCI_A1 SPI slave transmit enable (direction controlled by USCI)

USCI_B1 clock input/output (direction controlled by USCI)

USCI_A1 UART TXD (Direction controlled by USCI - output)

USCI_A1 SPI slave in master out (direction controlled by USCI)

USCI_A1 UART RXD (Direction controlled by USCI - input)

USCI_A1 SPI slave out master in (direction controlled by USCI)

P4.6/P4MAP6

P4.7/P4MAP7

PM_NONE

None

DVSS

9.9.3 Oscillator and System Clock

The clock system in the MSP430F532x family of devices is supported by the Unified Clock System (UCS)

module that includes support for a 32-kHz watch crystal oscillator (XT1 LF mode only; XT1 HF mode is not

supported), an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency

oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency crystal

oscillator XT2. The UCS module is designed to meet the requirements of both low system cost and low power

consumption. The UCS module features digital frequency-locked loop (FLL) hardware that, in conjunction with a

digital modulator, stabilizes the DCO frequency to a programmable multiple of the selected FLL reference

frequency. The internal DCO provides a fast turnon clock source and stabilizes in 3.5 µs (typical). The UCS

module provides the following clock signals:

•

Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the

internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal DCO.

Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made

available to ACLK.

Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by

same sources made available to ACLK.

ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.

9.9.4 Power-Management Module (PMM)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains

programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor

(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is

implemented to provide the proper internal reset signal to the device during power-on and power-off. The

SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply

voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not

automatically reset). SVS and SVM circuitry are available on the primary supply and core supply.

9.9.5 Hardware Multiplier (MPY)

The multiplication operation is supported by a dedicated peripheral module. The module performs operations

with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication as well as signed

and unsigned multiply-and-accumulate operations.

9.9.6 Real-Time Clock (RTC_A)

The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated real-

time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers that

can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Calendar mode

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integrates an internal calendar which compensates for months with less than 31 days and includes leap year

correction. The RTC_A also supports flexible alarm functions and offset-calibration hardware.

9.9.7 Watchdog Timer (WDT_A)

The primary function of the WDT_A module is to perform a controlled system restart after a software problem

occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed

in an application, the module can be configured as an interval timer and can generate interrupts at selected time

intervals.

9.9.8 System Module (SYS)

The SYS module handles many of the system functions within the device. These functions include power on

reset and power up clear handling, NMI source selection and management, reset interrupt vector generators,

bootloader entry mechanisms, and configuration management (device descriptors). The SYS module also

includes a data exchange mechanism through JTAG called a JTAG mailbox that can be used in the application.

Table 9-8 lists the SYS module interrupt vector registers.

Table 9-8. System Module Interrupt Vector Registers

INTERRUPT VECTOR REGISTER

ADDRESS

INTERRUPT EVENT

No interrupt pending

Brownout (BOR)

RST/NMI (POR)

PMMSWBOR (BOR)

Wake up from LPMx.5

Security violation (BOR)

SVSL (POR)

VALUE

00h

PRIORITY

02h

Highest

04h

06h

08h

0Ah

0Ch

0Eh

SVSH (POR)

SVML_OVP (POR)

SVMH_OVP (POR)

PMMSWPOR (POR)

WDT time-out (PUC)

WDT password violation (PUC)

KEYV flash password violation (PUC)

Reserved

10h

SYSRSTIV, System Reset

019Eh

12h

14h

16h

18h

1Ah

1Ch

1Eh

Peripheral area fetch (PUC)

PMM password violation (PUC)

Reserved

20h

22h to 3Eh

00h

Lowest

Highest

No interrupt pending

SVMLIFG

02h

SVMHIFG

04h

SVSMLDLYIFG

06h

SVSMHDLYIFG

08h

SYSSNIV, System NMI

019Ch

VMAIFG

0Ah

JMBINIFG

0Ch

0Eh

JMBOUTIFG

SVMLVLRIFG

10h

SVMHVLRIFG

12h

Reserved

14h to 1Eh

00h

Lowest

Highest

No interrupt pending

NMIIFG

SYSUNIV, User NMI

019Ah

02h

OFIFG

04h

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Table 9-8. System Module Interrupt Vector Registers (continued)

INTERRUPT VECTOR REGISTER

ADDRESS

INTERRUPT EVENT

VALUE

06h

ACCVIFG

Reserved

08h

Reserved

0Ah to 1Eh

Lowest

9.9.9 DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU intervention.

For example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM.

Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces

system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move

data to or from a peripheral. Table 9-9 lists the available DMA triggers.

Table 9-9. DMA Trigger Assignments

CHANNEL

TRIGGER⁽¹⁾

0

1

2

0

DMAREQ

1

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TA2CCR0 CCIFG

TA2CCR2 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

Reserved

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TA2CCR0 CCIFG

TA2CCR2 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

Reserved

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TA2CCR0 CCIFG

TA2CCR2 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

Reserved

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

Reserved

UCA0RXIFG

UCA0TXIFG

UCB0RXIFG

UCB0TXIFG

UCA1RXIFG

UCA1TXIFG

UCB1RXIFG

UCB1TXIFG

ADC12IFGx

Reserved

UCA0RXIFG

UCA0TXIFG

UCB0RXIFG

UCB0TXIFG

UCA1RXIFG

UCA1TXIFG

UCB1RXIFG

UCB1TXIFG

ADC12IFGx

Reserved

UCA0RXIFG

UCA0TXIFG

UCB0RXIFG

UCB0TXIFG

UCA1RXIFG

UCA1TXIFG

UCB1RXIFG

UCB1TXIFG

ADC12IFGx

Reserved

MPY ready

DMA2IFG

DMA0IFG

DMA1IFG

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Table 9-9. DMA Trigger Assignments (continued)

CHANNEL

TRIGGER⁽¹⁾

0

1

2

31

DMAE0

(1) If a reserved trigger source is selected, no trigger is generated.

9.9.10 Universal Serial Communication Interface (USCI)

The USCI modules are used for serial data communication. The USCI module supports synchronous

communication protocols such as SPI (3- or 4-pin) and I²C, and asynchronous communication protocols such as

UART, enhanced UART with automatic baud-rate detection, and IrDA. Each USCI module contains two portions,

A and B.

The USCI_An module provides support for SPI (3- or 4-pin), UART, enhanced UART, or IrDA.

The USCI_Bn module provides support for SPI (3- or 4-pin) or I²C.

The MSP430F532x series includes two complete USCI modules (n = 0, 1).

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9.9.11 TA0

TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compares. TA0 can support multiple capture/

compares, PWM outputs, and interval timing (see Table 9-10). TA0 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compares.

Table 9-10. TA0 Signal Connections

INPUT PIN NUMBER

OUTPUT PIN NUMBER

DEVICE

INPUT

SIGNAL

MODULE

INPUT

SIGNAL

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

MODULE

BLOCK

RGC, ZXH,

PN

RGC, ZXH, ZQE

PN

ZQE

18, H2-P1.0

21-P1.0

TA0CLK

TACLK

ACLK

(internal)

Timer

NA

SMCLK

(internal)

SMCLK

18, H2-P1.0

19, H3-P1.1

21-P1.0

22-P1.1

TA0CLK

TA0.0

DV_SS

TACLK

CCI0A

CCI0B

GND

19, H3-P1.1

20, J3-P1.2

22-P1.1

23-P1.2

CCR0

CCR1

TA0

TA1

TA0.0

TA0.1

DV_SS

DV_CC

TA0.1

V_CC

20, J3-P1.2

21, G4-P1.3

23-P1.2

24-P1.3

CCI1A

CBOUT

(internal)

ADC12 (internal) ADC12 (internal)

ADC12SHSx = {1} ADC12SHSx = {1}

CCI1B

DV_SS

DV_CC

TA0.2

GND

V_CC

CCI2A

21, G4-P1.3

24-P1.3

ACLK

(internal)

CCI2B

CCR2

TA2

TA0.2

DV_SS

DV_CC

TA0.3

DV_SS

DV_CC

TA0.4

DV_SS

DV_CC

GND

V_CC

22, H4-P1.4

23, J4-P1.5

25-P1.4

26-P1.5

CCI3A

CCI3B

GND

V_CC

22, H4-P1.4

23, J4-P1.5

25-P1.4

26-P1.5

CCR3

CCR4

TA3

TA4

TA0.3

TA0.4

CCI4A

CCI4B

GND

V_CC

60

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9.9.12 TA1

TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compares. TA1 can support multiple capture/

compares, PWM outputs, and interval timing (see Table 9-11). TA1 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compares.

Table 9-11. TA1 Signal Connections

INPUT PIN NUMBER

OUTPUT PIN NUMBER

DEVICE

INPUT

SIGNAL

MODULE

INPUT

SIGNAL

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

MODULE

BLOCK

RGC, ZXH,

PN

RGC, ZXH,

PN

ZQE

24, G5-P1.6

27-P1.6

TA1CLK

TACLK

ACLK

(internal)

Timer

NA

SMCLK

(internal)

SMCLK

24, G5-P1.6

25, H5-P1.7

27-P1.6

28-P1.7

TA1CLK

TA1.0

DV_SS

TACLK

CCI0A

CCI0B

GND

25, H5-P1.7

26, J5-P2.0

28-P1.7

29-P2.0

CCR0

CCR1

TA0

TA1

TA1.0

TA1.1

DV_SS

DV_CC

TA1.1

V_CC

26, J5-P2.0

27, G6-P2.1

29-P2.0

30-P2.1

CCI1A

CBOUT

(internal)

CCI1B

DV_SS

DV_CC

TA1.2

GND

V_CC

CCI2A

27, G6-P2.1

30-P2.1

ACLK

(internal)

CCI2B

CCR2

TA2

TA1.2

DV_SS

DV_CC

GND

V_CC

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9.9.13 TA2

TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compares. TA2 can support multiple capture/

compares, PWM outputs, and interval timing (see Table 9-12). TA2 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compares.

Table 9-12. TA2 Signal Connections

INPUT PIN NUMBER

OUTPUT PIN NUMBER

DEVICE

INPUT

SIGNAL

MODULE

INPUT

SIGNAL

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

MODULE

BLOCK

RGC, ZXH,

PN

RGC, ZXH,

PN

ZQE

28, J6-P2.2

31-P2.2

TA2CLK

TACLK

ACLK

(internal)

Timer

NA

SMCLK

(internal)

SMCLK

28, J6-P2.2

29, H6-P2.3

31-P2.2

32-P2.3

TA2CLK

TA2.0

DV_SS

TACLK

CCI0A

CCI0B

GND

29, H6-P2.3

30, J7-P2.4

32-P2.3

33-P2.4

CCR0

CCR1

TA0

TA1

TA2.0

TA2.1

DV_SS

DV_CC

TA2.1

V_CC

30, J7-P2.4

31, J8-P2.5

33-P2.4

34-P2.5

CCI1A

CBOUT

(internal)

CCI1B

DV_SS

DV_CC

TA2.2

GND

V_CC

CCI2A

31, J8-P2.5

34-P2.5

ACLK

(internal)

CCI2B

CCR2

TA2

TA2.2

DV_SS

DV_CC

GND

V_CC

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9.9.14 TB0

TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compares. TB0 can support multiple capture/

compares, PWM outputs, and interval timing (see Table 9-13). TB0 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compares.

Table 9-13. TB0 Signal Connections

INPUT PIN NUMBER

OUTPUT PIN NUMBER

DEVICE

INPUT

SIGNAL

MODULE

INPUT

SIGNAL

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

MODULE

BLOCK

RGC, ZXH,

PN

RGC, ZXH, ZQE⁽¹⁾

PN

ZQE⁽¹⁾

60-P7.7

TB0CLK

TBCLK

ACLK

(internal)

Timer

NA

SMCLK

(internal)

SMCLK

60-P7.7

55-P5.6

TB0CLK

TB0.0

TBCLK

CCI0A

55-P5.6

ADC12 (internal) ADC12 (internal)

ADC12SHSx = {2} ADC12SHSx = {2}

55-P5.6

TB0.0

CCI0B

CCR0

CCR1

TB0

TB1

TB0.0

TB0.1

DV_SS

DV_CC

TB0.1

GND

V_CC

56-P5.7

CCI1A

56-P5.7

CBOUT

(internal)

ADC12 (internal) ADC12 (internal)

ADC12SHSx = {3} ADC12SHSx = {3}

CCI1B

DV_SS

DV_CC

TB0.2

DV_SS

DV_CC

TB0.3

DV_SS

DV_CC

TB0.4

DV_SS

DV_CC

TB0.5

DV_SS

DV_CC

TB0.6

GND

V_CC

57-P7.4

CCI2A

CCI2B

GND

57-P7.4

58-P7.5

59-P7.6

42-P3.5

43-P3.6

CCR2

CCR3

CCR4

CCR5

TB2

TB3

TB4

TB5

TB0.2

TB0.3

TB0.4

TB0.5

V_CC

58-P7.5

CCI3A

CCI3B

GND

V_CC

59-P7.6

CCI4A

CCI4B

GND

V_CC

42-P3.5

CCI5A

CCI5B

GND

V_CC

43-P3.6

CCI6A

ACLK

(internal)

CCI6B

CCR6

TB6

TB0.6

DV_SS

DV_CC

GND

V_CC

(1) Timer functions are selectable through the port mapping controller.

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9.9.15 Comparator_B

The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions,

battery voltage supervision, and monitoring of external analog signals.

9.9.16 ADC12_A

The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR

core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversion-

and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU

intervention.

9.9.17 CRC16

The CRC16 module produces a signature based on a sequence of entered data values and can be used for data

checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.

9.9.18 REF Voltage Reference

The reference module (REF) is responsible for generation of all critical reference voltages that can be used by

the various analog peripherals in the device.

9.9.19 Embedded Emulation Module (EEM)

The EEM supports real-time in-system debugging. The L version of the EEM has the following features:

•

Eight hardware triggers or breakpoints on memory access

Two hardware trigger or breakpoint on CPU write access

Up to 10 hardware triggers can be combined to form complex triggers or breakpoints

Two cycle counters

Sequencer

State storage

Clock control on module level

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9.9.20 Peripheral File Map

Table 9-14 lists the base address and offset range for each module. Table 9-15 through Table 9-43 list all of the

available registers for each module.

Table 9-14. Peripherals

MODULE NAME

Special Functions (see Table 9-15)

BASE ADDRESS

0100h

0120h

0140h

0150h

0158h

015Ch

0160h

0180h

01B0h

01C0h

01E0h

0200h

0220h

0240h

0260h

0320h

0340h

0380h

03C0h

0400h

04A0h

04C0h

0500h

0510h

0520h

0530h

05C0h

05E0h

0600h

0620h

0700h

08C0h

0900h

OFFSET ADDRESS RANGE

000h to 01Fh

000h to 010h

000h to 00Fh

000h to 007h

000h to 001h

000h to 01Fh

000h to 001h

000h to 002h

000h to 007h

000h to 01Fh

000h to 00Bh

000h to 01Fh

000h to 02Eh

000h to 01Bh

000h to 02Fh

000h to 00Fh

000h to 00Ah

000h to 01Fh

000h to 03Eh

000h to 00Fh

000h to 014h

PMM (see Table 9-16)

Flash Control (see Table 9-17)

CRC16 (see Table 9-18)

RAM Control (see Table 9-19)

Watchdog (see Table 9-20)

UCS (see Table 9-21)

SYS (see Table 9-22)

Shared Reference (see Table 9-23)

Port Mapping Control (see Table 9-24)

Port Mapping Port P4 (see Table 9-24)

Port P1, P2 (see Table 9-25)

Port P3, P4 (see Table 9-26)

Port P5, P6 (see Table 9-27)

Port P7, P8 (see Table 9-28)

Port PJ (see Table 9-29)

TA0 (see Table 9-30)

TA1 (see Table 9-31)

TB0 (see Table 9-32)

TA2 (see Table 9-33)

Real-Time Clock (RTC_A) (see Table 9-34)

32-Bit Hardware Multiplier (see Table 9-35)

DMA General Control (see Table 9-36)

DMA Channel 0 (see Table 9-36)

DMA Channel 1 (see Table 9-36)

DMA Channel 2 (see Table 9-36)

USCI_A0 (see Table 9-37)

USCI_B0 (see Table 9-38)

USCI_A1 (see Table 9-39)

USCI_B1 (see Table 9-40)

ADC12_A (see Table 9-41)

Comparator_B (see Table 9-42)

LDO-PWR and Port U configuration (see Table 9-43)

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Table 9-15. Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION

REGISTER

OFFSET

SFR interrupt enable

SFR interrupt flag

SFRIE1

00h

02h

04h

SFRIFG1

SFRRPCR

SFR reset pin control

Table 9-16. PMM Registers (Base Address: 0120h)

REGISTER DESCRIPTION

REGISTER

PMMCTL0

PMMCTL1

SVSMHCTL

SVSMLCTL

PMMIFG

OFFSET

00h

PMM control 0

PMM control 1

02h

SVS high-side control

SVS low-side control

PMM interrupt flags

PMM interrupt enable

PMM power mode 5 control

04h

06h

0Ch

0Eh

PMMIE

PM5CTL0

10h

Table 9-17. Flash Control Registers (Base Address: 0140h)

REGISTER DESCRIPTION

REGISTER

OFFSET

00h

Flash control 1

Flash control 3

Flash control 4

FCTL1

FCTL3

04h

FCTL4

06h

Table 9-18. CRC16 Registers (Base Address: 0150h)

REGISTER DESCRIPTION

REGISTER

OFFSET

00h

CRC data input

CRC16DI

CRC data input reverse byte

CRC initialization and result

CRC result reverse byte

CRCDIRB

CRCINIRES

CRCRESR

02h

04h

06h

Table 9-19. RAM Control Registers (Base Address: 0158h)

REGISTER DESCRIPTION

REGISTER

OFFSET

RAM control 0

RCCTL0

00h

Table 9-20. Watchdog Registers (Base Address: 015Ch)

REGISTER DESCRIPTION

REGISTER

OFFSET

Watchdog timer control

WDTCTL

00h

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Table 9-21. UCS Registers (Base Address: 0160h)

REGISTER DESCRIPTION

REGISTER

UCSCTL0

UCSCTL1

UCSCTL2

UCSCTL3

UCSCTL4

UCSCTL5

UCSCTL6

UCSCTL7

UCSCTL8

OFFSET

00h

UCS control 0

UCS control 1

UCS control 2

UCS control 3

UCS control 4

UCS control 5

UCS control 6

UCS control 7

UCS control 8

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

Table 9-22. SYS Registers (Base Address: 0180h)

REGISTER DESCRIPTION

REGISTER

OFFSET

00h

System control

SYSCTL

Bootloader configuration area

JTAG mailbox control

SYSBSLC

SYSJMBC

SYSJMBI0

SYSJMBI1

SYSJMBO0

SYSJMBO1

SYSBERRIV

SYSUNIV

02h

06h

JTAG mailbox input 0

08h

JTAG mailbox input 1

0Ah

0Ch

0Eh

18h

JTAG mailbox output 0

JTAG mailbox output 1

Bus error vector generator

User NMI vector generator

System NMI vector generator

Reset vector generator

1Ah

1Ch

1Eh

SYSSNIV

SYSRSTIV

Table 9-23. Shared Reference Registers (Base Address: 01B0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Shared reference control

REFCTL

00h

Table 9-24. Port Mapping Registers

(Base Address of Port Mapping Control: 01C0h, Port P4: 01E0h)

REGISTER DESCRIPTION

REGISTER

PMAPKEYID

PMAPCTL

P4MAP0

P4MAP1

P4MAP2

P4MAP3

P4MAP4

P4MAP5

P4MAP6

P4MAP7

OFFSET

00h

Port mapping key/ID

Port mapping control

Port P4.0 mapping

Port P4.1 mapping

Port P4.2 mapping

Port P4.3 mapping

Port P4.4 mapping

Port P4.5 mapping

Port P4.6 mapping

Port P4.7 mapping

02h

00h

01h

02h

03h

04h

05h

06h

07h

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Table 9-25. Port P1, P2 Registers (Base Address: 0200h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P1 input

P1IN

00h

02h

04h

06h

08h

0Ah

0Eh

18h

1Ah

1Ch

01h

03h

05h

07h

09h

0Bh

1Eh

19h

1Bh

1Dh

Port P1 output

P1OUT

P1DIR

P1REN

P1DS

Port P1 direction

Port P1 resistor enable

Port P1 drive strength

Port P1 selection

P1SEL

P1IV

Port P1 interrupt vector word

Port P1 interrupt edge select

Port P1 interrupt enable

Port P1 interrupt flag

Port P2 input

P1IES

P1IE

P1IFG

P2IN

Port P2 output

P2OUT

P2DIR

P2REN

P2DS

Port P2 direction

Port P2 resistor enable

Port P2 drive strength

Port P2 selection

P2SEL

P2IV

Port P2 interrupt vector word

Port P2 interrupt edge select

Port P2 interrupt enable

Port P2 interrupt flag

P2IES

P2IE

P2IFG

Table 9-26. Port P3, P4 Registers (Base Address: 0220h)

REGISTER DESCRIPTION

REGISTER

OFFSET

00h

Port P3 input

P3IN

Port P3 output

P3OUT

P3DIR

P3REN

P3DS

02h

Port P3 direction

Port P3 resistor enable

Port P3 drive strength

Port P3 selection

Port P4 input

04h

06h

08h

P3SEL

P4IN

0Ah

01h

Port P4 output

P4OUT

P4DIR

P4REN

P4DS

03h

Port P4 direction

Port P4 resistor enable

Port P4 drive strength

Port P4 selection

05h

07h

09h

P4SEL

0Bh

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Table 9-27. Port P5, P6 Registers (Base Address: 0240h)

REGISTER DESCRIPTION

REGISTER

OFFSET

00h

Port P5 input

P5IN

Port P5 output

P5OUT

P5DIR

P5REN

P5DS

02h

Port P5 direction

Port P5 resistor enable

Port P5 drive strength

Port P5 selection

Port P6 input

04h

06h

08h

P5SEL

P6IN

0Ah

01h

Port P6 output

P6OUT

P6DIR

P6REN

P6DS

03h

Port P6 direction

Port P6 resistor enable

Port P6 drive strength

Port P6 selection

05h

07h

09h

P6SEL

0Bh

Table 9-28. Port P7, P8 Registers (Base Address: 0260h)

REGISTER DESCRIPTION

REGISTER

OFFSET

00h

Port P7 input

P7IN

Port P7 output

P7OUT

P7DIR

P7REN

P7DS

02h

Port P7 direction

Port P7 resistor enable

Port P7 drive strength

Port P7 selection

Port P8 input

04h

06h

08h

P7SEL

P8IN

0Ah

01h

Port P8 output

P8OUT

P8DIR

P8REN

P8DS

03h

Port P8 direction

Port P8 resistor enable

Port P8 drive strength

Port P8 selection

05h

07h

09h

P8SEL

0Bh

Table 9-29. Port J Registers (Base Address: 0320h)

REGISTER DESCRIPTION

REGISTER

OFFSET

00h

Port PJ input

PJIN

Port PJ output

PJOUT

PJDIR

02h

Port PJ direction

Port PJ resistor enable

Port PJ drive strength

04h

PJREN

PJDS

06h

08h

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Table 9-30. TA0 Registers (Base Address: 0340h)

REGISTER DESCRIPTION

REGISTER

OFFSET

TA0 control

TA0CTL

00h

02h

04h

06h

08h

0Ah

10h

12h

14h

16h

18h

1Ah

20h

2Eh

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

Capture/compare control 3

Capture/compare control 4

TA0 counter

TA0CCTL0

TA0CCTL1

TA0CCTL2

TA0CCTL3

TA0CCTL4

TA0R

Capture/compare 0

Capture/compare 1

Capture/compare 2

Capture/compare 3

Capture/compare 4

TA0 expansion 0

TA0CCR0

TA0CCR1

TA0CCR2

TA0CCR3

TA0CCR4

TA0EX0

TA0 interrupt vector

TA0IV

Table 9-31. TA1 Registers (Base Address: 0380h)

REGISTER DESCRIPTION

REGISTER

OFFSET

00h

TA1 control

TA1CTL

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

TA1 counter

TA1CCTL0

TA1CCTL1

TA1CCTL2

TA1R

02h

04h

06h

10h

Capture/compare 0

Capture/compare 1

Capture/compare 2

TA1 expansion 0

TA1CCR0

TA1CCR1

TA1CCR2

TA1EX0

12h

14h

16h

20h

TA1 interrupt vector

TA1IV

2Eh

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Table 9-32. TB0 Registers (Base Address: 03C0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

12h

14h

16h

18h

1Ah

1Ch

1Eh

20h

2Eh

TB0 control

TB0CTL

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

Capture/compare control 3

Capture/compare control 4

Capture/compare control 5

Capture/compare control 6

TB0 counter

TB0CCTL0

TB0CCTL1

TB0CCTL2

TB0CCTL3

TB0CCTL4

TB0CCTL5

TB0CCTL6

TB0R

Capture/compare 0

TB0CCR0

TB0CCR1

TB0CCR2

TB0CCR3

TB0CCR4

TB0CCR5

TB0CCR6

TB0EX0

Capture/compare 1

Capture/compare 2

Capture/compare 3

Capture/compare 4

Capture/compare 5

Capture/compare 6

TB0 expansion 0

TB0 interrupt vector

TB0IV

Table 9-33. TA2 Registers (Base Address: 0400h)

REGISTER DESCRIPTION

REGISTER

OFFSET

00h

TA2 control

TA2CTL

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

TA2 counter

TA2CCTL0

TA2CCTL1

TA2CCTL2

TA2R

02h

04h

06h

10h

Capture/compare 0

Capture/compare 1

Capture/compare 2

TA2 expansion 0

TA2CCR0

TA2CCR1

TA2CCR2

TA2EX0

12h

14h

16h

20h

TA2 interrupt vector

TA2IV

2Eh

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Table 9-34. Real-Time Clock Registers (Base Address: 04A0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

RTC control 0

RTCCTL0

00h

01h

02h

03h

08h

0Ah

0Ch

0Dh

0Eh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

RTC control 1

RTCCTL1

RTC control 2

RTCCTL2

RTC control 3

RTCCTL3

RTC prescaler 0 control

RTC prescaler 1 control

RTC prescaler 0

RTCPS0CTL

RTCPS1CTL

RTCPS0

RTC prescaler 1

RTCPS1

RTC interrupt vector word

RTC seconds/counter 1

RTC minutes/counter 2

RTC hours/counter 3

RTC day of week/counter 4

RTC days

RTCIV

RTCSEC/RTCNT1

RTCMIN/RTCNT2

RTCHOUR/RTCNT3

RTCDOW/RTCNT4

RTCDAY

RTC month

RTCMON

RTC year low

RTCYEARL

RTCYEARH

RTCAMIN

RTC year high

RTC alarm minutes

RTC alarm hours

RTC alarm day of week

RTC alarm day

RTCAHOUR

RTCADOW

RTCADAY

Table 9-35. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

12h

14h

16h

18h

1Ah

1Ch

1Eh

20h

22h

24h

26h

28h

2Ah

16-bit operand 1 – multiply

MPY

16-bit operand 1 – signed multiply

16-bit operand 1 – multiply accumulate

16-bit operand 1 – signed multiply accumulate

16-bit operand 2

MPYS

MAC

MACS

OP2

16 × 16 result low word

RESLO

RESHI

16 × 16 result high word

16 × 16 sum extension

SUMEXT

MPY32L

MPY32H

MPYS32L

MPYS32H

MAC32L

MAC32H

MACS32L

MACS32H

OP2L

32-bit operand 1 – multiply low word

32-bit operand 1 – multiply high word

32-bit operand 1 – signed multiply low word

32-bit operand 1 – signed multiply high word

32-bit operand 1 – multiply accumulate low word

32-bit operand 1 – multiply accumulate high word

32-bit operand 1 – signed multiply accumulate low word

32-bit operand 1 – signed multiply accumulate high word

32-bit operand 2 – low word

32-bit operand 2 – high word

OP2H

32 × 32 result 0 – least significant word

32 × 32 result 1

RES0

RES1

32 × 32 result 2

RES2

32 × 32 result 3 – most significant word

RES3

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Table 9-35. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h) (continued)

REGISTER DESCRIPTION

REGISTER

OFFSET

MPY32 control 0

MPY32CTL0

2Ch

Table 9-36. DMA Registers (Base Address DMA General Control: 0500h,

DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)

REGISTER DESCRIPTION

REGISTER

DMA0CTL

DMA0SAL

DMA0SAH

DMA0DAL

DMA0DAH

DMA0SZ

OFFSET

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Eh

DMA channel 0 control

DMA channel 0 source address low

DMA channel 0 source address high

DMA channel 0 destination address low

DMA channel 0 destination address high

DMA channel 0 transfer size

DMA channel 1 control

DMA1CTL

DMA1SAL

DMA1SAH

DMA1DAL

DMA1DAH

DMA1SZ

DMA channel 1 source address low

DMA channel 1 source address high

DMA channel 1 destination address low

DMA channel 1 destination address high

DMA channel 1 transfer size

DMA channel 2 control

DMA2CTL

DMA2SAL

DMA2SAH

DMA2DAL

DMA2DAH

DMA2SZ

DMA channel 2 source address low

DMA channel 2 source address high

DMA channel 2 destination address low

DMA channel 2 destination address high

DMA channel 2 transfer size

DMA module control 0

DMACTL0

DMACTL1

DMACTL2

DMACTL3

DMACTL4

DMAIV

DMA module control 1

DMA module control 2

DMA module control 3

DMA module control 4

DMA interrupt vector

Table 9-37. USCI_A0 Registers (Base Address: 05C0h)

REGISTER DESCRIPTION

REGISTER

UCA0CTL1

UCA0CTL0

UCA0BR0

OFFSET

00h

USCI control 1

USCI control 0

01h

USCI baud rate 0

06h

USCI baud rate 1

UCA0BR1

07h

USCI modulation control

USCI status

UCA0MCTL

UCA0STAT

UCA0RXBUF

UCA0TXBUF

UCA0ABCTL

UCA0IRTCTL

UCA0IRRCTL

UCA0IE

08h

0Ah

0Ch

0Eh

10h

USCI receive buffer

USCI transmit buffer

USCI LIN control

USCI IrDA transmit control

USCI IrDA receive control

USCI interrupt enable

USCI interrupt flags

12h

13h

1Ch

1Dh

UCA0IFG

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Table 9-37. USCI_A0 Registers (Base Address: 05C0h) (continued)

REGISTER DESCRIPTION

REGISTER

OFFSET

1Eh

USCI interrupt vector word

UCA0IV

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Table 9-38. USCI_B0 Registers (Base Address: 05E0h)

REGISTER DESCRIPTION

REGISTER

UCB0CTL1

UCB0CTL0

UCB0BR0

UCB0BR1

UCB0STAT

UCB0RXBUF

UCB0TXBUF

UCB0I2COA

UCB0I2CSA

UCB0IE

OFFSET

00h

USCI synchronous control 1

USCI synchronous control 0

USCI synchronous bit rate 0

USCI synchronous bit rate 1

USCI synchronous status

01h

06h

07h

0Ah

0Ch

0Eh

10h

USCI synchronous receive buffer

USCI synchronous transmit buffer

USCI I2C own address

USCI I2C slave address

USCI interrupt enable

12h

1Ch

1Dh

1Eh

USCI interrupt flags

UCB0IFG

USCI interrupt vector word

UCB0IV

Table 9-39. USCI_A1 Registers (Base Address: 0600h)

REGISTER DESCRIPTION

REGISTER

UCA1CTL1

UCA1CTL0

UCA1BR0

OFFSET

00h

USCI control 1

USCI control 0

01h

USCI baud rate 0

06h

USCI baud rate 1

UCA1BR1

07h

USCI modulation control

USCI status

UCA1MCTL

UCA1STAT

UCA1RXBUF

UCA1TXBUF

UCA1ABCTL

UCA1IRTCTL

UCA1IRRCTL

UCA1IE

08h

0Ah

0Ch

0Eh

10h

USCI receive buffer

USCI transmit buffer

USCI LIN control

USCI IrDA transmit control

USCI IrDA receive control

USCI interrupt enable

USCI interrupt flags

USCI interrupt vector word

12h

13h

1Ch

1Dh

1Eh

UCA1IFG

UCA1IV

Table 9-40. USCI_B1 Registers (Base Address: 0620h)

REGISTER DESCRIPTION

REGISTER

UCB1CTL1

UCB1CTL0

UCB1BR0

UCB1BR1

UCB1STAT

UCB1RXBUF

UCB1TXBUF

UCB1I2COA

UCB1I2CSA

UCB1IE

OFFSET

00h

USCI synchronous control 1

USCI synchronous control 0

USCI synchronous bit rate 0

USCI synchronous bit rate 1

USCI synchronous status

01h

06h

07h

0Ah

0Ch

0Eh

10h

USCI synchronous receive buffer

USCI synchronous transmit buffer

USCI I2C own address

USCI I2C slave address

USCI interrupt enable

12h

1Ch

1Dh

1Eh

USCI interrupt flags

UCB1IFG

USCI interrupt vector word

UCB1IV

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Table 9-41. ADC12_A Registers (Base Address: 0700h)

REGISTER DESCRIPTION

REGISTER

OFFSET

ADC control 0

ADC12CTL0

00h

02h

04h

0Ah

0Ch

0Eh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

22h

24h

26h

28h

2Ah

2Ch

2Eh

30h

32h

34h

36h

38h

3Ah

3Ch

3Eh

ADC control 1

ADC12CTL1

ADC control 2

ADC12CTL2

ADC interrupt flag

ADC12IFG

ADC interrupt enable

ADC interrupt vector word

ADC memory control 0

ADC memory control 1

ADC memory control 2

ADC memory control 3

ADC memory control 4

ADC memory control 5

ADC memory control 6

ADC memory control 7

ADC memory control 8

ADC memory control 9

ADC memory control 10

ADC memory control 11

ADC memory control 12

ADC memory control 13

ADC memory control 14

ADC memory control 15

Conversion memory 0

Conversion memory 1

Conversion memory 2

Conversion memory 3

Conversion memory 4

Conversion memory 5

Conversion memory 6

Conversion memory 7

Conversion memory 8

Conversion memory 9

Conversion memory 10

Conversion memory 11

Conversion memory 12

Conversion memory 13

Conversion memory 14

Conversion memory 15

ADC12IE

ADC12IV

ADC12MCTL0

ADC12MCTL1

ADC12MCTL2

ADC12MCTL3

ADC12MCTL4

ADC12MCTL5

ADC12MCTL6

ADC12MCTL7

ADC12MCTL8

ADC12MCTL9

ADC12MCTL10

ADC12MCTL11

ADC12MCTL12

ADC12MCTL13

ADC12MCTL14

ADC12MCTL15

ADC12MEM0

ADC12MEM1

ADC12MEM2

ADC12MEM3

ADC12MEM4

ADC12MEM5

ADC12MEM6

ADC12MEM7

ADC12MEM8

ADC12MEM9

ADC12MEM10

ADC12MEM11

ADC12MEM12

ADC12MEM13

ADC12MEM14

ADC12MEM15

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Table 9-42. Comparator_B Registers (Base Address: 08C0h)

REGISTER DESCRIPTION

REGISTER

CBCTL0

CBCTL1

CBCTL2

CBCTL3

CBINT

OFFSET

00h

Comp_B control 0

Comp_B control 1

Comp_B control 2

Comp_B control 3

Comp_B interrupt

02h

04h

06h

0Ch

Comp_B interrupt vector word

CBIV

0Eh

Table 9-43. LDO and Port U Configuration Registers (Base Address: 0900h)

REGISTER DESCRIPTION

REGISTER

LDOKEYPID

PUCTL

OFFSET

00h

LDO key/ID

PU port control

LDO power control

04h

LDOPWRCTL

08h

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9.10 Input/Output Diagrams

9.10.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger

Figure 9-2 shows the port diagram. Table 9-44 summarizes the selection of the pin functions.

Pad Logic

P1REN.x

DV_SS

DV_CC

0

1

P1DIR.x

0

1

Direction

0: Input

1: Output

From module

P1OUT.x

0

1

From module

P1.0/TA0CLK/ACLK

P1.1/TA0.0

P1.2/TA0.1

P1.3/TA0.2

P1.4/TA0.3

P1DS.x

0: Low drive

1: High drive

P1SEL.x

P1IN.x

P1.5/TA0.4

P1.6/TA1CLK/CBOUT

P1.7/TA1.0

EN

D

To module

P1IRQ.x

P1IE.x

EN

Q

P1IFG.x

Set

P1SEL.x

P1IES.x

Interrupt

Edge

Select

Figure 9-2. Port P1 (P1.0 to P1.7) Diagram

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Table 9-44. Port P1 (P1.0 to P1.7) Pin Functions

CONTROL BITS OR SIGNALS

PIN NAME (P1.x)

x

FUNCTION

P1DIR.x

P1SEL.x

P1.0 (I/O)

TA0CLK

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

P1.0/TA0CLK/ACLK

P1.1/TA0.0

0

1

2

3

4

5

6

7

0

ACLK

1

P1.1 (I/O)

TA0.CCI0A

TA0.0

I: 0; O: 1

0

1

P1.2 (I/O)

TA0.CCI1A

TA0.1

I: 0; O: 1

P1.2/TA0.1

0

1

P1.3 (I/O)

TA0.CCI2A

TA0.2

I: 0; O: 1

P1.3/TA0.2

0

1

P1.4 (I/O)

TA0.CCI3A

TA0.3

I: 0; O: 1

P1.4/TA0.3

0

1

P1.5 (I/O)

TA0.CCI4A

TA0.4

I: 0; O: 1

P1.5/TA0.4

0

1

P1.6 (I/O)

TA1CLK

I: 0; O: 1

P1.6/TA1CLK/CBOUT

P1.7/TA1.0

0

CBOUT comparator B

P1.7 (I/O)

TA1.CCI0A

TA1.0

1

I: 0; O: 1

0

1

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9.10.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger

Figure 9-3 shows the port diagram. Table 9-45 summarizes the selection of the pin functions.

Pad Logic

P2REN.x

DV_SS

DV_CC

0

1

P2DIR.x

0

1

Direction

0: Input

1: Output

From module

P2OUT.x

0

1

From module

P2.0/TA1.1

P2.1/TA1.2

P2.2/TA2CLK/SMCLK

P2.3/TA2.0

P2.4/TA2.1

P2DS.x

0: Low drive

1: High drive

P2SEL.x

P2IN.x

P2.5/TA2.2

P2.6/RTCCLK/DMAE0

P2.7/UB0STE/UCA0CLK

EN

D

To module

P2IE.x

EN

Q

P2IFG.x

Set

P2SEL.x

P2IES.x

Interrupt

Edge

Select

Figure 9-3. Port P2 (P2.0 to P2.7) Diagram

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Table 9-45. Port P2 (P2.0 to P2.7) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P2.x)

x

FUNCTION

P2DIR.x

P2SEL.x

P2.0 (I/O)

TA1.CCI1A

TA1.1

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

P2.0/TA1.1

0

1

2

3

4

5

0

1

P2.1 (I/O)

TA1.CCI2A

TA1.2

I: 0; O: 1

P2.1/TA1.2

0

1

P2.2 (I/O)

TA2CLK

I: 0; O: 1

P2.2/TA2CLK/SMCLK

P2.3/TA2.0

0

SMCLK

1

P2.3 (I/O)

TA2.CCI0A

TA2.0

I: 0; O: 1

0

1

P2.4 (I/O)

TA2.CCI1A

TA2.1

I: 0; O: 1

P2.4/TA2.1

0

1

P2.5 (I/O)

TA2.CCI2A

TA2.2

I: 0; O: 1

P2.5/TA2.2

0

1

P2.6 (I/O)

DMAE0

I: 0; O: 1

P2.6/RTCCLK/DMAE0

6

7

0

RTCCLK

P2.7 (I/O)

UCB0STE/UCA0CLK^{(2) (3)}

1

I: 0; O: 1

X

P2.7/UCB0STE/UCA0CLK

(1) X = Don't care

(2) The pin direction is controlled by the USCI module.

(3) UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI B0 is forced to

3-wire SPI mode if 4-wire SPI mode is selected.

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9.10.3 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger

Figure 9-4 shows the port diagram. Table 9-46 summarizes the selection of the pin functions.

Pad Logic

P3REN.x

DV_SS

DV_CC

0

1

P3DIR.x

0

1

Direction

0: Input

1: Output

From module

P3OUT.x

0

1

From module

P3.0/UCB0SIMO/UCB0SDA

P3.1/UCB0SOMI/UCB0SCL

P3.2/UCB0CLK/UCA0STE

P3.3/UCA0TXD/UCA0SIMO

P3.4/UCA0RXD/UCA0SOMI

P3.5/TB0.5

P3DS.x

0: Low drive

1: High drive

P3SEL.x

P3IN.x

P3.6/TB0.6

P3.7/TB0OUTH/SVMOUT

EN

D

To module

Figure 9-4. Port P3 (P3.0 to P3.7) Diagram

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Table 9-46. Port P3 (P3.0 to P3.7) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P3.x)

x

FUNCTION

P3DIR.x

P3SEL.x

P3.0 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

P3.0/UCB0SIMO/UCB0SDA

P3.1/UCB0SOMI/UCB0SCL

P3.2/UCB0CLK/UCA0STE

P3.3/UCA0TXD/UCA0SIMO

P3.4/UCA0RXD/UCA0SOMI

0

1

2

3

4

UCB0SIMO/UCB0SDA^{(2) (3)}

X

P3.1 (I/O)

I: 0; O: 1

UCB0SOMI/UCB0SCL^{(2) (3)}

P3.2 (I/O)

X

I: 0; O: 1

UCB0CLK/UCA0STE^{(2) (4)}

X

P3.3 (I/O)

I: 0; O: 1

UCA0TXD/UCA0SIMO⁽²⁾

P3.4 (I/O)

X

I: 0; O: 1

UCA0RXD/UCA0SOMI⁽²⁾

X

P3.5 (I/O)

I: 0; O: 1

P3.5/TB0.5⁽⁵⁾

P3.6/TB0.6⁽⁵⁾

5

6

7

TB0.CCI5A

0

TB0.5

1

P3.6 (I/O)

I: 0; O: 1

TB0.CCI6A

0

TB0.6

1

P3.7 (I/O)

I: 0; O: 1

P3.7/TB0OUTH/SVMOUT⁽⁵⁾

(1) X = Don't care

TB0OUTH

0

1

SVMOUT

(2) The pin direction is controlled by the USCI module.

(3) If the I²C functionality is selected, the output drives only the logical 0 to V_SSlevel.

(4) UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI A0 is forced to

3-wire SPI mode if 4-wire SPI mode is selected.

(5) F5329, F5327, F5325 devices only.

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9.10.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger

Figure 9-5 shows the port diagram. Table 9-47 summarizes the selection of the pin functions.

Pad Logic

P4REN.x

DV_SS

DV_CC

0

1

P4DIR.x

0

1

Direction

0: Input

1: Output

from Port Mapping Control

P4OUT.x

0

1

from Port Mapping Control

P4.0/P4MAP0

P4.1/P4MAP1

P4.2/P4MAP2

P4.3/P4MAP3

P4.4/P4MAP4

P4.5/P4MAP5

P4.6/P4MAP6

P4.7/P4MAP7

P4DS.x

0: Low drive

1: High drive

P4SEL.x

P4IN.x

EN

D

to Port Mapping Control

Figure 9-5. Port P4 (P4.0 to P4.7) Diagram

Table 9-47. Port P4 (P4.0 to P4.7) Pin Functions

CONTROL BITS OR SIGNALS

PIN NAME (P4.x)

P4.0/P4MAP0

P4.1/P4MAP1

P4.2/P4MAP2

P4.3/P4MAP3

P4.4/P4MAP4

P4.5/P4MAP5

P4.6/P4MAP6

P4.7/P4MAP7

x

0

1

2

3

4

5

6

7

FUNCTION

P4DIR.x⁽¹⁾

P4SEL.x

P4MAPx

P4.0 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

≤ 30

X

Mapped secondary digital function

P4.1 (I/O)

X

I: 0; O: 1

Mapped secondary digital function

P4.2 (I/O)

X

≤ 30

X

I: 0; O: 1

Mapped secondary digital function

P4.3 (I/O)

X

≤ 30

X

I: 0; O: 1

Mapped secondary digital function

P4.4 (I/O)

X

≤ 30

X

I: 0; O: 1

Mapped secondary digital function

P4.5 (I/O)

X

≤ 30

X

I: 0; O: 1

Mapped secondary digital function

P4.6 (I/O)

X

I: 0; O: 1

X

≤ 30

X

Mapped secondary digital function

P4.7 (I/O)

≤ 30

X

I: 0; O: 1

X

Mapped secondary digital function

≤ 30

(1) The direction of some mapped secondary functions are controlled directly by the module. See Table 9-6 for specific direction control

information of mapped secondary functions.

84

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SLAS678G – AUGUST 2010 – REVISED SEPTEMBER 2020

9.10.5 Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger

Figure 9-6 shows the port diagram. Table 9-48 summarizes the selection of the pin functions.

Pad Logic

to/from Reference

to ADC12

INCHx = x

P5REN.x

DV_SS

DV_CC

0

1

P5DIR.x

0

1

P5OUT.x

0

1

From module

P5.0/A8/VREF+/VeREF+

P5.1/A9/VREF–/VeREF–

P5DS.x

0: Low drive

1: High drive

P5SEL.x

P5IN.x

Bus

Keeper

EN

D

To module

Figure 9-6. Port P5 (P5.0 and P5.1) Diagram

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Table 9-48. Port P5 (P5.0 and P5.1) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P5.x)

x

FUNCTION

P5DIR.x

P5SEL.x

REFOUT

P5.0 (I/O)⁽²⁾

A8/VeREF+⁽³⁾

A8/VREF+⁽⁴⁾

P5.1 (I/O)⁽²⁾

A9/VeREF–⁽⁵⁾

A9/VREF-⁽⁶⁾

I: 0; O: 1

0

1

0

1

X

0

1

X

0

1

P5.0/A8/VREF+/VeREF+

0

X

I: 0; O: 1

P5.1/A9/VREF-/VeREF–

1

X

(1) X = Don't care

(2) Default condition

(3) Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A. Channel A8, when

selected with the INCHx bits, is connected to the VREF+/VeREF+ pin.

(4) Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. The VREF+ reference is available at the pin. Channel A8, when selected with the INCHx bits, is connected to the

VREF+/VeREF+ pin.

(5) Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A. Channel A9, when selected

with the INCHx bits, is connected to the VREF-/VeREF- pin.

(6) Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. The VREF- reference is available at the pin. Channel A9, when selected with the INCHx bits, is connected to the

VREF-/VeREF- pin.

86

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SLAS678G – AUGUST 2010 – REVISED SEPTEMBER 2020

9.10.6 Port P5 (P5.2) Input/Output With Schmitt Trigger

Figure 9-7 shows the port diagram. Table 9-49 summarizes the selection of the pin functions.

Pad Logic

To XT2

P5REN.2

DV_SS

DV_CC

0

1

P5DIR.2

0

1

P5OUT.2

0

1

Module X OUT

P5.2/XT2IN

P5DS.2

0: Low drive

1: High drive

P5SEL.2

P5IN.2

Bus

Keeper

EN

D

Module X IN

Figure 9-7. Port P5 (P5.2) Diagram

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9.10.7 Port P5 (P5.3) Input/Output With Schmitt Trigger

Figure 9-8 shows the port diagram. Table 9-49 summarizes the selection of the pin functions.

Pad Logic

To XT2

P5REN.3

DV_SS

DV_CC

0

1

P5DIR.3

0

1

P5OUT.3

0

1

Module X OUT

P5.3/XT2OUT

P5SEL.2

P5DS.3

0: Low drive

1: High drive

XT2BYPASS

P5SEL.3

P5IN.3

EN

D

Bus

Keeper

Module X IN

Figure 9-8. Port P5 (P5.3) Diagram

Table 9-49. Port P5 (P5.2 and P5.3) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P5.x)

x

FUNCTION

P5DIR.x

P5SEL.2

P5SEL.3

XT2BYPASS

P5.2 (I/O)

I: 0; O: 1

0

1

0

1

X

0

1

X

0

1

P5.2/XT2IN

2

XT2IN crystal mode⁽²⁾

XT2IN bypass mode⁽²⁾

P5.3 (I/O)

X

I: 0; O: 1

P5.3/XT2OUT

3

XT2OUT crystal mode⁽³⁾

P5.3 (I/O)⁽³⁾

X

(1) X = Don't care

(2) Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal

mode or bypass mode.

(3) Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as

general-purpose I/O.

88

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SLAS678G – AUGUST 2010 – REVISED SEPTEMBER 2020

9.10.8 Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger

Figure 9-9 and Figure 9-10 show the port schematics. Table 9-50 summarizes the selection of the pin functions.

Pad Logic

to XT1

P5REN.4

DV_SS

DV_CC

0

1

P5DIR.4

0

1

P5OUT.4

0

1

Module X OUT

P5.4/XIN

P5DS.4

0: Low drive

1: High drive

P5SEL.4

P5IN.4

Bus

Keeper

EN

D

Module X IN

Figure 9-9. Port P5 (P5.4) Diagram

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Pad Logic

to XT1

P5REN.5

DV_SS

DV_CC

0

1

P5DIR.5

0

1

P5OUT.5

0

1

Module X OUT

P5.5/XOUT

P5SEL.4

P5DS.5

0: Low drive

1: High drive

XT1BYPASS

P5SEL.5

P5IN.5

Bus

Keeper

EN

D

Module X IN

Figure 9-10. Port P5 (P5.5) Diagram

Table 9-50. Port P5 (P5.4 and P5.5) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P5.x)

x

FUNCTION

P5DIR.x

P5SEL.4

P5SEL.5

XT1BYPASS

P5.4 (I/O)

I: 0; O: 1

0

1

0

1

X

0

1

X

0

1

P5.4/XIN

4

XIN crystal mode⁽²⁾

XIN bypass mode⁽²⁾

P5.5 (I/O)

X

I: 0; O: 1

P5.5/XOUT

5

XOUT crystal mode⁽³⁾

P5.5 (I/O)⁽³⁾

X

(1) X = Don't care

(2) Setting P5SEL.4 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P5.4 is configured for crystal

mode or bypass mode.

(3) Setting P5SEL.4 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.5 can be used as

general-purpose I/O.

90

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SLAS678G – AUGUST 2010 – REVISED SEPTEMBER 2020

9.10.9 Port P5 (P5.6 to P5.7), Input/Output With Schmitt Trigger

Figure 9-11 shows the port diagram. Table 9-51 summarizes the selection of the pin functions.

Pad Logic

P5REN.x

DV_SS

DV_CC

0

1

P5DIR.x

0

1

Direction

0: Input

1: Output

From Module

P5OUT.x

0

1

P5DS.x

0: Low drive

1: High drive

P5.6/TB0.0

P5.7/TB0.1

P5SEL.x

P5IN.x

EN

D

To module

Figure 9-11. Port P5 (P5.6 to P5.7) Diagram

Table 9-51. Port P5 (P5.6 to P5.7) Pin Functions

CONTROL BITS OR SIGNALS

PIN NAME (P5.x)

x

FUNCTION

P5DIR.x

P5SEL.x

P5.6 (I/O)

I: 0; O: 1

0

1

P5.6/TB0.0⁽¹⁾

P5.7/TB0.1⁽¹⁾

6

7

TB0.CCI0A

TB0.0

0

1

0

1

TB0.CCI1A

TB0.1

(1) F5329, F5327, F5325 devices only.

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9.10.10 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger

Figure 9-12 shows the port diagram. Table 9-52 summarizes the selection of the pin functions.

Pad Logic

to ADC12

INCHx = x

to Comparator_B

from Comparator_B

CBPD.x

P6REN.x

P6DIR.x

DVSS

DVCC

0

1

0

1

Direction

0: Input

1: Output

P6OUT.x

0

1

From module

P6.0/CB0/A0

P6.1/CB1/A1

P6.2/CB2/A2

P6.3/CB3/A3

P6.4/CB4/A4

P6.5/CB5/A5

P6.6/CB6/A6

P6.7/CB7/A7

P6DS.x

0: Low drive

1: High drive

P6SEL.x

P6IN.x

Bus

Keeper

EN

D

To module

Figure 9-12. Port P6 (P6.0 to P6.7) Diagram

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SLAS678G – AUGUST 2010 – REVISED SEPTEMBER 2020

Table 9-52. Port P6 (P6.0 to P6.7) Pin Functions

CONTROL BITS OR SIGNALS

FUNCTION

PIN NAME (P6.x)

x

P6DIR.x

P6SEL.x

CBPD

P6.0 (I/O)

A0

I: 0; O: 1

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

P6.0/CB0/(A0)

P6.1/CB1/(A1)

P6.2/CB2/(A2)

P6.3/CB3/(A3)

P6.4/CB4/(A4)

P6.5/CB5/(A5)

P6.6/CB6/(A6)

P6.7/CB7/(A7)

0

X

1

CB0⁽¹⁾

P6.1 (I/O)

A1

X

I: 0; O: 1

0

1

2

3

4

5

6

7

X

1

CB1⁽¹⁾

P6.2 (I/O)

A2

X

I: 0; O: 1

0

X

1

CB2⁽¹⁾

P6.3 (I/O)

A3

X

I: 0; O: 1

0

X

1

CB3⁽¹⁾

P6.4 (I/O)

A4

X

I: 0; O: 1

0

X

1

CB4⁽¹⁾

P6.5 (I/O)

A5

X

I: 0; O: 1

0

X

1

CB5⁽¹⁾

P6.6 (I/O)

A6

X

I: 0; O: 1

0

X

1

CB6⁽¹⁾

P6.7 (I/O)

A7

X

I: 0; O: 1

0

X

1

CB7⁽¹⁾

(1) Setting the CBPD.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog

signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input

buffer for that pin, regardless of the state of the associated CBPD.x bit.

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9.10.11 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger

Figure 9-13 shows the port diagram. Table 9-53 summarizes the selection of the pin functions.

Pad Logic

to ADC12

INCHx = x

to Comparator_B

from Comparator_B

CBPD.x

P7REN.x

P7DIR.x

DVSS

DVCC

0

1

0

1

Direction

0: Input

1: Output

P7OUT.x

0

1

From module

P7.0/CB8/A12

P7.1/CB9/A13

P7.2/CB10/A14

P7.3/CB11/A15

P7DS.x

0: Low drive

1: High drive

P7SEL.x

P7IN.x

Bus

Keeper

EN

D

To module

Figure 9-13. Port P7 (P7.0 to P7.3) Diagram

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SLAS678G – AUGUST 2010 – REVISED SEPTEMBER 2020

Table 9-53. Port P7 (P7.0 to P7.3) Pin Functions

CONTROL BITS OR SIGNALS

FUNCTION

PIN NAME (P7.x)

x

P7DIR.x

P7SEL.x

CBPD

P7.0 (I/O) ⁽²⁾

A12 ⁽³⁾

I: 0; O: 1

0

1

X

0

1

X

0

1

X

0

1

X

0

X

1

0

X

1

0

X

1

0

X

1

P7.0/CB8/(A12)

P7.1/CB9/(A13)

P7.2/CB10/(A14)

P7.3/CB11/(A15)

0

X

CB8^{(1) (2)}

P7.1 (I/O)⁽²⁾

A13 ⁽³⁾

X

I: 0; O: 1

1

2

3

X

CB9^{(1) (2)}

P7.2 (I/O)⁽²⁾

A14⁽³⁾

X

I: 0; O: 1

X

CB10^{(1) (2)}

P7.3 (I/O)⁽²⁾

A15⁽³⁾

X

I: 0; O: 1

X

CB11^{(1) (2)}

(1) Setting the CBPD.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog

signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input

buffer for that pin, regardless of the state of the associated CBPD.x bit.

(2) F5329, F5327, F5325 devices only.

(3) F5329, F5327, F5325 devices only.

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9.10.12 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger

Figure 9-14 shows the port diagram. Table 9-54 summarizes the selection of the pin functions.

Pad Logic

P7REN.x

DV_SS

DV_CC

0

1

P7DIR.x

0

1

Direction

0: Input

1: Output

From module

P7OUT.x

0

1

P7DS.x

0: Low drive

1: High drive

P7.4/TB0.2

P7.5/TB0.3

P7.6/TB0.4

P7.7/TB0CLK/MCLK

P7SEL.x

P7IN.x

EN

D

To module

Figure 9-14. Port P7 (P7.4 to P7.7) Diagram

Table 9-54. Port P7 (P7.4 to P7.7) Pin Functions

CONTROL BITS OR SIGNALS

PIN NAME (P7.x)

x

FUNCTION

P7DIR.x

P7SEL.x

P7.4 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

P7.4/TB0.2⁽¹⁾

4

TB0.CCI2A

TB0.2

0

1

P7.5 (I/O)

TB0.CCI3A

TB0.3

I: 0; O: 1

P7.5/TB0.3⁽¹⁾

5

6

7

0

1

P7.6 (I/O)

TB0.CCI4A

TB0.4

I: 0; O: 1

P7.6/TB0.4⁽¹⁾

0

1

P7.7 (I/O)

TB0CLK

MCLK

I: 0; O: 1

P7.7/TB0CLK/MCLK⁽¹⁾

0

1

(1) F5329, F5327, F5325 devices only.

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9.10.13 Port P8 (P8.0 to P8.2) Input/Output With Schmitt Trigger

Figure 9-15 shows the port diagram. Table 9-55 summarizes the selection of the pin functions.

Pad Logic

P8REN.x

DV_SS

DV_CC

0

1

P8DIR.x

0

1

Direction

0: Input

1: Output

from Port Mapping Control

P8OUT.x

0

1

from Port Mapping Control

P8.0

P8.1

P8.2

P8DS.x

0: Low drive

1: High drive

P8SEL.x

P8IN.x

EN

D

to Port Mapping Control

Figure 9-15. Port P8 (P8.0 to P8.2) Diagram

Table 9-55. Port P8 (P8.0 to P8.2) Pin Functions

CONTROL BITS OR SIGNALS

PIN NAME (P8.x)

x

FUNCTION

P8DIR.x

I: 0; O: 1

P8SEL.x

P8.0⁽¹⁾

P8.1⁽¹⁾

P8.2⁽¹⁾

0

1

2

P8.0(I/O)

0

P8.1(I/O)

P8.2(I/O)

(1) F5329, F5327, F5325 devices only.

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9.10.14 Port U (PU.0 and PU.1)

Figure 9-16 shows the port diagram. Table 9-56 summarizes the selection of the pin functions.

LDOO

VSSU

Pad Logic

PUOPE

PU.0

PUOUT0

PUIN0

PUIPE

PUIN1

PUOUT1

PU.1

Figure 9-16. Port U (PU.0 and PU.1) Diagram

Table 9-56. Port U (PU.0 and PU.1) Functions

PUIPE⁽¹⁾

PUOPE

PUOUT1

PUOUT0

PU.1

PU.0

PORT U FUNCTION

0

1

0

1

0

1

X

0

1

0

1

X

Output low

Output high

Input enabled

Hi-Z

Output low

Output high

Output low

Output high

Input enabled

Hi-Z

Outputs enabled

Inputs enabled

Outputs and inputs disabled

(1) PU.1 and PU.0 inputs and outputs are supplied from LDOO. LDOO can be generated by the device using the integrated 3.3-V LDO

when enabled. LDOO can also be supplied externally when the 3.3-V LDO is not being used and is disabled.

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9.10.15 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output

Figure 9-17 shows the port diagram. Table 9-57 summarizes the selection of the pin functions.

Pad Logic

PJREN.0

0

1

DV_SS

DV_CC

1

PJDIR.0

DVCC

0

1

PJOUT.0

0

1

From JTAG

PJ.0/TDO

PJDS.0

0: Low drive

1: High drive

From JTAG

PJIN.0

EN

D

Figure 9-17. Port PJ (PJ.0) Diagram

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9.10.16 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output

Figure 9-18 shows the port diagram. Table 9-57 summarizes the selection of the pin functions.

Pad Logic

PJREN.x

0

1

DV_SS

DV_CC

1

PJDIR.x

DVSS

0

1

PJOUT.x

0

1

From JTAG

PJ.1/TDI/TCLK

PJ.2/TMS

PJ.3/TCK

PJDS.x

0: Low drive

1: High drive

From JTAG

PJIN.x

EN

D

To JTAG

Figure 9-18. Port PJ (PJ.1 to PJ.3) Diagram

Table 9-57. Port PJ (PJ.0 to PJ.3) Pin Functions

CONTROL BITS

OR SIGNALS⁽¹⁾

PIN NAME (PJ.x)

x

FUNCTION

PJDIR.x

I: 0; O: 1

X

PJ.0 (I/O)⁽²⁾

PJ.0/TDO

0

1

2

3

TDO⁽³⁾

PJ.1 (I/O)⁽²⁾

TDI/TCLK^{(3) (4)}

PJ.2 (I/O)⁽²⁾

TMS^{(3) (4)}

I: 0; O: 1

X

PJ.1/TDI/TCLK

PJ.2/TMS

I: 0; O: 1

X

PJ.3 (I/O)⁽²⁾

TCK^{(3) (4)}

I: 0; O: 1

X

PJ.3/TCK

(1) X = Don't care

(2) Default condition

(3) The pin direction is controlled by the JTAG module.

(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.

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9.11 Device Descriptors

Table 9-58 lists the complete contents of the device descriptor tag-length-value (TLV) structure for each device

type.

Table 9-58. Device Descriptor Table

VALUE

SIZE

(bytes)

DESCRIPTION⁽¹⁾

Info length

ADDRESS

F5329

06h

F5328

06h

F5327

06h

F5326

06h

F5325

06h

F5324

06h

01A00h

01A01h

01A02h

01A04h

01A05h

01A06h

01A07h

01A08h

01A09h

01A0Ah

01A0Eh

01A10h

01A12h

01A14h

01A15h

01A16h

01A18h

1

2

1

4

2

1

2

CRC length

CRC value

06h

Per unit

1Bh

Per unit

1Ah

Per unit

19h

Per unit

18h

Per unit

17h

Per unit

16h

Info Block

Device ID

81h

Hardware revision

Firmware revision

Die record tag

Die record length

Lot/Wafer ID

Per unit

08h

Per unit

08h

Per unit

08h

Per unit

08h

Per unit

08h

Per unit

08h

0Ah

Per unit

11h

Per unit

11h

Per unit

11h

Per unit

11h

Per unit

11h

Per unit

11h

Die Record

Die X position

Die Y position

Test results

ADC12 calibration tag

ADC12 calibration length

ADC gain factor

ADC offset

10h

Per unit

ADC 1.5-V reference

Temperature sensor 30°C

01A1Ah

01A1Ch

01A1Eh

01A20h

01A22h

01A24h

2

Per unit

ADC 1.5-V reference

Temperature sensor 85°C

ADC12 Calibration

ADC 2.0-V reference

Temperature sensor 30°C

ADC 2.0-V reference

Temperature sensor 85°C

ADC 2.5-V reference

Temperature sensor 30°C

ADC 2.5-V reference

Temperature sensor 85°C

REF calibration tag

REF calibration length

01A26h

01A27h

01A28h

01A2Ah

01A2Ch

01A2Eh

01A2Fh

1

2

1

12h

06h

12h

06h

12h

06h

12h

06h

12h

06h

12h

06h

REF Calibration

REF 1.5-V reference factor

REF 2.0-V reference factor

REF 2.5-V reference factor

Peripheral descriptor tag

Peripheral descriptor length

Per unit

02h

Per unit

02h

Per unit

02h

Per unit

02h

Per unit

02h

Per unit

02h

62h

60h

62h

60h

62h

60h

08h

8Ah

08h

8Ah

08h

8Ah

08h

8Ah

08h

8Ah

08h

8Ah

Memory 1

Memory 2

Memory 3

Memory 4

2

0Ch

86h

0Ch

86h

0Ch

86h

0Ch

86h

0Ch

86h

0Ch

86h

Peripheral

Descriptor

0Eh

2Fh

0Eh

2Fh

0Eh

2Eh

0Eh

2Eh

0Eh

2Dh

0Eh

2Dh

2Ah

22h

2Ah

22h

95h

22h

95h

2Ah

22h

2Ah

22h

Memory 5

Delimiter

1

96h

00h

21h

96h

00h

20h

92h

00h

21h

92h

00h

20h

94h

00h

21h

94h

00h

20h

Peripheral count

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Table 9-58. Device Descriptor Table (continued)

VALUE

SIZE

(bytes)

DESCRIPTION⁽¹⁾

ADDRESS

F5329

F5328

F5327

F5326

F5325

00h

23h

00h

23h

00h

23h

00h

23h

00h

23h

00h

23h

MSP430CPUXV2

2

00h

09h

00h

09h

00h

09h

00h

09h

00h

09h

00h

09h

JTAG

SBW

00h

0Fh

00h

0Fh

00h

0Fh

00h

0Fh

00h

0Fh

00h

0Fh

00h

05h

00h

05h

00h

05h

00h

05h

00h

05h

00h

05h

EEM-L

TI BSL

SFR

00h

FCh

00h

FCh

00h

FCh

00h

FCh

00h

FCh

00h

FCh

10h

41h

10h

41h

10h

41h

10h

41h

10h

41h

10h

41h

02h

30h

02h

30h

02h

30h

02h

30h

02h

30h

02h

30h

PMM

02h

38h

02h

38h

02h

38h

02h

38h

02h

38h

02h

38h

FCTL

01h

3Ch

01h

3Ch

01h

3Ch

01h

3Ch

01h

3Ch

01h

3Ch

CRC16

CRC16_RB

RAMCTL

WDT_A

UCS

00h

3Dh

00h

3Dh

00h

3Dh

00h

3Dh

00h

3Dh

00h

3Dh

00h

44h

00h

44h

00h

44h

00h

44h

00h

44h

00h

44h

00h

40h

00h

40h

00h

40h

00h

40h

00h

40h

00h

40h

01h

48h

01h

48h

01h

48h

01h

48h

01h

48h

01h

48h

02h

42h

02h

42h

02h

42h

02h

42h

02h

42h

02h

42h

SYS

03h

A0h

03h

A0h

03h

A0h

03h

A0h

03h

A0h

03h

A0h

REF

01h

10h

01h

10h

01h

10h

01h

10h

01h

10h

01h

10h

Port Mapping

Port 1 and 2

Port 3 and 4

Port 5 and 6

Port 7 and 8

JTAG

04h

51h

04h

51h

04h

51h

04h

51h

04h

51h

04h

51h

02h

52h

02h

52h

02h

52h

02h

52h

02h

52h

02h

52h

02h

53h

02h

53h

02h

53h

02h

53h

02h

53h

02h

53h

02h

54h

02h

54h

02h

54h

N/A

0Ch

5Fh

0Eh

5Fh

0Ch

5Fh

0Eh

5Fh

0Ch

5Fh

0Eh

5Fh

02h

62h

02h

62h

02h

62h

02h

62h

02h

62h

02h

62h

TA0

04h

61h

04h

61h

04h

61h

04h

61h

04h

61h

04h

61h

TA1

04h

67h

04h

67h

04h

67h

04h

67h

04h

67h

04h

67h

TB0

Peripheral

Descriptor

(continued)

04h

61h

04h

61h

04h

61h

04h

61h

04h

61h

04h

61h

TA2

0Ah

68h

0Ah

68h

0Ah

68h

0Ah

68h

0Ah

68h

0Ah

68h

RTC

02h

85h

02h

85h

02h

85h

02h

85h

02h

85h

02h

85h

MPY32

DMA-3

USCI_A/B

04h

47h

04h

47h

04h

47h

04h

47h

04h

47h

04h

47h

0Ch

90h

0Ch

90h

0Ch

90h

0Ch

90h

0Ch

90h

0Ch

90h

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Table 9-58. Device Descriptor Table (continued)

VALUE

SIZE

DESCRIPTION⁽¹⁾

ADDRESS

(bytes)

F5329

F5328

F5327

F5326

F5325

F5324

04h

90h

04h

90h

04h

90h

04h

90h

04h

90h

04h

90h

USCI_A/B

2

10h

D1h

10h

D1h

10h

D1h

10h

D1h

10h

D1h

10h

D1h

ADC12_A

COMP_B

LDO

1Ch

A8h

1Ch

A8h

1Ch

A8h

1Ch

A8h

1Ch

A8h

1Ch

A8h

04h

5Ch

04h

5Ch

04h

5Ch

04h

5Ch

04h

5Ch

04h

5Ch

COMP_B

TB0.CCIFG0

TB0.CCIFG1..6

WDTIFG

1

A8h

64h

65h

40h

90h

91h

D0h

60h

61h

5Ch

46h

62h

63h

50h

92h

93h

66h

67h

51h

68h

00h

A8h

64h

65h

40h

90h

91h

D0h

60h

61h

5Ch

46h

62h

63h

50h

92h

93h

66h

67h

51h

68h

00h

A8h

64h

65h

40h

90h

91h

D0h

60h

61h

5Ch

46h

62h

63h

50h

92h

93h

66h

67h

51h

68h

00h

A8h

64h

65h

40h

90h

91h

D0h

60h

61h

5Ch

46h

62h

63h

50h

92h

93h

66h

67h

51h

68h

00h

A8h

64h

65h

40h

90h

91h

D0h

60h

61h

5Ch

46h

62h

63h

50h

92h

93h

66h

67h

51h

68h

00h

A8h

64h

65h

40h

90h

91h

D0h

60h

61h

5Ch

46h

62h

63h

50h

92h

93h

66h

67h

51h

68h

00h

USCI_A0

USCI_B0

ADC12_A

TA0.CCIFG0

TA0.CCIFG1..4

LDO-PWR

DMA

Interrupts

TA1.CCIFG0

TA1.CCIFG1..2

P1

USCI_A1

USCI_B1

TA1.CCIFG0

TA1.CCIFG1..2

P2

RTC_A

Delimiter

(1) NA = Not applicable, blank = unused and reads FFh.

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10 Device and Documentation Support

10.1 Getting Started and Next Steps

For an introduction to the MSP430^™family of devices and the tools and libraries that are available to help with

your development, visit the MSP430 ultra-low-power sensing & measurement MCUs overview.

10.2 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP

MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These

prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully

qualified production devices (MSP).

XMS – Experimental device that is not necessarily representative of the final device's electrical specifications

MSP – Fully qualified production device

XMS devices are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated

fully. TI's standard warranty applies.

Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.

TI recommends that these devices not be used in any production system because their expected end-use failure

rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature

range, package type, and distribution format. Figure 10-1 provides a legend for reading the complete device

name.

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MSP 430 F 5 438 A I PM T -EP

Processor Family

MCU Platform

Device Type

Series

Feature Set

Optional: Additional Features

Optional: Tape and Reel

Packaging

Optional: Temperature Range

Optional: Revision

Processor Family

CC = Embedded RF Radio

MSP = Mixed-Signal Processor

XMS = Experimental Silicon

PMS = Prototype Device

MCU Platform

Device Type

430 = MSP430 low-power microcontroller platform

Memory Type

C = ROM

F = Flash

FR = FRAM

G = Flash

L = No nonvolatile memory

Specialized Application

AFE = Analog front end

BQ = Contactless power

CG = ROM medical

FE = Flash energy meter

FG = Flash medical

FW = Flash electronic flow meter

Series

1 = Up to 8 MHz

2 = Up to 16 MHz

3 = Legacy

4 = Up to 16 MHz with LCD driver

5 = Up to 25 MHz

6 = Up to 25 MHz with LCD driver

0 = Low-voltage series

Feature Set

Various levels of integration within a series

Updated version of the base part number

Optional: Revision

Optional: Temperature Range S = 0°C to 50°C

C = 0°C to 70°C

I = –40°C to 85°C

T = –40°C to 105°C

Packaging

http://www.ti.com/packaging

Optional: Tape and Reel

T = Small reel

R = Large reel

No markings = Tube or tray

Optional: Additional Features -EP = Enhanced product (–40°C to 105°C)

-HT = Extreme temperature parts (–55°C to 150°C)

-Q1 = Automotive Q100 qualified

Figure 10-1. Device Nomenclature

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10.3 Tools and Software

All MSP microcontrollers are supported by a wide variety of software and hardware development tools. Tools are

available from TI and various third parties. See them all at MSP430 ultra-low-power MCUs – Design &

development.

Table 10-1 lists the debug features of the MSP430F532x MCUs. See the Code Composer Studio™ IDE for

MSP430™ MCUs User's Guide for details on the available features.

Table 10-1. Hardware Debug Features

BREAK-

POINTS

(N)

RANGE

BREAK-

POINTS

LPMX.5

DEBUGGING

SUPPORT

MSP430

ARCHITECTURE

4-WIRE

JTAG

2-WIRE

JTAG

CLOCK

CONTROL SEQUENCER

STATE

TRACE

BUFFER

MSP430Xv2

Yes

8

Yes

No

Design Kits and Evaluation Modules

80-pin Target Development Board for MSP430F5x MCUs

The MSP-TS430PN80A is a standalone 80-pin ZIF socket target board used to program and debug the MSP430

MCU in-system through the JTAG interface or the Spy Bi-Wire (2-wire JTAG) protocol.

80-pin Target Development Board and MSP-FET Programmer Bundle for MSP430F5x MCUs

The MSP-FET is a powerful flash emulation tool to quickly begin application development on the MSP430 MCU.

It includes USB debugging interface used to program and debug the MSP430 in-system through the JTAG

interface or the pin saving Spy-Bi-Wire (2-wire JTAG) protocol. The flash memory can be erased and

programmed in seconds with only a few keystrokes, and since the MSP430 flash is ultra-low power, no external

power supply is required.

Software

MSP430Ware^™Software

MSP430Ware software is a collection of code examples, data sheets, and other design resources for all

MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing

MSP430 design resources, MSP430Ware software also includes a high-level API called MSP Driver Library. This

library makes it easy to program MSP430 hardware. MSP430Ware software is available as a component of

Code Composer Studio^™IDE or as a stand-alone package.

MSP430F532x Code Examples

C Code examples are available for every MSP device that configures each of the integrated peripherals for

various application needs.

MSP Driver Library

Driver Library's abstracted API keeps you above the bits and bytes of the MSP430 hardware by providing easy-

to-use function calls. Thorough documentation is delivered through a helpful API Guide, which includes details

on each function call and the recognized parameters. Developers can use Driver Library functions to write

complete projects with minimal overhead.

MSP EnergyTrace^™Technology

EnergyTrace technology for MSP430 microcontrollers is an energy-based code analysis tool that measures and

displays the application's energy profile and helps to optimize it for ultra-low-power consumption.

ULP (Ultra-Low Power) Advisor

ULP Advisor^™software is a tool for guiding developers to write more efficient code to fully utilize the unique

ultra-low power features of MSP and MSP432 microcontrollers. Aimed at both experienced and new

microcontroller developers, ULP Advisor checks your code against a thorough ULP checklist to squeeze every

last nano amp out of your application. At build time, ULP Advisor will provide notifications and remarks to

highlight areas of your code that can be further optimized for lower power.

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IEC60730 Software Package

The IEC60730 MSP430 software package was developed to be useful in assisting customers in complying with

IEC 60730-1:2010 (Automatic Electrical Controls for Household and Similar Use – Part 1: General

Requirements) for up to Class B products, which includes home appliances, arc detectors, power converters,

power tools, e-bikes, and many others. The IEC60730 MSP430 software package can be embedded in customer

applications running on MSP430s to help simplify the customer’s certification efforts of functional safety-

compliant consumer devices to IEC 60730-1:2010 Class B.

Fixed Point Math Library for MSP

The MSP IQmath and Qmath Libraries are a collection of highly optimized and high-precision mathematical

functions for C programmers to seamlessly port a floating-point algorithm into fixed-point code on MSP430 and

MSP432 devices. These routines are typically used in computationally intensive real-time applications where

optimal execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and Qmath

libraries, it is possible to achieve execution speeds considerably faster and energy consumption considerably

lower than equivalent code written using floating-point math.

Floating Point Math Library for MSP430

Continuing to innovate in the low power and low cost microcontroller space, TI brings you MSPMATHLIB.

Leveraging the intelligent peripherals of our devices, this floating point math library of scalar functions brings you

up to 26x better performance. Mathlib is easy to integrate into your designs. This library is free and is integrated

in both Code Composer Studio and IAR IDEs. Read the user’s guide for an in depth look at the math library and

relevant benchmarks.

Development Tools

Code Composer Studio^™Integrated Development Environment for MSP Microcontrollers

Code Composer Studio is an integrated development environment (IDE) that supports all MSP microcontroller

devices. Code Composer Studio comprises a suite of embedded software utilities used to develop and debug

embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,

debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking you through

each step of the application development flow. Familiar utilities and interfaces allow users to get started faster

than ever before. Code Composer Studio combines the advantages of the Eclipse software framework with

advanced embedded debug capabilities from TI resulting in a compelling feature-rich development environment

for embedded developers. When using CCS with an MSP MCU, a unique and powerful set of plugins and

embedded software utilities are made available to fully leverage the MSP microcontroller.

Command-Line Programmer

MSP Flasher is an open-source shell-based interface for programming MSP microcontrollers through a FET

programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP Flasher can download binary

files (.txt or .hex) files directly to the MSP microcontroller without an IDE.

MSP MCU Programmer and Debugger

The MSP-FET is a powerful emulation development tool – often called a debug probe – which allows users to

quickly begin application development on MSP low-power microcontrollers (MCU). Creating MCU software

usually requires downloading the resulting binary program to the MSP device for validation and debugging. The

MSP-FET provides a debug communication pathway between a host computer and the target MSP.

Furthermore, the MSP-FET also provides a Backchannel UART connection between the computer's USB

interface and the MSP UART. This affords the MSP programmer a convenient method for communicating serially

between the MSP and a terminal running on the computer. It also supports loading programs (often called

firmware) to the MSP target using the BSL (bootloader) through the UART and I²C communication protocols.

Submit Document Feedback 107

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MSP430F5324

MSP430F5329, MSP430F5328, MSP430F5327, MSP430F5326, MSP430F5325, MSP430F5324

SLAS678G – AUGUST 2010 – REVISED SEPTEMBER 2020

www.ti.com

MSP-GANG Production Programmer

The MSP Gang Programmer is an MSP430 or MSP432 device programmer that can program up to eight

identical MSP430 or MSP432 Flash or FRAM devices at the same time. The MSP Gang Programmer connects

to a host PC using a standard RS-232 or USB connection and provides flexible programming options that allow

the user to fully customize the process. The MSP Gang Programmer is provided with an expansion board, called

the Gang Splitter, that implements the interconnections between the MSP Gang Programmer and multiple target

devices. Eight cables are provided that connect the expansion board to eight target devices (through JTAG or

Spy-Bi-Wire connectors). The programming can be done with a PC or as a stand-alone device. A PC-side

graphical user interface is also available and is DLL-based.

10.4 Documentation Support

The following documents describe the MSP430F532x MCUs. Copies of these documents are available on the

Internet at www.ti.com.

Receiving Notification of Document Updates

To receive notification of documentation updates—including silicon errata—go to the product folder for your

device on ti.com (for links to the product folders, see Table 10-2). In the upper right corner, click the "Alert me"

button. This registers you to receive a weekly digest of product information that has changed (if any). For change

details, check the revision history of any revised document.

Errata

MSP430F5329 Device Erratasheet

Describes the known exceptions to the functional specifications for all silicon revisions of the device.

MSP430F5328 Device Erratasheet

Describes the known exceptions to the functional specifications for all silicon revisions of the device.

MSP430F5327 Device Erratasheet

Describes the known exceptions to the functional specifications for all silicon revisions of the device.

MSP430F5326 Device Erratasheet

Describes the known exceptions to the functional specifications for all silicon revisions of the device.

MSP430F5325 Device Erratasheet

Describes the known exceptions to the functional specifications for all silicon revisions of the device.

MSP430F5324 Device Erratasheet

Describes the known exceptions to the functional specifications for all silicon revisions of the device.

User's Guides

MSP430F5xx and MSP430F6xx Family User's Guide

Detailed information on the modules and peripherals available in this device family.

MSP430 Flash Device Bootloader (BSL) User's Guide

The MSP430 bootloader (BSL) lets users communicate with embedded memory in the MSP430 microcontroller

during the prototyping phase, final production, and in service. Both the programmable memory (flash memory)

and the data memory (RAM) can be modified as required. Do not confuse the bootloader with the bootstrap

loader programs found in some digital signal processors (DSPs) that automatically load program code (and data)

from external memory to the internal memory of the DSP.

108 Submit Document Feedback

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MSP430F5324

MSP430F5329, MSP430F5328, MSP430F5327, MSP430F5326, MSP430F5325, MSP430F5324

www.ti.com

SLAS678G – AUGUST 2010 – REVISED SEPTEMBER 2020

MSP430 Programming With the JTAG Interface

This document describes the functions that are required to erase, program, and verify the memory module of the

MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In addition,

it describes how to program the JTAG access security fuse that is available on all MSP430 devices. This

document describes device access using both the standard 4-wire JTAG interface and the 2-wire JTAG

interface, which is also referred to as Spy-Bi-Wire (SBW).

MSP430 Hardware Tools User's Guide

This manual describes the hardware of the TI MSP-FET430 Flash Emulation Tool (FET). The FET is the

program development tool for the MSP430 ultra-low-power microcontroller. Both available interface types, the

parallel port interface and the USB interface, are described.

Application Reports

MSP430 32-kHz Crystal Oscillators

Selection of the right crystal, correct load circuit, and proper board layout are important for a stable crystal

oscillator. This application report summarizes crystal oscillator function and explains the parameters to select the

correct crystal for MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout

are given. The document also contains detailed information on the possible oscillator tests to ensure stable

oscillator operation in mass production.

MSP430 System-Level ESD Considerations

System-Level ESD has become increasingly demanding with silicon technology scaling towards lower voltages

and the need for designing cost-effective and ultra-low-power components. This application report addresses

three different ESD topics to help board designers and OEMs understand and design robust system-level

designs: (1) Component-level ESD testing and system-level ESD testing, their differences and why component-

level ESD rating does not ensure system-level robustness. (2) General design guidelines for system-level ESD

protection at different levels including enclosures, cables, PCB layout, and on-board ESD protection devices. (3)

Introduction to System Efficient ESD Design (SEED), a co-design methodology of on-board and on-chip ESD

protection to achieve system-level ESD robustness, with example simulations and test results. A few real-world

system-level ESD protection design examples and their results are also discussed.

Advanced Debugging Using the Enhanced Emulation Module (EEM) With CCS v6

This document describes the benefits of the Enhanced Emulation Module (EEM) advanced debugging features

that are available in the MSP430 devices and how they can be used with Code Composer Studio (CCS) version

6 software development tool. The EEM advanced debugging features support both precision analog and full-

speed digital debugging. The configuration of the debug environment for maximum control and the use of the

embedded trace capability are described. Some techniques that allow rapid development and design-for-

testability are demonstrated.

10.5 Related Links

Table 10-2 lists quick access links. Categories include technical documents, support and community resources,

tools and software, and quick access to sample or buy.

Table 10-2. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

ORDER NOW

MSP430F5329

MSP430F5328

MSP430F5327

MSP430F5326

MSP430F5325

MSP430F5324

Click here

Submit Document Feedback 109

Product Folder Links: MSP430F5329 MSP430F5328 MSP430F5327 MSP430F5326 MSP430F5325

MSP430F5324

MSP430F5329, MSP430F5328, MSP430F5327, MSP430F5326, MSP430F5325, MSP430F5324

SLAS678G – AUGUST 2010 – REVISED SEPTEMBER 2020

www.ti.com

10.6 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

10.7 Trademarks

MSP430^™, MicroStar Junior^™, MSP430Ware^™, Code Composer Studio^™, EnergyTrace^™, ULP Advisor^™, TI

E2E^™are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

10.8 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

10.9 Export Control Notice

Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as

defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled

product restricted by other applicable national regulations, received from disclosing party under nondisclosure

obligations (if any), or any direct product of such technology, to any destination to which such export or re-export

is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.

Department of Commerce and other competent Government authorities to the extent required by those laws.

10.10 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

110

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MSP430F5324

MSP430F5329, MSP430F5328, MSP430F5327, MSP430F5326, MSP430F5325, MSP430F5324

www.ti.com

SLAS678G – AUGUST 2010 – REVISED SEPTEMBER 2020

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

111

Product Folder Links: MSP430F5329 MSP430F5328 MSP430F5327 MSP430F5326 MSP430F5325

MSP430F5324

PACKAGE MATERIALS INFORMATION

www.ti.com

13-Sep-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

MSP430F5324IRGCR

MSP430F5324IRGCT

MSP430F5324IZQER

VQFN

RGC

ZQE

64

80

2000

250

330.0

180.0

330.0

16.4

12.4

9.3

5.3

9.3

5.3

1.5

12.0

8.0

16.0

12.0

Q2

Q1

BGA MI

CROSTA

R JUNI

OR

2500

MSP430F5324IZXHR

MSP430F5325IPNR

MSP430F5326IRGCR

MSP430F5326IRGCT

MSP430F5326IZQER

NFBGA

LQFP

ZXH

PN

80

64

80

2500

1000

2000

250

330.0

180.0

330.0

12.4

24.4

16.4

12.4

5.3

15.0

9.3

5.3

15.0

9.3

1.5

2.1

1.5

8.0

20.0

12.0

8.0

12.0

24.0

16.0

12.0

Q1

Q2

Q1

VQFN

RGC

ZQE

9.3

BGA MI

CROSTA

R JUNI

OR

2500

5.3

MSP430F5326IZXHR

MSP430F5327IPNR

MSP430F5328IRGCR

MSP430F5328IRGCT

MSP430F5328IZQER

NFBGA

LQFP

ZXH

PN

80

64

80

2500

1000

2000

250

330.0

180.0

330.0

12.4

24.4

16.4

12.4

5.3

15.0

9.3

5.3

15.0

9.3

1.5

2.1

1.5

8.0

20.0

12.0

8.0

12.0

24.0

16.0

12.0

Q1

Q2

Q1

VQFN

RGC

ZQE

9.3

BGA MI

2500

5.3

CROSTA

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

13-Sep-2020

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

R JUNI

OR

MSP430F5328IZXHR

MSP430F5329IPNR

NFBGA

LQFP

ZXH

PN

80

2500

1000

330.0

12.4

24.4

5.3

1.5

2.1

8.0

12.0

24.0

Q1

Q2

15.0

20.0

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

MSP430F5324IRGCR

MSP430F5324IRGCT

MSP430F5324IZQER

VQFN

RGC

ZQE

64

80

2000

250

367.0

210.0

350.0

367.0

185.0

350.0

38.0

35.0

43.0

BGA MICROSTAR

JUNIOR

2500

MSP430F5324IZXHR

MSP430F5325IPNR

MSP430F5326IRGCR

MSP430F5326IRGCT

MSP430F5326IZQER

NFBGA

LQFP

ZXH

PN

80

64

80

2500

1000

2000

250

350.0

367.0

210.0

350.0

367.0

185.0

350.0

43.0

38.0

35.0

43.0

VQFN

RGC

ZQE

BGA MICROSTAR

JUNIOR

2500

MSP430F5326IZXHR

MSP430F5327IPNR

MSP430F5328IRGCR

MSP430F5328IRGCT

NFBGA

LQFP

ZXH

PN

80

64

2500

1000

2000

250

350.0

367.0

210.0

350.0

367.0

185.0

43.0

38.0

35.0

VQFN

RGC

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

13-Sep-2020

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

MSP430F5328IZQER

BGA MICROSTAR

JUNIOR

ZQE

80

2500

350.0

43.0

MSP430F5328IZXHR

MSP430F5329IPNR

NFBGA

LQFP

ZXH

PN

80

2500

1000

350.0

43.0

Pack Materials-Page 3

GENERIC PACKAGE VIEW

RGC 64

9 x 9, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224597/A

www.ti.com

PACKAGE OUTLINE

RGC0064B

VQFN - 1 mm max height

S

C

A

L

E

1

.

5

0

PLASTIC QUAD FLATPACK - NO LEAD

9.15

8.85

A

B

PIN 1 INDEX AREA

9.15

8.85

1.0

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

2X 7.5

SYMM

EXPOSED

THERMAL PAD

(0.2) TYP

17

32

16

33

65

SYMM

2X 7.5

4.25 0.1

60X

0.5

1

48

0.30

0.18

64X

49

64

PIN 1 ID

0.1

C A B

0.5

0.3

64X

0.05

4219010/A 10/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGC0064B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

4.25)

SEE SOLDER MASK

DETAIL

SYMM

64X (0.6)

49

64

64X (0.24)

1

48

60X (0.5)

(R0.05) TYP

(1.18) TYP

(8.8)

65

SYMM

(0.695) TYP

(

0.2) TYP

VIA

33

16

32

17

(0.695) TYP

(1.18) TYP

(8.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219010/A 10/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGC0064B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

64X (0.6)

64

49

64X (0.24)

1

48

60X (0.5)

(R0.05) TYP

9X ( 1.19)

65

SYMM

(8.8)

(1.39)

33

16

17

32

(1.39)

(8.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 10X

EXPOSED PAD 65

71% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4219010/A 10/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

ZXH0080A

NFBGA - 1 mm max height

S

C

A

L

E

3

.

0

BALL GRID ARRAY

5.1

4.9

A

B

BALL A1 CORNER

INDEX AREA

5.1

4.9

0.7

0.6

C

1 MAX

SEATING PLANE

0.08 C

BALL TYP

0.25

TYP

0.15

4 TYP

SYMM

J

H

G

F

SYMM

80X

4

E

D

C

B

A

TYP

0.35

0.25

0.15

0.05

C B

C

A

0.5 TYP

1

2

3

4

5

6

7

8

9

0.5 TYP

4221325/A 01/2014

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis is for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This is a Pb-free solder ball design.

www.ti.com

EXAMPLE BOARD LAYOUT

ZXH0080A

NFBGA - 1 mm max height

BALL GRID ARRAY

(0.5) TYP

0.265

0.235

80X

6

7

9

2

3

4

5

8

1

A

B

C

(0.5) TYP

D

E

F

G

H

J

SYMM

LAND PATTERN EXAMPLE

SCALE:15X

0.05 MAX

0.05 MIN

METAL

UNDER

MASK

(

0.25)

METAL

(

0.25)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4221325/A 01/2014

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

See Texas Instruments Literature No. SBVA017 (www.ti.com/lit/sbva017).

www.ti.com

EXAMPLE STENCIL DESIGN

ZXH0080A

NFBGA - 1 mm max height

BALL GRID ARRAY

(0.5) TYP

80X ( 0.25)

(R0.05) TYP

5

4

3

6

7

9

2

8

1

A

(0.5)

TYP

B

C

METAL

TYP

D

E

F

G

H

J

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:20X

4221325/A 01/2014

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

MECHANICAL DATA

MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996

PN (S-PQFP-G80)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

60

M

0,08

41

61

40

0,13 NOM

80

21

1

20

Gage Plane

9,50 TYP

0,25

12,20

SQ

11,80

0,05 MIN

0°–7°

14,20

SQ

13,80

0,75

0,45

1,45

1,35

Seating Plane

0,08

1,60 MAX

4040135 /B 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	MSP430F5326IZXHR
厂家：	TEXAS INSTRUMENTS
描述：	MSP430F532x Mixed-Signal Microcontrollers 微控制器
文件：	总127页 (文件大小：3953K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MSP430F5326IZXHR [TI]

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MSP430F5328IRGC

MSP430F5328IRGCR

MSP430F5328IRGCT

MSP430F5328IZQE

MSP430F5328IZQER