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MSP430F5528IZQE [TI]

MIXED SIGNAL MICROCONTROLLER; 混合信号微控制器
MSP430F5528IZQE
型号： MSP430F5528IZQE
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

MIXED SIGNAL MICROCONTROLLER
混合信号微控制器

微控制器和处理器 外围集成电路 装置 时钟
文件： 总115页 (文件大小：1126K)
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MSP430F551x  
MSP430F552x  
www.ti.com  
SLAS590D –OCTOBER 2009–REVISED APRIL 2010  
MIXED SIGNAL MICROCONTROLLER  
1
FEATURES  
•
Low Supply-Voltage Range: 1.8 V to 3.6 V  
•
•
•
•
•
16-Bit Timer TA0, Timer_A With Five  
Capture/Compare Registers  
•
Ultralow Power Consumption  
16-Bit Timer TA1, Timer_A With Three  
Capture/Compare Registers  
–
Active Mode (AM):  
All System Clocks Active  
290 µA/MHz at 8 MHz, 3.0 V, Flash Program  
Execution (Typical)  
150 µA/MHz at 8 MHz, 3.0 V, RAM Program  
Execution (Typical)  
16-Bit Timer TA2, Timer_A With Three  
Capture/Compare Registers  
16-Bit Timer TB0, Timer_B With Seven  
Capture/Compare Shadow Registers  
–
Standby Mode (LPM3):  
Two Universal Serial Communication  
Interfaces  
Real Time Clock With Crystal , Watchdog,  
and Supply Supervisor Operational, Full  
RAM Retention, Fast Wake-Up:  
1.9 µA at 2.2 V, 2.1 µA at 3.0 V (Typical)  
Low-Power Oscillator (VLO),  
General-Purpose Counter, Watchdog, and  
Supply Supervisor Operational, Full RAM  
Retention, Fast Wake-Up:  
–
–
USCI_A0 and USCI_A1 Each Supporting  
–
Enhanced UART supporting  
Auto-Baudrate Detection  
–
–
IrDA Encoder and Decoder  
Synchronous SPI  
USCI_B0 and USCI_B1 Each Supporting  
1.4 µA at 3.0 V (Typical)  
–
–
I2CTM  
–
–
Off Mode (LPM4):  
Synchronous SPI  
Full RAM Retention, Supply Supervisor  
Operational, Fast Wake-Up:  
1.1 µA at 3.0 V (Typical)  
•
•
Full-Speed Universal Serial Bus (USB)  
–
–
–
–
Integrated USB-PHY  
Integrated 3.3-V/1.8-V USB Power System  
Integrated USB-PLL  
Shutdown Mode (LPM4.5):  
0.18 µA at 3.0 V (Typical)  
•
•
•
Wake-Up From Standby Mode in Less Than  
5 µs  
Eight Input, Eight Output Endpoints  
12-Bit Analog-to-Digital (A/D) Converter  
(MSP430F552x Only) With Internal Reference,  
Sample-and-Hold, and Autoscan Feature  
16-Bit RISC Architecture, Extended Memory,  
up to 25-MHz System Clock  
Flexible Power Management System  
•
•
Comparator  
–
Fully Integrated LDO With Programmable  
Regulated Core Supply Voltage  
Hardware Multiplier Supporting 32-Bit  
Operations  
–
Supply Voltage Supervision, Monitoring,  
and Brownout  
•
Serial Onboard Programming, No External  
Programming Voltage Needed  
•
Unified Clock System  
•
•
•
•
Three Channel Internal DMA  
–
–
–
FLL Control Loop for Frequency  
Stabilization  
Basic Timer With Real-Time Clock Feature  
Family Members are Summarized in Table 1  
Low Power/Low Frequency Internal Clock  
Source (VLO)  
For Complete Module Descriptions, See the  
MSP430x5xx Family User's Guide (SLAU208)  
Low Frequency Trimmed Internal Reference  
Source (REFO)  
–
–
32-kHz Watch Crystals (XT1)  
High-Frequency Crystals up to 32 MHz  
(XT2)  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009–2010, Texas Instruments Incorporated  
MSP430F551x  
MSP430F552x  
SLAS590D –OCTOBER 2009–REVISED APRIL 2010  
www.ti.com  
DESCRIPTION  
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring  
different sets of peripherals targeted for various applications. The architecture, combined with extensive  
low-power modes, is optimized to achieve extended battery life in portable measurement applications. The  
device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to  
maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to  
active mode in less than 5 µs.  
The MSP430F5529, MSP430F5527, MSP430F5525, and MSP430F5521 are microcontroller configurations with  
integrated USB and PHY supporting USB 2.0, four 16-bit timers, a high-performance 12-bit analog-to-digital  
converter (ADC), two universal serial communication interfaces (USCI), hardware multiplier, DMA, real-time clock  
module with alarm capabilities, and 63 I/O pins. The MSP430F5528, MSP430F5526, MSP430F5524, and  
MSP430F5522 include all of these peripherals but have 47 I/O pins.  
The MSP430F5519, MSP430F5517, and MSP430F5515 are microcontroller configurations with integrated USB  
and PHY supporting USB 2.0, four 16-bit timers, two universal serial communication interfaces (USCI), hardware  
multiplier, DMA, real time clock module with alarm capabilities, and 63 I/O pins. The MSP430F5514 and  
MSP430FF5513 include all of these peripherals but have 47 I/O pins.  
Typical applications include analog and digital sensor systems, data loggers, etc. that require connectivity to  
various USB hosts.  
Family members available are summarized in Table 1.  
Table 1. Family Members  
USCI  
Flash  
(KB)  
SRAM  
(KB)(1)  
ADC12_A  
(Ch)  
Comp_B  
(Ch)  
Package  
Type  
Timer_A(2) Timer_B(3)  
I/O  
Channel A: Channel B:  
UART/IrDA/  
Device  
SPI/I2C  
SPI  
MSP430F5529  
MSP430F5528  
MSP430F5527  
MSP430F5526  
MSP430F5525  
MSP430F5524  
128  
128  
96  
8 + 2  
8 + 2  
6 + 2  
6 + 2  
4 + 2  
4 + 2  
5, 3, 3  
5, 3, 3  
5, 3, 3  
5, 3, 3  
5, 3, 3  
5, 3, 3  
7
7
7
7
7
7
2
2
2
2
2
2
2
2
2
2
2
2
14 ext / 2 int  
10 ext / 2 int  
14 ext / 2 int  
10 ext / 2 int  
14 ext / 2 int  
10 ext / 2 int  
12  
8
63  
47  
63  
47  
63  
47  
80 PN  
64 RGC,  
80 ZQE  
12  
8
80 PN  
64 RGC,  
80 ZQE  
96  
64  
12  
8
80 PN  
64 RGC,  
80 ZQE  
64  
64 RGC,  
80 ZQE  
MSP430F5522  
32  
8 + 2  
5, 3, 3  
7
2
2
10 ext / 2 int  
8
47  
MSP430F5521  
MSP430F5519  
MSP430F5517  
MSP430F5515  
32  
128  
96  
6 + 2  
8 + 2  
6 + 2  
4 + 2  
5, 3, 3  
5, 3, 3  
5, 3, 3  
5, 3, 3  
7
7
7
7
2
2
2
2
2
2
2
2
14 ext/ 2 int  
12  
12  
12  
12  
63  
63  
63  
63  
80 PN  
80 PN  
80 PN  
80 PN  
-
-
-
64  
64 RGC,  
80 ZQE  
MSP430F5514  
MSP430F5513  
64  
32  
4 + 2  
4 + 2  
5, 3, 3  
5, 3, 3  
7
7
2
2
2
2
-
-
8
8
47  
47  
64 RGC,  
80 ZQE  
(1) The additional 2 KB USB SRAM that is listed can be used as general purpose SRAM when USB is not in use.  
(2) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM  
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first  
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.  
(3) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM  
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first  
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.  
2
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Copyright © 2009–2010, Texas Instruments Incorporated  
 
MSP430F551x  
MSP430F552x  
www.ti.com  
SLAS590D –OCTOBER 2009–REVISED APRIL 2010  
ORDERING INFORMATION(1)  
PACKAGED DEVICES(2)  
TA  
PLASTIC 80-PIN TQFP (PN)  
PLASTIC 64-PIN QFN (RGC)  
PLASTIC 80-BALL BGA (ZQE)  
MSP430F5529IPN  
MSP430F5527IPN  
MSP430F5525IPN  
MSP430F5521IPN  
MSP430F5519IPN  
MSP430F5517IPN  
MSP430F5515IPN  
MSP430F5528IRGC  
MSP430F5526IRGC  
MSP430F5524IRGC  
MSP430F5522IRGC  
MSP430F5514IRGC  
MSP430F5513IRGC  
MSP430F5528IZQE  
MSP430F5526IZQE  
MSP430F5524IZQE  
MSP430F5522IZQE  
MSP430F5514IZQE  
MSP430F5513IZQE  
–40°C to 85°C  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
Functional Block Diagram – MSP430F5529IPN, MSP430F5527IPN, MSP430F5525IPN,  
MSP430F5521IPN  
PA  
PB  
PC  
PD  
XIN XOUT  
DVCC DVSS VCORE AVCC AVSS  
RST/NMI  
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x  
DP,DM,PUR  
XT2IN  
SYS  
ACLK  
Power  
Management  
I/O Ports  
P1/P2  
2×8 I/Os  
Interrupt  
& Wakeup  
I/O Ports  
P3/P4  
2×8 I/Os  
I/O Ports  
P5/P6  
2×8 I/Os  
I/O Ports  
P7/P8  
1×8 I/Os  
1×3 I/Os  
Unified  
Clock  
System  
Full-speed  
USB  
Watchdog  
128KB  
96KB  
64KB  
32KB  
8KB+2KB  
6KB+2KB  
4KB+2KB  
XT2OUT  
SMCLK  
Port Map  
Control  
(P4)  
USB-PHY  
USB-LDO  
USB-PLL  
LDO  
SVM/SVS  
Brownout  
MCLK  
PA  
1×16 I/Os  
PB  
1×16 I/Os  
PC  
1×16 I/Os  
PD  
1×11 I/Os  
Flash  
RAM  
MAB  
MDB  
CPUXV2  
and  
Working  
Registers  
DMA  
3 Channel  
EEM  
(L: 8+2)  
ADC12_A  
USCI0,1  
TA2  
TB0  
12 Bit  
200 KSPS  
TA0  
TA1  
USCI_Ax:  
UART,  
IrDA, SPI  
JTAG/  
SBW  
Interface  
REF  
COMP_B  
RTC_A  
MPY32  
CRC16  
Timer_A  
5 CC  
Registers  
Timer_A  
3 CC  
Registers  
Timer_A  
3 CC  
Registers  
Timer_B  
7 CC  
Registers  
12 Channels  
16 Channels  
(14 ext/2 int)  
Autoscan  
USCI_Bx:  
SPI, I2C  
Copyright © 2009–2010, Texas Instruments Incorporated  
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3
MSP430F551x  
MSP430F552x  
SLAS590D –OCTOBER 2009–REVISED APRIL 2010  
www.ti.com  
Pin Designation – MSP430F5529IPN, MSP430F5527IPN, MSP430F5525IPN, MSP430F5521IPN  
PN PACKAGE  
(TOP VIEW)  
1
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
P7.7/TB0CLK/MCLK  
P7.6/TB0.4  
P6.4/CB4/A4  
P6.5/CB5/A5  
2
3
P7.5/TB0.3  
P6.6/CB6/A6  
4
P7.4/TB0.2  
P6.7/CB7/A7  
P7.0/CB8/A12  
P7.1/CB9/A13  
5
P5.7/TB0.1  
6
P5.6/TB0.0  
P4.7/PM_NONE  
P7.2/CB10/A14  
P7.3/CB11/A15  
P5.0/A8/VREF+/VeREF+  
P5.1/A9/VREF−/VeREF−  
AVCC1  
7
P4.6/PM_NONE  
8
P4.5/PM_UCA1RXD/PM_UCA1SOMI  
P4.4/PM_UCA1TXD/PM_UCA1SIMO  
DVCC2  
9
MSP430F5529IPN  
MSP430F5527IPN  
MSP430F5525IPN  
MSP430F5521IPN  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
DVSS2  
P5.4/XIN  
P5.5/XOUT  
AVSS1  
P4.3/PM_UCB1CLK/PM_UCA1STE  
P4.2/PM_UCB1SOMI/PM_UCB1SCL  
P4.1/PM_UCB1SIMO/PM_UCB1SDA  
P4.0/PM_UCB1STE/PM_UCA1CLK  
P8.0  
P8.1  
P8.2  
P3.7/TB0OUTH/SVMOUT  
P3.6/TB0.6  
P3.5/TB0.5  
DVCC1  
DVSS1  
VCORE  
P3.4/UCA0RXD/UCA0SOMI  
A0.3  
A0.4  
A1.0  
P1.4/T  
P1.5/T  
P1.7/T  
A2CLK/SMCLK  
A1CLK/CBOUT  
P2.2/T  
P1.6/T  
4
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Copyright © 2009–2010, Texas Instruments Incorporated  
MSP430F551x  
MSP430F552x  
www.ti.com  
SLAS590D –OCTOBER 2009–REVISED APRIL 2010  
Functional Block Diagram – MSP430F5528IRGC, MSP430F5526IRGC, MSP430F5524IRGC,  
MSP430F5522IRGC, MSP430F5528IZQE, MSP430F5526IZQE, MSP430F5524IZQE,  
MSP430F5522IZQE  
PA  
PB  
PC  
XIN XOUT  
DVCC DVSS VCORE AVCC AVSS  
RST/NMI  
P1.x P2.x P3.x P4.x P5.x P6.x  
DP,DM,PUR  
XT2IN  
SYS  
ACLK  
Power  
Management  
I/O Ports  
P1/P2  
2×8 I/Os  
Interrupt  
& Wakeup  
I/O Ports  
P3/P4  
1×5 I/Os  
1×8 I/Os  
I/O Ports  
P5/P6  
1×6 I/Os  
1×8 I/Os  
Unified  
Clock  
System  
Full-speed  
USB  
Watchdog  
128KB  
96KB  
64KB  
32KB  
8KB+2KB  
6KB+2KB  
4KB+2KB  
XT2OUT  
SMCLK  
Port Map  
Control  
(P4)  
USB-PHY  
USB-LDO  
USB-PLL  
LDO  
SVM/SVS  
Brownout  
MCLK  
PA  
1×16 I/Os  
PB  
1×13 I/Os  
PC  
1×14 I/Os  
Flash  
RAM  
MAB  
MDB  
CPUXV2  
and  
Working  
Registers  
DMA  
3 Channel  
EEM  
(L: 8+2)  
ADC12_A  
USCI0,1  
TA2  
TB0  
12 Bit  
200 KSPS  
TA0  
TA1  
USCI_Ax:  
UART,  
IrDA, SPI  
JTAG/  
SBW  
Interface  
REF  
COMP_B  
RTC_A  
MPY32  
CRC16  
Timer_A  
5 CC  
Registers  
Timer_A  
3 CC  
Registers  
Timer_A  
3 CC  
Registers  
Timer_B  
7 CC  
Registers  
8 Channels  
12 Channels  
(10 ext/2 int)  
Autoscan  
USCI_Bx:  
SPI, I2C  
Copyright © 2009–2010, Texas Instruments Incorporated  
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5
MSP430F551x  
MSP430F552x  
SLAS590D –OCTOBER 2009–REVISED APRIL 2010  
www.ti.com  
Pin Designation – MSP430F5528IRGC, MSP430F5526IRGC, MSP430F5524IRGC,  
MSP430F5522IRGC  
RGC PACKAGE  
(TOP VIEW)  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
P4.7/PM_NONE  
P4.6/PM_NONE  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
P6.0/CB0/A0  
P6.1/CB1/A1  
2
3
P4.5/PM_UCA1RXD/PM_UCA1SOMI  
P4.4/PM_UCA1TXD/PM_UCA1SIMO  
P4.3/PM_UCB1CLK/PM_UCA1STE  
P4.2/PM_UCB1SOMI/PM_UCB1SCL  
P4.1/PM_UCB1SIMO/PM_UCB1SDA  
P4.0/PM_UCB1STE/PM_UCA1CLK  
DVCC2  
P6.2/CB2/A2  
4
P6.3/CB3/A3  
P6.4/CB4/A4  
5
P6.5/CB5/A5  
6
P6.6/CB6/A6  
7
MSP430F5528IRGC  
MSP430F5526IRGC  
MSP430F5524IRGC  
MSP430F5522IRGC  
P6.7/CB7/A7  
8
P5.0/A8/VREF+/VeREF+  
P5.1/A9/VREF−/VeREF−  
AVCC1  
9
DVSS2  
10  
11  
12  
13  
14  
15  
16  
P3.4/UCA0RXD/UCA0SOMI  
P3.3/UCA0TXD/UCA0SIMO  
P3.2/UCB0CLK/UCA0STE  
P3.1/UCB0SOMI/UCB0SCL  
P3.0/UCB0SIMO/UCB0SDA  
P2.7/UCB0STE/UCA0CLK  
P5.4/XIN  
P5.5/XOUT  
AVSS1  
DVCC1  
DVSS1  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
A0.3  
A0.4  
A1.0  
A1.2  
A1.1  
P1.4/T  
P1.5/T  
P1.7/T  
P2.1/T  
P2.0/T  
A1CLK/CBOUT  
A2CLK/SMCLK  
P1.6/T  
P2.2/T  
6
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Copyright © 2009–2010, Texas Instruments Incorporated  
MSP430F551x  
MSP430F552x  
www.ti.com  
SLAS590D –OCTOBER 2009–REVISED APRIL 2010  
Functional Block Diagram – MSP430F5519IPN, MSP430F5517IPN, MSP430F5515IPN  
PA  
PB  
PC  
PD  
XIN XOUT  
DVCC DVSS VCORE AVCC AVSS  
RST/NMI  
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x  
DP,DM,PUR  
XT2IN  
SYS  
ACLK  
Power  
Management  
I/O Ports  
P1/P2  
2×8 I/Os  
Interrupt  
& Wakeup  
I/O Ports  
P3/P4  
2×8 I/Os  
I/O Ports  
P5/P6  
2×8 I/Os  
I/O Ports  
P7/P8  
1×8 I/Os  
1×3 I/Os  
Unified  
Clock  
System  
Full-speed  
USB  
Watchdog  
128KB  
96KB  
64KB  
4KB+2KB  
RAM  
XT2OUT  
SMCLK  
Port Map  
Control  
(P4)  
USB-PHY  
USB-LDO  
USB-PLL  
LDO  
SVM/SVS  
Brownout  
MCLK  
Flash  
PA  
1×16 I/Os  
PB  
1×16 I/Os  
PC  
1×16 I/Os  
PD  
1×11 I/Os  
MAB  
MDB  
CPUXV2  
and  
Working  
Registers  
DMA  
3 Channel  
EEM  
(L: 8+2)  
USCI0,1  
TA0  
TA1  
TA2  
TB0  
USCI_Ax:  
UART,  
IrDA, SPI  
JTAG/  
SBW  
Interface  
COMP_B  
RTC_A  
MPY32  
CRC16  
Timer_A  
5 CC  
Registers  
Timer_A  
3 CC  
Registers  
Timer_A  
3 CC  
Registers  
Timer_B  
7 CC  
Registers  
12 Channels  
USCI_Bx:  
SPI, I2C  
Copyright © 2009–2010, Texas Instruments Incorporated  
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7
MSP430F551x  
MSP430F552x  
SLAS590D –OCTOBER 2009–REVISED APRIL 2010  
www.ti.com  
Pin Designation – MSP430F5519IPN, MSP430F5517IPN, MSP430F5515IPN  
PN PACKAGE  
(TOP VIEW)  
1
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
P7.7/TB0CLK/MCLK  
P7.6/TB0.4  
P6.4/CB4  
P6.5/CB5  
P6.6/CB6  
P6.7/CB7  
P7.0/CB8  
P7.1/CB9  
P7.2/CB10  
P7.3/CB11  
P5.0  
2
3
P7.5/TB0.3  
4
P7.4/TB0.2  
5
P5.7/TB0.1  
6
P5.6/TB0.0  
P4.7/PM_NONE  
P4.6/PM_NONE  
7
8
P4.5/PM_UCA1RXD/PM_UCA1SOMI  
P4.4/PM_UCA1TXD/PM_UCA1SIMO  
DVCC2  
9
MSP430F5519IPN  
MSP430F5517IPN  
MSP430F5515IPN  
P5.1  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
AVCC1  
DVSS2  
P5.4/XIN  
P5.5/XOUT  
AVSS1  
P4.3/PM_UCB1CLK/PM_UCA1STE  
P4.2/PM_UCB1SOMI/PM_UCB1SCL  
P4.1/PM_UCB1SIMO/PM_UCB1SDA  
P4.0/PM_UCB1STE/PM_UCA1CLK  
P3.7/TB0OUTH/SVMOUT  
P3.6/TB0.6  
P8.0  
P8.1  
P8.2  
DVCC1  
DVSS1  
VCORE  
P3.5/TB0.5  
P3.4/UCA0RXD/UCA0SOMI  
A0.3  
A0.4  
A1.0  
P1.4/T  
P1.5/T  
P1.7/T  
A2CLK/SMCLK  
A1CLK/CBOUT  
P2.2/T  
P1.6/T  
8
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Functional Block Diagram – MSP430F5514IRGC, MSP430F5513IRGC, MSP430F5514IZQE,  
MSP430F5513IZQE  
PA  
PB  
PC  
XIN XOUT  
DVCC DVSS VCORE AVCC AVSS  
RST/NMI  
P1.x P2.x P3.x P4.x P5.x P6.x  
DP,DM,PUR  
XT2IN  
SYS  
ACLK  
Power  
Management  
I/O Ports  
P1/P2  
2×8 I/Os  
Interrupt  
& Wakeup  
I/O Ports  
P3/P4  
1×5 I/Os  
1×8 I/Os  
I/O Ports  
P5/P6  
1×6 I/Os  
1×8 I/Os  
Unified  
Clock  
System  
Full-speed  
USB  
Watchdog  
64KB  
32KB  
4KB+2KB  
RAM  
XT2OUT  
SMCLK  
Port Map  
Control  
(P4)  
USB-PHY  
USB-LDO  
USB-PLL  
LDO  
SVM/SVS  
Brownout  
MCLK  
Flash  
PA  
1×16 I/Os  
PB  
1×13 I/Os  
PC  
1×14 I/Os  
MAB  
MDB  
CPUXV2  
and  
Working  
Registers  
DMA  
3 Channel  
EEM  
(L: 8+2)  
USCI0,1  
TA0  
TA1  
TA2  
TB0  
USCI_Ax:  
UART,  
IrDA, SPI  
JTAG/  
SBW  
Interface  
COMP_B  
RTC_A  
MPY32  
CRC16  
Timer_A  
5 CC  
Registers  
Timer_A  
3 CC  
Registers  
Timer_A  
3 CC  
Registers  
Timer_B  
7 CC  
Registers  
8 Channels  
USCI_Bx:  
SPI, I2C  
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Pin Designation – MSP430F5514IRGC, MSP430F5513IRGC  
RGC PACKAGE  
(TOP VIEW)  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
P4.7/PM_NONE  
P4.6/PM_NONE  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
P6.0/CB0  
P6.1/CB1  
P6.2/CB2  
P6.3/CB3  
P6.4/CB4  
P6.5/CB5  
P6.6/CB6  
P6.7/CB7  
P5.0  
2
3
P4.5/PM_UCA1RXD/PM_UCA1SOMI  
P4.4/PM_UCA1TXD/PM_UCA1SIMO  
P4.3/PM_UCB1CLK/PM_UCA1STE  
P4.2/PM_UCB1SOMI/PM_UCB1SCL  
P4.1/PM_UCB1SIMO/PM_UCB1SDA  
P4.0/PM_UCB1STE/PM_UCA1CLK  
DVCC2  
4
5
6
7
8
MSP430F5514IRGC  
MSP430F5513IRGC  
9
P5.1  
DVSS2  
10  
11  
12  
13  
14  
15  
16  
AVCC1  
P3.4/UCA0RXD/UCA0SOMI  
P3.3/UCA0TXD/UCA0SIMO  
P3.2/UCB0CLK/UCA0STE  
P3.1/UCB0SOMI/UCB0SCL  
P3.0/UCB0SIMO/UCB0SDA  
P2.7/UCB0STE/UCA0CLK  
P5.4/XIN  
P5.5/XOUT  
AVSS1  
DVCC1  
DVSS1  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
A0.3  
A0.4  
A1.0  
A1.2  
A1.1  
P1.4/T  
P1.5/T  
P1.7/T  
P2.1/T  
P2.0/T  
A1CLK/CBOUT  
A2CLK/SMCLK  
P1.6/T  
P2.2/T  
10  
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Pin Designation – MSP430F5528IZQE, MSP430F5526IZQE, MSP430F5524IZQE,  
MSP430F5522IZQE, MSP430F5514IZQE, MSP430F5513IZQE  
ZQE PACKAGE  
(TOP VIEW)  
A1  
B1  
C1  
D1  
E1  
F1  
G1  
H1  
J1  
A2  
B2  
C2  
D2  
E2  
F2  
G2  
H2  
J2  
A3  
B3  
A4  
B4  
C4  
D4  
E4  
F4  
G4  
H4  
J4  
A5  
B5  
C5  
D5  
E5  
F5  
G5  
H5  
J5  
A6  
B6  
C6  
D6  
E6  
F6  
G6  
H6  
J6  
A7  
B7  
C7  
D7  
E7  
F7  
G7  
H7  
J7  
A8  
B8  
C8  
D8  
E8  
F8  
G8  
H8  
J8  
A9  
B9  
C9  
D9  
E9  
F9  
G9  
H9  
J9  
D3  
E3  
F3  
G3  
H3  
J3  
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Table 2. TERMINAL FUNCTIONS  
TERMINAL  
NO.  
I/O(1)  
DESCRIPTION  
NAME  
PN RGC ZQE  
General-purpose digital I/O  
P6.4/CB4/A4  
P6.5/CB5/A5  
P6.6/CB6/A6  
P6.7/CB7/A7  
1
2
3
4
5
6
7
8
C1  
D2  
D1  
D3  
I/O Comparator_B input CB4  
Analog input A4 – ADC (not available on '551x devices)  
General-purpose digital I/O  
I/O Comparator_B input CB5  
Analog input A5 – ADC (not available on '551x devices)  
General-purpose digital I/O  
I/O Comparator_B input CB6  
Analog input A6 – ADC (not available on '551x devices)  
General-purpose digital I/O  
I/O Comparator_B input CB7  
Analog input A7 – ADC (not available on '551x devices)  
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,  
'5513 devices)  
P7.0/CB8/A12  
5
6
N/A N/A  
N/A N/A  
N/A N/A  
N/A N/A  
I/O Comparator_B input CB8 (not available on '5528, '5526, '5524, '5522, '5514,  
'5513 devices)  
Analog input A12 – ADC (not available on '551x devices)  
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,  
'5513 devices)  
I/O Comparator_B input CB9 (not available on '5528, '5526, '5524, '5522, '5514,  
'5513 devices)  
P7.1/CB9/A13  
Analog input A13 – ADC (not available on '551x devices)  
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,  
'5513 devices)  
I/O Comparator_B input CB10 (not available on '5528, '5526, '5524, '5522, '5514,  
'5513 devices)  
P7.2/CB10/A14  
7
Analog input A14 – ADC (not available on '551x devices)  
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,  
'5513 devices)  
I/O Comparator_B input CB11 (not available on '5528, '5526, '5524, '5522, '5514,  
'5513 devices)  
P7.3/CB11/A15  
8
Analog input A15 – ADC (not available on '551x devices)  
General-purpose digital I/O  
Output of reference voltage to the ADC (not available on '551x devices)  
I/O Input for an external reference voltage to the ADC (not available on '551x  
devices)  
P5.0/A8/VREF+/VeREF+  
P5.1/A9/VREF-/VeREF-  
9
9
E1  
E2  
Analog input A8 – ADC (not available on '551x devices)  
General-purpose digital I/O  
Negative terminal for the ADC's reference voltage for both sources, the  
I/O internal reference voltage, or an external applied reference voltage (not  
available on '551x devices)  
10  
10  
Analog input A9 – ADC (not available on '551x devices)  
AVCC1  
11  
12  
11  
12  
F2  
F1  
Analog power supply  
General-purpose digital I/O  
I/O  
P5.4/XIN  
Input terminal for crystal oscillator XT1  
General-purpose digital I/O  
I/O  
P5.5/XOUT  
13  
13  
14  
G1  
G2  
Output terminal of crystal oscillator XT1  
AVSS1  
P8.0  
14  
15  
16  
17  
18  
19  
Analog ground supply  
I/O General-purpose digital I/O  
I/O General-purpose digital I/O  
I/O General-purpose digital I/O  
Digital power supply  
N/A N/A  
N/A N/A  
N/A N/A  
P8.1  
P8.2  
DVCC1  
DVSS1  
15  
16  
H1  
J1  
Digital ground supply  
(1) I = input, O = output, N/A = not available  
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Table 2. TERMINAL FUNCTIONS (continued)  
TERMINAL  
NO.  
I/O(1)  
DESCRIPTION  
NAME  
PN RGC ZQE  
Regulated core power supply output (internal usage only, no external current  
loading)  
VCORE(2)  
20  
21  
17  
18  
J2  
General-purpose digital I/O with port interrupt  
TA0 clock signal TA0CLK input ; ACLK output (divided by 1, 2, 4, or 8)  
P1.0/TA0CLK/ACLK  
P1.1/TA0.0  
H2  
I/O  
General-purpose digital I/O with port interrupt  
I/O TA0 CCR0 capture: CCI0A input, compare: Out0 output  
BSL transmit output  
22  
23  
19  
20  
H3  
J3  
General-purpose digital I/O with port interrupt  
I/O TA0 CCR1 capture: CCI1A input, compare: Out1 output  
BSL receive input  
P1.2/TA0.1  
General-purpose digital I/O with port interrupt  
TA0 CCR2 capture: CCI2A input, compare: Out2 output  
P1.3/TA0.2  
P1.4/TA0.3  
P1.5/TA0.4  
24  
25  
26  
21  
22  
23  
G4  
H4  
J4  
I/O  
General-purpose digital I/O with port interrupt  
TA0 CCR3 capture: CCI3A input compare: Out3 output  
I/O  
General-purpose digital I/O with port interrupt  
TA0 CCR4 capture: CCI4A input, compare: Out4 output  
I/O  
General-purpose digital I/O with port interrupt  
I/O TA1 clock signal TA1CLK input  
Comparator_B output  
P1.6/TA1CLK/CBOUT  
27  
24  
G5  
General-purpose digital I/O with port interrupt  
TA1 CCR0 capture: CCI0A input, compare: Out0 output  
P1.7/TA1.0  
28  
29  
30  
31  
32  
33  
34  
25  
26  
27  
28  
29  
30  
31  
H5  
J5  
I/O  
General-purpose digital I/O with port interrupt  
TA1 CCR1 capture: CCI1A input, compare: Out1 output  
P2.0/TA1.1  
I/O  
General-purpose digital I/O with port interrupt  
TA1 CCR2 capture: CCI2A input, compare: Out2 output  
P2.1/TA1.2  
G6  
J6  
I/O  
General-purpose digital I/O with port interrupt  
I/O  
P2.2/TA2CLK/SMCLK  
P2.3/TA2.0  
TA2 clock signal TA2CLK input ; SMCLK output  
General-purpose digital I/O with port interrupt  
TA2 CCR0 capture: CCI0A input, compare: Out0 output  
H6  
J7  
I/O  
General-purpose digital I/O with port interrupt  
TA2 CCR1 capture: CCI1A input, compare: Out1 output  
P2.4/TA2.1  
I/O  
General-purpose digital I/O with port interrupt  
TA2 CCR2 capture: CCI2A input, compare: Out2 output  
P2.5/TA2.2  
J8  
I/O  
General-purpose digital I/O with port interrupt  
I/O RTC clock output for calibration  
DMA external trigger input  
P2.6/RTCCLK/DMAE0  
35  
36  
32  
33  
J9  
General-purpose digital I/O  
Slave transmit enable – USCI_B0 SPI mode  
Clock signal input – USCI_A0 SPI slave mode  
P2.7/UCB0STE/UCA0CLK  
H7  
I/O  
Clock signal output – USCI_A0 SPI master mode  
General-purpose digital I/O  
P3.0/UCB0SIMO/UCB0SDA  
P3.1/UCB0SOMI/UCB0SCL  
37  
38  
34  
35  
H8  
H9  
I/O Slave in, master out – USCI_B0 SPI mode  
I2C data – USCI_B0 I2C mode  
General-purpose digital I/O  
I/O Slave out, master in – USCI_B0 SPI mode  
I2C clock – USCI_B0 I2C mode  
General-purpose digital I/O  
Clock signal input – USCI_B0 SPI slave mode  
Clock signal output – USCI_B0 SPI master mode  
Slave transmit enable – USCI_A0 SPI mode  
P3.2/UCB0CLK/UCA0STE  
P3.3/UCA0TXD/UCA0SIMO  
39  
40  
36  
37  
G8  
G9  
I/O  
General-purpose digital I/O  
I/O Transmit data – USCI_A0 UART mode  
Slave in, master out – USCI_A0 SPI mode  
(2) VCORE is for internal usage only. No external current loading is possible. VCORE should only be connected to the recommended  
capacitor value, CVCORE  
.
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Table 2. TERMINAL FUNCTIONS (continued)  
TERMINAL  
NO.  
I/O(1)  
DESCRIPTION  
NAME  
PN RGC ZQE  
General-purpose digital I/O  
P3.4/UCA0RXD/UCA0SOMI  
P3.5/TB0.5  
41  
42  
43  
38  
G7  
I/O Receive data – USCI_A0 UART mode  
Slave out, master in – USCI_A0 SPI mode  
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,  
I/O '5513 devices)  
N/A N/A  
N/A N/A  
TB0 CCR5 capture: CCI5A input, compare: Out5 output  
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,  
I/O '5513 devices)  
P3.6/TB0.6  
TB0 CCR6 capture: CCI6A input, compare: Out6 output  
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,  
'5513 devices)  
P3.7/TB0OUTH/SVMOUT  
44  
45  
N/A N/A  
I/O Switch all PWM outputs high impedance input – TB0 (not available on '5528,  
'5526, '5524, '5522, '5514, '5513 devices)  
SVM output (not available on '5528, '5526, '5524, '5522, '5514, '5513 devices)  
General-purpose digital I/O with reconfigurable port mapping secondary  
function  
I/O Default mapping: Slave transmit enable – USCI_B1 SPI mode  
Default mapping: Clock signal input – USCI_A1 SPI slave mode  
Default mapping: Clock signal output – USCI_A1 SPI master mode  
P4.0/PM_UCB1STE/  
PM_UCA1CLK  
41  
E8  
General-purpose digital I/O with reconfigurable port mapping secondary  
P4.1/PM_UCB1SIMO/  
PM_UCB1SDA  
function  
46  
47  
42  
43  
E7  
D9  
I/O  
Default mapping: Slave in, master out – USCI_B1 SPI mode  
Default mapping: I2C data – USCI_B1 I2C mode  
General-purpose digital I/O with reconfigurable port mapping secondary  
function  
Default mapping: Slave out, master in – USCI_B1 SPI mode  
P4.2/PM_UCB1SOMI/  
PM_UCB1SCL  
I/O  
Default mapping: I2C clock – USCI_B1 I2C mode  
General-purpose digital I/O with reconfigurable port mapping secondary  
function  
I/O Default mapping: Clock signal input – USCI_B1 SPI slave mode  
Default mapping: Clock signal output – USCI_B1 SPI master mode  
Default mapping: Slave transmit enable – USCI_A1 SPI mode  
P4.3/PM_UCB1CLK/  
PM_UCA1STE  
48  
44  
D8  
DVSS2  
DVCC2  
49  
50  
39  
40  
F9  
E9  
Digital ground supply  
Digital power supply  
General-purpose digital I/O with reconfigurable port mapping secondary  
P4.4/PM_UCA1TXD/  
PM_UCA1SIMO  
function  
51  
52  
45  
46  
D7  
C9  
I/O  
Default mapping: Transmit data – USCI_A1 UART mode  
Default mapping: Slave in, master out – USCI_A1 SPI mode  
General-purpose digital I/O with reconfigurable port mapping secondary  
function  
Default mapping: Receive data – USCI_A1 UART mode  
P4.5/PM_UCA1RXD/  
PM_UCA1SOMI  
I/O  
Default mapping: Slave out, master in – USCI_A1 SPI mode  
General-purpose digital I/O with reconfigurable port mapping secondary  
I/O function  
P4.6/PM_NONE  
P4.7/PM_NONE  
53  
54  
47  
48  
C8  
C7  
Default mapping: no secondary function.  
General-purpose digital I/O with reconfigurable port mapping secondary  
I/O function  
Default mapping: no secondary function.  
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,  
'5513 devices)  
P5.6/TB0.0  
P5.7/TB0.1  
55  
56  
N/A N/A  
N/A N/A  
I/O  
TB0 CCR0 capture: CCI0A input, compare: Out0 output (not available on  
'5528, '5526, '5524, '5522, '5514, '5513 devices)  
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,  
'5513 devices)  
TB0 CCR1 capture: CCI1A input, compare: Out1 output (not available on  
I/O  
'5528, '5526, '5524, '5522, '5514, '5513 devices)  
14  
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SLAS590D –OCTOBER 2009–REVISED APRIL 2010  
Table 2. TERMINAL FUNCTIONS (continued)  
TERMINAL  
NO.  
I/O(1)  
DESCRIPTION  
NAME  
PN RGC ZQE  
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,  
'5513 devices)  
TB0 CCR2 capture: CCI2A input, compare: Out2 output (not available on  
'5528, '5526, '5524, '5522, '5514, '5513 devices)  
P7.4/TB0.2  
P7.5/TB0.3  
P7.6/TB0.4  
57  
58  
59  
N/A N/A  
N/A N/A  
N/A N/A  
I/O  
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,  
'5513 devices)  
TB0 CCR3 capture: CCI3A input, compare: Out3 output (not available on  
'5528, '5526, '5524, '5522, '5514, '5513 devices)  
I/O  
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,  
'5513 devices)  
TB0 CCR4 capture: CCI4A input, compare: Out4 output (not available on  
'5528, '5526, '5524, '5522, '5514, '5513 devices)  
I/O  
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,  
'5513 devices)  
TB0 clock signal TBCLK input (not available on '5528, '5526, '5524, '5522,  
'5514, '5513 devices)  
MCLK output (not available on '5528, '5526, '5524, '5522, '5514, '5513  
devices)  
P7.7/TB0CLK/MCLK  
VSSU  
60  
61  
N/A N/A  
I/O  
B8,  
49  
B9  
USB PHY ground supply  
General-purpose digital I/O - controlled by USB control register  
USB data terminal DP  
PU.0/DP  
PUR  
62  
63  
64  
50  
51  
52  
A9  
B7  
A8  
I/O  
I/O USB pullup resistor pin (open drain)  
General-purpose digital I/O - controlled by USB control register  
USB data terminal DM  
PU.1/DM  
I/O  
VBUS  
VUSB  
V18  
65  
66  
67  
68  
53  
54  
55  
56  
A7  
A6  
B6  
A5  
USB LDO input (connect to USB power source)  
USB LDO output  
USB regulated power (internal usage only, no external current loading)  
Analog ground supply  
AVSS2  
General-purpose digital I/O  
I/O  
P5.2/XT2IN  
69  
70  
71  
72  
73  
74  
75  
57  
58  
59  
60  
61  
62  
63  
B5  
B4  
A4  
C5  
C4  
A3  
B3  
Input terminal for crystal oscillator XT2  
General-purpose digital I/O  
I/O  
P5.3/XT2OUT  
TEST/SBWTCK(3)  
PJ.0/TDO(4)  
Output terminal of crystal oscillator XT2  
Test mode pin – Selects four wire JTAG operation.  
Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated  
I
General-purpose digital I/O  
I/O  
JTAG test data output port  
General-purpose digital I/O  
I/O  
PJ.1/TDI/TCLK(4)  
PJ.2/TMS(4)  
JTAG test data input or test clock input  
General-purpose digital I/O  
I/O  
JTAG test mode select  
General-purpose digital I/O  
JTAG test clock  
PJ.3/TCK(4)  
I/O  
Reset input active low  
I/O Non-maskable interrupt input  
RST/NMI/SBWTDIO(3)  
P6.0/CB0/A0  
76  
77  
78  
64  
1
A2  
A1  
B2  
Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated.  
General-purpose digital I/O  
I/O Comparator_B input CB0  
Analog input A0 – ADC (not available on '551x devices)  
General-purpose digital I/O  
I/O Comparator_B input CB1  
P6.1/CB1/A1  
2
Analog input A1 – ADC (not available on '551x devices)  
(3) Please refer to Bootstrap Loader (BSL) and JTAG Operation for usage with BSL and JTAG functions  
(4) Please refer to JTAG Operation for usage with JTAG function.  
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Table 2. TERMINAL FUNCTIONS (continued)  
TERMINAL  
NO.  
I/O(1)  
DESCRIPTION  
NAME  
PN RGC ZQE  
General-purpose digital I/O  
I/O Comparator_B input CB2  
P6.2/CB2/A2  
79  
80  
3
4
B1  
Analog input A2 – ADC (not available on '551x devices)  
General-purpose digital I/O  
I/O Comparator_B input CB3  
P6.3/CB3/A3  
Reserved  
C2  
Analog input A3 – ADC (not available on '551x devices)  
(5)  
N/A N/A  
(5) C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground.  
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SHORT-FORM DESCRIPTION  
CPU  
The MSP430 CPU has a 16-bit RISC architecture  
that is highly transparent to the application. All  
operations, other than program-flow instructions, are  
performed as register operations in conjunction with  
seven addressing modes for source operand and four  
addressing modes for destination operand.  
Program Counter  
PC/R0  
Stack Pointer  
SP/R1  
SR/CG1/R2  
CG2/R3  
R4  
Status Register  
Constant Generator  
The CPU is integrated with 16 registers that provide  
reduced  
instruction  
execution  
time.  
The  
General-Purpose Register  
General-Purpose Register  
General-Purpose Register  
General-Purpose Register  
General-Purpose Register  
General-Purpose Register  
General-Purpose Register  
General-Purpose Register  
General-Purpose Register  
General-Purpose Register  
General-Purpose Register  
General-Purpose Register  
register-to-register operation execution time is one  
cycle of the CPU clock.  
R5  
Four of the registers, R0 to R3, are dedicated as  
program counter, stack pointer, status register, and  
constant generator, respectively. The remaining  
registers are general-purpose registers.  
R6  
R7  
R8  
Peripherals are connected to the CPU using data,  
address, and control buses, and can be handled with  
all instructions.  
R9  
R10  
The instruction set consists of the original 51  
instructions with three formats and seven address  
modes and additional instructions for the expanded  
address range. Each instruction can operate on word  
and byte data.  
R11  
R12  
R13  
R14  
R15  
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Operating Modes  
The MSP430 has one active mode and six software selectable low-power modes of operation. An interrupt event  
can wake up the device from any of the low-power modes, service the request, and restore back to the  
low-power mode on return from the interrupt program.  
The following seven operating modes can be configured by software:  
•
Active mode (AM)  
All clocks are active  
Low-power mode 0 (LPM0)  
–
•
–
–
–
CPU is disabled  
ACLK and SMCLK remain active, MCLK is disabled  
FLL loop control remains active  
•
•
Low-power mode 1 (LPM1)  
–
–
–
CPU is disabled  
FLL loop control is disabled  
ACLK and SMCLK remain active, MCLK is disabled  
Low-power mode 2 (LPM2)  
–
–
–
–
CPU is disabled  
MCLK and FLL loop control and DCOCLK are disabled  
DCO's dc-generator remains enabled  
ACLK remains active  
•
•
Low-power mode 3 (LPM3)  
–
–
–
–
CPU is disabled  
MCLK, FLL loop control, and DCOCLK are disabled  
DCO's dc generator is disabled  
ACLK remains active  
Low-power mode 4 (LPM4)  
–
–
–
–
–
–
CPU is disabled  
ACLK is disabled  
MCLK, FLL loop control, and DCOCLK are disabled  
DCO's dc generator is disabled  
Crystal oscillator is stopped  
Complete data retention  
•
Low-power mode 4.5 (LPM4.5)  
–
–
–
Internal regulator disabled  
No data retention  
Wakeup from RST/NMI, P1, and P2  
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Interrupt Vector Addresses  
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The  
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.  
Table 3. Interrupt Sources, Flags, and Vectors  
SYSTEM  
INTERRUPT  
WORD  
ADDRESS  
INTERRUPT SOURCE  
INTERRUPT FLAG  
PRIORITY  
System Reset  
Power-Up  
External Reset  
Watchdog Timeout, Password  
Violation  
WDTIFG, KEYV (SYSRSTIV)(1) (2)  
Reset  
0FFFEh  
63, highest  
Flash Memory Password Violation  
System NMI  
PMM  
Vacant Memory Access  
JTAG Mailbox  
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,  
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,  
JMBOUTIFG (SYSSNIV)(1)  
(Non)maskable  
(Non)maskable  
0FFFCh  
0FFFAh  
62  
61  
User NMI  
NMI  
Oscillator Fault  
NMIIFG, OFIFG, ACCVIFG, BUSIFG  
(SYSUNIV)(1) (2)  
Flash Memory Access Violation  
Comp_B  
TB0  
Comparator B interrupt flags (CBIV)(1) (3)  
Maskable  
Maskable  
0FFF8h  
0FFF6h  
60  
59  
(3)  
TB0CCR0 CCIFG0  
TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,  
TB0IFG (TB0IV)(1) (3)  
TB0  
Maskable  
Maskable  
0FFF4h  
0FFF2h  
58  
57  
Watchdog Timer_A Interval Timer  
Mode  
WDTIFG  
USCI_A0 Receive/Transmit  
USCI_B0 Receive/Transmit  
ADC12_A  
UCA0RXIFG, UCA0TXIFG (UCA0IV)(1) (3)  
UCB0RXIFG, UCB0TXIFG (UCAB0IV)(1) (3)  
ADC12IFG0 to ADC12IFG15 (ADC12IV)(1) (3) (4)  
TA0CCR0 CCIFG0(3)  
Maskable  
Maskable  
Maskable  
Maskable  
0FFF0h  
0FFEEh  
0FFECh  
0FFEAh  
56  
55  
54  
53  
TA0  
TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,  
TA0IFG (TA0IV)(1) (3)  
TA0  
Maskable  
0FFE8h  
52  
USB_UBM  
DMA  
USB interrupts (USBIV)(1) (3)  
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)(1) (3)  
TA1CCR0 CCIFG0(3)  
Maskable  
Maskable  
Maskable  
0FFE6h  
0FFE4h  
0FFE2h  
51  
50  
49  
TA1  
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,  
TA1IFG (TA1IV)(1) (3)  
TA1  
Maskable  
0FFE0h  
48  
I/O Port P1  
USCI_A1 Receive/Transmit  
USCI_B1 Receive/Transmit  
TA2  
P1IFG.0 to P1IFG.7 (P1IV)(1) (3)  
UCA1RXIFG, UCA1TXIFG (UCA1IV)(1) (3)  
UCB1RXIFG, UCB1TXIFG (UCB1IV)(1) (3)  
TA2CCR0 CCIFG0(3)  
Maskable  
Maskable  
Maskable  
Maskable  
0FFDEh  
0FFDCh  
0FFDAh  
0FFD8h  
47  
46  
45  
44  
TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,  
TA2IFG (TA2IV)(1) (3)  
TA2  
Maskable  
Maskable  
Maskable  
0FFD6h  
0FFD4h  
0FFD2h  
43  
42  
41  
I/O Port P2  
RTC_A  
P2IFG.0 to P2IFG.7 (P2IV)(1) (3)  
RTCRDYIFG, RTCTEVIFG, RTCAIFG,  
RT0PSIFG, RT1PSIFG (RTCIV)(1) (3)  
0FFD0h  
⋮
40  
⋮
Reserved  
Reserved(5)  
0FF80h  
0, lowest  
(1) Multiple source flags  
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.  
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.  
(3) Interrupt flags are located in the module.  
(4) Only on devices with ADC, otherwise reserved.  
(5) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain  
compatibility with other devices, it is recommended to reserve these locations.  
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Memory Organization  
Table 4. Memory Organization(1)  
MSP430F5525  
MSP430F5522  
MSP430F5521  
MSP430F5513  
MSP430F5527  
MSP430F5526  
MSP430F5517  
MSP430F5529  
MSP430F5528  
MSP430F5519  
MSP430F5524  
MSP430F5515  
MSP430F5514  
Memory (flash)  
Total Size  
32 KB  
64 KB  
96 KB  
128 KB  
Main: interrupt vector  
00FFFFh–00FF80h  
00FFFFh–00FF80h  
00FFFFh–00FF80h  
00FFFFh–00FF80h  
N/A  
N/A  
N/A  
32 KB  
0243FFh–01C400h  
Bank 3  
Bank 2  
Bank 1  
N/A  
N/A  
32 KB  
01C3FFh–014400h  
32 KB  
01C3FFh–014400h  
Main: code memory  
15 KB  
00FFFFh–00C400h  
32 KB  
0143FFh–00C400h  
32 KB  
0143FFh–00C400h  
32 KB  
0143FFh–00C400h  
17 KB  
00C3FFh–008000h  
32 KB  
00C3FFh–004400h  
32 KB  
00C3FFh–004400h  
32 KB  
00C3FFh–004400h  
Bank 0  
Sector 3  
2 KB(2)  
N/A  
N/A  
2 KB  
0043FFh–003C00h  
0043FFh–003C00h  
Sector 2  
Sector 1  
Sector 0  
Sector 7  
Info A  
2 KB(3)  
003BFFh–003400h  
N/A  
2 KB  
003BFFh–003400h  
2 KB  
003BFFh–003400h  
RAM  
2 KB  
0033FFh–002C00h  
2 KB  
0033FFh–002C00h  
2 KB  
0033FFh–002C00h  
2 KB  
0033FFh–002C00h  
2 KB  
002BFFh–002400h  
2 KB  
002BFFh–002400h  
2 KB  
002BFFh–002400h  
2 KB  
002BFFh–002400h  
2 KB  
0023FFh–001C00h  
2 KB  
0023FFh–001C00h  
2 KB  
0023FFh–001C00h  
2 KB  
0023FFh–001C00h  
USB RAM(4)  
128 B  
128 B  
128 B  
128 B  
0019FFh–001980h  
0019FFh–001980h  
0019FFh–001980h  
0019FFh–001980h  
Info B  
128 B  
128 B  
128 B  
128 B  
00197Fh–001900h  
00197Fh–001900h  
00197Fh–001900h  
00197Fh–001900h  
Information memory  
(flash)  
Info C  
128 B  
128 B  
128 B  
128 B  
0018FFh–001880h  
0018FFh–001880h  
0018FFh–001880h  
0018FFh–001880h  
Info D  
128 B  
128 B  
128 B  
128 B  
00187Fh–001800h  
00187Fh–001800h  
00187Fh–001800h  
00187Fh–001800h  
BSL 3  
BSL 2  
BSL 1  
BSL 0  
Size  
512 B  
0017FFh–001600h  
512 B  
0017FFh–001600h  
512 B  
0017FFh–001600h  
512 B  
0017FFh–001600h  
512 B  
0015FFh–001400h  
512 B  
0015FFh–001400h  
512 B  
0015FFh–001400h  
512 B  
0015FFh–001400h  
Bootstrap loader (BSL)  
memory (flash)  
512 B  
0013FFh–001200h  
512 B  
0013FFh–001200h  
512 B  
0013FFh–001200h  
512 B  
0013FFh–001200h  
512 B  
0011FFh–001000h  
512 B  
0011FFh–001000h  
512 B  
0011FFh–001000h  
512 B  
0011FFh–001000h  
4 KB  
000FFFh–0h  
4 KB  
000FFFh–0h  
4 KB  
000FFFh–0h  
4 KB  
000FFFh–0h  
Peripherals  
(1) N/A = Not available  
(2) 'F5522 only  
(3) 'F5522, 'F5521 only  
(4) USB RAM can be used as general purpose RAM when not used for USB operation.  
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Bootstrap Loader (BSL)  
The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to the  
device memory via the BSL is protected by an user-defined password. For complete description of the features of  
the BSL and its implementation, see the MSP430 Memory Programming User's Guide, literature number  
SLAU265.  
USB BSL  
All devices come pre-programmed with the USB BSL. Usage of the USB BSL requires external access to the six  
pins shown in Table 5. In addition to these pins, the application must support external components necessary for  
normal USB operation e.g. proper crystal on XT2IN and XT2OUT, proper decoupling, etc.  
Table 5. USB BSL Pin Requirements and Functions  
DEVICE SIGNAL  
RST/NMI/SBWTDIO  
PU.0/DP  
BSL FUNCTION  
Entry sequence signal  
USB data terminal DP  
USB data terminal DM  
USB pullup resistor terminal  
USB bus power supply  
USB ground supply  
PU.1/DM  
PUR  
VBUS  
VSSU  
UART BSL  
A UART BSL is also available that can be programmed by the user into the BSL memory by replacing the  
pre-programmed, factory supplied, USB BSL. Usage of the UART BSL requires external access to the six pins  
shown in Table 6.  
Table 6. UART BSL Pin Requirements and Functions  
DEVICE SIGNAL  
BSL FUNCTION  
Entry sequence signal  
Entry sequence signal  
Data transmit  
RST/NMI/SBWTDIO  
TEST/SBWTCK  
P1.1  
P1.2  
VCC  
VSS  
Data receive  
Power supply  
Ground supply  
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JTAG Operation  
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JTAG Standard Interface  
The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving  
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the  
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430  
development tools and device programmers. The JTAG pin requirements are shown in Table 7. For further  
details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's  
Guide, literature number SLAU278.  
Table 7. JTAG Pin Requirements and Functions  
DEVICE SIGNAL  
PJ.3/TCK  
DIRECTION  
FUNCTION  
JTAG clock input  
JTAG state control  
JTAG data input/TCLK input  
JTAG data output  
Enable JTAG pins  
External reset  
IN  
IN  
PJ.2/TMS  
PJ.1/TDI/TCLK  
PJ.0/TDO  
IN  
OUT  
IN  
TEST/SBWTCK  
RST/NMI/SBWTDIO  
VCC  
IN  
Power supply  
VSS  
Ground supply  
Spy-Bi-Wire Interface  
In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface.  
Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire  
interface pin requirements are shown in Table 8. For further details on interfacing to development tools and  
device programmers, see the MSP430 Hardware Tools User's Guide, literature number SLAU278.  
Table 8. Spy-Bi-Wire Pin Requirements and Functions  
DEVICE SIGNAL  
TEST/SBWTCK  
RST/NMI/SBWTDIO  
VCC  
DIRECTION  
IN  
FUNCTION  
Spy-Bi-Wire clock input  
Spy-Bi-Wire data input/output  
Power supply  
IN, OUT  
VSS  
Ground supply  
Flash Memory  
The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the  
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the  
flash memory include:  
•
Flash memory has n segments of main memory and four segments of information memory (A to D) of  
128 bytes each. Each segment in main memory is 512 bytes in size.  
•
•
•
Segments 0 to n may be erased in one step, or each segment may be individually erased.  
Segments A to D can be erased individually. Segments A to D are also called information memory.  
Segment A can be locked separately.  
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RAM Memory  
The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,  
however all data is lost. Features of the RAM memory include:  
•
•
•
•
RAM memory has n sectors. The size of a sector can be found in the Memory Organization section.  
Each sector 0 to n can be complete disabled, however data retention is lost.  
Each sector 0 to n automatically enters low power retention mode when possible.  
For Devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.  
Peripherals  
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all  
instructions. For complete module descriptions, see the MSP430x5xx Family User's Guide, literature number  
SLAU208.  
Digital I/O  
There are up to eight 8-bit I/O ports implemented: For 80 pin options, P1, P2, P3, P4, P5, P6, and P7 are  
complete. P8 is reduced to 3-bit I/O. For 64 pin options, P3 and P5 are reduced to 5-bit I/O and 6-bit I/O,  
respectively. P7 and P8 are completely removed. Port PJ contains four individual I/O ports, common to all  
devices.  
•
•
•
•
•
•
•
All individual I/O bits are independently programmable.  
Any combination of input, output, and interrupt conditions is possible.  
Pullup or pulldown on all ports is programmable.  
Drive strength on all ports is programmable.  
Edge-selectable interrupt and LPM4.5 wakeup input capability is available for all bits of ports P1 and P2.  
Read/write access to port-control registers is supported by all instructions.  
Ports can be accessed byte-wise (P1 through P8) or word-wise in pairs (PA through PD).  
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Port Mapping Controller  
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4.  
Table 9. Port Mapping, Mnemonics, and Functions  
VALUE  
PxMAPy MNEMONIC  
PM_NONE  
INPUT PIN FUNCTION  
OUTPUT PIN FUNCTION  
DVSS  
0
None  
PM_CBOUT0  
PM_TB0CLK  
-
Comparator_B output  
1
2
TB0 clock input  
PM_ADC12CLK  
PM_DMAE0  
-
ADC12CLK  
SVM output  
DMAE0 input  
-
PM_SVMOUT  
3
TB0 high impedance input  
TB0OUTH  
PM_TB0OUTH  
4
5
PM_TB0CCR0A  
PM_TB0CCR1A  
PM_TB0CCR2A  
PM_TB0CCR3A  
PM_TB0CCR4A  
PM_TB0CCR5A  
PM_TB0CCR6A  
PM_UCA1RXD  
PM_UCA1SOMI  
PM_UCA1TXD  
PM_UCA1SIMO  
PM_UCA1CLK  
PM_UCB1STE  
PM_UCB1SOMI  
PM_UCB1SCL  
PM_UCB1SIMO  
PM_UCB1SDA  
PM_UCB1CLK  
PM_UCA1STE  
PM_CBOUT1  
TB0 CCR0 capture input CCI0A  
TB0 CCR1 capture input CCI1A  
TB0 CCR2 capture input CCI2A  
TB0 CCR3 capture input CCI3A  
TB0 CCR4 capture input CCI4A  
TB0 CCR5 capture input CCI5A  
TB0 CCR6 capture input CCI6A  
TB0 CCR0 compare output Out0  
TB0 CCR1 compare output Out1  
TB0 CCR2 compare output Out2  
TB0 CCR3 compare output Out3  
TB0 CCR4 compare output Out4  
TB0 CCR5 compare output Out5  
TB0 CCR6 compare output Out6  
6
7
8
9
10  
USCI_A1 UART RXD (Direction controlled by USCI - input)  
USCI_A1 SPI slave out master in (direction controlled by USCI)  
USCI_A1 UART TXD (Direction controlled by USCI - output)  
USCI_A1 SPI slave in master out (direction controlled by USCI)  
USCI_A1 clock input/output (direction controlled by USCI)  
USCI_B1 SPI slave transmit enable (direction controlled by USCI)  
USCI_B1 SPI slave out master in (direction controlled by USCI)  
USCI_B1 I2C clock (open drain and direction controlled by USCI)  
USCI_B1 SPI slave in master out (direction controlled by USCI)  
USCI_B1 I2C data (open drain and direction controlled by USCI)  
USCI_B1 clock input/output (direction controlled by USCI)  
USCI_A1 SPI slave transmit enable (direction controlled by USCI)  
11  
12  
13  
14  
15  
16  
17  
18  
None  
None  
None  
Comparator_B output  
MCLK  
PM_MCLK  
19 - 30  
Reserved  
DVSS  
Disables the output driver as well as the input Schmitt-trigger to prevent  
parasitic cross currents when applying analog signals.  
31 (0FFh)(1)  
PM_ANALOG  
(1) The value of the PMPAP_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are  
ignored resulting in a read out value of 31.  
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Table 10. Default Mapping  
PIN  
PxMAPy MNEMONIC  
INPUT PIN FUNCTION  
OUTPUT PIN FUNCTION  
USCI_B1 SPI slave transmit enable (direction controlled by USCI)  
USCI_A1 clock input/output (direction controlled by USCI)  
P4.0/P4MAP0  
P4.1/P4MAP1  
P4.2/P4MAP2  
P4.3/P4MAP3  
P4.4/P4MAP4  
P4.5/P4MAP5  
PM_UCB1STE/PM_UCA1CLK  
USCI_B1 SPI slave in master out (direction controlled by USCI)  
USCI_B1 I2C data (open drain and direction controlled by USCI)  
PM_UCB1SIMO/PM_UCB1SDA  
PM_UCB1SOMI/PM_UCB1SCL  
PM_UCB1CLK/PM_UCA1STE  
PM_UCA1TXD/PM_UCA1SIMO  
PM_UCA1RXD/PM_UCA1SOMI  
USCI_B1 SPI slave out master in (direction controlled by USCI)  
USCI_B1 I2C clock (open drain and direction controlled by USCI)  
USCI_A1 SPI slave transmit enable (direction controlled by USCI)  
USCI_B1 clock input/output (direction controlled by USCI)  
USCI_A1 UART TXD (Direction controlled by USCI - output)  
USCI_A1 SPI slave in master out (direction controlled by USCI)  
USCI_A1 UART RXD (Direction controlled by USCI - input)  
USCI_A1 SPI slave out master in (direction controlled by USCI)  
P4.6/P4MAP6  
P4.7/P4MAP7  
PM_NONE  
PM_NONE  
None  
None  
DVSS  
DVSS  
Oscillator and System Clock  
The clock system in the MSP430F552x and MSP430F551x family of devices is supported by the Unified Clock  
System (UCS) module that includes support for a 32 kHz watch crystal oscillator (XT1 LF mode - XT1 HF mode  
not supported), an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency  
oscillator (REFO), an integrated internal digitally-controlled oscillator (DCO), and a high-frequency crystal  
oscillator XT2. The UCS module is designed to meet the requirements of both low system cost and low-power  
consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction with a  
digital modulator, stabilizes the DCO frequency to a programmable multiple of the selected FLL reference  
frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 5 µs. The UCS  
module provides the following clock signals:  
•
Auxiliary clock (ACLK), sourced from a 32 kHz watch crystal (XT1), a high-frequency crystal (XT2), the  
internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal  
digitally-controlled oscillator DCO.  
•
•
•
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made  
available to ACLK.  
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by  
same sources made available to ACLK.  
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.  
Power Management Module (PMM)  
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains  
programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor  
(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is  
implemented to provide the proper internal reset signal to the device during power-on and power-off. The  
SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply  
voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not  
automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.  
Hardware Multiplier  
The multiplication operation is supported by a dedicated peripheral module. The module performs operations with  
32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication  
as well as signed and unsigned multiply and accumulate operations.  
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Real-Time Clock (RTC_A)  
The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated  
real-time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers  
that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Calendar  
mode integrates an internal calendar which compensates for months with less than 31 days and includes leap  
year correction. The RTC_A also supports flexible alarm functions and offset-calibration hardware.  
Watchdog Timer (WDT_A)  
The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a  
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog  
function is not needed in an application, the module can be configured as an interval timer and can generate  
interrupts at selected time intervals.  
System Module (SYS)  
The SYS module handles many of the system functions within the device. These include power on reset and  
power up clear handling, NMI source selection and management, reset interrupt vector generators, boot strap  
loader entry mechanisms, as well as, configuration management (device descriptors). It also includes a data  
exchange mechanism via JTAG called a JTAG mailbox that can be used in the application.  
Table 11. System Module Interrupt Vector Registers  
INTERRUPT VECTOR REGISTER  
ADDRESS  
INTERRUPT EVENT  
No interrupt pending  
Brownout (BOR)  
VALUE  
00h  
PRIORITY  
019Eh  
02h  
Highest  
RST/NMI (POR)  
04h  
PMMSWBOR (BOR)  
Wakeup from LPMx.5  
Security violation (BOR)  
SVSL (POR)  
06h  
08h  
0Ah  
0Ch  
0Eh  
SVSH (POR)  
SVML_OVP (POR)  
SVMH_OVP (POR)  
PMMSWPOR (POR)  
WDT timeout (PUC)  
WDT password violation (PUC)  
KEYV flash password violation (PUC)  
FLL unlock (PUC)  
Peripheral area fetch (PUC)  
PMM password violation (PUC)  
Reserved  
10h  
SYSRSTIV , System Reset  
12h  
14h  
16h  
18h  
1Ah  
1Ch  
1Eh  
20h  
22h to 3Eh  
00h  
Lowest  
Highest  
019Ch  
No interrupt pending  
SVMLIFG  
02h  
SVMHIFG  
04h  
SVSMLDLYIFG  
06h  
SVSMHDLYIFG  
08h  
SYSSNIV , System NMI  
VMAIFG  
0Ah  
JMBINIFG  
0Ch  
0Eh  
JMBOUTIFG  
SVMLVLRIFG  
10h  
SVMHVLRIFG  
12h  
Reserved  
14h to 1Eh  
Lowest  
26  
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Table 11. System Module Interrupt Vector Registers (continued)  
INTERRUPT VECTOR REGISTER  
ADDRESS  
INTERRUPT EVENT  
No interrupt pending  
NMIFG  
VALUE  
00h  
PRIORITY  
019Ah  
02h  
Highest  
OFIFG  
04h  
SYSUNIV, User NMI  
ACCVIFG  
06h  
BUSIFG  
08h  
Reserved  
0Ah to 1Eh  
Lowest  
DMA Controller  
The DMA controller allows movement of data from one memory address to another without CPU intervention. For  
example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM. Using  
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system  
power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or  
from a peripheral.  
The USB timestamp generator also utilizes the DMA trigger assignments described in Table 12.  
Table 12. DMA Trigger Assignments(1)  
CHANNEL  
TRIGGER  
0
1
2
0
DMAREQ  
DMAREQ  
DMAREQ  
1
TA0CCR0 CCIFG  
TA0CCR2 CCIFG  
TA1CCR0 CCIFG  
TA1CCR2 CCIFG  
TA2CCR0 CCIFG  
TA2CCR2 CCIFG  
TB0CCR0 CCIFG  
TB0CCR2 CCIFG  
Reserved  
TA0CCR0 CCIFG  
TA0CCR2 CCIFG  
TA1CCR0 CCIFG  
TA1CCR2 CCIFG  
TA2CCR0 CCIFG  
TA2CCR2 CCIFG  
TB0CCR0 CCIFG  
TB0CCR2 CCIFG  
Reserved  
TA0CCR0 CCIFG  
TA0CCR2 CCIFG  
TA1CCR0 CCIFG  
TA1CCR2 CCIFG  
TA2CCR0 CCIFG  
TA2CCR2 CCIFG  
TB0CCR0 CCIFG  
TB0CCR2 CCIFG  
Reserved  
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
UCA0RXIFG  
UCA0TXIFG  
UCB0RXIFG  
UCB0TXIFG  
UCA1RXIFG  
UCA1TXIFG  
UCB1RXIFG  
UCB1TXIFG  
ADC12IFGx(2)  
Reserved  
UCA0RXIFG  
UCA0TXIFG  
UCB0RXIFG  
UCB0TXIFG  
UCA1RXIFG  
UCA1TXIFG  
UCB1RXIFG  
UCB1TXIFG  
ADC12IFGx(2)  
Reserved  
UCA0RXIFG  
UCA0TXIFG  
UCB0RXIFG  
UCB0TXIFG  
UCA1RXIFG  
UCA1TXIFG  
UCB1RXIFG  
UCB1TXIFG  
ADC12IFGx(2)  
Reserved  
Reserved  
Reserved  
Reserved  
USB FNRXD  
USB FNRXD  
USB FNRXD  
(1) If a reserved trigger source is selected, no Trigger1 is generated.  
(2) Only on devices with ADC. Reserved on devices without ADC.  
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Table 12. DMA Trigger Assignments (1) (continued)  
CHANNEL  
1
TRIGGER  
0
2
28  
29  
30  
31  
USB ready  
MPY ready  
DMA2IFG  
DMAE0  
USB ready  
MPY ready  
DMA0IFG  
DMAE0  
USB ready  
MPY ready  
DMA1IFG  
DMAE0  
Universal Serial Communication Interface (USCI)  
The USCI modules are used for serial data communication. The USCI module supports synchronous  
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as  
UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions,  
A and B.  
The USCI_An module provides support for SPI (3 pin or 4 pin), UART, enhanced UART, or IrDA.  
The USCI_Bn module provides support for SPI (3 pin or 4 pin) or I2C.  
The MSP430F55xx series includes two complete USCI modules (n = 0, 1).  
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TA0  
TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. It can support multiple  
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may  
be generated from the counter on overflow conditions and from each of the capture/compare registers.  
Table 13. TA0 Signal Connections  
INPUT PIN NUMBER  
DEVICE  
INPUT  
SIGNAL  
MODULE  
INPUT  
SIGNAL  
MODULE  
OUTPUT  
SIGNAL  
DEVICE  
OUTPUT  
SIGNAL  
OUTPUT PIN NUMBER  
MODULE  
BLOCK  
RGC/ZQE  
PN  
RGC/ZQE  
PN  
18/H2-P1.0  
21-P1.0  
TA0CLK  
TACLK  
ACLK  
(internal)  
ACLK  
Timer  
CCR0  
NA  
NA  
SMCLK  
(internal)  
SMCLK  
18/H2-P1.0  
19/H3-P1.1  
21-P1.0  
22-P1.1  
TA0CLK  
TA0.0  
DVSS  
TACLK  
CCI0A  
CCI0B  
GND  
19/H3-P1.1  
20/J3-P1.2  
22-P1.1  
23-P1.2  
TA0  
TA0.0  
DVSS  
DVCC  
VCC  
20/J3-P1.2  
23-P1.2  
24-P1.3  
TA0.1  
CCI1A  
ADC12  
(internal)(1)  
ADC12SHSx =  
{1}  
ADC12  
(internal)(1)  
ADC12SHSx =  
{1}  
CBOUT  
(internal)  
CCI1B  
CCR1  
CCR2  
TA1  
TA2  
TA0.1  
TA0.2  
DVSS  
DVCC  
TA0.2  
GND  
VCC  
21/G4-P1.3  
CCI2A  
21/G4-P1.3  
24-P1.3  
ACLK  
(internal)  
CCI2B  
DVSS  
DVCC  
TA0.3  
DVSS  
DVSS  
DVCC  
TA0.4  
DVSS  
DVSS  
DVCC  
GND  
VCC  
22/H4-P1.4  
23/J4-P1.5  
25-P1.4  
26-P1.5  
CCI3A  
CCI3B  
GND  
VCC  
22/H4-P1.4  
23/J4-P1.5  
25-P1.4  
26-P1.5  
CCR3  
CCR4  
TA3  
TA4  
TA0.3  
TA0.4  
CCI4A  
CCI4B  
GND  
VCC  
(1) Only on devices with ADC.  
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TA1  
TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple  
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may  
be generated from the counter on overflow conditions and from each of the capture/compare registers.  
Table 14. TA1 Signal Connections  
INPUT PIN NUMBER  
DEVICE  
INPUT  
SIGNAL  
MODULE  
INPUT  
SIGNAL  
MODULE  
OUTPUT  
SIGNAL  
DEVICE  
OUTPUT  
SIGNAL  
OUTPUT PIN NUMBER  
MODULE  
BLOCK  
RGC/ZQE  
PN  
RGC/ZQE  
PN  
24/G5-P1.6  
27-P1.6  
TA1CLK  
TACLK  
ACLK  
(internal)  
ACLK  
Timer  
NA  
NA  
SMCLK  
(internal)  
SMCLK  
24/G5-P1.6  
25/H5-P1.7  
27-P1.6  
28-P1.7  
TA1CLK  
TA1.0  
DVSS  
TACLK  
CCI0A  
CCI0B  
GND  
25/H5-P1.7  
26/J5-P2.0  
28-P1.7  
29-P2.0  
CCR0  
CCR1  
TA0  
TA1  
TA1.0  
TA1.1  
DVSS  
DVCC  
VCC  
26/J5-P2.0  
27/G6-P2.1  
29-P2.0  
30-P2.1  
TA1.1  
CCI1A  
CBOUT  
(internal)  
CCI1B  
DVSS  
DVCC  
TA1.2  
GND  
VCC  
CCI2A  
27/G6-P2.1  
30-P2.1  
ACLK  
(internal)  
CCI2B  
CCR2  
TA2  
TA1.2  
DVSS  
DVCC  
GND  
VCC  
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TA2  
TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple  
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may  
be generated from the counter on overflow conditions and from each of the capture/compare registers.  
Table 15. TA2 Signal Connections  
INPUT PIN NUMBER  
DEVICE  
INPUT  
SIGNAL  
MODULE  
INPUT  
SIGNAL  
MODULE  
OUTPUT  
SIGNAL  
DEVICE  
OUTPUT  
SIGNAL  
OUTPUT PIN NUMBER  
MODULE  
BLOCK  
RGC/ZQE  
PN  
RGC/ZQE  
PN  
28/J6-P2.2  
31-P2.2  
TA2CLK  
TACLK  
ACLK  
(internal)  
ACLK  
Timer  
NA  
NA  
SMCLK  
(internal)  
SMCLK  
28/J6-P2.2  
29/H6-P2.3  
31-P2.2  
32-P2.3  
TA2CLK  
TA2.0  
DVSS  
TACLK  
CCI0A  
CCI0B  
GND  
29/H6-P2.3  
30/J7-P2.4  
32-P2.3  
33-P2.4  
CCR0  
CCR1  
TA0  
TA1  
TA2.0  
TA2.1  
DVSS  
DVCC  
VCC  
30/J7-P2.4  
31/J8-P2.5  
33-P2.4  
34-P2.5  
TA2.1  
CCI1A  
CBOUT  
(internal)  
CCI1B  
DVSS  
DVCC  
TA2.2  
GND  
VCC  
CCI2A  
31/J8-P2.5  
34-P2.5  
ACLK  
(internal)  
CCI2B  
CCR2  
TA2  
TA2.2  
DVSS  
DVCC  
GND  
VCC  
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TB0  
TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. It can support multiple  
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may  
be generated from the counter on overflow conditions and from each of the capture/compare registers.  
Table 16. TB0 Signal Connections  
INPUT PIN NUMBER  
DEVICE  
INPUT  
SIGNAL  
MODULE  
INPUT  
SIGNAL  
MODULE  
OUTPUT  
SIGNAL  
DEVICE  
OUTPUT  
SIGNAL  
OUTPUT PIN NUMBER  
MODULE  
BLOCK  
RGC/ZQE(1)  
PN  
RGC/ZQE(1)  
PN  
60-P7.7  
TB0CLK  
TBCLK  
ACLK  
(internal)  
ACLK  
Timer  
CCR0  
CCR1  
NA  
TB0  
TB1  
NA  
SMCLK  
(internal)  
SMCLK  
60-P7.7  
55-P5.6  
TB0CLK  
TB0.0  
TBCLK  
CCI0A  
55-P5.6  
ADC12  
(internal)(2)  
ADC12SHSx =  
{2}  
ADC12  
(internal)(2)  
ADC12SHSx =  
{2}  
55-P5.6  
TB0.0  
CCI0B  
TB0.0  
TB0.1  
DVSS  
DVCC  
TB0.1  
GND  
VCC  
56-P5.7  
CCI1A  
56-P5.7  
ADC12 (internal) ADC12 (internal)  
CBOUT  
(internal)  
CCI1B  
ADC12SHSx =  
{3}  
ADC12SHSx =  
{3}  
DVSS  
DVCC  
TB0.2  
TB0.2  
DVSS  
DVCC  
TB0.3  
TB0.3  
DVSS  
DVCC  
TB0.4  
TB0.4  
DVSS  
DVCC  
TB0.5  
TB0.5  
DVSS  
DVCC  
TB0.6  
GND  
VCC  
57-P7.4  
57-P7.4  
CCI2A  
CCI2B  
GND  
57-P7.4  
58-P7.5  
59-P7.6  
42-P3.5  
43-P3.6  
CCR2  
CCR3  
CCR4  
CCR5  
TB2  
TB3  
TB4  
TB5  
TB0.2  
TB0.3  
TB0.4  
TB0.5  
VCC  
58-P7.5  
58-P7.5  
CCI3A  
CCI3B  
GND  
VCC  
59-P7.6  
59-P7.6  
CCI4A  
CCI4B  
GND  
VCC  
42-P3.5  
42-P3.5  
CCI5A  
CCI5B  
GND  
VCC  
43-P3.6  
CCI6A  
ACLK  
(internal)  
CCI6B  
CCR6  
TB6  
TB0.6  
DVSS  
DVCC  
GND  
VCC  
(1) Timer functions selectable via the port mapping controller.  
(2) Only on devices with ADC.  
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Comparator_B  
The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions,  
battery voltage supervision, and monitoring of external analog signals.  
ADC12_A  
The ADC12_A module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR  
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The  
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any  
CPU intervention.  
CRC16  
The CRC16 module produces a signature based on a sequence of entered data values and can be used for data  
checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.  
REF Voltage Reference  
The reference module (REF) is responsible for generation of all critical reference voltages that can be used by  
the various analog peripherals in the device.  
USB Universal Serial Bus  
The USB module is a fully integrated USB interface that is compliant with the USB 2.0 specification. The module  
supports full-speed operation of control, interrupt, and bulk transfers. The module includes an integrated LDO,  
PHY, and PLL. The PLL is highly-flexible and can support a wide range of input clock frequencies. USB RAM,  
when not used for USB communication, can be used by the system.  
Embedded Emulation Module (EEM)  
The Embedded Emulation Module (EEM) supports real-time in-system debugging. The L version of the EEM  
implemented on all devices has the following features:  
•
•
•
•
•
•
•
Eight hardware triggers/breakpoints on memory access  
Two hardware trigger/breakpoint on CPU register write access  
Up to ten hardware triggers can be combined to form complex triggers/breakpoints  
Two cycle counters  
Sequencer  
State storage  
Clock control on module level  
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Peripheral File Map  
Table 17. Peripherals  
OFFSET ADDRESS  
RANGE  
MODULE NAME  
BASE ADDRESS  
Special Functions (refer to Table 18)  
PMM (refer to Table 19)  
0100h  
0120h  
0140h  
0150h  
0158h  
015Ch  
0160h  
0180h  
01B0h  
01C0h  
01E0h  
0200h  
0220h  
0240h  
0260h  
0320h  
0340h  
0380h  
03C0h  
0400h  
04A0h  
04C0h  
0500h  
0510h  
0520h  
0530h  
05C0h  
05E0h  
0600h  
0620h  
0700h  
08C0h  
0900h  
0920h  
000h - 01Fh  
000h - 010h  
000h - 00Fh  
000h - 007h  
000h - 001h  
000h - 001h  
000h - 01Fh  
000h - 01Fh  
000h - 001h  
000h - 002h  
000h - 007h  
000h - 01Fh  
000h - 00Bh  
000h - 00Bh  
000h - 00Bh  
000h - 01Fh  
000h - 02Eh  
000h - 02Eh  
000h - 02Eh  
000h - 02Eh  
000h - 01Bh  
000h - 02Fh  
000h - 00Fh  
000h - 00Ah  
000h - 00Ah  
000h - 00Ah  
000h - 01Fh  
000h - 01Fh  
000h - 01Fh  
000h - 01Fh  
000h - 03Eh  
000h - 00Fh  
000h - 014h  
000h - 01Fh  
Flash Control (refer to Table 20)  
CRC16 (refer to Table 21)  
RAM Control (refer to Table 22)  
Watchdog (refer to Table 23)  
UCS (refer to Table 24)  
SYS (refer to Table 25)  
Shared Reference (refer to Table 26)  
Port Mapping Control (refer to Table 27)  
Port Mapping Port P4 (refer to Table 27)  
Port P1/P2 (refer to Table 28)  
Port P3/P4 (refer to Table 29)  
Port P5/P6 (refer to Table 30)  
Port P7/P8 (refer to Table 31)  
Port PJ (refer to Table 32)  
TA0 (refer to Table 33)  
TA1 (refer to Table 34)  
TB0 (refer to Table 35)  
TA2 (refer to Table 36)  
Real Timer Clock (RTC_A) (refer to Table 37)  
32-bit Hardware Multiplier (refer to Table 38)  
DMA General Control (refer to Table 39)  
DMA Channel 0 (refer to Table 39)  
DMA Channel 1 (refer to Table 39)  
DMA Channel 2 (refer to Table 39)  
USCI_A0 (refer to Table 40)  
USCI_B0 (refer to Table 41)  
USCI_A1 (refer to Table 42)  
USCI_B1 (refer to Table 43)  
ADC12_A (refer to Table 44)  
Comparator_B (refer to Table 45)  
USB configuration (refer to Table 46)  
USB control (refer to Table 47)  
34  
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Table 18. Special Function Registers (Base Address: 0100h)  
REGISTER DESCRIPTION  
REGISTER  
SFRIE1  
OFFSET  
SFR interrupt enable  
SFR interrupt flag  
00h  
02h  
04h  
SFRIFG1  
SFR reset pin control  
SFRRPCR  
Table 19. PMM Registers (Base Address: 0120h)  
REGISTER DESCRIPTION  
REGISTER  
PMMCTL0  
OFFSET  
PMM Control 0  
00h  
02h  
04h  
06h  
0Ch  
0Eh  
10h  
PMM control 1  
PMMCTL1  
SVSMHCTL  
SVSMLCTL  
PMMIFG  
SVS high side control  
SVS low side control  
PMM interrupt flags  
PMM interrupt enable  
PMM power mode 5 control  
PMMIE  
PM5CTL0  
Table 20. Flash Control Registers (Base Address: 0140h)  
REGISTER DESCRIPTION  
REGISTER  
OFFSET  
Flash control 1  
Flash control 3  
Flash control 4  
FCTL1  
FCTL3  
FCTL4  
00h  
04h  
06h  
Table 21. CRC16 Registers (Base Address: 0150h)  
REGISTER DESCRIPTION  
REGISTER  
CRC16DI  
OFFSET  
CRC data input  
00h  
02h  
04h  
06h  
CRC data input reverse byte  
CRC initialization and result  
CRC result reverse byte  
CRCDIRB  
CRCINIRES  
CRCRESR  
Table 22. RAM Control Registers (Base Address: 0158h)  
REGISTER DESCRIPTION  
REGISTER  
RCCTL0  
OFFSET  
OFFSET  
OFFSET  
RAM control 0  
00h  
00h  
Table 23. Watchdog Registers (Base Address: 015Ch)  
REGISTER DESCRIPTION  
REGISTER  
WDTCTL  
Watchdog timer control  
Table 24. UCS Registers (Base Address: 0160h)  
REGISTER DESCRIPTION  
REGISTER  
UCSCTL0  
UCS control 0  
UCS control 1  
UCS control 2  
UCS control 3  
UCS control 4  
UCS control 5  
UCS control 6  
UCS control 7  
UCS control 8  
00h  
02h  
04h  
06h  
08h  
0Ah  
0Ch  
0Eh  
10h  
UCSCTL1  
UCSCTL2  
UCSCTL3  
UCSCTL4  
UCSCTL5  
UCSCTL6  
UCSCTL7  
UCSCTL8  
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Table 25. SYS Registers (Base Address: 0180h)  
REGISTER DESCRIPTION  
REGISTER  
SYSCTL  
OFFSET  
System control  
00h  
02h  
06h  
08h  
0Ah  
0Ch  
0Eh  
18h  
1Ah  
1Ch  
1Eh  
Bootstrap loader configuration area  
JTAG mailbox control  
SYSBSLC  
SYSJMBC  
SYSJMBI0  
SYSJMBI1  
SYSJMBO0  
SYSJMBO1  
SYSBERRIV  
SYSUNIV  
JTAG mailbox input 0  
JTAG mailbox input 1  
JTAG mailbox output 0  
JTAG mailbox output 1  
Bus Error vector generator  
User NMI vector generator  
System NMI vector generator  
Reset vector generator  
SYSSNIV  
SYSRSTIV  
Table 26. Shared Reference Registers (Base Address: 01B0h)  
REGISTER DESCRIPTION  
REGISTER  
REFCTL  
OFFSET  
OFFSET  
Shared reference control  
00h  
Table 27. Port Mapping Registers  
(Base Address of Port Mapping Control: 01C0h, Port P4: 01E0h)  
REGISTER DESCRIPTION  
REGISTER  
PMAPKEYID  
Port mapping key/ID register  
Port mapping control register  
Port P4.0 mapping register  
Port P4.1 mapping register  
Port P4.2 mapping register  
Port P4.3 mapping register  
Port P4.4 mapping register  
Port P4.5 mapping register  
Port P4.6 mapping register  
Port P4.7 mapping register  
00h  
02h  
00h  
01h  
02h  
03h  
04h  
05h  
06h  
07h  
PMAPCTL  
P4MAP0  
P4MAP1  
P4MAP2  
P4MAP3  
P4MAP4  
P4MAP5  
P4MAP6  
P4MAP7  
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Table 28. Port P1/P2 Registers (Base Address: 0200h)  
REGISTER DESCRIPTION  
REGISTER  
OFFSET  
Port P1 input  
P1IN  
00h  
02h  
04h  
06h  
08h  
0Ah  
0Eh  
18h  
1Ah  
1Ch  
01h  
03h  
05h  
07h  
09h  
0Bh  
1Eh  
19h  
1Bh  
1Dh  
Port P1 output  
Port P1 direction  
P1OUT  
P1DIR  
P1REN  
P1DS  
P1SEL  
P1IV  
Port P1 pullup/pulldown enable  
Port P1 drive strength  
Port P1 selection  
Port P1 interrupt vector word  
Port P1 interrupt edge select  
Port P1 interrupt enable  
Port P1 interrupt flag  
P1IES  
P1IE  
P1IFG  
P2IN  
Port P2 input  
Port P2 output  
P2OUT  
P2DIR  
P2REN  
P2DS  
P2SEL  
P2IV  
Port P2 direction  
Port P2 pullup/pulldown enable  
Port P2 drive strength  
Port P2 selection  
Port P2 interrupt vector word  
Port P2 interrupt edge select  
Port P2 interrupt enable  
Port P2 interrupt flag  
P2IES  
P2IE  
P2IFG  
Table 29. Port P3/P4 Registers (Base Address: 0220h)  
REGISTER DESCRIPTION  
REGISTER  
OFFSET  
Port P3 input  
P3IN  
00h  
02h  
04h  
06h  
08h  
0Ah  
01h  
03h  
05h  
07h  
09h  
0Bh  
Port P3 output  
P3OUT  
P3DIR  
P3REN  
P3DS  
Port P3 direction  
Port P3 pullup/pulldown enable  
Port P3 drive strength  
Port P3 selection  
P3SEL  
P4IN  
Port P4 input  
Port P4 output  
P4OUT  
P4DIR  
P4REN  
P4DS  
Port P4 direction  
Port P4 pullup/pulldown enable  
Port P4 drive strength  
Port P4 selection  
P4SEL  
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Table 30. Port P5/P6 Registers (Base Address: 0240h)  
REGISTER DESCRIPTION  
REGISTER  
OFFSET  
Port P5 input  
P5IN  
00h  
02h  
04h  
06h  
08h  
0Ah  
01h  
03h  
05h  
07h  
09h  
0Bh  
Port P5 output  
P5OUT  
P5DIR  
P5REN  
P5DS  
Port P5 direction  
Port P5 pullup/pulldown enable  
Port P5 drive strength  
Port P5 selection  
P5SEL  
P6IN  
Port P6 input  
Port P6 output  
P6OUT  
P6DIR  
P6REN  
P6DS  
Port P6 direction  
Port P6 pullup/pulldown enable  
Port P6 drive strength  
Port P6 selection  
P6SEL  
Table 31. Port P7/P8 Registers (Base Address: 0260h)  
REGISTER DESCRIPTION  
REGISTER  
OFFSET  
Port P7 input  
P7IN  
00h  
02h  
04h  
06h  
08h  
0Ah  
01h  
03h  
05h  
07h  
09h  
0Bh  
Port P7 output  
P7OUT  
P7DIR  
P7REN  
P7DS  
Port P7 direction  
Port P7 pullup/pulldown enable  
Port P7 drive strength  
Port P7 selection  
P7SEL  
P8IN  
Port P8 input  
Port P8 output  
P8OUT  
P8DIR  
P8REN  
P8DS  
Port P8 direction  
Port P8 pullup/pulldown enable  
Port P8 drive strength  
Port P8 selection  
P8SEL  
Table 32. Port J Registers (Base Address: 0320h)  
REGISTER DESCRIPTION  
REGISTER  
OFFSET  
Port PJ input  
PJIN  
00h  
02h  
04h  
06h  
08h  
Port PJ output  
PJOUT  
PJDIR  
PJREN  
PJDS  
Port PJ direction  
Port PJ pullup/pulldown enable  
Port PJ drive strength  
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Table 33. TA0 Registers (Base Address: 0340h)  
REGISTER DESCRIPTION  
REGISTER  
OFFSET  
TA0 control  
TA0CTL  
00h  
02h  
04h  
06h  
08h  
0Ah  
10h  
12h  
14h  
16h  
18h  
1Ah  
20h  
2Eh  
Capture/compare control 0  
Capture/compare control 1  
Capture/compare control 2  
Capture/compare control 3  
Capture/compare control 4  
TA0 counter register  
TA0CCTL0  
TA0CCTL1  
TA0CCTL2  
TA0CCTL3  
TA0CCTL4  
TA0R  
Capture/compare register 0  
Capture/compare register 1  
Capture/compare register 2  
Capture/compare register 3  
Capture/compare register 4  
TA0 expansion register 0  
TA0 interrupt vector  
TA0CCR0  
TA0CCR1  
TA0CCR2  
TA0CCR3  
TA0CCR4  
TA0EX0  
TA0IV  
Table 34. TA1 Registers (Base Address: 0380h)  
REGISTER DESCRIPTION  
REGISTER  
TA1CTL  
OFFSET  
TA1 control  
00h  
02h  
04h  
06h  
10h  
12h  
14h  
16h  
20h  
2Eh  
Capture/compare control 0  
Capture/compare control 1  
Capture/compare control 2  
TA1 counter register  
TA1CCTL0  
TA1CCTL1  
TA1CCTL2  
TA1R  
Capture/compare register 0  
Capture/compare register 1  
Capture/compare register 2  
TA1 expansion register 0  
TA1 interrupt vector  
TA1CCR0  
TA1CCR1  
TA1CCR2  
TA1EX0  
TA1IV  
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Table 35. TB0 Registers (Base Address: 03C0h)  
REGISTER DESCRIPTION  
REGISTER  
TB0CTL  
OFFSET  
TB0 control  
00h  
02h  
04h  
06h  
08h  
0Ah  
0Ch  
0Eh  
10h  
12h  
14h  
16h  
18h  
1Ah  
1Ch  
1Eh  
20h  
2Eh  
Capture/compare control 0  
Capture/compare control 1  
Capture/compare control 2  
Capture/compare control 3  
Capture/compare control 4  
Capture/compare control 5  
Capture/compare control 6  
TB0 register  
TB0CCTL0  
TB0CCTL1  
TB0CCTL2  
TB0CCTL3  
TB0CCTL4  
TB0CCTL5  
TB0CCTL6  
TB0R  
Capture/compare register 0  
Capture/compare register 1  
Capture/compare register 2  
Capture/compare register 3  
Capture/compare register 4  
Capture/compare register 5  
Capture/compare register 6  
TB0 expansion register 0  
TB0 interrupt vector  
TB0CCR0  
TB0CCR1  
TB0CCR2  
TB0CCR3  
TB0CCR4  
TB0CCR5  
TB0CCR6  
TB0EX0  
TB0IV  
Table 36. TA2 Registers (Base Address: 0400h)  
REGISTER DESCRIPTION  
REGISTER  
TA2CTL  
OFFSET  
TA2 control  
00h  
02h  
04h  
06h  
10h  
12h  
14h  
16h  
20h  
2Eh  
Capture/compare control 0  
Capture/compare control 1  
Capture/compare control 2  
TA2 counter register  
TA2CCTL0  
TA2CCTL1  
TA2CCTL2  
TA2R  
Capture/compare register 0  
Capture/compare register 1  
Capture/compare register 2  
TA2 expansion register 0  
TA2 interrupt vector  
TA2CCR0  
TA2CCR1  
TA2CCR2  
TA2EX0  
TA2IV  
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Table 37. Real Time Clock Registers (Base Address: 04A0h)  
REGISTER DESCRIPTION  
REGISTER  
RTCCTL0  
OFFSET  
RTC control 0  
00h  
01h  
02h  
03h  
08h  
0Ah  
0Ch  
0Dh  
0Eh  
10h  
11h  
12h  
13h  
14h  
15h  
16h  
17h  
18h  
19h  
1Ah  
1Bh  
RTC control 1  
RTCCTL1  
RTC control 2  
RTCCTL2  
RTC control 3  
RTCCTL3  
RTC prescaler 0 control  
RTC prescaler 1 control  
RTC prescaler 0  
RTC prescaler 1  
RTC interrupt vector word  
RTCPS0CTL  
RTCPS1CTL  
RTCPS0  
RTCPS1  
RTCIV  
RTC seconds/counter register 1  
RTC minutes/counter register 2  
RTC hours/counter register 3  
RTC day of week/counter register 4  
RTC days  
RTCSEC/RTCNT1  
RTCMIN/RTCNT2  
RTCHOUR/RTCNT3  
RTCDOW/RTCNT4  
RTCDAY  
RTC month  
RTCMON  
RTC year low  
RTCYEARL  
RTCYEARH  
RTCAMIN  
RTC year high  
RTC alarm minutes  
RTC alarm hours  
RTCAHOUR  
RTCADOW  
RTCADAY  
RTC alarm day of week  
RTC alarm days  
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Table 38. 32-bit Hardware Multiplier Registers (Base Address: 04C0h)  
REGISTER DESCRIPTION  
REGISTER  
OFFSET  
16-bit operand 1 – multiply  
MPY  
00h  
02h  
04h  
06h  
08h  
0Ah  
0Ch  
0Eh  
10h  
12h  
14h  
16h  
18h  
1Ah  
1Ch  
1Eh  
20h  
22h  
24h  
26h  
28h  
2Ah  
2Ch  
16-bit operand 1 – signed multiply  
16-bit operand 1 – multiply accumulate  
16-bit operand 1 – signed multiply accumulate  
16-bit operand 2  
MPYS  
MAC  
MACS  
OP2  
16 × 16 result low word  
RESLO  
RESHI  
16 × 16 result high word  
16 × 16 sum extension register  
SUMEXT  
MPY32L  
MPY32H  
MPYS32L  
MPYS32H  
MAC32L  
MAC32H  
MACS32L  
MACS32H  
OP2L  
32-bit operand 1 – multiply low word  
32-bit operand 1 – multiply high word  
32-bit operand 1 – signed multiply low word  
32-bit operand 1 – signed multiply high word  
32-bit operand 1 – multiply accumulate low word  
32-bit operand 1 – multiply accumulate high word  
32-bit operand 1 – signed multiply accumulate low word  
32-bit operand 1 – signed multiply accumulate high word  
32-bit operand 2 – low word  
32-bit operand 2 – high word  
OP2H  
32 × 32 result 0 – least significant word  
32 × 32 result 1  
RES0  
RES1  
32 × 32 result 2  
RES2  
32 × 32 result 3 – most significant word  
MPY32 control register 0  
RES3  
MPY32CTL0  
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Table 39. DMA Registers (Base Address DMA General Control: 0500h,  
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)  
REGISTER DESCRIPTION  
REGISTER  
DMA0CTL  
OFFSET  
DMA channel 0 control  
00h  
02h  
04h  
06h  
08h  
0Ah  
00h  
02h  
04h  
06h  
08h  
0Ah  
00h  
02h  
04h  
06h  
08h  
0Ah  
00h  
02h  
04h  
06h  
08h  
0Eh  
DMA channel 0 source address low  
DMA channel 0 source address high  
DMA channel 0 destination address low  
DMA channel 0 destination address high  
DMA channel 0 transfer size  
DMA0SAL  
DMA0SAH  
DMA0DAL  
DMA0DAH  
DMA0SZ  
DMA channel 1 control  
DMA1CTL  
DMA1SAL  
DMA1SAH  
DMA1DAL  
DMA1DAH  
DMA1SZ  
DMA channel 1 source address low  
DMA channel 1 source address high  
DMA channel 1 destination address low  
DMA channel 1 destination address high  
DMA channel 1 transfer size  
DMA channel 2 control  
DMA2CTL  
DMA2SAL  
DMA2SAH  
DMA2DAL  
DMA2DAH  
DMA2SZ  
DMA channel 2 source address low  
DMA channel 2 source address high  
DMA channel 2 destination address low  
DMA channel 2 destination address high  
DMA channel 2 transfer size  
DMA module control 0  
DMACTL0  
DMACTL1  
DMACTL2  
DMACTL3  
DMACTL4  
DMAIV  
DMA module control 1  
DMA module control 2  
DMA module control 3  
DMA module control 4  
DMA interrupt vector  
Table 40. USCI_A0 Registers (Base Address: 05C0h)  
REGISTER DESCRIPTION  
REGISTER  
UCA0CTL1  
OFFSET  
USCI control 1  
00h  
01h  
06h  
07h  
08h  
0Ah  
0Ch  
0Eh  
10h  
12h  
13h  
1Ch  
1Dh  
1Eh  
USCI control 0  
UCA0CTL0  
UCA0BR0  
USCI baud rate 0  
USCI baud rate 1  
UCA0BR1  
USCI modulation control  
USCI status  
UCA0MCTL  
UCA0STAT  
UCA0RXBUF  
UCA0TXBUF  
UCA0ABCTL  
UCA0IRTCTL  
UCA0IRRCTL  
UCA0IE  
USCI receive buffer  
USCI transmit buffer  
USCI LIN control  
USCI IrDA transmit control  
USCI IrDA receive control  
USCI interrupt enable  
USCI interrupt flags  
USCI interrupt vector word  
UCA0IFG  
UCA0IV  
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Table 41. USCI_B0 Registers (Base Address: 05E0h)  
REGISTER DESCRIPTION  
REGISTER  
UCB0CTL1  
OFFSET  
USCI synchronous control 1  
USCI synchronous control 0  
USCI synchronous bit rate 0  
USCI synchronous bit rate 1  
USCI synchronous status  
00h  
01h  
06h  
07h  
0Ah  
0Ch  
0Eh  
10h  
12h  
1Ch  
1Dh  
1Eh  
UCB0CTL0  
UCB0BR0  
UCB0BR1  
UCB0STAT  
UCB0RXBUF  
UCB0TXBUF  
UCB0I2COA  
UCB0I2CSA  
UCB0IE  
USCI synchronous receive buffer  
USCI synchronous transmit buffer  
USCI I2C own address  
USCI I2C slave address  
USCI interrupt enable  
USCI interrupt flags  
UCB0IFG  
USCI interrupt vector word  
UCB0IV  
Table 42. USCI_A1 Registers (Base Address: 0600h)  
REGISTER DESCRIPTION  
REGISTER  
UCA1CTL1  
OFFSET  
USCI control 1  
00h  
01h  
06h  
07h  
08h  
0Ah  
0Ch  
0Eh  
10h  
12h  
13h  
1Ch  
1Dh  
1Eh  
USCI control 0  
UCA1CTL0  
UCA1BR0  
USCI baud rate 0  
USCI baud rate 1  
UCA1BR1  
USCI modulation control  
USCI status  
UCA1MCTL  
UCA1STAT  
UCA1RXBUF  
UCA1TXBUF  
UCA1ABCTL  
UCA1IRTCTL  
UCA1IRRCTL  
UCA1IE  
USCI receive buffer  
USCI transmit buffer  
USCI LIN control  
USCI IrDA transmit control  
USCI IrDA receive control  
USCI interrupt enable  
USCI interrupt flags  
USCI interrupt vector word  
UCA1IFG  
UCA1IV  
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Table 43. USCI_B1 Registers (Base Address: 0620h)  
REGISTER DESCRIPTION  
REGISTER  
OFFSET  
USCI synchronous control 1  
USCI synchronous control 0  
USCI synchronous bit rate 0  
USCI synchronous bit rate 1  
USCI synchronous status  
USCI synchronous receive buffer  
USCI synchronous transmit buffer  
USCI I2C own address  
UCB1CTL1  
UCB1CTL0  
UCB1BR0  
UCB1BR1  
UCB1STAT  
UCB1RXBUF  
UCB1TXBUF  
UCB1I2COA  
UCB1I2CSA  
UCB1IE  
00h  
01h  
06h  
07h  
0Ah  
0Ch  
0Eh  
10h  
12h  
1Ch  
1Dh  
1Eh  
USCI I2C slave address  
USCI interrupt enable  
USCI interrupt flags  
UCB1IFG  
USCI interrupt vector word  
UCB1IV  
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Table 44. ADC12_A Registers (Base Address: 0700h)  
REGISTER DESCRIPTION  
REGISTER  
ADC12CTL0  
OFFSET  
Control register 0  
00h  
02h  
04h  
0Ah  
0Ch  
0Eh  
10h  
11h  
12h  
13h  
14h  
15h  
16h  
17h  
18h  
19h  
1Ah  
1Bh  
1Ch  
1Dh  
1Eh  
1Fh  
20h  
22h  
24h  
26h  
28h  
2Ah  
2Ch  
2Eh  
30h  
32h  
34h  
36h  
38h  
3Ah  
3Ch  
3Eh  
Control register 1  
ADC12CTL1  
Control register 2  
ADC12CTL2  
Interrupt-flag register  
ADC12IFG  
Interrupt-enable register  
Interrupt-vector-word register  
ADC memory-control register 0  
ADC memory-control register 1  
ADC memory-control register 2  
ADC memory-control register 3  
ADC memory-control register 4  
ADC memory-control register 5  
ADC memory-control register 6  
ADC memory-control register 7  
ADC memory-control register 8  
ADC memory-control register 9  
ADC memory-control register 10  
ADC memory-control register 11  
ADC memory-control register 12  
ADC memory-control register 13  
ADC memory-control register 14  
ADC memory-control register 15  
Conversion memory 0  
ADC12IE  
ADC12IV  
ADC12MCTL0  
ADC12MCTL1  
ADC12MCTL2  
ADC12MCTL3  
ADC12MCTL4  
ADC12MCTL5  
ADC12MCTL6  
ADC12MCTL7  
ADC12MCTL8  
ADC12MCTL9  
ADC12MCTL10  
ADC12MCTL11  
ADC12MCTL12  
ADC12MCTL13  
ADC12MCTL14  
ADC12MCTL15  
ADC12MEM0  
ADC12MEM1  
ADC12MEM2  
ADC12MEM3  
ADC12MEM4  
ADC12MEM5  
ADC12MEM6  
ADC12MEM7  
ADC12MEM8  
ADC12MEM9  
ADC12MEM10  
ADC12MEM11  
ADC12MEM12  
ADC12MEM13  
ADC12MEM14  
ADC12MEM15  
Conversion memory 1  
Conversion memory 2  
Conversion memory 3  
Conversion memory 4  
Conversion memory 5  
Conversion memory 6  
Conversion memory 7  
Conversion memory 8  
Conversion memory 9  
Conversion memory 10  
Conversion memory 11  
Conversion memory 12  
Conversion memory 13  
Conversion memory 14  
Conversion memory 15  
46  
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Table 45. Comparator_B Registers (Base Address: 08C0h)  
REGISTER DESCRIPTION  
REGISTER  
CBCTL0  
OFFSET  
Comp_B control register 0  
Comp_B control register 1  
Comp_B control register 2  
Comp_B control register 3  
Comp_B interrupt register  
00h  
02h  
04h  
06h  
0Ch  
0Eh  
CBCTL1  
CBCTL2  
CBCTL3  
CBINT  
Comp_B interrupt vector word  
CBIV  
Table 46. USB Configuration Registers (Base Address: 0900h)  
REGISTER DESCRIPTION  
REGISTER  
USBKEYID  
OFFSET  
USB key/ID  
00h  
02h  
04h  
08h  
10h  
12h  
14h  
USB module configuration  
USB PHY control  
USB power control  
USB PLL control  
USB PLL divider  
USB PLL interrupts  
USBCNF  
USBPHYCTL  
USBPWRCTL  
USBPLLCTL  
USBPLLDIV  
USBPLLIR  
Table 47. USB Control Registers (Base Address: 0920h)  
REGISTER DESCRIPTION  
REGISTER  
IEPCNF_0  
OFFSET  
Input endpoint#0 configuration  
Input endpoint #0 byte count  
Output endpoint#0 configuration  
Output endpoint #0 byte count  
Input endpoint interrupt enables  
Output endpoint interrupt enables  
Input endpoint interrupt flags  
Output endpoint interrupt flags  
USB interrupt vector  
00h  
01h  
02h  
03h  
0Eh  
0Fh  
10h  
11h  
12h  
16h  
18h  
1Ah  
1Ch  
1Dh  
1Eh  
1Fh  
IEPCNT_0  
OEPCNF_0  
OEPCNT_0  
IEPIE  
OEPIE  
IEPIFG  
OEPIFG  
USBIV  
USB maintenance  
MAINT  
Time stamp  
TSREG  
USBFN  
USBCTL  
USBIE  
USB frame number  
USB control  
USB interrupt enables  
USB interrupt flags  
USBIFG  
FUNADR  
Function address  
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Absolute Maximum Ratings(1)  
over operating free-air temperature range (unless otherwise noted)  
Voltage applied at VCC to VSS  
–0.3 V to 4.1 V  
Voltage applied to any pin (excluding VCORE, VBUS, V18)(2)  
Diode current at any device pin  
–0.3 V to VCC + 0.3 V  
±2 mA  
(3)  
Storage temperature range, Tstg  
–55°C to 105°C  
95°C  
Maximum junction temperature, TJ  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) All voltages referenced to VSS. VCORE is for internal device usage only. No external DC loading or voltage should be applied.  
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow  
temperatures not higher than classified on the device label on the shipping boxes or reels.  
Thermal Packaging Characteristics  
PARAMETER  
VALUE  
70  
UNIT  
QFP (PN)  
Low-K board (JESD51-3)  
QFN (RGC)  
BGA (ZQE)  
QFP (PN)  
55  
84  
qJA  
Junction-to-ambient thermal resistance, still air  
°C/W  
45  
High-K board (JESD51-7)  
QFN (RGC)  
BGA (ZQE)  
QFP (PN)  
25  
46  
12  
qJC  
Junction-to-case thermal resistance  
Junction-to-board thermal resistance  
QFN (RGC)  
BGA (ZQE)  
QFP (PN)  
12  
°C/W  
°C/W  
30  
22  
qJB  
QFN (RGC)  
BGA (ZQE)  
6
20  
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Recommended Operating Conditions  
MIN NOM  
MAX UNIT  
PMMCOREVx = 0  
1.8  
2.0  
2.2  
2.4  
1.8  
2.0  
2.2  
2.4  
2.2  
2.4  
0
3.6  
3.6  
3.6  
3.6  
3.6  
3.6  
3.6  
3.6  
3.6  
3.6  
V
V
PMMCOREVx = 0, 1  
PMMCOREVx = 0, 1, 2  
PMMCOREVx = 0, 1, 2, 3  
PMMCOREVx = 0  
Supply voltage during program execution and flash  
VCC  
(1)  
programming(AVCC = DVCC1/2 = DVCC  
)
V
V
V
PMMCOREVx = 0, 1  
PMMCOREVx = 0, 1, 2  
PMMCOREVx = 0, 1, 2, 3  
PMMCOREVx = 2  
V
Supply voltage during USB operation, USB PLL disabled  
USB_EN = 1, UPLLEN = 0  
V
VCC, USB  
V
Supply voltage during USB operation, USB PLL enabled(2)  
USB_EN = 1, UPLLEN = 1  
V
PMMCOREVx = 2, 3  
V
VSS  
TA  
Supply voltage (AVSS = DVSS1/2 = DVSS  
Operating free-air temperature  
Operating junction temperature  
Capacitor at VCORE  
)
V
I version  
I version  
–40  
–40  
470  
85  
85  
°C  
°C  
nF  
TJ  
CVCORE  
CDVCC  
CVCORE  
/
Capacitor ratio of DVCC to VCORE  
10  
PMMCOREVx = 0  
1.8 V ≤ VCC ≤ 3.6 V  
(default condition)  
0
8.0  
PMMCOREVx = 1  
2.0 V ≤ VCC ≤ 3.6 V  
Processor frequency (maximum MCLK frequency)(3)  
(see Figure 1)  
0
0
0
12.0  
20.0  
25.0  
fSYSTEM  
MHz  
PMMCOREVx = 2  
2.2 V ≤ VCC ≤ 3.6 V  
PMMCOREVx = 3  
2.4 V ≤ VCC ≤ 3.6 V  
fSYSTEM_USB  
USB_wait  
Minimum processor frequency for USB operation  
Wait state cycles during USB operation  
1.5  
MHz  
16  
cycles  
(1) It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be  
tolerated during power up and operation.  
(2) USB operation with USB PLL enabled requires PMMCOREVx ≥ 2 for proper operation.  
(3) Modules may have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.  
25  
3
20  
2, 3  
2
12  
8
1, 2  
1, 2, 3  
1
0
0, 1  
0, 1, 2  
0, 1, 2, 3  
0
1.8  
2.0  
2.2  
2.4  
3.6  
Supply Voltage - V  
The numbers within the fields denote the supported PMMCOREVx settings.  
Figure 1. Maximum System Frequency  
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Electrical Characteristics  
Active Mode Supply Current Into VCC Excluding External Current  
(2) (3)  
over recommended operating free-air temperature (unless otherwise noted)(1)  
FREQUENCY (fDCO = fMCLK = fSMCLK  
)
EXECUTION  
MEMORY  
PARAMETER  
VCC  
PMMCOREVx  
1 MHz  
8 MHz 12 MHz 20 MHz  
25 MHz  
UNIT  
TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX  
0
1
2
3
0
1
2
3
0.36 0.47 2.32 2.60  
0.40  
0.44  
0.46  
2.65  
2.90  
3.10  
4.0  
4.3  
4.6  
4.4  
IAM, Flash  
Flash  
RAM  
3.0 V  
mA  
7.1  
7.6  
7.7  
4.2  
10.1 11.0  
0.20 0.24 1.20 1.30  
0.22  
0.24  
0.26  
1.35  
1.50  
1.60  
2.0  
2.2  
2.4  
2.2  
IAM, RAM  
3.0 V  
mA  
3.7  
3.9  
5.3  
6.2  
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.  
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load  
capacitance are chosen to closely match the required 12.5 pF.  
(3) Characterized with program executing typical data processing. USB disabled (VUSBEN = 0, SLDOEN = 0).  
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.  
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.  
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Low-Power Mode Supply Currents (Into VCC) Excluding External Current  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)  
(2)  
-40°C  
TYP MAX  
25°C  
TYP MAX  
77 85  
60°C  
TYP MAX  
80  
85°C  
TYP MAX  
97  
PARAMETER  
VCC  
PMMCOREVx  
UNIT  
µA  
2.2 V  
3.0 V  
2.2 V  
3.0 V  
0
3
0
3
0
1
2
0
1
2
3
0
1
2
3
0
1
2
3
73  
79  
85  
95  
ILPM0,1MHz Low-power mode 0(3)(4)  
83  
6.5  
92  
12  
13  
88  
10  
105  
17  
6.5  
7.0  
1.60  
1.65  
1.75  
1.8  
1.9  
2.0  
2.0  
1.1  
1.1  
1.2  
1.3  
0.9  
1.1  
1.2  
1.3  
0.15  
11  
ILPM2  
Low-power mode 2(5)(4)  
µA  
7.0  
11  
12  
18  
1.90  
2.00  
2.15  
2.1  
2.6  
2.7  
2.9  
2.8  
2.9  
3.0  
3.1  
1.9  
2.0  
2.1  
2.2  
1.8  
2.0  
2.1  
2.2  
0.26  
4.4  
4.6  
4.9  
4.6  
4.8  
5.0  
5.1  
3.8  
4.0  
4.1  
4.2  
4.0  
4.2  
4.3  
4.4  
0.5  
2.2 V  
Low-power mode 3,  
crystal mode(6)(4)  
ILPM3,XT1LF  
2.9  
7.0  
µA  
µA  
2.3  
3.0 V  
2.4  
2.5  
3.9  
2.7  
9.0  
6.5  
1.4  
1.4  
Low-power mode 3,  
VLO mode(7)(4)  
ILPM3,VLO  
3.0 V  
1.5  
1.6  
3.0  
1.5  
8.5  
6.0  
1.1  
1.2  
ILPM4  
Low-power mode 4(8)(4)  
Low-power mode 4.5(9)  
3.0 V  
3.0 V  
µA  
µA  
1.2  
1.3  
1.6  
8.0  
1.0  
ILPM4.5  
0.18  
0.35  
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.  
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load  
capacitance are chosen to closely match the required 12.5 pF.  
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).  
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz  
USB disabled (VUSBEN = 0, SLDOEN = 0).  
(4) Current for brownout, high side supervisor (SVSH) normal mode included. Low side supervisor and monitors disabled (SVSL, SVML).  
High side monitor disabled (SVMH). RAM retention enabled.  
(5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).  
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO setting = 1  
MHz operation, DCO bias generator enabled.  
USB disabled (VUSBEN = 0, SLDOEN = 0)  
(6) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).  
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz  
USB disabled (VUSBEN = 0, SLDOEN = 0)  
(7) Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.  
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz  
USB disabled (VUSBEN = 0, SLDOEN = 0)  
(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz  
USB disabled (VUSBEN = 0, SLDOEN = 0)  
(9) Internal regulator disabled. No data retention.  
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz  
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MAX UNIT  
Schmitt-Trigger Inputs – General Purpose I/O(1)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
1.8 V  
3 V  
MIN  
0.80  
1.50  
0.45  
0.75  
0.3  
TYP  
1.40  
V
VIT+  
VIT–  
Vhys  
Positive-going input threshold voltage  
2.10  
1.8 V  
3 V  
1.00  
V
Negative-going input threshold voltage  
1.65  
1.8 V  
3 V  
0.85  
V
Input voltage hysteresis (VIT+ – VIT–  
)
0.4  
1.0  
For pullup: VIN = VSS  
For pulldown: VIN = VCC  
RPull  
CI  
Pullup/pulldown resistor  
Input capacitance  
20  
35  
5
50  
kΩ  
VIN = VSS or VCC  
pF  
(1) Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).  
Inputs – Ports P1 and P2(1)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
MAX UNIT  
Port P1, P2: P1.x to P2.x, External trigger pulse width to  
set interrupt flag  
t(int)  
External interrupt timing(2)  
2.2 V/3 V  
20  
ns  
(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.  
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set by trigger signals shorter  
than t(int)  
.
Leakage Current – General Purpose I/O  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
MAX UNIT  
±50 nA  
(1) (2)  
Ilkg(Px.x)  
High-impedance leakage current  
1.8 V/3 V  
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.  
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is  
disabled.  
Outputs – General Purpose I/O (Full Drive Strength)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
I(OHmax) = –3 mA(1)  
VCC  
MIN  
VCC – 0.25  
VCC – 0.60  
VCC – 0.25  
VCC – 0.60  
MAX UNIT  
VCC  
1.8 V  
I(OHmax) = –10 mA(2)  
I(OHmax) = –5 mA(1)  
I(OHmax) = –15 mA(2)  
I(OLmax) = 3 mA(1)  
I(OLmax) = 10 mA(2)  
I(OLmax) = 5 mA(1)  
I(OLmax) = 15 mA(2)  
VCC  
VOH  
High-level output voltage  
V
VCC  
3 V  
1.8 V  
3 V  
VCC  
VSS VSS + 0.25  
VSS VSS + 0.60  
VSS VSS + 0.25  
VSS VSS + 0.60  
VOL  
Low-level output voltage  
V
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop  
specified.  
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage  
drop specified.  
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Outputs – General Purpose I/O (Reduced Drive Strength)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)  
PARAMETER  
TEST CONDITIONS  
I(OHmax) = –1 mA(2)  
VCC  
MIN  
VCC – 0.25  
VCC – 0.60  
VCC – 0.25  
VCC – 0.60  
MAX UNIT  
VCC  
1.8 V  
I(OHmax) = –3 mA(3)  
I(OHmax) = –2 mA(2)  
I(OHmax) = –6 mA(3)  
I(OLmax) = 1 mA(2)  
I(OLmax) = 3 mA(3)  
I(OLmax) = 2 mA(2)  
I(OLmax) = 6 mA(3)  
VCC  
VOH  
High-level output voltage  
V
VCC  
3.0 V  
1.8 V  
3.0 V  
VCC  
VSS VSS + 0.25  
VSS VSS + 0.60  
VSS VSS + 0.25  
VSS VSS + 0.60  
VOL  
Low-level output voltage  
V
(1) Selecting reduced drive strength may reduce EMI.  
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop  
specified.  
(3) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage  
drop specified.  
Output Frequency – General Purpose I/O  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
MAX UNIT  
(1)(2)  
V
CC  
= 1.8 V  
16  
PMMCOREVx = 0  
Port output frequency  
(with load)  
fPx.y  
MHz  
25  
VCC = 3 V  
PMMCOREVx = 3  
VCC = 1.8 V  
PMMCOREVx = 0  
ACLK  
16  
SMCLK  
MCLK  
fPort_CLK  
Clock output frequency  
MHz  
25  
VCC = 3 V  
PMMCOREVx = 3  
CL = 20 pF(2)  
(1) A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full  
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS  
.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.  
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Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
TYPICAL LOW-LEVEL OUTPUT CURRENT  
TYPICAL LOW-LEVEL OUTPUT CURRENT  
vs  
vs  
LOW-LEVEL OUTPUT VOLTAGE  
LOW-LEVEL OUTPUT VOLTAGE  
8.0  
7.0  
6.0  
5.0  
4.0  
3.0  
2.0  
1.0  
0.0  
25.0  
20.0  
15.0  
10.0  
5.0  
TA = 25°C  
VCC = 3.0 V  
VCC = 1.8 V  
Px.y  
Px.y  
TA = 25°C  
TA = 85°C  
TA = 85°C  
0.0  
0.0  
0.5  
1.0  
1.5  
2.0  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
VOL – Low-Level Output Voltage – V  
VOL – Low-Level Output Voltage – V  
Figure 2.  
Figure 3.  
TYPICAL HIGH-LEVEL OUTPUT CURRENT  
TYPICAL HIGH-LEVEL OUTPUT CURRENT  
vs  
vs  
HIGH-LEVEL OUTPUT VOLTAGE  
HIGH-LEVEL OUTPUT VOLTAGE  
0.0  
-1.0  
-2.0  
-3.0  
-4.0  
-5.0  
-6.0  
-7.0  
-8.0  
0.0  
-5.0  
VCC = 1.8 V  
Px.y  
VCC = 3.0 V  
Px.y  
-10.0  
-15.0  
-20.0  
-25.0  
TA = 85°C  
TA = 25°C  
TA = 85°C  
TA = 25°C  
0.0  
0.5  
1.0  
1.5  
2.0  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
VOH – High-Level Output Voltage – V  
VOH – High-Level Output Voltage – V  
Figure 4.  
Figure 5.  
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Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
TYPICAL LOW-LEVEL OUTPUT CURRENT  
TYPICAL LOW-LEVEL OUTPUT CURRENT  
vs  
vs  
LOW-LEVEL OUTPUT VOLTAGE  
LOW-LEVEL OUTPUT VOLTAGE  
60.0  
55.0  
50.0  
45.0  
40.0  
35.0  
30.0  
25.0  
20.0  
15.0  
10.0  
5.0  
TA = 25°C  
24  
20  
16  
12  
8
VCC = 1.8 V  
VCC = 3.0 V  
Px.y  
Px.y  
TA = 25°C  
TA = 85°C  
TA = 85°C  
4
0
0.0  
0.0  
0.5  
1.0  
1.5  
2.0  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
VOL – Low-Level Output Voltage – V  
VOL – Low-Level Output Voltage – V  
Figure 6.  
Figure 7.  
TYPICAL HIGH-LEVEL OUTPUT CURRENT  
TYPICAL HIGH-LEVEL OUTPUT CURRENT  
vs  
vs  
HIGH-LEVEL OUTPUT VOLTAGE  
HIGH-LEVEL OUTPUT VOLTAGE  
0
0.0  
-5.0  
VCC = 1.8 V  
Px.y  
VCC = 3.0 V  
Px.y  
-10.0  
-15.0  
-20.0  
-25.0  
-30.0  
-35.0  
-40.0  
-45.0  
-50.0  
-55.0  
-60.0  
-4  
-8  
-12  
-16  
-20  
TA = 85°C  
TA = 25°C  
TA = 85°C  
TA = 25°C  
0.0  
0.5  
1.0  
1.5  
2.0  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
VOH – High-Level Output Voltage – V  
VOH – High-Level Output Voltage – V  
Figure 8.  
Figure 9.  
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Crystal Oscillator, XT1, Low-Frequency Mode(1)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
TYP  
MAX UNIT  
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,  
XT1DRIVEx = 1, TA = 25°C  
0.075  
Differential XT1 oscillator  
crystal current consumption  
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,  
ΔIDVCC.LF  
3.0 V  
0.170  
0.290  
32768  
µA  
from lowest drive setting, LF XT1DRIVEx = 2, TA = 25°C  
mode  
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,  
XT1DRIVEx = 3, TA = 25°C  
XT1 oscillator crystal  
frequency, LF mode  
fXT1,LF0  
XTS = 0, XT1BYPASS = 0  
Hz  
XT1 oscillator logic-level  
fXT1,LF,SW  
square-wave input frequency, XTS = 0, XT1BYPASS = 1(2) (3)  
LF mode  
10 32.768  
50 kHz  
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0,  
fXT1,LF = 32768 Hz, CL,eff = 6 pF  
210  
300  
Oscillation allowance for  
LF crystals(4)  
OALF  
kΩ  
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1,  
fXT1,LF = 32768 Hz, CL,eff = 12 pF  
XTS = 0, XCAPx = 0(6)  
XTS = 0, XCAPx = 1  
XTS = 0, XCAPx = 2  
XTS = 0, XCAPx = 3  
2
5.5  
Integrated effective load  
capacitance, LF mode(5)  
CL,eff  
pF  
8.5  
12.0  
XTS = 0, Measured at ACLK,  
fXT1,LF = 32768 Hz  
Duty cycle LF mode  
30  
70  
%
Oscillator fault frequency,  
fFault,LF  
XTS = 0(8)  
10  
10000  
Hz  
LF mode(7)  
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,  
XT1DRIVEx = 0, TA = 25°C, CL,eff = 6 pF  
1000  
500  
tSTART,LF  
Startup time, LF mode  
3.0 V  
ms  
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,  
XT1DRIVEx = 3, TA = 25°C, CL,eff = 12 pF  
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.  
(a) Keep the trace between the device and the crystal as short as possible.  
(b) Design a good ground plane around the oscillator pins.  
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.  
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.  
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.  
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.  
(2) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in  
the Schmitt-trigger Inputs section of this datasheet.  
(3) Maximum frequency of operation of the entire device cannot be exceeded.  
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the  
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following  
guidelines, but should be evaluated based on the actual crystal selected for the application:  
(a) For XT1DRIVEx = 0, CL,ef f ≤ 6 pF.  
(b) For XT1DRIVEx = 1, 6 pF ≤ CL,ef f ≤ 9 pF.  
(c) For XT1DRIVEx = 2, 6 pF ≤ CL,ef f ≤ 10 pF.  
(d) For XT1DRIVEx = 3, CL,ef f ≥ 6 pF.  
(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).  
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a  
correct setup, the effective load capacitance should always match the specification of the used crystal.  
(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.  
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.  
Frequencies in between might set the flag.  
(8) Measured with logic-level input frequency but also applies to operation with crystals.  
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Crystal Oscillator, XT2  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)  
(2)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
TYP  
MAX UNIT  
fOSC = 4 MHz, XT2OFF = 0, XT2BYPASS = 0,  
XT2DRIVEx = 0, TA = 25°C  
200  
fOSC = 12 MHz, XT2OFF = 0, XT2BYPASS = 0,  
XT2DRIVEx = 1, TA = 25°C  
260  
325  
450  
XT2 oscillator crystal  
current consumption  
IDVCC.XT2  
3.0 V  
µA  
fOSC = 20 MHz, XT2OFF = 0, XT2BYPASS = 0,  
XT2DRIVEx = 2, TA = 25°C  
fOSC = 32 MHz, XT2OFF = 0, XT2BYPASS = 0,  
XT2DRIVEx = 3, TA = 25°C  
XT2 oscillator crystal  
frequency, mode 0  
fXT2,HF0  
fXT2,HF1  
fXT2,HF2  
fXT2,HF3  
XT2DRIVEx = 0, XT2BYPASS = 0(3)  
XT2DRIVEx = 1, XT2BYPASS = 0(3)  
XT2DRIVEx = 2, XT2BYPASS = 0(3)  
XT2DRIVEx = 3, XT2BYPASS = 0(3)  
4
8
8
MHz  
XT2 oscillator crystal  
frequency, mode 1  
16 MHz  
24 MHz  
32 MHz  
XT2 oscillator crystal  
frequency, mode 2  
16  
24  
XT2 oscillator crystal  
frequency, mode 3  
XT2 oscillator logic-level  
fXT2,HF,SW square-wave input  
frequency, bypass mode  
XT2BYPASS = 1(4) (3)  
1.5  
32 MHz  
XT2DRIVEx = 0, XT2BYPASS = 0,  
fXT2,HF0 = 6 MHz, CL,eff = 15 pF  
450  
320  
200  
200  
0.5  
XT2DRIVEx = 1, XT2BYPASS = 0,  
fXT2,HF1 = 12 MHz, CL,eff = 15 pF  
Oscillation allowance for  
HF crystals(5)  
OAHF  
Ω
XT2DRIVEx = 2, XT2BYPASS = 0,  
fXT2,HF2 = 20 MHz, CL,eff = 15 pF  
XT2DRIVEx = 3, XT2BYPASS = 0,  
fXT2,HF3 = 32 MHz, CL,eff = 15 pF  
fOSC = 6 MHz, XT2BYPASS = 0, XT2DRIVEx = 0,  
TA = 25°C, CL,eff = 15 pF  
tSTART,HF  
Startup time  
3.0 V  
ms  
pF  
fOSC = 20 MHz, XT2BYPASS = 0, XT2DRIVEx = 2,  
TA = 25°C, CL,eff = 15 pF  
0.3  
Integrated effective load  
capacitance,  
CL,eff  
1
HF mode(6) (7)  
Duty cycle  
fFault,HF  
Measured at ACLK, fXT2,HF2 = 20 MHz  
XT2BYPASS = 1(9)  
40  
30  
50  
60  
%
Oscillator fault  
frequency(8)  
300 kHz  
(1) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.  
(2) To improve EMI on the XT2 oscillator the following guidelines should be observed.  
(a) Keep the traces between the device and the crystal as short as possible.  
(b) Design a good ground plane around the oscillator pins.  
(c) Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.  
(d) Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.  
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.  
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.  
(3) This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device  
operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.  
(4) When XT2BYPASS is set, the XT2 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined  
in the Schmitt-trigger Inputs section of this datasheet.  
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.  
(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).  
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a  
correct setup, the effective load capacitance should always match the specification of the used crystal.  
(7) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.  
(8) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.  
Frequencies in between might set the flag.  
(9) Measured with logic-level input frequency but also applies to operation with crystals.  
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Internal Very-Low-Power Low-Frequency Oscillator (VLO)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
VLO frequency  
VLO frequency temperature drift  
TEST CONDITIONS  
VCC  
MIN  
TYP  
9.4  
0.5  
4
MAX UNIT  
14 kHz  
%/°C  
fVLO  
Measured at ACLK  
1.8 V to 3.6 V  
1.8 V to 3.6 V  
1.8 V to 3.6 V  
1.8 V to 3.6 V  
6
dfVLO/dT  
Measured at ACLK(1)  
Measured at ACLK(2)  
Measured at ACLK  
dfVLO/dVCC VLO frequency supply voltage drift  
Duty cycle  
%/V  
40  
50  
60  
%
(1) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))  
(2) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)  
Internal Reference, Low-Frequency Oscillator (REFO)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
TYP  
3
MAX UNIT  
IREFO  
REFO oscillator current consumption TA = 25°C  
1.8 V to 3.6 V  
1.8 V to 3.6 V  
1.8 V to 3.6 V  
3 V  
µA  
Hz  
REFO frequency calibrated  
Measured at ACLK  
32768  
fREFO  
Full temperature range  
TA = 25°C  
Measured at ACLK(1)  
±3.5  
±1.5  
%
%
REFO absolute tolerance calibrated  
REFO frequency temperature drift  
REFO frequency supply voltage drift Measured at ACLK(2)  
dfREFO/dT  
dfREFO/dVCC  
Duty cycle  
tSTART  
1.8 V to 3.6 V  
1.8 V to 3.6 V  
1.8 V to 3.6 V  
1.8 V to 3.6 V  
0.01  
1.0  
50  
%/°C  
%/V  
%
Measured at ACLK  
40  
60  
REFO startup time  
40%/60% duty cycle  
25  
µs  
(1) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))  
(2) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)  
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DCO Frequency  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
DCORSELx = 0, DCOx = 0, MODx = 0  
DCORSELx = 0, DCOx = 31, MODx = 0  
DCORSELx = 1, DCOx = 0, MODx = 0  
DCORSELx = 1, DCOx = 31, MODx = 0  
DCORSELx = 2, DCOx = 0, MODx = 0  
DCORSELx = 2, DCOx = 31, MODx = 0  
DCORSELx = 3, DCOx = 0, MODx = 0  
DCORSELx = 3, DCOx = 31, MODx = 0  
DCORSELx = 4, DCOx = 0, MODx = 0  
DCORSELx = 4, DCOx = 31, MODx = 0  
DCORSELx = 5, DCOx = 0, MODx = 0  
DCORSELx = 5, DCOx = 31, MODx = 0  
DCORSELx = 6, DCOx = 0, MODx = 0  
DCORSELx = 6, DCOx = 31, MODx = 0  
DCORSELx = 7, DCOx = 0, MODx = 0  
DCORSELx = 7, DCOx = 31, MODx = 0  
MIN  
0.07  
0.70  
0.15  
1.47  
0.32  
3.17  
0.64  
6.07  
1.3  
TYP  
MAX UNIT  
0.20 MHz  
1.70 MHz  
0.36 MHz  
3.45 MHz  
0.75 MHz  
7.38 MHz  
1.51 MHz  
14.0 MHz  
3.2 MHz  
fDCO(0,0)  
fDCO(0,31)  
fDCO(1,0)  
fDCO(1,31)  
fDCO(2,0)  
fDCO(2,31)  
fDCO(3,0)  
fDCO(3,31)  
fDCO(4,0)  
fDCO(4,31)  
fDCO(5,0)  
fDCO(5,31)  
fDCO(6,0)  
fDCO(6,31)  
fDCO(7,0)  
fDCO(7,31)  
DCO frequency (0, 0)  
DCO frequency (0, 31)  
DCO frequency (1, 0)  
DCO frequency (1, 31)  
DCO frequency (2, 0)  
DCO frequency (2, 31)  
DCO frequency (3, 0)  
DCO frequency (3, 31)  
DCO frequency (4, 0)  
DCO frequency (4, 31)  
DCO frequency (5, 0)  
DCO frequency (5, 31)  
DCO frequency (6, 0)  
DCO frequency (6, 31)  
DCO frequency (7, 0)  
DCO frequency (7, 31)  
12.3  
2.5  
28.2 MHz  
6.0 MHz  
23.7  
4.6  
54.1 MHz  
10.7 MHz  
88.0 MHz  
19.6 MHz  
135 MHz  
39.0  
8.5  
60  
Frequency step between range  
DCORSEL and DCORSEL + 1  
SDCORSEL  
SDCO  
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)  
1.2  
2.3 ratio  
Frequency step between tap  
DCO and DCO + 1  
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)  
1.02  
40  
1.12 ratio  
Duty cycle  
dfDCO/dT  
Measured at SMCLK  
DCO frequency temperature drift fDCO = 1 MHz,  
50  
0.1  
1.9  
60  
%
%/°C  
%/V  
dfDCO/dVCC  
DCO frequency voltage drift  
fDCO = 1 MHz  
Typical DCO Frequency, VCC = 3.0 V,TA = 25°C  
100  
10  
DCOx = 31  
1
DCOx = 0  
0.1  
0
1
2
3
4
5
6
7
DCORSEL  
Figure 10. Typical DCO frequency  
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MAX UNIT  
PMM, Brown-Out Reset (BOR)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
| dDVCC/dt | < 3 V/s  
| dDVCC/dt | < 3 V/s  
MIN  
TYP  
BORH on voltage,  
DVCC falling level  
V(DVCC_BOR_IT–)  
1.45  
1.50  
V
V
BORH off voltage,  
DVCC rising level  
V(DVCC_BOR_IT+)  
V(DVCC_BOR_hys)  
0.80  
60  
1.30  
BORH hysteresis  
250 mV  
µs  
Pulse length required at  
RST/NMI pin to accept a  
reset  
tRESET  
2
PMM, Core Voltage  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
Core voltage, active mode,  
PMMCOREV = 3  
VCORE3(AM)  
VCORE2(AM)  
VCORE1(AM)  
VCORE0(AM)  
VCORE3(LPM)  
VCORE2(LPM)  
VCORE1(LPM)  
VCORE0(LPM)  
2.4 V ≤ DVCC ≤ 3.6 V  
1.90  
V
Core voltage, active mode,  
PMMCOREV = 2  
2.2 V ≤ DVCC ≤ 3.6 V  
2.0 V ≤ DVCC ≤ 3.6 V  
1.8 V ≤ DVCC ≤ 3.6 V  
2.4 V ≤ DVCC ≤ 3.6 V  
2.2 V ≤ DVCC ≤ 3.6 V  
2.0 V ≤ DVCC ≤ 3.6 V  
1.8 V ≤ DVCC ≤ 3.6 V  
1.80  
1.60  
1.40  
1.94  
1.84  
1.64  
1.44  
V
V
V
V
V
V
V
Core voltage, active mode,  
PMMCOREV = 1  
Core voltage, active mode,  
PMMCOREV = 0  
Core voltage, low-current mode,  
PMMCOREV = 3  
Core voltage, low-current mode,  
PMMCOREV = 2  
Core voltage, low-current mode,  
PMMCOREV = 1  
Core voltage, low-current mode,  
PMMCOREV = 0  
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PMM, SVS High Side  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
SVSHE = 0, DVCC = 3.6 V  
MIN  
TYP  
0
MAX UNIT  
nA  
nA  
I(SVSH)  
SVS current consumption SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0  
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1  
200  
1.5  
µA  
SVSHE = 1, SVSHRVL = 0  
1.57  
1.79  
1.98  
2.10  
1.62  
1.88  
2.07  
2.20  
2.32  
2.52  
2.90  
2.90  
1.68  
1.88  
2.08  
2.18  
1.74  
1.94  
2.14  
2.30  
2.40  
2.70  
3.10  
3.10  
1.78  
SVSHE = 1, SVSHRVL = 1  
SVSH on voltage level(1)  
1.98  
V
V(SVSH_IT–)  
SVSHE = 1, SVSHRVL = 2  
2.21  
SVSHE = 1, SVSHRVL = 3  
SVSHE = 1, SVSMHRRL = 0  
SVSHE = 1, SVSMHRRL = 1  
SVSHE = 1, SVSMHRRL = 2  
2.31  
1.85  
2.07  
2.28  
SVSHE = 1, SVSMHRRL = 3  
SVSH off voltage level(1)  
2.42  
V
V(SVSH_IT+)  
SVSHE = 1, SVSMHRRL = 4  
2.55  
SVSHE = 1, SVSMHRRL = 5  
SVSHE = 1, SVSMHRRL = 6  
SVSHE = 1, SVSMHRRL = 7  
SVSHE = 1, dVDVCC/dt = 10 mV/µs,  
2.88  
3.23  
3.23  
2.5  
20  
SVSHFP = 1  
tpd(SVSH)  
SVSH propagation delay  
µs  
µs  
SVSHE = 1, dVDVCC/dt = 1 mV/µs,  
SVSHFP = 0  
SVSHE = 0 → 1  
SVSHFP = 1  
12.5  
100  
t(SVSH)  
SVSH on/off delay time  
SVSHE = 0 → 1  
SVSHFP = 0  
dVDVCC/dt  
DVCC rise time  
0
1000  
V/s  
(1) The SVSH settings available depend on the VCORE (PMMCOREVx) setting. Please refer to the Power Management Module and Supply  
Voltage Supervisor chapter in the MSP430x5xx Family User's Guide (SLAU208) on recommended settings and usage.  
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PMM, SVM High Side  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
SVMHE = 0, DVCC = 3.6 V  
MIN  
TYP  
0
MAX UNIT  
nA  
I(SVMH)  
SVMH current consumption  
SVMHE= 1, DVCC = 3.6 V, SVMHFP = 0  
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1  
SVMHE = 1, SVSMHRRL = 0  
SVMHE = 1, SVSMHRRL = 1  
SVMHE = 1, SVSMHRRL = 2  
SVMHE = 1, SVSMHRRL = 3  
SVMHE = 1, SVSMHRRL = 4  
SVMHE = 1, SVSMHRRL = 5  
SVMHE = 1, SVSMHRRL = 6  
SVMHE = 1, SVSMHRRL = 7  
SVMHE = 1, SVMHOVPE = 1  
200  
1.5  
nA  
µA  
1.62  
1.88  
2.07  
2.20  
2.32  
2.52  
2.90  
2.90  
1.74  
1.94  
2.14  
2.30  
2.40  
2.70  
3.10  
3.10  
3.75  
1.85  
2.07  
2.28  
2.42  
V(SVMH)  
SVMH on/off voltage level(1)  
2.55  
2.88  
3.23  
3.23  
V
SVMHE = 1, dVDVCC/dt = 10 mV/µs,  
SVMHFP = 1  
2.5  
20  
tpd(SVMH)  
SVMH propagation delay  
SVMH on/off delay time  
µs  
µs  
SVMHE = 1, dVDVCC/dt = 1 mV/µs,  
SVMHFP = 0  
SVMHE = 0 → 1  
SVMHFP = 1  
12.5  
100  
t(SVMH)  
SVMHE = 0 → 1  
SVMHFP = 0  
(1) The SVMH settings available depend on the VCORE (PMMCOREVx) setting. Please refer to the Power Management Module and  
Supply Voltage Supervisor chapter in the MSP430x5xx Family User's Guide (SLAU208) on recommended settings and usage.  
PMM, SVS Low Side  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
0
MAX UNIT  
SVSLE = 0, PMMCOREV = 2  
nA  
nA  
µA  
I(SVSL)  
SVSL current consumption  
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0  
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1  
200  
1.5  
SVSLE = 1, dVCORE/dt = 10 mV/µs,  
SVSLFP = 1  
2.5  
20  
tpd(SVSL)  
SVSL propagation delay  
SVSL on/off delay time  
µs  
µs  
SVSLE = 1, dVCORE/dt = 1 mV/µs,  
SVSLFP = 0  
SVSLE = 0 → 1  
SVSLFP = 1  
12.5  
100  
t(SVSL)  
SVSLE = 0 → 1  
SVSLFP = 0  
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PMM, SVM Low Side  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
0
MAX UNIT  
SVMLE = 0, PMMCOREV = 2  
nA  
nA  
µA  
I(SVML)  
SVML current consumption  
SVMLE= 1, PMMCOREV = 2, SVMLFP = 0  
SVMLE= 1, PMMCOREV = 2, SVMLFP = 1  
200  
1.5  
SVMLE = 1, dVCORE/dt = 10 mV/µs,  
SVMLFP = 1  
2.5  
20  
tpd(SVML)  
SVML propagation delay  
SVML on/off delay time  
µs  
µs  
SVMLE = 1, dVCORE/dt = 1 mV/µs,  
SVMLFP = 0  
SVMLE = 0 → 1  
SVMLFP = 1  
12.5  
100  
t(SVML)  
SVMLE = 0 → 1  
SVMLFP = 0  
Wake-up from Low Power Modes and Reset  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
Wake-up time from LPM2,  
LPM3, or LPM4 to active  
mode(1)  
PMMCOREV = SVSMLRRL = n,  
where n = 0, 1, 2, or 3  
SVSLFP = 1  
f
MCLK ≥ 4.0 MHz  
5
tWAKE-UP-FAST  
µs  
fMCLK < 4.0 MHz  
6
Wake-up time from LPM2,  
LPM3 or LPM4 to active  
mode(2)  
PMMCOREV = SVSMLRRL = n, where n = 0, 1, 2,  
or 3  
SVSLFP = 0  
tWAKE-UP-SLOW  
150  
165  
µs  
Wake-up time from LPM4.5 to  
active mode(3)  
tWAKE-UP-LPM5  
tWAKE-UP-RESET  
2
2
3
3
ms  
ms  
Wake-up time from RST or  
BOR event to active mode(3)  
(1) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance  
mode of the low side supervisor (SVSL) and low side monitor (SVML). Fastest wakeup times are possible with SVSLand SVML in full  
performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while  
operating in LPM2, LPM3, and LPM4. Please refer to the Power Management Module and Supply Voltage Supervisor chapter in the  
MSP430x5xx Family User's Guide (SLAU208).  
(2) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance  
mode of the low side supervisor (SVSL) and low side monitor (SVML). In this case, the SVSLand SVML are in normal mode (low current)  
mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while operating in LPM2, LPM3, and  
LPM4. Please refer to the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx Family User's Guide  
(SLAU208).  
(3) This value represents the time from the wakeup event to the reset vector execution.  
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Timer_A  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
TYP  
MAX UNIT  
Internal: SMCLK, ACLK  
External: TACLK  
Duty cycle = 50% ± 10%  
1.8 V/  
3.0 V  
fTA  
Timer_A input clock frequency  
25 MHz  
All capture inputs.  
Minimum pulse width required for  
capture.  
1.8 V/  
3.0 V  
tTA,cap  
Timer_A capture timing  
20  
ns  
Timer_B  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
TYP  
MAX UNIT  
Internal: SMCLK, ACLK  
External: TBCLK  
Duty cycle = 50% ± 10%  
1.8 V/  
3.0 V  
fTB  
Timer_B input clock frequency  
25 MHz  
All capture inputs.  
Minimum pulse width required for  
capture.  
1.8 V/  
3.0 V  
tTB,cap  
Timer_B capture timing  
20  
ns  
USCI (UART Mode) - recommended operating conditions  
PARAMETER  
CONDITIONS  
VCC  
MIN  
TYP  
MAX UNIT  
Internal: SMCLK, ACLK  
External: UCLK  
fUSCI  
USCI input clock frequency  
fSYSTEM MHz  
Duty cycle = 50% ± 10%  
BITCLK clock frequency  
(equals baud rate in MBaud)  
fBITCLK  
1
MHz  
USCI (UART Mode)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
2.2 V  
3 V  
MIN  
50  
TYP  
MAX UNIT  
600  
ns  
tt  
UART receive deglitch time(1)  
50  
600  
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are  
correctly recognized their width should exceed the maximum specification of the deglitch time.  
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USCI (SPI Master Mode) - recommended operating conditions  
PARAMETER  
CONDITIONS  
VCC  
MIN  
TYP  
MAX UNIT  
Internal: SMCLK, ACLK  
Duty cycle = 50% ± 10%  
fUSCI  
USCI input clock frequency  
fSYSTEM MHz  
USCI (SPI Master Mode)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
(see Note (1), Figure 11 and Figure 12)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
TYP  
MAX UNIT  
SMCLK, ACLK  
fUSCI  
USCI input clock frequency  
fSYSTEM MHz  
Duty cycle = 50% ± 10%  
PMMCOREV = 0  
1.8 V  
3.0 V  
2.4 V  
3.0 V  
1.8 V  
3.0 V  
2.4 V  
3.0 V  
1.8 V  
55  
38  
30  
25  
0
ns  
ns  
ns  
tSU,MI  
SOMI input data setup time  
SOMI input data hold time  
PMMCOREV = 3  
PMMCOREV = 0  
PMMCOREV = 3  
0
tHD,MI  
0
ns  
0
UCLK edge to SIMO valid,  
CL = 20 pF  
PMMCOREV = 0  
20  
ns  
3.0 V  
2.4 V  
3.0 V  
18  
tVALID,MO  
SIMO output data valid time(2)  
SIMO output data hold time(3)  
UCLK edge to SIMO valid,  
CL = 20 pF  
PMMCOREV = 3  
16  
ns  
15  
1.8 V  
3.0 V  
2.4 V  
3.0 V  
-10  
-8  
CL = 20 pF  
PMMCOREV = 0  
ns  
ns  
tHD,MO  
-10  
-8  
CL = 20 pF  
PMMCOREV = 3  
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).  
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) refer to the SPI parameters of the attached slave.  
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing  
diagrams in Figure 11 and Figure 12.  
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data  
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in  
Figure 11 and Figure 12.  
1/fUCxCLK  
CKPL = 0  
UCLK  
CKPL = 1  
tLO/HI  
tLO/HI  
tSU,MI  
tHD,MI  
SOMI  
tHD,MO  
tVALID,MO  
SIMO  
Figure 11. SPI Master Mode, CKPH = 0  
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1/fUCxCLK  
CKPL = 0  
UCLK  
CKPL = 1  
tLO/HI  
tLO/HI  
tHD,MI  
tSU,MI  
SOMI  
tHD,MO  
tVALID,MO  
SIMO  
Figure 12. SPI Master Mode, CKPH = 1  
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USCI (SPI Slave Mode)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
(see Note (1), Figure 13 and Figure 14)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
11  
8
TYP  
MAX UNIT  
1.8 V  
3.0 V  
2.4 V  
3.0 V  
1.8 V  
3.0 V  
2.4 V  
3.0 V  
1.8 V  
3.0 V  
2.4 V  
3.0 V  
1.8 V  
3.0 V  
2.4 V  
3.0 V  
1.8 V  
3.0 V  
2.4 V  
3.0 V  
1.8 V  
3.0 V  
2.4 V  
3.0 V  
1.8 V  
PMMCOREV = 0  
ns  
tSTE,LEAD  
tSTE,LAG  
tSTE,ACC  
tSTE,DIS  
tSU,SI  
STE lead time, STE low to clock  
7
PMMCOREV = 3  
PMMCOREV = 0  
PMMCOREV = 3  
PMMCOREV = 0  
PMMCOREV = 3  
PMMCOREV = 0  
PMMCOREV = 3  
PMMCOREV = 0  
PMMCOREV = 3  
PMMCOREV = 0  
PMMCOREV = 3  
ns  
ns  
ns  
6
3
3
STE lag time, Last clock to STE high  
3
3
66  
ns  
50  
STE access time, STE low to SOMI data out  
36  
ns  
30  
30  
ns  
23  
STE disable time, STE high to SOMI high  
impedance  
16  
ns  
13  
5
5
2
2
5
5
5
5
ns  
ns  
ns  
SIMO input data setup time  
SIMO input data hold time  
tHD,SI  
ns  
UCLK edge to SOMI valid,  
CL = 20 pF  
PMMCOREV = 0  
76  
ns  
3.0 V  
2.4 V  
3.0 V  
60  
tVALID,SO  
SOMI output data valid time(2)  
SOMI output data hold time(3)  
UCLK edge to SOMI valid,  
CL = 20 pF  
PMMCOREV = 3  
44  
ns  
40  
1.8 V  
3.0 V  
2.4 V  
3.0 V  
18  
12  
10  
8
CL = 20 pF  
PMMCOREV = 0  
ns  
ns  
tHD,SO  
CL = 20 pF  
PMMCOREV = 3  
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).  
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached slave.  
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing  
diagrams in Figure 11 and Figure 12.  
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in  
Figure 11 and Figure 12.  
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tSTE,LEAD  
tSTE,LAG  
STE  
1/fUCxCLK  
CKPL = 0  
UCLK  
CKPL = 1  
tSU,SI  
tLO/HI  
tLO/HI  
tHD,SI  
SIMO  
tHD,SO  
tVALID,SO  
tSTE,ACC  
tSTE,DIS  
SOMI  
Figure 13. SPI Slave Mode, CKPH = 0  
tSTE,LEAD  
tSTE,LAG  
STE  
1/fUCxCLK  
CKPL = 0  
UCLK  
CKPL = 1  
tLO/HI  
tLO/HI  
tHD,SI  
tSU,SI  
SIMO  
tHD,MO  
tVALID,SO  
tSTE,ACC  
tSTE,DIS  
SOMI  
Figure 14. SPI Slave Mode, CKPH = 1  
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USCI (I2C Mode)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 15)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
TYP  
MAX UNIT  
Internal: SMCLK, ACLK  
External: UCLK  
fUSCI  
USCI input clock frequency  
fSYSTEM MHz  
Duty cycle = 50% ± 10%  
fSCL  
SCL clock frequency  
2.2 V/3 V  
2.2 V/3 V  
0
4.0  
0.6  
4.7  
0.6  
0
400 kHz  
µs  
f
SCL ≤ 100 kHz  
fSCL > 100 kHz  
SCL ≤ 100 kHz  
fSCL > 100 kHz  
tHD,STA  
Hold time (repeated) START  
f
tSU,STA  
Setup time for a repeated START  
2.2 V/3 V  
µs  
tHD,DAT  
tSU,DAT  
Data hold time  
Data setup time  
2.2 V/3 V  
2.2 V/3 V  
ns  
ns  
250  
4.0  
0.6  
50  
fSCL ≤ 100 kHz  
tSU,STO  
Setup time for STOP  
2.2 V/3 V  
µs  
fSCL > 100 kHz  
2.2 V  
3 V  
600  
ns  
tSP  
Pulse width of spikes suppressed by input filter  
50  
600  
tHD,STA  
tSU,STA  
tHD,STA  
tBUF  
SDA  
SCL  
tLOW  
tHIGH  
tSP  
tSU,DAT  
tSU,STO  
tHD,DAT  
Figure 15. I2C Mode Timing  
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MAX UNIT  
12-Bit ADC, Power Supply and Input Range Conditions  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
2.2  
0
TYP  
AVCC and DVCC are connected together,  
AVSS and DVSS are connected together,  
V(AVSS) = V(DVSS) = 0 V  
Analog supply voltage  
Full performance  
AVCC  
3.6  
V
V
V(Ax)  
Analog input voltage range(2) All ADC12 analog input pins Ax  
AVCC  
155  
fADC12CLK = 5.0 MHz, ADC12ON = 1,  
Operating supply current into  
2.2 V  
3 V  
125  
150  
IADC12_A  
REFON = 0, SHT0 = 0, SHT1 = 0,  
AVCC terminal(3)  
µA  
220  
ADC12DIV = 0  
Only one terminal Ax can be selected at one  
CI  
RI  
Input capacitance  
time  
2.2 V  
20  
25  
pF  
Input MUX ON resistance  
0 V ≤ VAx ≤ AVCC  
10  
200  
1900  
Ω
(1) The leakage current is specified by the digital I/O input leakage.  
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If the  
reference voltage is supplied by an external source or if the internal reference voltage is used and REFOUT = 1, then decoupling  
capacitors are required. See REF, External Reference andREF, Built-In Reference.  
(3) The internal reference supply current is not included in current consumption parameter IADC12_A  
.
12-Bit ADC, Timing Parameters  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
TYP  
MAX UNIT  
For specified performance of ADC12 linearity  
parameters  
fADC12CLK  
fADC12OSC  
2.2 V/3 V  
0.45  
4.8  
5.4 MHz  
Internal ADC12  
oscillator(1)  
ADC12DIV = 0, fADC12CLK = fADC12OSC  
2.2 V/3 V  
2.2 V/3 V  
4.2  
2.4  
4.8  
5.4 MHz  
REFON = 0, Internal oscillator,  
fADC12OSC = 4.2 MHz to 5.4 MHz  
3.1  
µs  
tCONVERT  
Conversion time  
External fADC12CLK from ACLK, MCLK or SMCLK,  
(2)  
ADC12SSEL ≠ 0  
RS = 400 Ω, RI = 1000 Ω, CI = 20 pF,  
t = [RS + RI] × CI  
tSample  
Sampling time  
2.2 V/3 V  
1000  
ns  
(3)  
(1) The ADC12OSC is sourced directly from MODOSC inside the UCS.  
(2) 13 × ADC12DIV × 1/fADC12CLK  
(3) Approximately ten Tau (t) are needed to get an error of less than ±0.5 LSB:  
tSample = ln(2n+1) x (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance  
12-Bit ADC, Linearity Parameters  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
TYP  
MAX UNIT  
1.4 V ≤ (VeREF+ – VREF–/VeREF–)min ≤ 1.6 V  
1.6 V < (VeREF+ – VREF–/VeREF–)min ≤ VAVCC  
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),  
±2  
LSB  
±1.7  
Integral  
linearity error (INL)  
EI  
2.2 V/3 V  
Differential  
ED  
EO  
EG  
ET  
2.2 V/3 V  
2.2 V/3 V  
2.2 V/3 V  
2.2 V/3 V  
±1.0 LSB  
±2.0 LSB  
±2.0 LSB  
±3.5 LSB  
linearity error (DNL) CVREF+ = 20 pF  
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),  
Internal impedance of source RS < 100 Ω, CVREF+ = 20 pF  
Offset error  
Gain error  
±1.0  
±1.0  
±1.4  
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),  
CVREF+ = 20 pF  
Total unadjusted  
error  
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),  
CVREF+ = 20 pF  
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(1)  
12-Bit ADC, Temperature Sensor and Built-In VMID  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
2.2 V  
3 V  
MIN  
TYP  
680  
680  
2.25  
2.25  
MAX UNIT  
ADC12ON = 1, INCH = 0Ah,  
TA = 0°C  
(2)  
VSENSOR  
See  
mV  
2.2 V  
3 V  
TCSENSOR  
ADC12ON = 1, INCH = 0Ah  
mV/°C  
2.2 V  
3 V  
30  
30  
Sample time required if  
channel 10 is selected(3)  
ADC12ON = 1, INCH = 0Ah,  
Error of conversion result ≤ 1 LSB  
tSENSOR(sample)  
µs  
AVCC divider at channel 11,  
VAVCC factor  
ADC12ON = 1, INCH = 0Bh  
ADC12ON = 1, INCH = 0Bh  
0.48  
0.5  
0.52 VAVCC  
VMID  
2.2 V  
3 V  
1.06  
1.44  
1.1  
1.5  
1.14  
V
AVCC divider at channel 11  
1.56  
Sample time required if  
channel 11 is selected(4)  
ADC12ON = 1, INCH = 0Bh,  
Error of conversion result ≤ 1 LSB  
tVMID(sample)  
2.2 V/3 V  
1000  
ns  
(1) The temperature sensor is provided by the REF module. Please refer to the REF module parametric, IREF+, regarding the current  
consumption of the temperature sensor.  
(2) The temperature sensor offset can be as much as ±20°C. A single-point calibration is recommended in order to minimize the offset error  
of the built-in temperature sensor. The TLV structure contains calibration values for 30°C ± 3°C and 85°C ± 3°C for each of the available  
reference voltage levels. The sensor voltage can be computed as VSENSE = TCSENSOR * (Temperature,°C) + VSENSOR, where TCSENSOR  
and VSENSOR can be computed from the calibration values for higher accuracy. See also the MSP430x5xx Family User's Guide  
(SLAU208).  
(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)  
.
(4) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.  
1000  
950  
900  
850  
800  
750  
700  
650  
600  
550  
500  
-40 -30 -20 -10  
0 10 20 30 40 50 60 70 80  
Ambient Temperature - ˚C  
Figure 16. Typical Temperature Sensor Voltage  
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MAX UNIT  
REF, External Reference  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
TYP  
Positive external reference  
voltage input  
(2)  
VeREF+  
VeREF+ > VREF–/VeREF–  
1.4  
AVCC  
1.2  
V
V
V
Negative external reference  
voltage input  
(3)  
(4)  
VREF–/VeREF–  
VeREF+ > VREF–/VeREF–  
VeREF+ > VREF–/VeREF–  
0
(VeREF+  
VREF–/VeREF–  
–
Differential external reference  
voltage input  
1.4  
AVCC  
)
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0  
V, fADC12CLK = 5 MHz,  
ADC12SHTx = 1h,  
2.2 V/3 V  
2.2 V/3 V  
±8.5  
±26  
±1  
µA  
Conversion rate 200ksps  
IVeREF+,  
IVREF–/VeREF–  
Static input current  
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0  
V, fADC12CLK = 5 MHz,  
ADC12SHTx = 8h,  
µA  
µF  
Conversion rate 20ksps  
CVREF+/-  
Capacitance at VREF+/- terminal  
(5)10  
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also  
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the  
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.  
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced  
accuracy requirements.  
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced  
accuracy requirements.  
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with  
reduced accuracy requirements.  
(5) Two decoupling capacitors, 10µF and 100nF, should be connected to VREF to decouple the dynamic current required for an external  
reference source if it is used for the ADC12_A. See also the MSP430x5xx Family User's Guide (SLAU208).  
REF, Built-In Reference  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
TYP  
MAX UNIT  
REFVSEL = {2} for 2.5 V  
REFON = REFOUT = 1  
IVREF+= 0 A  
3 V  
2.50 ±1.5%  
1.98 ±1.5%  
1.49 ±1.5%  
REFVSEL = {1} for 2.0 V  
REFON = REFOUT = 1  
IVREF+= 0 A  
Positive built-in reference  
voltage output  
VREF+  
3 V  
V
V
REFVSEL = {0} for 1.5 V  
REFON = REFOUT = 1  
IVREF+= 0 A  
2.2 V/ 3 V  
REFVSEL = {0} for 1.5 V, reduced  
performance  
1.8  
AVCC minimum voltage,  
Positive built-in reference  
active  
REFVSEL = {0} for 1.5 V  
2.2  
2.3  
2.8  
AVCC(min)  
REFVSEL = {1} for 2.0 V  
REFVSEL = {2} for 2.5 V  
REFON = 1, REFOUT = 0, REFBURST = 0  
REFON = 1, REFOUT = 1, REFBURST = 0  
3 V  
3 V  
100  
0.9  
140  
1.5  
µA  
Operating supply current into  
AVCC terminal(2) (3)  
IREF+  
mA  
(1) The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers, one  
smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal, as well as,  
used as the reference for the conversion and utilizes the larger buffer. When REFOUT = 0, the reference is only used as the reference  
for the conversion and utilizes the smaller buffer.  
(2) The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a  
conversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current  
contribution of the larger buffer without external load.  
(3) The temperature sensor is provided by the REF module. Its current is supplied via terminal AVCC and is equivalent to IREF+ with REFON  
=1 and REFOUT = 0.  
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REF, Built-In Reference (continued)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
TYP  
MAX UNIT  
REFVSEL = (0, 1, 2}  
Load-current regulation,  
VREF+ terminal(4)  
IVREF+ = +10 µA/–1000 µA  
AVCC = AVCC (min) for each reference level.  
REFVSEL = (0, 1, 2}, REFON = REFOUT = 1  
IL(VREF+)  
2500 µV/mA  
Capacitance at VREF+/-  
terminals  
CVREF+/-  
REFON = REFOUT = 1(5)  
20  
100  
50  
pF  
IVREF+ = 0 A  
REFVSEL = (0, 1, 2}, REFON = 1,  
REFOUT = 0 or 1  
Temperature coefficient of  
built-in reference(6)  
ppm/°  
C
TCREF+  
30  
AVCC = AVCC (min) - AVCC(max)  
TA = 25°C  
REFVSEL = (0, 1, 2}, REFON = 1,  
REFOUT = 0 or 1  
Power supply rejection ratio  
(DC)  
PSRR_DC  
PSRR_AC  
120  
300 µV/V  
mV/V  
AVCC = AVCC (min) - AVCC(max)  
TA = 25°C  
f = 1 kHz, ΔVpp = 100 mV  
REFVSEL = (0, 1, 2}, REFON = 1,  
REFOUT = 0 or 1  
Power supply rejection ratio  
(AC)  
6.4  
AVCC = AVCC (min) - AVCC(max)  
REFVSEL = (0, 1, 2}, REFOUT = 0,  
REFON = 0 → 1  
75  
75  
Settling time of reference  
voltage(7)  
tSETTLE  
µs  
AVCC = AVCC (min) - AVCC(max)  
CVREF = CVREF(max)  
REFVSEL = (0, 1, 2}, REFOUT = 1,  
REFON = 0 → 1  
(4) Contribution only due to the reference and buffer including package. This does not include resistance due to PCB trace, etc.  
(5) Two decoupling capacitors, 10µF and 100nF, should be connected to VREF to decouple the dynamic current required for an external  
reference source if it is used for the ADC12_A. See also the MSP430x5xx Family User's Guide (SLAU208).  
(6) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C)/(85°C – (–40°C)).  
(7) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external  
capacitive load when REFOUT = 1.  
Comparator B  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
TYP  
MAX UNIT  
VCC  
Supply voltage  
1.8  
3.6  
40  
50  
65  
30  
0.5  
V
1.8 V  
2.2 V  
CBPWRMD = 00  
30  
40  
Comparator operating supply  
current into AVCC. Excludes  
reference resistor ladder.  
IAVCC_COMP  
3.0 V  
µA  
CBPWRMD = 01  
CBPWRMD = 10  
2.2/3.0 V  
2.2/3.0 V  
10  
0.1  
Quiescent current of local  
IAVCC_REF  
reference voltage amplifier into  
CBREFACC = 1, CBREFLx = 01  
22  
µA  
AVCC  
.
VIC  
Common mode input range  
0
VCC-1  
±20  
V
CBPWRMD = 00  
mV  
mV  
pF  
kΩ  
MΩ  
ns  
VOFFSET  
CIN  
Input offset voltage  
CBPWRMD = 01, 10  
±10  
Input capacitance  
5
3
ON - switch closed  
4
RSIN  
Series input resistance  
OFF - switch opened  
CBPWRMD = 00, CBF = 0  
30  
450  
600  
50  
tPD  
Propagation delay, response time CBPWRMD = 01, CBF = 0  
CBPWRMD = 10, CBF = 0  
ns  
µs  
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MAX UNIT  
Comparator B (continued)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
TYP  
CBPWRMD = 00, CBON = 1,  
CBF = 1, CBFDLY = 00  
0.35  
0.6  
1.0  
1.8  
3.4  
6.5  
µs  
µs  
µs  
µs  
CBPWRMD = 00, CBON = 1,  
CBF = 1, CBFDLY = 01  
0.6  
1.0  
1.8  
1.0  
1.8  
3.4  
Propagation delay with filter  
active  
tPD,filter  
CBPWRMD = 00, CBON = 1,  
CBF = 1, CBFDLY = 10  
CBPWRMD = 00, CBON = 1,  
CBF = 1, CBFDLY = 11  
Comparator enable time, settling CBON = 0 to CBON = 1  
tEN_CMP  
tEN_REF  
1
2
µs  
µs  
time  
CBPWRMD = 00, 01, 10  
Resistor reference enable time  
CBON = 0 to CBON = 1  
0.3  
1.5  
VIN*(n  
+1)  
VIN = reference into resistor ladder.  
n = 0 to 31  
VCB_REF  
Reference voltage for a given tap  
V
/32  
Ports PU.0 and PU.1  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VUSB = 3.3 V ± 10%, IOH = -25 mA  
VUSB = 3.3 V ± 10%, IOL = 25 mA  
VUSB = 3.3 V ± 10%  
VCC  
MIN  
TYP  
MAX UNIT  
VOH  
VOL  
VIH  
VIL  
High-level output voltage  
Low-level output voltage  
High-level input voltage  
Low-level input voltage  
2.4  
V
0.4  
0.8  
V
V
V
2.0  
VUSB = 3.3 V ± 10%  
USB-Output Ports DP and DM  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
USB 2.0 load conditions  
VCC  
MIN  
2.8  
0
TYP  
MAX UNIT  
VOH  
D+, D- single ended  
D+, D- single ended  
D+, D- impedance  
3.6  
0.3  
44  
V
V
Ω
VOL  
USB 2.0 load conditions  
Z(DRV)  
Including external series resistor of 27 Ω  
28  
Full speed, differential, CL = 50 pF,  
10%/90%, Rpu on D+  
tRISE  
tFALL  
Rise time  
Fall time  
4
4
20  
20  
ns  
ns  
Full speed, differential, CL = 50 pF,  
10%/90%, Rpu on D+  
USB-Input Ports DP and DM  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
0.8  
TYP  
MAX UNIT  
V(CM)  
Z(IN)  
VCRS  
VIL  
Differential input common mode range  
Input impedance  
2.5  
V
kΩ  
V
300  
1.3  
Crossover voltage  
2.0  
Static SE input logic low level  
Static SE input logic high level  
Differential input voltage  
0.8  
V
VIH  
2.0  
0.2  
V
VDI  
V
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USB-PWR (USB Power System)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
VBUS detection threshold  
USB bus voltage  
TEST CONDITIONS  
VCC  
MIN  
TYP  
MAX UNIT  
VLAUNCH  
VBUS  
VUSB  
V18  
3.75  
5.5  
V
V
V
V
Normal operation  
3.76  
USB LDO output voltage  
Internal USB voltage(1)  
3.3  
1.8  
±9%  
Maximum external current from VUSB  
terminal(2)  
USB LDO current overload detection(3)  
IUSB_EXT  
IDET  
USB LDO is on  
12  
100  
250  
mA  
mA  
µA  
60  
USB LDO is on,  
USB PLL disabled  
ISUSPEND  
Operating supply current into VBUS terminal.(4)  
CBUS  
CUSB  
C18  
VBUS terminal recommended capacitance  
VUSB terminal recommended capacitance  
V18 terminal recommended capacitance  
4.7  
220  
220  
µF  
nF  
nF  
Within 2%,  
recommended capacitances  
tENABLE  
RPUR  
Settling time VUSB and V18  
2
ms  
Pullup resistance of PUR terminal  
70  
110  
150  
Ω
(1) This voltage is for internal usages only. No external DC loading should be applied.  
(2) This represents additional current that can be supplied to the application from the VUSB terminal beyond the needs of the USB  
operation.  
(3) A current overload will be detected when the total current supplied from the USB LDO, including IUSB_EXT, exceeds this value.  
(4) Does not include current contribution of Rpu and Rpd as outlined in the USB specification.  
USB-PLL (USB Phase Locked Loop)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
TYP  
MAX UNIT  
IPLL  
Operating supply current  
PLL frequency  
7
mA  
MHz  
MHz  
ms  
fPLL  
48  
fUPD  
tLOCK  
tJitter  
PLL reference frequency  
PLL lock time  
1.5  
3
2
PLL jitter  
1000  
ps  
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Flash Memory  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
TEST  
CONDITIONS  
PARAMETER  
MIN  
TYP  
MAX UNIT  
DVCC(PGM/ERASE) Program and erase supply voltage  
1.8  
3.6  
5
V
mA  
IPGM  
Average supply current from DVCC during program  
3
IERASE  
Average supply current from DVCC during erase  
Average supply current from DVCC during mass erase or bank erase  
Cumulative program time  
2
mA  
IMERASE, IBANK  
tCPT  
2
mA  
(1)  
See  
16  
ms  
Program/erase endurance  
104  
100  
64  
105  
cycles  
years  
µs  
tRetention  
tWord  
Data retention duration  
TJ = 25°C  
(2)  
Word or byte program time  
See  
85  
65  
(2)  
tBlock, 0  
Block program time for first byte or word  
See  
49  
µs  
Block program time for each additional byte or word, except for last  
byte or word  
(2)  
tBlock, 1–(N–1)  
tBlock, N  
See  
37  
55  
23  
49  
73  
32  
µs  
µs  
(2)  
Block program time for last byte or word  
See  
Erase time for segment, mass erase, and bank erase when  
available.  
(2)  
tErase  
See  
ms  
MCLK frequency in marginal read mode  
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)  
fMCLK,MGR  
0
1
MHz  
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming  
methods: individual word/byte write and block write modes.  
(2) These values are hardwired into the flash controller's state machine.  
JTAG and Spy-Bi-Wire Interface  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
TEST  
CONDITIONS  
PARAMETER  
MIN  
TYP  
MAX UNIT  
fSBW  
Spy-Bi-Wire input frequency  
2.2 V/3 V  
0
20 MHz  
tSBW,Low  
Spy-Bi-Wire low clock pulse length  
2.2 V/3 V  
0.025  
15  
µs  
Spy-Bi-Wire enable time (TEST high to acceptance of first clock  
edge)(1)  
tSBW, En  
tSBW,Rst  
2.2 V/3 V  
1
µs  
Spy-Bi-Wire return to normal operation time  
TCK input frequency - 4-wire JTAG(2)  
Internal pulldown resistance on TEST  
15  
0
100  
5
µs  
2.2 V  
3 V  
MHz  
fTCK  
0
10 MHz  
80 kΩ  
Rinternal  
2.2 V/3 V  
45  
60  
(1) Tools accessing the Spy-Bi-Wire interface need to wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the  
first SBWTCK clock edge.  
(2) fTCK may be restricted to meet the timing requirements of the module selected.  
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INPUT/OUTPUT SCHEMATICS  
Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger  
Pad Logic  
P1REN.x  
DVSS  
DVCC  
0
1
1
P1DIR.x  
0
1
Direction  
0: Input  
1: Output  
From module  
P1OUT.x  
0
1
From module  
P1.0/TA0CLK/ACLK  
P1.1/TA0.0  
P1.2/TA0.1  
P1.3/TA0.2  
P1.4/TA0.3  
P1DS.x  
0: Low drive  
1: High drive  
P1SEL.x  
P1IN.x  
P1.5/TA0.4  
P1.6/TA1CLK/CBOUT  
P1.7/TA1.0  
EN  
D
To module  
P1IRQ.x  
P1IE.x  
EN  
Q
P1IFG.x  
Set  
P1SEL.x  
P1IES.x  
Interrupt  
Edge  
Select  
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Table 48. Port P1 (P1.0 to P1.7) Pin Functions  
CONTROL BITS/SIGNALS  
PIN NAME (P1.x)  
x
FUNCTION  
P1DIR.x  
P1SEL.x  
P1.0/TA0CLK/ACLK  
0
P1.0 (I/O)  
TA0CLK  
I: 0; O: 1  
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
ACLK  
1
P1.1/TA0.0  
1
2
3
4
5
6
7
P1.1 (I/O)  
TA0.CCI0A  
TA0.0  
I: 0; O: 1  
0
1
P1.2/TA0.1  
P1.2 (I/O)  
TA0.CCI1A  
TA0.1  
I: 0; O: 1  
0
1
P1.3/TA0.2  
P1.3 (I/O)  
TA0.CCI2A  
TA0.2  
I: 0; O: 1  
0
1
P1.4/TA0.3  
P1.4 (I/O)  
TA0.CCI3A  
TA0.3  
I: 0; O: 1  
0
1
P1.5/TA0.4  
P1.5 (I/O)  
TA0.CCI4A  
TA0.4  
I: 0; O: 1  
0
1
P1.6/TA1CLK/CBOUT  
P1.7/TA1.0  
P1.6 (I/O)  
TA1CLK  
I: 0; O: 1  
0
CBOUT comparator B  
P1.7 (I/O)  
TA1.CCI0A  
TA1.0  
1
I: 0; O: 1  
0
1
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Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger  
Pad Logic  
P2REN.x  
DVSS  
DVCC  
0
1
1
P2DIR.x  
0
1
Direction  
0: Input  
1: Output  
From module  
P2OUT.x  
0
1
From module  
P2.0/TA1.1  
P2.1/TA1.2  
P2.2/TA2CLK/SMCLK  
P2.3/TA2.0  
P2.4/TA2.1  
P2DS.x  
0: Low drive  
1: High drive  
P2SEL.x  
P2IN.x  
P2.5/TA2.2  
P2.6/RTCCLK/DMAE0  
P2.7/UB0STE/UCA0CLK  
EN  
D
To module  
To module  
P2IE.x  
EN  
Q
P2IFG.x  
Set  
P2SEL.x  
P2IES.x  
Interrupt  
Edge  
Select  
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Table 49. Port P2 (P2.0 to P2.7) Pin Functions  
CONTROL BITS/SIGNALS(1)  
PIN NAME (P2.x)  
P2.0/TA1.1  
x
FUNCTION  
P2DIR.x  
P2SEL.x  
0
P2.0 (I/O)  
TA1.CCI1A  
TA1.1  
I: 0; O: 1  
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
P2.1/TA1.2  
1
2
3
4
5
6
7
P2.1 (I/O)  
TA1.CCI2A  
TA1.2  
I: 0; O: 1  
0
1
P2.2/TA2CLK/SMCLK  
P2.3/TA2.0  
P2.2 (I/O)  
TA2CLK  
I: 0; O: 1  
0
SMCLK  
1
P2.3 (I/O)  
TA2.CCI0A  
TA2.0  
I: 0; O: 1  
0
1
P2.4/TA2.1  
P2.4 (I/O)  
TA2.CCI1A  
TA2.1  
I: 0; O: 1  
0
1
P2.5/TA2.2  
P2.5 (I/O)  
TA2.CCI2A  
TA2.2  
I: 0; O: 1  
0
1
P2.6/RTCCLK/DMAE0  
P2.6 (I/O)  
DMAE0  
I: 0; O: 1  
0
RTCCLK  
P2.7 (I/O)  
UCB0STE/UCA0CLK(2) (3)  
1
I: 0; O: 1  
X
P2.7/UCB0STE/UCA0CLK  
(1) X = Don't care  
(2) The pin direction is controlled by the USCI module.  
(3) UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI A0/B0 is forced  
to 3-wire SPI mode if 4-wire SPI mode is selected.  
80  
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Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger  
Pad Logic  
P3REN.x  
DVSS  
DVCC  
0
1
1
P3DIR.x  
0
1
Direction  
0: Input  
1: Output  
From module  
P3OUT.x  
0
1
From module  
P3.0/UCB0SIMO/UCB0SDA  
P3.1/UCB0SOMI/UCB0SCL  
P3.2/UCB0CLK/UCA0STE  
P3.3/UCA0TXD/UCA0SIMO  
P3.4/UCA0RXD/UCA0SOMI  
P3.5/TB0.5  
P3DS.x  
0: Low drive  
1: High drive  
P3SEL.x  
P3IN.x  
P3.6/TB0.6  
P3.7/TB0OUTH/SVMOUT  
EN  
D
To module  
Table 50. Port P3 (P3.0 to P3.7) Pin Functions  
CONTROL BITS/SIGNALS(1)  
PIN NAME (P3.x)  
x
FUNCTION  
P3DIR.x  
P3SEL.x  
P3.0/UCB0SIMO/UCB0SDA  
0
1
2
3
4
5
P3.0 (I/O)  
UCB0SIMO/UCB0SDA(2) (3)  
I: 0; O: 1  
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
1
0
1
1
X
P3.1/UCB0SOMI/UCB0SCL  
P3.2/UCB0CLK/UCA0STE  
P3.3/UCA0TXD/UCA0SIMO  
P3.4/UCA0RXD/UCA0SOMI  
P3.5/TB0.5(5)  
P3.1 (I/O)  
I: 0; O: 1  
UCB0SOMI/UCB0SCL(2) (3)  
P3.2 (I/O)  
UCB0CLK/UCA0STE(2) (4)  
X
I: 0; O: 1  
X
P3.3 (I/O)  
I: 0; O: 1  
UCA0TXD/UCA0SIMO(2)  
P3.4 (I/O)  
UCA0RXD/UCA0SOMI(2)  
X
I: 0; O: 1  
X
P3.5 (I/O)  
I: 0; O: 1  
TB0.CCI5A  
0
TB0.5  
1
P3.6/TB0.6(5)  
6
7
P3.6 (I/O)  
I: 0; O: 1  
TB0.CCI6A  
0
TB0.6  
1
P3.7/TB0OUTH/SVMOUT(5)  
P3.7 (I/O)  
I: 0; O: 1  
TB0OUTH  
0
1
SVMOUT  
(1) X = Don't care  
(2) The pin direction is controlled by the USCI module.  
(3) If the I2C functionality is selected, the output drives only the logical 0 to VSS level.  
(4) UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI A0/B0 is forced  
to 3-wire SPI mode if 4-wire SPI mode is selected.  
(5) 'F5529, 'F5527, 'F5525, 'F5521, 'F5519, 'F5517, 'F5515 devices only.  
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Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger  
Pad Logic  
P4REN.x  
DVSS  
DVCC  
0
1
1
P4DIR.x  
0
1
Direction  
0: Input  
1: Output  
from Port Mapping Control  
P4OUT.x  
0
1
from Port Mapping Control  
P4.0/P4MAP0  
P4.1/P4MAP1  
P4.2/P4MAP2  
P4.3/P4MAP3  
P4.4/P4MAP4  
P4.5/P4MAP5  
P4.6/P4MAP6  
P4.7/P4MAP7  
P4DS.x  
0: Low drive  
1: High drive  
P4SEL.x  
P4IN.x  
EN  
D
to Port Mapping Control  
Table 51. Port P4 (P4.0 to P4.7) Pin Functions  
CONTROL BITS/SIGNALS  
PIN NAME (P4.x)  
x
FUNCTION  
P4DIR.x(1)  
P4SEL.x  
P4MAPx  
P4.0/P4MAP0  
0
P4.0 (I/O)  
I: 0; O: 1  
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
≤ 30  
X
Mapped secondary digital function  
P4.1 (I/O)  
X
P4.1/P4MAP1  
P4.2/P4MAP2  
P4.3/P4MAP3  
P4.4/P4MAP4  
P4.5/P4MAP5  
P4.6/P4MAP6  
P4.7/P4MAP7  
1
2
3
4
5
6
7
I: 0; O: 1  
Mapped secondary digital function  
P4.2 (I/O)  
X
≤ 30  
X
I: 0; O: 1  
Mapped secondary digital function  
P4.3 (I/O)  
X
≤ 30  
X
I: 0; O: 1  
Mapped secondary digital function  
P4.4 (I/O)  
X
≤ 30  
X
I: 0; O: 1  
Mapped secondary digital function  
P4.5 (I/O)  
X
≤ 30  
X
I: 0; O: 1  
Mapped secondary digital function  
P4.6 (I/O)  
X
I: 0; O: 1  
X
≤ 30  
X
Mapped secondary digital function  
P4.7 (I/O)  
≤ 30  
X
I: 0; O: 1  
X
Mapped secondary digital function  
≤ 30  
(1) The direction of some mapped secondary functions are controlled directly by the module. Please refer to Table 9 for specific direction  
control information of mapped secondary functions.  
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Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger  
Pad Logic  
to/from Reference  
(n/a MSP430F551x)  
(n/a MSPF430F551x)  
to ADC12  
(n/a MSPF430F551x)  
INCHx = x  
P5REN.x  
DVSS  
DVCC  
0
1
1
P5DIR.x  
0
1
P5OUT.x  
0
1
From module  
P5.0/(A8/VREF+/VeREF+)  
P5.1/(A9/VREF–/VeREF–)  
P5DS.x  
0: Low drive  
1: High drive  
P5SEL.x  
P5IN.x  
Bus  
Keeper  
EN  
D
To module  
Table 52. Port P5 (P5.0 and P5.1) Pin Functions  
CONTROL BITS/SIGNALS(1)  
PIN NAME (P5.x)  
x
FUNCTION  
P5DIR.x  
P5SEL.x  
REFOUT  
P5.0/A8/VREF+/VeREF+(2)  
0
P5.0 (I/O)(3)  
A8/VeREF+(4)  
A8/VREF+(5)  
P5.1 (I/O)(3)  
A9/VeREF–(7)  
A9/VREF–(8)  
I: 0; O: 1  
0
1
1
0
1
1
X
0
1
X
0
1
X
X
P5.1/A9/VREF–/VeREF–(6)  
1
I: 0; O: 1  
X
X
(1) X = Don't care  
(2) VREF+/VeREF+ available on MSP430F552x devices only.  
(3) Default condition  
(4) Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying  
analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A when available. Channel A8,  
when selected with the INCHx bits, is connected to the VREF+/VeREF+ pin.  
(5) Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying  
analog signals. The VREF+ reference is available at the pin. Channel A8, when selected with the INCHx bits, is connected to the  
VREF+/VeREF+ pin.  
(6) VREF-/VeREF- available on MSP430F552x devices only.  
(7) Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying  
analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A when available. Channel A9,  
when selected with the INCHx bits, is connected to the VREF-/VeREF- pin.  
(8) Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying  
analog signals. The VREF– reference is available at the pin. Channel A9, when selected with the INCHx bits, is connected to the  
VREF-/VeREF- pin.  
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Port P5, P5.2, Input/Output With Schmitt Trigger  
Pad Logic  
To XT2  
P5REN.2  
DVSS  
DVCC  
0
1
1
P5DIR.2  
0
1
P5OUT.2  
0
1
Module X OUT  
P5.2/XT2IN  
P5DS.2  
0: Low drive  
1: High drive  
P5SEL.2  
P5IN.2  
Bus  
Keeper  
EN  
D
Module X IN  
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Port P5, P5.3, Input/Output With Schmitt Trigger  
Pad Logic  
To XT2  
P5REN.3  
DVSS  
DVCC  
0
1
1
P5DIR.3  
0
1
P5OUT.3  
0
1
Module X OUT  
P5.3/XT2OUT  
P5DS.3  
0: Low drive  
1: High drive  
P5SEL.3  
P5IN.3  
Bus  
Keeper  
EN  
D
Module X IN  
Table 53. Port P5 (P5.2, P5.3) Pin Functions  
CONTROL BITS/SIGNALS(1)  
PIN NAME (P5.x)  
x
FUNCTION  
P5DIR.x  
P5SEL.2  
P5SEL.3  
XT2BYPASS  
P5.2/XT2IN  
2
P5.2 (I/O)  
I: 0; O: 1  
0
1
1
0
1
1
X
X
X
X
X
X
X
0
1
X
0
1
XT2IN crystal mode(2)  
XT2IN bypass mode(2)  
P5.3 (I/O)  
XT2OUT crystal mode(3)  
P5.3 (I/O)(3)  
X
X
P5.3/XT2OUT  
3
I: 0; O: 1  
X
X
(1) X = Don't care  
(2) Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal  
mode or bypass mode.  
(3) Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as  
general-purpose I/O.  
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Port P5, P5.4 and P5.5 Input/Output With Schmitt Trigger  
Pad Logic  
to XT1  
P5REN.4  
DVSS  
DVCC  
0
1
1
P5DIR.4  
0
1
P5OUT.4  
0
1
Module X OUT  
P5.4/XIN  
P5DS.4  
0: Low drive  
1: High drive  
P5SEL.4  
P5IN.4  
Bus  
Keeper  
EN  
D
Module X IN  
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Pad Logic  
to XT1  
P5REN.5  
DVSS  
DVCC  
0
1
1
P5DIR.5  
0
1
P5OUT.5  
0
1
Module X OUT  
P5.5/XOUT  
P5DS.5  
0: Low drive  
1: High drive  
P5SEL.5  
XT1BYPASS  
P5IN.5  
Bus  
Keeper  
EN  
D
Module X IN  
Table 54. Port P5 (P5.4 and P5.5) Pin Functions  
CONTROL BITS/SIGNALS(1)  
PIN NAME (P7.x)  
P5.4/XIN  
x
FUNCTION  
P5DIR.x  
P5SEL.4  
P5SEL.5  
XT1BYPASS  
4
P5.4 (I/O)  
I: 0; O: 1  
0
1
1
0
1
1
X
X
X
X
X
X
X
0
1
X
0
1
XIN crystal mode(2)  
XIN bypass mode(2)  
P5.5 (I/O)  
XOUT crystal mode(3)  
P5.5 (I/O)(3)  
X
X
P5.5/XOUT  
5
I: 0; O: 1  
X
X
(1) X = Don't care  
(2) Setting P5SEL.4 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P5.4 is configured for crystal  
mode or bypass mode.  
(3) Setting P5SEL.4 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.5 can be used as  
general-purpose I/O.  
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Port P5, P5.6 to P5.7, Input/Output With Schmitt Trigger  
Pad Logic  
P5REN.x  
DVSS  
DVCC  
0
1
1
P5DIR.x  
0
1
Direction  
0: Input  
1: Output  
From Module  
P5OUT.x  
0
1
P5DS.x  
0: Low drive  
1: High drive  
P5.6/TB0.0  
P5.7/TB0.1  
P5SEL.x  
P5IN.x  
EN  
D
To module  
Table 55. Port P5 (P5.6 to P5.7) Pin Functions  
CONTROL BITS/SIGNALS  
PIN NAME (P5.x)  
x
FUNCTION  
P5DIR.x  
P5SEL.x  
P5.6/TB0.0(1)  
6
P5.6 (I/O)  
I: 0; O: 1  
0
1
1
1
1
TB0.CCI0A  
TB0.0  
0
1
0
1
P5.7/TB0.1(1)  
7
TB0.CCI1A  
TB0.1  
(1) 'F5529, 'F5527, 'F5525, 'F5521, 'F5519, 'F5517, 'F5515 devices only.  
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Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger  
Pad Logic  
to ADC12  
(n/a MSPF430F551x)  
INCHx = x  
(n/a MSPF430F551x)  
to Comparator_B  
from Comparator_B  
CBPD.x  
P6REN.x  
DVSS  
DVCC  
0
1
1
P6DIR.x  
0
1
Direction  
0: Input  
1: Output  
P6OUT.x  
0
1
From module  
P6.0/CB0/(A0)  
P6.1/CB1/(A1)  
P6.2/CB2/(A2)  
P6.3/CB3/(A3)  
P6.4/CB4/(A4)  
P6.5/CB5/(A5)  
P6.6/CB6/(A6)  
P6.7/CB7/(A7)  
P6DS.x  
0: Low drive  
1: High drive  
P6SEL.x  
P6IN.x  
Bus  
Keeper  
EN  
D
To module  
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Table 56. Port P6 (P6.0 to P6.7) Pin Functions  
CONTROL BITS/SIGNALS  
PIN NAME (P6.x)  
P6.0/CB0/(A0)  
x
FUNCTION  
P6DIR.x  
P6SEL.x  
CBPD  
0
0
P6.0 (I/O)  
I: 0; O: 1  
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
A0 (only MSP430F552x)  
CB0(1)  
X
X
1
X
P6.1/CB1/(A1)  
P6.2/CB2/(A2)  
P6.3/CB3/(A3)  
P6.4/CB4/(A4)  
P6.5/CB5/(A5)  
P6.6/CB6/(A6)  
P6.7/CB7/(A7)  
1
2
3
4
5
6
7
P6.1 (I/O)  
I: 0; O: 1  
0
A1 (only MSP430F552x)  
CB1(1)  
X
X
1
X
P6.2 (I/O)  
I: 0; O: 1  
0
A2 (only MSP430F552x)  
CB2(1)  
X
X
1
X
P6.3 (I/O)  
I: 0; O: 1  
0
A3 (only MSP430F552x)  
CB3(1)  
X
X
1
X
P6.4 (I/O)  
I: 0; O: 1  
0
A4 (only MSP430F552x)  
CB4(1)  
X
X
1
X
P6.5 (I/O)  
I: 0; O: 1  
0
A5 (only MSP430F552x)  
CB5(1)  
X
X
1
X
P6.6 (I/O)  
I: 0; O: 1  
0
A6 (only MSP430F552x)  
CB6(1)  
X
X
1
X
P6.7 (I/O)  
I: 0; O: 1  
0
A7 (only MSP430F552x)  
CB7(1)  
X
X
X
1
(1) Setting the CBPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying  
analog signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input  
buffer for that pin, regardless of the state of the associated CBPD.x bit.  
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Port P7, P7.0 to P7.3, Input/Output With Schmitt Trigger  
Pad Logic  
to ADC12  
(n/a MSPF430F551x)  
INCHx = x  
(n/a MSPF430F551x)  
to Comparator_B  
from Comparator_B  
CBPD.x  
P7REN.x  
DVSS  
DVCC  
0
1
1
P7DIR.x  
0
1
Direction  
0: Input  
1: Output  
P7OUT.x  
0
1
From module  
P7.0/CB8/(A12)  
P7.1/CB9/(A13)  
P7.2/CB10/(A14)  
P7.3/CB11/(A15)  
P7DS.x  
0: Low drive  
1: High drive  
P7SEL.x  
P7IN.x  
Bus  
Keeper  
EN  
D
To module  
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Table 57. Port P7 (P7.0 to P7.3) Pin Functions  
CONTROL BITS/SIGNALS  
PIN NAME (P7.x)  
x
FUNCTION  
P7DIR.x  
P7SEL.x  
CBPD  
(1)  
P7.0/CB8/(A12)  
0
P7.0 (I/O)  
I: 0; O: 1  
0
1
X
0
1
X
0
1
X
0
1
X
0
X
1
0
X
1
0
X
1
0
X
1
(2)  
A12  
X
CB8(3) (1)  
X
P7.1/CB9/(A13)  
P7.2/CB10/(A14)  
P7.3/CB11/(A15)  
1
2
3
P7.1 (I/O)(1)  
I: 0; O: 1  
(2)  
A13  
X
CB9(3) (1)  
P7.2 (I/O)(1)  
A14(2)  
CB10(3) (1)  
P7.3 (I/O)(1)  
A15(2)  
X
I: 0; O: 1  
X
X
I: 0; O: 1  
X
X
CB11(3) (1)  
(1) 'F5529, 'F5527, 'F5525, 'F5521, 'F5519, 'F5517, 'F5515 devices only.  
(2) 'F5529, 'F5527, 'F5525, 'F5521 devices only.  
(3) Setting the CBPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying  
analog signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input  
buffer for that pin, regardless of the state of the associated CBPD.x bit.  
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Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger  
Pad Logic  
P7REN.x  
DVSS  
DVCC  
0
1
1
P7DIR.x  
0
1
Direction  
0: Input  
1: Output  
From module  
P7OUT.x  
0
1
P7DS.x  
0: Low drive  
1: High drive  
P7.4/TB0.2  
P7.5/TB0.3  
P7.6/TB0.4  
P7.7/TB0CLK/MCLK  
P7SEL.x  
P7IN.x  
EN  
D
To module  
Table 58. Port P7 (P7.4 to P7.7) Pin Functions  
CONTROL BITS/SIGNALS  
PIN NAME (P7.x)  
P7.4/TB0.2(1)  
x
FUNCTION  
P7DIR.x  
P7SEL.x  
4
P7.4 (I/O)  
I: 0; O: 1  
0
1
1
0
1
1
0
1
1
0
1
1
TB0.CCI2A  
TB0.2  
0
1
P7.5/TB0.3(1)  
5
6
7
P7.5 (I/O)  
TB0.CCI3A  
TB0.3  
I: 0; O: 1  
0
1
P7.6/TB0.4(1)  
P7.6 (I/O)  
TB0.CCI4A  
TB0.4  
I: 0; O: 1  
0
1
P7.7/TB0CLK/MCLK(1)  
P7.7 (I/O)  
TB0CLK  
MCLK  
I: 0; O: 1  
0
1
(1) 'F5529, 'F5527, 'F5525, 'F5521, 'F5519, 'F5517, 'F5515 devices only.  
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Port P8, P8.0 to P8.2, Input/Output With Schmitt Trigger  
Pad Logic  
P8REN.x  
DVSS  
DVCC  
0
1
1
P8DIR.x  
0
1
Direction  
0: Input  
1: Output  
from Port Mapping Control  
P8OUT.x  
0
1
from Port Mapping Control  
P8.0  
P8.1  
P8.2  
P8DS.x  
0: Low drive  
1: High drive  
P8SEL.x  
P8IN.x  
EN  
D
to Port Mapping Control  
Table 59. Port P8 (P8.0 to P8.2) Pin Functions  
CONTROL BITS/SIGNALS  
PIN NAME (P8.x)  
x
FUNCTION  
P8DIR.x  
I: 0; O: 1  
I: 0; O: 1  
I: 0; O: 1  
P8SEL.x  
P8.0(1)  
P8.1(1)  
P8.2(1)  
0
1
2
P8.0(I/O)  
0
0
0
P8.1(I/O)  
P8.2(I/O)  
(1) 'F5529, 'F5527, 'F5525, 'F5521, 'F5519, 'F5517, 'F5515 devices only.  
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Port PU.0/DP, PU.1/DM, PUR USB Ports  
PUSEL  
VUSB  
VSSU  
Pad Logic  
PUDIR  
0
1
USB output enable  
PUOUT0  
0
1
PU.0/  
DP  
USB DP output  
PUIN0  
USB DP input  
.
PUIN1  
USB DM input  
PUOUT0  
0
1
PU.1/  
DM  
USB DM output  
VUSB  
VSSU  
Pad Logic  
PUREN  
PUR  
“1”  
PUSEL  
PURIN  
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Table 60. Port PU.0/DP, PU.1/DM Output Functions  
CONTROL BITS  
PUDIR PUOUT1  
PIN NAME  
PU.1/DM  
FUNCTION  
PUSEL  
PUOUT0  
PU.0/DP  
0
0
0
0
0
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Hi-Z  
Hi-Z  
Outputs off  
0
0
1
1
0
1
0
1
Outputs enabled  
Outputs enabled  
Outputs enabled  
Outputs enabled  
Direction set by  
USB module  
1
X
X
X
DM  
DP  
Table 61. Port PUR Input Functions  
CONTROL BITS  
FUNCTION  
PUSEL  
0
PUREN  
0
Input disabled  
Pull up disabled  
Input disabled  
Pull up enabled  
0
1
1
1
0
1
Input enabled  
Pull up disabled  
Input enabled  
Pull up enabled  
96  
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Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output  
Pad Logic  
PJREN.0  
0
1
DVSS  
DVCC  
1
PJDIR.0  
DVCC  
0
1
PJOUT.0  
0
1
From JTAG  
PJ.0/TDO  
PJDS.0  
0: Low drive  
1: High drive  
From JTAG  
PJIN.0  
EN  
D
Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output  
Pad Logic  
PJREN.x  
0
1
DVSS  
DVCC  
1
PJDIR.x  
DVSS  
0
1
PJOUT.x  
0
1
From JTAG  
PJ.1/TDI/TCLK  
PJ.2/TMS  
PJ.3/TCK  
PJDS.x  
0: Low drive  
1: High drive  
From JTAG  
PJIN.x  
EN  
D
To JTAG  
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Table 62. Port PJ (PJ.0 to PJ.3) Pin Functions  
CONTROL BITS/  
SIGNALS(1)  
PIN NAME (PJ.x)  
PJ.0/TDO  
x
FUNCTION  
PJDIR.x  
0
PJ.0 (I/O)(2)  
TDO(3)  
I: 0; O: 1  
X
PJ.1/TDI/TCLK  
PJ.2/TMS  
1
2
3
PJ.1 (I/O)(2)  
TDI/TCLK(3) (4)  
PJ.2 (I/O)(2)  
TMS(3) (4)  
PJ.3 (I/O)(2)  
TCK(3) (4)  
I: 0; O: 1  
X
I: 0; O: 1  
X
PJ.3/TCK  
I: 0; O: 1  
X
(1) X = Don't care  
(2) Default condition  
(3) The pin direction is controlled by the JTAG module.  
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.  
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DEVICE DESCRIPTORS (TLV)  
Table 63 and Table 64 list the complete contents of the device descriptor tag-length-value (TLV) structure for  
each device type.  
Table 63. 'F552x Device Descriptor Table(1)  
'F5529  
Value  
06h  
'F5528  
Value  
06h  
'F5527  
Value  
06h  
'F5526  
Value  
06h  
'F5525  
Value  
06h  
'F5524  
Value  
06h  
'F5522  
Value  
06h  
'F5521  
Value  
06h  
Size  
bytes  
Description  
Address  
Info Block  
Info length  
CRC length  
01A00h  
01A01h  
01A02h  
01A04h  
01A05h  
01A06h  
01A07h  
01A08h  
01A09h  
01A0Ah  
01A0Eh  
01A10h  
01A12h  
1
1
2
1
1
1
1
1
1
4
2
2
2
06h  
06h  
06h  
06h  
06h  
06h  
06h  
06h  
CRC value  
per unit  
55h  
per unit  
55h  
per unit  
55h  
per unit  
55h  
per unit  
55h  
per unit  
55h  
per unit  
55h  
per unit  
55h  
Device ID  
Device ID  
29h  
28h  
27h  
26h  
25h  
24h  
22h  
21h  
Hardware revision  
Firmware revision  
Die Record Tag  
Die Record length  
Lot/Wafer ID  
Die X position  
Die Y position  
Test results  
per unit  
per unit  
08h  
per unit  
per unit  
08h  
per unit  
per unit  
08h  
per unit  
per unit  
08h  
per unit  
per unit  
08h  
per unit  
per unit  
08h  
per unit  
per unit  
08h  
per unit  
per unit  
08h  
Die Record  
0Ah  
0Ah  
0Ah  
0Ah  
0Ah  
0Ah  
0Ah  
0Ah  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
ADC12  
Calibration  
ADC12 Calibration Tag  
01A14h  
1
11h  
11h  
11h  
11h  
11h  
11h  
11h  
11h  
ADC12 Calibration length  
ADC Gain Factor  
ADC Offset  
01A15h  
01A16h  
01A18h  
1
2
2
10h  
10h  
10h  
10h  
10h  
10h  
10h  
10h  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
ADC 1.5-V Reference  
Temp. Sensor 30°C  
01A1Ah  
01A1Ch  
01A1Eh  
01A20h  
01A22h  
01A24h  
2
2
2
2
2
2
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
ADC 1.5-V Reference  
Temp. Sensor 85°C  
ADC 2.0-V Reference  
Temp. Sensor 30°C  
ADC 2.0-V Reference  
Temp. Sensor 85°C  
ADC 2.5-V Reference  
Temp. Sensor 30°C  
ADC 2.5-V Reference  
Temp. Sensor 85°C  
REF  
Calibration  
REF Calibration Tag  
01A26h  
01A27h  
01A28h  
1
1
2
12h  
06h  
12h  
06h  
12h  
06h  
12h  
06h  
12h  
06h  
12h  
06h  
12h  
06h  
12h  
06h  
REF Calibration length  
REF 1.5-V Reference  
Factor  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
REF 2.0-V Reference  
Factor  
01A2Ah  
01A2Ch  
01A2Eh  
01A2Fh  
2
2
1
1
2
2
2
per unit  
per unit  
02h  
per unit  
per unit  
02h  
per unit  
per unit  
02h  
per unit  
per unit  
02h  
per unit  
per unit  
02h  
per unit  
per unit  
02h  
per unit  
per unit  
02h  
per unit  
per unit  
02h  
REF 2.5-V Reference  
Factor  
Peripheral  
Descriptor  
Peripheral Descriptor Tag  
Peripheral Descriptor  
Length  
63h  
61h  
65h  
63h  
63h  
61h  
61h  
64h  
08h  
8Ah  
08h  
8Ah  
08h  
8Ah  
08h  
8Ah  
08h  
8Ah  
08h  
8Ah  
08h  
8Ah  
08h  
8Ah  
Memory 1  
Memory 2  
Memory 3  
0Ch  
86h  
0Ch  
86h  
0Ch  
86h  
0Ch  
86h  
0Ch  
86h  
0Ch  
86h  
0Ch  
86h  
0Ch  
86h  
0Eh  
2Ah  
0Eh  
2Ah  
0Eh  
2Ah  
0Eh  
2Ah  
0Eh  
2Ah  
0Eh  
2Ah  
0Eh  
2Ah  
0Eh  
2Ah  
(1) NA = Not applicable, blank = unused and reads FFh.  
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Table 63. 'F552x Device Descriptor Table (1) (continued)  
'F5529  
Value  
'F5528  
Value  
'F5527  
Value  
'F5526  
Value  
'F5525  
Value  
'F5524  
Value  
'F5522  
Value  
'F5521  
Value  
Size  
bytes  
Description  
Address  
12h  
2Eh  
12h  
2Eh  
12h  
2Dh  
12h  
2Dh  
12h  
2Ch  
12h  
2Ch  
12h  
2Eh  
12h  
2Dh  
Memory 4  
Memory 5  
Memory 6  
2
2
22h  
96h  
22h  
96h  
2Ah  
22h  
2Ah  
22h  
22h  
94h  
22h  
94h  
40h  
92h  
2Ah  
40h  
95h  
92h  
95h  
92h  
1/2  
N/A  
N/A  
N/A  
N/A  
N/A  
92h  
delimiter  
1
1
00h  
21h  
00h  
20h  
00h  
21h  
00h  
20h  
00h  
21h  
00h  
20h  
00h  
20h  
00h  
21h  
Peripheral count  
00h  
23h  
00h  
23h  
00h  
23h  
00h  
23h  
00h  
23h  
00h  
23h  
00h  
23h  
00h  
23h  
MSP430CPUXV2  
JTAG  
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
00h  
09h  
00h  
09h  
00h  
09h  
00h  
09h  
00h  
09h  
00h  
09h  
00h  
09h  
00h  
09h  
00h  
0Fh  
00h  
0Fh  
00h  
0Fh  
00h  
0Fh  
00h  
0Fh  
00h  
0Fh  
00h  
0Fh  
00h  
0Fh  
SBW  
00h  
05h  
00h  
05h  
00h  
05h  
00h  
05h  
00h  
05h  
00h  
05h  
00h  
05h  
00h  
05h  
EEM-L  
TI BSL  
SFR  
00h  
FCh  
00h  
FCh  
00h  
FCh  
00h  
FCh  
00h  
FCh  
00h  
FCh  
00h  
FCh  
00h  
FCh  
10h  
41h  
10h  
41h  
10h  
41h  
10h  
41h  
10h  
41h  
10h  
41h  
10h  
41h  
10h  
41h  
02h  
30h  
02h  
30h  
02h  
30h  
02h  
30h  
02h  
30h  
02h  
30h  
02h  
30h  
02h  
30h  
PMM  
02h  
38h  
02h  
38h  
02h  
38h  
02h  
38h  
02h  
38h  
02h  
38h  
02h  
38h  
02h  
38h  
FCTL  
01h  
3Ch  
01h  
3Ch  
01h  
3Ch  
01h  
3Ch  
01h  
3Ch  
01h  
3Ch  
01h  
3Ch  
01h  
3Ch  
CRC16  
CRC16_RB  
RAMCTL  
WDT_A  
UCS  
00h  
3Dh  
00h  
3Dh  
00h  
3Dh  
00h  
3Dh  
00h  
3Dh  
00h  
3Dh  
00h  
3Dh  
00h  
3Dh  
00h  
44h  
00h  
44h  
00h  
44h  
00h  
44h  
00h  
44h  
00h  
44h  
00h  
44h  
00h  
44h  
00h  
40h  
00h  
40h  
00h  
40h  
00h  
40h  
00h  
40h  
00h  
40h  
00h  
40h  
00h  
40h  
01h  
48h  
01h  
48h  
01h  
48h  
01h  
48h  
01h  
48h  
01h  
48h  
01h  
48h  
01h  
48h  
02h  
42h  
02h  
42h  
02h  
42h  
02h  
42h  
02h  
42h  
02h  
42h  
02h  
42h  
02h  
42h  
SYS  
03h  
A0h  
03h  
A0h  
03h  
A0h  
03h  
A0h  
03h  
A0h  
03h  
A0h  
03h  
A0h  
03h  
A0h  
REF  
01h  
10h  
01h  
10h  
01h  
10h  
01h  
10h  
01h  
10h  
01h  
10h  
01h  
10h  
01h  
10h  
Port Mapping  
Port 1/2  
Port 3/4  
Port 5/6  
Port 7/8  
JTAG  
04h  
51h  
04h  
51h  
04h  
51h  
04h  
51h  
04h  
51h  
04h  
51h  
04h  
51h  
04h  
51h  
02h  
52h  
02h  
52h  
02h  
52h  
02h  
52h  
02h  
52h  
02h  
52h  
02h  
52h  
02h  
52h  
02h  
53h  
02h  
53h  
02h  
53h  
02h  
53h  
02h  
53h  
02h  
53h  
02h  
53h  
02h  
53h  
02h  
54h  
02h  
54h  
02h  
54h  
02h  
54h  
N/A  
N/A  
N/A  
N/A  
0Ch  
5Fh  
0Eh  
5Fh  
0Ch  
5Fh  
0Eh  
5Fh  
0Ch  
5Fh  
0Eh  
5Fh  
0Eh  
5Fh  
0Ch  
5Fh  
02h  
62h  
02h  
62h  
02h  
62h  
02h  
62h  
02h  
62h  
02h  
62h  
02h  
62h  
02h  
62h  
TA0  
04h  
61h  
04h  
61h  
04h  
61h  
04h  
61h  
04h  
61h  
04h  
61h  
04h  
61h  
04h  
61h  
TA1  
04h  
67h  
04h  
67h  
04h  
67h  
04h  
67h  
04h  
67h  
04h  
67h  
04h  
67h  
04h  
67h  
TB0  
04h  
61h  
04h  
61h  
04h  
61h  
04h  
61h  
04h  
61h  
04h  
61h  
04h  
61h  
04h  
61h  
TA2  
0Ah  
68h  
0Ah  
68h  
0Ah  
68h  
0Ah  
68h  
0Ah  
68h  
0Ah  
68h  
0Ah  
68h  
0Ah  
68h  
RTC  
100  
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SLAS590D –OCTOBER 2009–REVISED APRIL 2010  
Table 63. 'F552x Device Descriptor Table (1) (continued)  
'F5529  
Value  
'F5528  
Value  
'F5527  
Value  
'F5526  
Value  
'F5525  
Value  
'F5524  
Value  
'F5522  
Value  
'F5521  
Value  
Size  
bytes  
Description  
Address  
02h  
85h  
02h  
85h  
02h  
85h  
02h  
85h  
02h  
85h  
02h  
85h  
02h  
85h  
02h  
85h  
MPY32  
DMA-3  
2
2
2
2
2
2
2
04h  
47h  
04h  
47h  
04h  
47h  
04h  
47h  
04h  
47h  
04h  
47h  
04h  
47h  
04h  
47h  
0Ch  
90h  
0Ch  
90h  
0Ch  
90h  
0Ch  
90h  
0Ch  
90h  
0Ch  
90h  
0Ch  
90h  
0Ch  
90h  
USCI_A/B  
USCI_A/B  
ADC12_A  
COMP_B  
USB  
04h  
90h  
04h  
90h  
04h  
90h  
04h  
90h  
04h  
90h  
04h  
90h  
04h  
90h  
04h  
90h  
10h  
D1h  
10h  
D1h  
10h  
D1h  
10h  
D1h  
10h  
D1h  
10h  
D1h  
10h  
D1h  
10h  
D1h  
1Ch  
A8h  
1Ch  
A8h  
1Ch  
A8h  
1Ch  
A8h  
1Ch  
A8h  
1Ch  
A8h  
1Ch  
A8h  
1Ch  
A8h  
04h  
98h  
04h  
98h  
04h  
98h  
04h  
98h  
04h  
98h  
04h  
98h  
04h  
98h  
04h  
98h  
Interrupts  
COMP_B  
TB0.CCIFG0  
TB0.CCIFG1..6  
WDTIFG  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A8h  
64h  
65h  
40h  
90h  
91h  
D0h  
60h  
61h  
98h  
46h  
62h  
63h  
50h  
92h  
93h  
66h  
67h  
51h  
68h  
00h  
A8h  
64h  
65h  
40h  
90h  
91h  
D0h  
60h  
61h  
98h  
46h  
62h  
63h  
50h  
92h  
93h  
66h  
67h  
51h  
68h  
00h  
A8h  
64h  
65h  
40h  
90h  
91h  
D0h  
60h  
61h  
98h  
46h  
62h  
63h  
50h  
92h  
93h  
66h  
67h  
51h  
68h  
00h  
A8h  
64h  
65h  
40h  
90h  
91h  
D0h  
60h  
61h  
98h  
46h  
62h  
63h  
50h  
92h  
93h  
66h  
67h  
51h  
68h  
00h  
A8h  
64h  
65h  
40h  
90h  
91h  
D0h  
60h  
61h  
98h  
46h  
62h  
63h  
50h  
92h  
93h  
66h  
67h  
51h  
68h  
00h  
A8h  
64h  
65h  
40h  
90h  
91h  
D0h  
60h  
61h  
98h  
46h  
62h  
63h  
50h  
92h  
93h  
66h  
67h  
51h  
68h  
00h  
A8h  
64h  
65h  
40h  
90h  
91h  
D0h  
60h  
61h  
98h  
46h  
62h  
63h  
50h  
92h  
93h  
66h  
67h  
51h  
68h  
00h  
A8h  
64h  
65h  
40h  
90h  
91h  
D0h  
60h  
61h  
98h  
46h  
62h  
63h  
50h  
92h  
93h  
66h  
67h  
51h  
68h  
00h  
USCI_A0  
USCI_B0  
ADC12_A  
TA0.CCIFG0  
TA0.CCIFG1..4  
USB  
DMA  
TA1.CCIFG0  
TA1.CCIFG1..2  
P1  
USCI_A1  
USCI_B1  
TA1.CCIFG0  
TA1.CCIFG1..2  
P2  
RTC_A  
delimiter  
Table 64. 'F551x Device Descriptor Table(1)  
'F5519  
Value  
55h  
'F5517  
Value  
55h  
'F5515  
'F5514  
Value  
55h  
'F5513  
Size  
bytes  
Description  
Address  
Value  
55h  
Value  
55h  
Info Block  
Info length  
CRC length  
01A00h  
01A01h  
01A02h  
01A04h  
01A05h  
01A06h  
01A07h  
01A08h  
01A09h  
01A0Ah  
01A0Eh  
1
1
2
1
1
1
1
1
1
4
2
19h  
17h  
15h  
14h  
13h  
CRC value  
per unit  
22h  
per unit  
21h  
per unit  
55h  
per unit  
55h  
per unit  
20h  
Device ID  
Device ID  
80h  
80h  
15h  
14h  
80h  
Hardware revision  
Firmware revision  
Die Record Tag  
Die Record length  
Lot/Wafer ID  
Die X position  
per unit  
per unit  
08h  
per unit  
per unit  
08h  
per unit  
per unit  
08h  
per unit  
per unit  
08h  
per unit  
per unit  
08h  
Die Record  
0Ah  
0Ah  
0Ah  
0Ah  
0Ah  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
(1) NA = Not applicable, blank = unused and reads FFh.  
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MSP430F551x  
MSP430F552x  
SLAS590D –OCTOBER 2009–REVISED APRIL 2010  
www.ti.com  
Table 64. 'F551x Device Descriptor Table (1) (continued)  
'F5519  
Value  
'F5517  
Value  
'F5515  
Value  
'F5514  
Value  
'F5513  
Value  
Size  
bytes  
Description  
Address  
Die Y position  
Test results  
01A10h  
01A12h  
2
2
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
per unit  
ADC12  
Calibration  
ADC12 Calibration  
Tag  
01A14h  
01A15h  
1
1
05h  
10h  
05h  
10h  
11h  
10h  
11h  
10h  
05h  
10h  
ADC12 Calibration  
length  
ADC Gain Factor  
ADC Offset  
01A16h  
01A18h  
2
2
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
ADC 1.5-V  
Reference  
Temp. Sensor  
30°C  
01A1Ah  
01A1Ch  
01A1Eh  
01A20h  
01A22h  
01A24h  
2
2
2
2
2
2
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
blank  
ADC 1.5-V  
Reference  
Temp. Sensor  
85°C  
ADC 2.0-V  
Reference  
Temp. Sensor  
30°C  
ADC 2.0-V  
Reference  
Temp. Sensor  
85°C  
ADC 2.5-V  
Reference  
Temp. Sensor  
30°C  
ADC 2.5-V  
Reference  
Temp. Sensor  
85°C  
REF  
Calibration  
REF Calibration  
Tag  
01A26h  
01A27h  
01A28h  
01A2Ah  
01A2Ch  
01A2Eh  
01A2Fh  
1
1
2
2
2
1
1
2
2
2
2
2
12h  
06h  
12h  
06h  
12h  
06h  
12h  
06h  
12h  
06h  
REF Calibration  
length  
REF 1.5-V  
Reference Factor  
per unit  
per unit  
per unit  
02h  
per unit  
per unit  
per unit  
02h  
per unit  
per unit  
per unit  
02h  
per unit  
per unit  
per unit  
02h  
per unit  
per unit  
per unit  
02h  
REF 2.0-V  
Reference Factor  
REF 2.5-V  
Reference Factor  
Peripheral  
Descriptor  
Peripheral  
Descriptor Tag  
Peripheral  
Descriptor Length  
61h  
63h  
61h  
5Fh  
5Fh  
08h  
8Ah  
08h  
8Ah  
08h  
8Ah  
08h  
8Ah  
08h  
8Ah  
Memory 1  
Memory 2  
Memory 3  
Memory 4  
Memory 5  
0Ch  
86h  
0Ch  
86h  
0Ch  
86h  
0Ch  
86h  
0Ch  
86h  
0Eh  
2Ah  
0Eh  
2Ah  
0Eh  
2Ah  
0Eh  
2Ah  
0Eh  
2Ah  
12h  
2Eh  
12h  
2Dh  
12h  
2Ch  
12h  
2Ch  
12h  
2Ch  
22h  
96h  
2Ah  
22h  
22h  
94h  
22h  
94h  
40h  
92h  
102  
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Copyright © 2009–2010, Texas Instruments Incorporated  
MSP430F551x  
MSP430F552x  
www.ti.com  
SLAS590D –OCTOBER 2009–REVISED APRIL 2010  
Table 64. 'F551x Device Descriptor Table (1) (continued)  
'F5519  
Value  
'F5517  
Value  
'F5515  
Value  
'F5514  
Value  
'F5513  
Value  
Size  
bytes  
Description  
Address  
95h  
92h  
Memory 6  
1/2  
N/A  
N/A  
N/A  
N/A  
delimiter  
1
1
00h  
20h  
00h  
20h  
00h  
20h  
00h  
1Fh  
00h  
1Fh  
Peripheral count  
00h  
23h  
00h  
23h  
00h  
23h  
00h  
23h  
00h  
23h  
MSP430CPUXV2  
JTAG  
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
00h  
09h  
00h  
09h  
00h  
09h  
00h  
09h  
00h  
09h  
00h  
0Fh  
00h  
0Fh  
00h  
0Fh  
00h  
0Fh  
00h  
0Fh  
SBW  
00h  
05h  
00h  
05h  
00h  
05h  
00h  
05h  
00h  
05h  
EEM-L  
TI BSL  
SFR  
00h  
FCh  
00h  
FCh  
00h  
FCh  
00h  
FCh  
00h  
FCh  
10h  
41h  
10h  
41h  
10h  
41h  
10h  
41h  
10h  
41h  
02h  
30h  
02h  
30h  
02h  
30h  
02h  
30h  
02h  
30h  
PMM  
02h  
38h  
02h  
38h  
02h  
38h  
02h  
38h  
02h  
38h  
FCTL  
01h  
3Ch  
01h  
3Ch  
01h  
3Ch  
01h  
3Ch  
01h  
3Ch  
CRC16  
CRC16_RB  
RAMCTL  
WDT_A  
UCS  
00h  
3Dh  
00h  
3Dh  
00h  
3Dh  
00h  
3Dh  
00h  
3Dh  
00h  
44h  
00h  
44h  
00h  
44h  
00h  
44h  
00h  
44h  
00h  
40h  
00h  
40h  
00h  
40h  
00h  
40h  
00h  
40h  
01h  
48h  
01h  
48h  
01h  
48h  
01h  
48h  
01h  
48h  
02h  
42h  
02h  
42h  
02h  
42h  
02h  
42h  
02h  
42h  
SYS  
03h  
A0h  
03h  
A0h  
03h  
A0h  
03h  
A0h  
03h  
A0h  
REF  
01h  
10h  
01h  
10h  
01h  
10h  
01h  
10h  
01h  
10h  
Port Mapping  
Port 1/2  
Port 3/4  
Port 5/6  
Port 7/8  
JTAG  
04h  
51h  
04h  
51h  
04h  
51h  
04h  
51h  
04h  
51h  
02h  
52h  
02h  
52h  
02h  
52h  
02h  
52h  
02h  
52h  
02h  
53h  
02h  
53h  
02h  
53h  
02h  
53h  
02h  
53h  
02h  
54h  
02h  
54h  
02h  
54h  
N/A  
N/A  
0Ch  
5Fh  
0Ch  
5Fh  
0Ch  
5Fh  
0Eh  
5Fh  
0Eh  
5Fh  
02h  
62h  
02h  
62h  
02h  
62h  
02h  
62h  
02h  
62h  
TA0  
04h  
61h  
04h  
61h  
04h  
61h  
04h  
61h  
04h  
61h  
TA1  
04h  
67h  
04h  
67h  
04h  
67h  
04h  
67h  
04h  
67h  
TB0  
04h  
61h  
04h  
61h  
04h  
61h  
04h  
61h  
04h  
61h  
TA2  
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MSP430F552x  
SLAS590D –OCTOBER 2009–REVISED APRIL 2010  
www.ti.com  
Table 64. 'F551x Device Descriptor Table (1) (continued)  
'F5519  
Value  
'F5517  
Value  
'F5515  
Value  
'F5514  
Value  
'F5513  
Value  
Size  
bytes  
Description  
Address  
0Ah  
68h  
0Ah  
68h  
0Ah  
68h  
0Ah  
68h  
0Ah  
68h  
RTC  
MPY32  
DMA-3  
2
2
2
2
02h  
85h  
02h  
85h  
02h  
85h  
02h  
85h  
02h  
85h  
04h  
47h  
04h  
47h  
04h  
47h  
04h  
47h  
04h  
47h  
0Ch  
90h  
0Ch  
90h  
0Ch  
90h  
0Ch  
90h  
0Ch  
90h  
USCI_A/B  
04h  
90h  
04h  
90h  
04h  
90h  
04h  
90h  
04h  
90h  
USCI_A/B  
ADC12_A  
COMP_B  
2
2
2
N/A  
N/A  
N/A  
N/A  
N/A  
2Ch  
A8h  
2Ch  
A8h  
2Ch  
A8h  
2Ch  
A8h  
2Ch  
A8h  
04h  
98h  
04h  
98h  
04h  
98h  
04h  
98h  
04h  
98h  
USB  
2
Interrupts  
COMP_B  
TB0.CCIFG0  
TB0.CCIFG1..6  
WDTIFG  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A8h  
64h  
65h  
40h  
90h  
91h  
01h  
60h  
61h  
98h  
46h  
62h  
63h  
50h  
92h  
93h  
66h  
67h  
51h  
68h  
00h  
A8h  
64h  
65h  
40h  
90h  
91h  
01h  
60h  
61h  
98h  
46h  
62h  
63h  
50h  
92h  
93h  
66h  
67h  
51h  
68h  
00h  
A8h  
64h  
65h  
40h  
90h  
91h  
01h  
60h  
61h  
98h  
46h  
62h  
63h  
50h  
92h  
93h  
66h  
67h  
51h  
68h  
00h  
A8h  
64h  
65h  
40h  
90h  
91h  
01h  
60h  
61h  
98h  
46h  
62h  
63h  
50h  
92h  
93h  
66h  
67h  
51h  
68h  
00h  
A8h  
64h  
65h  
40h  
90h  
91h  
01h  
60h  
61h  
98h  
46h  
62h  
63h  
50h  
92h  
93h  
66h  
67h  
51h  
68h  
00h  
USCI_A0  
USCI_B0  
ADC12_A  
TA0.CCIFG0  
TA0.CCIFG1..4  
USB  
DMA  
TA1.CCIFG0  
TA1.CCIFG1..2  
P1  
USCI_A1  
USCI_B1  
TA1.CCIFG0  
TA1.CCIFG1..2  
P2  
RTC_A  
delimiter  
104  
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MSP430F551x  
MSP430F552x  
www.ti.com  
SLAS590D –OCTOBER 2009–REVISED APRIL 2010  
REVISION HISTORY  
REVISION  
DESCRIPTION  
SLAS590  
SLAS590A  
SLAS590B  
SLAS590C  
SLAS590D  
Limited product preview release  
Changes throughout for XMS430F5529 sampling  
Changes throughout for updated preview  
Changes throughout for updated preview  
Production data release  
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105  
PACKAGE OPTION ADDENDUM  
www.ti.com  
28-May-2010  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
MSP430F5513IRGCR  
MSP430F5513IRGCT  
MSP430F5513IZQE  
ACTIVE  
ACTIVE  
ACTIVE  
VQFN  
VQFN  
RGC  
RGC  
ZQE  
64  
64  
80  
2000  
250  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-3-260C-168 HR  
Purchase Samples  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-3-260C-168 HR  
SNAGCU Level-3-260C-168 HR  
Purchase Samples  
Purchase Samples  
BGA  
MICROSTAR  
JUNIOR  
360  
Green (RoHS  
& no Sb/Br)  
MSP430F5513IZQER  
ACTIVE  
BGA  
MICROSTAR  
JUNIOR  
ZQE  
80  
2500  
Green (RoHS  
& no Sb/Br)  
SNAGCU Level-3-260C-168 HR  
Request Free Samples  
MSP430F5514IRGCR  
MSP430F5514IRGCT  
PREVIEW  
ACTIVE  
VQFN  
VQFN  
RGC  
RGC  
64  
64  
2000  
250  
TBD  
Call TI  
Call TI  
Samples Not Available  
Request Free Samples  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-3-260C-168 HR  
MSP430F5514IZQE  
MSP430F5514IZQER  
ACTIVE  
ACTIVE  
BGA  
MICROSTAR  
JUNIOR  
ZQE  
ZQE  
80  
80  
360  
Green (RoHS  
& no Sb/Br)  
SNAGCU Level-3-260C-168 HR  
Purchase Samples  
BGA  
MICROSTAR  
JUNIOR  
2500  
Green (RoHS  
& no Sb/Br)  
SNAGCU Level-3-260C-168 HR  
Request Free Samples  
MSP430F5515IPN  
MSP430F5515IPNR  
MSP430F5517IPN  
MSP430F5517IPNR  
MSP430F5519IPN  
MSP430F5519IPNR  
MSP430F5521IPN  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
LQFP  
LQFP  
LQFP  
LQFP  
LQFP  
LQFP  
LQFP  
PN  
PN  
PN  
PN  
PN  
PN  
PN  
80  
80  
80  
80  
80  
80  
80  
119  
1000  
119  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-3-260C-168 HR  
CU NIPDAU Level-3-260C-168 HR  
CU NIPDAU Level-3-260C-168 HR  
CU NIPDAU Level-3-260C-168 HR  
CU NIPDAU Level-3-260C-168 HR  
CU NIPDAU Level-3-260C-168 HR  
CU NIPDAU Level-3-260C-168 HR  
Purchase Samples  
Request Free Samples  
Purchase Samples  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
1000  
119  
Green (RoHS  
& no Sb/Br)  
Request Free Samples  
Purchase Samples  
Green (RoHS  
& no Sb/Br)  
1000  
119  
Green (RoHS  
& no Sb/Br)  
Request Free Samples  
Purchase Samples  
Green (RoHS  
& no Sb/Br)  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
28-May-2010  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
MSP430F5521IPNR  
MSP430F5522IRGCR  
MSP430F5522IRGCT  
MSP430F5522IZQE  
LQFP  
VQFN  
VQFN  
PN  
80  
64  
64  
80  
1000  
2000  
250  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-3-260C-168 HR  
Request Free Samples  
RGC  
RGC  
ZQE  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-3-260C-168 HR  
CU NIPDAU Level-3-260C-168 HR  
SNAGCU Level-3-260C-168 HR  
Request Free Samples  
Purchase Samples  
Purchase Samples  
Green (RoHS  
& no Sb/Br)  
BGA  
360  
Green (RoHS  
& no Sb/Br)  
MICROSTAR  
JUNIOR  
MSP430F5522IZQER  
ACTIVE  
BGA  
MICROSTAR  
JUNIOR  
ZQE  
80  
2500  
Green (RoHS  
& no Sb/Br)  
SNAGCU Level-3-260C-168 HR  
Request Free Samples  
MSP430F5524IRGCR  
MSP430F5524IRGCT  
MSP430F5524IZQE  
ACTIVE  
ACTIVE  
ACTIVE  
VQFN  
RGC  
RGC  
ZQE  
64  
64  
80  
2000  
250  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-3-260C-168 HR  
CU NIPDAU Level-3-260C-168 HR  
SNAGCU Level-3-260C-168 HR  
Purchase Samples  
Request Free Samples  
Purchase Samples  
VQFN  
Green (RoHS  
& no Sb/Br)  
BGA  
MICROSTAR  
JUNIOR  
360  
Green (RoHS  
& no Sb/Br)  
MSP430F5524IZQER  
ACTIVE  
BGA  
MICROSTAR  
JUNIOR  
ZQE  
80  
2500  
Green (RoHS  
& no Sb/Br)  
SNAGCU Level-3-260C-168 HR  
Request Free Samples  
MSP430F5525IPN  
MSP430F5525IPNR  
MSP430F5526IRGCR  
MSP430F5526IRGCT  
MSP430F5526IZQE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
LQFP  
LQFP  
VQFN  
VQFN  
PN  
PN  
80  
80  
64  
64  
80  
119  
1000  
2000  
250  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-3-260C-168 HR  
CU NIPDAU Level-3-260C-168 HR  
CU NIPDAU Level-3-260C-168 HR  
CU NIPDAU Level-3-260C-168 HR  
SNAGCU Level-3-260C-168 HR  
Purchase Samples  
Request Free Samples  
Purchase Samples  
Green (RoHS  
& no Sb/Br)  
RGC  
RGC  
ZQE  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Request Free Samples  
Purchase Samples  
BGA  
MICROSTAR  
JUNIOR  
360  
Green (RoHS  
& no Sb/Br)  
MSP430F5526IZQER  
ACTIVE  
BGA  
MICROSTAR  
JUNIOR  
ZQE  
80  
2500  
Green (RoHS  
& no Sb/Br)  
SNAGCU Level-3-260C-168 HR  
Request Free Samples  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
28-May-2010  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
MSP430F5527IPN  
MSP430F5527IPNR  
MSP430F5528IRGCR  
MSP430F5528IRGCT  
MSP430F5528IZQE  
LQFP  
LQFP  
VQFN  
VQFN  
PN  
PN  
80  
80  
64  
64  
80  
119  
50  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-3-260C-168 HR  
Purchase Samples  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-3-260C-168 HR  
CU NIPDAU Level-3-260C-168 HR  
CU NIPDAU Level-3-260C-168 HR  
SNAGCU Level-3-260C-168 HR  
Request Free Samples  
Purchase Samples  
RGC  
RGC  
ZQE  
2000  
250  
360  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Request Free Samples  
Purchase Samples  
BGA  
Green (RoHS  
& no Sb/Br)  
MICROSTAR  
JUNIOR  
MSP430F5528IZQER  
ACTIVE  
BGA  
MICROSTAR  
JUNIOR  
ZQE  
80  
2500  
Green (RoHS  
& no Sb/Br)  
SNAGCU Level-3-260C-168 HR  
Request Free Samples  
MSP430F5529CY  
MSP430F5529IPN  
PREVIEW  
ACTIVE  
DIESALE  
LQFP  
Y
0
1
TBD  
Call TI  
Call TI  
Samples Not Available  
Purchase Samples  
PN  
80  
119  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-3-260C-168 HR  
MSP430F5529IPNR  
ACTIVE  
LQFP  
PN  
80  
1000  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-3-260C-168 HR  
Request Free Samples  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Addendum-Page 3  
PACKAGE OPTION ADDENDUM  
www.ti.com  
28-May-2010  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 4  
MECHANICAL DATA  
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996  
PN (S-PQFP-G80)  
PLASTIC QUAD FLATPACK  
0,27  
0,17  
0,50  
60  
M
0,08  
41  
61  
40  
0,13 NOM  
80  
21  
1
20  
Gage Plane  
9,50 TYP  
0,25  
12,20  
SQ  
11,80  
0,05 MIN  
0°–7°  
14,20  
SQ  
13,80  
0,75  
0,45  
1,45  
1,35  
Seating Plane  
0,08  
1,60 MAX  
4040135 /B 11/96  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Falls within JEDEC MS-026  
1
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IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,  
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard  
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www.ti.com/medical  
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www.ti.com/security  
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