MSP430F5630IZQW_技术文档

MSP430F563x

www.ti.com

SLAS650B –JUNE 2010–REVISED AUGUST 2011

MIXED SIGNAL MICROCONTROLLER

1

FEATURES

2

•

Low Supply Voltage Range: 1.8 V to 3.6 V

•

Two Universal Serial Communication

Interfaces

•

Ultralow Power Consumption

–

USCI_A0 and USCI_A1 Each Supporting

–

Active Mode (AM):

All System Clocks Active:

270 µA/MHz at 8 MHz, 3.0 V, Flash Program

Execution (Typical)

–

Enhanced UART Supporting

Auto-Baudrate Detection

–

IrDA Encoder and Decoder

Synchronous SPI

Standby Mode (LPM3):

Watchdog With Crystal, and Supply

Supervisor Operational, Full RAM

Retention, Fast Wake-Up:

–

USCI_B0 and USCI_B1 Each Supporting

–

I²C^TM

Synchronous SPI

1.8 µA at 2.2 V, 2.1 µA at 3.0 V (Typical)

•

Full-Speed Universal Serial Bus (USB)

–

Shutdown RTC Mode (LPM3.5):

Shutdown Mode, Active Real-Time Clock

With Crystal:

–

Integrated USB-PHY

Integrated 3.3-V/1.8-V USB Power System

Integrated USB-PLL

1.1 µA at 3.0 V (Typical)

Shutdown Mode (LPM4.5):

0.3 µA at 3.0 V (Typical)

Eight Input, Eight Output Endpoints

•

12-Bit Analog-to-Digital (A/D) Converter With

Internal Shared Reference, Sample-and-Hold,

and Autoscan Feature

•

Wake-Up From Standby Mode in 3 µs (Typical)

16-Bit RISC Architecture, Extended Memory,

up to 20-MHz System Clock

Dual 12-Bit Digital-to-Analog (D/A) Converters

With Synchronization

•

Flexible Power Management System

–

Fully Integrated LDO With Programmable

Regulated Core Supply Voltage

•

Voltage Comparator

Hardware Multiplier Supporting 32-Bit

Operations

–

Supply Voltage Supervision, Monitoring,

and Brownout

•

Serial Onboard Programming, No External

Programming Voltage Needed

•

Unified Clock System

–

FLL Control Loop for Frequency

Stabilization

•

Six-Channel Internal DMA

Real-Time Clock Module With Supply Voltage

Backup Switch

Low-Power/Low-Frequency Internal Clock

Source (VLO)

•

Family Members are Summarized in Table 1

Low-Frequency Trimmed Internal Reference

Source (REFO)

For Complete Module Descriptions, See the

MSP430x5xx/MSP430x6xx Family User's Guide

(SLAU208)

–

32-kHz Crystals (XT1)

High-Frequency Crystals Up to 32 MHz

(XT2)

•

Four 16-Bit Timer With 3, 5, or 7

Capture/Compare Registers

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

DESCRIPTION

The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low power

modes is optimized to achieve extended battery life in portable measurement applications. The device features a

powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.

The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in 3 µs (typical).

The MSP430F563x series are microcontroller configurations with a high performance 12-bit analog-to-digital

(A/D) converter, comparator, two universal serial communication interfaces (USCI), USB 2.0, hardware multiplier,

DMA, four 16-bit timers, real-time clock module with alarm capabilities, and up to 74 I/O pins.

Typical applications for this device include analog and digital sensor systems, digital motor control, remote

controls, thermostats, digital timers, hand-held meters, etc.

Family members available are summarized in Table 1.

Table 1. Family Members

USCI

Flash

(KB)

SRAM

(KB)

Timer_A

Timer_B

ADC12_A DAC12_A Comp_B

Package

Type

Channel A: Channel B:

UART/IrDA/

Device

I/O

(1)

(2)

(3)

(Ch)

SPI/I²C

SPI

12 ext /

4 int

100 PZ,

113 ZQW

MSP430F5638

MSP430F5637

MSP430F5636

MSP430F5635

MSP430F5634

MSP430F5633

MSP430F5632

MSP430F5631

MSP430F5630

256

192

128

256

192

128

256

192

128

16 + 2

5, 3, 3

7

2

-

12

74

12 ext /

4 int

100 PZ,

113 ZQW

12 ext /

4 int

100 PZ,

113 ZQW

12 ext /

4 int

100 PZ,

113 ZQW

12 ext /

4 int

100 PZ,

113 ZQW

-

12 ext /

4 int

100 PZ,

113 ZQW

-

100 PZ,

113 ZQW

-

100 PZ,

113 ZQW

-

100 PZ,

113 ZQW

-

(1) The additional 2 KB USB SRAM that is listed can be used as general purpose SRAM when USB is not in use.

(2) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM

output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first

instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

(3) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM

output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first

instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

2

MSP430F563x

www.ti.com

SLAS650B –JUNE 2010–REVISED AUGUST 2011

Table 2. Ordering Information⁽¹⁾

PACKAGED DEVICES⁽²⁾

T_A

PLASTIC 100-PIN TQFP (PZ)

MSP430F5638IPZ

MSP430F5637IPZ

MSP430F5636IPZ

MSP430F5635IPZ

MSP430F5634IPZ

MSP430F5633IPZ

MSP430F5632IPZ

MSP430F5631IPZ

MSP430F5630IPZ

PLASTIC 113-BALL BGA (ZQW)

MSP430F5638IZQW

MSP430F5637IZQW

MSP430F5636IZQW

MSP430F5635IZQW

MSP430F5634IZQW

MSP430F5633IZQW

MSP430F5632IZQW

MSP430F5631IZQW

MSP430F5630IZQW

–40°C to 85°C

(1) For the most current package and ordering information, see the Package Option Addendum at the end

of this document, or see the TI web site at www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/package.

3

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

Functional Block Diagram, MSP430F5638, MSP430F5637, MSP430F5636

PA

PB

PC

PD

XIN XOUT

DV_CCDV_SS

AV_CCAV_SS

RST/NMI

P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x

P9.x

XT2IN

I/O Ports

P1/P2

2×8 I/Os

Interrupt

Capability

I/O Ports

P3/P4

2×8 I/Os

Interrupt

Capability

I/O Ports

P5/P6

2×8 I/Os

16KB

RAM

I/O Ports

P7/P8

1×6 I/Os

1×8 I/Os

ACLK

SYS

Power

Management

I/O Ports

P9

1×8 I/Os

Unified

Clock

System

USCI0,1

USB

256KB

192KB

128KB

XT2OUT

Watchdog

SMCLK

Ax: UART,

IrDA, SPI

+2KB RAM

USB Buffer

Full-speed

P2 Port

Mapping

Controller

LDO

SVM/SVS

Brownout

Flash

PE

1×8 I/Os

Bx: SPI, I2C

MCLK

PA

1×16 I/Os

PB

1×16 I/Os

PC

1×16 I/Os

+8B Backup

RAM

PD

1×14 I/Os

CPUXV2

and

Working

Registers

EEM

(L: 8+2)

DMA

ADC12_A

TA1 and

TA2

RTC_B

6 Channel

DAC12_A

REF

TA0

TB0

12 Bit

JTAG/

SBW

Interface/

200 KSPS

12 bit

2 channels

voltage out

Comp_B

MPY32

CRC16

2 Timer_A

each with

3 CC

Reference

1.5V, 2.0V,

2.5V

Timer_A

5 CC

Registers

Timer_B

7 CC

Registers

Battery

Backup

System

16 Channels

(12 ext/4 int)

Autoscan

Port PJ

Registers

Functional Block Diagram, MSP430F5635, MSP430F5634, MSP430F5633

PA

PB

PC

PD

XIN XOUT

DV_CCDV_SS

AV_CCAV_SS

RST/NMI

P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x

P9.x

XT2IN

I/O Ports

P1/P2

2×8 I/Os

Interrupt

Capability

I/O Ports

P3/P4

2×8 I/Os

Interrupt

Capability

I/O Ports

P5/P6

2×8 I/Os

16KB

RAM

I/O Ports

P7/P8

1×6 I/Os

1×8 I/Os

ACLK

Power

Management

SYS

I/O Ports

P9

1×8 I/Os

Unified

Clock

System

USCI0,1

USB

256KB

192KB

128KB

XT2OUT

Watchdog

SMCLK

Ax: UART,

IrDA, SPI

+2KB RAM

USB Buffer

Full-speed

LDO

SVM/SVS

Brownout

P2 Port

Mapping

Controller

Flash

PE

1×8 I/Os

Bx: SPI, I2C

MCLK

PA

1×16 I/Os

PB

1×16 I/Os

PC

1×16 I/Os

+8B Backup

RAM

PD

1×14 I/Os

CPUXV2

and

Working

Registers

EEM

(L: 8+2)

DMA

ADC12_A

TA1 and

TA2

RTC_B

6 Channel

REF

TA0

TB0

12 Bit

JTAG/

SBW

Interface/

200 KSPS

Comp_B

MPY32

CRC16

2 Timer_A

each with

3 CC

Reference

1.5V, 2.0V,

2.5V

Timer_A

5 CC

Registers

Timer_B

7 CC

Registers

Battery

Backup

System

16 Channels

(12 ext/4 int)

Autoscan

Port PJ

Registers

4

MSP430F563x

www.ti.com

SLAS650B –JUNE 2010–REVISED AUGUST 2011

Functional Block Diagram, MSP430F5632, MSP430F5631, MSP430F5630

PA

PB

PC

PD

XIN XOUT

DV_CCDV_SS

AV_CCAV_SS

RST/NMI

P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x

P9.x

XT2IN

I/O Ports

P1/P2

2×8 I/Os

Interrupt

Capability

I/O Ports

P3/P4

2×8 I/Os

Interrupt

Capability

I/O Ports

P5/P6

2×8 I/Os

16KB

RAM

I/O Ports

P7/P8

1×6 I/Os

1×8 I/Os

ACLK

Power

Management

SYS

I/O Ports

P9

1×8 I/Os

Unified

Clock

System

USCI0,1

USB

256KB

192KB

128KB

XT2OUT

Watchdog

SMCLK

Ax: UART,

IrDA, SPI

+2KB RAM

USB Buffer

Full-speed

LDO

SVM/SVS

Brownout

P2 Port

Mapping

Controller

Flash

PE

1×8 I/Os

Bx: SPI, I2C

MCLK

PA

1×16 I/Os

PB

1×16 I/Os

PC

1×16 I/Os

+8B Backup

RAM

PD

1×14 I/Os

CPUXV2

and

Working

Registers

EEM

(L: 8+2)

DMA

TA1 and

TA2

RTC_B

6 Channel

REF

TA0

TB0

JTAG/

SBW

Interface/

Comp_B

MPY32

CRC16

2 Timer_A

each with

3 CC

Reference

1.5V, 2.0V,

2.5V

Timer_A

5 CC

Registers

Timer_B

7 CC

Registers

Battery

Backup

System

Port PJ

Registers

5

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

Pin Designation, MSP430F5638IPZ, MSP430F5637IPZ, MSP430F5636IPZ

P6.4/CB4/A4

P6.5/CB5/A5

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

P9.7

P9.6

P9.5

P9.4

P9.3

P9.2

P9.1

P9.0

P8.7

2

P6.6/CB6/A6/DAC0

P6.7/CB7/A7/DAC1

P7.4/CB8/A12

P7.5/CB9/A13

P7.6/CB10/A14/DAC0

P7.7/CB11/A15/DAC1

P5.0/VREF+/VeREF+

P5.1/VREF−/VeREF−

AVCC1

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

P8.6/UCB1SOMI/UCB1SCL

P8.5/UCB1SIMO/UCB1SDA

DVCC2

MSP430F5638

MSP430F5637

MSP430F5636

AVSS1

XIN

DVSS2

PZ PACKAGE

(TOP VIEW)

XOUT

P8.4/UCB1CLK/UCA1STE

P8.3/UCA1RXD/UCA1SOMI

P8.2/UCA1TXD/UCA1SIMO

P8.1/UCB1STE/UCA1CLK

P8.0/TB0CLK

AVSS2

P5.6/ADC12CLK/DMAE0

P2.0/P2MAP0

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

P2.6/P2MAP6

P2.7/P2MAP7

DVCC1

P4.7/TB0OUTH/SVMOUT

P4.6/TB0.6

P4.5/TB0.5

P4.4/TB0.4

P4.3/TB0.3

P4.2/TB0.2

P4.1/TB0.1

DNC - Do not connect

6

MSP430F563x

www.ti.com

SLAS650B –JUNE 2010–REVISED AUGUST 2011

Pin Designation, MSP430F5635IPZ, MSP430F5634IPZ, MSP430F5633IPZ

P6.4/CB4/A4

P6.5/CB5/A5

P6.6/CB6/A6

P6.7/CB7/A7

P7.4/CB8/A12

P7.5/CB9/A13

P7.6/CB10/A14

P7.7/CB11/A15

P5.0/VREF+/VeREF+

P5.1/VREF−/VeREF−

AVCC1

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

P9.7

2

P9.6

3

P9.5

4

P9.4

5

P9.3

6

P9.2

7

P9.1

8

P9.0

9

P8.7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

P8.6/UCB1SOMI/UCB1SCL

P8.5/UCB1SIMO/UCB1SDA

DVCC2

MSP430F5635

MSP430F5634

MSP430F5633

AVSS1

XIN

DVSS2

PZ PACKAGE

(TOP VIEW)

XOUT

P8.4/UCB1CLK/UCA1STE

P8.3/UCA1RXD/UCA1SOMI

P8.2/UCA1TXD/UCA1SIMO

P8.1/UCB1STE/UCA1CLK

P8.0/TB0CLK

P4.7/TB0OUTH/SVMOUT

P4.6/TB0.6

AVSS2

P5.6/ADC12CLK/DMAE0

P2.0/P2MAP0

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

P2.6/P2MAP6

P2.7/P2MAP7

DVCC1

P4.5/TB0.5

P4.4/TB0.4

P4.3/TB0.3

P4.2/TB0.2

P4.1/TB0.1

DNC - Do not connect

7

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

Pin Designation, MSP430F5632IPZ, MSP430F5631IPZ, MSP430F5630IPZ

P6.4/CB4

P6.5/CB5

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

P9.7

P9.6

P9.5

P9.4

P9.3

P9.2

P9.1

P9.0

P8.7

2

P6.6/CB6

3

P6.7/CB7

4

P7.4/CB8

5

P7.5/CB9

6

P7.6/CB10

P7.7/CB11

P5.0/VREF+/VeREF+

P5.1/VREF−/VeREF−

AVCC1

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

P8.6/UCB1SOMI/UCB1SCL

P8.5/UCB1SIMO/UCB1SDA

DVCC2

MSP430F5632

MSP430F5631

MSP430F5630

AVSS1

XIN

DVSS2

PZ PACKAGE

(TOP VIEW)

XOUT

P8.4/UCB1CLK/UCA1STE

P8.3/UCA1RXD/UCA1SOMI

P8.2/UCA1TXD/UCA1SIMO

P8.1/UCB1STE/UCA1CLK

P8.0/TB0CLK

AVSS2

P5.6/DMAE0

P2.0/P2MAP0

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

P2.6/P2MAP6

P2.7/P2MAP7

DVCC1

P4.7/TB0OUTH/SVMOUT

P4.6/TB0.6

P4.5/TB0.5

P4.4/TB0.4

P4.3/TB0.3

P4.2/TB0.2

P4.1/TB0.1

DNC - Do not connect

8

MSP430F563x

www.ti.com

SLAS650B –JUNE 2010–REVISED AUGUST 2011

Pin Designation, MSP430F5638IZQW, MSP430F5637IZQW, MSP430F5636IZQW,

MSP430F5635IZQW, MSP430F5634IZQW, MSP430F5633IZQW, MSP430F5632IZQW,

MSP430F5631IZQW, MSP430F5630IZQW

ZQW PACKAGE

(TOP VIEW)

A1

B1

C1

D1

E1

F1

G1

H1

J1

A2

B2

C2

D2

E2

F2

G2

H2

J2

A3

B3

C3

A4

B4

A5

B5

A6

B6

A7

B7

A8

B8

A9

B9

A10

B10

A11

B11

C11

D11

E11

F11

G11

H11

J11

A12

B12

C12

D12

E12

F12

G12

H12

J12

D4

E4

F4

G4

H4

J4

D5

E5

F5

G5

H5

J5

D6

E6

D7

E7

D8

E8

F8

G8

H8

J8

D9

E9

F9

G9

H9

J9

H6

J6

H7

J7

K1

L1

K2

L2

K11

L11

M11

K12

L12

M12

L3

L4

L5

L6

L7

L8

L9

L10

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

NOTE: For terminal assignments, see Table 3

9

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

Table 3. Terminal Functions

TERMINAL

NO.

I/O⁽¹⁾

DESCRIPTION

NAME

PZ ZQW

General-purpose digital I/O

P6.4/CB4/A4

P6.5/CB5/A5

1

2

A1

B2

I/O Comparator_B input CB4

Analog input A4 – ADC (not available on '5632, '5631, '5630 devices)

General-purpose digital I/O

I/O Comparator_B input CB5

Analog input A5 – ADC (not available on '5632, '5631, '5630 devices)

General-purpose digital I/O

Comparator_B input CB6

Analog input A6 – ADC (not available on '5632, '5631, '5630 devices)

DAC12.0 output (not available on '5635, '5634, '5633, '5632, '5631, '5630 devices)

P6.6/CB6/A6/DAC0

P6.7/CB7/A7/DAC1

3

4

B1

C2

I/O

General-purpose digital I/O

Comparator_B input CB7

Analog input A7 – ADC (not available on '5632, '5631, '5630 devices)

DAC12.1 output (not available on '5635, '5634, '5633, '5632, '5631, '5630 devices)

I/O

General-purpose digital I/O

P7.4/CB8/A12

P7.5/CB9/A13

5

6

C1

C3

I/O Comparator_B input CB8

Analog input A12 –ADC (not available on '5632, '5631, '5630 devices)

General-purpose digital I/O

I/O Comparator_B input CB9

Analog input A13 – ADC (not available on '5632, '5631, '5630 devices)

General-purpose digital I/O

Comparator_B input CB10

Analog input A14 – ADC (not available on '5632, '5631, '5630 devices)

DAC12.0 output (not available on '5635, '5634, '5633, '5632, '5631, '5630 devices)

P7.6/CB10/A14/DAC0

7

D2

D1

I/O

General-purpose digital I/O

Comparator_B input CB11

Analog input A15 – ADC (not available on '5632, '5631, '5630 devices)

DAC12.1 output (not available on '5635, '5634, '5633, '5632, '5631, '5630 devices)

P7.7/CB11/A15/DAC1

P5.0/VREF+/VeREF+

8

9

I/O

General-purpose digital I/O

I/O Output of reference voltage to the ADC

Input for an external reference voltage to the ADC

D4

E4

General-purpose digital I/O

I/O Negative terminal for the ADC's reference voltage for both sources, the internal

reference voltage, or an external applied reference voltage

P5.1/VREF-/VeREF-

AVCC1

10

11

E1,

E2

Analog power supply

Analog ground supply

AVSS1

XIN

12

13

14

15

F2

F1

G1

G2

I

Input terminal for crystal oscillator XT1

Output terminal of crystal oscillator XT1

Analog ground supply

XOUT

AVSS2

O

General-purpose digital I/O

P5.6/ADC12CLK/DMAE0

16

H1

I/O Conversion clock output ADC (not available on '5632, '5631, '5630 devices)

DMA external trigger input

General-purpose digital I/O with port interrupt and map-able secondary function

Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output

P2.0/P2MAP0

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

17

18

19

20

21

22

G4

H2

J1

I/O

General-purpose digital I/O with port interrupt and map-able secondary function

Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I2C data

I/O

General-purpose digital I/O with port interrupt and map-able secondary function

Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I2C clock

I/O

General-purpose digital I/O with port interrupt and map-able secondary function

Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable

H4

J2

I/O

General-purpose digital I/O with port interrupt and map-able secondary function

Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/master out

I/O

General-purpose digital I/O with port interrupt and map-able secondary function

Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/master in

K1

I/O

(1) I = input, O = output, N/A = not available on this package offering

10

MSP430F563x

www.ti.com

SLAS650B –JUNE 2010–REVISED AUGUST 2011

Table 3. Terminal Functions (continued)

TERMINAL

NAME

NO.

PZ ZQW

I/O⁽¹⁾

DESCRIPTION

General-purpose digital I/O with port interrupt and map-able secondary function

Default mapping: no secondary function

P2.6/P2MAP6

P2.7/P2MAP7

23

24

K2

L2

I/O

General-purpose digital I/O with port interrupt and map-able secondary function

Default mapping: no secondary function

DVCC1

DVSS1

VCORE⁽²⁾

P5.2

25

26

27

28

29

30

31

32

33

L1

M1

M2

L3

Digital power supply

Digital ground supply

Regulated core power supply (internal usage only, no external current loading)

I/O General-purpose digital I/O

DVSS

DNC

M3

J4

Digital ground supply

I/O Do not connect. It is strongly recommended to leave this terminal open.

I/O General-purpose digital I/O

P5.3

L4

P5.4

M4

J5

I/O General-purpose digital I/O

P5.5

I/O General-purpose digital I/O

General-purpose digital I/O with port interrupt

I/O Timer TA0 clock signal TACLK input

ACLK output (divided by 1, 2, 4, or 8)

P1.0/TA0CLK/ACLK

P1.1/TA0.0

34

35

36

L5

M5

J6

General-purpose digital I/O with port interrupt

I/O Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output

BSL transmit output

General-purpose digital I/O with port interrupt

I/O Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output

BSL receive input

P1.2/TA0.1

General-purpose digital I/O with port interrupt

Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output

P1.3/TA0.2

P1.4/TA0.3

P1.5/TA0.4

P1.6/TA0.1

P1.7/TA0.2

37

38

39

40

41

H6

M6

L6

I/O

General-purpose digital I/O with port interrupt

Timer TA0 CCR3 capture: CCI3A input compare: Out3 output

I/O

General-purpose digital I/O with port interrupt

Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output

I/O

General-purpose digital I/O with port interrupt

Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output

J7

I/O

General-purpose digital I/O with port interrupt

Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output

M7

I/O

General-purpose digital I/O with port interrupt

I/O Timer TA1 clock input

P3.0/TA1CLK/CBOUT

42

L7

Comparator_B output

General-purpose digital I/O with port interrupt

Timer TA1 capture CCR0: CCI0A/CCI0B input, compare: Out0 output

P3.1/TA1.0

P3.2/TA1.1

P3.3/TA1.2

43

44

45

H7

M8

L8

I/O

General-purpose digital I/O with port interrupt

Timer TA1 capture CCR1: CCI1A/CCI1B input, compare: Out1 output

I/O

General-purpose digital I/O with port interrupt

Timer TA1 capture CCR2: CCI2A/CCI2B input, compare: Out2 output

I/O

General-purpose digital I/O with port interrupt

I/O Timer TA2 clock input

P3.4/TA2CLK/SMCLK

46

J8

SMCLK output

General-purpose digital I/O with port interrupt

Timer TA2 capture CCR0: CCI0A/CCI0B input, compare: Out0 output

P3.5/TA2.0

P3.6/TA2.1

P3.7/TA2.2

47

48

49

M9

L9

I/O

General-purpose digital I/O with port interrupt

Timer TA2 capture CCR1: CCI1A/CCI1B input, compare: Out1 output

I/O

General-purpose digital I/O with port interrupt

Timer TA2 capture CCR2: CCI2A/CCI2B input, compare: Out2 output

M10

I/O

(2) VCORE is for internal usage only. No external current loading is possible. VCORE should only be connected to the recommended

capacitor value, C_VCORE

.

11

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

Table 3. Terminal Functions (continued)

TERMINAL

NO.

I/O⁽¹⁾

DESCRIPTION

NAME

PZ ZQW

General-purpose digital I/O with port interrupt

Timer TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output

P4.0/TB0.0

P4.1/TB0.1

P4.2/TB0.2

P4.3/TB0.3

P4.4/TB0.4

P4.5/TB0.5

P4.6/TB0.6

50

51

52

53

54

55

56

J9

I/O

General-purpose digital I/O with port interrupt

Timer TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output

M11

L10

M12

L12

L11

K11

General-purpose digital I/O with port interrupt

Timer TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output

General-purpose digital I/O with port interrupt

Timer TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output

General-purpose digital I/O with port interrupt

Timer TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output

General-purpose digital I/O with port interrupt

Timer TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output

General-purpose digital I/O with port interrupt

Timer TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output

General-purpose digital I/O with port interrupt

P4.7/TB0OUTH/SVMOUT

57

K12

I/O Timer TB0: Switch all PWM outputs high impedance

SVM output

General-purpose digital I/O

I/O

P8.0/TB0CLK

58

59

60

61

62

J11

J12

Timer TB0 clock input

General-purpose digital I/O

USCI_B1 SPI slave transmit enable; USCI_A1 clock input/output

P8.1/UCB1STE/UCA1CLK

P8.2/UCA1TXD/UCA1SIMO

P8.3/UCA1RXD/UCA1SOMI

P8.4/UCB1CLK/UCA1STE

I/O

General-purpose digital I/O

USCI_A1 UART transmit data; USCI_A1 SPI slave in/master out

H11

H12

G11

I/O

General-purpose digital I/O

USCI_A1 UART receive data; USCI_A1 SPI slave out/master in

I/O

General-purpose digital I/O

USCI_B1 clock input/output; USCI_A1 SPI slave transmit enable

I/O

DVSS2

DVCC2

63

64

G12

F12

Digital ground supply

Digital power supply

General-purpose digital I/O

USCI_B1 SPI slave in/master out; USCI_B1 I2C data

P8.5/UCB1SIMO/UCB1SDA

P8.6/UCB1SOMI/UCB1SCL

65

66

F11

G9

I/O

General-purpose digital I/O

USCI_B1 SPI slave out/master in; USCI_B1 I2C clock

I/O

P8.7

P9.0

P9.1

P9.2

P9.3

P9.4

P9.5

P9.6

P9.7

67

68

69

70

71

72

73

74

75

E12

E11

F9

I/O General-purpose digital I/O

D12

D11

E9

C12

C11

D9

B11

and

B12

VSSU

76

USB PHY ground supply

General-purpose digital I/O - controlled by USB control register

USB data terminal DP

PU.0/DP

PUR

77

78

79

A12

B10

A11

I/O

I/O USB pull-up resistor pin (open drain)

General-purpose digital I/O - controlled by USB control register

USB data terminal DM

PU.1/DM

I/O

VBUS

VUSB

80

81

A10

A9

USB LDO input (connect to USB power source)

USB LDO output

12

MSP430F563x

www.ti.com

SLAS650B –JUNE 2010–REVISED AUGUST 2011

Table 3. Terminal Functions (continued)

TERMINAL

NAME

NO.

PZ ZQW

I/O⁽¹⁾

DESCRIPTION

V18

82

83

B9

A8

USB regulated power (internal usage only, no external current loading)

AVSS3

Analog ground supply

General-purpose digital I/O

Input terminal for crystal oscillator XT2

P7.2/XT2IN

84

85

86

87

88

B8

B7

A7

D8

D7

I/O

General-purpose digital I/O

Output terminal of crystal oscillator XT2

P7.3/XT2OUT

VBAK

Capacitor for backup subsystem. Do not load this pin externally. For capacitor

values, see C_BAKin Recommended Operating Conditions.

Backup/secondary supply voltage. If backup voltage is not supplied connect to

DVCC externally.

VBAT

General-purpose digital I/O

RTCCLK output

P5.7/RTCCLK

I/O

DVCC3

DVSS3

89

90

A6

A5

Digital power supply

Digital ground supply

Test mode pin – select digital I/O on JTAG pins

Spy-bi-wire input clock

TEST/SBWTCK

PJ.0/TDO

91

92

93

94

95

B6

B5

A4

E7

D6

I

General-purpose digital I/O

Test data output port

I/O

General-purpose digital I/O

Test data input or test clock input

PJ.1/TDI/TCLK

PJ.2/TMS

General-purpose digital I/O

Test mode select

General-purpose digital I/O

Test clock

PJ.3/TCK

Reset input active low

RST/NMI/SBWTDIO

P6.0/CB0/A0

96

97

A3

B4

B3

A2

D5

I/O Non-maskable interrupt input

Spy-bi-wire data input/output

General-purpose digital I/O

I/O Comparator_B input CB0

Analog input A0 – ADC (not available on '5632, '5631, '5630 devices)

General-purpose digital I/O

I/O Comparator_B input CB1

P6.1/CB1/A1

98

Analog input A1 – ADC (not available on '5632, '5631, '5630 devices)

General-purpose digital I/O

I/O Comparator_B input CB2

P6.2/CB2/A2

99

Analog input A2 – ADC (not available on '5632, '5631, '5630 devices)

General-purpose digital I/O

I/O Comparator_B input CB3

P6.3/CB3/A3

100

Analog input A3 – ADC (not available on '5632, '5631, '5630 devices)

E5

E6

E8

F4

F5

F8

G5

G8

H5

H8

H9

Reserved BGA package balls. It is recommended to connect to ground

(DV_SS/AV_SS).

Reserved

N/A

13

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

SHORT-FORM DESCRIPTION

Program Counter

PC/R0

SP/R1

CPU

The MSP430 CPU has a 16-bit RISC architecture

that is highly transparent to the application. All

operations, other than program-flow instructions, are

performed as register operations in conjunction with

seven addressing modes for source operand and four

addressing modes for destination operand.

Stack Pointer

Status Register

SR/CG1/R2

CG2/R3

R4

Constant Generator

General-Purpose Register

The CPU is integrated with 16 registers that provide

R5

reduced

instruction

execution

time.

The

register-to-register operation execution time is one

cycle of the CPU clock.

R6

R7

Four of the registers, R0 to R3, are dedicated as

program counter, stack pointer, status register, and

constant generator, respectively. The remaining

registers are general-purpose registers.

R8

R9

Peripherals are connected to the CPU using data,

address, and control buses, and can be handled with

all instructions.

R10

R11

R12

R13

R14

R15

Instruction Set

The instruction set consists of the original 51

instructions with three formats and seven address

modes and additional instructions for the expanded

address range. Each instruction can operate on word

and byte data. Table 4 shows examples of the three

types of instruction formats; Table 5 shows the

address modes.

Table 4. Instruction Word Formats

INSTRUCTION WORD FORMAT

Dual operands, source-destination

Single operands, destination only

Relative jump, un/conditional

EXAMPLE

ADD R4,R5

CALL R8

JNE

OPERATION

R4 + R5 → R5

PC → (TOS), R8 → PC

Jump-on-equal bit = 0

Table 5. Address Mode Descriptions

ADDRESS MODE

Register

S⁽¹⁾

+

D⁽¹⁾

+

SYNTAX

MOV Rs,Rd

EXAMPLE

OPERATION

MOV R10,R11

R10 → R11

Indexed

+

MOV X(Rn),Y(Rm)

MOV EDE,TONI

MOV &MEM, &TCDAT

MOV @Rn,Y(Rm)

MOV 2(R5),6(R6)

M(2+R5) → M(6+R6)

M(EDE) → M(TONI)

M(MEM) → M(TCDAT)

M(R10) → M(Tab+R6)

Symbolic (PC relative)

Absolute

+

Indirect

+

MOV @R10,Tab(R6)

MOV @R10+,R11

MOV #45,TONI

M(R10) → R11

R10 + 2 → R10

Indirect auto-increment

Immediate

+

MOV @Rn+,Rm

MOV #X,TONI

#45 → M(TONI)

(1) S = source, D = destination

14

MSP430F563x

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SLAS650B –JUNE 2010–REVISED AUGUST 2011

Operating Modes

The MSP430 has one active mode and seven software selectable low-power modes of operation. An interrupt

event can wake up the device from any of the low-power modes, service the request, and restore back to the

low-power mode on return from the interrupt program.

The following seven operating modes can be configured by software:

•

Active mode (AM)

All clocks are active

Low-power mode 0 (LPM0)

–

•

–

CPU is disabled

ACLK and SMCLK remain active, MCLK is disabled

FLL loop control remains active

•

Low-power mode 1 (LPM1)

–

CPU is disabled

FLL loop control is disabled

ACLK and SMCLK remain active, MCLK is disabled

Low-power mode 2 (LPM2)

–

CPU is disabled

MCLK, FLL loop control, and DCOCLK are disabled

DCO's dc generator remains enabled

ACLK remains active

•

Low-power mode 3 (LPM3)

–

CPU is disabled

MCLK, FLL loop control, and DCOCLK are disabled

DCO's dc generator is disabled

ACLK remains active

Low-power mode 4 (LPM4)

–

CPU is disabled

ACLK is disabled

MCLK, FLL loop control, and DCOCLK are disabled

DCO's dc generator is disabled

Crystal oscillator is stopped

Complete data retention

•

Low-power mode 3.5 (LPM3.5)

–

Internal regulator disabled

No data retention

RTC enabled and clocked by low-frequency oscillator

Wakeup from RST/NMI, RTC_B, P1, P2, P3, and P4

Low-power mode 4.5 (LPM4.5)

–

Internal regulator disabled

No data retention

Wakeup from RST/NMI, RTC_B, P1, P2, P3, and P4

15

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

Interrupt Vector Addresses

The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The

vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 6. Interrupt Sources, Flags, and Vectors of MSP430F563x Configurations

SYSTEM

INTERRUPT

WORD

ADDRESS

INTERRUPT SOURCE

INTERRUPT FLAG

PRIORITY

System Reset

Power-Up, External Reset

Watchdog Timeout, Key Violation

Flash Memory Key Violation

WDTIFG, KEYV (SYSRSTIV)^{(1) (2)}

Reset

0FFFEh

0FFFCh

0FFFAh

63, highest

System NMI

PMM

Vacant Memory Access

JTAG Mailbox

SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,

VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,

JMBOUTIFG (SYSSNIV)⁽¹⁾

(Non)maskable

62

61

User NMI

NMI

Oscillator Fault

NMIIFG, OFIFG, ACCVIFG, BUSIFG

(SYSUNIV)^{(1) (2)}

Flash Memory Access Violation

Comp_B

Comparator B interrupt flags (CBIV)^{(1) (3)}

Maskable

0FFF8h

0FFF6h

60

59

(3)

Timer TB0

TB0CCR0 CCIFG0

TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,

TB0IFG (TBIV)^{(1) (3)}

Timer TB0

Maskable

0FFF4h

58

Watchdog Interval Timer Mode

USCI_A0 Receive/Transmit

USCI_B0 Receive/Transmit

ADC12_A⁽⁴⁾

WDTIFG

Maskable

0FFF2h

0FFF0h

0FFEEh

0FFECh

0FFEAh

57

56

55

54

53

UCA0RXIFG, UCA0TXIFG (UCA0IV)^{(1) (3)}

UCB0RXIFG, UCB0TXIFG (UCAB0IV)^{(1) (3)}

ADC12IFG0 to ADC12IFG15 (ADC12IV)^{(1) (3)}

TA0CCR0 CCIFG0⁽³⁾

Timer TA0

TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,

TA0IFG (TA0IV)^{(1) (3)}

Timer TA0

USB_UBM

DMA

Maskable

0FFE8h

0FFE6h

0FFE4h

0FFE2h

0FFE0h

52

51

50

49

48

USB interrupts (USBIV)⁽¹⁾⁽³⁾

DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG,

DMA4IFG, DMA5IFG (DMAIV)^{(1) (3)}

Timer TA1

TA1CCR0 CCIFG0⁽³⁾

TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,

TA1IFG (TA1IV)^{(1) (3)}

I/O Port P1

USCI_A1 Receive/Transmit

USCI_B1 Receive/Transmit

I/O Port P2

P1IFG.0 to P1IFG.7 (P1IV)^{(1) (3)}

UCA1RXIFG, UCA1TXIFG (UCA1IV)^{(1) (3)}

UCB1RXIFG, UCB1TXIFG (UCB1IV)^{(1) (3)}

P2IFG.0 to P2IFG.7 (P2IV)^{(1) (3)}

Reserved

Maskable

0FFDEh

0FFDCh

0FFDAh

0FFD8h

0FFD6h

47

46

45

44

43

Reserved

RTCRDYIFG, RTCTEVIFG, RTCAIFG,

RTC_B

Maskable

0FFD4h

42

RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV)^{(1) (3)}

DAC12_A⁽⁵⁾

Timer TA2

DAC12_0IFG, DAC12_1IFG^{(1) (3)}

TA2CCR0 CCIFG2⁽³⁾

Maskable

0FFD2h

0FFD0h

41

40

TA2CCR1 CCIFG1 to TA2CCR2,

TA2IFG (TA2IV)^{(1) (3)}

Timer TA2

Maskable

0FFCEh

39

I/O Port P3

I/O Port P4

P3IFG.0 to P3IFG.7 (P3IV)^{(1) (3)}

P4IFG.0 to P4IFG.7 (P4IV)^{(1) (3)}

Maskable

0FFCCh

0FFCAh

38

37

(1) Multiple source flags

(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.

(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

(3) Interrupt flags are located in the module.

(4) Only on devices with peripheral module ADC12_A, otherwise reserved.

(5) Only on devices with peripheral module DAC12_A, otherwise reserved.

16

MSP430F563x

www.ti.com

SLAS650B –JUNE 2010–REVISED AUGUST 2011

Table 6. Interrupt Sources, Flags, and Vectors of MSP430F563x Configurations (continued)

SYSTEM

INTERRUPT

WORD

ADDRESS

INTERRUPT SOURCE

INTERRUPT FLAG

PRIORITY

0FFC8h

⋮

36

Reserved

Reserved⁽⁶⁾

⋮

0FF80h

0, lowest

(6) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain

compatability with other devices, it is recommended to reserve these locations.

Memory Organization

Table 7. Memory Organization^{(1) (2)}

MSP430F5636

MSP430F5633

MSP430F5630

MSP430F5637

MSP430F5634

MSP430F5631

MSP430F5637

MSP430F5634

MSP430F5631

Memory (flash)

Main: interrupt vector

Total Size

Bank 3

128KB

00FFFFh–00FF80h

192KB

00FFFFh–00FF80h

256KB

00FFFFh–00FF80h

N/A

64 KB

047FFF-038000h

Bank 2

N/A

64 KB

037FFF-028000h

Main: code memory

Bank 1

64 KB

027FFF-018000h

Bank 0

64 KB

017FFF-008000h

Sector 3

Sector 2

Sector 1

Sector 0

4 KB

0063FFh–005400h

4 KB

0063FFh–005400h

4 KB

0063FFh–005400h

4 KB

0053FFh–004400h

4 KB

0053FFh–004400h

4 KB

0053FFh–004400h

RAM

4 KB

0043FFh–003400h

4 KB

0043FFh–003400h

4 KB

0043FFh–003400h

4 KB

0033FFh–002400h

Size

RAM

2KB

USB RAM⁽³⁾

0023FFh-001C00h

Info A

Info B

Info C

Info D

BSL 3

BSL 2

BSL 1

BSL 0

Size

128 B

0019FFh–001980h

128 B

0019FFh–001980h

128 B

0019FFh–001980h

128 B

00197Fh–001900h

128 B

00197Fh–001900h

128 B

00197Fh–001900h

Information memory

(flash)

128 B

0018FFh–001880h

128 B

0018FFh–001880h

128 B

0018FFh–001880h

128 B

00187Fh–001800h

128 B

00187Fh–001800h

128 B

00187Fh–001800h

512 B

0017FFh–001600h

512 B

0017FFh–001600h

512 B

0017FFh–001600h

512 B

0015FFh–001400h

512 B

0015FFh–001400h

512 B

0015FFh–001400h

Bootstrap loader (BSL)

memory (flash)

512 B

0013FFh–001200h

512 B

0013FFh–001200h

512 B

0013FFh–001200h

512 B

0011FFh–001000h

512 B

0011FFh–001000h

512 B

0011FFh–001000h

4KB

Peripherals

000FFFh–000000h

(1) N/A = Not available.

(2) Backup RAM is accessed via the control registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.

(3) USB RAM can be used as general purpose RAM when not used for USB operation.

17

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

Bootstrap Loader (BSL)

The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to the

device memory via the BSL is protected by an user-defined password. For complete description of the features of

the BSL and its implementation, see the MSP430 Memory Programming User's Guide (SLAU265).

USB BSL

All devices come pre-programmed with the USB BSL. Usage of the USB BSL requires external access to the six

pins shown in Table 8. In addition to these pins, the application must support external components necessary for

normal USB operation; for example, proper crystal on XT2IN and XT2OUT, proper decoupling, etc.

Table 8. USB BSL Pin Requirements and Functions

DEVICE SIGNAL

RST/NMI/SBWTDIO

PU.0/DP

BSL FUNCTION

Entry sequence signal

USB data terminal DP

USB data terminal DM

USB pullup resistor terminal

USB bus power supply

USB ground supply

PU.1/DM

PUR

VBUS

VSSU

UART BSL

A UART BSL is also available that can be programmed by the user into the BSL memory by replacing the

pre-programmed, factory supplied, USB BSL. Usage of the UART BSL requires external access to the six pins

shown in Table 9.

Table 9. UART BSL Pin Requirements and Functions

DEVICE SIGNAL

BSL FUNCTION

Entry sequence signal

Data transmit

RST/NMI/SBWTDIO

TEST/SBWTCK

P1.1

P1.2

VCC

VSS

Data receive

Power supply

Ground supply

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JTAG Operation

JTAG Standard Interface

The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving

data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the

JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430

development tools and device programmers. The JTAG pin requirements are shown in Table 10. For further

details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's

Guide (SLAU278).

Table 10. JTAG Pin Requirements and Functions

DEVICE SIGNAL

PJ.3/TCK

DIRECTION

FUNCTION

JTAG clock input

JTAG state control

JTAG data input/TCLK input

JTAG data output

Enable JTAG pins

External reset

IN

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

IN

OUT

IN

TEST/SBWTCK

RST/NMI/SBWTDIO

VCC

IN

Power supply

VSS

Ground supply

Spy-Bi-Wire Interface

In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface.

Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire

interface pin requirements are shown in Table 11. For further details on interfacing to development tools and

device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278).

Table 11. Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL

TEST/SBWTCK

RST/NMI/SBWTDIO

VCC

DIRECTION

IN

FUNCTION

Spy-Bi-Wire clock input

Spy-Bi-Wire data input/output

Power supply

IN, OUT

VSS

Ground supply

Flash Memory

The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the

CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the

flash memory include:

•

Flash memory has n segments of main memory and four segments of information memory (A to D) of

128 bytes each. Each segment in main memory is 512 bytes in size.

•

Segments 0 to n may be erased in one step, or each segment may be individually erased.

Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also

called information memory.

•

Segment A can be locked separately.

RAM Memory

The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,

however all data is lost. Features of the RAM memory include:

•

RAM memory has n sectors. The size of a sector can be found in Memory Organization.

Each sector 0 to n can be complete disabled, however data retention is lost.

Each sector 0 to n automatically enters low power retention mode when possible.

For devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.

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Backup RAM Memory

The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5 and during

operation from a backup supply if the Battery Backup System module is implemented.

There are 8 bytes of Backup RAM available on MSP430F563x. It can be wordwise accessed via the control

registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.

Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all

instructions. For complete module descriptions, see the MSP430x5xx/MSP430x6xx Family User's Guide (SLAU

208).

Digital I/O

There are up to nine 8-bit I/O ports implemented: P1 through P9 are complete, and port PJ contains four

individual I/O ports.

•

All individual I/O bits are independently programmable.

Any combination of input, output, and interrupt conditions is possible.

Programmable pullup or pulldown on all ports.

Programmable drive strength on all ports.

Edge-selectable interrupt input capability for all the eight bits of ports P1, P2, P3, and P4.

Read/write access to port-control registers is supported by all instructions.

Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PD).

Port Mapping Controller

The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P2.

Table 12. Port Mapping, Mnemonics and Functions

VALUE

PxMAPy MNEMONIC

PM_NONE

INPUT PIN FUNCTION

OUTPUT PIN FUNCTION

0

None

DV_SS

PM_CBOUT

-

Comparator_B output

1

2

PM_TB0CLK

Timer TB0 clock input

-

PM_ADC12CLK

PM_DMAE0

-

ADC12CLK

-

DMAE0 Input

-

PM_SVMOUT

SVM output

3

Timer TB0 high impedance input

TB0OUTH

PM_TB0OUTH

-

4

5

PM_TB0CCR0B

PM_TB0CCR1B

PM_TB0CCR2B

PM_TB0CCR3B

PM_TB0CCR4B

PM_TB0CCR5B

PM_TB0CCR6B

PM_UCA0RXD

PM_UCA0SOMI

PM_UCA0TXD

PM_UCA0SIMO

PM_UCA0CLK

PM_UCB0STE

PM_UCB0SOMI

PM_UCB0SCL

Timer TB0 CCR0 capture input CCI0B

Timer TB0 CCR1 capture input CCI1B

Timer TB0 CCR2 capture input CCI2B

Timer TB0 CCR3 capture input CCI3B

Timer TB0 CCR4 capture input CCI4B

Timer TB0 CCR5 capture input CCI5B

Timer TB0 CCR6 capture input CCI6B

Timer TB0: TB0.0 compare output Out0

Timer TB0: TB0.1 compare output Out1

Timer TB0: TB0.2 compare output Out2

Timer TB0: TB0.3 compare output Out3

Timer TB0: TB0.4 compare output Out4

Timer TB0: TB0.5 compare output Out5

Timer TB0: TB0.6 compare output Out6

6

7

8

9

10

USCI_A0 UART RXD (Direction controlled by USCI - input)

11

12

13

14

USCI_A0 SPI slave out master in (direction controlled by USCI)

USCI_A0 UART TXD (Direction controlled by USCI - output)

USCI_A0 SPI slave in master out (direction controlled by USCI)

USCI_A0 clock input/output (direction controlled by USCI)

USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)

USCI_B0 SPI slave out master in (direction controlled by USCI)

USCI_B0 I2C clock (open drain and direction controlled by USCI)

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Table 12. Port Mapping, Mnemonics and Functions (continued)

VALUE

PxMAPy MNEMONIC

PM_UCB0SIMO

PM_UCB0SDA

PM_UCB0CLK

PM_UCA0STE

PM_MCLK

INPUT PIN FUNCTION

OUTPUT PIN FUNCTION

USCI_B0 SPI slave in master out (direction controlled by USCI)

USCI_B0 I2C data (open drain and direction controlled by USCI)

USCI_B0 clock input/output (direction controlled by USCI)

15

16

USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)

17

18

-

MCLK

Reserved

Reserved for test purposes. Do not use this setting.

19

Reserved

20 - 30

Reserved

None

DV_SS

Disables the output driver as well as the input Schmitt-trigger to prevent parasitic cross

currents when applying analog signals.

31 (0FFh)⁽¹⁾

PM_ANALOG

(1) The value of the PMPAP_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are

ignored resulting in a read out value of 31.

Table 13. Default Mapping

PxMAPy MNEMONIC

INPUT PIN FUNCTION

OUTPUT PIN FUNCTION

PM_UCB0STE/

PM_UCA0CLK

USCI_B0 SPI slave transmit enable (direction controlled by USCI - input) /

USCI_A0 clock input/output (direction controlled by USCI)

P2.0/P2MAP0

PM_UCB0SIMO/

PM_UCB0SDA

USCI_B0 SPI slave in master out (direction controlled by USCI) / USCI_B0 I2C

data (open drain and direction controlled by USCI)

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

PM_UCB0SOMI/

PM_UCB0SCL

USCI_B0 SPI slave out master in (direction controlled by USCI) / USCI_B0 I2C

clock (open drain and direction controlled by USCI)

PM_UCB0CLK/

PM_UCA0STE

USCI_B0 clock input/output (direction controlled by USCI) / USCI_A0 SPI slave

transmit enable (direction controlled by USCI - input)

PM_UCA0TXD/

PM_UCA0SIMO

USCI_A0 UART TXD (direction controlled by USCI - output) / USCI_A0 SPI slave

in master out (direction controlled by USCI)

PM_UCA0RXD/

PM_UCA0SOMI

USCI_A0 UART RXD (direction controlled by USCI - input) / USCI_A0 SPI slave

out master in (direction controlled by USCI)

P2.6/P2MAP6

P2.7/P2MAP7

PM_NONE

-

DV_SS

Oscillator and System Clock

The clock system in the MSP430F563x family of devices is supported by the Unified Clock System (UCS)

module that includes support for a 32-kHz watch crystal oscillator (in XT1 LF mode; XT1 HF mode is not

supported), an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency

oscillator (REFO), an integrated internal digitally-controlled oscillator (DCO), and a high-frequency crystal

oscillator XT2. The UCS module is designed to meet the requirements of both low system cost and low power

consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction with a

digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The

internal DCO provides a fast turn-on clock source and stabilizes in 3 µs (typical). The UCS module provides the

following clock signals:

•

Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the

internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal

digitally-controlled oscillator DCO.

•

Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources available to

ACLK.

Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by

same sources available to ACLK.

ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.

Power Management Module (PMM)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains

programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor

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MSP430F563x

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(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is

implemented to provide the proper internal reset signal to the device during power-on and power-off. The

SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply

voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not

automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.

Hardware Multiplier

The multiplication operation is supported by a dedicated peripheral module. The module performs operations with

32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication

as well as signed and unsigned multiply and accumulate operations.

Real-Time Clock (RTC_B)

The RTC_B module can be configured for real-time clock (RTC) and calendar mode providing seconds, minutes,

hours, day of week, day of month, month, and year. Calendar mode integrates an internal calendar which

compensates for months with less than 31 days and includes leap year correction. The RTC_B also supports

flexible alarm functions and offset-calibration hardware. The implementation on this device supports operation in

LPM3.5 mode and operation from a backup supply.

Watchdog Timer (WDT_A)

The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a

software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog

function is not needed in an application, the module can be configured as an interval timer and can generate

interrupts at selected time intervals.

System Module (SYS)

The SYS module handles many of the system functions within the device. These include power-on reset and

power-up clear handling, NMI source selection and management, reset interrupt vector generators, bootstrap

loader entry mechanisms, and configuration management (device descriptors). SYS also includes a data

exchange mechanism via JTAG called a JTAG mailbox that can be used in the application.

Table 14. System Module Interrupt Vector Registers

INTERRUPT VECTOR

INTERRUPT EVENT

WORD ADDRESS

OFFSET

PRIORITY

REGISTER

No interrupt pending

Brownout (BOR)

00h

02h

Highest

RST/NMI (BOR)

04h

DoBOR (BOR)

06h

LPM3.5 or LPM4.5 wakeup (BOR)

Security violation (BOR)

SVSL (POR)

08h

0Ah

0Ch

0Eh

SVSH (POR)

SVML_OVP (POR)

SVMH_OVP (POR)

DoPOR (POR)

10h

SYSRSTIV , System Reset

019Eh

12h

14h

WDT timeout (PUC)

WDT key violation (PUC)

KEYV flash key violation (PUC)

FLL unlock (PUC)

16h

18h

1Ah

1Ch

1Eh

Peripheral area fetch (PUC)

PMM key violation (PUC)

Reserved

20h

22h to 3Eh

Lowest

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Table 14. System Module Interrupt Vector Registers (continued)

INTERRUPT VECTOR

INTERRUPT EVENT

WORD ADDRESS

OFFSET

PRIORITY

REGISTER

No interrupt pending

SVMLIFG

00h

02h

Highest

SVMHIFG

04h

DLYLIFG

06h

DLYHIFG

08h

SYSSNIV , System NMI

VMAIFG

019Ch

0Ah

JMBINIFG

0Ch

JMBOUTIFG

VLRLIFG

0Eh

10h

VLRHIFG

12h

Reserved

14h to 1Eh

00h

Lowest

Highest

No interrupt pending

NMIFG

02h

OFIFG

04h

SYSUNIV, User NMI

019Ah

0198h

ACCVIFG

06h

BUSIFG

08h

Reserved

0Ah to 1Eh

00h

Lowest

No interrupt pending

USB wait state timeout

Reserved

SYSBERRIV, Bus Error

02h

Highest

Lowest

04h to 1Eh

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DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU intervention. For

example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM. Using

the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system

power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or

from a peripheral.

The USB timestamp generator also uses the channel 0, 1, and 2 DMA trigger assignments described in

Table 15.

Table 15. DMA Trigger Assignments⁽¹⁾

Channel

Trigger

0

1

2

3

4

5

0

DMAREQ

1

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TA2CCR0 CCIFG

TA2CCR2 CCIFG

TBCCR0 CCIFG

TBCCR2 CCIFG

Reserved

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Reserved

UCA0RXIFG

UCA0TXIFG

UCB0RXIFG

UCB0TXIFG

UCA1RXIFG

UCA1TXIFG

UCB1RXIFG

UCB1TXIFG

ADC12IFGx⁽²⁾

DAC12_0IFG⁽³⁾

DAC12_1IFG⁽³⁾

USB FNRXD

USB ready

MPY ready

DMA5IFG

DMA0IFG

DMA1IFG

DMA2IFG

DMAE0

DMA3IFG

DMA4IFG

(1) Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers will not

cause any DMA trigger event when selected.

(2) Only on devices with peripheral module ADC12_A. Reserved on devices without ADC.

(3) Only on devices with peripheral module DAC12_A. Reserved on devices without DAC.

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Universal Serial Communication Interface (USCI)

The USCI modules are used for serial data communication. The USCI module supports synchronous

communication protocols such as SPI (3 or 4 pin) and I²C, and asynchronous communication protocols such as

UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions,

A and B.

The USCI_An module provides support for SPI (3 or 4 pin), UART, enhanced UART, or IrDA.

The USCI_Bn module provides support for SPI (3 or 4 pin) or I2C.

The MSP430F563x series includes two complete USCI modules (n = 0 to 1).

Timer TA0

Timer TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. It can support multiple

capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may

be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 16. Timer TA0 Signal Connections

INPUT PIN NUMBER

DEVICE

INPUT

SIGNAL

MODULE

INPUT

SIGNAL

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

OUTPUT PIN NUMBER

MODULE

BLOCK

PZ

ZQW

PZ

ZQW

34-P1.0

L5-P1.0

TA0CLK

ACLK

TACLK

ACLK

SMCLK

TACLK

CCI0A

CCI0B

GND

Timer

CCR0

NA

SMCLK

TA0CLK

TA0.0

DV_SS

34-P1.0

35-P1.1

L5-P1.0

M5-P1.1

35-P1.1

M5-P1.1

J6-P1.2

TA0

TA0.0

DV_SS

DV_CC

V_CC

36-P1.2

40-P1.6

J6-P1.2

J7-P1.6

TA0.1

CCI1A

CCI1B

36-P1.2

40-P1.6

J7-P1.6

(1)

CCR1

TA1

TA0.1

ADC12_A (internal)

ADC12SHSx = {1}

DV_SS

GND

DV_CC

TA0.2

DV_SS

DV_CC

TA0.3

DV_SS

DV_CC

TA0.4

DV_SS

DV_CC

V_CC

CCI2A

CCI2B

GND

37-P1.3

41-P1.7

H6-P1.3

M7-P1.7

37-P1.3

41-P1.7

H6-P1.3

M7-P1.7

CCR2

CCR3

CCR4

TA2

TA3

TA4

TA0.2

TA0.3

TA0.4

V_CC

38-P1.4

39-P1.5

M6-P1.4

L6-P1.5

CCI3A

CCI3B

GND

38-P1.4

39-P1.5

M6-P1.4

V_CC

CCI4A

CCI4B

GND

L6-P1.5

V_CC

(1) Only on devices with peripheral module ADC12_A.

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SLAS650B –JUNE 2010–REVISED AUGUST 2011

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Timer TA1

Timer TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It supports multiple

capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may

be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 17. Timer TA1 Signal Connections

INPUT PIN NUMBER

DEVICE

INPUT

SIGNAL

MODULE

INPUT

SIGNAL

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

OUTPUT PIN NUMBER

MODULE

BLOCK

PZ

ZQW

PZ

ZQW

42-P3.0

L7-P3.0

TA1CLK

ACLK

TACLK

ACLK

SMCLK

TACLK

CCI0A

CCI0B

GND

Timer

CCR0

NA

SMCLK

TA1CLK

TA1.0

DV_SS

42-P3.0

43-P3.1

L7-P3.0

H7-P3.1

43-P3.1

44-P3.2

H7-P3.1

M8-P3.2

TA0

TA1.0

DV_SS

DV_CC

V_CC

44-P3.2

45-P3.3

M8-P3.2

L8-P3.3

TA1.1

CCI1A

DAC12_A

CBOUT

(internal)

CCI1B

⁽¹⁾DAC12_0, DAC12_1

(internal)

CCR1

CCR2

TA1

TA2

TA1.1

TA1.2

DV_SS

DV_CC

TA1.2

GND

V_CC

CCI2A

45-P3.3

L8-P3.3

ACLK

(internal)

CCI2B

DV_SS

DV_CC

GND

V_CC

(1) Only on devices with peripheral module DAC12_A.

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Timer TA2

Timer TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It supports multiple

capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may

be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 18. Timer TA2 Signal Connections

INPUT PIN NUMBER

DEVICE

INPUT

SIGNAL

MODULE

INPUT

SIGNAL

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

OUTPUT PIN NUMBER

MODULE

BLOCK

PZ

ZQW

PZ

ZQW

46-P3.4

J8-P3.4

TA2CLK

ACLK

TACLK

ACLK

SMCLK

TACLK

CCI0A

CCI0B

GND

Timer

CCR0

NA

SMCLK

TA2CLK

TA2.0

DV_SS

46-P3.4

47-P3.5

J8-P3.4

M9-P3.5

47-P3.5

48-P3.6

M9-P3.5

L9-P3.6

TA0

TA2.0

DV_SS

DV_CC

V_CC

48-P3.6

49-P3.7

L9-P3.6

TA2.1

CCI1A

CBOUT

(internal)

CCI1B

CCR1

CCR2

TA1

TA2

TA2.1

TA2.2

DV_SS

DV_CC

TA2.2

GND

V_CC

M10-P3.7

CCI2A

49-P3.7

M10-P3.7

ACLK

(internal)

CCI2B

DV_SS

DV_CC

GND

V_CC

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Timer TB0

Timer TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. It supports multiple

capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may

be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 19. Timer TB0 Signal Connections

INPUT PIN NUMBER

DEVICE

INPUT

SIGNAL

MODULE

INPUT

SIGNAL

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

OUTPUT PIN NUMBER

MODULE

BLOCK

PZ

ZQW

PZ

ZQW

58-P8.0

J11-P8.0

TB0CLK

P2MAPx⁽¹⁾

ACLK

Timer

NA

SMCLK

58-P8.0

J11-P8.0

TB0CLK

P2MAPx⁽¹⁾

50-P4.0

P2MAPx⁽¹⁾

J9-P4.0

P2MAPx⁽¹⁾

TB0.0

CCI0A

CCI0B

50-P4.0

P2MAPx⁽¹⁾

J9-P4.0

P2MAPx⁽¹⁾

(2)

CCR0

CCR1

TB0

TB1

TB0.0

TB0.1

ADC12 (internal)

DV_SS

GND

ADC12SHSx = {2}

DV_CC

TB0.1

V_CC

51-P4.1

P2MAPx⁽¹⁾

M11-P4.1

P2MAPx⁽¹⁾

CCI1A

CCI1B

51-P4.1

P2MAPx⁽¹⁾

M11-P4.1

P2MAPx⁽¹⁾

(2)

ADC12 (internal)

DV_SS

GND

ADC12SHSx = {3}

DV_CC

TB0.2

V_CC

52-P4.2

P2MAPx⁽¹⁾

L10-P4.2

P2MAPx⁽¹⁾

CCI2A

CCI2B

52-P4.2

P2MAPx⁽¹⁾

L10-P4.2

P2MAPx⁽¹⁾

DAC12_A⁽³⁾

DAC12_0, DAC12_1

(internal)

CCR2

TB2

TB0.2

DV_SS

GND

DV_CC

TB0.3

DV_SS

DV_CC

TB0.4

DV_SS

DV_CC

TB0.5

DV_SS

DV_CC

TB0.6

DV_SS

DV_CC

V_CC

CCI3A

CCI3B

GND

53-P4.3

P2MAPx⁽¹⁾

M12-P4.3

P2MAPx⁽¹⁾

53-P4.3

P2MAPx⁽¹⁾

M12-P4.3

P2MAPx⁽¹⁾

CCR3

CCR4

CCR5

CCR6

TB3

TB4

TB5

TB6

TB0.3

TB0.4

TB0.5

TB0.6

V_CC

54-P4.4

P2MAPx⁽¹⁾

L12-P4.4

P2MAPx⁽¹⁾

CCI4A

CCI4B

GND

54-P4.4

P2MAPx⁽¹⁾

L12-P4.4

P2MAPx⁽¹⁾

V_CC

55-P4.5

P2MAPx⁽¹⁾

L11-P4.5

P2MAPx⁽¹⁾

CCI5A

CCI5B

GND

55-P4.5

P2MAPx⁽¹⁾

L11-P4.5

P2MAPx⁽¹⁾

V_CC

56-P4.6

P2MAPx⁽¹⁾

K11-P4.6

P2MAPx⁽¹⁾

CCI6A

CCI6B

GND

56-P4.6

P2MAPx⁽¹⁾

K11-P4.6

P2MAPx⁽¹⁾

V_CC

(1) Timer functions selectable via the port mapping controller.

(2) Only on devices with peripheral module ADC12_A.

(3) Only on devices with peripheral module DAC12_A.

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MSP430F563x

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SLAS650B –JUNE 2010–REVISED AUGUST 2011

Comparator_B

The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions,

battery voltage supervision, and monitoring of external analog signals.

ADC12_A

The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR

core, sample select control, reference generator, and

a 16-word conversion-and-control buffer. The

conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any

CPU intervention.

DAC12_A

The DAC12_A module is a 12-bit R-ladder voltage-output DAC. The DAC12_A may be used in 8-bit or 12-bit

mode, and may be used in conjunction with the DMA controller. When multiple DAC12_A modules are present,

they may be grouped together for synchronous operation.

CRC16

The CRC16 module produces a signature based on a sequence of entered data values and can be used for data

checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.

REF Voltage Reference

The reference module (REF) is responsible for generation of all critical reference voltages that can be used by

the various analog peripherals in the device.

USB Universal Serial Bus

The USB module is a fully integrated USB interface that is compliant with the USB 2.0 specification. The module

supports full-speed operation of control, interrupt, and bulk transfers. The module includes an integrated LDO,

PHY, and PLL. The PLL is highly flexible and can support a wide range of input clock frequencies. USB RAM,

when not used for USB communication, can be used by the system.

Embedded Emulation Module (EEM)

The Embedded Emulation Module (EEM) supports real-time in-system debugging. The L version of the EEM

implemented on these devices has the following features:

•

Eight hardware triggers/breakpoints on memory access

Two hardware triggers/breakpoints on CPU register write access

Up to ten hardware triggers can be combined to form complex triggers/breakpoints

Two cycle counters

Sequencer

State storage

Clock control on module level

29

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

Peripheral File Map

Table 20. Peripherals

(1)

MODULE NAME

Special Functions (see Table 21)

PMM (see Table 22)

BASE ADDRESS

0100h

0120h

0140h

0150h

0158h

015Ch

0160h

0180h

01B0h

01C0h

01D0h

0200h

0220h

0240h

0260h

0280h

0320h

0340h

0380h

03C0h

0400h

0480h

04A0h

04C0h

0500h

0510h

0520h

0530h

0540h

0550h

0560h

05C0h

05E0h

0600h

0620h

0700h

0780h

08C0h

0900h

0920h

OFFSET ADDRESS RANGE

000h - 01Fh

000h - 00Fh

000h - 007h

000h - 001h

000h - 01Fh

000h - 001h

000h - 003h

000h - 007h

000h - 01Fh

000h - 00Bh

000h - 01Fh

000h - 02Eh

000h - 01Fh

000h - 02Fh

000h - 00Fh

000h - 00Ah

000h - 01Fh

000h - 03Fh

000h - 01Fh

000h - 00Fh

000h - 014h

000h - 01Fh

Flash Control (see Table 23)

CRC16 (see Table 24)

RAM Control (see Table 25)

Watchdog (see Table 26)

UCS (see Table 27)

SYS (see Table 28)

Shared Reference (see Table 29)

Port Mapping Control (see Table 30)

Port Mapping Port P2 (see Table 30)

Port P1/P2 (see Table 31)

Port P3/P4 (see Table 32)

Port P5/P6 (see Table 33)

Port P7/P8 (see Table 34)

Port P9 (see Table 35)

Port PJ (see Table 36)

Timer TA0 (see Table 37)

Timer TA1 (see Table 38)

Timer TB0 (see Table 39)

Timer TA2 (see Table 40)

Battery Backup (see Table 41)

RTC_B (see Table 42)

32-bit Hardware Multiplier (see Table 43)

DMA General Control (see Table 44)

DMA Channel 0 (see Table 44)

DMA Channel 1 (see Table 44)

DMA Channel 2 (see Table 44)

DMA Channel 3 (see Table 44)

DMA Channel 4 (see Table 44)

DMA Channel 5 (see Table 44)

USCI_A0 (see Table 45)

USCI_B0 (see Table 46)

USCI_A1 (see Table 47)

USCI_B1 (see Table 48)

ADC12_A (see Table 49)

DAC12_A (see Table 50)

Comparator_B (see Table 51)

USB configuration (see Table 52)

USB control (see Table 53)

(1) For a detailed description of the individual control register offset addresses, see the MSP430F5xx and MSP430F6xx Family User's

Guide (SLAU208).

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Table 21. Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION

REGISTER

SFRIE1

OFFSET

SFR interrupt enable

SFR interrupt flag

00h

02h

04h

SFRIFG1

SFR reset pin control

SFRRPCR

Table 22. PMM Registers (Base Address: 0120h)

REGISTER DESCRIPTION

REGISTER

PMMCTL0

OFFSET

PMM Control 0

00h

02h

04h

06h

0Ch

0Eh

PMM control 1

PMMCTL1

SVSMHCTL

SVSMLCTL

PMMIFG

SVS high side control

SVS low side control

PMM interrupt flags

PMM interrupt enable

PMMIE

Table 23. Flash Control Registers (Base Address: 0140h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Flash control 1

Flash control 3

Flash control 4

FCTL1

FCTL3

FCTL4

00h

04h

06h

Table 24. CRC16 Registers (Base Address: 0150h)

REGISTER DESCRIPTION

REGISTER

CRC16DI

OFFSET

CRC data input

CRC result

00h

04h

CRC16INIRES

Table 25. RAM Control Registers (Base Address: 0158h)

REGISTER DESCRIPTION

REGISTER

RCCTL0

OFFSET

RAM control 0

00h

Table 26. Watchdog Registers (Base Address: 015Ch)

REGISTER DESCRIPTION

REGISTER

WDTCTL

Watchdog timer control

Table 27. UCS Registers (Base Address: 0160h)

REGISTER DESCRIPTION

REGISTER

UCSCTL0

UCS control 0

UCS control 1

UCS control 2

UCS control 3

UCS control 4

UCS control 5

UCS control 6

UCS control 7

UCS control 8

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

UCSCTL1

UCSCTL2

UCSCTL3

UCSCTL4

UCSCTL5

UCSCTL6

UCSCTL7

UCSCTL8

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SLAS650B –JUNE 2010–REVISED AUGUST 2011

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Table 28. SYS Registers (Base Address: 0180h)

REGISTER DESCRIPTION

REGISTER

SYSCTL

OFFSET

System control

00h

02h

06h

08h

0Ah

0Ch

0Eh

18h

1Ah

1Ch

1Eh

Bootstrap loader configuration area

JTAG mailbox control

SYSBSLC

SYSJMBC

SYSJMBI0

SYSJMBI1

SYSJMBO0

SYSJMBO1

SYSBERRIV

SYSUNIV

JTAG mailbox input 0

JTAG mailbox input 1

JTAG mailbox output 0

JTAG mailbox output 1

Bus Error vector generator

User NMI vector generator

System NMI vector generator

Reset vector generator

SYSSNIV

SYSRSTIV

Table 29. Shared Reference Registers (Base Address: 01B0h)

REGISTER DESCRIPTION

REGISTER

REFCTL

OFFSET

Shared reference control

00h

Table 30. Port Mapping Registers

(Base Address of Port Mapping Control: 01C0h, Port P2: 01D0h)

REGISTER DESCRIPTION

REGISTER

PMAPPWD

Port mapping password register

Port mapping control register

Port P2.0 mapping register

Port P2.1 mapping register

Port P2.2 mapping register

Port P2.3 mapping register

Port P2.4 mapping register

Port P2.5 mapping register

Port P2.6 mapping register

Port P2.7 mapping register

00h

02h

00h

01h

02h

03h

04h

05h

06h

07h

PMAPCTL

P2MAP0

P2MAP1

P2MAP2

P2MAP3

P2MAP4

P2MAP5

P2MAP6

P2MAP7

Table 31. Port P1/P2 Registers (Base Address: 0200h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P1 input

P1IN

00h

02h

04h

06h

08h

0Ah

0Eh

18h

1Ah

1Ch

01h

03h

05h

07h

09h

Port P1 output

P1OUT

P1DIR

P1REN

P1DS

P1SEL

P1IV

Port P1 direction

Port P1 pullup/pulldown enable

Port P1 drive strength

Port P1 selection

Port P1 interrupt vector word

Port P1 interrupt edge select

Port P1 interrupt enable

Port P1 interrupt flag

Port P2 input

P1IES

P1IE

P1IFG

P2IN

Port P2 output

P2OUT

P2DIR

P2REN

P2DS

Port P2 direction

Port P2 pullup/pulldown enable

Port P2 drive strength

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Table 31. Port P1/P2 Registers (Base Address: 0200h) (continued)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P2 selection

P2SEL

P2IV

0Bh

1Eh

19h

1Bh

1Dh

Port P2 interrupt vector word

Port P2 interrupt edge select

Port P2 interrupt enable

Port P2 interrupt flag

P2IES

P2IE

P2IFG

Table 32. Port P3/P4 Registers (Base Address: 0220h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P3 input

P3IN

00h

02h

04h

06h

08h

0Ah

0Eh

18h

1Ah

1Ch

01h

03h

05h

07h

09h

0Bh

1Eh

19h

1Bh

1Dh

Port P3 output

Port P3 direction

P3OUT

P3DIR

P3REN

P3DS

P3SEL

P3IV

Port P3 pullup/pulldown enable

Port P3 drive strength

Port P3 selection

Port P3 interrupt vector word

Port P3 interrupt edge select

Port P3 interrupt enable

Port P3 interrupt flag

P3IES

P3IE

P3IFG

P4IN

Port P4 input

Port P4 output

P4OUT

P4DIR

P4REN

P4DS

P4SEL

P4IV

Port P4 direction

Port P4 pullup/pulldown enable

Port P4 drive strength

Port P4 selection

Port P4 interrupt vector word

Port P4 interrupt edge select

Port P4 interrupt enable

Port P4 interrupt flag

P4IES

P4IE

P4IFG

Table 33. Port P5/P6 Registers (Base Address: 0240h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P5 input

P5IN

00h

02h

04h

06h

08h

0Ah

01h

03h

05h

07h

09h

0Bh

Port P5 output

P5OUT

P5DIR

P5REN

P5DS

Port P5 direction

Port P5 pullup/pulldown enable

Port P5 drive strength

Port P5 selection

P5SEL

P6IN

Port P6 input

Port P6 output

P6OUT

P6DIR

P6REN

P6DS

Port P6 direction

Port P6 pullup/pulldown enable

Port P6 drive strength

Port P6 selection

P6SEL

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SLAS650B –JUNE 2010–REVISED AUGUST 2011

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Table 34. Port P7/P8 Registers (Base Address: 0260h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P7 input

P7IN

00h

02h

04h

06h

08h

0Ah

01h

03h

05h

07h

09h

0Bh

Port P7 output

P7OUT

P7DIR

P7REN

P7DS

Port P7 direction

Port P7 pullup/pulldown enable

Port P7 drive strength

Port P7 selection

P7SEL

P8IN

Port P8 input

Port P8 output

P8OUT

P8DIR

P8REN

P8DS

Port P8 direction

Port P8 pullup/pulldown enable

Port P8 drive strength

Port P8 selection

P8SEL

Table 35. Port P9 Register (Base Address: 0280h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P9 input

P9IN

00h

02h

04h

06h

08h

0Ah

Port P9 output

P9OUT

P9DIR

P9REN

P9DS

Port P9 direction

Port P9 pullup/pulldown enable

Port P9 drive strength

Port P9 selection

P9SEL

Table 36. Port J Registers (Base Address: 0320h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port PJ input

PJIN

00h

02h

04h

06h

08h

Port PJ output

PJOUT

PJDIR

PJREN

PJDS

Port PJ direction

Port PJ pullup/pulldown enable

Port PJ drive strength

Table 37. TA0 Registers (Base Address: 0340h)

REGISTER DESCRIPTION

REGISTER

TA0CTL

OFFSET

TA0 control

00h

02h

04h

06h

08h

0Ah

10h

12h

14h

16h

18h

1Ah

20h

2Eh

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

Capture/compare control 3

Capture/compare control 4

TA0 counter register

TA0CCTL0

TA0CCTL1

TA0CCTL2

TA0CCTL3

TA0CCTL4

TA0R

Capture/compare register 0

Capture/compare register 1

Capture/compare register 2

Capture/compare register 3

Capture/compare register 4

TA0 expansion register 0

TA0 interrupt vector

TA0CCR0

TA0CCR1

TA0CCR2

TA0CCR3

TA0CCR4

TA0EX0

TA0IV

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Table 38. TA1 Registers (Base Address: 0380h)

REGISTER DESCRIPTION

REGISTER

OFFSET

TA1 control

TA1CTL

00h

02h

04h

06h

10h

12h

14h

16h

20h

2Eh

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

TA1 counter register

TA1CCTL0

TA1CCTL1

TA1CCTL2

TA1R

Capture/compare register 0

Capture/compare register 1

Capture/compare register 2

TA1 expansion register 0

TA1 interrupt vector

TA1CCR0

TA1CCR1

TA1CCR2

TA1EX0

TA1IV

Table 39. TB0 Registers (Base Address: 03C0h)

REGISTER DESCRIPTION

REGISTER

TB0CTL

OFFSET

TB0 control

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

12h

14h

16h

18h

1Ah

1Ch

1Eh

20h

2Eh

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

Capture/compare control 3

Capture/compare control 4

Capture/compare control 5

Capture/compare control 6

TB0 register

TB0CCTL0

TB0CCTL1

TB0CCTL2

TB0CCTL3

TB0CCTL4

TB0CCTL5

TB0CCTL6

TB0R

Capture/compare register 0

Capture/compare register 1

Capture/compare register 2

Capture/compare register 3

Capture/compare register 4

Capture/compare register 5

Capture/compare register 6

TB0 expansion register 0

TB0 interrupt vector

TB0CCR0

TB0CCR1

TB0CCR2

TB0CCR3

TB0CCR4

TB0CCR5

TB0CCR6

TB0EX0

TB0IV

Table 40. TA2 Registers (Base Address: 0400h)

REGISTER DESCRIPTION

REGISTER

TA2CTL

OFFSET

TA2 control

00h

02h

04h

06h

10h

12h

14h

16h

20h

2Eh

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

TA2 counter register

TA2CCTL0

TA2CCTL1

TA2CCTL2

TA2R

Capture/compare register 0

Capture/compare register 1

Capture/compare register 2

TA2 expansion register 0

TA2 interrupt vector

TA2CCR0

TA2CCR1

TA2CCR2

TA2EX0

TA2IV

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SLAS650B –JUNE 2010–REVISED AUGUST 2011

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Table 41. Battery Backup Registers (Base Address: 0480h)

REGISTER DESCRIPTION

REGISTER

BAKMEM0

OFFSET

Battery Backup Memory 0

Battery Backup Memory 1

Battery Backup Memory 2

Battery Backup Memory 3

Battery Backup Control

Battery Charger Control

00h

02h

04h

06h

1Ch

1Eh

BAKMEM1

BAKMEM2

BAKMEM3

BAKCTL

BAKCHCTL

Table 42. Real-Time Clock Registers (Base Address: 04A0h)

REGISTER DESCRIPTION

REGISTER

RTCCTL0

OFFSET

RTC control register 0

RTC control register 1

RTC control register 2

RTC control register 3

00h

01h

02h

03h

08h

0Ah

0Ch

0Dh

0Eh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Eh

RTCCTL1

RTCCTL2

RTCCTL3

RTCPS0CTL

RTCPS1CTL

RTCPS0

RTC prescaler 0 control register

RTC prescaler 1 control register

RTC prescaler 0

RTC prescaler 1

RTCPS1

RTC interrupt vector word

RTC seconds

RTCIV

RTCSEC

RTC minutes

RTCMIN

RTC hours

RTCHOUR

RTCDOW

RTCDAY

RTC day of week

RTC days

RTC month

RTCMON

RTCYEARL

RTCYEARH

RTCAMIN

RTCAHOUR

RTCADOW

RTCADAY

BIN2BCD

BCD2BIN

RTC year low

RTC year high

RTC alarm minutes

RTC alarm hours

RTC alarm day of week

RTC alarm days

Binary-to-BCD conversion register

BCD-to-binary conversion register

Table 43. 32-bit Hardware Multiplier Registers (Base Address: 04C0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

16-bit operand 1 – multiply

MPY

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

12h

14h

16h

16-bit operand 1 – signed multiply

16-bit operand 1 – multiply accumulate

16-bit operand 1 – signed multiply accumulate

16-bit operand 2

MPYS

MAC

MACS

OP2

16 × 16 result low word

RESLO

RESHI

16 × 16 result high word

16 × 16 sum extension register

SUMEXT

MPY32L

32-bit operand 1 – multiply low word

32-bit operand 1 – multiply high word

32-bit operand 1 – signed multiply low word

32-bit operand 1 – signed multiply high word

MPY32H

MPYS32L

MPYS32H

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Table 43. 32-bit Hardware Multiplier Registers (Base Address: 04C0h) (continued)

REGISTER DESCRIPTION

REGISTER

MAC32L

OFFSET

32-bit operand 1 – multiply accumulate low word

32-bit operand 1 – multiply accumulate high word

32-bit operand 1 – signed multiply accumulate low word

32-bit operand 1 – signed multiply accumulate high word

32-bit operand 2 – low word

18h

1Ah

1Ch

1Eh

20h

22h

24h

26h

28h

2Ah

2Ch

MAC32H

MACS32L

MACS32H

OP2L

32-bit operand 2 – high word

OP2H

32 × 32 result 0 – least significant word

32 × 32 result 1

RES0

RES1

32 × 32 result 2

RES2

32 × 32 result 3 – most significant word

MPY32 control register 0

RES3

MPY32CTL0

Table 44. DMA Registers (Base Address DMA General Control: 0500h,

DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA

Channel 4: 0550h, DMA Channel 5: 0560h)

REGISTER DESCRIPTION

DMA General Control: DMA module control 0

REGISTER

DMACTL0

OFFSET

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Ah

00h

02h

DMA General Control: DMA module control 1

DMA General Control: DMA module control 2

DMA General Control: DMA module control 3

DMA General Control: DMA module control 4

DMA General Control: DMA interrupt vector

DMA Channel 0 control

DMACTL1

DMACTL2

DMACTL3

DMACTL4

DMAIV

DMA0CTL

DMA0SAL

DMA0SAH

DMA0DAL

DMA0DAH

DMA0SZ

DMA Channel 0 source address low

DMA Channel 0 source address high

DMA Channel 0 destination address low

DMA Channel 0 destination address high

DMA Channel 0 transfer size

DMA Channel 1 control

DMA1CTL

DMA1SAL

DMA1SAH

DMA1DAL

DMA1DAH

DMA1SZ

DMA Channel 1 source address low

DMA Channel 1 source address high

DMA Channel 1 destination address low

DMA Channel 1 destination address high

DMA Channel 1 transfer size

DMA Channel 2 control

DMA2CTL

DMA2SAL

DMA2SAH

DMA2DAL

DMA2DAH

DMA2SZ

DMA Channel 2 source address low

DMA Channel 2 source address high

DMA Channel 2 destination address low

DMA Channel 2 destination address high

DMA Channel 2 transfer size

DMA Channel 3 control

DMA3CTL

DMA3SAL

DMA3SAH

DMA3DAL

DMA3DAH

DMA3SZ

DMA Channel 3 source address low

DMA Channel 3 source address high

DMA Channel 3 destination address low

DMA Channel 3 destination address high

DMA Channel 3 transfer size

DMA Channel 4 control

DMA4CTL

DMA4SAL

DMA Channel 4 source address low

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Table 44. DMA Registers (Base Address DMA General Control: 0500h,

DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA

Channel 4: 0550h, DMA Channel 5: 0560h) (continued)

REGISTER DESCRIPTION

DMA Channel 4 source address high

REGISTER

DMA4SAH

OFFSET

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Ah

DMA Channel 4 destination address low

DMA Channel 4 destination address high

DMA Channel 4 transfer size

DMA4DAL

DMA4DAH

DMA4SZ

DMA Channel 5 control

DMA5CTL

DMA5SAL

DMA5SAH

DMA5DAL

DMA5DAH

DMA5SZ

DMA Channel 5 source address low

DMA Channel 5 source address high

DMA Channel 5 destination address low

DMA Channel 5 destination address high

DMA Channel 5 transfer size

Table 45. USCI_A0 Registers (Base Address: 05C0h)

REGISTER DESCRIPTION

REGISTER

UCA0CTL0

OFFSET

USCI control 0

00h

01h

06h

07h

08h

0Ah

0Ch

0Eh

10h

12h

13h

1Ch

1Dh

1Eh

USCI control 1

UCA0CTL1

UCA0BR0

USCI baud rate 0

USCI baud rate 1

UCA0BR1

USCI modulation control

USCI status

UCA0MCTL

UCA0STAT

UCA0RXBUF

UCA0TXBUF

UCA0ABCTL

UCA0IRTCTL

UCA0IRRCTL

UCA0IE

USCI receive buffer

USCI transmit buffer

USCI LIN control

USCI IrDA transmit control

USCI IrDA receive control

USCI interrupt enable

USCI interrupt flags

USCI interrupt vector word

UCA0IFG

UCA0IV

Table 46. USCI_B0 Registers (Base Address: 05E0h)

REGISTER DESCRIPTION

REGISTER

UCB0CTL0

OFFSET

USCI synchronous control 0

USCI synchronous control 1

USCI synchronous bit rate 0

USCI synchronous bit rate 1

USCI synchronous status

USCI synchronous receive buffer

USCI synchronous transmit buffer

USCI I2C own address

00h

01h

06h

07h

0Ah

0Ch

0Eh

10h

12h

1Ch

1Dh

1Eh

UCB0CTL1

UCB0BR0

UCB0BR1

UCB0STAT

UCB0RXBUF

UCB0TXBUF

UCB0I2COA

UCB0I2CSA

UCB0IE

USCI I2C slave address

USCI interrupt enable

USCI interrupt flags

UCB0IFG

USCI interrupt vector word

UCB0IV

38

MSP430F563x

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SLAS650B –JUNE 2010–REVISED AUGUST 2011

Table 47. USCI_A1 Registers (Base Address: 0600h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI control 0

UCA1CTL0

UCA1CTL1

UCA1BR0

00h

01h

06h

07h

08h

0Ah

0Ch

0Eh

10h

12h

13h

1Ch

1Dh

1Eh

USCI control 1

USCI baud rate 0

USCI baud rate 1

UCA1BR1

USCI modulation control

USCI status

UCA1MCTL

UCA1STAT

UCA1RXBUF

UCA1TXBUF

UCA1ABCTL

UCA1IRTCTL

UCA1IRRCTL

UCA1IE

USCI receive buffer

USCI transmit buffer

USCI LIN control

USCI IrDA transmit control

USCI IrDA receive control

USCI interrupt enable

USCI interrupt flags

USCI interrupt vector word

UCA1IFG

UCA1IV

Table 48. USCI_B1 Registers (Base Address: 0620h)

REGISTER DESCRIPTION

REGISTER

UCB1CTL0

OFFSET

USCI synchronous control 0

USCI synchronous control 1

USCI synchronous bit rate 0

USCI synchronous bit rate 1

USCI synchronous status

USCI synchronous receive buffer

USCI synchronous transmit buffer

USCI I2C own address

00h

01h

06h

07h

0Ah

0Ch

0Eh

10h

12h

1Ch

1Dh

1Eh

UCB1CTL1

UCB1BR0

UCB1BR1

UCB1STAT

UCB1RXBUF

UCB1TXBUF

UCB1I2COA

UCB1I2CSA

UCB1IE

USCI I2C slave address

USCI interrupt enable

USCI interrupt flags

UCB1IFG

USCI interrupt vector word

UCB1IV

Table 49. ADC12_A Registers (Base Address: 0700h)

REGISTER DESCRIPTION

REGISTER

ADC12CTL0

OFFSET

Control register 0

00h

02h

04h

0Ah

0Ch

0Eh

10h

11h

12h

13h

14h

15h

16h

17h

18h

Control register 1

ADC12CTL1

ADC12CTL2

ADC12IFG

Control register 2

Interrupt-flag register

Interrupt-enable register

ADC12IE

Interrupt-vector-word register

ADC memory-control register 0

ADC memory-control register 1

ADC memory-control register 2

ADC memory-control register 3

ADC memory-control register 4

ADC memory-control register 5

ADC memory-control register 6

ADC memory-control register 7

ADC memory-control register 8

ADC12IV

ADC12MCTL0

ADC12MCTL1

ADC12MCTL2

ADC12MCTL3

ADC12MCTL4

ADC12MCTL5

ADC12MCTL6

ADC12MCTL7

ADC12MCTL8

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MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

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Table 49. ADC12_A Registers (Base Address: 0700h) (continued)

REGISTER DESCRIPTION

REGISTER

ADC12MCTL9

OFFSET

ADC memory-control register 9

ADC memory-control register 10

ADC memory-control register 11

ADC memory-control register 12

ADC memory-control register 13

ADC memory-control register 14

ADC memory-control register 15

Conversion memory 0

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

22h

24h

26h

28h

2Ah

2Ch

2Eh

30h

32h

34h

36h

38h

3Ah

3Ch

3Eh

ADC12MCTL10

ADC12MCTL11

ADC12MCTL12

ADC12MCTL13

ADC12MCTL14

ADC12MCTL15

ADC12MEM0

ADC12MEM1

ADC12MEM2

ADC12MEM3

ADC12MEM4

ADC12MEM5

ADC12MEM6

ADC12MEM7

ADC12MEM8

ADC12MEM9

ADC12MEM10

ADC12MEM11

ADC12MEM12

ADC12MEM13

ADC12MEM14

ADC12MEM15

Conversion memory 1

Conversion memory 2

Conversion memory 3

Conversion memory 4

Conversion memory 5

Conversion memory 6

Conversion memory 7

Conversion memory 8

Conversion memory 9

Conversion memory 10

Conversion memory 11

Conversion memory 12

Conversion memory 13

Conversion memory 14

Conversion memory 15

Table 50. DAC12_A Registers (Base Address: 0780h)

REGISTER DESCRIPTION

REGISTER

DAC12_0CTL0

OFFSET

DAC12_A channel 0 control register 0

DAC12_A channel 0 control register 1

DAC12_A channel 0 data register

00h

02h

04h

06h

08h

10h

12h

14h

16h

18h

1Eh

DAC12_0CTL1

DAC12_0DAT

DAC12_A channel 0 calibration control register

DAC12_A channel 0 calibration data register

DAC12_A channel 1 control register 0

DAC12_A channel 1 control register 1

DAC12_A channel 1 data register

DAC12_0CALCTL

DAC12_0CALDAT

DAC12_1CTL0

DAC12_1CTL1

DAC12_1DAT

DAC12_A channel 1 calibration control register

DAC12_A channel 1 calibration data register

DAC12_A interrupt vector word

DAC12_1CALCTL

DAC12_1CALDAT

DAC12IV

Table 51. Comparator_B Registers (Base Address: 08C0h)

REGISTER DESCRIPTION

REGISTER

CBCTL0

OFFSET

Comp_B control register 0

Comp_B control register 1

Comp_B control register 2

Comp_B control register 3

Comp_B interrupt register

00h

02h

04h

06h

0Ch

0Eh

CBCTL1

CBCTL2

CBCTL3

CBINT

Comp_B interrupt vector word

CBIV

40

MSP430F563x

www.ti.com

SLAS650B –JUNE 2010–REVISED AUGUST 2011

Table 52. USB Configuration Registers (Base Address: 0900h)

REGISTER DESCRIPTION

REGISTER

USBKEYID

OFFSET

USB key/ID

00h

02h

04h

08h

0Ah

10h

12h

14h

USB module configuration

USB PHY control

USBCNF

USBPHYCTL

USBPWRCTL

USBPWRVSR

USBPLLCTL

USBPLLDIV

USBPLLIR

USB power control

USB power voltage setting

USB PLL control

USB PLL divider

USB PLL interrupts

Table 53. USB Control Registers (Base Address: 0920h)

REGISTER DESCRIPTION

REGISTER

IEPCNF_0

OFFSET

Input endpoint#0 configuration

Input endpoint #0 byte count

Output endpoint#0 configuration

Output endpoint #0 byte count

Input endpoint interrupt enables

Output endpoint interrupt enables

Input endpoint interrupt flags

Output endpoint interrupt flags

USB interrupt vector

00h

01h

02h

03h

0Eh

0Fh

10h

11h

12h

16h

18h

1Ah

1Ch

1Dh

1Eh

1Fh

IEPCNT_0

OEPCNF_0

OEPCNT_0

IEPIE

OEPIE

IEPIFG

OEPIFG

USBIV

USB maintenance

MAINT

Time stamp

TSREG

USBFN

USBCTL

USBIE

USB frame number

USB control

USB interrupt enables

USB interrupt flags

USBIFG

FUNADR

Function address

41

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

Voltage applied at V_CCto V_SS

–0.3 V to 4.1 V

–0.3 V to V_CC+ 0.3 V

±2 mA

Voltage applied to any pin (excluding VCORE, VBUS, V18)⁽²⁾

Diode current at any device pin

(3)

Storage temperature range, T_stg

–55°C to 150°C

95°C

Maximum junction temperature, T_J

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V_SS. VCORE is for internal device usage only. No external dc loading or voltage should be applied.

(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

Thermal Packaging Characteristics

PARAMETER

VALUE

122

108

83

UNIT

QFP (PZ)

θ_JA

Junction-to-ambient thermal resistance, still air⁽¹⁾

°C/W

BGA (ZQW)

QFP (PZ)

θ_JC(TOP)

Junction-to-case (top) thermal resistance⁽²⁾

Junction-to-board thermal resistance⁽³⁾

°C/W

BGA (ZQW)

QFP (PZ)

72

98

θ_JB

BGA (ZQW)

76

(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(2) The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard

test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

Recommended Operating Conditions

MIN NOM

MAX UNIT

PMMCOREVx = 0

1.8

2.0

2.2

2.4

1.8

2.0

2.2

2.4

2.2

3.6

Supply voltage during program execution and flash

PMMCOREVx = 0, 1

PMMCOREVx = 0, 1, 2

PMMCOREVx = 0, 1, 2, 3

PMMCOREVx = 0

3.6

V

V_CC

programming (AVCC1 = DVCC1 = DVCC2 = DVCC3

(1)

3.6

= DV_CC= V_CC

)

3.6

Supply voltage during USB operation, USB PLL

disabled

PMMCOREVx = 0, 1

PMMCOREVx = 0, 1, 2

PMMCOREVx = 0, 1, 2, 3

PMMCOREVx = 2

USB_EN = 1, UPLLEN = 0

V_{CC, USB}

V

3.6

Supply voltage during USB operation, USB PLL

enabled⁽²⁾

USB_EN = 1, UPLLEN = 1

3.6

PMMCOREVx = 2, 3

2.4

Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 =

V_SS

0

V

DVSS2 = DVSS3 = V_SS

)

T_A= 0°C to 85°C

T_A= –40°C to 85°C

I version

1.55

1.70

1.20

–40

3.6

V

V_BAT,RTC

Backup-supply voltage with RTC operational

3.6

V_BAT,MEM

T_A

Backup-supply voltage with backup memory retained.

Operating free-air temperature

Operating junction temperature

Capacitance at pin VBAK

3.6

85

10

V

°C

nF

T_J

I version

–40

C_BAK

C_VCORE

1

4.7

Capacitor at VCORE

470

(1) It is recommended to power AV_CCand DV_CCfrom the same source. A maximum difference of 0.3 V between AV_CCand DV_CCcan be

tolerated during power up and operation.

(2) USB operation with USB PLL enabled requires PMMCOREVx ≥ 2 for proper operation.

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MSP430F563x

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SLAS650B –JUNE 2010–REVISED AUGUST 2011

Recommended Operating Conditions (continued)

MIN NOM

MAX UNIT

C_DVCC/C_VCORE

Capacitor ratio of DVCC to VCORE

10

PMMCOREVx = 0,

1.8 V ≤ V_CC≤ 3.6 V

(default condition)

0

8.0

PMMCOREVx = 1,

2 V ≤ V_CC≤ 3.6 V

Processor frequency (maximum MCLK frequency)^{(3) (4)}

(see Figure 1)

0

12.0

MHz

f_SYSTEM

PMMCOREVx = 2,

2.2 V ≤ V_CC≤ 3.6 V

16.0

20.0

PMMCOREVx = 3,

2.4 V ≤ V_CC≤ 3.6 V

f_{SYSTEM_USB}

USB_wait

Minimum processor frequency for USB operation

Wait state cycles during USB operation

1.5

MHz

16

cycles

(3) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the

specified maximum frequency.

(4) Modules may have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.

25

20

3

16

2, 3

2

12

8

1, 2

1, 2, 3

1

0

0, 1

0, 1, 2

0, 1, 2, 3

0

1.8

2.0

2.2

2.4

3.6

Supply Voltage - V

The numbers within the fields denote the supported PMMCOREVx settings.

Figure 1. Frequency vs Supply Voltage

43

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

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Electrical Characteristics

Active Mode Supply Current Into V_CCExcluding External Current

(2) (3)

over recommended operating free-air temperature (unless otherwise noted)⁽¹⁾

FREQUENCY (f_DCO= f_MCLK= f_SMCLK

8 MHz 12 MHz

TYP MAX TYP MAX

)

EXECUTION

MEMORY

PARAMETER

V_CC

PMMCOREVx

1 MHz

TYP MAX

0.32

20 MHz

TYP MAX

UNIT

0

1

2

3

0

1

2

3

0.36

2.1

2.4

2.5

2.7

1.0

1.2

1.3

1.4

2.4

0.36

0.37

0.39

0.18

0.20

0.22

0.23

3.6

3.8

4.0

I_{AM, Flash}

Flash

RAM

3 V

mA

6.6

3.6

0.21

1.2

1.7

2.0

2.1

1.9

I_{AM, RAM}

3 V

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load

capacitance are chosen to closely match the required 12.5 pF.

(3) Characterized with program executing typical data processing. USB disabled (VUSBEN = 0, SLDOEN = 0).

f_ACLK= 32786 Hz, f_DCO= f_MCLK= f_SMCLKat specified frequency.

XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.

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MSP430F563x

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Low-Power Mode Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

(2)

-40°C

TYP MAX

25°C

TYP MAX

75 87

60°C

TYP MAX

81

85°C

TYP MAX

99

PARAMETER

V_CC

PMMCOREVx

UNIT

µA

2.2 V

3 V

0

3

0

3

0

1

2

0

1

2

3

0

1

2

3

0

1

2

3

71

78

85

94

I_LPM0,1MHzLow-power mode 0⁽³⁾⁽⁴⁾

83

6.7

7.0

1.8

1.9

2.0

2.1

2.2

1.2

1.3

1.1

1.2

98

9.9

11

89

9.0

10

108

16

2.2 V

3 V

6.3

6.6

1.6

1.7

1.9

2.0

0.9

1.0

0.9

1.0

11

I_LPM2

Low-power mode 2⁽⁵⁾⁽⁴⁾

µA

12

18

2.4

4.7

4.8

4.9

5.0

5.1

5.2

5.4

4.0

4.1

4.2

4.3

3.9

4.0

4.1

4.2

6.5

6.6

6.7

6.8

7.0

7.1

7.3

5.9

6.0

6.1

6.3

5.8

5.9

6.1

6.2

10.5

2.2 V

Low-power mode 3,

crystal mode⁽⁶⁾⁽⁴⁾

I_LPM3,XT1LF

2.7

10.8

µA

3 V

2.9

1.9

12.6

10.3

Low-power mode 3,

VLO mode, Watchdog

enabled⁽⁷⁾⁽⁴⁾

I_LPM3,

VLO,WDT

3 V

2.2

1.8

11.3

10

I_LPM4

Low-power mode 4⁽⁸⁾⁽⁴⁾

3 V

µA

2.1

11

Low-power mode 3.5

(LPM3.5) current with

active RTC into primary

I_LPM3.5,

RTC,VCC

0.5

0.8

1.4

(9)

supply pin DV_CC

Low-power mode 3.5

(LPM3.5) current with

active RTC into backup

supply pin VBAT⁽¹⁰⁾

I_LPM3.5,

RTC,VBAT

3 V

0.6

1.1

0.8

1.6

1.4

2.8

µA

Total low-power mode

3.5 (LPM3.5) current

with active RTC⁽¹¹⁾

I_LPM3.5,

RTC,TOT

1.0

1.3

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external

load capacitance are chosen to closely match the required 9 pF.

(3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); f_ACLK= 32768 Hz, f_MCLK= 0 MHz, f_SMCLK= f_DCO= 1 MHz

USB disabled (VUSBEN = 0, SLDOEN = 0).

(4) Current for brownout included. Low side supervisor and monitors disabled (SVS_L, SVM_L). High side supervisor and monitor disabled

(SVS_H, SVM_H). RAM retention enabled.

(5) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation

(XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); f_ACLK= 32768 Hz, f_MCLK= 0 MHz, f_SMCLK= f_DCO= 0 MHz; DCO

setting = 1 MHz operation, DCO bias generator enabled.

USB disabled (VUSBEN = 0, SLDOEN = 0).

(6) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation

(XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); f_ACLK= 32768 Hz, f_MCLK= f_SMCLK= f_DCO= 0 MHz

USB disabled (VUSBEN = 0, SLDOEN = 0).

(7) Current for watchdog timer clocked by VLO included.

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); f_ACLK= f_MCLK= f_SMCLK= f_DCO= 0 MHz

USB disabled (VUSBEN = 0, SLDOEN = 0).

(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); f_DCO= f_ACLK= f_MCLK= f_SMCLK= 0 MHz

USB disabled (VUSBEN = 0, SLDOEN = 0).

(9) V_VBAT= V_CC- 0.2 V, f_DCO= f_MCLK= f_SMCLK= 0 MHz, f_ACLK= 32768 Hz, PMMREGOFF = 1, RTC in backup domain active

(10) V_VBAT= V_CC- 0.2 V, f_DCO= f_MCLK= f_SMCLK= 0 MHz, f_ACLK= 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no

current drawn on VBAK

(11) f_DCO= f_MCLK= f_SMCLK= 0 MHz, f_ACLK= 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no current drawn on VBAK

45

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

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Low-Power Mode Supply Currents (Into V_CC) Excluding External Current (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)^{(1) (2)}

-40°C

TYP MAX

25°C

TYP MAX

60°C

TYP MAX

85°C

TYP MAX

PARAMETER

V_CC

PMMCOREVx

UNIT

µA

Low-power mode 4.5

(LPM4.5)⁽¹²⁾

I_LPM4.5

3 V

0.2

0.3

0.6

0.7

0.9

1.4

(12) Internal regulator disabled. No data retention.

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5); f_DCO= f_ACLK= f_MCLK= f_SMCLK= 0 MHz

Schmitt-Trigger Inputs – General Purpose I/O⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

1.8 V

3 V

MIN

0.80

1.50

0.45

0.75

0.3

TYP

MAX UNIT

1.40

V

V_IT+

V_IT–

V_hys

Positive-going input threshold voltage

2.10

1.8 V

3 V

1.00

V

Negative-going input threshold voltage

1.65

1.8 V

3 V

0.8

V

Input voltage hysteresis (V_IT+– V_IT–

)

0.4

1.0

For pullup: V_IN= V_SS

For pulldown: V_IN= V_CC

R_Pull

C_I

Pullup/pulldown resistor

Input capacitance

20

35

5

50

kΩ

V_IN= V_SSor V_CC

pF

(1) Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).

Inputs – Ports P1, P2, P3, and P4⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

Port P1, P2, P3, P4: P1.x to P4.x, External trigger pulse

width to set interrupt flag

t_(int)

External interrupt timing⁽²⁾

2.2 V/3 V

20

ns

(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.

(2) An external signal sets the interrupt flag every time the minimum interrupt pulse width t_(int)is met. It may be set by trigger signals shorter

than t_(int)

.

Leakage Current – General Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

±50 nA

(1) (2)

I_lkg(Px.x)

High-impedance leakage current

1.8 V/3 V

(1) The leakage current is measured with V_SSor V_CCapplied to the corresponding pin(s), unless otherwise noted.

(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is

disabled.

Outputs – General Purpose I/O (Full Drive Strength)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_(OHmax)= –3 mA⁽¹⁾

I_(OHmax)= –10 mA⁽²⁾

I_(OHmax)= –5 mA⁽¹⁾

I_(OHmax)= –15 mA⁽²⁾

V_CC

MIN

_CC– 0.25

_CC– 0.60

_CC– 0.25

_CC– 0.60

MAX UNIT

V

V_CC

1.8 V

V_CC

V_OH

High-level output voltage

V

V_CC

3 V

V_CC

(1) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop

specified.

(2) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage

drop specified.

46

MSP430F563x

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SLAS650B –JUNE 2010–REVISED AUGUST 2011

Outputs – General Purpose I/O (Full Drive Strength) (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_(OLmax)= 3 mA⁽¹⁾

I_(OLmax)= 10 mA⁽²⁾

I_(OLmax)= 5 mA⁽¹⁾

I_(OLmax)= 15 mA⁽²⁾

V_CC

MIN

MAX UNIT

V_SSV_SS+ 0.25

V_SSV_SS+ 0.60

V_SSV_SS+ 0.25

V_SSV_SS+ 0.60

1.8 V

V_OL

Low-level output voltage

V

3 V

Outputs – General Purpose I/O (Reduced Drive Strength)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

I_(OHmax)= –1 mA⁽²⁾

V_CC

MIN

_CC– 0.25

_CC– 0.60

_CC– 0.25

_CC– 0.60

MAX UNIT

V

V_CC

1.8 V

I_(OHmax)= –3 mA⁽³⁾

I_(OHmax)= –2 mA⁽²⁾

I_(OHmax)= –6 mA⁽³⁾

I_(OLmax)= 1 mA⁽²⁾

I_(OLmax)= 3 mA⁽³⁾

I_(OLmax)= 2 mA⁽²⁾

I_(OLmax)= 6 mA⁽³⁾

V_CC

V_OH

High-level output voltage

V

V_CC

3 V

1.8 V

3 V

V_CC

V_SSV_SS+ 0.25

V_SSV_SS+ 0.60

V_SSV_SS+ 0.25

V_SSV_SS+ 0.60

V_OL

Low-level output voltage

V

(1) Selecting reduced drive strength may reduce EMI.

(2) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop

specified.

(3) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage

drop specified.

Output Frequency – Ports P1, P2 and P3

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX UNIT

V_CC= 1.8 V

PMMCOREVx = 0

8

Port output frequency

(with load)

P3.4/TA2CLK/SMCLK/S27

f_Px.y

MHz

20

C_L= 20 pF, R_L= 1 kΩ ⁽¹⁾or 3.2 kΩ^{(2) (3)}

V_CC= 3 V

PMMCOREVx = 3

V_CC= 1.8 V

PMMCOREVx = 0

P1.0/TA0CLK/ACLK/S39

P3.4/TA2CLK/SMCLK/S27

P2.0/P2MAP0 (P2MAP0 = PM_MCLK )

C_L= 20 pF⁽³⁾

8

f_{Port_CLK}

Clock output frequency

MHz

20

V_CC= 3 V

PMMCOREVx = 3

(1) Full drive strength of port: A resistive divider with 2 × 0.5 kΩ between V_CCand V_SSis used as load. The output is connected to the

center tap of the divider.

(2) Reduced drive strength of port: A resistive divider with 2 × 1.6 kΩ between V_CCand V_SSis used as load. The output is connected to the

center tap of the divider.

(3) The output voltage reaches at least 10% and 90% V_CCat the specified toggle frequency.

47

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

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Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TYPICAL LOW-LEVEL OUTPUT CURRENT

vs

LOW-LEVEL OUTPUT VOLTAGE

25.0

20.0

15.0

10.0

5.0

8.0

7.0

6.0

5.0

4.0

3.0

2.0

1.0

0.0

V_CC= 3.0 V

P3.2

V_CC= 1.8 V

P3.2

T_A= 25°C

T_A= 85°C

T_A= 25°C

T_A= 85°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

V_OL– Low-Level Output Voltage – V

Figure 2.

Figure 3.

TYPICAL HIGH-LEVEL OUTPUT CURRENT

vs

HIGH-LEVEL OUTPUT VOLTAGE

0.0

−1.0

−2.0

−3.0

−4.0

−5.0

−6.0

−7.0

−8.0

0.0

−5.0

V_CC= 1.8 V

P3.2

V_CC= 3.0 V

P3.2

−10.0

−15.0

−20.0

−25.0

T_A= 85°C

T_A= 25°C

T_A= 85°C

T_A= 25°C

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

V_OH– High-Level Output Voltage – V

Figure 4.

Figure 5.

48

MSP430F563x

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Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TYPICAL LOW-LEVEL OUTPUT CURRENT

vs

LOW-LEVEL OUTPUT VOLTAGE

60.0

55.0

50.0

45.0

40.0

35.0

30.0

25.0

20.0

15.0

10.0

5.0

24

20

16

12

8

V_CC= 1.8 V

P3.2

V_CC= 3.0 V

P3.2

T_A= 25°C

T_A= 85°C

T_A= 25°C

T_A= 85°C

4

0

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

V_OL– Low-Level Output Voltage – V

Figure 6.

Figure 7.

TYPICAL HIGH-LEVEL OUTPUT CURRENT

vs

HIGH-LEVEL OUTPUT VOLTAGE

0

0.0

−5.0

V_CC= 1.8 V

P3.2

V_CC= 3.0 V

P3.2

−10.0

−15.0

−20.0

−25.0

−30.0

−35.0

−40.0

−45.0

−50.0

−55.0

−60.0

−4

−8

−12

−16

−20

T_A= 85°C

T_A= 25°C

T_A= 85°C

T_A= 25°C

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

V_OH– High-Level Output Voltage – V

Figure 8.

Figure 9.

49

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

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MAX UNIT

Crystal Oscillator, XT1, Low-Frequency Mode⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 1,

T_A= 25°C

0.075

Differential XT1 oscillator crystal

f_OSC= 32768 Hz, XTS = 0,

ΔI_DVCC,LF

current consumption from lowest XT1BYPASS = 0, XT1DRIVEx = 2,

3 V

0.170

µA

drive setting, LF mode

T_A= 25°C

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 3,

T_A= 25°C

0.290

XT1 oscillator crystal frequency,

LF mode

f_XT1,LF0

XTS = 0, XT1BYPASS = 0

32768

Hz

XT1 oscillator logic-level

square-wave input frequency,

LF mode

f_XT1,LF,SW

XTS = 0, XT1BYPASS = 1^{(2) (3)}

10 32.768

210

50 kHz

XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 0,

f_XT1,LF= 32768 Hz, C_L,eff= 6 pF

Oscillation allowance for

LF crystals⁽⁴⁾

OA_LF

kΩ

XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 1,

f_XT1,LF= 32768 Hz, C_L,eff= 12 pF

300

XTS = 0, XCAPx = 0⁽⁶⁾

XTS = 0, XCAPx = 1

XTS = 0, XCAPx = 2

XTS = 0, XCAPx = 3

2

5.5

Integrated effective load

capacitance, LF mode⁽⁵⁾

C_L,eff

pF

8.5

12.0

XTS = 0, Measured at ACLK,

f_XT1,LF= 32768 Hz

Duty cycle, LF mode

30

10

70

%

Oscillator fault frequency,

LF mode⁽⁷⁾

f_Fault,LF

XTS = 0⁽⁸⁾

10000

Hz

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 0,

T_A= 25°C,

1000

500

C_L,eff= 6 pF

t_START,LF

Startup time, LF mode

3 V

ms

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 3,

T_A= 25°C,

C_L,eff= 12 pF

(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.

(a) Keep the trace between the device and the crystal as short as possible.

(b) Design a good ground plane around the oscillator pins.

(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.

(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

(2) When XT1BYPASS is set, XT1 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined in

the Schmitt-trigger Inputs section of this datasheet.

(3) Maximum frequency of operation of the entire device cannot be exceeded.

(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the

XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following

guidelines, but should be evaluated based on the actual crystal selected for the application:

(a) For XT1DRIVEx = 0, C_{L,ef f}≤ 6 pF.

(b) For XT1DRIVEx = 1, 6 pF ≤ C_{L,ef f}≤ 9 pF.

(c) For XT1DRIVEx = 2, 6 pF ≤ C_{L,ef f}≤ 10 pF.

(d) For XT1DRIVEx = 3, C_{L,ef f}≥ 6 pF.

(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a

correct setup, the effective load capacitance should always match the specification of the used crystal.

(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(8) Measured with logic-level input frequency but also applies to operation with crystals.

50

MSP430F563x

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Crystal Oscillator, XT2

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

(2)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

f_OSC= 4 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 0,

T_A= 25°C

200

f_OSC= 12 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 1,

T_A= 25°C

260

325

450

XT2 oscillator crystal current

consumption

I_DVCC,XT2

3 V

µA

f_OSC= 20 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 2,

T_A= 25°C

f_OSC= 32 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 3,

T_A= 25°C

XT2 oscillator crystal frequency,

mode 0

f_XT2,HF0

f_XT2,HF1

f_XT2,HF2

f_XT2,HF3

f_XT2,HF,SW

XT2DRIVEx = 0, XT2BYPASS = 0⁽³⁾

XT2DRIVEx = 1, XT2BYPASS = 0⁽³⁾

XT2DRIVEx = 2, XT2BYPASS = 0⁽³⁾

XT2DRIVEx = 3, XT2BYPASS = 0⁽³⁾

XT2BYPASS = 1^{(4) (3)}

4

8

MHz

XT2 oscillator crystal frequency,

mode 1

16 MHz

24 MHz

32 MHz

XT2 oscillator crystal frequency,

mode 2

16

24

0.7

XT2 oscillator crystal frequency,

mode 3

XT2 oscillator logic-level

square-wave input frequency

XT2DRIVEx = 0, XT2BYPASS = 0,

f_XT2,HF0= 6 MHz, C_L,eff= 15 pF

450

320

200

XT2DRIVEx = 1, XT2BYPASS = 0,

f_XT2,HF1= 12 MHz, C_L,eff= 15 pF

Oscillation allowance for

HF crystals⁽⁵⁾

OA_HF

Ω

XT2DRIVEx = 2, XT2BYPASS = 0,

f_XT2,HF2= 20 MHz, C_L,eff= 15 pF

XT2DRIVEx = 3, XT2BYPASS = 0,

f_XT2,HF3= 32 MHz, C_L,eff= 15 pF

f_OSC= 6 MHz

XT2BYPASS = 0, XT2DRIVEx = 0,

T_A= 25°C,

C_L,eff= 15 pF

0.5

0.3

t_START,HF

Startup time

3 V

ms

pF

f_OSC= 20 MHz

XT2BYPASS = 0, XT2DRIVEx = 3,

T_A= 25°C,

C_L,eff= 15 pF

Integrated effective load

C_L,eff

1

capacitance, HF mode^{(6) (1)}

Duty cycle

Oscillator fault frequency⁽⁷⁾

Measured at ACLK, f_XT2,HF2= 20 MHz

XT2BYPASS = 1⁽⁸⁾

40

30

50

60

%

f_Fault,HF

300 kHz

(1) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

(2) To improve EMI on the XT2 oscillator the following guidelines should be observed.

(a) Keep the traces between the device and the crystal as short as possible.

(b) Design a good ground plane around the oscillator pins.

(c) Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.

(d) Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.

(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.

(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

(3) Maximum frequency of operation of the entire device cannot be exceeded.

(4) When XT2BYPASS is set, the XT2 circuit is automatically powered down.

(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.

(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a

correct setup, the effective load capacitance should always match the specification of the used crystal.

(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(8) Measured with logic-level input frequency but also applies to operation with crystals.

51

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Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

VLO frequency

VLO frequency temperature drift

TEST CONDITIONS

V_CC

MIN

TYP

9.4

0.5

4

MAX UNIT

14 kHz

%/°C

f_VLO

Measured at ACLK

1.8 V to 3.6 V

6

df_VLO/d_T

Measured at ACLK⁽¹⁾

Measured at ACLK⁽²⁾

Measured at ACLK

df_VLO/dV_CCVLO frequency supply voltage drift

Duty cycle

%/V

40

50

60

%

(1) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))

(2) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)

Internal Reference, Low-Frequency Oscillator (REFO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

3

MAX UNIT

REFO oscillator current

consumption

I_REFO

T_A= 25°C

1.8 V to 3.6 V

µA

REFO frequency calibrated

Measured at ACLK

Full temperature range

T_A= 25°C

1.8 V to 3.6 V

3 V

32768

Hz

f_REFO

±3.5

±1.5

%

REFO absolute tolerance

calibrated

df_REFO/d_T

REFO frequency temperature drift Measured at ACLK⁽¹⁾

1.8 V to 3.6 V

0.01

1.0

%/°C

REFO frequency supply voltage

Measured at ACLK⁽²⁾

drift

df_REFO/dV_CC

1.8 V to 3.6 V

%/V

Duty cycle

Measured at ACLK

40%/60% duty cycle

1.8 V to 3.6 V

40

50

25

60

%

t_START

REFO startup time

µs

(1) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))

(2) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)

52

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DCO Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

DCORSELx = 0, DCOx = 0, MODx = 0

DCORSELx = 0, DCOx = 31, MODx = 0

DCORSELx = 1, DCOx = 0, MODx = 0

DCORSELx = 1, DCOx = 31, MODx = 0

DCORSELx = 2, DCOx = 0, MODx = 0

DCORSELx = 2, DCOx = 31, MODx = 0

DCORSELx = 3, DCOx = 0, MODx = 0

DCORSELx = 3, DCOx = 31, MODx = 0

DCORSELx = 4, DCOx = 0, MODx = 0

DCORSELx = 4, DCOx = 31, MODx = 0

DCORSELx = 5, DCOx = 0, MODx = 0

DCORSELx = 5, DCOx = 31, MODx = 0

DCORSELx = 6, DCOx = 0, MODx = 0

DCORSELx = 6, DCOx = 31, MODx = 0

DCORSELx = 7, DCOx = 0, MODx = 0

DCORSELx = 7, DCOx = 31, MODx = 0

MIN

0.07

0.70

0.15

1.47

0.32

3.17

0.64

6.07

1.3

TYP

MAX UNIT

0.20 MHz

1.70 MHz

0.36 MHz

3.45 MHz

0.75 MHz

7.38 MHz

1.51 MHz

14.0 MHz

3.2 MHz

f_DCO(0,0)

f_DCO(0,31)

f_DCO(1,0)

f_DCO(1,31)

f_DCO(2,0)

f_DCO(2,31)

f_DCO(3,0)

f_DCO(3,31)

f_DCO(4,0)

f_DCO(4,31)

f_DCO(5,0)

f_DCO(5,31)

f_DCO(6,0)

f_DCO(6,31)

f_DCO(7,0)

f_DCO(7,31)

DCO frequency (0, 0)

DCO frequency (0, 31)

DCO frequency (1, 0)

DCO frequency (1, 31)

DCO frequency (2, 0)

DCO frequency (2, 31)

DCO frequency (3, 0)

DCO frequency (3, 31)

DCO frequency (4, 0)

DCO frequency (4, 31)

DCO frequency (5, 0)

DCO frequency (5, 31)

DCO frequency (6, 0)

DCO frequency (6, 31)

DCO frequency (7, 0)

DCO frequency (7, 31)

12.3

2.5

28.2 MHz

6.0 MHz

23.7

4.6

54.1 MHz

10.7 MHz

88.0 MHz

19.6 MHz

135 MHz

39.0

8.5

60

Frequency step between range

DCORSEL and DCORSEL + 1

S_DCORSEL

S_DCO

S_RSEL= f_{DCO(DCORSEL+1,DCO)}/f_{DCO(DCORSEL,DCO)}

1.2

2.3 ratio

Frequency step between tap

DCO and DCO + 1

S_DCO= f_{DCO(DCORSEL,DCO+1)}/f_{DCO(DCORSEL,DCO)}

1.02

40

1.12 ratio

Duty cycle

df_DCO/dT

Measured at SMCLK

DCO frequency temperature drift f_DCO= 1 MHz,

50

0.1

1.9

60

%

%/°C

%/V

df_DCO/dV_CC

DCO frequency voltage drift

f_DCO= 1 MHz

Typical DCO Frequency, V_CC= 3.0 V,T_A= 25°C

100

10

DCOx = 31

1

DCOx = 0

0.1

0

1

2

3

4

5

6

7

DCORSEL

Figure 10. Typical DCO frequency

53

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

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MAX UNIT

PMM, Brown-Out Reset (BOR)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

| dDV_CC/d_t| < 3 V/s

MIN

TYP

BOR_Hon voltage,

DV_CCfalling level

V(DV_CC_BOR_IT–)

1.45

V

BOR_Hoff voltage,

DV_CCrising level

V(DV_CC_BOR_IT+)

0.80

60

1.30

1.50

250

V

V(DV_CC_BOR_hys) BOR_Hhysteresis

Pulse length required at

mV

t_RESET

RST/NMI pin to accept a

reset

2

µs

PMM, Core Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Core voltage, active

mode, PMMCOREV = 3

V_CORE3(AM)

V_CORE2(AM)

V_CORE1(AM)

V_CORE0(AM)

V_CORE3(LPM)

V_CORE2(LPM)

V_CORE1(LPM)

V_CORE0(LPM)

2.4 V ≤ DV_CC≤ 3.6 V, 0 mA ≤ I(V_CORE) ≤ 21 mA

1.90

V

Core voltage, active

mode, PMMCOREV = 2

2.2 V ≤ DV_CC≤ 3.6 V, 0 mA ≤ I(V_CORE) ≤ 21 mA

2 V ≤ DV_CC≤ 3.6 V, 0 mA ≤ I(V_CORE) ≤ 17 mA

1.8 V ≤ DV_CC≤ 3.6 V, 0 mA ≤ I(V_CORE) ≤ 13 mA

2.4 V ≤ DV_CC≤ 3.6 V, 0 µA ≤ I(V_CORE) ≤ 30 µA

2.2 V ≤ DV_CC≤ 3.6 V, 0 µA ≤ I(V_CORE) ≤ 30 µA

2 V ≤ DV_CC≤ 3.6 V, 0 µA ≤ I(V_CORE) ≤ 30 µA

1.8 V ≤ DV_CC≤ 3.6 V, 0 µA ≤ I(V_CORE) ≤ 30 µA

1.80

1.60

1.40

1.94

1.84

1.64

1.44

V

Core voltage, active

mode, PMMCOREV = 1

Core voltage, active

mode, PMMCOREV = 0

Core voltage, low-current

mode, PMMCOREV = 3

Core voltage, low-current

mode, PMMCOREV = 2

Core voltage, low-current

mode, PMMCOREV = 1

Core voltage, low-current

mode, PMMCOREV = 0

PMM, SVS High Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SVSHE = 0, DV_CC= 3.6 V

MIN

TYP

0

MAX UNIT

nA

I_(SVSH)

SVS current consumption

SVSHE = 1, DV_CC= 3.6 V, SVSHFP = 0

SVSHE = 1, DV_CC= 3.6 V, SVSHFP = 1

SVSHE = 1, SVSHRVL = 0

200

2.0

µA

1.59

1.79

1.98

2.10

1.62

1.88

2.07

2.20

2.32

2.56

2.85

1.64

1.84

2.04

2.16

1.74

1.94

2.14

2.26

2.40

2.70

3.00

1.69

SVSHE = 1, SVSHRVL = 1

1.91

V

V_{(SVSH_IT–)}

SVS_Hon voltage level⁽¹⁾

SVSHE = 1, SVSHRVL = 2

2.11

SVSHE = 1, SVSHRVL = 3

2.23

1.81

2.01

2.21

SVSHE = 1, SVSMHRRL = 0

SVSHE = 1, SVSMHRRL = 1

SVSHE = 1, SVSMHRRL = 2

SVSHE = 1, SVSMHRRL = 3

SVSHE = 1, SVSMHRRL = 4

SVSHE = 1, SVSMHRRL = 5

SVSHE = 1, SVSMHRRL = 6

SVSHE = 1, SVSMHRRL = 7

2.33

V

V_{(SVSH_IT+)}

SVS_Hoff voltage level⁽¹⁾

2.48

2.84

3.15

(1) The SVS_Hsettings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage

Supervisor chapter in the MSP430F5xx/MSP430F6xx Family User's Guide (SLAU208) on recommended settings and usage.

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PMM, SVS High Side (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SVSHE = 1, dV_DVCC/dt = 10 mV/µs,

SVSHFP = 1

2.5

t_pd(SVSH)

SVS_Hpropagation delay

µs

SVSHE = 1, dV_DVCC/dt = 1 mV/µs,

SVSHFP = 0

20

12.5

100

SVSHE = 0→1,

SVSHFP = 1

t_(SVSH)

SVS_Hon/off delay time

DV_CCrise time

µs

SVSHE = 0→1,

SVSHFP = 0

dV_DVCC/dt

0

1000

V/s

PMM, SVM High Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SVMHE = 0, DV_CC= 3.6 V

MIN

TYP

0

MAX UNIT

nA

I_(SVMH)

SVM_Hcurrent consumption

SVMHE = 1, DV_CC= 3.6 V, SVMHFP = 0

SVMHE = 1, DV_CC= 3.6 V, SVMHFP = 1

SVMHE = 1, SVSMHRRL = 0

SVMHE = 1, SVSMHRRL = 1

SVMHE = 1, SVSMHRRL = 2

SVMHE = 1, SVSMHRRL = 3

SVMHE = 1, SVSMHRRL = 4

SVMHE = 1, SVSMHRRL = 5

SVMHE = 1, SVSMHRRL = 6

SVMHE = 1, SVSMHRRL = 7

SVMHE = 1, SVMHOVPE = 1

200

2.0

nA

µA

1.65

1.85

2.02

2.18

2.32

2.56

2.85

1.74

1.94

2.14

2.26

2.40

2.70

3.00

3.75

1.86

2.02

2.22

2.35

V_(SVMH)

SVM_Hon/off voltage level⁽¹⁾

2.48

2.84

3.15

V

SVMHE = 1, dV_DVCC/dt = 10 mV/µs,

SVMHFP = 1

2.5

20

µs

t_pd(SVMH)

SVM_Hpropagation delay

SVM_Hon/off delay time

SVMHE = 1, dV_DVCC/dt = 1 mV/µs,

SVMHFP = 0

SVMHE = 0→1,

SVSMFP = 1

12.5

100

t_(SVMH)

SVMHE = 0→1,

SVMHFP = 0

(1) The SVM_Hsettings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage

Supervisor chapter in the MSP430F5xx/MSP430F6xx Family User's Guide (SLAU208) on recommended settings and usage.

PMM, SVS Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SVSLE = 0, PMMCOREV = 2

MIN

TYP

0

MAX UNIT

nA

µA

I_(SVSL)

SVS_Lcurrent consumption

SVSLE = 1, PMMCOREV = 2, SVSLFP = 0

SVSLE = 1, PMMCOREV = 2, SVSLFP = 1

200

2.0

SVSLE = 1, dV_CORE/dt = 10 mV/µs,

SVSLFP = 1

2.5

20

t_pd(SVSL)

SVS_Lpropagation delay

SVS_Lon/off delay time

µs

SVSLE = 1, dV_CORE/dt = 1 mV/µs,

SVSLFP = 0

SVSLE = 0→1,

SVSLFP = 1

12.5

100

t_(SVSL)

SVSLE = 0→1,

SVSLFP = 0

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PMM, SVM Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SVMLE = 0, PMMCOREV = 2

MIN

TYP

0

MAX UNIT

nA

µA

I_(SVML)

SVM_Lcurrent consumption

SVMLE = 1, PMMCOREV = 2, SVMLFP = 0

SVMLE = 1, PMMCOREV = 2, SVMLFP = 1

200

2.0

SVMLE = 1, dV_CORE/dt = 10 mV/µs,

SVMLFP = 1

2.5

20

t_pd(SVML)

SVM_Lpropagation delay

SVM_Lon/off delay time

µs

SVMLE = 1, dV_CORE/dt = 1 mV/µs,

SVMLFP = 0

SVMLE = 0→1,

SVMLFP = 1

12.5

100

t_(SVML)

SVMLE = 0→1,

SVMLFP = 0

Wake-Up From Low-Power Modes and Reset

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

f

_MCLK≥ 4 MHz

3

6.5

PMMCOREV = SVSMLRRL = n

(where n = 0, 1, 2, or 3),

SVSLFP = 1

Wake-up time from LPM2,

LPM3, or LPM4 to active

mode⁽¹⁾

t_WAKE-UP-FAST

µs

1 MHz < f_MCLK

4 MHz

<

4

8.0

PMMCOREV = SVSMLRRL = n

(where n = 0, 1, 2, or 3),

SVSLFP = 0

Wake-up time from LPM2,

LPM3 or LPM4 to active

mode⁽²⁾

t_WAKE-UP-SLOW

150

165

µs

Wake-up time from LPM3.5 or

LPM4.5 to active mode⁽³⁾

t_WAKE-UP-LPM5

t_{WAKE-UP-RESET}

2

3

ms

Wake-up time from RST or

BOR event to active mode⁽³⁾

(1) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance

mode of the low side supervisor (SVS_L) and low side monitor (SVM_L). Fastest wakeup times are possible with SVS_Land SVM_Lin full

performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVS_Land SVM_Lwhile

operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx

Family User's Guide (SLAU208).

(2) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance

mode of the low side supervisor (SVS_L) and low side monitor (SVM_L). In this case, the SVS_Land SVM_Lare in normal mode (low current)

mode when operating in AM, LPM0, and LPM1. Various options are available for SVS_Land SVM_Lwhile operating in LPM2, LPM3, and

LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx Family User's Guide

(SLAU208).

(3) This value represents the time from the wakeup event to the reset vector execution.

Timer_A, Timers TA0, TA1, and TA2

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK

f_TA

Timer_A input clock frequency

External: TACLK

1.8 V/ 3 V

20 MHz

Duty cycle = 50% ± 10%

All capture inputs.

t_TA,cap

Timer_A capture timing

Minimum pulse width required for

capture.

1.8 V/ 3 V

20

ns

Timer_B, Timer TB0

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK

f_TB

Timer_B input clock frequency

External: TBCLK

1.8 V/ 3 V

20 MHz

Duty cycle = 50% ± 10%

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Timer_B, Timer TB0 (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

All capture inputs.

t_TB,cap

Timer_B capture timing

Minimum pulse width required for

capture.

1.8 V/ 3 V

20

ns

Battery Backup

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

T_A= -40°C

0.43

0.52

VBAT = 1.7 V,

T_A= 25°C

T_A= 60°C

T_A= 85°C

T_A= -40°C

T_A= 25°C

T_A= 60°C

T_A= 85°C

T_A= -40°C

T_A= 25°C

T_A= 60°C

T_A= 85°C

General

DVCC not connected,

RTC running

µA

0.58

0.64

0.50

Current into VBAT terminal in VBAT = 2.2 V,

0.59

I_VBAT

case no primary battery is

connected.

DVCC not connected,

RTC running

µA

0.64

0.71

0.68

VBAT = 3 V,

0.75

DVCC not connected,

RTC running

µA

0.79

0.86

V_{SVSH_IT-}

SVSHRL = 0

SVSHRL = 1

SVSHRL = 2

SVSHRL = 3

1.59

1.79

1.98

2.10

1.69

Switch-over level (V_CCto

VBAT)

V_SWITCH

C_VCC= 4.7 µF

1.91

2.11

2.23

1

V

On-resistance of switch

between VBAT and VBAK

0.35

R_{ON_VBAT}

V_BAT= 1.8 V

0 V

kΩ

1.8 V

3 V

0.6

1.0

1.2

±5%

VBAT to ADC:

V_BATdivide,

V_BAT3≠ V_BAT/3

V_BAT3

V

3.6 V

t_Sample,VBAVBAT to ADC: Sampling time ADC12ON = 1,

1000

2.65

ns

V

required if VBAT3 selected

Error of conversion result ≤ 1 LSB

T3

V_CHVx

Charger end voltage

CHVx = 2

2.7

2.9

5

CHCx = 1

CHCx = 2

CHCx = 3

R_CHARGE

Charge limiting resistor

10

20

kΩ

USCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK

f_USCI

USCI input clock frequency

External: UCLK

f_SYSTEMMHz

Duty cycle = 50% ± 10%

BITCLK clock frequency

(equals baud rate in MBaud)

f_BITCLK

t_τ

1

MHz

ns

2.2 V

3 V

50

600

UART receive deglitch time⁽¹⁾

(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are

correctly recognized their width should exceed the maximum specification of the deglitch time.

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USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(see Note ⁽¹⁾, Figure 11 and )

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

SMCLK, ACLK,

Duty cycle = 50% ± 10%

f_USCI

USCI input clock frequency

f_SYSTEMMHz

1.8 V

3 V

55

38

30

25

0

PMMCOREV = 0

ns

t_SU,MI

SOMI input data setup time

SOMI input data hold time

2.4 V

3 V

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

1.8 V

3 V

0

t_HD,MI

2.4 V

3 V

0

ns

0

UCLK edge to SIMO valid,

C_L= 20 pF,

PMMCOREV = 0

1.8 V

20

ns

3 V

2.4 V

3 V

18

t_VALID,MO

SIMO output data valid time⁽²⁾

SIMO output data hold time⁽³⁾

UCLK edge to SIMO valid,

C_L= 20 pF,

PMMCOREV = 3

16

ns

15

1.8 V

3 V

-10

-8

C_L= 20 pF,

PMMCOREV = 0

ns

t_HD,MO

2.4 V

3 V

-10

-8

C_L= 20 pF,

PMMCOREV = 3

(1) f_UCxCLK= 1/2t_LO/HIwith t_LO/HI≥ max(t_{VALID,MO(USCI)}+ t_SU,SI(Slave), t_SU,MI(USCI)+ t_{VALID,SO(Slave)}).

For the slave's parameters t_SU,SI(Slave)and t_{VALID,SO(Slave)}, see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing

diagrams in Figure 11 and .

(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data

on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in

Figure 11 and .

1/f_UCxCLK

CKPL = 0

UCLK

CKPL = 1

t_LO/HI

t_SU,MI

t_HD,MI

SOMI

t_HD,MO

t_VALID,MO

SIMO

Figure 11. SPI Master Mode, CKPH = 0

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1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_LO/HI

t_HD,MI

t_SU,MI

SOMI

t_HD,MO

t_VALID,MO

SIMO

Figure 12. SPI Master Mode, CKPH = 1

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USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(see Note ⁽¹⁾, Figure 13 and Figure 14)

PARAMETER

TEST CONDITIONS

V_CC

1.8 V

3 V

MIN

11

8

TYP

MAX UNIT

PMMCOREV = 0

ns

t_STE,LEAD

t_STE,LAG

t_STE,ACC

t_STE,DIS

t_SU,SI

STE lead time, STE low to clock

2.4 V

3 V

7

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

ns

6

1.8 V

3 V

3

STE lag time, Last clock to STE high

2.4 V

3 V

3

1.8 V

3 V

66

ns

50

STE access time, STE low to SOMI data out

2.4 V

3 V

36

ns

30

1.8 V

3 V

30

ns

23

STE disable time, STE high to SOMI high

impedance

2.4 V

3 V

16

ns

13

1.8 V

3 V

5

2

5

ns

SIMO input data setup time

SIMO input data hold time

2.4 V

3 V

1.8 V

3 V

t_HD,SI

2.4 V

3 V

ns

UCLK edge to SOMI valid,

C_L= 20 pF,

PMMCOREV = 0

1.8 V

76

ns

3 V

2.4 V

3 V

60

t_VALID,SO

SOMI output data valid time⁽²⁾

SOMI output data hold time⁽³⁾

UCLK edge to SOMI valid,

C_L= 20 pF,

PMMCOREV = 3

44

ns

40

1.8 V

3 V

18

12

10

8

C_L= 20 pF,

PMMCOREV = 0

ns

t_HD,SO

2.4 V

3 V

C_L= 20 pF,

PMMCOREV = 3

(1) f_UCxCLK= 1/2t_LO/HIwith t_LO/HI≥ max(t_{VALID,MO(Master)}+ t_SU,SI(USCI), t_{SU,MI(Master)}+ t_{VALID,SO(USCI)}).

For the master's parameters t_{SU,MI(Master)}and t_{VALID,MO(Master)}, see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing

diagrams in Figure 13 and Figure 14.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in

Figure 13 and Figure 14.

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t_STE,LEAD

t_STE,LAG

STE

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_SU,SI

t_LO/HI

t_HD,SI

SIMO

t_HD,SO

t_VALID,SO

t_STE,ACC

t_STE,DIS

SOMI

Figure 13. SPI Slave Mode, CKPH = 0

t_STE,LEAD

t_STE,LAG

STE

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_LO/HI

t_HD,SI

t_SU,SI

SIMO

t_HD,MO

t_VALID,SO

t_STE,ACC

t_STE,DIS

SOMI

Figure 14. SPI Slave Mode, CKPH = 1

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USCI (I2C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 15)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK

External: UCLK

f_USCI

USCI input clock frequency

f_SYSTEMMHz

Duty cycle = 50% ± 10%

f_SCL

SCL clock frequency

2.2 V/3 V

0

4.0

0.6

4.7

0.6

0

400 kHz

f

_SCL≤ 100 kHz

_SCL> 100 kHz

_SCL≤ 100 kHz

_SCL> 100 kHz

t_HD,STA

Hold time (repeated) START

µs

t_SU,STA

Setup time for a repeated START

2.2 V/3 V

µs

t_HD,DAT

t_SU,DAT

Data hold time

Data setup time

2.2 V/3 V

ns

250

4.0

0.6

50

f_SCL≤ 100 kHz

_SCL> 100 kHz

t_SU,STO

Setup time for STOP

2.2 V/3 V

µs

f

2.2 V

3 V

600

ns

t_SP

Pulse width of spikes suppressed by input filter

50

600

t_HD,STA

t_SU,STA

t_HD,STA

t_BUF

SDA

SCL

t_LOW

t_HIGH

t_SP

t_SU,DAT

t_SU,STO

t_HD,DAT

Figure 15. I2C Mode Timing

12-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

2.2

0

TYP

MAX UNIT

AVCC and DVCC are connected together,

AVSS and DVSS are connected together,

V(AVSS) = V(DVSS) = 0 V

AV_CC

Analog supply voltage

3.6

V

V_(Ax)

Analog input voltage range⁽²⁾All ADC12 analog input pins Ax

AV_CC

200

V

2.2 V

3 V

150

Operating supply current into

f_ADC12CLK= 5.0 MHz⁽⁴⁾

AV_CCterminal⁽³⁾

I_{ADC12_A}

µA

250

Only one terminal Ax can be selected at one

time

C_I

R_I

Input capacitance

2.2 V

20

25

pF

Input MUX ON resistance

0 V ≤ VIN ≤ V(AVCC)

10

200

1900

Ω

(1) The leakage current is specified by the digital I/O input leakage.

(2) The analog input voltage range must be within the selected reference voltage range V_R+to V_R–for valid conversion results. If the

reference voltage is supplied by an external source or if the internal voltage is used and REFOUT = 1, then decoupling capacitors are

required. See REF, External Reference and REF, Built-In Reference.

(3) The internal reference supply current is not included in current consumption parameter I_ADC12

(4) ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0

.

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12-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

For specified performance of ADC12 linearity

parameters using an external reference voltage or

AVCC as reference⁽¹⁾

0.45

4.8

5.0

f_ADC12CLK

ADC conversion clock

For specified performance of ADC12 linearity

parameters using the internal reference⁽²⁾

2.2 V/3 V

MHz

4.0

0.45

4.2

2.4

4.8

For specified performance of ADC12 linearity

parameters using the internal reference⁽³⁾

2.7

Internal ADC12

oscillator⁽⁴⁾

f_ADC12OSC

t_CONVERT

t_Sample

ADC12DIV = 0, f_ADC12CLK= f_ADC12OSC

2.2 V/3 V

5.4 MHz

REFON = 0, Internal oscillator,

ADC12OSC used for ADC conversion clock

2.4

3.1

Conversion time

µs

External f_ADC12CLKfrom ACLK, MCLK or SMCLK,

ADC12SSEL ≠ 0

(5)

R_S= 400 Ω, R_I= 200 Ω, C_I= 20 pF,

Sampling time

2.2 V/3 V

1000

ns

(6)

τ = [R_S+ R_I] × C_I

(1) REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0,

SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the

specified performance of the ADC12 linearity is ensured with f_ADC12CLKmaximum of 5.0 MHz.

(2) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1

(3) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when

using the ADC12OSC divided by 2.

(4) The ADC12OSC is sourced directly from MODOSC inside the UCS.

(5) 13 × ADC12DIV × 1/f_ADC12CLK

(6) Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:

t_Sample= ln(2ⁿ⁺¹) x (R_S+ R_I) × C_I+ 800 ns, where n = ADC resolution = 12, R_S= external source resistance

12-Bit ADC, Linearity Parameters Using an External Reference Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

1.4 V ≤ dVREF ≤ 1.6 V⁽²⁾

V_CC

MIN

TYP

MAX UNIT

±2

LSB

±1.7

Integral

E_I

2.2 V/3 V

linearity error⁽¹⁾

(2)

1.6 V < dVREF

Differential

(2)

E_D

2.2 V/3 V

±1 LSB

linearity error⁽¹⁾

dVREF ≤ 2.2 V⁽²⁾

dVREF > 2.2 V⁽²⁾

2.2 V/3 V

±3

±1.5

±1

±5.6

LSB

±3.5

E_O

E_G

E_T

Offset error⁽³⁾

Gain error⁽³⁾

(2)

±2.5 LSB

dVREF ≤ 2.2 V⁽²⁾

dVREF > 2.2 V⁽²⁾

±3.5

±2

±7.1

LSB

±5

Total unadjusted

error

(1) Parameters are derived using the histogram method.

(2) The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = V_R+- V_R-. V_R+< AVCC. V_R-> AVSS.

Unless otherwise mentioned dVREF > 1.5V. Impedance of the external reference voltage R < 100 Ohm and two decoupling capacitors,

10µF and 100nF, should be connected to VREF to decouple the dynamic current. See also the MSP430F5xx/MSP430F6xx Family

User's Guide (SLAU208).

(3) Parameters are derived using a best fit curve.

12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Integral linearity error⁽¹⁾

Differential linearity error⁽¹⁾

Offset error⁽³⁾

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

±1.7 LSB

±1 LSB

(2)

E_I

See

2.2 V/3 V

E_D

E_O

±1

±2 LSB

(1) Parameters are derived using the histogram method.

(2) AVCC as reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 0.

(3) Parameters are derived using a best fit curve.

63

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12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Gain error⁽³⁾

Total unadjusted error

TEST CONDITIONS

V_CC

MIN

TYP

±2

MAX UNIT

±4 LSB

(2)

E_G

E_T

See

2.2 V/3 V

±2

±5 LSB

12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS⁽¹⁾

V_CC

MIN

TYP

MAX UNIT

ADC12SR = 0, REFOUT = 1

f

_ADC12CLK≤ 4.0 MHz

±1.7

LSB

±2.5

Integral

E_I

2.2 V/3 V

linearity error⁽²⁾

ADC12SR = 0, REFOUT = 0

ADC12SR = 0, REFOUT = 1

ADC12SR = 0, REFOUT = 0

ADC12SR = 0, REFOUT = 1

ADC12SR = 0, REFOUT = 0

ADC12SR = 0, REFOUT = 1

ADC12SR = 0, REFOUT = 0

ADC12SR = 0, REFOUT = 1

ADC12SR = 0, REFOUT = 0

_ADC12CLK≤ 2.7 MHz

_ADC12CLK≤ 4.0 MHz

_ADC12CLK≤ 2.7 MHz

_ADC12CLK≤ 4.0 MHz

_ADC12CLK≤ 2.7 MHz

_ADC12CLK≤ 4.0 MHz

_ADC12CLK≤ 2.7 MHz

_ADC12CLK≤ 4.0 MHz

_ADC12CLK≤ 2.7 MHz

-1

+1.5

Differential

E_D

2.2 V/3 V

±1 LSB

+2.5

linearity error⁽²⁾

±2

±1

±4

E_O

E_G

E_T

Offset error⁽³⁾

Gain error⁽³⁾

2.2 V/3 V

LSB

±4

±2.5 LSB

±1%⁽⁴⁾VREF

±5 LSB

±2

Total unadjusted

error

±1%⁽⁴⁾VREF

(1) The external reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 1. dVREF = V_R+- V_R-

.

(2) Parameters are derived using the histogram method.

(3) Parameters are derived using a best fit curve.

(4) The gain error and the total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In

this mode the reference voltage used by the ADC12_A is not available on a pin.

(1)

12-Bit ADC, Temperature Sensor and Built-In V_MID

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

2.2 V

3 V

MIN

TYP

680

2.25

MAX UNIT

ADC12ON = 1, INCH = 0Ah,

(2)

V_SENSOR

See

mV

T_A= 0°C

2.2 V

3 V

TC_SENSOR

ADC12ON = 1, INCH = 0Ah

mV/°C

µs

2.2 V

3 V

30

Sample time required if

channel 10 is selected⁽³⁾

ADC12ON = 1, INCH = 0Ah,

Error of conversion result ≤ 1 LSB

t_{SENSOR(sample)}

2.2 V

3 V

1.06

1.46

1.1

1.5

1.14

V

ADC12ON = 1, INCH = 0Bh,

V_MIDis ~0.5 × V_AVCC

V_MID

AV_CCdivider at channel 11

1.54

Sample time required if

channel 11 is selected⁽⁴⁾

ADC12ON = 1, INCH = 0Bh,

Error of conversion result ≤ 1 LSB

t_VMID(sample)

2.2 V/3 V

1000

ns

(1) The temperature sensor is provided by the REF module. Please refer to the REF module parametric, I_REF+, regarding the current

consumption of the temperature sensor.

(2) The temperature sensor offset can be as much as ±20°C. A single-point calibration is recommended in order to minimize the offset error

of the built-in temperature sensor. The TLV structure contains calibration values for 30°C ± 3°C and 85°C ± 3°C for each of the available

reference voltage levels. The sensor voltage can be computed as V_SENSE= TC_SENSOR* (Temperature,°C) + V_SENSOR, where TC_SENSOR

and V_SENSORcan be computed from the calibration values for higher accuracy. See also the MSP430F5xx/MSP430F6xx Family User's

Guide (SLAU208).

(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t_SENSOR(on)

.

(4) The on-time t_VMID(on)is included in the sampling time t_VMID(sample); no additional on time is needed.

64

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SLAS650B –JUNE 2010–REVISED AUGUST 2011

1000

950

900

850

800

750

700

650

600

550

500

-40 -30 -20 -10

0 10 20 30 40 50 60 70 80

Ambient Temperature - ˚C

Figure 16. Typical Temperature Sensor Voltage

REF, External Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Positive external

reference voltage input

(2)

V_eREF+

V

_eREF+> V_REF–/V_eREF–

1.4

AV_CC

1.2

V

Negative external

reference voltage input

(3)

(4)

V_REF–/V_eREF–

_eREF+> V_REF–/V_eREF–

0

V_eREF+

V_REF–/V_eREF–

–

Differential external

reference voltage input

1.4

AV_CC

1.4 V ≤ V_eREF+≤ V_AVCC, V_eREF–= 0 V,

f_ADC12CLK= 5 MHz, ADC12SHTx = 1h,

Conversion rate 200 ksps

2.2 V/3 V

-26

26

µA

I_VeREF+

I_{VREF–/VeREF–}

,

Static input current

1.4 V ≤ V_eREF+≤ V_AVCC, V_eREF–= 0 V,

f_ADC12CLK= 5 MHZ, ADC12SHTx = 8h,

Conversion rate 20 ksps

-1.2

10

+1.2

µA

µF

Capacitance at V_REF+/-

terminal⁽⁵⁾

C_VREF+/-

(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, C_i, is also

the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the

recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.

(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced

accuracy requirements.

(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced

accuracy requirements.

(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with

reduced accuracy requirements.

(5) Two decoupling capacitors, 10µF and 100nF, should be connected to VREF to decouple the dynamic current required for an external

reference source if it is used for the ADC12_A. See also the MSP430F5xx/MSP430F6xx Family User's Guide (SLAU208).

65

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REF, Built-In Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

REFVSEL = {2} for 2.5 V

REFON = REFOUT = 1

I_VREF+= 0 A

3 V

2.5

±1%

REFVSEL = {1} for 2 V

REFON = REFOUT = 1

I_VREF+= 0 A

Positive built-in reference

voltage output

V_REF+

3 V

2.0

1.5

±1%

V

REFVSEL = {0} for 1.5 V

REFON = REFOUT = 1

I_VREF+= 0 A

2.2 V / 3 V

REFVSEL = {0} for 1.5 V

2.2

2.3

2.8

AV_CCminimum voltage,

AV_CC(min)

Positive built-in reference REFVSEL = {1} for 2 V

V

active

REFVSEL = {2} for 2.5 V

ADC12SR = 1⁽⁴⁾, REFON = 1, REFOUT = 0,

REFBURST = 0

ADC12SR = 1⁽⁴⁾, REFON = 1, REFOUT = 1,

REFBURST = 0

ADC12SR = 0⁽⁴⁾, REFON = 1, REFOUT = 0,

REFBURST = 0

3V

70

0.45

210

100

0.75

310

1.7

µA

mA

µA

Operating supply current

into AV_CCterminal

I_REF+

(2) (3)

ADC12SR = 0⁽⁴⁾, REFON = 1, REFOUT = 1,

REFBURST = 0

0.95

mA

REFVSEL = {0, 1, 2}

Load-current regulation, I_VREF+= +10 µA / -1000 µA

I_L(VREF+)

1500

2500 µV/mA

V_REF+terminal⁽⁵⁾

AV_CC= AV_CC(min)for each reference level,

REFVSEL = {0, 1, 2}, REFON = REFOUT = 1

(6)

Capacitance at V_REF+

terminal

REFON = REFOUT = 1,

C_VREF+

TC_REF+

2.2 V/3 V

20

100

50

pF

0 mA ≤ I_VREF+≤ I_VREF+(max)

Temperature coefficient

of built-in reference⁽⁷⁾

I_VREF+is a constant in the range

REFOUT = 0

ppm/

°C

20

of 0 mA ≤ I_VREF+≤ –1 mA

Temperature coefficient

of built-in reference⁽⁷⁾

I_VREF+is a constant in the range

REFOUT = 1

ppm/

°C

of 0 mA ≤ I_VREF+≤ –1 mA

AV_CC= AV_CC(min)- AV_CC(max)

,

Power supply rejection

ratio (dc)

T_A= 25°C,

REFVSEL = {0, 1, 2}, REFON = 1,

REFOUT = 0 or 1

PSRR_DC

PSRR_AC

120

1

300 µV/V

AV_CC= AV_CC(min)- AV_CC(max)

T_A= 25°C,

REFVSEL = {0, 1, 2}, REFON = 1,

REFOUT = 0 or 1

,

Power supply rejection

ratio (ac)

mV/V

(1) The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers, one

smaller and one larger for driving the V_REF+terminal. When REFOUT = 1, the reference is available at the V_REF+terminal, as well as,

used as the reference for the conversion and utilizes the larger buffer. When REFOUT = 0, the reference is only used as the reference

for the conversion and utilizes the smaller buffer.

(2) The internal reference current is supplied via terminal AV_CC. Consumption is independent of the ADC12ON control bit, unless a

conversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current

contribution of the larger buffer without external load.

(3) The temperature sensor is provided by the REF module. Its current is supplied via terminal AV_CCand is equivalent to I_REF+with REFON

= 1 and REFOUT = 0.

(4) For devices without the ADC12, the parametric with ADC12SR = 0 are applicable.

(5) Contribution only due to the reference and buffer including package. This does not include resistance due to PCB trace, etc.

(6) Two decoupling capacitors, 10µF and 100nF, should be connected to VREF to decouple the dynamic current required for an external

reference source if it is used for the ADC12_A. See also the MSP430F5xx/MSP430F6xx Family User's Guide (SLAU208).

(7) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C)/(85°C – (–40°C)).

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REF, Built-In Reference (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

AV_CC= AV_CC(min)- AV_CC(max)

,

REFVSEL = {0, 1, 2}, REFOUT = 0,

REFON = 0 → 1

75

Settling time of reference

voltage⁽⁸⁾

t_SETTLE

µs

AV_CC= AV_CC(min)- AV_CC(max)

,

C_VREF= C_VREF(max),

REFVSEL = {0, 1, 2}, REFOUT = 1,

75

REFON = 0 → 1

(8) The condition is that the error in a conversion started after t_REFONis less than ±0.5 LSB. The settling time depends on the external

capacitive load when REFOUT = 1.

12-Bit DAC, Supply Specifications

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

AV_CCAnalog supply voltage

AV_CC= DV_CC, AV_SS= DV_SS= 0 V

2.20

3.60

V

DAC12AMPx = 2, DAC12IR = 0,

DAC12IOG = 1

DAC12_xDAT = 0800h

VeREF+ = VREF+ = 1.5 V

3 V

65

110

DAC12AMPx = 2, DAC12IR = 1,

DAC12_xDAT = 0800h,

VeREF+ = VREF+ = AV_CC

125

250

165

350

I_DD

Supply current, single DAC channel^{(1) (2)}

µA

DAC12AMPx = 5, DAC12IR = 1,

DAC12_xDAT = 0800h,

2.2 V/3 V

VeREF+ = VREF+ = AV_CC

DAC12AMPx = 7, DAC12IR = 1,

DAC12_xDAT = 0800h,

VeREF+ = VREF+ = AV_CC

750

70

1100

DAC12_xDAT = 800h,

VeREF+ = 1.5 V, ΔAV_CC= 100 mV

2.2 V

3 V

PSRR Power supply rejection ratio^{(3) (4)}

dB

DAC12_xDAT = 800h,

VeREF+ = 1.5 V or 2.5 V,

ΔAV_CC= 100 mV

70

(1) No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.

(2) Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input specifications.

(3) PSRR = 20 log (ΔAV_CC/ ΔV_{DAC12_xOUT}

)

(4) The internal reference is not used.

12-Bit DAC, Linearity Specifications

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 17)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Resolution

12-bit monotonic

12

bits

Ve_REF+= 1.5 V, DAC12AMPx = 7, DAC12IR = 1

Ve_REF+= 2.5 V, DAC12AMPx = 7, DAC12IR = 1

Ve_REF+= 1.5 V, DAC12AMPx = 7, DAC12IR = 1

Ve_REF+= 2.5 V, DAC12AMPx = 7, DAC12IR = 1

2.2 V

3 V

±2

±4⁽²⁾

LSB

±4

±1⁽²⁾

LSB

±1

Integral

INL

nonlinearity⁽¹⁾

2.2 V

3 V

±0.4

Differential

DNL

nonlinearity⁽¹⁾

(1) Parameters calculated from the best-fit curve from 0x0F to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and “b” of

the first-order equation: y = a + bx. V_{DAC12_xOUT}= E_O+ (1 + E_G) × (Ve_REF+/4095) × DAC12_xDAT, DAC12IR = 1.

(2) This parameter is not production tested.

67

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12-Bit DAC, Linearity Specifications (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 17)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Ve_REF+= 1.5 V,

DAC12AMPx = 7,

DAC12IR = 1

2.2 V

±21⁽²⁾

Without calibration^{(1) (3)}

Ve_REF+= 2.5 V,

DAC12AMPx = 7,

DAC12IR = 1

3 V

2.2 V

±21

mV

E_O

Offset voltage

Ve_REF+= 1.5 V,

DAC12AMPx = 7,

DAC12IR = 1

±1.5⁽²⁾

With calibration^{(1) (3)}

With calibration

Ve_REF+= 2.5 V,

DAC12AMPx = 7,

DAC12IR = 1

3 V

±1.5

Offset error

temperature

coefficient⁽¹⁾

d_E(O)/d_T

2.2 V/3 V

±10

µV/°C

Ve_REF+= 1.5 V

Ve_REF+= 2.5 V

2.2 V

3 V

±2.5

E_G

Gain error

%FSR

±2.5

ppm

of

FSR/ °

C

Gain temperature

coefficient⁽¹⁾

d_E(G)/d_T

2.2 V/3 V

10

DAC12AMPx = 2

165

Time for offset

calibration⁽⁴⁾

t_{Offset_Cal}

DAC12AMPx = 3, 5

DAC12AMPx = 4, 6, 7

66

ms

16.5

(3) The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON

(4) The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx =

{0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may effect

accuracy and is not recommended.

DAC V_OUT

DAC Output

V_R+

R_Load= ¥

Ideal transfer

function

AV_CC

2

Offset Error

Positive

Gain Error

C_Load= 100 pF

Negative

DAC Code

Figure 17. Linearity Test Load Conditions and Gain/Offset Definition

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12-Bit DAC, Output Specifications

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

No load, Ve_REF+= AV_CC

,

DAC12_xDAT = 0h, DAC12IR = 1,

DAC12AMPx = 7

0

0.005

No load, Ve_REF+= AV_CC

DAC12_xDAT = 0FFFh, DAC12IR = 1,

DAC12AMPx = 7

,

AV_CC

–

AV_CC

0.05

Output voltage

V_O

range⁽¹⁾(see

Figure 18)

2.2 V/3 V

V

R_Load= 3 kΩ, Ve_REF+= AV_CC

,

DAC12_xDAT = 0h, DAC12IR = 1,

DAC12AMPx = 7

0

0.1

R_Load= 3 kΩ, Ve_REF+= AV_CC

DAC12_xDAT = 0FFFh, DAC12IR = 1,

DAC12AMPx = 7

,

AV_CC

–

AV_CC

0.13

Maximum DAC12

load capacitance

C_L(DAC12)

2.2 V/3 V

100

pF

DAC12AMPx = 2, DAC12xDAT = 0FFFh,

–1

V

_O/P(DAC12)> AV_CC– 0.3

DAC12AMPx = 2, DAC12xDAT = 0h,

_O/P(DAC12)< 0.3 V

Maximum DAC12

load current

I_L(DAC12)

mA

1

250

6

V

R_Load= 3 kΩ, VO/P(DAC12) < 0.3 V,

DAC12AMPx = 2, DAC12_xDAT = 0h

150

Output resistance R_Load= 3 kΩ, V_O/P(DAC12)> AV_CC– 0.3 V,

(see Figure 18)

R_O/P(DAC12)

2.2 V/3 V

Ω

DAC12_xDAT = 0FFFh

R_Load= 3 kΩ,

0.3 V ≤ V_O/P(DAC12)≤ AV_CC– 0.3 V

(1) Data is valid after the offset calibration of the output amplifier.

R_{O/P(DAC12_x)}

Max

R_Load

I_Load

AV_CC

DAC12

2

C_Load= 100 pF

O/P(DAC12_x)

Min

0.3

AV_CC– 0.3 V

V_OUT

AV_CC

Figure 18. DAC12_x Output Resistance Tests

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12-Bit DAC, Reference Input Specifications

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

DAC12IR = 0^{(1) (2)}

V_CC

MIN

TYP

MAX UNIT

AV_CC

/

AV_CC

3

+ 0.2

Reference input voltage

range

Ve_REF+

2.2 V/3 V

V

AV_CC

DAC12IR = 1^{(3) (4)}

AV_CC

+ 0.2

DAC12_0 IR = DAC12_1 IR = 0

DAC12_0 IR = 1, DAC12_1 IR = 0

DAC12_0 IR = 0, DAC12_1 IR = 1

20

MΩ

48

Ri_(VREF+)

Ri_(VeREF+)

,

Reference input resistance⁽⁵⁾

2.2 V/3 V

kΩ

DAC12_0 IR = DAC12_1 IR = 1,

24

DAC12_0 SREFx = DAC12_1 SREFx⁽⁶⁾

(1) For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).

(2) The maximum voltage applied at reference input voltage terminal Ve_REF+= [AV_CC– V_E(O)] / [3 × (1 + E_G)].

(3) For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).

(4) The maximum voltage applied at reference input voltage terminal Ve_REF+= [AV_CC– V_E(O)] / (1 + E_G).

(5) This impedance depends on tradeoff in power savings. Current devices have 48 kΩ for each channel when divide is enabled. Can be

increased if performance can be maintained.

(6) When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel

reducing the reference input resistance.

12-Bit DAC, Dynamic Specifications

V_REF= V_CC, DAC12IR = 1 (see Figure 19 and Figure 20), over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

DAC12AMPx = 0 → {2, 3, 4}

V_CC

MIN

TYP

60

MAX UNIT

120

DAC12_xDAT = 800h,

Error_V(O)< ±0.5 LSB⁽¹⁾

(see Figure 19)

t_ON

DAC12 on time

DAC12AMPx = 0 → {5, 6}

DAC12AMPx = 0 → 7

DAC12AMPx = 2

2.2 V/3 V

15

30

12

µs

6

100

40

200

80

DAC12_xDAT =

t_S(FS)

t_S(C-C)

SR

Settling time, full scale

DAC12AMPx = 3, 5

DAC12AMPx = 4, 6, 7

DAC12AMPx = 2

2.2 V/3 V

80h → F7Fh → 80h

15

30

5

DAC12_xDAT =

Settling time, code to

code

3F8h → 408h → 3F8h,

BF8h → C08h → BF8h

DAC12AMPx = 3, 5

DAC12AMPx = 4, 6, 7

DAC12AMPx = 2

2

1

0.05

0.35

1.50

0.35

1.10

5.20

DAC12_xDAT =

Slew rate

DAC12AMPx = 3, 5

DAC12AMPx = 4, 6, 7

2.2 V/3 V

V/µs

80h → F7Fh → 80h⁽²⁾

DAC12_xDAT =

Glitch energy

DAC12AMPx = 7

35

nV-s

800h → 7FFh → 800h

(1) R_Loadand C_Loadconnected to AV_SS(not AV_CC/2) in Figure 19.

(2) Slew rate applies to output voltage steps ≥ 200 mV.

Conversion 1

Conversion 2

1/2 LꢀS

Conversion 3

V_OUT

DAC Output

R_Load= 3 kW

I_Load

Glitch

Energy

AV_CC

2

1/2 LꢀS

C_Load= 100 pF

R_O/P(DAC12.x)

t_settleLH

t_settleHL

Figure 19. Settling Time and Glitch Energy Testing

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Conversion 1

Conversion 2

Conversion 3

V_OUT

90%

10%

t_SRLH

t_SRHL

Figure 20. Slew Rate Testing

12-Bit DAC, Dynamic Specifications (Continued)

over recommended ranges of supply voltage and T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,

DAC12IR = 1, DAC12_xDAT = 800h

40

3-dB bandwidth,

V_DC= 1.5 V,

V_AC= 0.1 V_PP

(see Figure 21)

DAC12AMPx = {5, 6}, DAC12SREFx = 2,

DAC12IR = 1, DAC12_xDAT = 800h

BW_–3dB

2.2 V/3 V

180

550

kHz

DAC12AMPx = 7, DAC12SREFx = 2,

DAC12IR = 1, DAC12_xDAT = 800h

DAC12_0DAT = 800h, No load,

DAC12_1DAT = 80h ↔ F7Fh, R_Load= 3 kΩ,

f_{DAC12_0OUT}= 10 kHz at 50/50 duty cycle

–80

Channel-to-channel

crosstalk⁽¹⁾(see

Figure 22)

2.2 V/3 V

dB

DAC12_0DAT = 80h ↔ F7Fh, R_Load= 3 kΩ,

DAC12_1DAT = 800h, No load,

f_{DAC12_0OUT}= 10 kHz at 50/50 duty cycle

(1) R_Load= 3 kΩ, C_Load= 100 pF

R_Load= 3 kW

I_Load

Ve_REF+

AV_CC

2

DAC12_x

DACx

AC

DC

C_Load= 100 pF

Figure 21. Test Conditions for 3-dB Bandwidth Specification

R_Load

I_Load

AV_CC

DAC12_xDAT

V_OUT

080h

7F7h

080h

7F7h

080h

DAC12_0

DAC12_1

2

DAC0

C_Load= 100 pF

R_Load

V_REF+

V_{DAC12_yOUT}

I_Load

V_{DAC12_xOUT}

AV_CC

2

f_Toggle

DAC1

C_Load= 100 pF

Figure 22. Crosstalk Test Conditions

71

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

MAX UNIT

Comparator_B

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

V_CC

Supply voltage

1.8

3.6

40

50

65

30

0.5

V

1.8 V

2.2 V

Comparator operating supply

current into AV_CCterminal,

Excludes reference resistor

ladder

CBPWRMD = 00

30

40

I_{AVCC_COMP}

3 V

µA

CBPWRMD = 01

CBPWRMD = 10

2.2 V / 3 V

10

0.1

Quiescent current of local

reference voltage amplifier

into AV_CCterminal

I_{AVCC_REF}

CBREFACC = 1, CBREFLx = 01

22

µA

V_IC

Common mode input range

0

V_CC- 1

±20

V

CBPWRMD = 00

V_OFFSET

C_IN

Input offset voltage

mV

CBPWRMD = 01, 10

±10

Input capacitance

5

3

pF

kΩ

MΩ

ns

ON - switch closed

4

R_SIN

Series input resistance

OFF - switch opened

50

CBPWRMD = 00, CBF = 0

CBPWRMD = 01, CBF = 0

CBPWRMD = 10, CBF = 0

450

600

50

Propagation delay, response

time

t_PD

ns

µs

CBPWRMD = 00, CBON = 1, CBF = 1,

CBFDLY = 00

0.35

0.6

1.0

1.8

0.6

1.0

1.8

3.4

1

1.0

1.8

3.4

6.5

2

µs

CBPWRMD = 00, CBON = 1, CBF = 1,

CBFDLY = 01

Propagation delay with filter

active

t_PD,filter

CBPWRMD = 00, CBON = 1, CBF = 1,

CBFDLY = 10

CBPWRMD = 00, CBON = 1, CBF = 1,

CBFDLY = 11

Comparator enable time,

settling time

CBON = 0 to CBON = 1

CBPWRMD = 00, 01, 10

t_{EN_CMP}

t_{EN_REF}

Resistor reference enable

time

CBON = 0 to CBON = 1

0.3

1.5

VIN × VIN ×

(n+0.5) (n+1)

VIN ×

(n+1.5)

/ 32

Reference voltage for a given VIN = reference into resistor ladder,

tap n = 0 to 31

V_{CB_REF}

V

/ 32

72

MSP430F563x

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SLAS650B –JUNE 2010–REVISED AUGUST 2011

Ports PU.0 and PU.1

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_USB= 3.3 V ± 10%, I_OH= -25 mA

V_USB= 3.3 V ± 10%, I_OL= 25 mA

V_USB= 3.3 V ± 10%

V_CC

MIN

TYP

MAX UNIT

V_OH

V_OL

V_IH

V_IL

High-level output voltage

Low-level output voltage

High-level input voltage

Low-level input voltage

2.4

V

0.4

0.8

V

2.0

V_USB= 3.3 V ± 10%

USB Output Ports DP and DM

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

D+, D- single ended

D+, D- impedance

Rise time

TEST CONDITIONS

USB 2.0 load conditions

MIN

2.8

0

TYP

MAX UNIT

V_OH

3.6

0.3

44

20

V

V_OL

USB 2.0 load conditions

Z_(DRV)

t_RISE

t_FALL

Including external series resistor of 27 Ω

28

4

Ω

Full speed, differential, C_L= 50 pF, 10%/90%, Rpu on D+

ns

Fall time

4

USB Input Ports DP and DM

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Differential input common mode range

Input impedance

TEST CONDITIONS

MIN

0.8

TYP

MAX UNIT

V_(CM)

Z_(IN)

V_CRS

V_IL

2.5

V

kΩ

V

300

1.3

Crossover voltage

2.0

Static SE input logic low level

Static SE input logic high level

Differential input voltage

0.8

V

V_IH

2.0

0.2

V

VDI

V

USB-PWR (USB Power System)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

V_BUSdetection threshold

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_LAUNCH

V_BUS

3.75

5.5

V

USB bus voltage

Normal operation

3.76

V_USB

USB LDO output voltage

Internal USB voltage⁽¹⁾

3.3

1.8

±9%

V

V₁₈

V

I_{USB_EXT}

I_DET

Maximum external current from VUSB terminal⁽²⁾

USB LDO current overload detection⁽³⁾

USB LDO is on

12

mA

60

100

USB LDO is on,

USB PLL disabled

I_SUSPEND

Operating supply current into VBUS terminal.⁽⁴⁾

250

µA

C_BUS

C_USB

C₁₈

VBUS terminal recommended capacitance

VUSB terminal recommended capacitance

V18 terminal recommended capacitance

4.7

220

µF

nF

Within 2%,

recommended capacitances

t_ENABLE

RPUR

Settling time V_USBand V₁₈

2

ms

Pullup resistance of PUR terminal

70

110

150

Ω

(1) This voltage is for internal use only. No external dc loading should be applied.

(2) This represents additional current that can be supplied to the application from the VUSB terminal beyond the needs of the USB

operation.

(3) A current overload is detected when the total current supplied from the USB LDO, including I_{USB_EXT}, exceeds this value.

(4) Does not include current contribution of Rpu and Rpd as outlined in the USB specification.

73

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SLAS650B –JUNE 2010–REVISED AUGUST 2011

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MAX UNIT

USB-PLL (USB Phase-Locked Loop)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

I_PLL

Operating supply current

PLL frequency

7

mA

MHz

ms

f_PLL

48

f_UPD

t_LOCK

t_Jitter

PLL reference frequency

PLL lock time

1.5

3

2

PLL jitter

1000

ps

Flash Memory

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEST

CONDITIONS

PARAMETER

MIN

TYP

MAX UNIT

DV_{CC(PGM/ERASE)}Program and erase supply voltage

1.8

3.6

5

V

mA

I_PGM

Average supply current from DV_CCduring program

3

I_ERASE

Average supply current from DV_CCduring erase

Average supply current from DV_CCduring mass erase or bank erase

Cumulative program time

2.5

2

mA

I_MERASE, I_BANK

t_CPT

mA

(1)

See

16

ms

Program/erase endurance

10⁴

100

64

10⁵

cycles

years

µs

t_Retention

t_Word

Data retention duration

T_J= 25°C

(2)

Word or byte program time

See

85

65

(2)

t_{Block, 0}

Block program time for first byte or word

See

49

µs

Block program time for each additional byte or word, except for last

byte or word

(2)

t_{Block, 1–(N–1)}

t_{Block, N}

See

37

55

23

49

73

32

µs

(2)

Block program time for last byte or word

See

Erase time for segment, mass erase, and bank erase when

available

(2)

t_{Seg Erase}

See

ms

MCLK frequency in marginal read mode

(FCTL4.MGR0 = 1 or FCTL4.MGR1 = 1)

f_MCLK,MGR

0

1

MHz

(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming

methods: individual word/byte write and block write modes.

(2) These values are hardwired into the flash controller's state machine.

JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEST

CONDITIONS

PARAMETER

MIN

TYP

MAX UNIT

f_SBW

Spy-Bi-Wire input frequency

2.2 V/3 V

0

20 MHz

t_SBW,Low

Spy-Bi-Wire low clock pulse length

2.2 V/3 V

0.025

15

µs

Spy-Bi-Wire enable time (TEST high to acceptance of first clock

edge)⁽¹⁾

t_{SBW, En}

t_SBW,Rst

2.2 V/3 V

1

µs

Spy-Bi-Wire return to normal operation time

TCK input frequency - 4-wire JTAG⁽²⁾

Internal pull-down resistance on TEST

15

0

100

5

µs

2.2 V

3 V

MHz

f_TCK

0

10 MHz

80 kΩ

R_internal

2.2 V/3 V

45

60

(1) Tools accessing the Spy-Bi-Wire interface need to wait for the t_SBW,Entime after pulling the TEST/SBWTCK pin high before applying the

first SBWTCK clock edge.

(2) f_TCKmay be restricted to meet the timing requirements of the module selected.

74

MSP430F563x

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INPUT/OUTPUT SCHEMATICS

Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger

Pad Logic

P1REN.x

DV_SS

DV_CC

0

1

Direction

P1DIR.x

0: Input

1: Output

P1OUT.x

0

1

Module X OUT

P1.0/TA0CLK/ACLK

P1.1/TA0.0

P1.2/TA0.1

P1.3/TA0.2

P1.4/TA0.3

P1DS.x

0: Low drive

1: High drive

P1SEL.x

P1IN.x

P1.5/TA0.4

P1.6/TA0.1

P1.7/TA0.2

EN

D

Module X IN

P1IRQ.x

P1IE.x

EN

Q

P1IFG.x

Set

P1SEL.x

P1IES.x

Interrupt

Edge

Select

75

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

Table 54. Port P1 (P1.0 to P1.7) Pin Functions

CONTROL BITS/SIGNALS

PIN NAME (P1.x)

x

FUNCTION

P1DIR.x

P1SEL.x

P1.0/TA0CLK/ACLK

0

P1.0 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Timer TA0.TA0CLK

ACLK

0

1

P1.1/TA0.0

P1.2/TA0.1

P1.3/TA0.2

P1.4/TA0.3

P1.5/TA0.4

P1.6/TA0.1

P1.7/TA0.2

1

2

3

4

5

6

7

P1.1 (I/O)

I: 0; O: 1

Timer TA0.CCI0A capture input

Timer TA0.0 output

P1.2 (I/O)

0

1

I: 0; O: 1

Timer TA0.CCI1A capture input

Timer TA0.1 output

P1.3 (I/O)

0

1

I: 0; O: 1

Timer TA0.CCI2A capture input

Timer TA0.2 output

P1.4 (I/O)

0

1

I: 0; O: 1

Timer TA0.CCI3A capture input

Timer TA0.3 output

P1.5 (I/O)

0

1

I: 0; O: 1

Timer TA0.CCI4A capture input

Timer TA0.4 output

P1.6 (I/O)

0

1

I: 0; O: 1

Timer TA0.CCI1B capture input

Timer TA0.1 output

P1.7 (I/O)

0

1

I: 0; O: 1

Timer TA0.CCI2B capture input

Timer TA0.2 output

0

1

76

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SLAS650B –JUNE 2010–REVISED AUGUST 2011

Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger

Pad Logic

P2REN.x

DV_SS

DV_CC

0

1

P2DIR.x

0

1

Direction

0: Input

1: Output

From Port Mapping

P2OUT.x

0

1

From Port Mapping

P2.0/P2MAP0

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

P2.6/P2MAP6

P2.7/P2MAP7

P2DS.x

0: Low drive

1: High drive

P2SEL.x

P2IN.x

EN

D

To Port Mapping

P2IE.x

EN

P2IRQ.x

Q

P2IFG.x

Set

P2SEL.x

P2IES.x

Interrupt

Edge

Select

77

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SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

Table 55. Port P2 (P2.0 to P2.7) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P2.x)

x

FUNCTION

P2DIR.x

P2SEL.x

P2MAPx

P2.0/P2MAP0

0

P2.0 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Mapped secondary digital function

P2.1 (I/O)

X

≤ 19

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

P2.6/P2MAP6

P2.7/P2MAP7

1

2

3

4

5

6

7

I: 0; O: 1

Mapped secondary digital function

P2.2 (I/O)

X

≤ 19

I: 0; O: 1

Mapped secondary digital function

P2.3 (I/O)

X

≤ 19

I: 0; O: 1

Mapped secondary digital function

P2.4 (I/O)

X

≤ 19

I: 0; O: 1

Mapped secondary digital function

P2.5 (I/O

X

≤ 19

I: 0; O: 1

Mapped secondary digital function

P2.6 (I/O)

X

I: 0; O: 1

X

≤ 19

Mapped secondary digital function

P2.7 (I/O)

≤ 19

I: 0; O: 1

X

Mapped secondary digital function

≤ 19

(1) X = Don't care

78

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SLAS650B –JUNE 2010–REVISED AUGUST 2011

Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger

Pad Logic

P3REN.x

DV_SS

DV_CC

0

1

Direction

0: Input

1: Output

P3DIR.x

P3OUT.x

0

1

Module X OUT

P3.0/TA1CLK/CBOUT

P3.1/TA1.0

P3.2/TA1.1

P3DS.x

0: Low drive

1: High drive

P3SEL.x

P3IN.x

P3.3/TA1.2

P3.4/TA2CLK/SMCLK

P3.5/TA2.0

P3.6/TA2.1

EN

D

P3.7/TA2.2

Module X IN

P3IRQ.x

P3IE.x

EN

Q

P3IFG.x

Set

P3SEL.x

P3IES.x

Interrupt

Edge

Select

79

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

Table 56. Port P3 (P3.0 to P3.7) Pin Functions

CONTROL BITS/SIGNALS

PIN NAME (P3.x)

x

FUNCTION

P3DIR.x

P3SEL.x

P3.0/TA1CLK/CBOUT

0

P3.0 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Timer TA1.TA1CLK

CBOUT

0

1

P3.1/TA1.0

1

2

3

4

5

6

7

P3.1 (I/O)

I: 0; O: 1

Timer TA1.CCI0A capture input

Timer TA1.0 output

P3.2 (I/O)

0

1

P3.2/TA1.1

I: 0; O: 1

Timer TA1.CCI1A capture input

Timer TA1.1 output

P3.3 (I/O)

0

1

P3.3/TA1.2

I: 0; O: 1

Timer TA1.CCI2A capture input

Timer TA1.2 output

P3.4 (I/O)

0

1

P3.4/TA2CLK/SMCLK

P3.5/TA2.0

I: 0; O: 1

Timer TA2.TA2CLK

SMCLK

0

1

P3.5 (I/O)

I: 0; O: 1

Timer TA2.CCI0A capture input

Timer TA2.0 output

P3.6 (I/O)

0

1

P3.6/TA2.1

I: 0; O: 1

Timer TA2.CCI1A capture input

Timer TA2.1 output

P3.7 (I/O)

0

1

P3.7/TA2.2

I: 0; O: 1

Timer TA2.CCI2A capture input

Timer TA2.2 output

0

1

80

MSP430F563x

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SLAS650B –JUNE 2010–REVISED AUGUST 2011

Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger

Pad Logic

P4REN.x

DV_SS

DV_CC

0

1

Direction

P4DIR.x

0: Input

1: Output

P4OUT.x

0

1

Module X OUT

P4.0/TB0.0

P4.1/TB0.1

P4.2/TB0.2

P4.3/TB0.3

P4.4/TB0.4

P4DS.x

0: Low drive

1: High drive

P4SEL.x

P4IN.x

P4.5/TB0.5

P4.6/TB0.6

P4.7/TB0OUTH/SVMOUT

EN

D

Module X IN

P4IRQ.x

P4IE.x

EN

Q

P4IFG.x

Set

P4SEL.x

P4IES.x

Interrupt

Edge

Select

81

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

Table 57. Port P4 (P4.0 to P4.7) Pin Functions

CONTROL BITS/SIGNALS

PIN NAME (P4.x)

P4.0/TB0.0

x

FUNCTION

P4DIR.x

P4SEL.x

0

P4.0 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Timer TB0.CCI0A capture input

Timer TB0.0 output⁽¹⁾

P4.1 (I/O)

0

1

P4.1/TB0.1

P4.2/TB0.2

P4.3/TB0.3

P4.4/TB0.4

P4.5/TB0.5

P4.6/TB0.6

1

2

3

4

5

6

7

I: 0; O: 1

Timer TB0.CCI1A capture input

Timer TB0.1 output⁽¹⁾

P4.2 (I/O)

0

1

I: 0; O: 1

Timer TB0.CCI2A capture input

Timer TB0.2 output⁽¹⁾

P4.3 (I/O)

0

1

I: 0; O: 1

Timer TB0.CCI3A capture input

Timer TB0.3 output⁽¹⁾

P4.4 (I/O)

0

1

I: 0; O: 1

Timer TB0.CCI4A capture input

Timer TB0.4 output⁽¹⁾

P4.5 (I/O)

0

1

I: 0; O: 1

Timer TB0.CCI5A capture input

Timer TB0.5 output⁽¹⁾

P4.6 (I/O)

0

1

I: 0; O: 1

Timer TB0.CCI6A capture input

Timer TB0.6 output⁽¹⁾

P4.7 (I/O)

0

1

P4.7/TB0OUTH/

SVMOUT

I: 0; O: 1

Timer TB0.TB0OUTH

SVMOUT

0

1

(1) Setting TB0OUTH causes all Timer_B configured outputs to be set to high impedance.

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Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger

Pad Logic

To/From

Reference

P5REN.x

DV_SS

DV_CC

0

1

P5DIR.x

0

1

P5OUT.x

0

1

Module X OUT

P5.0/VREF+/VeREF+

P5.1/VREF–/VeREF–

P5DS.x

0: Low drive

1: High drive

P5SEL.x

P5IN.x

Bus

Keeper

EN

D

Module X IN

Table 58. Port P5 (P5.0 and P5.1) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P5.x)

x

FUNCTION

P5DIR.x

P5SEL.x

REFOUT

P5.0/VREF+/VeREF+

0

P5.0 (I/O)⁽²⁾

VeREF+⁽³⁾

VREF+⁽⁴⁾

P5.1 (I/O)⁽²⁾

VeREF–⁽⁵⁾

VREF–⁽⁶⁾

I: 0; O: 1

0

1

0

1

X

0

1

X

0

1

X

P5.1/VREF–/VeREF–

1

I: 0; O: 1

X

(1) X = Don't care

(2) Default condition

(3) Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A, Comparator_B, or

DAC12_A.

(4) Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. The ADC12_A, VREF+ reference is available at the pin.

(5) Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A, Comparator_B, or

DAC12_A.

(6) Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. The ADC12_A, VREF– reference is available at the pin.

83

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

Port P5, P5.2 to P5.7, Input/Output With Schmitt Trigger

Pad Logic

P5REN.x

DV_SS

DV_CC

0

1

Direction

0: Input

1: Output

P5DIR.x

P5OUT.x

0

1

Module X OUT

P5.2

P5.3

P5.4

P5.5

P5DS.x

0: Low drive

1: High drive

P5SEL.x

P5IN.x

P5.6/ADC12CLK/DMAE0

P5.7/RTCCLK

EN

D

Module X IN

Table 59. Port P5 (P5.2 to P5.7) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P5.x)

x

FUNCTION

P5DIR.x

I: 0; O: 1

1

P5SEL.x

P5.2

P5.3

P5.4

P5.5

2

3

4

5

6

P5.2 (I/O)

P5.3 (I/O)

P5.4 (I/O)

P5.5 (I/O)

P5.6 (I/O)

ADC12CLK

DMAE0

0

1

0

1

P5.6/ADC12CLK/DMAE0

0

P5.7/RTCCLK

7

P5.7 (I/O)

RTCCLK

I: 0; O: 1

1

(1) X = Don't care

84

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www.ti.com

SLAS650B –JUNE 2010–REVISED AUGUST 2011

Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger

Pad Logic

To ADC12

INCHx = y

0

Dvss

1

2

0 if DAC12AMPx=0

1 if DAC12AMPx=1

2 if DAC12AMPx>1

From DAC12_A

To Comparator_B

From Comparator_B

CBPD.x

DAC12AMPx>0

DAC12OPS

P6REN.x

DV_SS

DV_CC

0

1

P6DIR.x

P6OUT.x

P6.0/CB0/A0

P6.1/CB1/A1

P6.2/CB2/A2

P6.3/CB3/A3

P6.4/CB4/A4

P6.5/CB5/A5

P6DS.x

0: Low drive

1: High drive

P6SEL.x

P6IN.x

P6.6/CB6/A6/DAC0

P6.7/CB7/A7/DAC1

Bus

Keeper

85

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

Table 60. Port P6 (P6.0 to P6.7) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P6.x)

x

FUNCTION

P6DIR.x

P6SEL.x

CBPD.x

DAC12OPS

DAC12AMPx

P6.0/CB0/A0

0

P6.0 (I/O)

CB0

A0^{(2) (3)}

P6.1 (I/O)

CB1

A1^{(2) (3)}

P6.2 (I/O)

CB2

A2^{(2) (3)}

P6.3 (I/O)

CB3

A3^{(2) (3)}

P6.4 (I/O)

CB4

A4^{(2) (3)}

P6.5 (I/O)

CB5

A5^{(1) (2) (3)}

P6.6 (I/O)

CB6

I: 0; O: 1

0

X

1

0

X

1

0

X

1

0

X

1

0

X

1

0

X

1

0

X

1

X

0

X

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

n/a

X

n/a

0

X

P6.1/CB1/A1

P6.2/CB2/A2

P6.3/CB3/A3

P6.4/CB4/A4

P6.5/CB5/A5

P6.6/CB6/A6/DAC0

1

2

3

4

5

6

I: 0; O: 1

X

I: 0; O: 1

X

I: 0; O: 1

X

I: 0; O: 1

X

I: 0; O: 1

X

I: 0; O: 1

X

0

A6^{(2) (3)}

X

0

DAC0

X

0

>1

0

P6.7/CB7/A7/DAC1

7

P6.7 (I/O)

CB7

A7^{(2) (3)}

I: 0; O: 1

X

0

X

0

DAC1

0

>1

(1) X = Don't care

(2) Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals.

(3) The ADC12_A channel Ax is connected internally to AV_SSif not selected via the respective INCHx bits.

86

MSP430F563x

www.ti.com

SLAS650B –JUNE 2010–REVISED AUGUST 2011

Port P7, P7.2, Input/Output With Schmitt Trigger

Pad Logic

To XT2

P7REN.2

DV_SS

DV_CC

0

1

P7DIR.2

P7OUT.2

0

1

P7.2/XT2IN

P7DS.2

0: Low drive

1: High drive

P7SEL.2

P7IN.2

Bus

Keeper

87

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

Port P7, P7.3, Input/Output With Schmitt Trigger

Pad Logic

To XT2

P7REN.3

DV_SS

DV_CC

0

1

P7DIR.3

P7OUT.3

0

1

P7.3/XT2OUT

P7DS.3

0: Low drive

1: High drive

P7SEL.3

P7IN.3

Bus

Keeper

Table 61. Port P7 (P7.2 and P7.3) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P5.x)

x

FUNCTION

P7DIR.x

P7SEL.2

P7SEL.3

XT2BYPASS

P7.2/XT2IN

2

P7.2 (I/O)

I: 0; O: 1

0

1

0

1

X

0

1

X

0

1

XT2IN crystal mode⁽²⁾

XT2IN bypass mode⁽²⁾

P7.3 (I/O)

XT2OUT crystal mode⁽³⁾

P7.3 (I/O)⁽³⁾

X

P7.3/XT2OUT

3

I: 0; O: 1

X

(1) X = Don't care

(2) Setting P7SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P7.2 is configured for crystal

mode or bypass mode.

(3) Setting P7SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.3 can be used as

general-purpose I/O.

88

MSP430F563x

www.ti.com

SLAS650B –JUNE 2010–REVISED AUGUST 2011

Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger

0

Pad Logic

Dvss

1

2

0 if DAC12AMPx=0

1 if DAC12AMPx=1

2 if DAC12AMPx>1

From DAC12_A

To ADC12

INCHx = y

To Comparator_B

From Comparator_B

CBPD.x

DAC12AMPx>0

DAC12OPS

P7REN.x

DV_SS

DV_CC

0

1

P7DIR.x

P7OUT.x

P7.4/CB8/A12

P7.5/CB9/A13

P7.6/CB10/A14/DAC0

P7.7/CB11/A15/DAC1

P7DS.x

0: Low drive

1: High drive

P7SEL.x

P7IN.x

Bus

Keeper

89

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

Table 62. Port P7 (P7.4 to P7.7) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P7.x)

x

FUNCTION

P7DIR.x

P7SEL.x

CBPD.x

DAC12OPS

DAC12AMPx

P7.4/CB8/A12

4

P7.4 (I/O)

I: 0; O: 1

0

X

1

0

X

1

0

X

1

X

0

X

1

X

0

1

X

0

1

X

0

1

X

0

1

X

n/a

X

n/a

0

Comparator_B input CB8

A12^{(2) (3)}

X

P7.5/CB9/A13

5

6

P7.5 (I/O)

I: 0; O: 1

Comparator_B input CB9

A13^{(2) (3)}

X

P7.6/CB10/A14/DAC0

P7.6 (I/O)

I: 0; O: 1

Comparator_B input CB10

A14^{(2) (3)}

X

0

X

0

DAC12_A output DAC0

P7.7 (I/O)

X

1

>1

0

P7.7/CB11/A15/DAC1

7

I: 0; O: 1

X

Comparator_B input CB11

A15^{(2) (3)}

X

0

X

0

DAC12_A output DAC1

1

>1

(1) X = Don't care

(2) Setting the P7SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals.

(3) The ADC12_A channel Ax is connected internally to AV_SSif not selected via the respective INCHx bits.

90

MSP430F563x

www.ti.com

SLAS650B –JUNE 2010–REVISED AUGUST 2011

Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger

Pad Logic

P8REN.x

DV_SS

DV_CC

0

1

P8DIR.x

0

1

Direction

0: Input

1: Output

From module

0

1

P8OUT.x

Module X OUT

P8.0/TB0CLK

P8.1/UCB1STE/UCA1CLK

P8.2/UCA1TXD/UCA1SIMO

P8.3/UCA1RXD/UCA1SOMI

P8.4/UCB1CLK/UCA1STE

P8.5/UCB1SIMO//UCB1SDA

P8.6/UCB1SOMI/UCB1SCL

P8.7

P8DS.x

0: Low drive

1: High drive

P8SEL.x

P8IN.x

EN

D

Module X IN

Table 63. Port P8 (P8.0 to P8.7) Pin Functions

CONTROL BITS/SIGNALS

PIN NAME (P9.x)

x

FUNCTION

P8DIR.x

P8SEL.x

P8.0/TB0CLK

0

P8.0 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Timer TB0.TB0CLK clock input

P8.1 (I/O)

0

I: 0; O: 1

X

P8.1/UCB1STE/UCA1CLK

P8.2/UCA1TXD/UCA1SIMO

P8.3/UCA1RXD/UCA1SOMI

P8.4/UCB1CLK/UCA1STE

P8.5/UCB1SIMO/UCB1SDA

P8.6/UCB1SOMI/UCB1SCL

P8.7

1

2

3

4

5

6

7

UCB1STE/UCA1CLK

P8.2 (I/O)

I: 0; O: 1

X

UCA1TXD/UCA1SIMO

P8.3 (I/O)

I: 0; O: 1

X

UCA1RXD/UCA1SOMI

P8.4 (I/O)

I: 0; O: 1

X

UCB1CLK/UCA1STE

P8.5 (I/O)

I: 0; O: 1

X

UCB1SIMO/UCB1SDA

P8.6 (I/O)

I: 0; O: 1

X

UCB1SOMI/UCB1SCL

P8.7 (I/O)

I: 0; O: 1

91

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger

Pad Logic

P9REN.x

0

1

DV_SS

DV_CC

1

Direction

0: Input

1: Output

P9DIR.x

P9OUT.x

P9.0

P9.1

P9.2

P9.3

P9.4

P9.5

P9.6

P9.7

P9DS.x

0: Low drive

1: High drive

P9IN.x

Table 64. Port P9 (P9.0 to P9.7) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P9.x)

x

FUNCTION

P9DIR.x

I: 0; O: 1

P9SEL.x

P9.0

P9.1

P9.2

P9.3

P9.4

P9.5

P9.6

P9.7

0

1

2

3

4

5

6

7

P9.0 (I/O)

P9.1 (I/O)

P9.2 (I/O)

P9.3 (I/O)

P9.4 (I/O)

P9.5 (I/O)

P9.6 (I/O)

P9.7 (I/O)

0

(1) X = Don't care

92

MSP430F563x

www.ti.com

SLAS650B –JUNE 2010–REVISED AUGUST 2011

Port PU.0/DP, PU.1/DM, PUR USB Ports

PUSEL

VUSB

VSSU

Pad Logic

PUOPE

0

1

USB output enable

PUOUT0

0

1

PU.0/

DP

USB DP output

PUIN0

USB DP input

PUIPE

.

PUIN1

USB DM input

PUOUT1

0

1

PU.1/

DM

USB DM output

VUSB

VSSU

Pad Logic

PUREN

PUR

“1”

PUSEL

PURIN

Table 65. Port PU.0/DP, PU.1/DM Output Functions

CONTROL BITS

PUDIR PUOUT1

PIN NAME

PU.1/DM PU.0/DP

FUNCTION

PUSEL

PUOUT0

0

1

X

0

1

X

0

1

0

1

Hi-Z

Outputs off

0

1

0

1

0

1

Outputs enabled

Direction set by

USB module

1

X

DM

DP

93

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

Table 66. Port PUR Input Functions

CONTROL BITS

FUNCTION

PUSEL

0

PUREN

0

Input disabled

Pull up disabled

Input disabled

Pull up enabled

0

1

0

1

Input enabled

Pull up disabled

Input enabled

Pull up enabled

94

MSP430F563x

www.ti.com

SLAS650B –JUNE 2010–REVISED AUGUST 2011

Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output

Pad Logic

PJREN.0

0

1

DV_SS

DV_CC

1

PJDIR.0

DVCC

0

1

PJOUT.0

0

1

From JTAG

PJ.0/TDO

PJDS.0

0: Low drive

1: High drive

From JTAG

PJIN.0

EN

D

Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output

Pad Logic

PJREN.x

0

1

DV_SS

DV_CC

1

PJDIR.x

DVSS

0

1

PJOUT.x

0

1

From JTAG

PJ.1/TDI/TCLK

PJ.2/TMS

PJ.3/TCK

PJDS.x

0: Low drive

1: High drive

From JTAG

PJIN.x

EN

D

To JTAG

95

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

Table 67. Port PJ (PJ.0 to PJ.3) Pin Functions

CONTROL BITS/

SIGNALS⁽¹⁾

PIN NAME (PJ.x)

PJ.0/TDO

x

FUNCTION

PJDIR.x

0

PJ.0 (I/O)⁽²⁾

TDO⁽³⁾

I: 0; O: 1

X

PJ.1/TDI/TCLK

PJ.2/TMS

1

2

3

PJ.1 (I/O)⁽²⁾

TDI/TCLK^{(3) (4)}

PJ.2 (I/O)⁽²⁾

TMS^{(3) (4)}

PJ.3 (I/O)⁽²⁾

TCK^{(3) (4)}

I: 0; O: 1

X

I: 0; O: 1

X

PJ.3/TCK

I: 0; O: 1

X

(1) X = Don't care

(2) Default condition

(3) The pin direction is controlled by the JTAG module.

(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.

96

MSP430F563x

www.ti.com

SLAS650B –JUNE 2010–REVISED AUGUST 2011

DEVICE DESCRIPTORS

Table 68 list the complete contents of the device descriptor tag-length-value (TLV) structure for each device type.

Table 68. 'F563x Device Descriptor Table⁽¹⁾

'F5638

Value

06h

'F5637

Value

06h

'F5636

Value

06h

'F5635

Value

06h

'F5634

Value

06h

'F5633

Value

06h

'F5632

Value

06h

'F5631

Value

06h

'F5630

Value

06h

Size

bytes

Description

Address

Info Block

Info length

CRC length

01A00h

01A01h

01A02h

01A04h

01A06h

01A07h

01A08h

01A09h

01A0Ah

01A0Eh

01A10h

01A12h

1

2

1

4

2

06h

CRC value

per unit

8014h

per unit

08h

per unit

8012h

per unit

08h

per unit

8010h

per unit

08h

per unit

800Eh

per unit

08h

per unit

8044h

per unit

08h

per unit

8042h

per unit

08h

per unit

8040h

per unit

08h

per unit

803Eh

per unit

08h

per unit

803Ch

per unit

08h

Device ID

Hardware revision

Firmware revision

Die Record Tag

Die Record length

Lot/Wafer ID

Die Record

0Ah

per unit

Die X position

Die Y position

Test results

ADC12

Calibration

ADC12 Calibration Tag

01A14h

01A15h

1

11h

10h

11h

10h

11h

10h

11h

10h

11h

10h

11h

10h

11h

10h

11h

10h

11h

10h

ADC12 Calibration

length

ADC Gain Factor

ADC Offset

01A16h

01A18h

2

per unit

ADC 1.5-V Reference

Temp. Sensor 30°C

01A1Ah

01A1Ch

01A1Eh

01A20h

01A22h

01A24h

2

per unit

ADC 1.5-V Reference

Temp. Sensor 85°C

ADC 2.0-V Reference

Temp. Sensor 30°C

ADC 2.0-V Reference

Temp. Sensor 85°C

ADC 2.5-V Reference

Temp. Sensor 30°C

ADC 2.5-V Reference

Temp. Sensor 85°C

(1) NA = Not applicable

97

MSP430F563x

SLAS650B –JUNE 2010–REVISED AUGUST 2011

www.ti.com

REVISION HISTORY

REVISION

COMMENTS

SLAS650

SLAS650A

SLAS650B

Product Preview release

Updated Product Preview including electrical specifications

Production Data release

98

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Feb-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

MSP430F5632IZQWR BGA MI

ZQW

113

2500

330.0

16.4

7.3

1.5

12.0

16.0

Q1

CROSTA

R JUNI

OR

MSP430F5632IZQWT BGA MI

ZQW

113

250

330.0

16.4

7.3

1.5

12.0

16.0

Q1

CROSTA

R JUNI

OR

MSP430F5635IPZR

MSP430F5637IPZR

LQFP

PZ

100

113

1000

2500

330.0

24.4

16.4

17.4

7.3

17.4

7.3

2.0

1.5

20.0

12.0

24.0

16.0

Q2

Q1

MSP430F5638IZQWR BGA MI

ZQW

CROSTA

R JUNI

OR

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Feb-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

MSP430F5632IZQWR BGA MICROSTAR

JUNIOR

ZQW

113

2500

336.6

28.6

MSP430F5632IZQWT BGA MICROSTAR

JUNIOR

ZQW

113

250

336.6

28.6

MSP430F5635IPZR

MSP430F5637IPZR

LQFP

PZ

100

113

1000

2500

346.0

336.6

346.0

336.6

41.0

28.6

MSP430F5638IZQWR BGA MICROSTAR

JUNIOR

ZQW

Pack Materials-Page 2

MECHANICAL DATA

MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996

PZ (S-PQFP-G100)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

75

M

0,08

51

50

76

26

100

0,13 NOM

1

25

12,00 TYP

Gage Plane

14,20

SQ

13,80

0,25

16,20

SQ

0,05 MIN

0°–7°

15,80

1,45

1,35

0,75

0,45

Seating Plane

0,08

1,60 MAX

4040149/B 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

1

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型号：	MSP430F5630IZQW
厂家：	TEXAS INSTRUMENTS
描述：	MIXED SIGNAL MICROCONTROLLER 混合信号微控制器微控制器
文件：	总106页 (文件大小：1254K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MSP430F5630IZQW [TI]

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