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MSP430F6459-HIREL

ZHCSFC2A –AUGUST 2016–REVISED AUGUST 2016

MSP430F6459-HIREL 混合信号微控制器

1 器件概述

1.1 特性

1

– 低频修整内部参照源 (REFO)

– 32kHz 晶体 (XT1)

• 低电源电压范围：

1.8V 到 3.6V

• 超低功耗

– 高达 32MHz 的高频晶振 (XT2)

– 工作模式 (AM)：

所有系统时钟均工作：

• 4 个定时器，分别配有 3、5 或 7 个捕捉/比较寄存

器

在 8MHz、3V 且闪存程序执行时为 295μA/MHz

（典型值）

• 3 个通用串行通信接口 (USCI)

– USCI_A0，USCI_A1 和 USCI_A2 都支持：

– 待机模式 (LPM3)：

看门狗（采用晶振）和电源监控器工作，完全

•

具有自动波特率检测功能的增强型通用异步收

发器 (UART)

RAM 保持，快速唤醒：

2.2V 时为 2μA，3V 时为 2.2μA（典型值）

– 关断、实时时钟 (RTC) 模式 (LPM 3.5)：

关断模式，RTC（采用晶振）工作：

3V 时为 1.1µA（典型值）

•

IrDA 编码器和解码器

同步串行外设接口 (SPI)

– USCI_B0，USCI_B1 和 USCI_B2 都支持：

•

I²C

同步串行外设接口 (SPI)

– 关断模式 (LPM4.5)：

• 具有内部共用基准、采样保持、和自动扫描功能的

12 位模数转换器 (ADC)

3V 时为 0.45µA（典型值）

• 在 3μs（典型值）内从待机模式唤醒

• 2 个具有同步功能的 12 位数模转换器 (DAC)

• 电压比较器

• 16 位精简指令集 (RISC) 架构、扩展存储器、高达

20MHz 的系统时钟

• 具有高达 160 段对比度控制的集成 LCD 驱动器

• 硬件乘法器支持 32 位运算

• 串行板上编程，无需外部编程电压

• 6 通道内部直接内存访问 (DMA)

• 具有电源电压后备开关的 RTC 模块

• 灵活的电源管理系统

– 内置可编程的低压降稳压器 (LDO)

– 电源电压监控、监视、和临时限电

• 统一时钟系统

– 针对频率稳定的锁频环路 (FLL) 控制环路

– 低功率低频内部时钟源 (VLO)

1.2 应用范围

•

模拟和数字传感器系统

数字电机控制

遥控

•

恒温器

数字定时器

手持仪表

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLASEC3

MSP430F6459-HIREL

ZHCSFC2A –AUGUST 2016–REVISED AUGUST 2016

www.ti.com.cn

1.3 说明

TI 的 MSP430™系列超低功耗微控制器种类繁多，各成员器件配备不同的外设集以满足各类应用的需求。

该架构与五种低功耗模式配合使用，是延长便携式测量应用电池寿命的最优选择。该器件具有一个强大的

16 位精简指令集 (RISC) 中央处理器 (CPU)，使用 16 位寄存器以及常数发生器，以便获得最高编码效率。

该数控振荡器 (DCO) 可在 3µs（典型值）内从低功率模式唤醒至激活模式。

MSP430F6459-HIREL 微控制器配有一个集成式 3.3V LDO、四个 16 位定时器、一个高性能 12 位 ADC、

三个 USCI、一个硬件乘法器、DMA、具有报警功能的 RTC 模块、一个比较器和多达 74 个 I/O 引脚。

这些器件的典型应用包括模拟和数字传感器系统、数字电机控制、遥控、恒温器、数字定时器以及手持仪

表。

器件信息⁽¹⁾

封装

器件型号

MSP430F6459-HIREL

封装尺寸（标称值）⁽²⁾

PZ (100)

16.0mm x 16.0mm

(1) 要获得最新的器件、封装和订购信息，请参见封装选项附录（节 9），或者访问德州仪器 (TI) 网站 www.ti.com。

(2) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参见机械数据（节 9中）。

1.4 功能方框图

图 1-1 给出了此器件的功能框图。

PA

PB

PC

PD

PU.0

PU.1

XIN XOUT

DV_CCDV_SS

AV_CCAV_SS

RST/NMI

LDOO LDOI

P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x

P9.x

XT2IN

64KB

32KB

RAM

I/O Ports

P1, P2

2×8 I/Os

Interrupt

Capability

I/O Ports

P3, P4

2×8 I/Os

Interrupt

Capability

I/O Ports

P5, P6

2×8 I/Os

I/O Ports

P7, P8

1×6 I/Os

1×8 I/Os

ACLK

SMCLK

SYS

Power

Management

I/O Ports

P9

1×8 I/Os

Unified

Clock

System

USCI0,1,2

512KB

384KB

MID

PU Port

LDO

XT2OUT

Watchdog

Ax: UART,

IrDA, SPI

Memory

Integrity

Detection

+2KB RAM

P2 Port

Mapping

Controller

LDO

SVM, SVS

Brownout

Bx: SPI, I²C

PE

1×8 I/Os

Flash

MCLK

PA

1×16 I/Os

PB

1×16 I/Os

PC

1×16 I/Os

PD

1×14 I/Os

+8B Backup

RAM

CPUXV2

and

Working

Registers

EEM

(L: 8+2)

DMA

ADC12_A

LCD_B

TA1 and

TA2

RTC_B

6 Channel

DAC12_A

REF

TA0

TB0

12 bit

200 ksps

JTAG,

SBW

Interface

160

Segments

12 bit

2 channels

voltage out

Comp_B

MPY32

CRC16

2 Timer_A

each with

3 CC

Reference

1.5 V, 2.0 V,

2.5 V

Timer_A

5 CC

Registers

Timer_B

7 CC

Registers

Battery

Backup

System

16 channels

(12 ext, 4 int)

Autoscan

Port PJ

Registers

图 1-1. 功能方框图

2

器件概述

MSP430F6459-HIREL

www.ti.com.cn

ZHCSFC2A –AUGUST 2016–REVISED AUGUST 2016

内容

1

器件概述.................................................... 1

6

Detailed Description ................................... 50

6.1 Overview ............................................ 50

6.2 CPU ................................................. 50

6.3 Instruction Set....................................... 51

6.4 Operating Modes.................................... 52

6.5 Interrupt Vector Addresses.......................... 53

6.6 Memory Organization ............................... 55

6.7 Bootloader (BSL) .................................... 55

6.8 JTAG Operation ..................................... 57

6.9 Flash Memory ....................................... 57

6.10 Memory Integrity Detection (MID)................... 58

6.11 RAM ................................................. 58

6.12 Backup RAM ........................................ 59

6.13 Peripherals .......................................... 59

6.14 Input/Output Schematics ............................ 86

6.15 Device Descriptors................................. 109

Applications, Implementation, and Layout ...... 110

1.1 特性 ................................................... 1

1.2 应用范围 .............................................. 1

1.3 说明 ................................................... 2

1.4 功能方框图............................................ 2

修订历史记录............................................... 4

Device Comparison ..................................... 5

Terminal Configuration and Functions.............. 6

4.1 Pin Diagram .......................................... 6

4.2 Signal Descriptions ................................... 7

Specifications ........................................... 14

5.1 Absolute Maximum Ratings......................... 14

5.2 ESD Ratings ........................................ 14

5.3 Recommended Operating Conditions............... 14

2

3

4

5

5.4

5.5

5.6

Active Mode Supply Current Into V_CCExcluding

External Current..................................... 16

Low-Power Mode Supply Currents (Into V_CC

)

7

8

Excluding External Current.......................... 16

Low-Power Mode With LCD Supply Currents (Into

7.1

Device Connection and Layout Fundamentals .... 110

7.2

Peripheral- and Interface-Specific Design

V_CC) Excluding External Current.................... 18

Information ......................................... 114

5.7

5.8

5.9

Schmitt-Trigger Inputs – General-Purpose I/O ..... 19

器件和文档支持......................................... 116

8.1 入门和下一步....................................... 116

8.2 Device Nomenclature.............................. 116

8.3 工具和软件 ......................................... 117

8.4 文档支持 ........................................... 118

8.5 接收文档更新通知.................................. 120

8.6 Community Resources............................. 120

8.7 商标 ................................................ 120

8.8 静电放电警告....................................... 120

8.9 出口管制提示....................................... 120

8.10 Glossary............................................ 120

机械、封装和可订购信息 .............................. 121

Leakage Current – General-Purpose I/O ........... 19

Outputs – General-Purpose I/O (Full Drive

Strength) ............................................ 19

5.10 Outputs – General-Purpose I/O (Reduced Drive

Strength) ............................................ 19

5.11 Thermal Resistance Characteristics for PZ Package

...................................................... 20

5.12 Typical Characteristics – Outputs, Reduced Drive

Strength (PxDS.y = 0)............................... 21

5.13 Typical Characteristics – Outputs, Full Drive

Strength (PxDS.y = 1)............................... 22

5.14 Timing and Switching Characteristics............... 23

9

内容

3

MSP430F6459-HIREL

ZHCSFC2A –AUGUST 2016–REVISED AUGUST 2016

www.ti.com.cn

2 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (July 2016) to Revision A

Page

•

已更改文档状态至量产数据和完整数据手册 ...................................................................................... 1

4

修订历史记录

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ZHCSFC2A –AUGUST 2016–REVISED AUGUST 2016

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4 Terminal Configuration and Functions

4.1 Pin Diagram

Figure 4-1 shows the pinout diagram.

P6.4/CB4/A4

P6.5/CB5/A5

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

P9.7/S0

2

P9.6/UCB2SOMI/UCB2SCL/S1

P9.5/UCB2SIMO/UCB2SDA/S2

P9.4/UCB2CLK/UCA2STE/S3

P9.3/UCA2RXD/UCA2SOMI/S4

P9.2/UCA2TXD/UCA2SIMO/S5

P9.1/UCB2STE/UCA2CLK/S6

P9.0/S7

P6.6/CB6/A6/DAC0

P6.7/CB7/A7/DAC1

P7.4/CB8/A12

P7.5/CB9/A13

P7.6/CB10/A14/DAC0

P7.7/CB11/A15/DAC1

P5.0/VREF+/VeREF+

P5.1/VREF−/VeREF−

AVCC1

3

4

5

6

7

8

9

P8.7/S8

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

P8.6/UCB1SOMI/UCB1SCL/S9

P8.5/UCB1SIMO/UCB1SDA/S10

DVCC2

AVSS1

XIN

DVSS2

XOUT

P8.4/UCB1CLK/UCA1STE/S11

P8.3/UCA1RXD/UCA1SOMI/S12

P8.2/UCA1TXD/UCA1SIMO/S13

P8.1/UCB1STE/UCA1CLK/S14

P8.0/TB0CLK/S15

AVSS2

P5.6/ADC12CLK/DMAE0

P2.0/P2MAP0

P2.1/P2MAP1

P4.7/TB0OUTH/SVMOUT/S16

P4.6/TB0.6/S17

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P4.5/TB0.5/S18

P2.5/P2MAP5

P4.4/TB0.4/S19

P2.6/P2MAP6/R03

P2.7/P2MAP7/LCDREF/R13

DVCC1

P4.3/TB0.3/S20

P4.2/TB0.2/S21

P4.1/TB0.1/S22

Figure 4-1. PZ S-PQFP-G100 Package

6

Terminal Configuration and Functions

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4.2 Signal Descriptions

Table 4-1 describes the signals for all device variants and package options.

Table 4-1. Signal Descriptions

TERMINAL

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

General-purpose digital I/O

P6.4/CB4/A4

P6.5/CB5/A5

1

I/O Comparator_B input CB4

Analog input A4 – ADC

General-purpose digital I/O

2

3

I/O Comparator_B input CB5

Analog input A5 – ADC

General-purpose digital I/O

Comparator_B input CB6

I/O

P6.6/CB6/A6/DAC0

P6.7/CB7/A7/DAC1

Analog input A6 – ADC

DAC12.0 output

General-purpose digital I/O

Comparator_B input CB7

I/O

4

Analog input A7 – ADC

DAC12.1 output

General-purpose digital I/O

P7.4/CB8/A12

P7.5/CB9/A13

5

6

I/O Comparator_B input CB8

Analog input A12 –ADC

General-purpose digital I/O

I/O Comparator_B input CB9

Analog input A13 – ADC

General-purpose digital I/O

Comparator_B input CB10

I/O

P7.6/CB10/A14/DAC0

P7.7/CB11/A15/DAC1

7

8

Analog input A14 – ADC

DAC12.0 output

General-purpose digital I/O

Comparator_B input CB11

I/O

Analog input A15 – ADC

DAC12.1 output

General-purpose digital I/O

P5.0/VREF+/VeREF+

P5.1/VREF-/VeREF-

9

I/O Output of reference voltage to the ADC

Input for an external reference voltage to the ADC

General-purpose digital I/O

10

I/O

Negative terminal for the ADC's reference voltage for both sources, the internal

reference voltage, or an external applied reference voltage

AVCC1

AVSS1

XIN

11

12

13

14

15

Analog power supply

Analog ground supply

I

Input terminal for crystal oscillator XT1

Output terminal of crystal oscillator XT1

Analog ground supply

XOUT

AVSS2

O

(1) I = input, O = output, N/A = not available on this package offering.

Terminal Configuration and Functions

7

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Table 4-1. Signal Descriptions (continued)

TERMINAL

NAME

I/O⁽¹⁾

DESCRIPTION

NO.

General-purpose digital I/O

P5.6/ADC12CLK/DMAE0

16

I/O Conversion clock output ADC

DMA external trigger input

General-purpose digital I/O with port interrupt and mappable secondary function

P2.0/P2MAP0

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

17

18

19

20

21

22

I/O

Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 SPI slave in, master out; USCI_B0 I2C data

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 SPI slave out, master in; USCI_B0 I2C clock

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in, master out

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_A0 UART receive data; USCI_A0 slave out, master in

General-purpose digital I/O with port interrupt and mappable secondary function

P2.6/P2MAP6/R03

23

24

I/O Default mapping: no secondary function

Input/output port of lowest analog LCD voltage (V5)

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: no secondary function

P2.7/P2MAP7/LCDREF/R13

I/O

External reference voltage input for regulated LCD voltage

Input/output port of third most positive analog LCD voltage (V3 or V4)

Digital power supply

DVCC1

25

26

27

DVSS1

VCORE⁽²⁾

Digital ground supply

Regulated core power supply (internal use only, no external current loading)

General-purpose digital I/O

P5.2/R23

28

I/O

Input/output port of second most positive analog LCD voltage (V2)

LCD capacitor connection

LCDCAP/R33

COM0

29

30

I/O

Input/output port of most positive analog LCD voltage (V1)

O

LCD common output COM0 for LCD backplane

General-purpose digital I/O

P5.3/COM1/S42

P5.4/COM2/S41

P5.5/COM3/S40

31

32

33

I/O LCD common output COM1 for LCD backplane

LCD segment output S42

General-purpose digital I/O

I/O LCD common output COM2 for LCD backplane

LCD segment output S41

General-purpose digital I/O

I/O LCD common output COM3 for LCD backplane

LCD segment output S40

(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended

capacitor value, C_VCORE

.

8

Terminal Configuration and Functions

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Table 4-1. Signal Descriptions (continued)

TERMINAL

NAME

I/O⁽¹⁾

DESCRIPTION

General-purpose digital I/O with port interrupt

NO.

Timer TA0 clock signal TACLK input

P1.0/TA0CLK/ACLK/S39

P1.1/TA0.0/S38

34

I/O

ACLK output (divided by 1, 2, 4, 8, 16, or 32)

LCD segment output S39

General-purpose digital I/O with port interrupt

Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output

BSL transmit output

35

36

I/O

LCD segment output S38

General-purpose digital I/O with port interrupt

Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output

BSL receive input

P1.2/TA0.1/S37

LCD segment output S37

General-purpose digital I/O with port interrupt

P1.3/TA0.2/S36

P1.4/TA0.3/S35

P1.5/TA0.4/S34

P1.6/TA0.1/S33

P1.7/TA0.2/S32

37

38

39

40

41

I/O Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output

LCD segment output S36

General-purpose digital I/O with port interrupt

I/O Timer TA0 CCR3 capture: CCI3A input compare: Out3 output

LCD segment output S35

General-purpose digital I/O with port interrupt

I/O Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output

LCD segment output S34

General-purpose digital I/O with port interrupt

I/O Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output

LCD segment output S33

General-purpose digital I/O with port interrupt

I/O Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output

LCD segment output S32

General-purpose digital I/O with port interrupt

Timer TA1 clock input

I/O

P3.0/TA1CLK/CBOUT/S31

42

Comparator_B output

LCD segment output S31

General-purpose digital I/O with port interrupt

P3.1/TA1.0/S30

P3.2/TA1.1/S29

P3.3/TA1.2/S28

43

44

45

I/O Timer TA1 capture CCR0: CCI0A/CCI0B input, compare: Out0 output

LCD segment output S30

General-purpose digital I/O with port interrupt

I/O Timer TA1 capture CCR1: CCI1A/CCI1B input, compare: Out1 output

LCD segment output S29

General-purpose digital I/O with port interrupt

I/O Timer TA1 capture CCR2: CCI2A/CCI2B input, compare: Out2 output

LCD segment output S28

Terminal Configuration and Functions

9

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Table 4-1. Signal Descriptions (continued)

TERMINAL

NAME

I/O⁽¹⁾

DESCRIPTION

General-purpose digital I/O with port interrupt

NO.

Timer TA2 clock input

SMCLK output

P3.4/TA2CLK/SMCLK/S27

46

I/O

LCD segment output S27

General-purpose digital I/O with port interrupt

P3.5/TA2.0/S26

P3.6/TA2.1/S25

P3.7/TA2.2/S24

P4.0/TB0.0/S23

P4.1/TB0.1/S22

P4.2/TB0.2/S21

P4.3/TB0.3/S20

P4.4/TB0.4/S19

P4.5/TB0.5/S18

P4.6/TB0.6/S17

47

48

49

50

51

52

53

54

55

56

I/O Timer TA2 capture CCR0: CCI0A/CCI0B input, compare: Out0 output

LCD segment output S26

General-purpose digital I/O with port interrupt

I/O Timer TA2 capture CCR1: CCI1A/CCI1B input, compare: Out1 output

LCD segment output S25

General-purpose digital I/O with port interrupt

I/O Timer TA2 capture CCR2: CCI2A/CCI2B input, compare: Out2 output

LCD segment output S24

General-purpose digital I/O with port interrupt

I/O Timer TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output

LCD segment output S23

General-purpose digital I/O with port interrupt

I/O Timer TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output

LCD segment output S22

General-purpose digital I/O with port interrupt

I/O Timer TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output

LCD segment output S21

General-purpose digital I/O with port interrupt

I/O Timer TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output

LCD segment output S20

General-purpose digital I/O with port interrupt

I/O Timer TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output

LCD segment output S19

General-purpose digital I/O with port interrupt

I/O Timer TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output

LCD segment output S18

General-purpose digital I/O with port interrupt

I/O Timer TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output

LCD segment output S17

General-purpose digital I/O with port interrupt

Timer TB0: Switch all PWM outputs high impedance

P4.7/TB0OUTH/SVMOUT/S16

P8.0/TB0CLK/S15

57

58

I/O

SVM output

LCD segment output S16

General-purpose digital I/O

I/O Timer TB0 clock input

LCD segment output S15

10

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Table 4-1. Signal Descriptions (continued)

TERMINAL

NAME

I/O⁽¹⁾

DESCRIPTION

NO.

General-purpose digital I/O

USCI_B1 SPI slave transmit enable

USCI_A1 clock input/output

P8.1/UCB1STE/UCA1CLK/S14

P8.2/UCA1TXD/UCA1SIMO/S13

P8.3/UCA1RXD/UCA1SOMI/S12

P8.4/UCB1CLK/UCA1STE/S11

59

I/O

LCD segment output S14

General-purpose digital I/O

USCI_A1 UART transmit data

60

61

62

I/O

USCI_A1 SPI slave in, master out

LCD segment output S13

General-purpose digital I/O

USCI_A1 UART receive data

USCI_A1 SPI slave out, master in

LCD segment output S12

General-purpose digital I/O

USCI_B1 clock input/output

USCI_A1 SPI slave transmit enable

LCD segment output S11

Digital ground supply

DVSS2

DVCC2

63

64

Digital power supply

General-purpose digital I/O

USCI_B1 SPI slave in, master out

USCI_B1 I2C data

P8.5/UCB1SIMO/UCB1SDA/S10

P8.6/UCB1SOMI/UCB1SCL/S9

65

66

I/O

LCD segment output S10

General-purpose digital I/O

USCI_B1 SPI slave out, master in

USCI_B1 I2C clock

LCD segment output S9

General-purpose digital I/O

P8.7/S8

P9.0/S7

67

68

I/O

LCD segment output S8

General-purpose digital I/O

LCD segment output S7

General-purpose digital I/O

USCI_B2 SPI slave transmit enable

USCI_A2 clock input/output

P9.1/UCB2STE/UCA2CLK/S6

P9.2/UCA2TXD/UCA2SIMO/S5

P9.3/UCA2RXD/UCA2SOMI/S4

69

70

71

I/O

LCD segment output S6

General-purpose digital I/O

USCI_A2 UART transmit data

USCI_A2 SPI slave in, master out

LCD segment output S5

General-purpose digital I/O

USCI_A2 UART receive data

USCI_A2 SPI slave out, master in

LCD segment output S4

Terminal Configuration and Functions

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Table 4-1. Signal Descriptions (continued)

TERMINAL

NAME

I/O⁽¹⁾

DESCRIPTION

NO.

General-purpose digital I/O

USCI_B2 clock input/output

USCI_A2 SPI slave transmit enable

P9.4/UCB2CLK/UCA2STE/S3

P9.5/UCB2SIMO/UCB2SDA/S2

72

I/O

LCD segment output S3

General-purpose digital I/O

USCI_B2 SPI slave in, master out

USCI_B2 I2C data

73

I/O

LCD segment output S2

General-purpose digital I/O

USCI_B2 SPI slave out, master in

USCI_B2 I2C clock

P9.6/UCB2SOMI/UCB2SCL/S1

P9.7/S0

74

75

I/O

LCD segment output S1

General-purpose digital I/O

LCD segment output S0

PU ground supply

VSSU

PU.0/DP

NC

76

77

78

79

80

81

82

83

I/O PU control register (Port U is supplied the LDOO rail)

Not connected

PU.1/DM

LDOI

I/O PU control register (Port U is supplied the LDOO rail)

LDO input

LDOO

NC

LDO output

Not connected

Analog ground supply

AVSS3

General-purpose digital I/O

I/O

P7.2/XT2IN

84

85

Input terminal for crystal oscillator XT2

General-purpose digital I/O

I/O

P7.3/XT2OUT

Output terminal of crystal oscillator XT2

Capacitor for backup subsystem. Do not load this pin externally. For capacitor values,

see C_BAKin Section 5.3.

VBAK

VBAT

86

87

Backup supply voltage. If backup voltage is not supplied, connect to DVCC externally.

General-purpose digital I/O

P5.7/RTCCLK

88

I/O

RTCCLK output

DVCC3

DVSS3

89

90

Digital power supply

Digital ground supply

Test mode pin – select digital I/O on JTAG pins

TEST/SBWTCK

PJ.0/TDO

91

92

93

94

95

I

Spy-Bi-Wire input clock

General-purpose digital I/O

I/O

Test data output port

General-purpose digital I/O

PJ.1/TDI/TCLK

PJ.2/TMS

Test data input or test clock input

General-purpose digital I/O

Test mode select

General-purpose digital I/O

PJ.3/TCK

Test clock

12

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Table 4-1. Signal Descriptions (continued)

TERMINAL

NAME

I/O⁽¹⁾

DESCRIPTION

NO.

Reset input active low⁽³⁾

RST/NMI/SBWTDIO

P6.0/CB0/A0

96

I/O Nonmaskable interrupt input

Spy-Bi-Wire data input/output

General-purpose digital I/O

97

98

99

I/O Comparator_B input CB0

Analog input A0 – ADC

General-purpose digital I/O

P6.1/CB1/A1

I/O Comparator_B input CB1

Analog input A1 – ADC

General-purpose digital I/O

P6.2/CB2/A2

I/O Comparator_B input CB2

Analog input A2 – ADC

General-purpose digital I/O

P6.3/CB3/A3

Reserved

100

N/A

I/O Comparator_B input CB3

Analog input A3 – ADC

Reserved BGA package balls. TI recommends connecting to ground (DVSS, AVSS).

(3) When this pin is configured as reset, the internal pullup resistor is enabled by default.

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5 Specifications

5.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

4.1

UNIT

V

Voltage applied at V_CCto V_SS

Voltage applied to any pin (excluding VCORE, VBUS, V18)⁽²⁾

V_CC+ 0.3

±2

V

Diode current at any device pin

mA

°C

Maximum junction temperature, T_J

–40

–55

105

(3)

Storage temperature, T_stg

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V_SS. VCORE is for internal device use only. No external DC loading or voltage should be applied.

(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

5.2 ESD Ratings

VALUE

±1000

±250

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as

±1000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V

may actually have higher performance.

5.3 Recommended Operating Conditions

Typical values are specified at V_CC= 3.3 V and T_J= 25°C (unless otherwise noted)

MIN NOM

MAX UNIT

PMMCOREVx = 0

1.8

2

3.6

Supply voltage during program execution and flash

PMMCOREVx = 0, 1

PMMCOREVx = 0, 1, 2

PMMCOREVx = 0, 1, 2, 3

3.6

V

V_CC

programming (AVCC1 = DVCC1 = DVCC2 = DVCC3 =

(1)(2)

2.2

2.4

0

3.6

DV_CC= V_CC

)

3.6

V

V_SS

Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 = DVSS2 = DVSS3 = V_SS)

V_BAT,RTC

V_BAT,MEM

T_J

Backup-supply voltage with RTC operational

Backup-supply voltage with backup memory retained

Operating junction temperature

T_J= –40°C to 105°C

T version

1.7

1.2

–40

3.6

105

10

V

°C

nF

C_BAK

Capacitance at pin VBAK

Capacitor at VCORE⁽³⁾

1

4.7

C_VCORE

470

C_DVCC

C_VCORE

/

Capacitor ratio of DVCC to VCORE

10

(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be

tolerated during power up and operation.

(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Table 5-11 threshold parameters for

the exact values and further details.

(3) A capacitor tolerance of ±20% or better is required.

14

Specifications

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Recommended Operating Conditions (continued)

Typical values are specified at V_CC= 3.3 V and T_J= 25°C (unless otherwise noted)

MIN NOM

MAX UNIT

PMMCOREVx = 0,

1.8 V ≤ V_CC≤ 3.6 V

(default condition)

0

8

PMMCOREVx = 1,

2 V ≤ V_CC≤ 3.6 V

Processor frequency (maximum MCLK frequency)⁽⁴⁾⁽⁵⁾

(see Figure 5-1)

0

12

f_SYSTEM

MHz

PMMCOREVx = 2,

2.2 V ≤ V_CC≤ 3.6 V

16

20

PMMCOREVx = 3,

2.4 V ≤ V_CC≤ 3.6 V

(4) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the

specified maximum frequency.

(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

25

20

3

16

2, 3

2

12

8

1, 2

1, 2, 3

1

0

0, 1

0, 1, 2

0, 1, 2, 3

0

1.8

2.0

2.2

2.4

3.6

Supply Voltage - V

NOTE: The numbers within the fields denote the supported PMMCOREVx settings.

Figure 5-1. Frequency vs Supply Voltage

Specifications

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5.4 Active Mode Supply Current Into V_CCExcluding External Current

(2) (3)

over recommended operating junction temperature (unless otherwise noted)⁽¹⁾

FREQUENCY (f_DCO= f_MCLK= f_SMCLK

8 MHz 12 MHz

TYP MAX TYP MAX

)

EXECUTION

MEMORY

PARAMETER

V_CC

PMMCOREVx

1 MHz

20 MHz

UNIT

TYP

MAX

TYP

MAX

0

1

2

3

0

1

2

3

0.36

0.41

0.46

0.51

0.18

0.20

0.22

0.23

0.45

2.4

2.7

2.9

3.1

1.0

1.2

1.3

1.4

2.7

4.0

4.3

4.5

4.4

I_{AM, Flash}

Flash

RAM

3 V

mA

7.4

0.25

1.3

1.7

2.0

2.2

1.9

I_{AM, RAM}

3 V

mA

3.6

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load

capacitance are chosen to closely match the required 12.5 pF.

(3) Characterized with program executing typical data processing.

f_ACLK= 32786 Hz, f_DCO= f_MCLK= f_SMCLKat specified frequency.

XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.

5.5 Low-Power Mode Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)⁽¹⁾

(2)

–40°C

TYP MAX

25°C

TYP MAX

73 95

60°C

TYP MAX

79

105°C

TYP MAX

101

PARAMETER

V_CC

PMMCOREVx

UNIT

µA

2.2 V

3 V

0

3

0

3

0

1

2

0

1

2

3

0

1

2

3

69

79

135

155

40

I_LPM0,1MHzLow-power mode 0^{(3) (4)}

83

6.7

7.1

2.0

2.2

2.4

2.2

2.4

2.6

1.3

1.5

1.6

120

9.0

9.5

3.3

87

8.0

8.5

3.3

3.6

3.8

3.6

3.8

4.0

2.7

2.8

2.9

116

22

2.2 V

3 V

6.1

6.5

1.5

1.7

1.9

1.8

1.9

2.1

1.0

1.1

I_LPM2

Low-power mode 2^{(5) (4)}

µA

24

42

18

34

2.2 V

8.5

18.7

18.3

18.7

18.8

19.4

17.2

17.5

17.6

18.2

Low-power mode 3,

crystal mode^{(6) (4)}

I_LPM3,XT1LF

3.5

35

µA

3 V

4.2

2.7

37

34

Low-power mode 3,

VLO mode, Watchdog

enabled^{(7) (4)}

I_LPM3,VLO,

WDT

3 V

3.2

35

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external

load capacitance are chosen to closely match the required 9 pF.

(3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), f_ACLK= 32768 Hz, f_MCLK= 0 MHz, f_SMCLK= f_DCO= 1 MHz

(4) Current for brownout included. Low-side supervisor and monitors disabled (SVS_L, SVM_L). High-side supervisor and monitor disabled

(SVS_H, SVM_H). RAM retention enabled.

(5) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation

(XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), f_ACLK= 32768 Hz, f_MCLK= 0 MHz, f_SMCLK= f_DCO= 0 MHz, DCO

setting = 1 MHz operation, DCO bias generator enabled.

(6) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation

(XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), f_ACLK= 32768 Hz, f_MCLK= f_SMCLK= f_DCO= 0 MHz

(7) Current for watchdog timer clocked by VLO included.

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), f_ACLK= f_MCLK= f_SMCLK= f_DCO= 0 MHz

16

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Low-Power Mode Supply Currents (Into V_CC) Excluding External Current (continued)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)^{(1) (2)}

–40°C

TYP MAX

0.9

25°C

TYP MAX

1.3 2.5

60°C

TYP MAX

2.5

105°C

TYP MAX

17.1 34

PARAMETER

V_CC

PMMCOREVx

UNIT

0

1

2

3

1.0

1.3

1.4

2.6

2.7

17.3

17.5

18

I_LPM4

Low-power mode 4^{(8) (4)}

Low-power mode 3.5

3 V

µA

3.1

36

I_LPM3.5,RTC,(LPM3.5) current with

3 V

0.5

0.6

1.25

0.78

2.3

µA

active RTC into primary

supply pin DV_CC

VCC

(9)

Low-power mode 3.5

I_LPM3.5,RTC,(LPM3.5) current with

1.3

active RTC into backup

VBAT

supply pin VBAT⁽¹⁰⁾

Total Low-power mode

I_LPM3.5,RTC,

TOT

3.5 (LPM3.5) current

3 V

1.0

0.4

1.1

1.2

0.5

1.93

1.21

3.3

2.4

µA

with active RTC⁽¹¹⁾

I_LPM4.5

Low-power mode 4.5⁽¹²⁾

0.45

0.6

(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), f_DCO= f_ACLK= f_MCLK= f_SMCLK= 0 MHz

(9) V_VBAT= V_CC- 0.2 V, f_DCO= f_MCLK= f_SMCLK= 0 MHz, f_ACLK= 32768 Hz, PMMREGOFF = 1, RTC in backup domain active

(10) V_VBAT= V_CC- 0.2 V, f_DCO= f_MCLK= f_SMCLK= 0 MHz, f_ACLK= 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no

current drawn on VBAK

(11) f_DCO= f_MCLK= f_SMCLK= 0 MHz, f_ACLK= 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no current drawn on VBAK

(12) Internal regulator disabled. No data retention.

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), f_DCO= f_ACLK= f_MCLK= f_SMCLK= 0 MHz

Specifications

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5.6 Low-Power Mode With LCD Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)⁽¹⁾⁽²⁾

TEMPERATURE (T_J)

PARAMETER

V_CC

PMMCOREVx

–40°C

TYP MAX

2.7

25°C

TYP MAX

3.3 4.8

60°C

TYP MAX

4.7

105°C

TYP MAX

18.3 35

UNIT

0

1

2

3

0

1

2

0

1

2

3

Low-power mode 3

(LPM3) current, LCD 4-

mux mode, internal

biasing, charge pump

disabled^{(3) (4)}

2.9

3.0

3.1

3.5

3.7

3.6

3.7

4.0

3.5

3.7

3.8

3.9

5.0

5.2

18.7

19

I_{LPM3 LCD,}

int. bias

3 V

µA

5.3

19.3

37

2.2 V

3 V

Low-power mode 3

(LPM3) current, LCD 4-

mux mode, internal

biasing, charge pump

enabled^{(3) (5)}

I_LPM3

LCD,CP

µA

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external

load capacitance are chosen to closely match the required 9 pF.

(3) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation

(XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), f_ACLK= 32768 Hz, f_MCLK= f_SMCLK= f_DCO= 0 MHz

Current for brownout included. Low-side supervisor (SVS_L) and low-side monitor (SVM_L) disabled. High-side supervisor (SVS_H) and

high-side monitor (SVM_H) disabled. RAM retention enabled.

(4) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump

disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (f_LCD= 32768 Hz / 32 / 4 = 256 Hz)

Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.

(5) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump

enabled), VLCDx = 1000 (V_LCD= 3 V, typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (f_LCD= 32768 Hz / 32 / 4 = 256 Hz)

Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.

18

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5.7 Schmitt-Trigger Inputs – General-Purpose I/O⁽¹⁾

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

1.8 V

3 V

MIN

0.80

1.50

0.45

0.75

0.3

TYP

MAX UNIT

1.40

V

V_IT+

V_IT–

V_hys

Positive-going input threshold voltage

2.10

1.8 V

3 V

1.00

V

Negative-going input threshold voltage

1.65

1.8 V

3 V

0.8

V

Input voltage hysteresis (V_IT+– V_IT–

)

0.4

1.0

For pullup: V_IN= V_SS

For pulldown: V_IN= V_CC

R_Pull

C_I

Pullup or pulldown resistor⁽²⁾

Input capacitance

20

35

5

50

kΩ

V_IN= V_SSor V_CC

pF

(1) The same parametrics apply to the clock input pin when the crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).

(2) Also applies to RST pin when pullup or pulldown resistor is enabled.

5.8 Leakage Current – General-Purpose I/O

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

±50 nA

(1)(2)

I_lkg(Px.y)

High-impedance leakage current

1.8 V, 3 V

(1) The leakage current is measured with V_SSor V_CCapplied to the corresponding pin(s), unless otherwise noted.

(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is

disabled.

5.9 Outputs – General-Purpose I/O (Full Drive Strength)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_(OHmax)= –3 mA⁽¹⁾

V_CC

MIN

V_CC– 0.25

V_CC– 0.60

V_CC– 0.25

V_CC– 0.60

MAX UNIT

V_CC

1.8 V

I_(OHmax)= –10 mA⁽²⁾

I_(OHmax)= –5 mA⁽¹⁾

I_(OHmax)= –15 mA⁽²⁾

I_(OLmax)= 3 mA⁽¹⁾

I_(OLmax)= 10 mA⁽²⁾

I_(OLmax)= 5 mA⁽¹⁾

I_(OLmax)= 15 mA⁽²⁾

V_CC

V_OH

High-level output voltage

V

V_CC

3 V

1.8 V

3 V

V_CC

V_SSV_SS+ 0.25

V_SSV_SS+ 0.60

V_SSV_SS+ 0.25

V_SSV_SS+ 0.60

V_OL

Low-level output voltage

V

(1) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop

specified.

(2) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage

drop specified.

5.10 Outputs – General-Purpose I/O (Reduced Drive Strength)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

I_(OHmax)= –1 mA⁽²⁾

I_(OHmax)= –3 mA⁽³⁾

I_(OHmax)= –2 mA⁽²⁾

I_(OHmax)= –6 mA⁽³⁾

V_CC

MIN

V_CC– 0.25

V_CC– 0.60

V_CC– 0.25

V_CC– 0.60

MAX UNIT

V_CC

1.8 V

V_CC

V_OH

High-level output voltage

V

V_CC

3 V

V_CC

(1) Selecting reduced drive strength may reduce EMI.

(2) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop

specified.

(3) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage

drop specified.

Specifications

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Outputs – General-Purpose I/O (Reduced Drive Strength) (continued)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

I_(OLmax)= 1 mA⁽²⁾

I_(OLmax)= 3 mA⁽³⁾

I_(OLmax)= 2 mA⁽²⁾

I_(OLmax)= 6 mA⁽³⁾

V_CC

MIN

MAX UNIT

V_SSV_SS+ 0.25

V_SSV_SS+ 0.60

V_SSV_SS+ 0.25

V_SSV_SS+ 0.60

1.8 V

V_OL

Low-level output voltage

V

3 V

5.11 Thermal Resistance Characteristics for PZ Package

PARAMETER

PACKAGE

QFP (PZ)

VALUE

122

83

UNIT

°C/W

θ_JA

Junction-to-ambient thermal resistance, still air⁽¹⁾

Junction-to-case (top) thermal resistance⁽²⁾

Junction-to-board thermal resistance⁽³⁾

θ_JC(TOP)

θ_JB

QFP (PZ)

98

(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

20

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5.12 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

25.0

20.0

15.0

10.0

5.0

8.0

7.0

6.0

5.0

4.0

3.0

2.0

1.0

0.0

T_J= 25°C

T_J= 105°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

V_OL– Low-Level Output Voltage – V

V_CC= 3 V

V_CC= 1.8 V

Figure 5-2. Typical Low-Level Output Current vs Low-Level

Output Voltage

Figure 5-3. Typical Low-Level Output Current vs Low-Level

Output Voltage

0.0

−1.0

−2.0

−3.0

−4.0

−5.0

−10.0

T_J= 105°C

−5.0

−15.0

T_J= 105°C

−6.0

T_J= 25°C

−20.0

T_J= 25°C

−7.0

−8.0

−25.0

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

V_OH– High-Level Output Voltage – V

V_CC= 1.8 V

V_CC= 3 V

Figure 5-5. Typical High-Level Output Current vs High-Level

Output Voltage

Figure 5-4. Typical High-Level Output Current vs High-Level

Output Voltage

Specifications

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5.13 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

60.0

24

T_J= 25°C

55.0

T_J= 25°C

50.0

20

T_J= 105°C

45.0

40.0

35.0

30.0

25.0

20.0

15.0

10.0

5.0

16

12

8

T_J= 105°C

4

0

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

V_OL– Low-Level Output Voltage – V

V_CC= 1.8 V

V_CC= 3 V

Figure 5-7. Typical Low-Level Output Current vs Low-Level

Output Voltage

Figure 5-6. Typical Low-Level Output Current vs Low-Level

Output Voltage

0.0

−5.0

0

−10.0

−15.0

−20.0

−25.0

−30.0

−35.0

−40.0

−4

−8

−12

T_J= 105°C

−16

−45.0

T_J= 105°C

−50.0

T_J= 25°C

−20

−55.0

T_J= 25°C

−60.0

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

V_OH– High-Level Output Voltage – V

V_CC= 1.8 V

V_CC= 3 V

Figure 5-9. Typical High-Level Output Current vs High-Level

Output Voltage

Figure 5-8. Typical High-Level Output Current vs High-Level

Output Voltage

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5.14 Timing and Switching Characteristics

5.14.1 Power Supply Sequencing

TI recommends powering the AVCC and DVCC pins from the same source. At a minimum, during power

up, power down, and device operation, the voltage difference between AVCC and DVCC must not exceed

the limits specified in the Absolute Maximum Ratings section. Exceeding the specified limits may cause

malfunction of the device including erroneous writes to RAM and FRAM.

Table 5-1. PMM, Brownout Reset (BOR)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

| dDV_CC/d_t| < 3 V/s

MIN

TYP

MAX UNIT

V_{(DVCC_BOR_IT–)}

V_{(DVCC_BOR_IT+)}

V_{(DVCC_BOR_hys)}

t_RESET

BOR_Hon voltage, DV_CCfalling level

BOR_Hoff voltage, DV_CCrising level

BOR_Hhysteresis

1.45

1.50

250

V

0.80

60

2

1.30

mV

µs

Pulse duration required at RST/NMI pin to accept a reset

5.14.2 Clock Specifications

Table 5-2. Inputs – Ports P1, P2, P3, and P4⁽¹⁾

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

Port P1, P2, P3, P4: P1.x to P4.x, External trigger pulse

duration to set interrupt flag

t_(int)

External interrupt timing⁽²⁾

2.2 V, 3 V

20

ns

(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.

(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t_(int)is met. It may be set by trigger signals

shorter than t_(int)

.

Table 5-3. Output Frequency – Ports P1, P2, and P3

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX UNIT

V_CC= 1.8 V,

PMMCOREVx = 0

8

Port output frequency

(with load)

P3.4/TA2CLK/SMCLK/S27,

f_Px.y

MHz

20

C_L= 20 pF, R_L= 1 kΩ ⁽¹⁾or 3.2 kΩ^{(2) (3)}

V_CC= 3 V,

PMMCOREVx = 3

V_CC= 1.8 V,

PMMCOREVx = 0

P1.0/TA0CLK/ACLK/S39,

P3.4/TA2CLK/SMCLK/S27,

P2.0/P2MAP0 (P2MAP0 = PM_MCLK),

C_L= 20 pF⁽³⁾

8

f_{Port_CLK}

Clock output frequency

MHz

20

V_CC= 3 V,

PMMCOREVx = 3

(1) Full drive strength of port: A resistive divider with 2 × 0.5 kΩ between V_CCand V_SSis used as load. The output is connected to the

center tap of the divider.

(2) Reduced drive strength of port: A resistive divider with 2 × 1.6 kΩ between V_CCand V_SSis used as load. The output is connected to the

center tap of the divider.

(3) The output voltage reaches at least 10% and 90% V_CCat the specified toggle frequency.

Specifications

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Table 5-4. Crystal Oscillator, XT1, Low-Frequency Mode⁽¹⁾

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 1, T_J= 25°C

V_CC

MIN

TYP

MAX UNIT

0.075

Differential XT1 oscillator

crystal current consumption f_OSC= 32768 Hz, XTS = 0,

ΔI_DVCC,LF

3 V

0.170

0.290

32768

µA

from lowest drive setting,

LF mode

XT1BYPASS = 0, XT1DRIVEx = 2, T_J= 25°C

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 3, T_J= 25°C

XT1 oscillator crystal

frequency, LF mode

f_XT1,LF0

XTS = 0, XT1BYPASS = 0

Hz

XT1 oscillator logic-level

square-wave input

(3)

f_XT1,LF,SW

XTS = 0, XT1BYPASS = 1⁽²⁾

10 32.768

50 kHz

frequency, LF mode

XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0,

f_XT1,LF= 32768 Hz, C_L,eff= 6 pF, T_J= 25°C

210

300

Oscillation allowance for

LF crystals⁽⁴⁾

OA_LF

3 V

kΩ

XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1,

f_XT1,LF= 32768 Hz, C_L,eff= 12 pF, T_J= 25°C

XTS = 0, XCAPx = 0⁽⁶⁾

XTS = 0, XCAPx = 1

XTS = 0, XCAPx = 2

XTS = 0, XCAPx = 3

1

5.5

Integrated effective load

capacitance, LF mode⁽⁵⁾

C_L,eff

pF

8.5

12.0

XTS = 0, Measured at ACLK,

f_XT1,LF= 32768 Hz

Duty cycle, LF mode

30%

10

70%

Oscillator fault frequency,

LF mode⁽⁷⁾

f_Fault,LF

XTS = 0⁽⁸⁾

10000

Hz

ms

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 0,

T_J= 25°C, C_L,eff= 6 pF

1000

500

t_START,LF

Start-up time, LF mode

3 V

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 3,

T_J= 25°C, C_L,eff= 12 pF

(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.

•

Keep the trace between the device and the crystal as short as possible.

Design a good ground plane around the oscillator pins.

Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.

If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.

(2) When XT1BYPASS is set, XT1 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined in

the Schmitt-trigger Inputs section of this data sheet.

(3) Maximum frequency of operation of the entire device cannot be exceeded.

(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the

XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following

guidelines, but should be evaluated based on the actual crystal selected for the application:

•

For XT1DRIVEx = 0, C_L,eff≤ 6 pF.

For XT1DRIVEx = 1, 6 pF ≤ C_L,eff≤ 9 pF.

For XT1DRIVEx = 2, 6 pF ≤ C_L,eff≤ 10 pF.

For XT1DRIVEx = 3, C_L,eff≥ 6 pF.

(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a

correct setup, the effective load capacitance should always match the specification of the used crystal.

(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(8) Measured with logic-level input frequency but also applies to operation with crystals.

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Table 5-5. Crystal Oscillator, XT2

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)⁽¹⁾

(2)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

f_OSC= 4 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 0, T_J= 25°C

200

f_OSC= 12 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 1, T_J= 25°C

260

325

450

XT2 oscillator crystal current

consumption

I_DVCC,XT2

3 V

µA

f_OSC= 20 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 2, T_J= 25°C

f_OSC= 32 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 3, T_J= 25°C

XT2 oscillator crystal

frequency, mode 0

f_XT2,HF0

f_XT2,HF1

f_XT2,HF2

f_XT2,HF3

XT2DRIVEx = 0, XT2BYPASS = 0⁽³⁾

XT2DRIVEx = 1, XT2BYPASS = 0⁽³⁾

XT2DRIVEx = 2, XT2BYPASS = 0⁽³⁾

XT2DRIVEx = 3, XT2BYPASS = 0⁽³⁾

4

8

MHz

XT2 oscillator crystal

frequency, mode 1

16 MHz

24 MHz

32 MHz

XT2 oscillator crystal

frequency, mode 2

16

24

XT2 oscillator crystal

frequency, mode 3

XT2 oscillator logic-level

square-wave input

frequency

f_XT2,HF,SW

XT2BYPASS = 1^{(4) (3)}

0.7

32 MHz

XT2DRIVEx = 0, XT2BYPASS = 0,

f_XT2,HF0= 6 MHz, C_L,eff= 15 pF, T_J= 25°C

450

320

200

0.5

XT2DRIVEx = 1, XT2BYPASS = 0,

f_XT2,HF1= 12 MHz, C_L,eff= 15 pF, T_J= 25°C

Oscillation allowance for

HF crystals⁽⁵⁾

OA_HF

3 V

Ω

XT2DRIVEx = 2, XT2BYPASS = 0,

f_XT2,HF2= 20 MHz, C_L,eff= 15 pF, T_J= 25°C

XT2DRIVEx = 3, XT2BYPASS = 0,

f_XT2,HF3= 32 MHz, C_L,eff= 15 pF, T_J= 25°C

f_OSC= 6 MHz, XT2BYPASS = 0, XT2DRIVEx = 0,

T_J= 25°C, C_L,eff= 15 pF

t_START,HF

Start-up time

3 V

ms

pF

f_OSC= 20 MHz, XT2BYPASS = 0, XT2DRIVEx = 3,

T_J= 25°C, C_L,eff= 15 pF

0.3

Integrated effective load

C_L,eff

1

capacitance, HF mode^{(6) (1)}

Duty cycle

Measured at ACLK, f_XT2,HF2= 20 MHz

40%

30

50%

60%

300 kHz

f_Fault,HF

Oscillator fault frequency⁽⁷⁾XT2BYPASS = 1⁽⁸⁾

(1) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

(2) To improve EMI on the XT2 oscillator the following guidelines should be observed.

•

Keep the traces between the device and the crystal as short as possible.

Design a good ground plane around the oscillator pins.

Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.

Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.

Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.

If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.

(3) Maximum frequency of operation of the entire device cannot be exceeded.

(4) When XT2BYPASS is set, the XT2 circuit is automatically powered down.

(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.

(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a

correct setup, the effective load capacitance should always match the specification of the used crystal.

(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(8) Measured with logic-level input frequency but also applies to operation with crystals.

Specifications

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Table 5-6. Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

VLO frequency

VLO frequency temperature drift

TEST CONDITIONS

V_CC

MIN

TYP

9.4

0.5

4

MAX UNIT

14 kHz

%/°C

f_VLO

Measured at ACLK

1.8 V to 3.6 V

6

df_VLO/d_T

Measured at ACLK⁽¹⁾

Measured at ACLK⁽²⁾

Measured at ACLK

df_VLO/dV_CCVLO frequency supply voltage drift

Duty cycle

%/V

40%

50%

60%

(1) Calculated using the box method: (MAX(–40°C to 105°C) – MIN(–40°C to 105°C)) / MIN(–40°C to 105°C) / (105°C – (–40°C))

(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

Table 5-7. Internal Reference, Low-Frequency Oscillator (REFO)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

3

MAX UNIT

REFO oscillator current

consumption

I_REFO

T_J= 25°C

1.8 V to 3.6 V

µA

REFO frequency calibrated

Measured at ACLK

Full temperature range

T_J= 25°C

1.8 V to 3.6 V

3 V

32768

Hz

±3.5%

f_REFO

REFO absolute tolerance

calibrated

±1.5%

df_REFO/d_T

REFO frequency temperature drift Measured at ACLK⁽¹⁾

1.8 V to 3.6 V

0.01

1.0

%/°C

REFO frequency supply voltage

Measured at ACLK⁽²⁾

drift

df_REFO/dV_CC

1.8 V to 3.6 V

%/V

Duty cycle

Measured at ACLK

40%/60% duty cycle

1.8 V to 3.6 V

40%

50%

25

60%

µs

t_START

REFO start-up time

(1) Calculated using the box method: (MAX(–40°C to 105°C) – MIN(–40°C to 105°C)) / MIN(–40°C to 105°C) / (105°C – (–40°C))

(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

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Table 5-8. DCO Frequency

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

DCORSELx = 0, DCOx = 0, MODx = 0

DCORSELx = 0, DCOx = 31, MODx = 0

DCORSELx = 1, DCOx = 0, MODx = 0

DCORSELx = 1, DCOx = 31, MODx = 0

DCORSELx = 2, DCOx = 0, MODx = 0

DCORSELx = 2, DCOx = 31, MODx = 0

DCORSELx = 3, DCOx = 0, MODx = 0

DCORSELx = 3, DCOx = 31, MODx = 0

DCORSELx = 4, DCOx = 0, MODx = 0

DCORSELx = 4, DCOx = 31, MODx = 0

DCORSELx = 5, DCOx = 0, MODx = 0

DCORSELx = 5, DCOx = 31, MODx = 0

DCORSELx = 6, DCOx = 0, MODx = 0

DCORSELx = 6, DCOx = 31, MODx = 0

DCORSELx = 7, DCOx = 0, MODx = 0

DCORSELx = 7, DCOx = 31, MODx = 0

MIN

0.07

0.70

0.15

1.47

0.32

3.17

0.64

6.07

1.3

TYP

MAX UNIT

0.20 MHz

1.70 MHz

0.36 MHz

3.45 MHz

0.75 MHz

7.38 MHz

1.51 MHz

14.0 MHz

3.2 MHz

f_DCO(0,0)

f_DCO(0,31)

f_DCO(1,0)

f_DCO(1,31)

f_DCO(2,0)

f_DCO(2,31)

f_DCO(3,0)

f_DCO(3,31)

f_DCO(4,0)

f_DCO(4,31)

f_DCO(5,0)

f_DCO(5,31)

f_DCO(6,0)

f_DCO(6,31)

f_DCO(7,0)

f_DCO(7,31)

DCO frequency (0, 0)⁽¹⁾

DCO frequency (0, 31)⁽¹⁾

DCO frequency (1, 0)⁽¹⁾

DCO frequency (1, 31)⁽¹⁾

DCO frequency (2, 0)⁽¹⁾

DCO frequency (2, 31)⁽¹⁾

DCO frequency (3, 0)⁽¹⁾

DCO frequency (3, 31)⁽¹⁾

DCO frequency (4, 0)⁽¹⁾

DCO frequency (4, 31)⁽¹⁾

DCO frequency (5, 0)⁽¹⁾

DCO frequency (5, 31)⁽¹⁾

DCO frequency (6, 0)⁽¹⁾

DCO frequency (6, 31)⁽¹⁾

DCO frequency (7, 0)⁽¹⁾

DCO frequency (7, 31)⁽¹⁾

12.3

2.5

28.2 MHz

6.0 MHz

23.7

4.6

54.1 MHz

10.7 MHz

88.0 MHz

19.6 MHz

135 MHz

39.0

8.5

60

Frequency step between range

DCORSEL and DCORSEL + 1

S_DCORSEL

S_DCO

S_RSEL= f_{DCO(DCORSEL+1,DCO)}/f_{DCO(DCORSEL,DCO)}

1.2

2.3 ratio

Frequency step between tap

DCO and DCO + 1

S_DCO= f_{DCO(DCORSEL,DCO+1)}/f_{DCO(DCORSEL,DCO)}

Measured at SMCLK

1.02

40%

1.12 ratio

Duty cycle

50%

0.1

60%

%/°C

%/V

df_DCO/dT

DCO frequency temperature drift f_DCO= 1 MHz,

DCO frequency voltage drift f_DCO= 1 MHz

df_DCO/dV_CC

1.9

(1) When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, f_DCO, should be set to reside within the

range of f_{DCO(n, 0),MAX}≤ f_DCO≤ f_{DCO(n, 31),MIN}, where f_{DCO(n, 0),MAX}represents the maximum frequency specified for the DCO frequency,

range n, tap 0 (DCOx = 0) and f_{DCO(n,31),MIN}represents the minimum frequency specified for the DCO frequency, range n, tap 31

(DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual

f_DCOfrequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the

selected range is at its minimum or maximum tap setting.

100

V_CC= 3.0 V

T_A= 25°C

10

DCOx = 31

1

DCOx = 0

0.1

0

1

2

3

4

5

6

7

DCORSEL

Figure 5-10. Typical DCO Frequency

Specifications

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Table 5-9. Wake-Up Times From Low-Power Modes

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

PMMCOREV = SVSMLRRL = n

(where n = 0, 1, 2, or 3),

SVSLFP = 1,

3

6.5

f

_MCLK≥ 4.0 MHz

Wake-up time from LPM2, LPM3, or LPM4

to active mode⁽¹⁾

t_WAKE-UP-FAST

PMMCOREV = SVSMLRRL = n

(where n = 0, 1, 2, or 3),

SVSLFP = 1,

µs

4

8.0

1 MHz < f_MCLK< 4.0 MHz

PMMCOREV = SVSMLRRL = n

(where n = 0, 1, 2, or 3),

SVSLFP = 0

Wake-up time from LPM2, LPM3 or LPM4

to active mode⁽²⁾

t_WAKE-UP-SLOW

150

165

Wake-up time from LPM3.5 or LPM4.5 to

active mode⁽³⁾

t_{WAKE-UP LPM5}

t_{WAKE-UP-RESET}

2

3

ms

Wake-up time from RST or BOR event to

active mode⁽³⁾

(1) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance

mode of the low-side supervisor (SVS_L) and low-side monitor (SVM_L). Fastest wake-up times are possible with SVS_Land SVM_Lin full-

performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVS_Land SVM_Lwhile

operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx

and MSP430x6xx Family User's Guide (SLAU208).

(2) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance

mode of the low-side supervisor (SVS_L) and low-side monitor (SVM_L). In this case, the SVS_Land SVM_Lare in normal mode (low

current) mode when operating in AM, LPM0, and LPM1. Various options are available for SVS_Land SVM_Lwhile operating in LPM2,

LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx

Family User's Guide (SLAU208).

(3) This value represents the time from the wake-up event to the reset vector execution.

5.14.3 Peripherals

Table 5-10. PMM, Core Voltage

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Core voltage, active mode,

PMMCOREV = 3

V_CORE3(AM)

V_CORE2(AM)

V_CORE1(AM)

V_CORE0(AM)

V_CORE3(LPM)

V_CORE2(LPM)

V_CORE1(LPM)

V_CORE0(LPM)

2.4 V ≤ DV_CC≤ 3.6 V, 0 mA ≤ I(V_CORE) ≤ 21 mA

1.90

V

Core voltage, active mode,

PMMCOREV = 2

2.2 V ≤ DV_CC≤ 3.6 V, 0 mA ≤ I(V_CORE) ≤ 21 mA

2 V ≤ DV_CC≤ 3.6 V, 0 mA ≤ I(V_CORE) ≤ 17 mA

1.8 V ≤ DV_CC≤ 3.6 V, 0 mA ≤ I(V_CORE) ≤ 13 mA

2.4 V ≤ DV_CC≤ 3.6 V, 0 µA ≤ I(V_CORE) ≤ 30 µA

2.2 V ≤ DV_CC≤ 3.6 V, 0 µA ≤ I(V_CORE) ≤ 30 µA

2 V ≤ DV_CC≤ 3.6 V, 0 µA ≤ I(V_CORE) ≤ 30 µA

1.8 V ≤ DV_CC≤ 3.6 V, 0 µA ≤ I(V_CORE) ≤ 30 µA

1.80

1.60

1.40

1.94

1.84

1.64

1.44

V

Core voltage, active mode,

PMMCOREV = 1

Core voltage, active mode,

PMMCOREV = 0

Core voltage, low-current mode,

PMMCOREV = 3

Core voltage, low-current mode,

PMMCOREV = 2

Core voltage, low-current mode,

PMMCOREV = 1

Core voltage, low-current mode,

PMMCOREV = 0

28

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Table 5-11. PMM, SVS High Side

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SVSHE = 0, DV_CC= 3.6 V

MIN

TYP

0

MAX UNIT

nA

I_(SVSH)

SVS current consumption

SVSHE = 1, DV_CC= 3.6 V, SVSHFP = 0

SVSHE = 1, DV_CC= 3.6 V, SVSHFP = 1

SVSHE = 1, SVSHRVL = 0

200

2.0

µA

1.59

1.79

1.98

2.10

1.62

1.88

2.07

2.20

2.32

2.56

2.85

1.64

1.84

2.04

2.16

1.74

1.94

2.14

2.26

2.40

2.70

3.00

2.5

1.69

SVSHE = 1, SVSHRVL = 1

1.91

V

V_{(SVSH_IT–)}

SVS_Hon voltage level⁽¹⁾

SVSHE = 1, SVSHRVL = 2

2.11

SVSHE = 1, SVSHRVL = 3

2.23

1.81

2.01

2.21

SVSHE = 1, SVSMHRRL = 0

SVSHE = 1, SVSMHRRL = 1

SVSHE = 1, SVSMHRRL = 2

SVSHE = 1, SVSMHRRL = 3

2.33

V

V_{(SVSH_IT+)}

SVS_Hoff voltage level⁽¹⁾

SVSHE = 1, SVSMHRRL = 4

2.48

SVSHE = 1, SVSMHRRL = 5

2.84

3.15

SVSHE = 1, SVSMHRRL = 6

SVSHE = 1, SVSMHRRL = 7

SVSHE = 1, dV_DVCC/dt = 10 mV/µs, SVSHFP = 1

SVSHE = 1, dV_DVCC/dt = 1 mV/µs, SVSHFP = 0

SVSHE = 0→1, SVSHFP = 1

t_pd(SVSH)

SVS_Hpropagation delay

µs

20

12.5

100

t_(SVSH)

SVS_Hon or off delay time

DV_CCrise time

SVSHE = 0→1, SVSHFP = 0

dV_DVCC/dt

0

1000

V/s

(1) The SVS_Hsettings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage

Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and usage.

Table 5-12. PMM, SVM High Side

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SVMHE = 0, DV_CC= 3.6 V

MIN

TYP

0

MAX UNIT

nA

I_(SVMH)

SVM_Hcurrent consumption

SVMHE = 1, DV_CC= 3.6 V, SVMHFP = 0

SVMHE = 1, DV_CC= 3.6 V, SVMHFP = 1

SVMHE = 1, SVSMHRRL = 0

200

2.0

µA

1.86

1.65

1.85

2.02

2.18

2.32

2.56

2.85

1.74

1.94

2.14

2.26

2.40

2.70

3.00

3.75

2.5

SVMHE = 1, SVSMHRRL = 1

2.02

SVMHE = 1, SVSMHRRL = 2

2.22

SVMHE = 1, SVSMHRRL = 3

2.35

V_(SVMH)

SVM_Hon or off voltage level⁽¹⁾

SVMHE = 1, SVSMHRRL = 4

2.48

2.84

3.15

V

SVMHE = 1, SVSMHRRL = 5

SVMHE = 1, SVSMHRRL = 6

SVMHE = 1, SVSMHRRL = 7

SVMHE = 1, SVMHOVPE = 1

SVMHE = 1, dV_DVCC/dt = 10 mV/µs, SVMHFP = 1

SVMHE = 1, dV_DVCC/dt = 1 mV/µs, SVMHFP = 0

SVMHE = 0→1, SVSMFP = 1

t_pd(SVMH)

SVM_Hpropagation delay

SVM_Hon or off delay time

µs

20

12.5

100

t_(SVMH)

SVMHE = 0→1, SVMHFP = 0

(1) The SVM_Hsettings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage

Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and usage.

Specifications

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Table 5-13. PMM, SVS Low Side

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SVSLE = 0, PMMCOREV = 2

MIN

TYP

0

MAX UNIT

nA

µA

µs

I_(SVSL)

SVS_Lcurrent consumption

SVSLE = 1, PMMCOREV = 2, SVSLFP = 0

SVSLE = 1, PMMCOREV = 2, SVSLFP = 1

SVSLE = 1, dV_CORE/dt = 10 mV/µs, SVSLFP = 1

SVSLE = 1, dV_CORE/dt = 1 mV/µs, SVSLFP = 0

SVSLE = 0→1, SVSLFP = 1

200

2.0

2.5

20

t_pd(SVSL)

SVS_Lpropagation delay

SVS_Lon or off delay time

12.5

100

t_(SVSL)

µs

SVSLE = 0→1, SVSLFP = 0

Table 5-14. PMM, SVM Low Side

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SVMLE = 0, PMMCOREV = 2

MIN

TYP

0

MAX UNIT

nA

µA

µs

I_(SVML)

SVM_Lcurrent consumption

SVMLE = 1, PMMCOREV = 2, SVMLFP = 0

SVMLE = 1, PMMCOREV = 2, SVMLFP = 1

SVMLE = 1, dV_CORE/dt = 10 mV/µs, SVMLFP = 1

SVMLE = 1, dV_CORE/dt = 1 mV/µs, SVMLFP = 0

SVMLE = 0→1, SVMLFP = 1

200

2.0

2.5

20

t_pd(SVML)

SVM_Lpropagation delay

SVM_Lon or off delay time

12.5

100

t_(SVML)

µs

SVMLE = 0→1, SVMLFP = 0

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Table 5-15. Timer_A – Timers TA0, TA1, and TA2

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

Internal: SMCLK, ACLK

f_TA

Timer_A input clock frequency

External: TACLK

Duty cycle = 50% ±10%

1.8 V, 3 V

20

MHz

ns

All capture inputs, Minimum pulse duration

required for capture

t_TA,cap

Timer_A capture timing

1.8 V, 3 V

20

Table 5-16. Timer_B – Timer TB0

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

Internal: SMCLK, ACLK

f_TB

Timer_B input clock frequency

External: TBCLK

Duty cycle = 50% ±10%

1.8 V, 3 V

20

MHz

ns

All capture inputs, Minimum pulse duration

required for capture

t_TB,cap

Timer_B capture timing

1.8 V, 3 V

20

Table 5-17. Battery Backup

over operating junction temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_J= –40°C

V_CC

MIN

TYP

MAX UNIT

0.43

0.52

VBAT = 1.7 V,

DVCC not connected,

RTC running

T_J= 25°C

T_J= 60°C

0.58

T_J= 105°C

T_J= –40°C

T_J= 25°C

0.66

0.50

VBAT = 2.2 V,

DVCC not connected,

RTC running

0.59

Current into VBAT terminal if no

primary battery is connected

I_VBAT

µA

T_J= 60°C

0.64

T_J= 105°C

T_J= –40°C

T_J= 25°C

0.72

0.68

VBAT = 3 V,

DVCC not connected,

RTC running

0.75

T_J= 60°C

0.79

T_J= 105°C

General

0.87

V_{SVSH_IT-}

SVSHRL = 0

SVSHRL = 1

SVSHRL = 2

SVSHRL = 3

1.59

1.79

1.98

2.10

1.69

V_SWITCH

Switch-over level (V_CCto VBAT) C_VCC= 4.7 µF

1.91

2.11

2.23

V

On-resistance of switch between

V_BAT= 1.8 V

R_{ON_VBAT}

0 V

0.35

1

kΩ

VBAT and VBAK

1.8 V

3 V

0.6

1.0

1.2

±5%

VBAT to ADC input channel 12:

V_BATdivided, V_BAT3≈ V_BAT/3

V_BAT3

V

3.6 V

t_Sample,

VBAT3

VBAT to ADC: Sampling time

required if VBAT3 selected

ADC12ON = 1,

Error of conversion result ≤ 2 LSB

1000

2.65

ns

V

V_CHVx

Charger end voltage

CHVx = 2

CHCx = 1

CHCx = 2

CHCx = 3

2.7

2.9

5.2

R_CHARGE

Charge limiting resistor

10.2

20

kΩ

Specifications

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Table 5-18. USCI (UART Mode)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK

f_USCI

USCI input clock frequency

External: UCLK

f_SYSTEMMHz

Duty cycle = 50% ±10%

BITCLK clock frequency

(equals baud rate in MBaud)

f_BITCLK

t_τ

1

MHz

ns

2.2 V

3 V

50

600

UART receive deglitch time⁽¹⁾

(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To make sure that pulses are

correctly recognized, their duration should exceed the maximum specification of the deglitch time.

Table 5-19. USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)⁽¹⁾

(see Figure 5-11 and )

PARAMETER

TEST CONDITIONS

SMCLK or ACLK,

Duty cycle = 50% ±10%

V_CC

MIN

TYP

MAX UNIT

f_USCI

USCI input clock frequency

f_SYSTEMMHz

1.8 V

3 V

55

38

30

25

0

PMMCOREV = 0

t_SU,MI

SOMI input data setup time

SOMI input data hold time

SIMO output data valid time⁽²⁾

SIMO output data hold time⁽³⁾

ns

2.4 V

3 V

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

1.8 V

3 V

0

t_HD,MI

ns

2.4 V

3 V

0

1.8 V

3 V

20

UCLK edge to SIMO valid,

C_L= 20 pF, PMMCOREV = 0

18

ns

16

t_VALID,MO

2.4 V

3 V

UCLK edge to SIMO valid,

C_L= 20 pF, PMMCOREV = 3

15

1.8 V

3 V

–10

–8

C_L= 20 pF, PMMCOREV = 0

C_L= 20 pF, PMMCOREV = 3

t_HD,MO

ns

2.4 V

3 V

–10

–8

(1) f_UCxCLK= 1/2t_LO/HIwith t_LO/HI≥ max(t_{VALID,MO(USCI)}+ t_SU,SI(Slave), t_SU,MI(USCI)+ t_{VALID,SO(Slave)}).

For the slave parameters t_SU,SI(Slave)and t_{VALID,SO(Slave)}refer to the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams

in Figure 5-11 and Figure 5-12.

(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data

on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-

11 and Figure 5-12.

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1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_LO/HI

t_SU,MI

t_HD,MI

SOMI

SIMO

t_HD,MO

t_VALID,MO

Figure 5-11. SPI Master Mode, CKPH = 0

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_LO/HI

t_HD,MI

t_SU,MI

SOMI

SIMO

t_HD,MO

t_VALID,MO

Figure 5-12. SPI Master Mode, CKPH = 1

Specifications

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Table 5-20. USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)⁽¹⁾

(see Figure 5-13 and Figure 5-14)

PARAMETER

TEST CONDITIONS

PMMCOREV = 0

V_CC

1.8 V

3 V

MIN

11

8

TYP

MAX UNIT

t_STE,LEAD

t_STE,LAG

t_STE,ACC

t_STE,DIS

t_SU,SI

STE lead time, STE low to clock

ns

2.4 V

3 V

7

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

6

1.8 V

3 V

1

STE lag time, last clock to STE high

ns

2.4 V

3 V

1

1.8 V

3 V

66

50

ns

36

STE access time, STE low to SOMI data

out

2.4 V

3 V

30

1.8 V

3 V

30

ns

30

STE disable time, STE high to SOMI high

impedance

2.4 V

3 V

30

1.8 V

3 V

5

2

5

SIMO input data setup time

SIMO input data hold time

SOMI output data valid time⁽²⁾

SOMI output data hold time⁽³⁾

ns

2.4 V

3 V

1.8 V

3 V

t_HD,SI

ns

2.4 V

3 V

1.8 V

3 V

76

UCLK edge to SOMI valid,

C_L= 20 pF, PMMCOREV = 0

60

ns

44

t_VALID,SO

2.4 V

3 V

UCLK edge to SOMI valid,

C_L= 20 pF, PMMCOREV = 3

40

1.8 V

3 V

12

C_L= 20 pF, PMMCOREV = 0

C_L= 20 pF, PMMCOREV = 3

t_HD,SO

ns

2.4 V

3 V

(1) f_UCxCLK= 1/2t_LO/HIwith t_LO/HI≥ max(t_{VALID,MO(Master)}+ t_SU,SI(USCI), t_{SU,MI(Master)}+ t_{VALID,SO(USCI)}).

For the master parameters t_{SU,MI(Master)}and t_{VALID,MO(Master)}, see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams

in Figure 5-13 and Figure 5-14.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13

and Figure 5-14.

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t_STE,LEAD

t_STE,LAG

STE

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_SU,SI

t_LO/HI

t_HD,SI

SIMO

SOMI

t_HD,SO

t_VALID,SO

t_STE,ACC

t_STE,DIS

Figure 5-13. SPI Slave Mode, CKPH = 0

t_STE,LEAD

t_STE,LAG

STE

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_LO/HI

t_HD,SI

t_SU,SI

SIMO

SOMI

t_HD,MO

t_VALID,SO

t_STE,ACC

t_STE,DIS

Figure 5-14. SPI Slave Mode, CKPH = 1

Specifications

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Table 5-21. USCI (I²C Mode)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted) (see Figure 5-15)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK

External: UCLK

f_USCI

USCI input clock frequency

f_SYSTEMMHz

Duty cycle = 50% ±10%

f_SCL

SCL clock frequency

2.2 V, 3 V

0

4.0

0.6

4.7

0.6

0

400 kHz

µs

f

_SCL≤ 100 kHz

f_SCL> 100 kHz

_SCL≤ 100 kHz

f_SCL> 100 kHz

t_HD,STA

Hold time (repeated) START

f

t_SU,STA

Setup time for a repeated START

2.2 V, 3 V

µs

t_HD,DAT

t_SU,DAT

Data hold time

Data setup time

2.2 V, 3 V

ns

250

4.0

0.6

50

f_SCL≤ 100 kHz

t_SU,STO

Setup time for STOP

2.2 V, 3 V

µs

f_SCL> 100 kHz

2.2 V

3 V

600

ns

Pulse duration of spikes suppressed by

input filter

t_SP

50

600

t_HD,STA

t_SU,STA

t_HD,STA

t_BUF

SDA

SCL

t_LOW

t_HIGH

t_SP

t_SU,DAT

t_SU,STO

t_HD,DAT

Figure 5-15. I²C Mode Timing

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Table 5-22. LCD_B Operating Characteristics

over operating junction temperature range (unless otherwise noted)

PARAMETER

CONDITIONS

MIN

TYP

MAX UNIT

Supply voltage range, charge

pump enabled, V_LCD≤ 3.6 V

LCDCPEN = 1, 0000 < VLCDx ≤ 1111

(charge pump enabled, V_LCD≤ 3.6 V)

V_{CC,LCD_B,CP en,3.6}

V_{CC,LCD_B,CP en,3.3}

V_{CC,LCD_B,int. bias}

V_{CC,LCD_B,ext. bias}

2.2

3.6

V

Supply voltage range, charge

pump enabled, V_LCD≤ 3.3 V

LCDCPEN = 1, 0000 < VLCDx ≤ 1100

(charge pump enabled, V_LCD≤ 3.3 V)

2.0

2.4

Supply voltage range, internal

biasing, charge pump disabled

LCDCPEN = 0, VLCDEXT = 0

Supply voltage range, external

biasing, charge pump disabled

Supply voltage range, external

LCD voltage, internal or

external biasing, charge pump

disabled

V_{CC,LCD_B,VLCDEXT}

LCDCPEN = 0, VLCDEXT = 1

2.0

2.4

3.6

V

External LCD voltage at

LCDCAP/R33, internal or

external biasing, charge pump

disabled

V_LCDCAP/R33

Capacitor on LCDCAP when

charge pump enabled

LCDCPEN = 1, VLCDx > 0000 (charge

pump enabled)

C_LCDCAP

f_Frame

4.7

32

10

µF

Hz

f_LCD= 2 × mux × f_FRAMEwith mux = 1

(static), 2, 3, 4

LCD frame frequency range

0

100

f_ACLK,in

C_Panel

ACLK input frequency range

Panel capacitance

30

40

kHz

pF

100-Hz frame frequency

10000

V_CC

0.2

+

V_R33

Analog input voltage at R33

LCDCPEN = 0, VLCDEXT = 1

2.4

V

V_R03+ 2/3

LCDREXT = 1, LCDEXTBIAS = 1,

LCD2B = 0

V_R23,1/3bias

Analog input voltage at R23

V_R13

× (V_R33

–

V_R33

V

V_R03

)

V_R03+ 1/3

× (V_R33

V_R03

Analog input voltage at R13

with 1/3 biasing

LCDREXT = 1, LCDEXTBIAS = 1,

LCD2B = 0

V_R13,1/3bias

V_R03

–

)

V_R23

V

V_R03+ 1/2

× (V_R33

V_R03

Analog input voltage at R13

with 1/2 biasing

LCDREXT = 1, LCDEXTBIAS = 1,

LCD2B = 1

V_R13,1/2bias

V_R03

–

V_R33

)

V_R03

Analog input voltage at R03

R0EXT = 1

V_SS

2.4

V

Voltage difference between

V_LCDand R03

V_CC

0.2

+

V_LCD-V_R03

LCDCPEN = 0, R0EXT = 1

External LCD reference

voltage applied at

LCDREF/R13

V_LCDREF/R13

VLCDREFx = 01

0.8

1.2

1.5

V

Specifications

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MAX UNIT

Table 5-23. LCD_B Electrical Characteristics

over operating junction temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VLCDx = 0000, VLCDEXT = 0

LCDCPEN = 1, VLCDx = 0001

LCDCPEN = 1, VLCDx = 0010

LCDCPEN = 1, VLCDx = 0011

LCDCPEN = 1, VLCDx = 0100

LCDCPEN = 1, VLCDx = 0101

LCDCPEN = 1, VLCDx = 0110

LCDCPEN = 1, VLCDx = 0111

LCDCPEN = 1, VLCDx = 1000

LCDCPEN = 1, VLCDx = 1001

LCDCPEN = 1, VLCDx = 1010

LCDCPEN = 1, VLCDx = 1011

LCDCPEN = 1, VLCDx = 1100

LCDCPEN = 1, VLCDx = 1101

LCDCPEN = 1, VLCDx = 1110

LCDCPEN = 1, VLCDx = 1111

V_CC

MIN

TYP

V_CC

2.4 V to 3.6 V

2 V to 3.6 V

2.2 V to 3.6 V

2.59

2.66

2.72

2.79

2.85

2.92

2.98

3.05

3.10

3.17

3.24

3.30

3.36

3.42

3.48

V_LCD

LCD voltage

V

3.6

µA

Peak supply currents due to

charge pump activities

I_CC,Peak,CP

t_LCD,CP,on

I_CP,Load

LCDCPEN = 1, VLCDx = 1111

2.2 V

400

100

Time to charge C_LCDwhen

discharged

C_LCD= 4.7 µF, LCDCPEN = 0→1,

VLCDx = 1111

500

ms

µA

kΩ

Maximum charge pump load

current

LCDCPEN = 1, VLCDx = 1111

50

LCD driver output impedance,

segment lines

LCDCPEN = 1, VLCDx = 1000,

I_LOAD= ±10 µA

R_LCD,Seg

R_LCD,COM

10

LCD driver output impedance,

common lines

LCDCPEN = 1, VLCDx = 1000,

I_LOAD= ±10 µA

Table 5-24. 12-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

2.2

0

TYP

MAX UNIT

AVCC and DVCC are connected together,

AVSS and DVSS are connected together,

V(AVSS) = V(DVSS) = 0 V

AV_CC

Analog supply voltage

3.6

V

V_(Ax)

Analog input voltage range⁽²⁾All ADC12 analog input pins Ax

AV_CC

200

V

2.2 V

3 V

150

Operating supply current into

f_ADC12CLK= 5.0 MHz⁽⁴⁾

AVCC terminal⁽³⁾

I_{ADC12_A}

µA

250

Only one terminal Ax can be selected at one

time

C_I

R_I

Input capacitance

2.2 V

20

25

pF

Input MUX ON resistance

0 V ≤ VIN ≤ V(AVCC)

10

200

1900

Ω

(1) The leakage current is specified by the digital I/O input leakage.

(2) The analog input voltage range must be within the selected reference voltage range V_R+to V_R–for valid conversion results. If the

reference voltage is supplied by an external source or if the internal voltage is used and REFOUT = 1, then decoupling capacitors are

required. See Table 5-30 and Table 5-31.

(3) The internal reference supply current is not included in current consumption parameter I_ADC12

.

(4) ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0

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Table 5-25. 12-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

For specified performance of ADC12 linearity

parameters using an external reference voltage or

AV_CCas reference⁽¹⁾

0.45

4.8

5.0

f_ADC12CLK

ADC conversion clock

For specified performance of ADC12 linearity

parameters using the internal reference⁽²⁾

2.2 V, 3 V

MHz

4.0

0.45

4.2

2.4

4.8

For specified performance of ADC12 linearity

parameters using the internal reference⁽³⁾

2.7

Internal ADC12

oscillator⁽⁴⁾

f_ADC12OSC

t_CONVERT

t_Sample

ADC12DIV = 0, f_ADC12CLK= f_ADC12OSC

2.2 V, 3 V

5.4 MHz

REFON = 0, Internal oscillator,

ADC12OSC used for ADC conversion clock

2.4

3.1

µs

Conversion time

External f_ADC12CLKfrom ACLK, MCLK or SMCLK,

ADC12SSEL ≠ 0

See

(5)

R_S= 400 Ω, R_I= 200 Ω, C_I= 20 pF,

Sampling time

2.2 V, 3 V

1000

ns

(6)

τ = [R_S+ R_I] × C_I

(1) REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AV_CCas reference voltage: SREF2 = 0, SREF1 = 0,

SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the

specified performance of the ADC12 linearity is ensured with f_ADC12CLKmaximum of 5.0 MHz.

(2) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1

(3) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when

using the ADC12OSC divided by 2.

(4) The ADC12OSC is sourced directly from MODOSC inside the UCS.

(5) 13 × ADC12DIV × 1/f_ADC12CLK

(6) Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB:

t_Sample= ln(2ⁿ⁺¹) x (R_S+ R_I) × C_I+ 800 ns, where n = ADC resolution = 12, R_S= external source resistance

Table 5-26. 12-Bit ADC, Linearity Parameters Using an External Reference Voltage

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

Integral linearity error⁽¹⁾

Differential linearity error⁽¹⁾

Offset error⁽³⁾

TEST CONDITIONS

1.4 V ≤ dVREF ≤ 1.6 V⁽²⁾

V_CC

MIN

TYP

MAX UNIT

±2

LSB

±1.7

E_I

2.2 V, 3 V

(2)

1.6 V < dVREF

(2)

E_D

E_O

E_G

E_T

See

2.2 V, 3 V

±1 LSB

dVREF ≤ 2.2 V⁽²⁾

dVREF > 2.2 V⁽²⁾

±3

±1.5

±1

±5.6

LSB

±3.5

Gain error⁽³⁾

See

±2.5 LSB

(2)

dVREF ≤ 2.2 V⁽²⁾

dVREF > 2.2 V⁽²⁾

±3.5

±2

±7.1

LSB

±5

Total unadjusted error

(1) Parameters are derived using the histogram method.

(2) The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = V_R+– V_R–. V_R+< AVCC. V_R–> AVSS.

Unless otherwise mentioned dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω and two decoupling capacitors, 10

µF and 100 nF, should be connected to VREF to decouple the dynamic current. See also the MSP430F5xx and MSP430F6xx Family

User's Guide (SLAU208).

(3) Parameters are derived using a best fit curve.

Specifications

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Table 5-27. 12-Bit ADC, Linearity Parameters Using AV_CCas Reference Voltage

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

Integral linearity error⁽¹⁾

Differential linearity error⁽¹⁾

Offset error⁽³⁾

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

±2.0 LSB

±1 LSB

±2 LSB

±4 LSB

±5 LSB

(2)

E_I

See

2.2 V, 3 V

E_D

E_O

E_G

E_T

±1

±2

Gain error⁽³⁾

Total unadjusted error

(1) Parameters are derived using the histogram method.

(2) AV_CCas reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 0.

(3) Parameters are derived using a best fit curve.

Table 5-28. 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS⁽¹⁾

V_CC

MIN

TYP

MAX UNIT

ADC12SR = 0, REFOUT = 1

f

_ADC12CLK≤ 4.0 MHz

±2.0

LSB

±2.5

Integral

E_I

2.2 V, 3 V

linearity error⁽²⁾

ADC12SR = 0, REFOUT = 0

ADC12SR = 0, REFOUT = 1

ADC12SR = 0, REFOUT = 0

ADC12SR = 0, REFOUT = 1

ADC12SR = 0, REFOUT = 0

ADC12SR = 0, REFOUT = 1

ADC12SR = 0, REFOUT = 0

ADC12SR = 0, REFOUT = 1

ADC12SR = 0, REFOUT = 0

_ADC12CLK≤ 2.7 MHz

_ADC12CLK≤ 4.0 MHz

_ADC12CLK≤ 2.7 MHz

_ADC12CLK≤ 4.0 MHz

_ADC12CLK≤ 2.7 MHz

_ADC12CLK≤ 4.0 MHz

_ADC12CLK≤ 2.7 MHz

_ADC12CLK≤ 4.0 MHz

_ADC12CLK≤ 2.7 MHz

–1

+1.5

Differential

E_D

2.2 V, 3 V

±1 LSB

+2.5

linearity error⁽²⁾

±2

±1

±4

E_O

E_G

E_T

Offset error⁽³⁾

Gain error⁽³⁾

2.2 V, 3 V

LSB

±4

±2.5 LSB

±1%⁽⁴⁾VREF

±5 LSB

±2

Total unadjusted

error

±1%⁽⁴⁾VREF

(1) The external reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 1. dVREF = V_R+– V_R–

(2) Parameters are derived using the histogram method.

.

(3) Parameters are derived using a best fit curve.

(4) The gain error and the total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In

this mode, the reference voltage used by the ADC12_A is not available on a pin.

(1)

Table 5-29. 12-Bit ADC, Temperature Sensor and Built-In V_MID

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

2.2 V

3 V

MIN

TYP

680

MAX UNIT

V_SENSOR

See Figure 5-16⁽²⁾

ADC12ON = 1, INCH = 0Ah, T_J= 0°C

mV

2.2 V

3 V

30

t_{SENSOR(sample}Sample time required if channel 10

)

ADC12ON = 1, INCH = 0Ah,

Error of conversion result ≤ 1 LSB

µs

is selected⁽³⁾

2.2 V

3 V

1.06

1.46

1.1

1.5

1.14

V

ADC12ON = 1, INCH = 0Bh,

V_MID

AV_CCdivider at channel 11

V_MID≈ 0.5 × V_AVCC

1.54

Sample time required if channel 11

is selected⁽⁴⁾

ADC12ON = 1, INCH = 0Bh,

Error of conversion result ≤ 1 LSB

t_VMID(sample)

2.2 V, 3 V

1000

ns

(1) The temperature sensor is provided by the REF module. See the REF module parametric, I_REF+, regarding the current consumption of

the temperature sensor.

(2) The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in

temperature sensor. The TLV structure contains calibration values for 30°C ±3°C and 105°C ±3°C for each of the available reference

voltage levels. The sensor voltage can be computed as V_SENSE= TC_SENSOR× (Temperature,°C) + V_SENSOR, where TC_SENSORand

V_SENSORcan be computed from the calibration values for higher accuracy. See also the MSP430F5xx and MSP430F6xx Family User's

Guide (SLAU208).

(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t_SENSOR(on)

.

(4) The on-time t_VMID(on)is included in the sampling time t_VMID(sample); no additional on time is needed.

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1000

950

900

850

800

750

700

650

600

550

500

-40 -30 -20 -10

0 10 20 30 40 50 60 70 80

Ambient Temperature (°C)

Figure 5-16. Typical Temperature Sensor Voltage

Table 5-30. REF, External Reference

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

1.4 AV_CC

1.2

1.4 AV_CC

MAX UNIT

Positive external reference

voltage input

(2)

V_eREF+

V_eREF+> V_REF–/V_eREF–

V

Negative external reference

voltage input

(3)

(4)

V_REF–/V_eREF–

V_eREF+> V_REF–/V_eREF–

0

(V_eREF+

–

Differential external reference

voltage input

V_REF–/V_eREF–

)

1.4 V ≤ V_eREF+≤ V_AVCC, V_eREF–= 0 V,

f_ADC12CLK= 5 MHz, ADC12SHTx = 1h,

Conversion rate 200 ksps

2.2 V, 3 V

–32

32

I_VeREF+

I_{VREF–/VeREF–}

,

Static input current

µA

µF

1.4 V ≤ V_eREF+≤ V_AVCC, V_eREF–= 0 V,

f_ADC12CLK= 5 MHZ, ADC12SHTx = 8h,

Conversion rate 20 ksps

–1.2

10

+1.2

Capacitance at VREF+ or

VREF- terminal⁽⁵⁾

C_VREF+/-

(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, C_i, is also

the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the

recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.

(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced

accuracy requirements.

(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced

accuracy requirements.

(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with

reduced accuracy requirements.

(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external

reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).

Specifications

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Table 5-31. REF, Built-In Reference

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

REFVSEL = {2} for 2.5 V,

REFON = REFOUT = 1, I_VREF+= 0 A

3 V

2.5

±1%

Positive built-in

reference voltage

output

REFVSEL = {1} for 2 V,

REFON = REFOUT = 1, I_VREF+= 0 A

V_REF+

3 V

2.0

1.5

±1%

V

REFVSEL = {0} for 1.5 V,

REFON = REFOUT = 1, I_VREF+= 0 A

2.2 V, 3 V

AVCC minimum

voltage, Positive

built-in reference

active

REFVSEL = {0} for 1.5 V

REFVSEL = {1} for 2 V

REFVSEL = {2} for 2.5 V

2.2

2.3

2.8

AV_CC(min)

ADC12SR = 1⁽⁴⁾

REFON = 1, REFOUT = 0, REFBURST = 0

,

70

0.45

210

100

0.75

310

1.7

µA

mA

µA

ADC12SR = 1⁽⁴⁾

REFON = 1, REFOUT = 1, REFBURST = 0

,

Operating supply

current into AVCC

terminal

I_REF+

3 V

ADC12SR = 0⁽⁴⁾

REFON = 1, REFOUT = 0, REFBURST = 0

,

(2) (3)

ADC12SR = 0⁽⁴⁾

,

0.95

mA

REFON = 1, REFOUT = 1, REFBURST = 0

REFVSEL = {0, 1, 2},

I_VREF+= +10 µA or –1000 µA,

AV_CC= AV_CC(min)for each reference level,

REFVSEL = {0, 1, 2}, REFON = REFOUT = 1

Load-current

regulation, VREF+

terminal⁽⁵⁾

I_L(VREF+)

1500

2500 µV/mA

Capacitance at

VREF+ terminal

REFON = REFOUT = 1⁽⁶⁾

,

0 mA ≤ I_VREF+≤ I_VREF+(max)

C_VREF+

2.2 V, 3 V

20

100

pF

Temperature

I_VREF+is a constant in the range of

0 mA ≤ I_VREF+≤ –1 mA

ppm/

°C

TC_REF+

coefficient of built-in

REFOUT = 0 2.2 V, 3 V

20

120

1

reference⁽⁷⁾

Temperature

I_VREF+is a constant in the range of

0 mA ≤ I_VREF+≤ –1 mA

ppm/

°C

TC_REF+

coefficient of built-in

REFOUT = 1 2.2 V, 3 V

50

reference⁽⁷⁾

AV_CC= AV_CC(min)to AV_CC(max), T_J= 25°C,

REFVSEL = {0, 1, 2}, REFON = 1,

REFOUT = 0 or 1

Power supply

rejection ratio (DC)

PSRR_DC

PSRR_AC

300 µV/V

mV/V

AV_CC= AV_CC(min)to AV_CC(max), T_J= 25°C,

REFVSEL = {0, 1, 2}, REFON = 1,

REFOUT = 0 or 1

Power supply

rejection ratio (AC)

AV_CC= AV_CC(min)to AV_CC(max)

,

REFVSEL = {0, 1, 2}, REFOUT = 0,

REFON = 0 → 1

75

Settling time of

t_SETTLE

µs

reference voltage⁽⁸⁾

AV_CC= AV_CC(min)to AV_CC(max)

,

C_VREF= C_VREF(max), REFVSEL = {0, 1, 2},

REFOUT = 1, REFON = 0 → 1

(1) The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers, one

smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal and is used

as the reference for the conversion and uses the larger buffer. When REFOUT = 0, the reference is only used as the reference for the

conversion and uses the smaller buffer.

(2) The internal reference current is supplied from the AVCC terminal. Consumption is independent of the ADC12ON control bit, unless a

conversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current

contribution of the larger buffer without external load.

(3) The temperature sensor is provided by the REF module. Its current is supplied from the AVCC terminal and is equivalent to I_REF+with

REFON = 1 and REFOUT = 0.

(4) For devices without the ADC12, the parametric with ADC12SR = 0 are applicable.

(5) Contribution only due to the reference and buffer including package. This does not include resistance due to PCB trace or other causes.

(6) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external

reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).

(7) Calculated using the box method: (MAX(–40°C to 105°C) – MIN(–40°C to 105°C)) / MIN(–40°C to 105°C)/(105°C – (–40°C)).

(8) The condition is that the error in a conversion started after t_REFONis less than ±0.5 LSB. The settling time depends on the external

capacitive load when REFOUT = 1.

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Table 5-32. 12-Bit DAC, Supply Specifications

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

AV_CC

Analog supply voltage

AV_CC= DV_CC, AV_SS= DV_SS= 0 V

2.20

3.60

V

DAC12AMPx = 2, DAC12IR = 0, DAC12IOG = 1

DAC12_xDAT = 0800h

Ve_REF+= V_REF+= 1.5 V

3 V

65

110

DAC12AMPx = 2, DAC12IR = 1,

DAC12_xDAT = 0800h,

Ve_REF+= V_REF+= AV_CC

110

300

Supply current, single

DAC channel⁽¹⁾⁽²⁾

I_DD

µA

DAC12AMPx = 5, DAC12IR = 1,

DAC12_xDAT = 0800h,

Ve_REF+= V_REF+= AV_CC

2.2 V, 3 V

250

750

DAC12AMPx = 7, DAC12IR = 1,

DAC12_xDAT = 0800h,

1000

Ve_REF+= V_REF+= AV_CC

DAC12_xDAT = 800h, Ve_REF+= 1.5 V,

ΔAV_CC= 100 mV

2.2 V

3 V

70

Power supply rejection

ratio⁽³⁾⁽⁴⁾

PSRR

dB

DAC12_xDAT = 800h, Ve_REF+= 1.5 V or 2.5 V,

ΔAV_CC= 100 mV

(1) No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.

(2) Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Table 5-35.

(3) PSRR = 20 log (ΔAV_CC/ ΔV_{DAC12_xOUT}

)

(4) The internal reference is not used.

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Table 5-33. 12-Bit DAC, Linearity Specifications

See Figure 5-17, over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN TYP MAX UNIT

Resolution

12-bit monotonic

12

bits

Ve_REF+= 1.5 V, DAC12AMPx = 7, DAC12IR = 1

Ve_REF+= 2.5 V, DAC12AMPx = 7, DAC12IR = 1

Ve_REF+= 1.5 V, DAC12AMPx = 7, DAC12IR = 1

Ve_REF+= 2.5 V, DAC12AMPx = 7, DAC12IR = 1

2.2 V

3 V

±2

±4

±1

INL

Integral nonlinearity⁽¹⁾

LSB

2.2 V

3 V

±0.4

DNL

Differential nonlinearity⁽¹⁾

LSB

Ve_REF+= 1.5 V,

DAC12AMPx = 7,

DAC12IR = 1

2.2 V

3 V

±21

Without calibration^{(1) (2)}

Ve_REF+= 2.5 V,

DAC12AMPx = 7,

DAC12IR = 1

E_O

Offset voltage

mV

Ve_REF+= 1.5 V,

DAC12AMPx = 7,

DAC12IR = 1

2.2 V

±1.5

With calibration^{(1) (2)}

Ve_REF+= 2.5 V,

DAC12AMPx = 7,

DAC12IR = 1

3 V

Offset error temperature

coefficient⁽¹⁾

d_E(O)/d_T

E_G

With calibration

2.2 V, 3 V

±10

10

µV/°C

%FSR

Ve_REF+= 1.5 V

Ve_REF+= 2.5 V

2.2 V

3 V

±2.5

Gain error

Gain temperature

coefficient⁽¹⁾

ppm of

FSR/°C

d_E(G)/d_T

2.2 V, 3 V

DAC12AMPx = 2

165

66

Time for offset

calibration⁽³⁾

t_{Offset_Cal}

DAC12AMPx = 3, 5

DAC12AMPx = 4, 6, 7

2.2 V, 3 V

ms

16.5

(1) Parameters calculated from the best-fit curve from 0x0F to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and “b” of

the first-order equation: y = a + bx. V_{DAC12_xOUT}= E_O+ (1 + E_G) × (Ve_REF+/4095) × DAC12_xDAT, DAC12IR = 1.

(2) The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON.

(3) The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx =

{0, 1}. TI recommends configuring the DAC12 module before initiating calibration. Port activity during calibration may affect accuracy

and is not recommended.

DAC V_OUT

DAC Output

V_R+

R_Load= ¥

Ideal transfer

function

AV_CC

2

Offset Error

Positive

Gain Error

C_Load= 100 pF

Negative

DAC Code

Figure 5-17. Linearity Test Load Conditions and Gain/Offset Definition

44

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Table 5-34. 12-Bit DAC, Output Specifications

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

No load, Ve_REF+= AV_CC, DAC12_xDAT = 0h,

DAC12IR = 1, DAC12AMPx = 7

0

0.005

No load, Ve_REF+= AV_CC

DAC12_xDAT = 0FFFh, DAC12IR = 1,

DAC12AMPx = 7

,

AV_CC

– 0.05

AV_CC

Output voltage

V_O

range⁽¹⁾(see

Figure 5-18)

2.2 V, 3 V

V

R_Load= 3 kΩ, Ve_REF+= AV_CC

DAC12_xDAT = 0h, DAC12IR = 1,

DAC12AMPx = 7

,

0

0.1

R_Load= 3 kΩ, Ve_REF+= AV_CC

DAC12_xDAT = 0FFFh, DAC12IR = 1,

DAC12AMPx = 7

,

AV_CC

– 0.13

AV_CC

Maximum DAC12

load capacitance

C_L(DAC12)

2.2 V, 3 V

100

pF

DAC12AMPx = 2, DAC12_xDAT = 0FFFh,

V_O/P(DAC12)> AV_CC– 0.3

–1

Maximum DAC12

load current

I_L(DAC12)

mA

DAC12AMPx = 2, DAC12_xDAT = 0h,

V_O/P(DAC12)< 0.3 V

1

250

6

R_Load= 3 kΩ, VO/P(DAC12) < 0.3 V,

DAC12AMPx = 2, DAC12_xDAT = 0h

150

Output resistance

(see Figure 5-18)

R_Load= 3 kΩ, V_O/P(DAC12)> AV_CC– 0.3 V,

DAC12_xDAT = 0FFFh

R_O/P(DAC12)

2.2 V, 3 V

Ω

R_Load= 3 kΩ,

0.3 V ≤ V_O/P(DAC12)≤ AV_CC– 0.3 V

(1) Data is valid after the offset calibration of the output amplifier.

R_{O/P(DAC12_x)}

Max

R_Load

I_Load

AV_CC

DAC12

2

C_Load= 100 pF

O/P(DAC12_x)

Min

0.3

AV_CC– 0.3 V

V_OUT

AV_CC

Figure 5-18. DAC12_x Output Resistance Tests

Specifications

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Table 5-35. 12-Bit DAC, Reference Input Specifications

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

DAC12IR = 0^{(1) (2)}

V_CC

MIN

TYP

MAX UNIT

AV_CC

AV_CC/3

+ 0.2

Ve_REF+

Reference input voltage range

2.2 V, 3 V

V

AV_CC

DAC12IR = 1^{(3) (4)}

AV_CC

+ 0.2

DAC12_0 IR = DAC12_1 IR = 0

DAC12_0 IR = 1, DAC12_1 IR = 0

DAC12_0 IR = 0, DAC12_1 IR = 1

20

MΩ

52

Ri_(VREF+)

Ri_(VeREF+)

,

Reference input resistance

2.2 V, 3 V

kΩ

DAC12_0 IR = DAC12_1 IR = 1,

26

DAC12_0 SREFx = DAC12_1 SREFx⁽⁵⁾

(1) For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).

(2) The maximum voltage applied at reference input voltage terminal VeREF+ = [AV_CC– V_E(O)] / [3 × (1 + E_G)].

(3) For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AV_CC).

(4) The maximum voltage applied at reference input voltage terminal VeREF+ = [AV_CC– V_E(O)] / (1 + E_G).

(5) When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel

reducing the reference input resistance.

Table 5-36. 12-Bit DAC, Dynamic Specifications

V_REF= V_CC, DAC12IR = 1 (see Figure 5-19 and Figure 5-20), over recommended ranges of supply voltage and operating

junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

DAC12AMPx = 0 → {2, 3, 4}

V_CC

MIN

TYP MAX UNIT

60 120

DAC12_xDAT = 800h,

Error_V(O)< ±0.5 LSB⁽¹⁾

(see Figure 5-19)

t_ON

DAC12 on time

DAC12AMPx = 0 → {5, 6}

DAC12AMPx = 0 → 7

DAC12AMPx = 2

2.2 V, 3 V

15

6

30

12

µs

100 200

DAC12_xDAT =

t_S(FS)

t_S(C-C)

SR

Settling time, full scale

DAC12AMPx = 3, 5

DAC12AMPx = 4, 6, 7

DAC12AMPx = 2

2.2 V, 3 V

40

15

80

30

80h → F7Fh → 80h

5

DAC12_xDAT =

Settling time, code to

code

3F8h → 408h → 3F8h,

BF8h → C08h → BF8h

DAC12AMPx = 3, 5

DAC12AMPx = 4, 6, 7

DAC12AMPx = 2

2

1

0.05

0.35

1.10

5.20

DAC12_xDAT =

Slew rate

DAC12AMPx = 3, 5

DAC12AMPx = 4, 6, 7

2.2 V, 3 V 0.35

1.50

V/µs

nV-s

80h → F7Fh → 80h⁽²⁾

DAC12_xDAT =

Glitch energy

DAC12AMPx = 7

2.2 V, 3 V

35

800h → 7FFh → 800h

(1) R_Loadand C_Loadconnected to AV_SS(not AV_CC/2) in Figure 5-19.

(2) Slew rate applies to output voltage steps ≥ 200 mV.

Conversion 1

Conversion 2

1/2 LꢀS

Conversion 3

V_OUT

DAC Output

Glitch

Energy

R_Load= 3 kW

I_Load

AV_CC

2

1/2 LꢀS

C_Load= 100 pF

R_O/P(DAC12.x)

t_settleLH

t_settleHL

Figure 5-19. Settling Time and Glitch Energy Testing

46

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Conversion 1

Conversion 2

Conversion 3

V_OUT

90%

10%

t_SRLH

t_SRHL

Figure 5-20. Slew Rate Testing

Table 5-37. 12-Bit DAC, Dynamic Specifications (Continued)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,

DAC12IR = 1, DAC12_xDAT = 800h

T_J= 25°C

40

3-dB bandwidth,

V_DC= 1.5 V,

V_AC= 0.1 V_PP(see

Figure 5-21)

DAC12AMPx = {5, 6}, DAC12SREFx = 2,

DAC12IR = 1, DAC12_xDAT = 800h

T_J= 25°C

BW_–3dB

2.2 V, 3 V

180

550

kHz

DAC12AMPx = 7, DAC12SREFx = 2,

DAC12IR = 1, DAC12_xDAT = 800h

T_J= 25°C

DAC12_0DAT = 800h, No load,

DAC12_1DAT = 80h ↔ F7Fh, R_Load= 3 kΩ,

f_{DAC12_1OUT}= 10 kHz at 50/50 duty cycle,

T_J= 25°C

–80

Channel-to-channel

crosstalk⁽¹⁾(see Figure 5-

22)

2.2 V, 3 V

dB

DAC12_0DAT = 80h ↔ F7Fh, R_Load= 3 kΩ,

DAC12_1DAT = 800h, No load,

f_{DAC12_0OUT}= 10 kHz at 50/50 duty cycle,

T_J= 25°C

(1) R_Load= 3 kΩ, C_Load= 100 pF

R_Load= 3 kW

I_Load

Ve_REF+

AV_CC

2

DAC12_x

DACx

AC

DC

C_Load= 100 pF

Figure 5-21. Test Conditions for 3-dB Bandwidth Specification

R_Load

I_Load

AV_CC

DAC12_xDAT

V_OUT

080h

F7Fh

080h

F7Fh

DAC12_0

DAC12_1

2

DAC0

C_Load= 100 pF

R_Load

V_REF+

V_{DAC12_yOUT}

I_Load

V_{DAC12_xOUT}

AV_CC

2

1/f_Toggle

DAC1

C_Load= 100 pF

Figure 5-22. Crosstalk Test Conditions

Specifications

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Table 5-38. Comparator_B

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER

Supply voltage

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

V_CC

1.8

3.6

40

50

65

30

0.5

V

1.8 V

2.2 V

CBPWRMD = 00

30

40

Comparator operating supply

current into AVCC terminal,

Excludes reference resistor ladder

I_{AVCC_COM}

P

3 V

µA

CBPWRMD = 01

CBPWRMD = 10

2.2 V, 3 V

10

0.1

Quiescent current of local reference CBREFACC = 1,

voltage amplifier into AVCC terminal CBREFLx = 01

I_{AVCC_REF}

V_IC

V_OFFSET

C_IN

22

µA

V

Common mode input range

0

V_CC– 1

±20

CBPWRMD = 00

Input offset voltage

mV

CBPWRMD = 01, 10

±10

Input capacitance

5

3

pF

kΩ

ON, switch closed

Series input resistance

4

R_SIN

OFF, switch opened

50

MΩ

CBPWRMD = 00, CBF = 0

450

600

50

ns

µs

t_PD

Propagation delay, response time

Propagation delay with filter active

CBPWRMD = 01, CBF = 0

CBPWRMD = 10, CBF = 0

CBPWRMD = 00, CBON = 1,

CBF = 1, CBFDLY = 00

0.35

0.6

1.0

1.8

3.4

1.0

1.8

3.4

6.5

CBPWRMD = 00, CBON = 1,

CBF = 1, CBFDLY = 01

t_PD,filter

µs

CBPWRMD = 00, CBON = 1,

CBF = 1, CBFDLY = 10

1.0

CBPWRMD = 00, CBON = 1,

CBF = 1, CBFDLY = 11

1.8

Comparator enable time, settling

time

CBON = 0 to CBON = 1

CBPWRMD = 00, 01, 10

t_{EN_CMP}

t_{EN_REF}

1

0.3

2

1.5

µs

Resistor reference enable time

CBON = 0 to CBON = 1

VIN ×

(n +

0.5)

VIN ×

(n + 1) (n + 1.5)

/ 32 / 32

VIN ×

VIN = reference into resistor

ladder, n = 0 to 31

V_{CB_REF}

Reference voltage for a given tap

V

/ 32

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Table 5-39. Flash Memory

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

TEST

CONDITIONS

PARAMETER

MIN

TYP

MAX UNIT

DV_{CC(PGM/ERASE)}Program and erase supply voltage

1.8

3.6

5

V

I_PGM

Average supply current from DVCC during program

3

6

mA

I_ERASE

Average supply current from DVCC during erase

17

Average supply current from DVCC during mass erase or bank

erase

I_MERASE, I_BANK

t_CPT

6

17

16

mA

(1)

Cumulative program time

See

ms

cycles

years

µs

Program and erase endurance

Data retention duration

10³

100

64

10⁵

t_Retention

t_Word

T_J= 25°C

(2)

Word or byte program time

Block program time for first byte or word

See

85

65

(2)

t_{Block, 0}

See

49

µs

Block program time for each additional byte or word, except for last

byte or word

(2)

t_{Block, 1–(N–1)}

t_{Block, N}

See

37

55

23

49

73

32

µs

(2)

Block program time for last byte or word

See

Erase time for segment, mass erase, and bank erase when

available

(2)

t_{Seg Erase}

See

ms

MCLK frequency in marginal read mode

(FCTL4.MRG0 = 1 or FCTL4.MRG1 = 1)

f_MCLK,MRG

0

1

MHz

(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming

methods: individual word write, individual byte write, and block write modes.

(2) These values are hardwired into the state machine of the flash controller.

5.14.4 Emulation and Debug

Table 5-40. JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

TEST

CONDITIONS

PARAMETER

MIN

TYP

MAX UNIT

f_SBW

Spy-Bi-Wire input frequency

2.2 V, 3 V

0

20 MHz

t_SBW,Low

t_{SBW, En}

t_SBW,Rst

Spy-Bi-Wire low clock pulse duration

Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)⁽¹⁾

2.2 V, 3 V

0.025

15

1

µs

2.2 V, 3 V

Spy-Bi-Wire return to normal operation time

15

0

100

5

2.2 V

3 V

f_TCK

TCK input frequency for 4-wire JTAG⁽²⁾

Internal pulldown resistance on TEST

MHz

0

10

80

R_internal

2.2 V, 3 V

45

60

kΩ

(1) Tools that access the Spy-Bi-Wire interface must wait for the t_SBW,Entime after pulling the TEST/SBWTCK pin high before applying the

first SBWTCK clock edge.

(2) f_TCKmay be restricted to meet the timing requirements of the module selected.

Specifications

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6 Detailed Description

6.1 Overview

The MSP430F6459 is an ultra-low-power microcontroller that consists of several features which include

different sets of peripherals targeted for various applications. The architecture, combined with five low-

power modes, is optimized to achieve extended battery life in portable measurement applications.

The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute

to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from

low-power modes to active mode in 3 μs (typical).

6.2 CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All

operations, other than program-flow instructions, are performed as register operations in conjunction with

seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-

register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and

constant generator, respectively. The remaining registers are general-purpose registers (see Figure 6-1).

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all

instructions.

For further details, see the CPUX Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)

(SLAU391).

Program Counter

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R4

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15

Figure 6-1. CPU Registers

50

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6.3 Instruction Set

The instruction set consists of the original 51 instructions with three formats and seven address modes

and additional instructions for the expanded address range. Each instruction can operate on word and

byte data. Table 6-1 shows examples of the three types of instruction formats; Table 6-2 shows the

address modes.

Table 6-1. Instruction Word Formats

INSTRUCTION WORD FORMAT

Dual operands, source-destination

EXAMPLE

ADD R4,R5

CALL R8

JNE

OPERATION

R4 + R5 → R5

Single operands, destination only

PC → (TOS), R8 → PC

Jump-on-equal bit = 0

Relative jump, unconditional or conditional

Table 6-2. Address Mode Descriptions

ADDRESS MODE

Register

S⁽¹⁾

+

D⁽¹⁾

SYNTAX

MOV Rs,Rd

EXAMPLE

OPERATION

+

MOV R10,R11

R10 → R11

Indexed

+

MOV X(Rn),Y(Rm)

MOV EDE,TONI

MOV &MEM, &TCDAT

MOV @Rn,Y(Rm)

MOV 2(R5),6(R6)

M(2+R5) → M(6+R6)

M(EDE) → M(TONI)

M(MEM) → M(TCDAT)

M(R10) → M(Tab+R6)

Symbolic (PC relative)

Absolute

+

Indirect

+

MOV @R10,Tab(R6)

MOV @R10+,R11

MOV #45,TONI

M(R10) → R11

R10 + 2 → R10

Indirect auto-increment

+

MOV @Rn+,Rm

MOV #X,TONI

Immediate

#45 → M(TONI)

(1) S = source, D = destination

Detailed Description

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6.4 Operating Modes

The MCUs have one active mode and seven software selectable low-power modes of operation. An

interrupt event can wake up the device from any of the low-power modes, service the request, and restore

back to the low-power mode on return from the interrupt program.

Software can configure the following operating modes:

•

Active mode (AM)

All clocks are active

Low-power mode 0 (LPM0)

–

•

–

CPU is disabled

ACLK and SMCLK remain active, MCLK is disabled

FLL loop control remains active

•

Low-power mode 1 (LPM1)

–

CPU is disabled

FLL loop control is disabled

ACLK and SMCLK remain active, MCLK is disabled

Low-power mode 2 (LPM2)

–

CPU is disabled

MCLK, FLL loop control, and DCOCLK are disabled

DC generator of the DCO remains enabled

ACLK remains active

•

Low-power mode 3 (LPM3)

–

CPU is disabled

MCLK, FLL loop control, and DCOCLK are disabled

DC generator of the DCO is disabled

ACLK remains active

Low-power mode 4 (LPM4)

–

CPU is disabled

ACLK is disabled

MCLK, FLL loop control, and DCOCLK are disabled

DC generator of the DCO is disabled

Crystal oscillator is stopped

Complete data retention

•

Low-power mode 3.5 (LPM3.5)

–

Internal regulator disabled

No data retention

RTC enabled and clocked by low-frequency oscillator

Wake-up signal from RST/NMI, RTC_B, P1, P2, P3, and P4

Low-power mode 4.5 (LPM4.5)

–

Internal regulator disabled

No data retention

Wake-up signal from RST/NMI, P1, P2, P3, and P4

52

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6.5 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see

Table 6-3). The vector contains the 16-bit address of the appropriate interrupt-handler instruction

sequence.

Table 6-3. Interrupt Sources, Flags, and Vectors

SYSTEM

INTERRUPT

WORD

ADDRESS

INTERRUPT SOURCE

INTERRUPT FLAG

PRIORITY

System Reset

Power-Up, External Reset

Watchdog Time-out, Key Violation

Flash Memory Key Violation

(2)

WDTIFG, KEYV (SYSRSTIV)⁽¹⁾

Reset

0FFFEh

0FFFCh

0FFFAh

63, highest

System NMI

PMM

Vacant Memory Access

JTAG Mailbox

SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,

SVMLVLRIFG, SVMHVLRIFG, VMAIFG,

JMBNIFG, JMBOUTIFG (SYSSNIV)⁽¹⁾

(Non)maskable

62

61

User NMI

NMI

Oscillator Fault

NMIIFG, OFIFG, ACCVIFG, BUSIFG

(SYSUNIV)^{(1) (2)}

Flash Memory Access Violation

Comp_B

Comparator B interrupt flags (CBIV)^{(1) (3)}

Maskable

0FFF8h

0FFF6h

60

59

(3)

Timer TB0

TB0CCR0 CCIFG0

TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,

TB0IFG (TB0IV)^{(1) (3)}

Timer TB0

Maskable

0FFF4h

58

Watchdog Interval Timer Mode

USCI_A0 Receive or Transmit

USCI_B0 Receive or Transmit

ADC12_A

WDTIFG

Maskable

0FFF2h

0FFF0h

0FFEEh

0FFECh

0FFEAh

57

56

55

54

53

UCA0RXIFG, UCA0TXIFG (UCA0IV)^{(1) (3)}

UCB0RXIFG, UCB0TXIFG (UCB0IV)^{(1) (3)}

ADC12IFG0 to ADC12IFG15 (ADC12IV)^{(1) (3)}

TA0CCR0 CCIFG0⁽³⁾

Timer TA0

TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,

TA0IFG (TA0IV)^{(1) (3)}

Timer TA0

Maskable

0FFE8h

0FFE6h

0FFE4h

0FFE2h

0FFE0h

52

51

50

49

48

(4)

LDO-PWR

LDOOFFIG, LDOONIFG, LDOOVLIFG

DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG,

DMA4IFG, DMA5IFG (DMAIV)^{(1) (3)}

DMA

Timer TA1

TA1CCR0 CCIFG0⁽³⁾

TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,

TA1IFG (TA1IV)^{(1) (3)}

I/O Port P1

USCI_A1 Receive or Transmit

USCI_B1 Receive or Transmit

I/O Port P2

P1IFG.0 to P1IFG.7 (P1IV)⁽¹⁾⁽³⁾

UCA1RXIFG, UCA1TXIFG (UCA1IV)^{(1) (3)}

UCB1RXIFG, UCB1TXIFG (UCB1IV)^{(1) (3)}

P2IFG.0 to P2IFG.7 (P2IV)^{(1) (3)}

Maskable

0FFDEh

0FFDCh

0FFDAh

0FFD8h

0FFD6h

47

46

45

44

43

LCD_B⁽⁵⁾

LCD_B Interrupt Flags (LCDBIV)⁽¹⁾

RTCRDYIFG, RTCTEVIFG, RTCAIFG,

RTC_B

Maskable

0FFD4h

42

RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV)^{(1) (3)}

DAC12_A

Timer TA2

DAC12_0IFG, DAC12_1IFG^{(1) (3)}

TA2CCR0 CCIFG0⁽³⁾

Maskable

0FFD2h

0FFD0h

41

40

TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,

TA2IFG (TA2IV)^{(1) (3)}

Timer TA2

Maskable

0FFCEh

39

I/O Port P3

I/O Port P4

P3IFG.0 to P3IFG.7 (P3IV)^{(1) (3)}

P4IFG.0 to P4IFG.7 (P4IV)^{(1) (3)}

Maskable

0FFCCh

0FFCAh

38

37

(1) Multiple source flags

(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.

(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

(3) Interrupt flags are in the module.

(4) Only on devices with peripheral module LDO-PWR.

(5) Only on devices with peripheral module LCD_B, otherwise reserved.

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PRIORITY

Table 6-3. Interrupt Sources, Flags, and Vectors (continued)

SYSTEM

INTERRUPT

WORD

ADDRESS

INTERRUPT SOURCE

INTERRUPT FLAG

USCI_A2 Receive or Transmit

USCI_B2 Receive or Transmit

UCA2RXIFG, UCA2TXIFG (UCA2IV)^{(1) (3)}

UCB2RXIFG, UCB2TXIFG (UCB2IV)^{(1) (3)}

0FFC8h

0FFC6h

0FFC4h

⋮

36

35

34

Reserved

Reserved⁽⁶⁾

⋮

0FF80h

0, lowest

(6) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain

compatibility with other devices, TI recommends reserving these locations.

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6.6 Memory Organization

Table 6-4 summarizes the memory map.

Table 6-4. Memory Organization⁽¹⁾

DESCRIPTION

512KB

Memory (flash)

Total Size

Main: interrupt vector

00FFFFh–00FF80h

Bank 3

Bank 2

128KB

087FFFh-068000h

128KB

067FFFh-48000h

Main: code memory

Bank 1

128KB

047FFFh-028000h

Bank 0

128KB

027FFFh-008000h

Total Size

Sector 3

Sector 2

Sector 1

Sector 0

1KB

MID support software (ROM)

006FFFh-006C00h

16KB

0FBFFFh-0F8000h

16KB

0F7FFFh-0F4000h

16KB

0F3FFFh-0F0000h

RAM

16KB

0063FFh–002400h

(mirrored at address range

0FFFFFh-0FC000h)

Sector 7

Info A

Info B

Info C

Info D

BSL 3

BSL 2

BSL 1

BSL 0

Size

2KB

RAM

0023FFh-001C00h

128 B

0019FFh–001980h

128 B

00197Fh–001900h

Information memory (flash)

128 B

0018FFh–001880h

128 B

00187Fh–001800h

512 B

0017FFh–001600h

512 B

0015FFh–001400h

Bootloader (BSL) memory (flash)

512 B

0013FFh–001200h

512 B

0011FFh–001000h

4KB

Peripherals

000FFFh–000000h

(1) N/A = Not available

6.7 Bootloader (BSL)

The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to

the device memory by the BSL is protected by an user-defined password. For complete description of the

features of the BSL and its implementation, see MSP430 Programming WIth the Bootloader (BSL)

(SLAU319).

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6.7.1 UART BSL

MSP4306459 comes preprogrammed with the UART BSL. Use of the UART BSL requires external access

to six pins (see Table 6-5).

Table 6-5. UART BSL Pin Requirements and Functions

DEVICE SIGNAL

BSL FUNCTION

Entry sequence signal

Data transmit

RST/NMI/SBWTDIO

TEST/SBWTCK

P1.1

P1.2

VCC

VSS

Data receive

Power supply

Ground supply

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6.8 JTAG Operation

6.8.1 JTAG Standard Interface

The MSP430 family supports the standard JTAG interface which requires four signals for sending and

receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to

enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with

MSP430 development tools and device programmers. Table 6-6 lists the JTAG pin requirements. For

further details on interfacing to development tools and device programmers, see the MSP430 Hardware

Tools User's Guide (SLAU278). For a complete description of the features of the BSL and its

implementation, see the MSP430 Programming With the Bootloader User's Guide (SLAU319).

Table 6-6. JTAG Pin Requirements and Functions

DEVICE SIGNAL

PJ.3/TCK

DIRECTION

FUNCTION

JTAG clock input

JTAG state control

JTAG data input, TCLK input

JTAG data output

Enable JTAG pins

External reset

IN

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

IN

OUT

IN

TEST/SBWTCK

RST/NMI/SBWTDIO

VCC

IN

Power supply

VSS

Ground supply

6.8.2 Spy-Bi-Wire Interface

In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire

interface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers.

Table 6-7 lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing to

development tools and device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278).

For a complete description of the features of the JTAG interface and its implementation, see MSP430

Programming Via the JTAG Interface (SLAU320).

Table 6-7. Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL

TEST/SBWTCK

RST/NMI/SBWTDIO

VCC

DIRECTION

IN

FUNCTION

Spy-Bi-Wire clock input

Spy-Bi-Wire data input and output

Power supply

IN, OUT

VSS

Ground supply

6.9 Flash Memory

The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system

by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory.

Features of the flash memory include:

•

Flash memory has n segments of main memory and four segments of information memory (A to D) of

128 bytes each. Each segment in main memory is 512 bytes in size.

•

Segments 0 to n may be erased in one step, or each segment may be individually erased.

Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are

also called information memory.

•

Segment A can be locked separately.

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For further information, see the Flash Controller Module (Chapter Excerpt From MSP430x5xx Family,

SLAU208) (SLAU392).

6.10 Memory Integrity Detection (MID)

The MID is an add-on to the MSP430 flash memory controller. MID provides additional functionality over

the regular flash operation methods. Main purpose of the MID function is gaining higher reliability of flash

content and overall system integrity in harsh environments and application areas requiring such features.

The on-chip MID ROM contains the factory programmed MID support software. This software package

provides several software functions that allow to use all MID features.

The MID functionality can be enabled for different flash memory ranges. These memory ranges are

selectable by the cw0 parameter of the MID function MidEnable(). Details about address range coverage

is listed in Table 6-8.

For further information, see the MID Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)

(SLAU459).

Table 6-8. Address Range Coverage of cw0 Parameter

of MidEnable() Function

BITS OF cw0 PARAMETER

ADDRESS RANGE

087FFFh-080000h

07FFFFh-078000h

077FFFh-070000h

06FFFFh-068000h

067FFFh-060000h

05FFFFh-058000h

057FFFh-050000h

04FFFFh-048000h

047FFFh-040000h

03FFFFh-038000h

037FFFh-030000h

02FFFFh-028000h

027FFFh-020000h

01FFFFh-018000h

017FFFh-010000h

00FFFFh-008000h

cw0.15

cw0.14

cw0.13

cw0.12

cw0.11

cw0.10

cw0.9

cw0.8

cw0.7

cw0.6

cw0.5

cw0.4

cw0.3

cw0.2

cw0.1

cw0.0

6.11 RAM

The RAM is made up of n sectors. Each sector can be completely powered down to save leakage;

however, all data is lost. Features of the RAM include:

•

RAM has n sectors. The size of a sector can be found in Section 6.6.

Each sector 0 to n can be complete disabled; however, data retention is lost.

Each sector 0 to n automatically enters low-power retention mode when possible.

For further information, see the RAM Controller Module (Chapter Excerpt From MSP430x5xx Family,

SLAU208) (SLAU393).

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6.12 Backup RAM

The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5 and during

operation from a backup supply if the battery backup system module is implemented.

There are 8 bytes of backup RAM available. It can be word-wise accessed by the control registers

BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.

For further information, see the Backup RAM Module (Chapter Excerpt From MSP430x5xx Family,

SLAU208) (SLAU394).

6.13 Peripherals

Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be

handled using all instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx

Family User's Guide (SLAU208).

6.13.1 Digital I/O

There are up to nine 8-bit I/O ports implemented: P1 through P9 are complete and port PJ contains four

individual I/O ports.

•

All individual I/O bits are independently programmable.

Any combination of input, output, and interrupt conditions is possible.

Programmable pullup or pulldown on all ports.

Programmable drive strength on all ports.

Edge-selectable interrupt input capability for all the eight bits of ports P1, P2, P3, and P4.

Read and write access to port-control registers is supported by all instructions.

Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PD).

For further information, see the Digital I/O Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)

(SLAU396).

6.13.2 Port Mapping Controller

The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P2.

Table 6-9 lists the available mappings, and Table 6-10 lists the default settings.

For further information, see the Port Mapping Controller Module (Chapter Excerpt From MSP430x5xx

Family, SLAU208) (SLAU397).

Table 6-9. Port Mapping Mnemonics and Functions

VALUE

PxMAPy MNEMONIC

PM_NONE

INPUT PIN FUNCTION

OUTPUT PIN FUNCTION

0

None

DVSS

PM_CBOUT

–

Comparator_B output

1

2

PM_TB0CLK

Timer TB0 clock input

–

PM_ADC12CLK

PM_DMAE0

–

ADC12CLK

–

DMAE0 Input

–

PM_SVMOUT

SVM output

3

Timer TB0 high impedance input

TB0OUTH

PM_TB0OUTH

–

4

5

6

7

8

9

PM_TB0CCR0B

PM_TB0CCR1B

PM_TB0CCR2B

PM_TB0CCR3B

PM_TB0CCR4B

PM_TB0CCR5B

Timer TB0 CCR0 capture input CCI0B

Timer TB0 CCR1 capture input CCI1B

Timer TB0 CCR2 capture input CCI2B

Timer TB0 CCR3 capture input CCI3B

Timer TB0 CCR4 capture input CCI4B

Timer TB0 CCR5 capture input CCI5B

Timer TB0: TB0.0 compare output Out0

Timer TB0: TB0.1 compare output Out1

Timer TB0: TB0.2 compare output Out2

Timer TB0: TB0.3 compare output Out3

Timer TB0: TB0.4 compare output Out4

Timer TB0: TB0.5 compare output Out5

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Table 6-9. Port Mapping Mnemonics and Functions (continued)

VALUE

PxMAPy MNEMONIC

PM_TB0CCR6B

PM_UCA0RXD

PM_UCA0SOMI

PM_UCA0TXD

PM_UCA0SIMO

PM_UCA0CLK

PM_UCB0STE

PM_UCB0SOMI

PM_UCB0SCL

PM_UCB0SIMO

PM_UCB0SDA

PM_UCB0CLK

PM_UCA0STE

PM_MCLK

INPUT PIN FUNCTION

OUTPUT PIN FUNCTION

Timer TB0: TB0.6 compare output Out6

10

Timer TB0 CCR6 capture input CCI6B

USCI_A0 UART RXD (Direction controlled by USCI - input)

11

12

13

14

15

16

USCI_A0 SPI slave out master in (direction controlled by USCI)

USCI_A0 UART TXD (Direction controlled by USCI - output)

USCI_A0 SPI slave in master out (direction controlled by USCI)

USCI_A0 clock input/output (direction controlled by USCI)

USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)

USCI_B0 SPI slave out master in (direction controlled by USCI)

USCI_B0 I2C clock (open drain and direction controlled by USCI)

USCI_B0 SPI slave in master out (direction controlled by USCI)

USCI_B0 I2C data (open drain and direction controlled by USCI)

USCI_B0 clock input/output (direction controlled by USCI)

USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)

17

18

–

MCLK

Reserved

Reserved for test purposes. Do not use this setting.

19

Reserved

20-30

Reserved

None

DVSS

Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents

when applying analog signals.

31 (0FFh)⁽¹⁾

PM_ANALOG

(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide, and the upper bits are

ignored, which results in a read out value of 31.

Table 6-10. Default Mapping

PxMAPy MNEMONIC

INPUT PIN FUNCTION

OUTPUT PIN FUNCTION

PM_UCB0STE,

PM_UCA0CLK

USCI_B0 SPI slave transmit enable (direction controlled by USCI - input),

USCI_A0 clock input/output (direction controlled by USCI)

P2.0/P2MAP0

PM_UCB0SIMO,

PM_UCB0SDA

USCI_B0 SPI slave in master out (direction controlled by USCI),

USCI_B0 I2C data (open drain and direction controlled by USCI)

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

PM_UCB0SOMI,

PM_UCB0SCL

USCI_B0 SPI slave out master in (direction controlled by USCI),

USCI_B0 I2C clock (open drain and direction controlled by USCI)

PM_UCB0CLK,

PM_UCA0STE

USCI_B0 clock input/output (direction controlled by USCI),

USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)

PM_UCA0TXD,

PM_UCA0SIMO

USCI_A0 UART TXD (direction controlled by USCI - output),

USCI_A0 SPI slave in master out (direction controlled by USCI)

PM_UCA0RXD,

PM_UCA0SOMI

USCI_A0 UART RXD (direction controlled by USCI - input),

USCI_A0 SPI slave out master in (direction controlled by USCI)

P2.6/P2MAP6/ R03

PM_NONE

–

DVSS

P2.7/P2MAP7/LCDREF/R13

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6.13.3 Oscillator and System Clock

The clock system is supported by the Unified Clock System (UCS) module that includes support for a 32-

kHz watch crystal oscillator (in XT1 LF mode; XT1 HF mode is not supported), an internal very-low-power

low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal

digitally controlled oscillator (DCO), and a high-frequency crystal oscillator (XT2). The UCS module is

designed to meet the requirements of both low system cost and low power consumption. The UCS module

features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator,

stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal

DCO provides a fast turnon clock source and stabilizes in 3 µs (typical). The UCS module provides the

following clock signals:

•

Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the

internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal

digitally-controlled oscillator DCO.

•

Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources

available to ACLK.

Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be

sourced by same sources available to ACLK.

ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.

For further information, see the UCS Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)

(SLAU390).

6.13.4 Power-Management Module (PMM)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device and

contains programmable output levels to provide for power optimization. The PMM also includes supply

voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection.

The brownout circuit is implemented to provide the proper internal reset signal to the device during power-

on and power-off. The SVS and SVM circuitry detects if the supply voltage drops below a user-selectable

level and supports both supply voltage supervision (the device is automatically reset) and supply voltage

monitoring (the device is not automatically reset). SVS and SVM circuitry is available on the primary

supply and core supply.

For further information, see the PMM Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)

(SLAU388).

6.13.5 Hardware Multiplier (MPY)

The multiplication operation is supported by a dedicated peripheral module. The module performs

operations with 32-bit, 24-bit, 16-bit, and 8-bit operands. The module supports signed and unsigned

multiplication as well as signed and unsigned multiply-and-accumulate operations.

For further information, see the MPY Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)

(SLAU404).

6.13.6 Real-Time Clock (RTC_B)

The RTC_B module can be configured for real-time clock (RTC) or calendar mode providing seconds,

minutes, hours, day of week, day of month, month, and year. Calendar mode integrates an internal

calendar which compensates for months with less than 31 days and includes leap year correction. The

RTC_B also supports flexible alarm functions and offset-calibration hardware. The implementation on this

device supports operation in LPM3.5 mode and operation from a backup supply.

The application report Using the MSP430 RTC_B Module With Battery Backup Supply (SLAA665)

describes how to use the RTC_B with battery backup supply functionality to retain the time and keep the

RTC counting through loss of main power supply, as well as how to handle correct reinitialization when the

main power supply is restored.

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For further information, see the RTC_B Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)

(SLAU403).

6.13.7 Watchdog Timer (WDT_A)

The primary function of the WDT_A module is to perform a controlled system restart after a software

problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function

is not needed in an application, the module can be configured as an interval timer and can generate

interrupts at selected time intervals.

For further information, see the WDT_A Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)

(SLAU399).

6.13.8 System Module (SYS)

The SYS module handles many of the system functions within the device. These include power-on reset

and power-up clear handling, NMI source selection and management, reset interrupt vector generators

(see Table 6-11), bootloader entry mechanisms, and configuration management (device descriptors). SYS

also includes a data exchange mechanism using JTAG called a JTAG mailbox that can be used in the

application.

For further information, see the SYS Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)

(SLAU387).

Table 6-11. System Module Interrupt Vector Registers

INTERRUPT VECTOR

INTERRUPT EVENT

WORD ADDRESS

OFFSET

PRIORITY

REGISTER

No interrupt pending

Brownout (BOR)

00h

02h

Highest

RST/NMI (BOR)

04h

PMMSWBOR (BOR)

LPM3.5 or LPM4.5 wakeup (BOR)

Security violation (BOR)

SVSL (POR)

06h

08h

0Ah

0Ch

0Eh

SVSH (POR)

SVML_OVP (POR)

SVMH_OVP (POR)

PMMSWPOR (POR)

WDT time-out (PUC)

WDT key violation (PUC)

KEYV flash key violation (PUC)

Reserved

10h

SYSRSTIV, System Reset

019Eh

12h

14h

16h

18h

1Ah

1Ch

1Eh

Peripheral area fetch (PUC)

PMM key violation (PUC)

Reserved

20h

22h to 3Eh

Lowest

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Table 6-11. System Module Interrupt Vector Registers (continued)

INTERRUPT VECTOR

REGISTER

INTERRUPT EVENT

WORD ADDRESS

OFFSET

PRIORITY

No interrupt pending

SVMLIFG

00h

02h

Highest

SVMHIFG

04h

DLYLIFG

06h

DLYHIFG

08h

SYSSNIV, System NMI

VMAIFG

019Ch

0Ah

JMBINIFG

0Ch

JMBOUTIFG

SVMLVLRIFG

SVMHVLRIFG

Reserved

0Eh

10h

12h

14h to 1Eh

00h

Lowest

Highest

No interrupt pending

NMIIFG

02h

OFIFG

04h

SYSUNIV, User NMI

019Ah

0198h

ACCVIFG

06h

BUSIFG

08h

Reserved

0Ah to 1Eh

00h

Lowest

Highest

No interrupt pending

02h

Reserved

SYSBERRIV, Bus Error

04h

MID error

Reserved

06h

08h to 1Eh

Lowest

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6.13.9 DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU

intervention. For example, the DMA controller can be used to move data from the ADC12_A conversion

memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA

controller reduces system power consumption by allowing the CPU to remain in sleep mode, without

having to awaken to move data to or from a peripheral.

For further information, see the DMA Controller Module (Chapter Excerpt From MSP430x5xx Family,

SLAU208) (SLAU395).

Table 6-12. DMA Trigger Assignments⁽¹⁾

CHANNEL

TRIGGER

0

1

2

3

4

5

0

DMAREQ

1

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TA2CCR0 CCIFG

TA2CCR2 CCIFG

TBCCR0 CCIFG

TBCCR2 CCIFG

Reserved

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Reserved

UCA2RXIFG

UCA2TXIFG

UCB2RXIFG

UCB2TXIFG

UCA0RXIFG

UCA0TXIFG

UCB0RXIFG

UCB0TXIFG

UCA1RXIFG

UCA1TXIFG

UCB1RXIFG

UCB1TXIFG

ADC12IFGx

DAC12_0IFG

DAC12_1IFG

Reserved

MPY ready

DMA5IFG

DMA0IFG

DMA1IFG

DMA2IFG

DMAE0

DMA3IFG

DMA4IFG

(1) Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers do not

cause any DMA trigger event when selected.

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6.13.10 Universal Serial Communication Interface (USCI)

The USCI modules are used for serial data communication. The USCI module supports synchronous

communication protocols such as SPI (3-pin or 4-pin) and I²C, and asynchronous communication

protocols such as UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI

module contains two portions, A and B.

The USCI_An module provides support for SPI (3-pin or 4-pin), UART, enhanced UART, or IrDA.

The USCI_Bn module provides support for SPI (3-pin or 4-pin) or I²C.

The MSP430F665x, MSP430F645x, MSP430F565x, MSP430F535x series includes three complete USCI

modules (n = 0 to 2).

For further information, see the following User's Guides:

•

USCI UART Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU410)

USCI SPI Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU411)

USCI I2C Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU412)

6.13.11 Timer TA0

Timer TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers (see Table 6-13).

TA0 supports multiple capture/compares, PWM outputs, and interval timing. TA0 also has extensive

interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each

of the capture/compare registers.

For further information, see the Timer_A Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)

(SLAU400).

Table 6-13. Timer TA0 Signal Connections

INPUT PIN

NUMBER

DEVICE INPUT

SIGNAL

MODULE INPUT

SIGNAL

MODULE

OUTPUT SIGNAL

DEVICE OUTPUT

SIGNAL

OUTPUT PIN

NUMBER

MODULE BLOCK

34-P1.0

TA0CLK

ACLK

TACLK

ACLK

SMCLK

TACLK

CCI0A

CCI0B

GND

Timer

NA

SMCLK

TA0CLK

TA0.0

DV_SS

34-P1.0

35-P1.1

CCR0

CCR1

TA0

TA0.0

DV_SS

DV_CC

V_CC

36-P1.2

40-P1.6

TA0.1

CCI1A

CCI1B

36-P1.2

40-P1.6

ADC12_A

(internal)

TA1

TA0.1

DV_SS

GND

ADC12SHSx = {1}

DV_CC

TA0.2

DV_SS

DV_CC

TA0.3

DV_SS

DV_CC

V_CC

CCI2A

CCI2B

GND

37-P1.3

41-P1.7

37-P1.3

41-P1.7

CCR2

CCR3

TA2

TA3

TA0.2

TA0.3

V_CC

38-P1.4

CCI3A

CCI3B

GND

38-P1.4

V_CC

Detailed Description

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Table 6-13. Timer TA0 Signal Connections (continued)

INPUT PIN

NUMBER

DEVICE INPUT

SIGNAL

MODULE INPUT

SIGNAL

MODULE

OUTPUT SIGNAL

DEVICE OUTPUT

SIGNAL

OUTPUT PIN

NUMBER

MODULE BLOCK

39-P1.5

TA0.4

DV_SS

DV_CC

CCI4A

CCI4B

GND

39-P1.5

CCR4

TA4

TA0.4

V_CC

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6.13.12 Timer TA1

Timer TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers (see Table 6-14).

TA1 supports multiple capture/compares, PWM outputs, and interval timing. TA1 also has extensive

interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each

of the capture/compare registers.

For further information, see the Timer_A Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)

(SLAU400).

Table 6-14. Timer TA1 Signal Connections

INPUT PIN

NUMBER

DEVICE INPUT

SIGNAL

MODULE INPUT

SIGNAL

MODULE

OUTPUT SIGNAL

DEVICE OUTPUT

SIGNAL

OUTPUT PIN

NUMBER

MODULE BLOCK

42-P3.0

TA1CLK

ACLK

TACLK

ACLK

SMCLK

TACLK

CCI0A

CCI0B

GND

Timer

NA

SMCLK

TA1CLK

TA1.0

DV_SS

42-P3.0

43-P3.1

44-P3.2

CCR0

CCR1

CCR2

TA0

TA1.0

DV_SS

DV_CC

V_CC

44-P3.2

45-P3.3

TA1.1

CCI1A

DAC12_A

DAC12_0,

DAC12_1

(internal)

CBOUT (internal)

CCI1B

TA1

TA2

TA1.1

TA1.2

DV_SS

DV_CC

GND

V_CC

TA1.2

CCI2A

CCI2B

GND

V_CC

45-P3.3

ACLK (internal)

DV_SS

DV_CC

Detailed Description

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6.13.13 Timer TA2

Timer TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers (see Table 6-15).

TA2 supports multiple capture/compares, PWM outputs, and interval timing. TA2 also has extensive

interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each

of the capture/compare registers.

For further information, see the Timer_A Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)

(SLAU400).

Table 6-15. Timer TA2 Signal Connections

INPUT PIN

NUMBER

DEVICE INPUT

SIGNAL

MODULE INPUT

SIGNAL

MODULE

OUTPUT SIGNAL

DEVICE OUTPUT

SIGNAL

OUTPUT PIN

NUMBER

MODULE BLOCK

46-P3.4

TA2CLK

ACLK

TACLK

ACLK

SMCLK

TACLK

CCI0A

CCI0B

GND

Timer

NA

SMCLK

TA2CLK

TA2.0

46-P3.4

47-P3.5

48-P3.6

49-P3.7

DV_SS

CCR0

CCR1

CCR2

TA0

TA1

TA2

TA2.0

TA2.1

TA2.2

DV_SS

DV_CC

V_CC

48-P3.6

49-P3.7

TA2.1

CCI1A

CCI1B

GND

CBOUT (internal)

DV_SS

DV_CC

V_CC

TA2.2

CCI2A

CCI2B

GND

ACLK (internal)

DV_SS

DV_CC

V_CC

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6.13.14 Timer TB0

Timer TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers (see Table 6-16).

TB0 supports multiple capture/compares, PWM outputs, and interval timing. TB0 also has extensive

interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each

of the capture/compare registers.

For further information, see the Timer_B Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)

(SLAU401).

Table 6-16. Timer TB0 Signal Connections

INPUT PIN

NUMBER

DEVICE INPUT

SIGNAL

MODULE INPUT

SIGNAL

MODULE

OUTPUT SIGNAL

DEVICE OUTPUT

SIGNAL

OUTPUT PIN

NUMBER

MODULE BLOCK

58-P8.0

TB0CLK

P2MAPx⁽¹⁾

ACLK

Timer

NA

SMCLK

58-P8.0

TB0CLK

P2MAPx⁽¹⁾

50-P4.0

P2MAPx⁽¹⁾

TB0.0

CCI0A

CCI0B

50-P4.0

P2MAPx⁽¹⁾

CCR0

CCR1

TB0

TB1

TB0.0

TB0.1

ADC12 (internal)

ADC12SHSx = {2}

DV_SS

GND

DV_CC

TB0.1

V_CC

51-P4.1

P2MAPx⁽¹⁾

CCI1A

CCI1B

51-P4.1

P2MAPx⁽¹⁾

ADC12 (internal)

ADC12SHSx = {3}

DV_SS

GND

DV_CC

TB0.2

V_CC

52-P4.2

P2MAPx⁽¹⁾

CCI2A

CCI2B

52-P4.2

P2MAPx⁽¹⁾

DAC12_A

DAC12_0,

DAC12_1

(internal)

CCR2

TB2

TB0.2

DV_SS

GND

DV_CC

TB0.3

DV_SS

DV_CC

TB0.4

DV_SS

DV_CC

TB0.5

DV_SS

DV_CC

TB0.6

DV_SS

DV_CC

V_CC

CCI3A

CCI3B

GND

53-P4.3

P2MAPx⁽¹⁾

53-P4.3

P2MAPx⁽¹⁾

CCR3

CCR4

CCR5

CCR6

TB3

TB4

TB5

TB6

TB0.3

TB0.4

TB0.5

TB0.6

V_CC

54-P4.4

P2MAPx⁽¹⁾

CCI4A

CCI4B

GND

54-P4.4

P2MAPx⁽¹⁾

V_CC

55-P4.5

P2MAPx⁽¹⁾

CCI5A

CCI5B

GND

55-P4.5

P2MAPx⁽¹⁾

V_CC

56-P4.6

P2MAPx⁽¹⁾

CCI6A

CCI6B

GND

56-P4.6

P2MAPx⁽¹⁾

V_CC

(1) Timer functions are selectable through the port mapping controller.

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6.13.15 Comparator_B

The primary function of the Comparator_B module is to support precision slope analog-to-digital

conversions, battery voltage supervision, and monitoring of external analog signals.

For further information, see the COMP_B Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)

(SLAU408).

6.13.16 ADC12_A

The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit

SAR core, sample select control, reference generator, and a 16 word conversion-and-control buffer. The

conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored

without any CPU intervention.

For further information, see the ADC12_A Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)

(SLAU406).

6.13.17 DAC12_A

The DAC12_A module is a 12-bit, R-ladder, voltage output DAC. The DAC12_A may be used in 8-bit or

12-bit mode, and may be used in conjunction with the DMA controller. When multiple DAC12_A modules

are present, they may be grouped together for synchronous operation.

6.13.18 CRC16

The CRC16 module produces a signature based on a sequence of entered data values and can be used

for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.

For further information, see the CRC Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)

(SLAU398).

6.13.19 Voltage Reference (REF) Module

The REF module is responsible for generation of all critical reference voltages that can be used by the

various analog peripherals in the device.

For further information, see the REF Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)

(SLAU405).

6.13.20 LCD_B

The LCD_B driver generates the segment and common signals that are required to drive a liquid crystal

display (LCD). The LCD_B controller has dedicated data memories to hold segment drive information.

Common and segment signals are generated as defined by the mode. Static, 2-mux, 3-mux, and 4-mux

LCDs are supported. The module can provide a LCD voltage independent of the supply voltage with its

integrated charge pump. It is possible to control the level of the LCD voltage, and thus contrast, by

software. The module also provides an automatic blinking capability for individual segments.

The LCD_B module is only available on the MSP430F665x and MSP430F645x devices.

For further information, see the LCD_B Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)

(SLAU409).

6.13.21 LDO and PU Port

The integrated 3.3-V power system incorporates an integrated 3.3-V LDO regulator that allows the entire

MSP430 microcontroller to be powered from nominal 5-V LDOI when it is made available for the system.

Alternatively, the power system can supply power only to other components within the system, or it can be

unused altogether.

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The Port U Pins (PU.0 and PU.1) function as general-purpose high-current I/O pins. These pins can only

be configured together as either both inputs or both outputs. Port U is supplied by the LDOO rail. If the

3.3-V LDO is not being used in the system (disabled), the LDOO pin can be supplied externally.

The LDO-PWR module (LDO and PU Port) is only available on the MSP430F645x and MSP430F535x

devices.

Detailed Description

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6.13.22 Embedded Emulation Module (EEM) (L Version)

The EEM supports real-time in-system debugging. The L version of the EEM has the following features:

•

Eight hardware triggers or breakpoints on memory access

Two hardware triggers or breakpoints on CPU register write access

Up to ten hardware triggers can be combined to form complex triggers or breakpoints

Two cycle counters

Sequencer

State storage

Clock control on module level

For further information, see the EEM Module (Chapter Excerpt From MSP430x5xx Family, SLAU208)

(SLAU414).

6.13.23 Peripheral File Map

Table 6-17 lists the base register address for each available peripheral.

Table 6-17. Peripherals

MODULE NAME

Special Functions (see Table 6-18)

PMM (see Table 6-19)

BASE ADDRESS

0100h

0120h

0140h

0150h

0158h

015Ch

0160h

0180h

01B0h

01C0h

01D0h

0200h

0220h

0240h

0260h

0280h

0320h

0340h

0380h

03C0h

0400h

0480h

04A0h

04C0h

0500h

0510h

0520h

0530h

0540h

OFFSET ADDRESS RANGE⁽¹⁾

000h-01Fh

000h-010h

000h-00Fh

000h-007h

000h-001h

000h-01Fh

000h-001h

000h-003h

000h-007h

000h-01Fh

000h-00Bh

000h-01Fh

000h-02Eh

000h-01Fh

000h-02Fh

000h-00Fh

000h-00Ah

Flash Control (see Table 6-20)

CRC16 (see Table 6-21)

RAM Control (see Table 6-22)

Watchdog (see Table 6-23)

UCS (see Table 6-24)

SYS (see Table 6-25)

Shared Reference (see Table 6-26)

Port Mapping Control (see Table 6-27)

Port Mapping Port P2 (see Table 6-27)

Port P1, P2 (see Table 6-28)

Port P3, P4 (see Table 6-29)

Port P5, P6 (see Table 6-30)

Port P7, P8 (see Table 6-31)

Port P9 (see Table 6-32)

Port PJ (see Table 6-33)

Timer TA0 (see Table 6-34)

Timer TA1 (see Table 6-35)

Timer TB0 (see Table 6-36)

Timer TA2 (see Table 6-37)

Battery Backup (see Table 6-38)

RTC_B (see Table 6-39)

32-Bit Hardware Multiplier (see Table 6-40)

DMA General Control (see Table 6-41)

DMA Channel 0 (see Table 6-41)

DMA Channel 1 (see Table 6-41)

DMA Channel 2 (see Table 6-41)

DMA Channel 3 (see Table 6-41)

(1) For a detailed description of the individual control register offset addresses, see the MSP430F5xx and MSP430F6xx Family User's

Guide (SLAU208).

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Table 6-17. Peripherals (continued)

MODULE NAME

BASE ADDRESS

0550h

OFFSET ADDRESS RANGE⁽¹⁾

000h-00Ah

DMA Channel 4 (see Table 6-41)

DMA Channel 5 (see Table 6-41)

USCI_A0 (see Table 6-42)

USCI_B0 (see Table 6-43)

USCI_A1 (see Table 6-44)

USCI_B1 (see Table 6-45)

USCI_A2 (see Table 6-46)

USCI_B2 (see Table 6-47)

ADC12_A (see Table 6-48)

DAC12_A (see Table 6-49)

Comparator_B (see Table 6-50)

0560h

000h-00Ah

05C0h

05E0h

000h-01Fh

0600h

000h-01Fh

0620h

000h-01Fh

0640h

000h-01Fh

0660h

000h-01Fh

0700h

000h-03Fh

0780h

000h-01Fh

08C0h

0900h

000h-00Fh

(2)

LDO-PWR; LDO and Port U configuration (see Table 6-51)

000h-014h

(3)

LCD_B control (see Table 6-52)

0A00h

000h-05Fh

(2) Only on devices with peripheral module LDO-PWR.

(3) Only on devices with peripheral module LCD_B.

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Table 6-18. Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION

REGISTER

SFRIE1

OFFSET

SFR interrupt enable

SFR interrupt flag

00h

02h

04h

SFRIFG1

SFR reset pin control

SFRRPCR

Table 6-19. PMM Registers (Base Address: 0120h)

REGISTER DESCRIPTION

REGISTER

PMMCTL0

OFFSET

PMM control 0

00h

02h

04h

06h

0Ch

0Eh

10h

PMM control 1

PMMCTL1

SVSMHCTL

SVSMLCTL

PMMIFG

SVS high-side control

SVS low-side control

PMM interrupt flags

PMM interrupt enable

PMM power mode 5 control

PMMIE

PM5CTL0

Table 6-20. Flash Control Registers (Base Address: 0140h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Flash control 1

Flash control 3

Flash control 4

FCTL1

FCTL3

FCTL4

00h

04h

06h

Table 6-21. CRC16 Registers (Base Address: 0150h)

REGISTER DESCRIPTION

REGISTER

CRC16DI

OFFSET

CRC data input

CRC result

00h

04h

CRC16INIRES

Table 6-22. RAM Control Registers (Base Address: 0158h)

REGISTER DESCRIPTION

REGISTER

RCCTL0

OFFSET

RAM control 0

00h

Table 6-23. Watchdog Registers (Base Address: 015Ch)

REGISTER DESCRIPTION

REGISTER

WDTCTL

Watchdog timer control

Table 6-24. UCS Registers (Base Address: 0160h)

REGISTER DESCRIPTION

REGISTER

UCSCTL0

UCS control 0

UCS control 1

UCS control 2

UCS control 3

UCS control 4

UCS control 5

UCS control 6

UCS control 7

UCS control 8

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

UCSCTL1

UCSCTL2

UCSCTL3

UCSCTL4

UCSCTL5

UCSCTL6

UCSCTL7

UCSCTL8

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Table 6-25. SYS Registers (Base Address: 0180h)

REGISTER DESCRIPTION

REGISTER

OFFSET

System control

SYSCTL

00h

02h

06h

08h

0Ah

0Ch

0Eh

18h

1Ah

1Ch

1Eh

Bootloader configuration area

JTAG mailbox control

JTAG mailbox input 0

JTAG mailbox input 1

JTAG mailbox output 0

JTAG mailbox output 1

Bus error vector generator

User NMI vector generator

System NMI vector generator

Reset vector generator

SYSBSLC

SYSJMBC

SYSJMBI0

SYSJMBI1

SYSJMBO0

SYSJMBO1

SYSBERRIV

SYSUNIV

SYSSNIV

SYSRSTIV

Table 6-26. Shared Reference Registers (Base Address: 01B0h)

REGISTER DESCRIPTION

REGISTER

REFCTL

OFFSET

Shared reference control

00h

Table 6-27. Port Mapping Registers

(Base Address of Port Mapping Control: 01C0h, Port P4: 01D0h)

REGISTER DESCRIPTION

REGISTER

PMAPPWD

Port mapping password

Port mapping control

Port P2.0 mapping

Port P2.1 mapping

Port P2.2 mapping

Port P2.3 mapping

Port P2.4 mapping

Port P2.5 mapping

Port P2.6 mapping

Port P2.7 mapping

00h

02h

00h

01h

02h

03h

04h

05h

06h

07h

PMAPCTL

P2MAP0

P2MAP1

P2MAP2

P2MAP3

P2MAP4

P2MAP5

P2MAP6

P2MAP7

Table 6-28. Port P1, P2 Registers (Base Address: 0200h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P1 input

P1IN

00h

02h

04h

06h

08h

0Ah

0Eh

18h

1Ah

1Ch

01h

03h

05h

07h

Port P1 output

Port P1 direction

P1OUT

P1DIR

P1REN

P1DS

P1SEL

P1IV

Port P1 pullup/pulldown enable

Port P1 drive strength

Port P1 selection

Port P1 interrupt vector word

Port P1 interrupt edge select

Port P1 interrupt enable

Port P1 interrupt flag

Port P2 input

P1IES

P1IE

P1IFG

P2IN

Port P2 output

P2OUT

P2DIR

P2REN

Port P2 direction

Port P2 pullup/pulldown enable

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Table 6-28. Port P1, P2 Registers (Base Address: 0200h) (continued)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P2 drive strength

Port P2 selection

P2DS

P2SEL

P2IV

09h

0Bh

1Eh

19h

1Bh

1Dh

Port P2 interrupt vector word

Port P2 interrupt edge select

Port P2 interrupt enable

Port P2 interrupt flag

P2IES

P2IE

P2IFG

Table 6-29. Port P3, P4 Registers (Base Address: 0220h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P3 input

P3IN

00h

02h

04h

06h

08h

0Ah

0Eh

18h

1Ah

1Ch

01h

03h

05h

07h

09h

0Bh

1Eh

19h

1Bh

1Dh

Port P3 output

Port P3 direction

P3OUT

P3DIR

P3REN

P3DS

P3SEL

P3IV

Port P3 pullup/pulldown enable

Port P3 drive strength

Port P3 selection

Port P3 interrupt vector word

Port P3 interrupt edge select

Port P3 interrupt enable

Port P3 interrupt flag

P3IES

P3IE

P3IFG

P4IN

Port P4 input

Port P4 output

P4OUT

P4DIR

P4REN

P4DS

P4SEL

P4IV

Port P4 direction

Port P4 pullup/pulldown enable

Port P4 drive strength

Port P4 selection

Port P4 interrupt vector word

Port P4 interrupt edge select

Port P4 interrupt enable

Port P4 interrupt flag

P4IES

P4IE

P4IFG

Table 6-30. Port P5, P6 Registers (Base Address: 0240h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P5 input

P5IN

00h

02h

04h

06h

08h

0Ah

01h

03h

05h

07h

09h

0Bh

Port P5 output

P5OUT

P5DIR

P5REN

P5DS

Port P5 direction

Port P5 pullup/pulldown enable

Port P5 drive strength

Port P5 selection

P5SEL

P6IN

Port P6 input

Port P6 output

P6OUT

P6DIR

P6REN

P6DS

Port P6 direction

Port P6 pullup/pulldown enable

Port P6 drive strength

Port P6 selection

P6SEL

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Table 6-31. Port P7, P8 Registers (Base Address: 0260h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P7 input

P7IN

00h

02h

04h

06h

08h

0Ah

01h

03h

05h

07h

09h

0Bh

Port P7 output

Port P7 direction

P7OUT

P7DIR

P7REN

P7DS

Port P7 pullup/pulldown enable

Port P7 drive strength

Port P7 selection

P7SEL

P8IN

Port P8 input

Port P8 output

P8OUT

P8DIR

P8REN

P8DS

Port P8 direction

Port P8 pullup/pulldown enable

Port P8 drive strength

Port P8 selection

P8SEL

Table 6-32. Port P9 Register (Base Address: 0280h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P9 input

P9IN

00h

02h

04h

06h

08h

0Ah

Port P9 output

P9OUT

P9DIR

P9REN

P9DS

Port P9 direction

Port P9 pullup/pulldown enable

Port P9 drive strength

Port P9 selection

P9SEL

Table 6-33. Port J Registers (Base Address: 0320h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port PJ input

PJIN

00h

02h

04h

06h

08h

Port PJ output

PJOUT

PJDIR

PJREN

PJDS

Port PJ direction

Port PJ pullup/pulldown enable

Port PJ drive strength

Table 6-34. TA0 Registers (Base Address: 0340h)

REGISTER DESCRIPTION

REGISTER

TA0CTL

OFFSET

TA0 control

00h

02h

04h

06h

08h

0Ah

10h

12h

14h

16h

18h

1Ah

20h

2Eh

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

Capture/compare control 3

Capture/compare control 4

TA0 counter

TA0CCTL0

TA0CCTL1

TA0CCTL2

TA0CCTL3

TA0CCTL4

TA0R

Capture/compare 0

Capture/compare 1

Capture/compare 2

Capture/compare 3

Capture/compare 4

TA0 expansion 0

TA0CCR0

TA0CCR1

TA0CCR2

TA0CCR3

TA0CCR4

TA0EX0

TA0 interrupt vector

TA0IV

Detailed Description

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Table 6-35. TA1 Registers (Base Address: 0380h)

REGISTER DESCRIPTION

REGISTER

TA1CTL

OFFSET

TA1 control

00h

02h

04h

06h

10h

12h

14h

16h

20h

2Eh

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

TA1 counter

TA1CCTL0

TA1CCTL1

TA1CCTL2

TA1R

Capture/compare 0

Capture/compare 1

Capture/compare 2

TA1 expansion 0

TA1CCR0

TA1CCR1

TA1CCR2

TA1EX0

TA1 interrupt vector

TA1IV

Table 6-36. TB0 Registers (Base Address: 03C0h)

REGISTER DESCRIPTION

REGISTER

TB0CTL

OFFSET

TB0 control

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

12h

14h

16h

18h

1Ah

1Ch

1Eh

20h

2Eh

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

Capture/compare control 3

Capture/compare control 4

Capture/compare control 5

Capture/compare control 6

TB0 counter

TB0CCTL0

TB0CCTL1

TB0CCTL2

TB0CCTL3

TB0CCTL4

TB0CCTL5

TB0CCTL6

TB0R

Capture/compare 0

TB0CCR0

TB0CCR1

TB0CCR2

TB0CCR3

TB0CCR4

TB0CCR5

TB0CCR6

TB0EX0

Capture/compare 1

Capture/compare 2

Capture/compare 3

Capture/compare 4

Capture/compare 5

Capture/compare 6

TB0 expansion 0

TB0 interrupt vector

TB0IV

Table 6-37. TA2 Registers (Base Address: 0400h)

REGISTER DESCRIPTION

REGISTER

TA2CTL

OFFSET

TA2 control

00h

02h

04h

06h

10h

12h

14h

16h

20h

2Eh

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

TA2 counter

TA2CCTL0

TA2CCTL1

TA2CCTL2

TA2R

Capture/compare 0

Capture/compare 1

Capture/compare 2

TA2 expansion 0

TA2CCR0

TA2CCR1

TA2CCR2

TA2EX0

TA2 interrupt vector

TA2IV

78

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Table 6-38. Battery Backup Registers (Base Address: 0480h)

REGISTER DESCRIPTION

REGISTER

BAKMEM0

OFFSET

Battery backup memory 0

Battery backup memory 1

Battery backup memory 2

Battery backup memory 3

Battery backup control

00h

02h

04h

06h

1Ch

1Eh

BAKMEM1

BAKMEM2

BAKMEM3

BAKCTL

Battery charger control

BAKCHCTL

Table 6-39. Real-Time Clock Registers (Base Address: 04A0h)

REGISTER DESCRIPTION

REGISTER

RTCCTL0

OFFSET

RTC control 0

00h

01h

02h

03h

08h

0Ah

0Ch

0Dh

0Eh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Eh

RTC control 1

RTCCTL1

RTCCTL2

RTCCTL3

RTCPS0CTL

RTCPS1CTL

RTCPS0

RTC control 2

RTC control 3

RTC prescaler 0 control

RTC prescaler 1 control

RTC prescaler 0

RTC prescaler 1

RTC interrupt vector word

RTC seconds

RTCPS1

RTCIV

RTCSEC

RTC minutes

RTCMIN

RTC hours

RTCHOUR

RTCDOW

RTCDAY

RTC day of week

RTC days

RTC month

RTCMON

RTCYEARL

RTCYEARH

RTCAMIN

RTCAHOUR

RTCADOW

RTCADAY

BIN2BCD

BCD2BIN

RTC year low

RTC year high

RTC alarm minutes

RTC alarm hours

RTC alarm day of week

RTC alarm days

Binary-to-BCD conversion

BCD-to-binary conversion

Table 6-40. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

16-bit operand 1 – multiply

MPY

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

12h

14h

16h

16-bit operand 1 – signed multiply

16-bit operand 1 – multiply accumulate

16-bit operand 1 – signed multiply accumulate

16-bit operand 2

MPYS

MAC

MACS

OP2

16 × 16 result low word

RESLO

RESHI

16 × 16 result high word

16 × 16 sum extension

SUMEXT

MPY32L

32-bit operand 1 – multiply low word

32-bit operand 1 – multiply high word

32-bit operand 1 – signed multiply low word

32-bit operand 1 – signed multiply high word

MPY32H

MPYS32L

MPYS32H

Detailed Description

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Table 6-40. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h) (continued)

REGISTER DESCRIPTION

REGISTER

MAC32L

OFFSET

32-bit operand 1 – multiply accumulate low word

32-bit operand 1 – multiply accumulate high word

32-bit operand 1 – signed multiply accumulate low word

32-bit operand 1 – signed multiply accumulate high word

32-bit operand 2 – low word

18h

1Ah

1Ch

1Eh

20h

22h

24h

26h

28h

2Ah

2Ch

MAC32H

MACS32L

MACS32H

OP2L

32-bit operand 2 – high word

OP2H

32 × 32 result 0 – least significant word

32 × 32 result 1

RES0

RES1

32 × 32 result 2

RES2

32 × 32 result 3 – most significant word

MPY32 control 0

RES3

MPY32CTL0

Table 6-41. DMA Registers (Base Address DMA General Control: 0500h,

DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA

Channel 4: 0550h, DMA Channel 5: 0560h)

REGISTER DESCRIPTION

DMA general control: DMA module control 0

REGISTER

DMACTL0

OFFSET

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Ah

00h

DMA general control: DMA module control 1

DMA general control: DMA module control 2

DMA general control: DMA module control 3

DMA general control: DMA module control 4

DMA general control: DMA interrupt vector

DMA channel 0 control

DMACTL1

DMACTL2

DMACTL3

DMACTL4

DMAIV

DMA0CTL

DMA0SAL

DMA0SAH

DMA0DAL

DMA0DAH

DMA0SZ

DMA channel 0 source address low

DMA channel 0 source address high

DMA channel 0 destination address low

DMA channel 0 destination address high

DMA channel 0 transfer size

DMA channel 1 control

DMA1CTL

DMA1SAL

DMA1SAH

DMA1DAL

DMA1DAH

DMA1SZ

DMA channel 1 source address low

DMA channel 1 source address high

DMA channel 1 destination address low

DMA channel 1 destination address high

DMA channel 1 transfer size

DMA channel 2 control

DMA2CTL

DMA2SAL

DMA2SAH

DMA2DAL

DMA2DAH

DMA2SZ

DMA channel 2 source address low

DMA channel 2 source address high

DMA channel 2 destination address low

DMA channel 2 destination address high

DMA channel 2 transfer size

DMA channel 3 control

DMA3CTL

DMA3SAL

DMA3SAH

DMA3DAL

DMA3DAH

DMA3SZ

DMA channel 3 source address low

DMA channel 3 source address high

DMA channel 3 destination address low

DMA channel 3 destination address high

DMA channel 3 transfer size

DMA channel 4 control

DMA4CTL

80

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Table 6-41. DMA Registers (Base Address DMA General Control: 0500h,

DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA

Channel 4: 0550h, DMA Channel 5: 0560h) (continued)

REGISTER DESCRIPTION

DMA channel 4 source address low

REGISTER

DMA4SAL

OFFSET

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Ah

DMA channel 4 source address high

DMA channel 4 destination address low

DMA channel 4 destination address high

DMA channel 4 transfer size

DMA4SAH

DMA4DAL

DMA4DAH

DMA4SZ

DMA channel 5 control

DMA5CTL

DMA5SAL

DMA5SAH

DMA5DAL

DMA5DAH

DMA5SZ

DMA channel 5 source address low

DMA channel 5 source address high

DMA channel 5 destination address low

DMA channel 5 destination address high

DMA channel 5 transfer size

Table 6-42. USCI_A0 Registers (Base Address: 05C0h)

REGISTER DESCRIPTION

REGISTER

UCA0CTL0

OFFSET

USCI control 0

00h

01h

06h

07h

08h

0Ah

0Ch

0Eh

10h

12h

13h

1Ch

1Dh

1Eh

USCI control 1

UCA0CTL1

UCA0BR0

USCI baud rate 0

USCI baud rate 1

UCA0BR1

USCI modulation control

USCI status

UCA0MCTL

UCA0STAT

UCA0RXBUF

UCA0TXBUF

UCA0ABCTL

UCA0IRTCTL

UCA0IRRCTL

UCA0IE

USCI receive buffer

USCI transmit buffer

USCI LIN control

USCI IrDA transmit control

USCI IrDA receive control

USCI interrupt enable

USCI interrupt flags

USCI interrupt vector word

UCA0IFG

UCA0IV

Table 6-43. USCI_B0 Registers (Base Address: 05E0h)

REGISTER DESCRIPTION

REGISTER

UCB0CTL0

OFFSET

USCI synchronous control 0

USCI synchronous control 1

USCI synchronous bit rate 0

USCI synchronous bit rate 1

USCI synchronous status

00h

01h

06h

07h

0Ah

0Ch

0Eh

10h

12h

1Ch

1Dh

1Eh

UCB0CTL1

UCB0BR0

UCB0BR1

UCB0STAT

UCB0RXBUF

UCB0TXBUF

UCB0I2COA

UCB0I2CSA

UCB0IE

USCI synchronous receive buffer

USCI synchronous transmit buffer

USCI I2C own address

USCI I2C slave address

USCI interrupt enable

USCI interrupt flags

UCB0IFG

USCI interrupt vector word

UCB0IV

Detailed Description

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Table 6-44. USCI_A1 Registers (Base Address: 0600h)

REGISTER DESCRIPTION

REGISTER

UCA1CTL0

OFFSET

USCI control 0

00h

01h

06h

07h

08h

0Ah

0Ch

0Eh

10h

12h

13h

1Ch

1Dh

1Eh

USCI control 1

UCA1CTL1

UCA1BR0

USCI baud rate 0

USCI baud rate 1

UCA1BR1

USCI modulation control

USCI status

UCA1MCTL

UCA1STAT

UCA1RXBUF

UCA1TXBUF

UCA1ABCTL

UCA1IRTCTL

UCA1IRRCTL

UCA1IE

USCI receive buffer

USCI transmit buffer

USCI LIN control

USCI IrDA transmit control

USCI IrDA receive control

USCI interrupt enable

USCI interrupt flags

USCI interrupt vector word

UCA1IFG

UCA1IV

Table 6-45. USCI_B1 Registers (Base Address: 0620h)

REGISTER DESCRIPTION

REGISTER

UCB1CTL0

OFFSET

USCI synchronous control 0

USCI synchronous control 1

USCI synchronous bit rate 0

USCI synchronous bit rate 1

USCI synchronous status

00h

01h

06h

07h

0Ah

0Ch

0Eh

10h

12h

1Ch

1Dh

1Eh

UCB1CTL1

UCB1BR0

UCB1BR1

UCB1STAT

UCB1RXBUF

UCB1TXBUF

UCB1I2COA

UCB1I2CSA

UCB1IE

USCI synchronous receive buffer

USCI synchronous transmit buffer

USCI I2C own address

USCI I2C slave address

USCI interrupt enable

USCI interrupt flags

UCB1IFG

USCI interrupt vector word

UCB1IV

Table 6-46. USCI_A2 Registers (Base Address: 0640h)

REGISTER DESCRIPTION

REGISTER

UCA2CTL0

OFFSET

USCI control 0

00h

01h

06h

07h

08h

0Ah

0Ch

0Eh

10h

12h

13h

1Ch

1Dh

1Eh

USCI control 1

UCA2CTL1

UCA2BR0

USCI baud rate 0

USCI baud rate 1

UCA2BR1

USCI modulation control

USCI status

UCA2MCTL

UCA2STAT

UCA2RXBUF

UCA2TXBUF

UCA2ABCTL

UCA2IRTCTL

UCA2IRRCTL

UCA2IE

USCI receive buffer

USCI transmit buffer

USCI LIN control

USCI IrDA transmit control

USCI IrDA receive control

USCI interrupt enable

USCI interrupt flags

USCI interrupt vector word

UCA2IFG

UCA2IV

82

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Table 6-47. USCI_B2 Registers (Base Address: 0660h)

REGISTER DESCRIPTION

REGISTER

UCB2CTL0

OFFSET

USCI synchronous control 0

USCI synchronous control 1

USCI synchronous bit rate 0

USCI synchronous bit rate 1

USCI synchronous status

00h

01h

06h

07h

0Ah

0Ch

0Eh

10h

12h

1Ch

1Dh

1Eh

UCB2CTL1

UCB2BR0

UCB2BR1

UCB2STAT

UCB2RXBUF

UCB2TXBUF

UCB2I2COA

UCB2I2CSA

UCB2IE

USCI synchronous receive buffer

USCI synchronous transmit buffer

USCI I2C own address

USCI I2C slave address

USCI interrupt enable

USCI interrupt flags

UCB2IFG

USCI interrupt vector word

UCB2IV

Table 6-48. ADC12_A Registers (Base Address: 0700h)

REGISTER DESCRIPTION

REGISTER

ADC12CTL0

OFFSET

ADC12 control 0

00h

02h

04h

0Ah

0Ch

0Eh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

22h

24h

26h

28h

2Ah

2Ch

2Eh

30h

32h

ADC12 control 1

ADC12CTL1

ADC12CTL2

ADC12IFG

ADC12 control 2

Interrupt flag

Interrupt enable

ADC12IE

Interrupt vector word

ADC memory control 0

ADC memory control 1

ADC memory control 2

ADC memory control 3

ADC memory control 4

ADC memory control 5

ADC memory control 6

ADC memory control 7

ADC memory control 8

ADC memory control 9

ADC memory control 10

ADC memory control 11

ADC memory control 12

ADC memory control 13

ADC memory control 14

ADC memory control 15

Conversion memory 0

Conversion memory 1

Conversion memory 2

Conversion memory 3

Conversion memory 4

Conversion memory 5

Conversion memory 6

Conversion memory 7

Conversion memory 8

Conversion memory 9

ADC12IV

ADC12MCTL0

ADC12MCTL1

ADC12MCTL2

ADC12MCTL3

ADC12MCTL4

ADC12MCTL5

ADC12MCTL6

ADC12MCTL7

ADC12MCTL8

ADC12MCTL9

ADC12MCTL10

ADC12MCTL11

ADC12MCTL12

ADC12MCTL13

ADC12MCTL14

ADC12MCTL15

ADC12MEM0

ADC12MEM1

ADC12MEM2

ADC12MEM3

ADC12MEM4

ADC12MEM5

ADC12MEM6

ADC12MEM7

ADC12MEM8

ADC12MEM9

Detailed Description

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Table 6-48. ADC12_A Registers (Base Address: 0700h) (continued)

REGISTER DESCRIPTION

REGISTER

ADC12MEM10

OFFSET

Conversion memory 10

Conversion memory 11

Conversion memory 12

Conversion memory 13

Conversion memory 14

Conversion memory 15

34h

36h

38h

3Ah

3Ch

3Eh

ADC12MEM11

ADC12MEM12

ADC12MEM13

ADC12MEM14

ADC12MEM15

Table 6-49. DAC12_A Registers (Base Address: 0780h)

REGISTER DESCRIPTION

REGISTER

DAC12_0CTL0

OFFSET

DAC12_A channel 0 control 0

DAC12_A channel 0 control 1

DAC12_A channel 0 data

00h

02h

04h

06h

08h

10h

12h

14h

16h

18h

1Eh

DAC12_0CTL1

DAC12_0DAT

DAC12_A channel 0 calibration control

DAC12_A channel 0 calibration data

DAC12_A channel 1 control 0

DAC12_A channel 1 control 1

DAC12_A channel 1 data

DAC12_0CALCTL

DAC12_0CALDAT

DAC12_1CTL0

DAC12_1CTL1

DAC12_1DAT

DAC12_A channel 1 calibration control

DAC12_A channel 1 calibration data

DAC12_A interrupt vector word

DAC12_1CALCTL

DAC12_1CALDAT

DAC12IV

Table 6-50. Comparator_B Registers (Base Address: 08C0h)

REGISTER DESCRIPTION

REGISTER

CBCTL0

OFFSET

Comp_B control 0

Comp_B control 1

Comp_B control 2

Comp_B control 3

Comp_B interrupt

00h

02h

04h

06h

0Ch

0Eh

CBCTL1

CBCTL2

CBCTL3

CBINT

Comp_B interrupt vector word

CBIV

Table 6-51. LDO and Port U Configuration Registers (Base Address: 0900h)

REGISTER DESCRIPTION

REGISTER

LDOKEYID

OFFSET

LDO key/ID

00h

04h

08h

PU port control

LDO power control

PUCTL

LDOPWRCTL

Table 6-52. LCD_B Registers (Base Address: 0A00h)

REGISTER DESCRIPTION

REGISTER

LCDBCTL0

OFFSET

LCD_B control 0

000h

002h

004h

006h

008h

00Ah

00Ch

00Eh

LCD_B control 1

LCDBCTL1

LCD_B blinking control

LCD_B memory control

LCD_B voltage control

LCD_B port control 0

LCD_B port control 1

LCD_B port control 2

LCDBBLKCTL

LCDBMEMCTL

LCDBVCTL

LCDBPCTL0

LCDBPCTL1

LCDBPCTL2

84

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Table 6-52. LCD_B Registers (Base Address: 0A00h) (continued)

REGISTER DESCRIPTION

REGISTER

LCDBCTL0

OFFSET

LCD_B charge pump control

LCD_B interrupt vector word

LCD_B memory 1

LCD_B memory 2

⋮

012h

01Eh

020h

021h

⋮

LCDBIV

LCDM1

LCDM2

⋮

LCD_B memory 22

LCD_B blinking memory 1

LCD_B blinking memory 2

⋮

LCDM22

LCDBM1

LCDBM2

⋮

035h

040h

041h

⋮

LCD_B blinking memory 22

LCDBM22

055h

Detailed Description

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6.14 Input/Output Schematics

6.14.1 Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger

Figure 6-2 shows the port schematic. summarizes selection of the pin function.

Pad Logic

S32...S39

LCDS32...LCDS39

P1REN.x

P1DIR.x

DV_SS

DV_CC

0

1

0

1

Direction

0: Input

1: Output

P1OUT.x

0

1

Module X OUT

P1.0/TA0CLK/ACLK/S39

P1.1/TA0.0/S38

P1.2/TA0.1/S37

P1.3/TA0.2/S36

P1.4/TA0.3/S35

P1.5/TA0.4/S34

P1.6/TA0.1/S33

P1.7/TA0.2/S32

P1DS.x

0: Low drive

1: High drive

P1SEL.x

P1IN.x

Bus

Keeper

EN

D

Module X IN

P1IRQ.x

P1IE.x

EN

Q

P1IFG.x

Set

P1SEL.x

P1IES.x

Interrupt

Edge

Select

Figure 6-2. Port P1 (P1.0 to P1.7) Schematic

86

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Port P1 (P1.0 to P1.7) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P1.x)

x

FUNCTION

P1DIR.x

P1SEL.x

LCDS32...39

P1.0 (I/O)

Timer TA0.TA0CLK

ACLK

I: 0; O: 1

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

P1.0/TA0CLK/ACLK/

S39

0

1

S39

X

P1.1 (I/O)

I: 0; O: 1

Timer TA0.CCI0A capture input

Timer TA0.0 output

S38

0

P1.1/TA0.0/S38

P1.2/TA0.1/S37

P1.3/TA0.2/S36

P1.4/TA0.3/S35

P1.5/TA0.4/S34

P1.6/TA0.1/S33

1

2

3

4

5

6

7

1

X

P1.2 (I/O)

I: 0; O: 1

Timer TA0.CCI1A capture input

Timer TA0.1 output

S37

0

1

X

P1.3 (I/O)

I: 0; O: 1

Timer TA0.CCI2A capture input

Timer TA0.2 output

S36

0

1

X

P1.4 (I/O)

I: 0; O: 1

Timer TA0.CCI3A capture input

Timer TA0.3 output

S35

0

1

X

P1.5 (I/O)

I: 0; O: 1

Timer TA0.CCI4A capture input

Timer TA0.4 output

S34

0

1

X

P1.6 (I/O)

I: 0; O: 1

Timer TA0.CCI1B capture input

Timer TA0.1 output

S33

0

1

X

P1.7 (I/O)

I: 0; O: 1

Timer TA0.CCI2B capture input

Timer TA0.2 output

S32

0

1

P1.7/TA0.2/S32

X

(1) X = Don't care

Detailed Description

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6.14.2 Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger

Figure 6-3 shows the port schematic. summarizes selection of the pin function.

Pad Logic

To LCD_B

From LCD_B

P2REN.x

DV_SS

DV_CC

0

1

P2DIR.x

0

1

Direction

0: Input

1: Output

From Port Mapping

P2OUT.x

0

1

From Port Mapping

P2.0/P2MAP0

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2DS.x

0: Low drive

1: High drive

P2SEL.x

P2.4/P2MAP4

P2.5/P2MAP5

P2IN.x

P2.6/P2MAP6/R03

P2.7/P2MAP7/LCDREF/R13

From Port Mapping

EN

D

To Port Mapping

P2IRQ.x

P2IE.x

EN

Q

P2IFG.x

Set

P2SEL.x

P2IES.x

Interrupt

Edge

Select

Figure 6-3. Port P2 (P2.0 to P2.7) Schematic

88

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Port P2 (P2.0 to P2.7) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P2.x)

P2.0/P2MAP0

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

x

0

1

2

3

4

5

FUNCTION

P2DIR.x

P2SEL.x

P2MAPx

P2.0 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Mapped secondary digital function

P2.1 (I/O)

X

≤ 19

I: 0; O: 1

Mapped secondary digital function

P2.2 (I/O)

X

I: 0; O: 1

Mapped secondary digital function

P2.3 (I/O)

X

I: 0; O: 1

Mapped secondary digital function

P2.4 (I/O)

X

I: 0; O: 1

Mapped secondary digital function

P2.5 (I/O

X

I: 0; O: 1

Mapped secondary digital function

P2.6 (I/O)

X

I: 0; O: 1

P2.6/P2MAP6/R03

6

7

Mapped secondary digital function

R03

X

≤ 19

X

= 31

P2.7 (I/O)

I: 0; O: 1

P2.7/P2MAP7/

LCDREF/R13

Mapped secondary digital function

LCDREF/R13

X

≤ 19

= 31

(1) X = Don't care

Detailed Description

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6.14.3 Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger

Figure 6-4 shows the port schematic. summarizes selection of the pin function.

Pad Logic

S24...S31

LCDS24...LCDS31

P3REN.x

P3DIR.x

DV_SS

DV_CC

0

1

0

1

Direction

0: Input

1: Output

P3OUT.x

0

1

Module X OUT

P3.0/TA1CLK/CBOUT/S31

P3.1/TA1.0/S30

P3.2/TA1.1/S29

P3DS.x

0: Low drive

1: High drive

P3SEL.x

P3IN.x

P3.3/TA1.2/S28

P3.4/TA2CLK/SMCLK/S27

P3.5/TA2.0/S26

P3.6/TA2.1/S25

Bus

Keeper

EN

D

P3.7/TA2.2/S24

Module X IN

P3IRQ.x

P3IE.x

EN

Q

P3IFG.x

Set

P3SEL.x

P3IES.x

Interrupt

Edge

Select

Figure 6-4. Port P3 (P3.0 to P3.7) Schematic

90

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Port P3 (P3.0 to P3.7) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P3.x)

x

FUNCTION

P3DIR.x

P3SEL.x

LCDS24...31

P3.0 (I/O)

Timer TA1.TA1CLK

CBOUT

I: 0; O: 1

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

P3.0/TA1CLK/CBOUT/

S31

0

1

S31

X

P3.1 (I/O)

I: 0; O: 1

Timer TA1.CCI0A capture input

0

P3.1/TA1.0/S30

P3.2/TA1.1/S29

P3.3/TA1.2/S28

1

2

3

4

5

6

7

Timer TA1.0 output

1

S30

X

P3.2 (I/O)

I: 0; O: 1

Timer TA1.CCI1A capture input

0

Timer TA1.1 output

1

S29

X

P3.3 (I/O)

I: 0; O: 1

Timer TA1.CCI2A capture input

0

Timer TA1.2 output

1

S28

X

P3.4 (I/O)

I: 0; O: 1

Timer TA2.TA2CLK

0

P3.4/TA2CLK/SMCLK/

S27

SMCLK

1

S27

X

P3.5 (I/O)

I: 0; O: 1

Timer TA2.CCI0A capture input

Timer TA2.0 output

S26

0

P3.5/TA2.0/S26

P3.6/TA2.1/S25

1

X

P3.6 (I/O)

I: 0; O: 1

Timer TA2.CCI1A capture input

Timer TA2.1 output

S25

0

1

X

P3.7 (I/O)

I: 0; O: 1

Timer TA2.CCI2A capture input

Timer TA2.2 output

S24

0

1

P3.7/TA2.2/S24

X

(1) X = Don't care

Detailed Description

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6.14.4 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger

Figure 6-5 shows the port schematic. summarizes selection of the pin function.

Pad Logic

S16...S23

LCDS16...LCDS23

P4REN.x

DV_SS

DV_CC

0

1

P4DIR.x

0

1

Direction

0: Input

1: Output

P4OUT.x

0

1

Module X OUT

P4.0/TB0.0/S23

P4.1/TB0.1/S22

P4.2/TB0.2/S21

P4.3/TB0.3/S20

P4.4/TB0.4/S19

P4.5/TB0.5/S18

P4DS.x

0: Low drive

1: High drive

P4SEL.x

P4IN.x

P4.6/TB0.6/S17

P4.7/TB0OUTH/SVMOUT/S16

Bus

Keeper

EN

D

Module X IN

P4IRQ.x

P4IE.x

EN

Q

P4IFG.x

Set

P4SEL.x

P4IES.x

Interrupt

Edge

Select

Figure 6-5. Port P4 (P4.0 to P4.7) Schematic

92

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Port P4 (P4.0 to P4.7) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P4.x)

x

FUNCTION

P4DIR.x

P4SEL.x

LCDS16...23

P4.0 (I/O)

I: 0; O: 1

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Timer TB0.CCI0A capture input

Timer TB0.0 output⁽²⁾

S23

0

P4.0/TB0.0/S23

0

1

X

P4.1 (I/O)

I: 0; O: 1

Timer TB0.CCI1A capture input

Timer TB0.1 output⁽²⁾

S22

0

P4.1/TB0.1/S22

P4.2/TB0.2/S21

P4.3/TB0.3/S20

P4.4/TB0.4/S19

P4.5/TB0.5/S18

P4.6/TB0.6/S17

1

2

3

4

5

6

7

1

X

P4.2 (I/O)

I: 0; O: 1

Timer TB0.CCI2A capture input

Timer TB0.2 output⁽²⁾

S21

0

1

X

P4.3 (I/O)

I: 0; O: 1

Timer TB0.CCI3A capture input

Timer TB0.3 output⁽²⁾

S20

0

1

X

P4.4 (I/O)

I: 0; O: 1

Timer TB0.CCI4A capture input

Timer TB0.4 output⁽²⁾

S19

0

1

X

P4.5 (I/O)

I: 0; O: 1

Timer TB0.CCI5A capture input

Timer TB0.5 output⁽²⁾

S18

0

1

X

P4.6 (I/O)

I: 0; O: 1

Timer TB0.CCI6A capture input

Timer TB0.6 output⁽²⁾

S17

0

1

X

P4.7 (I/O)

I: 0; O: 1

Timer TB0.TB0OUTH

SVMOUT

0

1

P4.7/TB0OUTH/

SVMOUT/S16

S16

X

(1) X = Don't care

(2) Setting TB0OUTH causes all Timer_B configured outputs to be set to high impedance.

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Detailed Description

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6.14.5 Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger

Figure 6-6 shows the port schematic. summarizes selection of the pin function.

Pad Logic

To/From

Reference

P5REN.x

DV_SS

DV_CC

0

1

P5DIR.x

0

1

P5OUT.x

0

1

Module X OUT

P5.0/VREF+/VeREF+

P5.1/VREF–/VeREF–

P5DS.x

0: Low drive

1: High drive

P5SEL.x

P5IN.x

Bus

Keeper

EN

D

Module X IN

Figure 6-6. Port P5 (P5.0 and P5.1) Schematic

Port P5 (P5.0 and P5.1) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P5.x)

x

FUNCTION

P5DIR.x

P5SEL.x

REFOUT

P5.0 (I/O)⁽²⁾

VeREF+⁽³⁾

VREF+⁽⁴⁾

P5.1 (I/O)⁽²⁾

VeREF–⁽⁵⁾

VREF–⁽⁶⁾

I: 0; O: 1

0

1

0

1

X

0

1

X

0

1

P5.0/VREF+/VeREF+

P5.1/VREF–/VeREF–

0

X

I: 0; O: 1

1

X

(1) X = Don't care

(2) Default condition

(3) Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog

signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A, Comparator_B, or DAC12_A.

(4) Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog

signals. The ADC12_A, VREF+ reference is available at the pin.

(5) Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog

signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A, Comparator_B, or DAC12_A.

(6) Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog

signals. The ADC12_A, VREF– reference is available at the pin.

94

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6.14.6 Port P5, P5.2 to P5.7, Input/Output With Schmitt Trigger

Figure 6-7 shows the port schematic. summarizes selection of the pin function.

Pad Logic

S40...S42

LCDS40...LCDS42

P5REN.x

P5DIR.x

DV_SS

DV_CC

0

1

0

1

Direction

0: Input

1: Output

P5OUT.x

0

1

Module X OUT

P5.2/R23

P5DS.x

0: Low drive

1: High drive

P5.3/COM1/S42

P5.4/COM2/S41

P5.5/COM3/S40

P5.6/ADC12CLK/DMAE0

P5.7/RTCCLK

P5SEL.x

P5IN.x

Bus

Keeper

EN

D

Module X IN

Figure 6-7. Port P5 (P5.2 to P5.7) Schematic

Port P5 (P5.2 to P5.7) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P5.x)

x

FUNCTION

P5DIR.x

P5SEL.x

LCDS40...42

P5.2 (I/O)

R23

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

N/A

0

P5.2/R23

2

X

P5.3 (I/O)

COM1

I: 0; O: 1

P5.3/COM1/S42

3

4

5

X

S42

X

1

P5.4 (I/O)

COM2

I: 0; O: 1

0

P5.4/COM2/S41

X

S41

X

1

P5.5 (I/O)

COM3

I: 0; O: 1

0

P5.5/COM3/S40

X

S40

X

1

P5.6 (I/O)

ADC12CLK

DMAE0

P5.7 (I/O)

RTCCLK

I: 0; O: 1

N/A

P5.6/ADC12CLK/DMAE0

6

7

1

0

I: 0; O: 1

1

P5.7/RTCCLK

(1) X = Don't care

Detailed Description

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6.14.7 Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger

Figure 6-8 shows the port schematic. summarizes selection of the pin function.

Pad Logic

To ADC12

INCHx = y

0

Dvss

1

2

0 if DAC12AMPx=0

1 if DAC12AMPx=1

2 if DAC12AMPx>1

From DAC12_A

To Comparator_B

From Comparator_B

CBPD.x

DAC12AMPx>0

DAC12OPS

P6REN.x

DV_SS

DV_CC

0

1

P6DIR.x

P6OUT.x

P6.0/CB0/A0

P6.1/CB1/A1

P6.2/CB2/A2

P6.3/CB3/A3

P6.4/CB4/A4

P6.5/CB5/A5

P6DS.x

0: Low drive

1: High drive

P6SEL.x

P6IN.x

P6.6/CB6/A6/DAC0

P6.7/CB7/A7/DAC1

Bus

Keeper

Figure 6-8. Port P6 (P6.0 to P6.7) Schematic

96

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Port P6 (P6.0 to P6.7) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P6.x)

x

FUNCTION

P6DIR.x

P6SEL.x

CBPD.x

DAC12OPS

N/A

X

DAC12AMPx

N/A

0

P6.0 (I/O)

CB0

A0⁽²⁾⁽³⁾

P6.1 (I/O)

CB1

A1⁽²⁾⁽³⁾

P6.2 (I/O)

CB2

A2⁽²⁾⁽³⁾

P6.3 (I/O)

CB3

A3⁽²⁾⁽³⁾

P6.4 (I/O)

CB4

A4⁽²⁾⁽³⁾

P6.5 (I/O)

CB5

A5⁽²⁾⁽³⁾

P6.6 (I/O)

CB6

I: 0; O: 1

0

X

1

0

X

1

0

X

1

0

X

1

0

X

1

0

X

1

0

X

1

X

0

X

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

P6.0/CB0/A0

0

X

I: 0; O: 1

P6.1/CB1/A1

P6.2/CB2/A2

P6.3/CB3/A3

P6.4/CB4/A4

P6.5/CB5/A5

1

2

3

4

5

X

I: 0; O: 1

X

I: 0; O: 1

X

I: 0; O: 1

X

I: 0; O: 1

X

I: 0; O: 1

X

0

P6.6/CB6/A6/DAC0

6

7

A6⁽²⁾⁽³⁾

X

0

DAC0

X

0

>1

P6.7 (I/O)

CB7

A7⁽²⁾⁽³⁾

I: 0; O: 1

X

0

X

0

P6.7/CB7/A7/DAC1

(1) X = Don't care

X

0

DAC1

0

>1

(2) Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog

signals.

(3) The ADC12_A channel Ax is connected internally to AV_SSif not selected by the respective INCHx bits.

Detailed Description

97

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6.14.8 Port P7, P7.2, Input/Output With Schmitt Trigger

Figure 6-9 shows the port schematic. summarizes selection of the pin function.

Pad Logic

To XT2

P7REN.2

DV_SS

DV_CC

0

1

P7DIR.2

P7OUT.2

0

1

P7.2/XT2IN

P7DS.2

0: Low drive

1: High drive

P7SEL.2

P7IN.2

Bus

Keeper

Figure 6-9. Port P7 (P7.2) Schematic

98

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6.14.9 Port P7, P7.3, Input/Output With Schmitt Trigger

Figure 6-10 shows the port schematic. summarizes selection of the pin function.

Pad Logic

To XT2

P7REN.3

DV_SS

DV_CC

0

1

P7DIR.3

0

1

P7OUT.3

P7SEL.2

P7.3/XT2OUT

P7DS.3

0: Low drive

1: High drive

XT2BYPASS

P7SEL.3

P7IN.3

Bus

Keeper

Figure 6-10. Port P7 (P7.3) Schematic

Port P7 (P7.2 and P7.3) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P5.x)

x

FUNCTION

P7DIR.x

P7SEL.2

P7SEL.3

XT2BYPASS

P7.2 (I/O)

I: 0; O: 1

0

1

0

1

X

0

X

0

1

X

0

1

P7.2/XT2IN

2

XT2IN crystal mode⁽²⁾

XT2IN bypass mode⁽²⁾

P7.3 (I/O)

XT2OUT crystal mode⁽³⁾

P7.3 (I/O)⁽³⁾

X

I: 0; O: 1

P7.3/XT2OUT

3

X

0

(1) X = Don't care

(2) Setting P7SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P7.2 is configured for crystal

mode or bypass mode.

(3) Setting P7SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.3 can be used as

general-purpose I/O.

Detailed Description

99

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6.14.10 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger

Figure 6-11 shows the port schematic. summarizes selection of the pin function.

0

Pad Logic

Dvss

1

2

0 if DAC12AMPx = 0

1 if DAC12AMPx = 1

2 if DAC12AMPx > 1

From DAC12_A

To ADC12

INCHx = y

To Comparator_B

From Comparator_B

CBPD.x

DAC12AMPx>0

DAC12OPS

P7REN.x

DV_SS

DV_CC

0

1

P7DIR.x

P7OUT.x

P7.4/CB8/A12

P7.5/CB9/A13

P7.6/CB10/A14/DAC0

P7.7/CB11/A15/DAC1

P7DS.x

0: Low drive

1: High drive

P7SEL.x

P7IN.x

Bus

Keeper

Figure 6-11. Port P7 (P7.4 to P7.7) Schematic

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Port P7 (P7.4 to P7.7) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P7.x)

x

FUNCTION

P7DIR.x

P7SEL.x

CBPD.x

DAC12OPS

DAC12AMPx

P7.4 (I/O)

I: 0; O: 1

0

X

1

0

X

1

0

X

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

X

N/A

X

N/A

0

P7.4/CB8/A12

4

Comparator_B input CB8

A12⁽²⁾⁽³⁾

X

P7.5 (I/O)

I: 0; O: 1

P7.5/CB9/A13

5

6

7

Comparator_B input CB9

A13⁽²⁾⁽³⁾

X

P7.6 (I/O)

I: 0; O: 1

Comparator_B input CB10

A14⁽²⁾⁽³⁾

X

0

P7.6/CB10/A14/DAC0

X

0

DAC12_A output DAC0

P7.7 (I/O)

A15⁽²⁾⁽³⁾

X

1

>1

0

I: 0; O: 1

X

P7.7/CB11/A15/DAC1

(1) X = Don't care

X

0

DAC12_A output DAC1

1

>1

(2) Setting the P7SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog

signals.

(3) The ADC12_A channel Ax is connected internally to AV_SSif not selected by the respective INCHx bits.

Detailed Description

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6.14.11 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger

Figure 6-12 shows the port schematic. summarizes selection of the pin function.

Pad Logic

S8...S15

LCDS8...LCDS15

P8REN.x

DV_SS

DV_CC

0

1

P8DIR.x

0

1

Direction

0: Input

1: Output

From module

0

1

P8OUT.x

Module X OUT

P8.0/TB0CLK/S15

P8DS.x

0: Low drive

1: High drive

P8.1/UCB1STE/UCA1CLK/S14

P8.2/UCA1TXD/UCA1SIMO/S13

P8.3/UCA1RXD/UCA1SOMI/S12

P8.4/UCB1CLK/UCA1STE/S11

P8.5/UCB1SIMO//UCB1SDA/S10

P8.6/UCB1SOMI/UCB1SCL/S9

P8.7/S8

P8SEL.x

P8IN.x

Bus

Keeper

EN

D

Module X IN

Figure 6-12. Port P8 (P8.0 to P8.7) Schematic

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Port P8 (P8.0 to P8.7) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P9.x)

x

FUNCTION

P8DIR.x

P8SEL.x

LCDS8...15

P8.0 (I/O)

I: 0; O: 1

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

P8.0/TB0CLK/S15

0

Timer TB0.TB0CLK clock input

0

S15

X

P8.1 (I/O)

I: 0; O: 1

P8.1/UCB1STE/UCA1CLK/S14

P8.2/UCA1TXD/UCA1SIMO/S13

P8.3/UCA1RXD/UCA1SOMI/S12

P8.4/UCB1CLK/UCA1STE/S11

P8.5/UCB1SIMO/UCB1SDA/S10

P8.6/UCB1SOMI/UCB1SCL/S9

1

2

3

4

5

UCB1STE/UCA1CLK

X

S14

X

P8.2 (I/O)

I: 0; O: 1

UCA1TXD/UCA1SIMO

X

S13

X

P8.3 (I/O)

I: 0; O: 1

UCA1RXD/UCA1SOMI

X

S12

X

P8.4 (I/O)

I: 0; O: 1

UCB1CLK/UCA1STE

X

S11

X

P8.5 (I/O)

I: 0; O: 1

UCB1SIMO/UCB1SDA

X

S10

X

P8.6 (I/O)

I: 0; O: 1

6

7

UCB1SOMI/UCB1SCL

X

S9

X

I: 0; O: 1

X

P8.7 (I/O)

S8

P8.7/S8

(1) X = Don't care

Detailed Description

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6.14.12 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger

Figure 6-13 shows the port schematic. summarizes selection of the pin function.

Pad Logic

S0...S7

LCDS0...LCDS7

P9REN.x

DV_SS

DV_CC

0

1

P9DIR.x

0

1

Direction

0: Input

1: Output

From module

0

1

P9OUT.x

Module X OUT

P9.0/S7

P9DS.x

0: Low drive

1: High drive

P9.1/UCB2STE/UCA2CLK/S6

P9.2/UCA2TXD/UCA2SIMO/S5

P9.3/UCA2RXD/UCA2SOMI/S4

P9.4/UCB2CLK/UCA2STE/S3

P9.5/UCB2SIMO//UCB2SDA/S2

P9.6/UCB2SOMI/UCB2SCL/S1

P9.7/S0

P9SEL.x

P9IN.x

Bus

Keeper

EN

D

Module X IN

Figure 6-13. Port P9 (P9.0 to P9.7) Schematic

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Port P9 (P9.0 to P9.7) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P9.x)

x

FUNCTION

P9DIR.x

P9SEL.x

LCDS0...7

P9.0 (I/O)

S7

I: 0; O: 1

0

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

P9.0/S7

0

X

P9.1 (I/O)

I: 0; O: 1

P9.1/UCB2STE/UCA2CLK/S6

1

2

3

4

5

UCB2STE/UCA2CLK

X

S6

X

P9.2 (I/O)

I: 0; O: 1

P9.2/UCA2TXD/UCA2SIMO/S5

P9.3/UCA2RXD/UCA2SOMI/S4

P9.4/UCB2CLK/UCA2STE/S3

P9.5/UCB2SIMO/UCB2SDA/S2

P9.6/UCB2SOMI/UCB2SCLK/S1

UCA2TXD/UCA2SIMO

X

S5

X

P9.3 (I/O)

I: 0; O: 1

UCA2RXD/UCA2SOMI

X

S4

X

P9.4 (I/O)

I: 0; O: 1

UCB2CLK/UCA2STE

X

S3

X

P9.5 (I/O)

I: 0; O: 1

UCB2SIMO/UCB2SDA

X

S2

X

P9.6 (I/O)

I: 0; O: 1

6

7

UCB2SOMI/UCB2SCLK

X

S1

X

I: 0; O: 1

X

P9.7 (I/O)

S0

P9.7/S0

(1) X = Don't care

Detailed Description

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6.14.13 Port PU.0, PU.1 Ports

Figure 6-14 shows the port schematic. Table 6-53 summarizes selection of the pin function.

LDOO

VSSU

Pad Logic

PUOPE

PU.0

PUOUT0

PUIN0

PUIPE

PUIN1

PUOUT1

PU.1

Figure 6-14. Port U (PU.0 and PU.1) Schematic

Table 6-53. Port PU.0, PU.1 Functions⁽¹⁾

PUIPE

PUOPE

PUOUT1

PUOUT0

PU.1

PU.0

PORT U FUNCTION

0

1

0

1

0

1

X

0

1

0

1

X

Output low

Output high

Input enabled

Hi-Z

Output low

Output high

Output low

Output high

Input enabled

Hi-Z

Outputs enabled

Inputs enabled

Outputs and inputs disabled

(1) PU.1 and PU.0 inputs and outputs are supplied from LDOO. LDOO can be generated by the device using the integrated 3.3-V LDO

when enabled. LDOO can also be supplied externally when the 3.3-V LDO is not being used and is disabled.

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6.14.14 Port J, PJ.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output

Figure 6-15 shows the port schematic. summarizes selection of the pin function.

Pad Logic

PJREN.0

0

1

DV_SS

DV_CC

1

PJDIR.0

DVCC

0

1

PJOUT.0

0

1

From JTAG

PJ.0/TDO

PJDS.0

0: Low drive

1: High drive

From JTAG

PJIN.0

EN

D

Figure 6-15. Port PJ (PJ.0) Schematic

Detailed Description

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6.14.15 Port J, PJ.1 to PJ.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt

Trigger or Output

Figure 6-16 shows the port schematic. summarizes selection of the pin function.

Pad Logic

PJREN.x

0

1

DV_SS

DV_CC

1

PJDIR.x

DVSS

0

1

PJOUT.x

0

1

From JTAG

PJ.1/TDI/TCLK

PJ.2/TMS

PJ.3/TCK

PJDS.x

0: Low drive

1: High drive

From JTAG

PJIN.x

EN

D

To JTAG

Figure 6-16. Port PJ (PJ.1 to PJ.3) Schematic

Port PJ (PJ.0 to PJ.3) Pin Functions

FUNCTION

CONTROL BITS OR

SIGNALS⁽¹⁾

PIN NAME (PJ.x)

x

PJDIR.x

PJ.0 (I/O)⁽²⁾

TDO⁽³⁾

I: 0; O: 1

PJ.0/TDO

0

1

2

3

X

PJ.1 (I/O)⁽²⁾

TDI/TCLK^{(3) (4)}

PJ.2 (I/O)⁽²⁾

TMS^{(3) (4)}

PJ.3 (I/O)⁽²⁾

TCK^{(3) (4)}

I: 0; O: 1

PJ.1/TDI/TCLK

PJ.2/TMS

X

I: 0; O: 1

X

I: 0; O: 1

X

PJ.3/TCK

(1) X = Don't care

(2) Default condition

(3) The pin direction is controlled by the JTAG module.

(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.

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6.15 Device Descriptors

Table 6-54 lists the contents of the device descriptor tag-length-value (TLV) structure for each device type.

Table 6-54. Device Descriptor Table⁽¹⁾

VALUE

SIZE

(bytes)

DESCRIPTION

Info length

ADDRESS

F6659

06h

F6658

06h

F6459

06h

F6458

06h

F5659

06h

F5658

06h

F5359

06h

F5358

06h

01A00h

01A01h

01A02h

01A04h

01A06h

01A07h

01A08h

01A09h

01A0Ah

01A0Eh

01A10h

01A12h

01A14h

01A15h

01A16h

01A18h

1

2

1

4

2

1

2

CRC length

CRC value

06h

per unit per unit per unit per unit

Info Block

Device ID

812Bh

10h

812Ch

10h

812Dh

10h

812Eh

10h

8130h

10h

8131h

10h

8132h

10h

8133h

10h

Hardware revision

Firmware revision

Die record tag

Die record length

Lot/wafer ID

10h

08h

0Ah

per unit per unit per unit per unit

Die Record

Die X position

Die Y position

Test results

ADC12 calibration tag

ADC12 calibration length

ADC gain factor

ADC offset

11h

10h

11h

10h

11h

10h

11h

10h

11h

10h

11h

10h

11h

10h

11h

10h

per unit per unit per unit per unit

ADC 1.5-V reference

temperature sensor 30°C

01A1Ah

01A1Ch

01A1Eh

01A20h

01A22h

01A24h

2

per unit per unit per unit per unit

ADC 1.5-V reference

temperature sensor 105°C

ADC12

Calibration

ADC 2.0-V reference

temperature sensor 30°C

ADC 2.0-V reference

temperature sensor 105°C

ADC 2.5-V reference

temperature sensor 30°C

ADC 2.5-V reference

temperature sensor 105°C

REF calibration tag

01A26h

01A27h

1

12h

06h

12h

06h

12h

06h

12h

06h

12h

06h

12h

06h

12h

06h

12h

06h

REF calibration length

REF 1.5-V

reference factor

01A28h

01A2Ah

01A2Ch

2

per unit per unit per unit per unit

REF Calibration

REF 2.0-V

reference factor

REF 2.5-V

reference factor

(1) N/A = Not applicable

Detailed Description

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7 Applications, Implementation, and Layout

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

7.1 Device Connection and Layout Fundamentals

This section discusses the recommended guidelines when designing with the MSP430. These guidelines

are to make sure that the device has proper connections for powering, programming, debugging, and

optimum analog performance.

7.1.1 Power Supply Decoupling and Bulk Capacitors

TI recommends connecting a combination of a 1-µF plus a 100-nF low-ESR ceramic decoupling capacitor

to each AVCC and DVCC pin. Higher-value capacitors may be used but can impact supply rail ramp-up

time. Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a

few millimeters). Additionally, separated grounds with a single-point connection are recommend for better

noise isolation from digital to analog circuits on the board and are especially recommended to achieve

high analog accuracy.

DVCC

Digital

Power Supply

Decoupling

+

DVSS

1 µF

100 nF

AVCC

Analog

Power Supply

Decoupling

+

AVSS

1 µF

100 nF

Figure 7-1. Power Supply Decoupling

7.1.2 External Oscillator

Depending on the device variant (see Table 3-1), the device can support a low-frequency crystal (32 kHz)

on the LFXT pins, a high-frequency crystal on the HFXT pins, or both. External bypass capacitors for the

crystal oscillator pins are required.

It is also possible to apply digital clock signals to the LFXIN and HFXIN input pins that meet the

specifications of the respective oscillator if the appropriate LFXTBYPASS or HFXTBYPASS mode is

selected. In this case, the associated LFXOUT and HFXOUT pins can be used for other purposes.

Figure 7-2 shows a typical connection diagram.

110

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LFXIN

or

LFXOUT

or

HFXIN

HFXOUT

C_L1

C_L2

Figure 7-2. Typical Crystal Connection

See the application report MSP430 32-kHz Crystal Oscillators (SLAA322) for more information on

selecting, testing, and designing a crystal oscillator with the MSP430 devices.

7.1.3 JTAG

With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or

MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the

connections also support the MSP-GANG production programmers, thus providing an easy way to

program prototype boards, if desired. Figure 7-3 shows the connections between the 14-pin JTAG

connector and the target device required to support in-system programming and debugging for 4-wire

JTAG communication. Figure 7-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).

The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are

identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSP-

FET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an

alternate connection (pin 4 instead of pin 2). The VCC-sense feature senses the local VCC present on the

target board (that is, a battery or other local power supply) and adjusts the output signals accordingly.

Figure 7-3 and Figure 7-4 show a jumper block that supports both scenarios of supplying VCC to the

target board. If this flexibility is not required, the desired VCC connections may be hard-wired to eliminate

the jumper block. Pins 2 and 4 must not be connected at the same time.

For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User's

Guide (SLAU278).

Applications, Implementation, and Layout

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V_CC

Important to connect

MSP430F6459

J1 (see Note A)

J2 (see Note A)

AVCC/DVCC

R1

47 kW

JTAG

RST/NMI/SBWTDIO

VCC TOOL

TDO/TDI

TDI

2

1

3

VCC TARGET

TDI

4

TMS

TCK

TMS

6

5

TEST

8

7

TCK

GND

RST

10

12

14

9

11

13

TEST/SBWTCK

AVSS/DVSS

C1

2.2 nF

(see Note B)

A. If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,

make connection J2.

B. The upper limit for C1 is 2.2 nF when using current TI tools.

Figure 7-3. Signal Connections for 4-Wire JTAG Communication

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V_CC

Important to connect

MSP430F6459

AVCC/DVCC

J1 (see Note A)

J2 (see Note A)

R1

47 kΩ

(See Note B)

JTAG

VCC TOOL

VCC TARGET

TDO/TDI

2

1

3

5

7

9

RST/NMI/SBWTDIO

4

6

TCK

GND

8

10

12

14

11

13

TEST/SBWTCK

AVSS/DVSS

C1

2.2 nF

(See Note B)

A. Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the

debug or programming adapter.

B. The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during

JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with

the device. The upper limit for C1 is 2.2 nF when using current TI tools.

Figure 7-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)

7.1.4 Reset

The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function

Register (SFR), SFRRPCR.

In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing

specifications generates a BOR-type device reset.

Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is

edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the

external NMI. When an external NMI event occurs, the NMIIFG is set.

The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either

pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.

If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an

external 47-kΩ pullup resistor to the RST/NMI pin with a 2.2-nF pulldown capacitor. The pulldown

capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or

in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers.

See the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) for more information on the

referenced control registers and bits.

Applications, Implementation, and Layout

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7.1.5 General Layout Recommendations

•

Proper grounding and short traces for external crystal to reduce parasitic capacitance. See the

application report MSP430 32-kHz Crystal Oscillators (SLAA322) for recommended layout guidelines.

•

Proper bypass capacitors on DVCC, AVCC, and reference pins if used.

Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital

switching signals such as PWM or JTAG signals away from the oscillator circuit.

•

Refer to the Circuit Board Layout Techniques design guide (SLOA089) for a detailed discussion of

PCB layout considerations. This document is written primarily about op amps, but the guidelines are

generally applicable for all mixed-signal applications.

Proper ESD level protection should be considered to protect the device from unintended high-voltage

electrostatic discharge. See the application report MSP430 System-Level ESD Considerations

(SLAA530) for guidelines.

7.1.6 Do's and Don'ts

TI recommends powering the AVCC and DVCC pins from the same source. At a minimum, during power

up, power down, and device operation, the voltage difference between AVCC and DVCC must not exceed

the limits specified in the Absolute Maximum Ratings section. Exceeding the specified limits may cause

malfunction of the device including erroneous writes to RAM and FRAM.

7.2 Peripheral- and Interface-Specific Design Information

7.2.1 ADC12_B Peripheral

7.2.1.1 Partial Schematic

AVSS

VREF+/VEREF+

Using an

External

Positive

Reference

+

4.7 µF

10 µF

VEREF-

Using an

External

+

Negative

Reference

10 µF

4.7 µF

Figure 7-5. ADC12_B Grounding and Noise Considerations

7.2.1.2 Design Requirements

As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should

be followed to eliminate ground loops, unwanted parasitic effects, and noise.

Ground loops are formed when return current from the ADC flows through paths that are common with

other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset

voltages that can add to or subtract from the reference or input voltages of the ADC. The general

guidelines in Section 7.1.1 combined with the connections shown in Section 7.2.1.1 prevent this.

In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital

switching or switching power supplies can corrupt the conversion result. A noise-free design using

separate analog and digital ground planes with a single-point connection is recommend to achieve high

accuracy.

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Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used. The

internal reference module has a maximum drive current as specified in the Reference module's I_O(VREF+)

specification.

The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are

selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage

enters the device. In this case, the 10-µF capacitor is used to buffer the reference pin and filter any low-

frequency ripple. A bypass capacitor of 4.7 µF is used to filter out any high frequency noise.

7.2.1.3 Detailed Design Procedure

For additional design information, see the ADC12_A section in the application report MSP430x5xx and

MSP430x6xx Family User's Guide (SLAU208).

7.2.1.4 Layout Guidelines

Component that are shown in the partial schematic (see Figure 7-5) should be placed as close as possible

to the respective device pins. Avoid long traces, because they add additional parasitic capacitance,

inductance, and resistance on the signal.

Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),

because the high-frequency switching can be coupled into the analog signal.

If differential mode is used for the ADC12_B, the analog differential input signals must be routed closely

together to minimize the effect of noise on the resulting signal.

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8 器件和文档支持

8.1 入门和下一步

要获得有助于您开发工作的 MSP430™系列器件、工具和库相关信息，请访问入门页面。

8.2 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

MSP430 MCU devices and support tools. Each MSP430 MCU commercial family member has one of

three prefixes: MSP, PMS, or XMS (for example, MSP430F5438A). TI recommends two of three possible

prefix designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of

product development from engineering prototypes (with XMS for devices and MSPX for tools) through fully

qualified production devices and tools (with MSP for devices and MSP for tools).

Device development evolutionary flow:

XMS – Experimental device that is not necessarily representative of the electrical specifications for the

final device

PMS – Final silicon die that conforms to the electrical specifications for the device but has not completed

quality and reliability verification

MSP – Fully qualified production device

Support tool development evolutionary flow:

MSPX – Development-support product that has not yet completed TI's internal qualification testing.

MSP – Fully-qualified development-support product

XMS and PMS devices and MSPX development-support tools are shipped against the following

disclaimer:

"Developmental product is intended for internal evaluation purposes."

MSP devices and MSP development-support tools have been characterized fully, and the quality and

reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (XMS and PMS) have a greater failure rate than the standard

production devices. TI recommends that these devices not be used in any production system because

their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the

package type (for example, PZP) and temperature range (for example, T). 图 8-1 provides a legend for

reading the complete device name for any family member.

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MSP 430 F 5 438 A I ZQW T -EP

Processor Family

MCU Platform

Device Type

Series

Feature Set

Optional: Additional Features

Optional: Tape and Reel

Packaging

Optional: Temperature Range

Optional: A = Revision

Processor Family

CC = Embedded RF Radio

MSP = Mixed-Signal Processor

XMS = Experimental Silicon

PMS = Prototype Device

MCU Platform

Device Type

430 = MSP430 low-power microcontroller platform

Memory Type

C = ROM

F = Flash

FR = FRAM

G = Flash or FRAM (Value Line)

L = No Nonvolatile Memory

Specialized Application

AFE = Analog Front End

BT = Preprogrammed with Bluetooth

BQ = Contactless Power

CG = ROM Medical

FE = Flash Energy Meter

FG = Flash Medical

FW = Flash Electronic Flow Meter

Series

1 Series = Up to 8 MHz

2 Series = Up to 16 MHz

3 Series = Legacy

5 Series = Up to 25 MHz

6 Series = Up to 25 MHz with LCD

0 = Low-Voltage Series

4 Series = Up to 16 MHz with LCD

Feature Set

Various Levels of Integration Within a Series

N/A

Optional: A = Revision

Optional: Temperature Range S = 0°C to 50°C

C = 0°C to 70°C

I = –40°C to 85°C

T = –40°C to 105°C

Packaging

http://www.ti.com/packaging

Optional: Tape and Reel

T = Small Reel

R = Large Reel

No Markings = Tube or Tray

Optional: Additional Features -EP = Enhanced Product (–40°C to 105°C)

-HT = Extreme Temperature Parts (–55°C to 150°C)

-Q1 = Automotive Q100 Qualified

图 8-1. Device Nomenclature

8.3 工具和软件

全部 MSP430™微控制器均受多种软件和硬件开发工具的支持。工具由 TI 以及多家第三方供应商提供。具

体信息请访问 www.ti.com/msp430tools。

8.3.1 硬件功能

关于可用特性的详细信息，请参见《适用于 MSP430 的 Code Composer Studio 用户指南》（文献编

号：SLAU157）等。

4 线制

JTAG

2 线制

JTAG

断点

(N)

状态序列发生

器

LPMx.5 调试支

持

MSP430 架构

范围断点

有

时钟控制

有

跟踪缓冲器

有

MSP430Xv2

有

8

有

器件和文档支持

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8.3.2 推荐的硬件选项

8.3.2.1 目标插座板

目标插座板可利用 JTAG 轻松实现器件编程和调试。板上还配有用于原型设计的排针引脚。目标插座板可单

独订购，也可以与 JTAG 编程器和调试器一起作为套件订购。下表列出了兼容的目标板以及支持的封装。

封装

目标板和编程器包

仅目标板

100 引脚 LQFP (PZ)

MSP-FET430U100USB

MSP-TS430PZ100USB

8.3.2.2 实验板

实验板和评估套件可用于部分 MSP430 器件。这类套件配有额外的硬件组件和连接功能，可实现全面的系

统评估和原型设计。有关详情，请访问 www.ti.com/msp430tools。

8.3.2.3 调试和编程工具

硬件编程和调试工具可从

www.ti.com/msp430tools。

TI

及其第三方供应商获取。要查看完整的可用工具列表，请访问

8.3.2.4 生产编程器

生产编程器可同时对多个器件进行编程，从而加快将固件载入器件的速度。

部件编号

PC 端口

特性

供应商

最多可同时对八个器件进行编程。可配合 PC 操作，也可以作为独立软件包

使用。

MSP-GANG

串行端口和 USB

德州仪器 (TI)

8.3.3 建议的软件选项

8.3.3.1 集成开发环境

软件开发工具由 TI 或第三方供应商提供。另外还提供开源解决方案。

此器件由 Code Composer Studio™IDE (CCS)。

8.3.3.2 MSP430Ware

MSP430Ware 将所有 MSP430 器件的代码示例、数据表以及其他设计资源打包在一起提供给用户。除了提

供已有 MSP430 设计资源的完备集合之外，MSP430Ware 还包含名为 MSP430 驱动程序库的高级 API。该

库可简化对 MSP430 硬件的编程。MSP430Ware 以 CCS 组件或独立软件包两种形式提供。

8.3.3.3 TI-RTOS

TI-RTOS 是一套适用于 MSP430 微控制器的高级实时操作系统。该器件支持优先确定多任务处理、硬件抽

象、内存管理和实时分析。TI-RTOS 可免费获取且附带全部源代码。

8.3.3.4 命令行编程器

MSP430 Flasher 是基于 shell 的开源接口，可使用 JTAG 或 Spy-Bi-Wire (SBW) 通信通过 FET 编程器或

eZ430™开发工具对 MSP430 微控制器进行编程。MSP430 Flasher 可用于将二进制文件（.txt 或 .hex 文

件）直接下载到 MSP430 闪存中，而无需使用 IDE。

8.4 文档支持

如需接收文档更新通知，请访问 ti.com（GPN1、GPN2 等）上的器件产品文件夹。点击右上角的提醒我

(Alert me) 注册后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含

的修订历史记录。

以下文档介绍 MSP430F665x、MSP430F645x、MSP430F565x 和 MSP430F535x 器件。在 www.ti.com 上

提供这些文档的副本。

SLAZ491

《MSP430F6459-Hirel 器件勘误表》。描述了针对这款器件的所有芯片修订版本功能技术规

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格的已知例外情况。

SLAU278

《MSP430 硬件工具用户指南》。本手册介绍了 TI MSP-FET430 闪存仿真工具 (FET) 的硬

件。FET 是针对 MSP430 超低功耗微控制器的程序开发工具。对提供的接口类型，即并行端

口接口和 USB 接口进行了说明。

SLAU319

《使用引导加载程序 (BSL) 对 MSP430 进行编程》。 MSP430 引导加载程序 (BSL) 允许用户

在原型设计、投产和维护等各阶段与 MSP430 微控制器中的嵌入式存储器进行通信。可编程

存储器（闪存）和数据存储器 (RAM) 可根据相关要求进行变更。请勿将此引导加载程序与某

些数字信号处理器 (DSP) 中将程序代码（和数据）从外部存储器自动加载到 DSP 内部存储器

的引导加载程序相混淆。

SLAU320

SLAA322

通过 JTAG 接口对 MSP430 进行编程。本文档介绍了使用 JTAG 通信端口擦除、编程和验证

基于 MSP430 闪存和 FRAM 的微控制器系列的存储器模块所需的功能。此外，它还介绍了如

何设定所有 MSP430 MCU 提供的 JTAG 来访问安全熔丝。本文档介绍了使用标准四线制

JTAG 接口和二线制 JTAG 接口（也称为 Spy-Bi-Wire (SBW)）进行的 MCU 访问。

《MSP430 32kHz 晶体振荡器》。对于稳定的晶体振荡器，选择合适的晶振、正确的负载电

路和适当的电路板布局布线至关重要。此应用报告总结了晶体振荡器的功能，介绍了为实现

MSP430 超低功耗运行而选择正确晶体的参数。此外，还给出了正确电路板布局布线的提示和

示例。本文档还包含与可能振荡器测试相关的详细信息以确保大批量生产中的稳定振荡器运

行。

器件和文档支持

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SLOA089

SLAA530

《电路板布局布线技巧》。运算放大器电路是模拟电路，与数字电路差异较大。在电路板中必

须通过特殊布线技术将其划分为独立区域。印刷电路板对于高速模拟电路的影响最为显著，但

本章介绍的常见错误甚至会影响音频电路的性能。本章旨在讨论设计人员的常见错误以及这些

错误对性能造成的不良影响，并提供避免此类错误的简单措施。

《MSP430 系统级 ESD 注意事项》。系统级 ESD 对于低电压下的硅晶技术以及经济高效型

和超低功耗组件的需求日益增加。该应用报告提出了三项不同的 ESD 主题，旨在帮助电路板

设计人员和 OEM 理解并设计出稳健耐用的系统级设计。

8.5 接收文档更新通知

如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me)

注册后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史

记录。

8.6 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the

respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;

see TI's Terms of Use.

TI E2E™ Community

TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At

e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow

engineers.

TI Embedded Processors Wiki

Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded

processors from Texas Instruments and to foster innovation and growth of general knowledge about the

hardware and software surrounding these devices.

8.7 商标

MSP430, Code Composer Studio, eZ430, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

8.8 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

8.9 出口管制提示

接收方同意：如果美国或其他适用法律限制或禁止将通过非披露义务的披露方获得的任何产品或技术数据

（其中包括软件）（见美国、欧盟和其他出口管理条例之定义）、或者其他适用国家条例限制的任何受管制

产品或此项技术的任何直接产品出口或再出口至任何目的地，那么在没有事先获得美国商务部和其他相关政

府机构授权的情况下，接收方不得在知情的情况下，以直接或间接的方式将其出口。

8.10 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

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9 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知

且不对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

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MECHANICAL DATA

MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996

PZ (S-PQFP-G100)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

75

M

0,08

51

50

76

26

100

0,13 NOM

1

25

12,00 TYP

Gage Plane

14,20

SQ

13,80

0,25

16,20

SQ

0,05 MIN

0°–7°

15,80

1,45

1,35

0,75

0,45

Seating Plane

0,08

1,60 MAX

4040149/B 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	MSP430F6459TPZR
厂家：	TEXAS INSTRUMENTS
描述：	HiRel 混合信号微控制器 \| PZ \| 100 \| -40 to 105 时钟控制器微控制器静态存储器外围集成电路装置
文件：	总126页 (文件大小：1391K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MSP430F6459TPZR [TI]

相关型号：

MSP430F645X

MSP430F663

MSP430F6630

MSP430F6630IPZ

MSP430F6630IPZR

MSP430F6630IZQW

MSP430F6630IZQWR

MSP430F6630IZQWT

MSP430F6630ZQWT

MSP430F6631

MSP430F6631IPZ

MSP430F6631IPZR