MSP430FG478IPN [TI]
MIXED SIGNAL MICROCONTROLLER; 混合信号微控制器
| 型号： | MSP430FG478IPN |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MIXED SIGNAL MICROCONTROLLER |
| 文件： | 总91页 (文件大小：1585K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
D
D
Low Supply-Voltage Range: 1.8 V to 3.6 V
D
Integrated LCD Driver With Contrast
Control for Up to 128 Segments
Ultra-Low Power Consumption:
Active Mode: 262 A at 1 MHz, 2.2 V
Standby Mode: 1.1 A
Off Mode (RAM Retention): 0.1 A
Five Power-Saving Modes
Wake-Up From Standby Mode in
Less Than 6 s
16-Bit RISC Architecture,
125-ns Instruction Cycle Time
16-Bit Sigma-Delta Analog-to-Digital (A/D)
Converter With Internal Reference and Five
Differential Analog Inputs
Dual 12-Bit Digital-to-Analog (D/A)
Converter
Dual Configurable Operational Amplifiers
16-Bit Timer_A With Three
Capture/Compare Registers
16-Bit Timer_B With Three
Capture/Compare-With-Shadow Registers
Two Universal Serial Communication
Interfaces (USCI)
USCI_A0
D
D
D
Brownout Detector
Basic Timer With Real-Time Clock Feature
Supply Voltage Supervisor/Monitor With
Programmable Level Detection
D
D
D
D
On-Chip Comparator
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
D
D
D
D
D
Bootstrap Loader
On-Chip Emulation Module
D
MSP430FG47x Family Members Include
MSP430FG477: 32KB+256B Flash Memory
2KB RAM
MSP430FG478: 48KB+256B Flash Memory
2KB RAM
MSP430FG479: 60KB+256B Flash Memory
2KB RAM
D
D
D
D
D
D
Available in 113-Ball BGA (ZQW) and
80-Pin QFP (PN) Packages (see Available
Options)
-- Enhanced UART Supporting
Auto-Baudrate Detection
-- IrDA Encoder and Decoder
-- Synchronous SPI
USCI_B0
For Complete Module Descriptions, See the
MSP430x4xx Family User’s Guide,
Literature Number SLAU056
-- I 2C
-- Synchronous SPI
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6 s.
The MSP430FG47x is a microcontroller configuration with two 16-bit timers, a basic timer with a real-time clock,
a high performance 16-bit sigma-delta A/D converter, dual 12-bit D/A converters, two configurable operational
amplifiers, two universal serial communication interface, 48 I/O pins, and a liquid crystal display driver.
Typical applications for this device include analog and digital sensor systems, digital motor control, remote
controls, thermostats, digital timers, hand-held meters, etc.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2011, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
†
AVAILABLE OPTIONS
PACKAGED DEVICES
‡
T
A
PLASTIC 113-BALL BGA (ZQW)
PLASTIC 80-PIN QFP (PN)
MSP430FG477IZQW
MSP430FG478IZQW
MSP430FG479IZQW
MSP430FG477IPN
MSP430FG478IPN
MSP430FG479IPN
-- 4 0 C to 85C
†
‡
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
DEVELOPMENT TOOL SUPPORT
All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging
and programming through easy to use development tools. Recommended hardware options include the
following:
D
Debugging and Programming Interface
-- MSP--FET430UIF (USB)
-- MSP--FET430PIF (Parallel Port)
Debugging and Programming Interface with Target Board
-- MSP--FET430U80 (PN package)
Production Programmer
D
D
-- MSP--GANG430
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
pin designation, MSP430FG47xIZQW
A1
B1
C1
D1
E1
F1
G1
H1
J1
A2
B2
C2
D2
E2
F2
G2
H2
J2
A3
B3
C3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
A9
B9
A10
B10
A11
B11
C11
D11
E11
F11
G11
H11
J11
A12
B12
C12
D12
E12
F12
G12
H12
J12
D4
E4
F4
G4
H4
J4
D5
E5
F5
G5
H5
J5
D6
E6
D7
E7
D8
D9
E9
F9
G9
H9
J9
E8
F8
G8
H8
H6
J6
H7
J7
J8
K1
L1
K2
L2
K11
L11
M11
K12
L12
M12
L3
L4
L5
L6
L7
L8
L9
L10
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
Note: For terminal assignments, see the MSP430xG47x Terminal Functions table.
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
pin designation, MSP430FG47xIPN
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DVCC1
P2.2/TB1
P2.1/TB0/S0
P2.0/TA2/S1
P2.6/CAOUT/S2
P2.7/S3
GND
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VREF
2
P6.7/OA1I2/SVSIN (SW1B)
P1.0/TA0/OA0RFB
3
4
P1.1/TA0/MCLK/OA1RFB
P1.2/TA1/A4-/OA0I3 (SW0C)
P1.3/TBOUTH/SVSOUT/A4+/OA1I3 (SW1C)
P1.4/TBCLK/SMCLK/A3-/OA1I0/DAC1
AVSS
5
6
7
XIN
8
XOUT
9
AVCC
80-pin
IPN PACKAGE
(TOP VIEW)
GND
10
11
12
13
14
15
16
17
18
19
20
P1.5/TACLK/ACLK/A3+
P1.6/CA0/A2-/OA0I0/DAC0
P1.7/CA1/A2+
P4.7/S4
P4.6/S5
P4.5/S6
P4.4/S7
P4.3/S8
P4.2/S9
P4.1/S10
P4.0/S11
S12
P3.7/S31
P3.6/S30
P3.5/S29
P3.4/S28
P3.3/UCB0CLK/UCA0STE
P3.2/UCB0SOMI/UCB0SCL/S27
P3.1/UCB0SIMO/UCB0SDA/S26
P3.0/UCB0STE/UCA0CLK
S13
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
functional block diagram
XIN/
XOUT/
P3.x/P4.x
P1.x/P2.x
DVCC1/2 DVSS1/2
AVCC
AVSS
XT2IN XT2OUT
P5.x/P6.x
2
2
2x8
4x8
ACLK
SD16_A
with
Buffer
1 Channel
Sigma-
Delta A/D
Converter
DAC12
12-Bit
Oscillators
FLL+
Ports
P1/P2
Ports
P3/P4
P5/P6
Flash
RAM
SMCLK
OA0, OA1
2 OpAmps
Comparator
_A
60kB
48kB
32kB
2kB
2kB
2kB
2
2x8 I/O
Interrupt
capability
Channels
Voltage
Out
4x8 I/O
MCLK
CPU
64kB
MAB
incl. 16
Registers
MDB
Timer_B3
USCI A0
UART/
LIN,
Brownout
Protection
LCD_A
128
Segments
1,2,3,4
Mux
Basic
Timer &
Real-
Time
Clock
EEM
Watchdog
WDT+
Timer_A3
3 CC
Registers,
Shadow
Reg
IrDA, SPI
3 CC
Registers
JTAG
Interface
SVS,
SVM
15-Bit
USCI B0
SPI, I2C
RST/NMI
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
NAME
80
113
PIN
PIN
AV
AV
52
53
1
F12
E12
A1
Analog supply voltage, positive terminal.
Analog supply voltage, negative terminal.
CC
SS
DV
DV
DV
Digital supply voltage, positive terminal. Supplies all digital parts.
Digital supply voltage, negative terminal. Supplies all digital parts.
Digital supply voltage, positive terminal. Supplies all digital parts.
CC1
79
80
A3
SS1
CC2
A2
B2
B3
DV
78
Digital supply voltage, negative terminal. Supplies all digital parts.
SS2
General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: Out0 output
Range switch to OA0 output
P1.0/TA0/
OA0RFB
58
C11
C12
D11
D12
I/O
I/O
I/O
BSL transmit
General-purpose digital I/O pin
Timer_A, capture: CCI0B input, compare: Out0 output
MCLK signal output
Range switch to OA1 output
BSL receive
P1.1/TA0/MCLK/
OA1RFB
57
56
55
General-purpose digital I/O pin
P1.2/TA1/A4--/
OA0I3 (SW0C)
Timer_A, capture: CCI1A input, compare: Out1 output
SD16 negative analog input A4
OA0, analog input I3
General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
switch all PWM digital output ports to high impedance -- Timer_B TB0 to TB2
I/O SVS comparator output
SD16 positive analog input A4
OA1, analog input I3
P1.3/TBOUTH/
SVSOUT/A4+/
OA1I3 (SW1C)
General-purpose digital I/O pin/
Timer_B, clock signal TBCLK input
SMCLK signal output
SD16 negative analog input A3
OA1, analog input I0
DAC12.1 output
P1.4/TBCLK/
SMCLK/A3--/
OA1I0/DAC1
54
E11
F11
I/O
General-purpose digital I/O pin
Timer_A, clock signal TACLK input
ACLK signal output
SD16 positive analog input A3
P1.5/TACLK/
ACLK/A3+
51
50
I/O
General-purpose digital I/O pin
Comparator_A input 0
SD16 negative analog input A2
OA0, analog input I0
DAC12.0 output
P1.6/CA0/A2--/
OA0I0/DAC0
G12
G11
I/O
General-purpose digital I/O pin
I/O Comparator_A input 1
SD16 positive analog input A2
P1.7/CA1/A2+
P2.0/TA2/S1
P2.1/TB0/S0
49
4
General-purpose digital I/O pin
I/O Timer_A, capture: CCI2A/B input, compare: Out2 output
LCD segment output 1
C2
C3
General-purpose digital I/O pin
I/O Timer_B, capture: CCI0A/B input, compare: Out0 output
LCD segment output 0
3
C1
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
Terminal Functions (continued)
TERMINAL
NO.
I/O
DESCRIPTION
NAME
80
113
PIN
PIN
General-purpose digital I/O pin
Timer_B, capture: CCI1A/B input, compare: Out1 output
P2.2/TB1
2
B1
B4
A4
D4
I/O
I/O
I/O
I/O
General-purpose digital I/O pin
Timer_B, capture: CCI2A/B input, compare: Out2 output
P2.3/TB2
77
76
75
P2.4/UCA0TXD/
UCA0SIMO
General-purpose digital I/O pin
USCIA transmit data output in UART mode, slave data in/master out in SPI mode
P2.5/UCA0RXD/
UCA0SOMI
General-purpose digital I/O pin
USCI A0 receive data input in UART mode, slave data out/master in in SPI mode
General-purpose digital I/O pin
P2.6/CAOUT/S2
5
D1
D2
I/O Comparator_A output
LCD segment output 2
General-purpose digital I/O pin
P2.7/S3
6
I/O
LCD segment output 3
P3.0/UCB0STE/
UCA0CLK
General-purpose digital I/O pin
USCI B0 slave transmit enable/USCI A0 clock input/output
41
M12
L12
I/O
General-purpose digital I/O pin
2
P3.1/UCB0SIMO/
UCB0SDA/S26
2
42
43
I/O USCI B0 slave in/master out in SPI mode, SDA I C data in I C mode
LCD segment output 26
General-purpose digital I/O pin
I/O USCI B0 slave out/master in in SPI mode, SCL I C clock in I C mode
LCD segment output 27
P3.2/UCB0SOMI/
UCB0SCL/S27
2
2
K11
P3.3/UCB0CLK/
UCA0STE
General-purpose digital I/O
USCI B0 clock input/output, USCI A0 slave transmit enable
44
45
46
47
48
18
17
16
15
14
13
12
11
K12
J11
J12
H11
H12
K2
I/O
General-purpose digital I/O pin
LCD segment output 28
P3.4/S28
P3.5/S29
P3.6/S30
P3.7/S31
P4.0/S11
P4.1/S10
P4.2/S9
P4.3/S8
P4.4/S7
P4.5/S6
P4.6/S5
P4.7/S4
I/O
General-purpose digital I/O pin
LCD segment output 29
I/O
General-purpose digital I/O pin
LCD segment output 30
I/O
General-purpose digital I/O pin
LCD segment output 31
I/O
General-purpose digital I/O pin
LCD segment output 11
I/O
General-purpose digital I/O pin
LCD segment output 10
K1
I/O
General-purpose digital I/O pin
LCD segment output 9
J2
I/O
General-purpose digital I/O pin
LCD segment output 8
J1
I/O
General-purpose digital I/O pin
LCD segment output 7
H2
I/O
General-purpose digital I/O pin
LCD segment output 6
H1
I/O
General-purpose digital I/O pin
LCD segment output 5
G2
G1
I/O
General-purpose digital I/O pin
LCD segment output 4
I/O
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
Terminal Functions (continued)
TERMINAL
NO.
I/O
DESCRIPTION
NAME
COM0
80
PIN
113
PIN
33
L8
O
Common output, COM0--3 are used for LCD backplanes
General-purpose digital I/O pin
LCD segment output 20
P5.0/S20
27
28
34
35
36
37
38
L5
I/O
General-purpose digital I/O pin
LCD segment output 21
P5.1/S21
M5
M8
L9
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O pin
common output, COM0--3 are used for LCD backplanes
P5.2/COM1
P5.3/COM2
P5.4/COM3
LCDCAP/R33
P5.5/R23
General-purpose digital I/O pin
common output, COM0--3 are used for LCD backplanes
General-purpose digital I/O pin
common output, COM0--3 are used for LCD backplanes
M9
J9
Capacitor connection for LCD charge pump
input port of most positive analog LCD level (V4)
General-purpose digital I/O pin
input port of the second most positive analog LCD level (V3)
M10
L10
P5.6/LCDREF/
R13
General-purpose digital I/O pin
External LCD reference voltage input
39
I/O
input port of the third most positive analog LCD level (V3 or V2)
P5.7/R03
40
67
M11
B8
I/O General-purpose digital I/O pin
input port of the fourth most positive analog LCD level (V1)
General-purpose digital I/O pin
I/O SD16 positive analog input A0
OA0, output
P6.0/A0+/OA0O
P6.1/A0--/OA0FB
General-purpose digital I/O pin
I/O SD16 positive negative input A0
OA0, analog input feedback
66
65
64
B9
A9
D9
P6.2/OA0I1
(SW0A)
General-purpose digital I/O pin
OA0, analog input I1
I/O
General-purpose digital I/O pin
I/O SD16 positive analog input A1
OA1, output
P6.3/A1+/OA1O
P6.4/A1--/OA1FB
General-purpose digital I/O pin
I/O SD16 positive negative input A1
OA1, analog input feedback
63
A10
P6.5/OA0I2
(SW0B)
General-purpose digital I/O pin
OA0, analog input I2
62
61
B10
A11
I/O
P6.6/OA1I1
(SW1A)
General-purpose digital I/O pin
OA1, analog input I1
I/O
General-purpose digital I/O pin
I/O OA1, analog input I2
SVS input
P6.7/OA1I2/
SVSIN (SW1B)
59
B12
S12
S13
S14
S15
S16
19
20
21
22
23
L1
M1
M2
M3
L3
O
O
O
O
O
LCD segment output 12
LCD segment output 13
LCD segment output 14
LCD segment output 15
LCD segment output 16
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
Terminal Functions (continued)
TERMINAL
NO.
I/O
DESCRIPTION
NAME
80
113
PIN
PIN
S17
S18
S19
S22
S23
S24
S25
GND
XIN
24
25
26
29
30
31
32
7
L4
M4
J4
O
O
O
O
O
O
O
LCD segment output 17
LCD segment output 18
LCD segment output 19
LCD segment output 22
LCD segment output 23
LCD segment output 24
LCD segment output 25
L6
M6
L7
M7
E2
E1
F1
F2
Ground. It is used to shield the oscillator. See Note 1.
8
I
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
Output port for crystal oscillator XT1. Standard or watch crystals can be connected.
Ground. It is used to shield the oscillator. See Note NO TAG.
XOUT
GND
9
O
10
60
74
V
A12
B5
O
I
Input for an external reference voltage/internal reference voltage output
Reset input, nonmaskable interrupt input port, or bootstrap loader start (in flash devices).
REF
RST/NMI
Test clock (JTAG). TCK is the clock input port for device programming test and bootstrap loader
start.
TCK
73
A5
I
TDI/TCLK
TDO/TDI
TMS
71
70
72
68
69
NA
A6
B7
B6
A8
A7
I
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
I/O Test data output port. TDO/TDI data output or programming data input terminal.
I
O
I
Test mode select. TMS is used as an input port for device programming and test.
Output terminal of crystal oscillator XT2
XT2OUT
XT2IN
Input port for crystal oscillator XT2
Reserved
B11,
BGA package unused balls. Connection to DV /AV recommended.
SS SS
D6, D7,
D8, E4,
E5, E6,
E7, E8,
E9, F4,
F5, F8,
F9, G4,
G5,G8,
G9, H4,
H5, H6,
H7, H8,
H9, J5,
J6, J7,
J8, L2,
L11
NOTE 1: It is recommended to connect GND externally to DVss.
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
short-form description
CPU
Program Counter
Stack Pointer
PC/R0
The MSP430 CPU has a 16--bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
R4
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
R5
R6
R7
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator, respectively. The
remaining registers are general-purpose
registers.
R8
R9
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
R10
R11
instruction set
R12
R13
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats, and Table 2 lists the address
modes.
R14
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
e.g., ADD R4,R5
R4 + R5 ------> R5
e.g., CALL
e.g., JNE
R8
PC ---->(TOS), R8----> PC
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
Register
S
D
SYNTAX
MOV Rs,Rd
EXAMPLE
MOV R10,R11
MOV 2(R5),6(R6)
OPERATION
F
F
F
F
F
F
F
F
F
R10 —> R11
Indexed
MOV X(Rn),Y(Rm)
MOV EDE,TONI
MOV & MEM, & TCDAT
MOV @Rn,Y(Rm)
M(2+R5)—> M(6+R6)
M(EDE) —> M(TONI)
M(MEM) —> M(TCDAT)
M(R10) —> M(Tab+R6)
Symbolic (PC relative)
Absolute
Indirect
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
Indirect
autoincrement
M(R10) —> R11
R10 + 2—> R10
F
MOV @Rn+,Rm
Immediate
F
MOV #X,TONI
#45 —> M(TONI)
NOTE: S = source
D = destination
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MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D
Active mode (AM)
-- All clocks are active
D
Low-power mode 0 (LPM0)
-- CPU is disabled
-- ACLK and SMCLK remain active
-- FLL+ loop control remains active
Low-power mode 1 (LPM1)
D
D
-- CPU is disabled
-- ACLK and SMCLK remain active
-- FLL+ loop control is disabled
Low-power mode 2 (LPM2)
-- CPU is disabled
-- MCLK, FLL+ loop control, and DCOCLK are disabled
-- DCO’s dc generator remains enabled
-- ACLK remains active
D
D
Low-power mode 3 (LPM3)
-- CPU is disabled
-- MCLK, FLL+ loop control, and DCOCLK are disabled
-- DCO’s dc generator is disabled
-- ACLK remains active
Low-power mode 4 (LPM4)
-- CPU is disabled
-- ACLK is disabled
-- MCLK, FLL+ loop control, and DCOCLK are disabled
-- DCO’s dc generator is disabled
-- Crystal oscillator is stopped
11
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MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0xFFFF to 0xFFC0.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
If the reset vector (located at address 0xFFFE) contains 0xFFFF (e.g., flash is not programmed) the CPU goes
into LPM4 immediately after power--up.
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
PRIORITY
Power-Up
External Reset
PORIFG
RSTIFG
Reset
0xFFFE
15, highest
Watchdog
Flash Memory
WDTIFG
KEYV
PC Out--of--Range (see Note 4)
(see Note 1)
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1, 2 and 4)
(Non)maskable
(Non)maskable
(Non)maskable
0xFFFC
14
Timer_B3
TBCCR0 CCIFG0 (see Note 2)
Maskable
0xFFFA
0xFFF8
13
12
TBCCR1 CCIFG1 ... TBCCR3 CCIFG3,
TBIFG (see Notes 1 and 2)
Timer_B3
Maskable
Comparator_A
CAIFG
Maskable
Maskable
Maskable
0xFFF6
0xFFF4
0xFFF2
11
10
9
Watchdog Timer+
WDTIFG
USCI_A0/USCI_B0 receive
USCI_B0 I2C status
UCA0RXIFG, UCB0RXIFG
(see Notes 1 and 5)
USCI_A0/USCI_B0 transmit
USCI_B0 I2C receive/transmit
UCA0TXIFG, UCB0TXIFG
(see Note 1 and 6)
Maskable
Maskable
0xFFF0
0xFFEE
8
7
SD16_A
SD16CCTLx SD16OVIFG, SD16CCTLx SD16IFG
(see Notes 1 and 2)
Timer_A3
Timer_A3
TACCR0 CCIFG0 (see Note 2)
Maskable
Maskable
0xFFEC
0xFFEA
6
5
TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG (see Notes 1 and 2)
I/O Port P1 (Eight Flags)
DAC12
P1IFG.0 to P1IFG.7 (see Notes 1 and 2)
DAC12_0IFG, DAC12_1IFG
Maskable
Maskable
Maskable
Maskable
Maskable
0xFFE8
0xFFE6
0xFFE4
0xFFE2
0xFFE0
4
3
2
1
I/O Port P2 (Eight Flags)
Basic Timer1/RTC
P2IFG.0 to P2IFG.7 (see Notes 1 and 2)
BTIFG
0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh).
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
4. Access and key violations, KEYV and ACCVIFG.
5. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
6. In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
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MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits
not allocated to a functional purpose are not physically present in the device. This arrangement provides simple
software access.
interrupt enable 1 and 2
Address
00h
7
6
5
4
3
2
1
0
ACCVIE
rw--0
NMIIE
rw--0
OFIE
rw--0
WDTIE
rw--0
WDTIE
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog
timer is configured in interval timer mode.
OFIE
Oscillator fault enable
NMIIE
ACCVIE
(Non)maskable interrupt enable
Flash access violation interrupt enable
Address
01h
7
6
5
4
3
2
1
0
BTIE
rw--0
UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE
rw--0 rw--0 rw--0 rw--0
UCA0RXIE
UCA0TXIE
UCB0RXIE
UCB0TXIE
BTIE
USCI_A0 receive interrupt enable
USCI_A0 transmit interrupt enable
USCI_B0 receive interrupt enable
USCI_B0 transmit interrupt enable
Basic timer interrupt enable
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MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
interrupt flag register 1 and 2
Address
02h
7
6
5
4
3
2
1
0
NMIIFG
rw--0
RSTIFG
rw--(0)
PORIFG
rw--(1)
OFIFG
rw--1
WDTIFG
rw--(0)
WDTIFG
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
OFIFG
Flag set on oscillator fault.
RSTIFG
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset
on VCC power-up.
PORIFG
NMIIFG
Power-on interrupt flag. Set on VCC power-up.
Set via RST/NMI pin.
Address
03h
7
6
5
4
3
2
1
0
UCB0
TXIFG
UCB0
RXIFG
UCA0
TXIFG
UCA0
RXIFG
BTIFG
rw--0
rw--1
rw--0
rw--1
rw--0
UCA0RXIFG USCI_A0 receive interrupt flag
UCA0TXIFG USCI_A0 transmit interrupt flag
UCB0RXIFG USCI_B0 receive interrupt flag
UCB0TXIFG
BTIFG
USCI_B0 transmit interrupt flag
Basic Timer1 interrupt flag
Legend
rw:
Bit can be read and written.
rw-0,1:
rw-(0,1):
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device
14
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MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
memory organization
MSP430FG477
MSP430FG478
MSP430FG479
Memory
Size
32KB
48KB
60KB
Main: interrupt vector
Main: code memory
Flash
Flash
0FFFFh to 0FFE0h
0FFFFh to 08000h
0FFFFh to 0FFE0h
0FFFFh to 04000h
0FFFFh to 0FFE0h
0FFFFh to 01100h
Information memory
Boot memory
RAM
Size
Flash
256 Byte
010FFh to 01000h
256 Byte
010FFh to 01000h
256 Byte
010FFh to 01000h
Size
ROM
1KB
0FFFh to 0C00h
1KB
0FFFh to 0C00h
1KB
0FFFh to 0C00h
Size
2KB
2KB
2KB
09FFh to 0200h
09FFh to 0200h
09FFh to 0200h
Peripherals
16-bit
8-bit
8-bit SFR
01FFh to 0100h
0FFh to 010h
0Fh to 00h
01FFh to 0100h
0FFh to 010h
0Fh to 00h
01FFh to 0100h
0FFh to 010h
0Fh to 00h
bootstrap loader (BSL)
The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access
to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the
features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap
Loader, literature number SLAA089.
BSL FUNCTION
Data Transmit
Data Receive
PN PACKAGE PINS
58 - P1.0
ZQW PACKAGE PINS
C11 - P1.0
57 - P1.1
C12 - P1.1
flash memory (Flash)
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D
Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
D
D
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
D
D
Segment A might contain calibration data. After reset, segment A is protected against programming or
erasing. It can be unlocked, but care should be taken not to erase this segment if this calibration data is
required.
Flash content integrity check with marginal read modes.
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MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, literature number
SLAU056.
oscillator and system clock
The clock system in the MSP430FG47x is supported by the FLL+ module, which includes support for a
32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a 8-MHz high-frequency
crystal oscillator (XT1), plus a 8-MHz high-frequency crystal oscillator (XT2). The FLL+ clock module is
designed to meet the requirements of both low system cost and low power consumption. The FLL+ features
digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO
frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on
clock source and stabilizes in less than 6 s. The FLL+ module provides the following clock signals:
D
D
D
D
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal
Main clock (MCLK), the system clock used by the CPU
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must ensure the default FLL+ settings are not changed until VCC
reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min)
.
digital I/O
There are six 8-bit I/O ports implemented, ports P1 through P6.
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
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MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
watchdog timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
Basic Timer1 and Real-Time Clock
The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 is extended to provide an integrated real-time
clock (RTC). An internal calendar compensates for month with less than 31 days and includes leap year
correction.
LCD_A driver with regulated charge pump
The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
The module can provide a LCD voltage independent of the supply voltage via an integrated charge pump.
Furthermore, it is possible to control the level of the LCD voltage and, thus, contrast in software.
Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_A3 SIGNAL CONNECTIONS
MODULE
OUTPUT
SIGNAL
INPUT PIN NUMBER
OUTPUT PIN NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
MODULE
BLOCK
PN
ZQW
PN
ZQW
P1.5 -- 51
F11
TACLK
ACLK
TACLK
ACLK
Timer
CCR0
CCR1
CCR2
NA
TA0
TA1
TA2
SMCLK
TAINCLK
TA0
SMCLK
INCLK
CCI0A
CCI0B
GND
P1.5 -- 51
P1.0 -- 58
P1.1 -- 57
F11
C11
C12
P1.0 -- 58
P1.1 -- 57
C11
C12
TA0
DV
DV
SS
CC
V
CC
P1.2 -- 56
P2.0 -- 4
D11
C2
TA1
CAOUT (internal)
CCI1A
CCI1B
GND
P1.2 -- 56
P2.0 -- 4
D11
C2
DV
DV
SS
CC
V
CC
TA2
ACLK (internal)
CCI2A
CCI2B
GND
DV
DV
SS
CC
V
CC
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MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
Timer_B3
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_B3 SIGNAL CONNECTIONS
MODULE
OUTPUT
SIGNAL
INPUT PIN NUMBER
OUTPUT PIN NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
MODULE
BLOCK
PN
ZQW
PN
ZQW
P1.4 -- 54
E11
TBCLK
ACLK
TBCLK
ACLK
Timer
NA
SMCLK
SMCLK
INCLK
P1.4 -- 54
E11
TBCLK
(See Note 1)
P2.1 -- 3
P2.1 -- 3
C1
C1
TB0
TB0
CCI0A
CCI0B
GND
P2.1 -- 3
P2.2 -- 2
P2.3 -- 77
C1
B1
B4
CCR0
CCR1
CCR2
TB0
TB1
TB2
V
SS
CC
V
V
CC
P2.2 -- 2
P2.2 -- 2
B1
B1
TB1
TB1
CCI1A
CCI1B
GND
V
SS
CC
V
V
CC
P2.3 -- 77
B4
TB2
CCI2A
CCI2B
GND
ACLK (internal)
V
SS
V
V
CC
CC
NOTE 1: The inversion of TBCLK is done inside the module.
universal serial communication interfaces (USCIs) (USCI_A0, USCI_B0)
The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 pin or 4 pin), I2C, and asynchronous communication protocols such
as UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.
USCI_A0 provides support for SPI (3 pin or 4 pin), UART, enhanced UART and IrDA.
USCI_B0 provides support for SPI (3 pin or 4 pin) and I2C.
Comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
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MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
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SD16_A
The SD16_A module supports 16-bit analog-to-digital conversions. The module implements a 16-bit
sigma-delta core and a reference generator. In addition to external analog inputs, an internal VCC sense and
temperature sensor are also available.
DAC12
The DAC12 module is a 12-bit R-ladder voltage-output DAC. The DAC12 may be used in 8-bit or 12-bit mode.
When multiple DAC12 modules are present, they may be grouped together for synchronous operation.
OA
The MSP430FG47x has two configurable low-current general-purpose operational amplifiers. Each OA input
and output terminal is software-selectable and offer a flexible choice of connections for various applications.
The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion.
OA0 SIGNAL CONNECTIONS
DEVICE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
INPUT PIN NUMBER
OUTPUT PIN NUMBER
MODULE
INPUT NAME
MODULE
BLOCK
PN
ZQW
PN
ZQW
P1.6 -- 50
P6.2 -- 65
P6.5 -- 62
P1.2 -- 56
P1.4 -- 54
P6.6 -- 61
P6.7 -- 59
P1.3 -- 55
G12
A9
OA0I0
OA0I1
OA0I2
OA0I3
OA1I0
OA1I1
OA1I2
OA1I3
OAxI0
OAxI1
OAxIA
OAxIB
OAxI0
OAxI1
OAxIA
OAxIB
P6.0 -- 67
B8
OA0
OA1
OA0OUT
OA1OUT
OA0O
OA1O
B10
D11
E11
A11
B12
D12
P6.4 -- 64
A10
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MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog
Timer_B3
Watchdog timer control
WDTCTL
0120h
Capture/compare register 2
Capture/compare register 1
Capture/compare register 0
Timer_B register
TBCCR2
TBCCR1
TBCCR0
TBR
0196h
0194h
0192h
0190h
0186h
0184h
0182h
0180h
011Eh
Capture/compare control 2
Capture/compare control 1
Capture/compare control 0
Timer_B control
TBCCTL2
TBCCTL1
TBCCTL0
TBCTL
Timer_B interrupt vector
TBIV
Timer_A3
Capture/compare register 2
Capture/compare register 1
Capture/compare register 0
Timer_A register
TACCR2
TACCR1
TACCR0
TAR
0176h
0174h
0172h
0170h
0166h
0164h
0162h
0160h
012Eh
Capture/compare control 2
Capture/compare control 1
Capture/compare control 0
Timer_A control
TACCTL2
TACCTL1
TACCTL0
TACTL
Timer_A interrupt vector
TAIV
Flash
Flash control 4
Flash control 3
Flash control 2
Flash control 1
DAC12_1 data
DAC12_1 control
DAC12_0 data
DAC12_0 control
FCTL4
01BEh
012Ch
012Ah
0128h
01CAh
01C2h
01C8h
01C0h
FCTL3
FCTL2
FCTL1
DAC12
DAC12_1DAT
DAC12_1CTL
DAC12_0DAT
DAC12_0CTL
SD16_A
(see also:
Peripherals with
Byte Access)
General control
SD16CTL
SD16CCTL0
SD16MEM0
SD16IV
0100h
0102h
0112h
0110h
Channel 0 control
Channel 0 conversion memory
Interrupt vector word register
OA switches
OA switches
OA1
Switch control register 1
SWCTL_1
00CEh
PERIPHERALS WITH BYTE ACCESS
Switch control register
Switch control register 1
SWCTL
00CFh
00CEh
SWCTL1
Operational amplifier 1 control register 1
Operational amplifier 1 control register 0
OA1CTL1
OA1CTL0
00C3h
00C2h
OA0
Operational amplifier 0 control register 1
Operational amplifier 0 control register 0
OA0CTL1
OA0CTL0
00C1h
00C0h
SD16_A
(see also:
Peripherals with
Word Access)
Channel 0 input control
Analog enable
SD16INCTL0
SD16AE
0B0h
0B7h
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
peripheral file map (continued)
LCD_A
LCD voltage control 1
LCDAVCTL1
LCDAVCTL0
LCDAPCTL1
LCDAPCTL0
LCDM20
:
0AFh
0AEh
0ADh
0ACh
0A4h
:
LCD voltage control 0
LCD voltage port control 1
LCD voltage port control 0
LCD memory 20
:
LCD memory 16
LCD memory 15
:
LCDM16
LCDM15
:
0A0h
09Fh
:
LCD memory 1
LCD control and mode
LCDM1
091h
090h
LCDACTL
USCI A0/B0
USCI A0 auto baud rate control
USCI A0 transmit buffer
USCI A0 receive buffer
USCI A0 status
UCA0ABCTL
UCA0TXBUF
UCA0RXBUF
UCA0STAT
UCA0MCTL
UCA0BR1
UCA0BR0
UCA0CTL1
UCA0CTL0
UCA0IRRCTL
UCA0IRTCTL
UCB0TXBUF
UCB0RXBUF
UCB0STAT
UCB0CIE
0x005D
0x0067
0x0066
0x0065
0x0064
0x0063
0x0062
0x0061
0x0060
0x005F
0x005E
0x006F
0x006E
0x006D
0x006C
0x006B
0x006A
0x0069
0x0068
0x011A
0x0118
05Bh
USCI A0 modulation control
USCI A0 baud rate control 1
USCI A0 baud rate control 0
USCI A0 control 1
USCI A0 control 0
USCI A0 IrDA receive control
USCI A0 IrDA transmit control
USCI B0 transmit buffer
USCI B0 receive buffer
USCI B0 status
USCI B0 I2C Interrupt enable
USCI B0 baud rate control 1
USCI B0 baud rate control 0
USCI B0 control 1
UCB0BR1
UCB0BR0
UCB0CTL1
UCB0CTL0
UCB0SA
USCI B0 control 0
USCI B0 I2C slave address
USCI B0 I2C own address
Comparator_A port disable
Comparator_A control2
Comparator_A control1
UCB0OA
Comparator_A
CAPD
CACTL2
05Ah
CACTL1
059h
Brownout, SVS
FLL+ Clock
SVS control register (reset by brownout signal) SVSCTL
056h
FLL+ control 1
FLL_CTL1
FLL_CTL0
SCFQCTL
SCFI1
054h
FLL+ control 0
053h
System clock frequency control
System clock frequency integrator
System clock frequency integrator
052h
051h
SCFI0
050h
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MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
RTC
(Basic Timer1)
Real-time clock year high byte
Real-time clock year low byte
Real-time clock month
Real-time clock day of month
Basic Timer1 counter
RTCYEARH
RTCYEARL
RTCMON
RTCDAY
BTCNT2
04Fh
04Eh
04Dh
04Ch
047h
046h
045h
Basic Timer1 counter
BTCNT1
Real-time counter 4
RTCNT4
(Real-time clock day of week)
Real-time counter 3
(RTCDOW)
RTCNT3
044h
043h
042h
(Real-time clock hour)
Real-time counter 2
(RTCHOUR)
RTCNT2
(Real-time clock minute)
Real-time counter 1
(RTCMIN)
RTCNT1
(Real-time clock second)
Real-time clock control
Basic Timer1 control
(RTCSEC)
RTCCTL
041h
040h
BTCTL
Port P6
Port P5
Port P4
Port P3
Port P2
Port P6 selection
Port P6 direction
Port P6 output
P6SEL
P6DIR
P6OUT
P6IN
037h
036h
035h
034h
033h
032h
031h
030h
01Fh
01Eh
01Dh
01Ch
01Bh
01Ah
019h
018h
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Port P6 input
Port P5 selection
Port P5 direction
Port P5 output
P5SEL
P5DIR
P5OUT
P5IN
Port P5 input
Port P4 selection
Port P4 direction
Port P4 output
P4SEL
P4DIR
P4OUT
P4IN
Port P4 input
Port P3 selection
Port P3 direction
Port P3 output
P3SEL
P3DIR
P3OUT
P3IN
Port P3 input
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt-edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
Port P2 input
22
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Port P1
Port P1 selection 2 register
Port P1 selection
P1SEL2
P1SEL
057h
026h
Port P1 interrupt enable
Port P1 interrupt-edge select
Port P1 interrupt flag
Port P1 direction
P1IE
025h
024h
023h
022h
021h
020h
P1IES
P1IFG
P1DIR
P1OUT
P1IN
Port P1 output
Port P1 input
Special functions SFR interrupt flag 2
SFR interrupt flag 1
IFG2
IFG1
IE2
003h
002h
001h
000h
SFR interrupt enable 2
SFR interrupt enable 1
IE1
23
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
absolute maximum ratings over operating free-air temperature (see Note 1)
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4.1 V
Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to VCC + 0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA
Storage temperature, Tstg: (unprogrammed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . --55C to 150C
(programmed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . --40C to 85C
NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
2. All voltages referenced to V . The JTAG fuse-blow voltage, V , is allowed to exceed the absolute maximum rating. The voltage
SS
FB
is applied to the TDI/TCLK pin when blowing the JTAG fuse.
3. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with
peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
recommended operating conditions
MIN
NOM
MAX UNITS
Supply voltage during program execution,
(AV = DV = V
1.8
3.6
3.6
V
V
V
)
CC
CC
CC
CC
Supply voltage during flash memory programming,
(AV = DV = V
2.2
V
)
CC
CC
CC
CC
Supply voltage, V (AV = DV = V )
SS
0
0
V
SS
SS
SS
Operating free-air temperature range, T
-- 4 0
85
C
A
LF selected,
XTS_FLL = 0
Watch crystal
Ceramic resonator
Crystal
32.768
kHz
MHz
MHz
XT1 selected,
XTS_FLL = 1
LFXT1 crystal frequency, f
(see Note 1)
(LFXT1)
0.45
1
6
6
XT1 selected,
XTS_FLL = 1
Ceramic resonator
Crystal
0.45
1
8
8
XT2 crystal frequency, f
MHz
(XT2)
V
V
= 1.8 V
= 2.5 V
dc
dc
4.15
8
CC
System frequency, MCLK, ACLK, SMCLK , f
MHz
(System)
CC
NOTES: 1. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
fSystem (MHz)
8 MHz
Supply voltage range,
MSP430FG47x, during
program execution
Supply voltage range, MSP430FG47x,
during flash memory programming
4.15 MHz
1.8
2.2
2.5
3.6
Supply Voltage - V
Figure 1. Frequency vs Supply Voltage, Typical Characteristics
24
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AVCC + DVCC excluding external current
PARAMETER
TEST CONDITIONS
V
MIN
TYP
MAX
UNIT
CC
Active mode (see Note 1)
2.2 V
3 V
262
295
f
f
= f
= 1 MHz,
(MCLK)
(SMCLK)
I
T
A
= --40C to 85C
A
(AM)
= 32,768 Hz
(ACLK)
420
460
XTS = 0, SELM = (0,1)
2.2 V
3 V
32
51
62
77
Low-power mode (LPM0)
(see Note 1)
I
I
T
= --40C to 85C
= --40C to 85C
A
A
(LPM0)
(LPM2)
A
Low-power mode (LPM2),
f(MCLK) = f (SMCLK) = 0 MHz,
f(ACLK) = 32,768 Hz, SCG0 = 0 (see Note 2)
2.2 V
3 V
5
7
9
T
A
13
T
= --40C
= 25C
= 60C
= 85C
= --40C
= 25C
= 60C
= 85C
= --40C
= 25C
= 85C
= --40C
= 25C
= 85C
= --40C
= 25C
= 60C
= 85C
= --40C
= 25C
= 60C
= 85C
1.0
1.0
1.1
2.3
1.2
1.2
1.4
2.7
1.0
1.1
3.5
1.8
2.0
4.2
0.1
0.1
0.7
1.7
0.1
0.1
0.8
1.5
1.8
1.8
2.0
4.0
2.0
2.0
2.2
4.5
3.0
3.2
6.0
3.3
4.0
7.5
0.5
0.5
1.1
3.0
0.8
0.8
1.2
3.5
A
T
A
Low-power mode (LPM3)
2.2 V
3 V
T
A
f
f
= f
= 0 MHz,
(MCLK)
(SMCLK)
= 32,768 Hz, SCG0 = 1
(ACLK)
T
A
Basic Timer1 enabled , ACLK selected
LCD_A enabled, LCDCPEN = 0:
I
I
I
A
A
A
(LPM3)
(LPM3)
(LPM4)
T
A
(static mode , f
= f
/32)
T
A
LCD
(ACLK)
(see Note 2 and Note 3)
T
A
T
A
T
A
Low-power mode (LPM3)
T
A
f
f
= f
= 0 MHz,
(SMCLK)
2.2 V
3 V
(MCLK)
(ACLK)
= 32,768 Hz, SCG0 = 1
T
A
Basic Timer1 enabled , ACLK selected
LCD_A enabled, LCDCPEN = 0:
T
A
(4-mux mode, f
= f
/32)
T
A
LCD
(ACLK)
(see Note 2 and Note 3)
T
A
T
A
T
A
2.2 V
3 V
T
A
Low-power mode (LPM4)
T
A
f
f
= 0 MHz, f
= 0 Hz, SCG0 = 1 (see Note 2)
= 0 MHz,
(SMCLK)
(MCLK)
(ACLK)
T
A
T
A
T
A
T
A
NOTES: 1. Timer_A is clocked by f
= 1 MHz. All inputs are tied to 0 V or to V . Outputs do not source or sink any current.
CC
(DCOCLK)
2. All inputs are tied to 0 V or to V . Outputs do not source or sink any current.
CC
3. The LPM3 currents are characterized with a Micro Crystal CC4V--T1A (9pF) crystal and OSCCAPx = 01h.
Current consumption of active mode versus system frequency
I
(AM) = I(AM) [1 MHz] f(System) [MHz]
Current consumption of active mode versus supply voltage
(AM) = I(AM) [3 V] + 200 A/V (VCC – 2.2 V)
I
25
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
typical characteristics -- LPM4 current
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Vcc = 3.6 V
Vcc = 3.0 V
Vcc = 2.2 V
Vcc = 1.8 V
--40.0 --20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0
T
A
-- Temperature -- C
Figure 2. ILPM4 -- LPM4 Current vs Temperature
26
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Schmitt-trigger inputs -- Ports P1, P2, P3, P4, P5, and P6, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
PARAMETER
TEST CONDITIONS
MIN
1.1
1.5
0.4
0.9
0.3
0.5
MAX
1.55
1.98
0.9
UNIT
V
V
V
V
V
V
= 2.2 V
= 3 V
CC
CC
CC
CC
CC
CC
V
V
V
Positive-going input threshold voltage
V
IT+
IT--
hys
= 2.2 V
= 3 V
Negative-going input threshold voltage
V
V
1.3
= 2.2 V
= 3 V
1.1
Input voltage hysteresis (V
-- V
)
IT--
IT+
1
inputs Px.y, TAx
PARAMETER
TEST CONDITIONS
V
MIN
62
MAX
UNIT
CC
2.2 V
3 V
Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag (see Note 1)
t
t
f
f
External interrupt timing
Timer_A capture timing
ns
(int)
50
2.2 V
3 V
62
TA0, TA1, TA2
ns
(cap)
50
2.2 V
3 V
8
10
8
Timer_A clock frequency externally
applied to pin
TACLK, INCLK: t = t
(L)
MHz
MHz
(TAext)
(H)
2.2 V
3 V
Timer_A, clock frequency
SMCLK or ACLK signal selected
(TAint)
10
NOTES: 1. The external signal sets the interrupt flag every time the minimum t
parameters are met. It may be set even with trigger signals
(int)
shorter than t
.
(int)
leakage current -- Ports P1, P2, P3, P4, P5, and P6 (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
I
Leakage current
Port Px
V
(see Note 2)
V = 2.2 V/3 V
CC
50
nA
lkg(Px.y)
(Px.y)
NOTES: 1. The leakage current is measured with V or V applied to the corresponding pin(s), unless otherwise noted.
SS
CC
2. The port pin must be selected as input.
27
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs -- Ports P1, P2, P3, P4, P5, and P6
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
I
I
I
I
I
I
I
I
-- 1 . 5 m A ,
-- 6 m A ,
-- 1 . 5 m A ,
-- 6 m A ,
1.5 mA,
6 mA,
V
V
V
V
V
V
V
V
2.2 V,
2.2 V,
3 V,
See Note 1
See Note 2
See Note 1
See Note 2
See Note 1
See Note 2
See Note 1
See Note 2
V
--0.25
V
V
V
V
OH(max) =
OH(max) =
OH(max) =
OH(max) =
OL(max) =
OL(max) =
OL(max) =
OL(max) =
CC =
CC =
CC =
CC =
CC =
CC =
CC =
CC =
CC
CC
CC
CC
CC
V
-- 0 . 6
CC
V
V
High-level output voltage
V
OH
V
--0.25
CC
3 V,
V
-- 0 . 6
CC
2.2 V,
2.2 V,
3 V,
V
V
V
V
V
+0.25
SS
SS
SS
SS
SS
V
+0.6
SS
Low-level output voltage
V
OL
1.5 mA,
6 mA,
V
+0.25
SS
3 V,
V
+0.6
SS
NOTES: 1. The maximum total current, I
specified voltage drop.
and I
for all outputs combined, should not exceed 12 mA to satisfy the maximum
OH(max)
OL(max),
2. The maximum total current, I
specified voltage drop.
and I
for all outputs combined, should not exceed 48 mA to satisfy the maximum
OH(max)
OL(max),
output frequency
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
MHz
C
= 20 pF,
= 1.5 mA
L
f
f
(x = 1, 2, 3, 4, 5, 6, 0 y 7)
V
2.2 V / 3 V
DC
f
f
(Px.y)
CC =
System
I
L
P1.1/TA0/MCLK
C = 20 pF
L
(MCLK)
System
f
f
= f
= f
40%
60%
(MCLK)
(MCLK)
(XT1)
P1.1/TA0/MCLK,
t
Duty cycle of output frequency
C
V
= 20 pF,
50%--
15 ns
50%+
15 ns
(Xdc)
L
50%
(DCOCLK)
= 2.2 V / 3 V
CC
28
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs -- Ports P1, P2, P3, P4, P5, and P6 (continued)
TYPICAL LOW-LEVEL OUTPUT CURRENT
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
T
= --40C
= 25C
V
P1.0
= 2.2 V
V
P1.0
= 3 V
CC
A
CC
T
= --40C
A
T
A
T
= 25C
= 85C
A
T
= 85C
A
T
A
0
0.0
0
0.0
0.5
1.0
1.5
2.0
2.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
-- Low-Level Output Voltage -- V
V
-- Low-Level Output Voltage -- V
OL
OL
Figure 3
Figure 4
TYPICAL HIGH-LEVEL OUTPUT CURRENT
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
vs
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
0.0
0.0
-- 5 . 0
V
P1.0
= 2.2 V
V
P1.0
= 3 V
CC
CC
-- 5 . 0
--10.0
--15.0
--20.0
--25.0
--30.0
--35.0
--40.0
--45.0
--50.0
--55.0
--10.0
--15.0
--20.0
--25.0
--30.0
T
A
= 25C
T
A
= 85C
T
A
= 85C
T = 25C
A
T
A
= --40C
T
A
= --40C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
V
-- High-Level Output Voltage -- V
V
-- High-Level Output Voltage -- V
OH
OH
Figure 5
Figure 6
29
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER
TEST CONDITIONS
f = 1 MHz
MIN
MAX
UNIT
6
6
6
f = 2 MHz
f = 3 MHz
t
Delay time
V
2.2 V/3 V
CC =
s
d(LPM3)
POR/brownout reset (BOR) (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
0.7 V
MAX
UNIT
s
t
2000
d(BOR)
V
dV /dt 3 V/s (see Figure 7)
V
CC(start)
CC
(B_IT--)
Brownout
V
V
dV /dt 3 V/s (see Figure 7 through Figure 9)
1.71
V
(B_IT--)
CC
(see Note 2)
dV /dt 3 V/s (see Figure 7)
CC
mV
hys(B_IT--)
Pulse length needed at RST/NMI pin to accepted reset internally,
= 2.2 V/3 V
t
2
s
(reset)
V
CC
NOTES: 1. The current consumption of the brownout module is already included in the I current consumption data. The voltage level V
CC
(B_IT--)
+ V
is 1.8V.
hys(B_IT--)
2. During power up, the CPU begins code execution following a period of t
after V = V
+ V
. The default
hys(B_IT--)
d(BOR)
CC
(B_IT--)
FLL+ settings must not be changed until V V
, where V
is the minimum supply voltage for the desired
CC
CC(min)
CC(min)
operating frequency. See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout.
typical characteristics
V
CC
V
hys(B_IT--)
V
(B_IT--)
V
CC(start)
1
0
t
d(BOR)
Figure 7. POR/Brownout Reset (BOR) vs Supply Voltage
30
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
typical characteristics (continued)
V
t
CC
pw
2
3 V
V
= 3 V
CC
Typical Conditions
1.5
1
V
CC(min)
0.5
0
0.001
1
1000
1 ns
1 ns
-- Pulse Width -- s
t
pw
-- Pulse Width -- s
t
pw
Figure 8. V(CC)min Level With a Square Voltage Drop to Generate a POR/Brownout Signal
V
t
CC
pw
2
1.5
1
3 V
V
= 3 V
CC
Typical Conditions
V
CC(min)
0.5
t
f =
t
r
0
0.001
1
1000
t
f
t
r
t
pw
-- Pulse Width -- s
t
pw
-- Pulse Width -- s
Figure 9. VCC(min) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
31
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
SVS (supply voltage supervisor/monitor)
PARAMETER
TEST CONDITIONS
dV /dt > 30 V/ms (see Figure 10)
MIN
TYP
MAX
150
2000
300
12
UNIT
s
5
CC
t
(SVSR)
dV /dt 30 V/ms
CC
s
t
t
SVSON, switch from VLD = 0 to VLD 0, V = 3 V
150
s
d(SVSon)
settle
CC
‡
VLD 0
s
V
VLD 0, V /dt 3 V/s (see Figure 10)
1.55
120
1.7
V
(SVSstart)
CC
VLD = 1
70
210
mV
V
V
/dt 3 V/s (see Figure 10)
V
V
(SVS_IT--)
x 0.016
CC
(SVS_IT--)
x 0.001
VLD = 2 .. 14
V
hys(SVS_IT-- )
/dt 3 V/s (see Figure 10), External voltage applied
CC
VLD = 15
4.4
20
mV
on A7
VLD = 1
VLD = 2
VLD = 3
VLD = 4
VLD = 5
VLD = 6
VLD = 7
VLD = 8
VLD = 9
VLD = 10
VLD = 11
VLD = 12
VLD = 13
VLD = 14
1.8
1.9
2.1
2.05
2.25
2.37
2.48
2.6
1.94
2.05
2.14
2.24
2.33
2.46
2.58
2.69
2.83
2.94
3.11
3.24
3.43
2.2
2.3
2.4
2.5
2.71
2.86
3
2.65
2.8
V
/dt 3 V/s (see Figure 10 and Figure 11)
CC
V
V
(SVS_IT--)
2.9
3.13
3.29
3.42
3.05
3.2
†
3.35
3.5
3.61
†
3.76
†
†
3.7
3.99
V
/dt 3 V/s (see Figure 10 and Figure 11), External
CC
VLD = 15
1.1
1.2
10
1.3
15
voltage applied on A7
I
CC(SVS)
VLD 0, V = 2.2 V/3 V
A
CC
(see Note 1)
†
‡
The recommended operating voltage range is limited to 3.6 V.
is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD 0 to a different VLD value somewhere
t
settle
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 1: The current consumption of the SVS module is not included in the I current consumption data.
CC
32
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
typical characteristics
Software sets VLD >0:
SVS is active
AV
CC
V
(SVS_IT--)
hys(SVS_IT--)
V
V
(SVSstart)
V
hys(B_IT--)
V
(B_IT--)
V
CC(start)
Brown-
out
Brownout
Region
Region
Brownout
1
0
t
t
SVS out
1
d(BOR)
d(BOR)
SVS Circuit is Active From VLD > to V < V(
CC
B_IT--)
0
t
t
d(SVSon)
d(SVSR)
Set POR
1
undefined
0
Figure 10. SVS Reset (SVSR) vs Supply Voltage
V
CC
t
pw
3 V
2
Rectangular Drop
V
CC(min)
1.5
1
Triangular Drop
1 ns
1 ns
V
t
CC
pw
0.5
0
3 V
1
10
100
1000
t
pw
-- Pulse Width -- s
V
CC(min)
t
f =
t
r
t
f
t
r
t -- Pulse Width -- s
Figure 11. VCC(min): Square Voltage Drop and Triangle Voltage Drop to Generate an SVS Signal (VLD = 1)
33
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
DCO
PARAMETER
TEST CONDITIONS
V
MIN
TYP
MAX
UNIT
CC
N
= 01E0h, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2,
(DCO)
f
2.2 V/3 V
1
MHz
(DCOCLK)
(DCO2)
DCOPLUS = 0
2.2 V
3 V
0.3
0.3
2.5
2.7
0.7
0.8
5.7
6.5
1.2
1.3
9
0.65
0.7
5.6
6.1
1.3
1.5
10.8
12.1
2
1.25
1.3
10.5
11.3
2.3
2.5
18
f
f
f
f
f
f
f
f
f
f
FN_8 = FN_4 = FN_3 = FN_2 = 0 , DCOPLUS = 1
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
2.2 V
3 V
FN_8 = FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1 (see Note 1)
FN_8 = FN_4 = FN_3 = 0, FN_2 = 1, DCOPLUS = 1
(DCO27)
(DCO2)
2.2 V
3 V
2.2 V
3 V
FN_8 = FN_4 = FN_3 = 0, FN_2 = 1, DCOPLUS = 1 (see Note 1)
FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1
FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1 (see Note 1)
FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1
FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1 (see Note 1)
FN_8 = 1, FN_4 = FN_3 = FN_2 = x, DCOPLUS = 1
(DCO27)
(DCO2)
20
2.2 V
3 V
3
2.2
15.5
17.9
2.8
3.4
21.5
26.6
4.2
6.3
32
3.5
25
2.2 V
3 V
(DCO27)
(DCO2)
10.3
1.8
2.1
13.5
16
28.5
4.2
5.2
33
2.2 V
3 V
2.2 V
3 V
(DCO27)
(DCO2)
41
2.2 V
3 V
2.8
4.2
21
6.2
9.2
46
2.2 V
3 V
FN_8 = 1,FN_4 = FN_3 = FN_2 = x, DCOPLUS = 1 (see Note 1)
Step size between adjacent DCO taps:
(DCO27)
30
46
70
1 < TAP 20
TAP = 27
2.2 V
3 V
1.06
1.07
–0.2
–0.2
1.11
1.17
–0.4
–0.4
S
n
S
= f
/ f (see Figure 13 for taps 21 to 27)
DCO(Tap n+1) DCO(Tap n)
n
–0.3
–0.3
Temperature drift, N
D = 2, DCOPLUS = 0 (see Note 2)
= 01E0h, FN_8 = FN_4 = FN_3 = FN_2 = 0
(DCO)
D
D
%_C
t
Drift with V variation, N = 01E0h, FN_8 = FN_4 = FN_3 =
FN_2 = 0, D = 2, DCOPLUS = 0 (see Note 2)
CC
(DCO)
0
5
15
%/V
V
NOTES: 1. Do not exceed the maximum system frequency.
2. This parameter is not production tested.
34
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
f
f
(DCO)
(DCO)
f
f
(DCO20 C)
(DCO3V)
1.0
1.0
0
1.8
2.4
3.0
3.6
-- 4 0
-- 2 0
0
20
40
60
85
V
-- V
T -- C
A
CC
Figure 12. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
35
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
1.17
Max
1.11
1.07
1.06
Min
1
20
27
DCO Tap
Figure 13. DCO Tap Step Size
Legend
Tolerance at Tap 27
DCO Frequency
Adjusted by Bits
9
5
2
to 2 in SCFI1 {N
}
{DCO}
Tolerance at Tap 2
Overlapping DCO Ranges:
Uninterrupted Frequency Range
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_3=x
FN_4=x
FN_8=1
Figure 14. Five Overlapping DCO Ranges Controlled by FN_x Bits
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
36
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
crystal oscillator, LFXT1, low frequency modes (see Note 4)
PARAMETER
TEST CONDITIONS
XTS = 0, LFXT1Sx = 0 or 1
XTS = 0, LFXT1Sx = 0,
V
MIN
TYP
MAX UNIT
CC
LFXT1 oscillator crystal
frequency, LF mode 0, 1
f
1.8 V to 3.6 V
32,768
Hz
LFXT1,LF
f
C
= 32,768 kHz,
= 6 pF
500
200
LFXT1,LF
L,eff
Oscillation allowance for
LF crystals
OA
kΩ
LF
XTS = 0, LFXT1Sx = 0,
= 32,768 kHz,
f
LFXT1,LF
C
L,eff
= 12 pF
XTS = 0, XCAPx = 0
XTS = 0, XCAPx = 1
XTS = 0, XCAPx = 2
XTS = 0, XCAPx = 3
1
5.5
8.5
11
Integrated effective load
capacitance, LF mode
(see Note 1)
C
L,eff
pF
XTS = 0,
Duty cycle, LF mode
Measured at P1.5/ACLK,
2.2 V/3 V
2.2 V/3 V
30
10
50
70
%
f
= 32,768Hz
LFXT1,LF
Oscillator fault frequency,
LF mode (see Note 3)
XTS = 0, XCAPx = 0.
LFXT1Sx = 3 (see Note 2)
f
10,000
Hz
Fault,LF
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Measured with logic level input frequency but also applies to operation with crystals.
3. Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
-- Keep the trace between the device and the crystal as short as possible.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
-- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
-- If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
-- Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
37
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
crystal oscillator, LFXT1, high frequency modes
PARAMETER
TEST CONDITIONS
Ceramic resonator
V
MIN
0.45
1
TYP
MAX UNIT
CC
f
f
LFXT1 oscillator crystal frequency
LFXT1 oscillator crystal frequency
1.8 V to 3.6 V
1.8 V to 3.6 V
8
8
MHz
MHz
LFXT1
LFXT1
Crystal resonator
Integrated effective load
capacitance, HF mode
(see Note 1)
C
(see Note 2)
1
pF
%
L,eff
Duty cycle
Measured at P1.5/ACLK,
2.2 V/3 V
40
50
60
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
crystal oscillator, XT2, high frequency modes
PARAMETER
TEST CONDITIONS
Ceramic resonator
V
MIN
0.45
1
TYP
MAX UNIT
CC
f
f
XT2 oscillator crystal frequency
XT2 oscillator crystal frequency
1.8 V to 3.6 V
1.8 V to 3.6 V
8
8
MHz
MHz
XT2
XT2
Crystal resonator
Integrated effective load
capacitance, HF mode
(see Note 1)
C
(see Note 2)
1
pF
%
L,eff
Duty cycle
Measured at P1.4/SMCLK,
2.2 V/3 V
40
50
60
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
38
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
RAM
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
VRAMh
CPU halted (see Note 1)
1.6
V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
LCD_A
PARAMETER
TEST CONDITIONS
V
MIN
2.2
4.7
TYP
MAX UNIT
CC
Charge pump enabled
(LCDCPEN = 1, VLCDx > 0000)
V
Supply Voltage Range
3.6
V
CC(LCD)
Charge pump enabled
(LCDCPEN = 1, VLCDx > 0000)
C
LCD
Capacitor on LCDCAP (see Note 1)
Average Supply Current (see Note 2)
F
V
= 3 V, LCDCPEN = 1,
LCD(typ)
VLCDx = 1000, All segments on,
I
f
2.2 V
3.8
A
CC(LCD)
LCD
f
=
f
/32, No LCD connected
A
LCD
ACLK
(see Note 3), T = 25C
LCD frequency
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
LCD voltage
1.1 kHz
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VLCDx = 0000
VLCDx = 0001
VLCDx = 0010
VLCDx = 0011
VLCDx = 0100
VLCDx = 0101
VLCDx = 0110
VLCDx = 0111
VLCDx = 1000
VLCDx = 1001
VLCDx = 1010
VLCDx = 1011
VLCDx = 1100
VLCDx = 1101
VLCDx = 1110
VLCDx = 1111
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
CC
2.60
2.66
2.72
2.78
2.84
2.90
2.96
3.02
3.08
3.14
3.20
3.26
3.32
3.38
3.44
3.60
10
V
V
3 V, LCDCPEN = 1,
LCD =
R
LCD Driver Output impedance
2.2 V
k
LCD
VLCDx = 1000, I
10 A
LOAD =
NOTES: 1. Enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device.
2. Refer to the supply current specifications I for additional current specifications with the LCD_A module active.
(LPM3)
3. Connecting an actual display will increase the current consumption depending on the size of the LCD.
39
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Comparator_A (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
25
MAX
40
UNIT
V
V
= 2.2 V
= 3 V
CC
CC
I
I
CAON = 1, CARSEL = 0, CAREF = 0
A
(CC)
45
30
60
50
CAON = 1, CARSEL = 0, CAREF =
1/2/3,
No load at P1.6/CA0 and P1.7/CA1
V
V
= 2.2 V
= 3 V
CC
CC
A
(Refladder/RefDiode)
45
80
Voltage @ 0.25 V
node
node
PCA0 = 1, CARSEL = 1, CAREF = 1,
No load at P1.6/CA0 and P1.7/CA1
CC
V
V
V
V
= 2.2 V / 3 V
= 2.2V / 3 V
0.23
0.47
0.24
0.25
(Ref025)
(Ref050)
CC
CC
V
CC
Voltage @ 0.5 V
PCA0 = 1, CARSEL = 1, CAREF = 2,
No load at P1.6/CA0 and P1.7/CA1
CC
0.48
0.5
V
CC
PCA0 = 1, CARSEL = 1, CAREF = 3,
No load at P1.6/CA0 and P1.7/CA1,
V
V
= 2.2 V
= 3 V
390
400
480
490
540
550
CC
CC
See Figure 15 and
Figure 16
V
V
mV
V
(RefVT)
IC
T
A =
85C
Common-mode input
voltage range
CAON = 1
V
= 2.2 V / 3 V
0
V
-- 1
30
CC
CC
V -- V
Offset voltage
See Note 2
CAON = 1
VCC = 2.2 V / 3 V
-- 3 0
0
mV
mV
p
S
V
Input hysteresis
V
= 2.2 V / 3 V
= 2.2 V
= 3 V
0.7
165
120
1.9
1.4
300
240
2.8
hys
CC
CC
CC
CC
CC
V
80
70
1.4
0.9
T
A
= 25C,
ns
Overdrive 10 mV, without filter: CAF = 0
V
t
, see Note 3
(response LH and HL)
V
V
= 2.2 V
= 3 V
T
A
= 25C
s
Overdrive 10 mV, with filter: CAF = 1
1.5
2.2
NOTES: 1. The leakage current for the Comparator_A terminals is identical to I
specification.
lkg(Px.x)
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
3. The response time is measured at P1.6/CA0 with an input voltage step and the Comparator_A already enabled (CAON = 1). If CAON
is set at the same time, a settling time of up to 300ns is added to the response time.
40
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
typical characteristics
REFERENCE VOLTAGE
vs
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
650
600
550
500
450
400
650
600
550
500
450
400
V
= 3 V
CC
V
= 2.2 V
CC
Typical
Typical
-- 4 5
-- 2 5
-- 5
1 5
3 5
5 5
7 5
9 5
-- 4 5
-- 2 5
-- 5
1 5
3 5
5 5
7 5
9 5
T
A
-- Free-Air Temperature -- C
T
A
-- Free-Air Temperature -- C
Figure 15. V(RefVT) vs Temperature
Figure 16. V(RefVT) vs Temperature
0 V
V
CC
CAF
0
1
CAON
To Internal
Modules
Low-Pass Filter
0
1
0
1
+
_
V+
V--
CAOUT
Set CAIFG
Flag
2 s
Figure 17. Block Diagram of Comparator_A Module
V
CAOUT
Overdrive
V--
400 mV
V+
t
(response)
Figure 18. Overdrive Definition
41
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16_A, power supply and recommended operating conditions
PARAMETER
TEST CONDITIONS
V
MIN
2.5
TYP
MAX
3.6
UNIT
CC
Analog supply
voltage
AV = DV
CC
SS
CC
SS
AV
V
CC
AV = DV = 0V
SD16BUFx = 00, GAIN: 1,2
SD16BUFx = 00, GAIN: 4,8,16
SD16BUFx = 00, GAIN: 32
3 V
3 V
3 V
750
1050
1150
1700
SD16LP = 0,
= 1 MHz,
SD16OSR = 256
830
f
SD16
1150
Analog supply
current including
internal reference
SD16LP = 1,
SD16BUFx = 00, GAIN: 1
SD16BUFx = 00, GAIN: 32
3 V
3 V
730
830
1030
1150
f
= 0.5 MHz,
SD16
ISD16
A
SD16OSR = 256
SD16BUFx = 01, GAIN: 1
SD16BUFx = 10, GAIN: 1
SD16BUFx = 11, GAIN: 1
3 V
3 V
3 V
850
1000
1130
SD16LP = 0,
SD16OSR = 256
Analog front-end
input clock
frequency
SD16LP = 0 (Low power mode disabled)
SD16LP = 1 (Low power mode enabled)
3 V
3 V
0.03
0.03
1
1.1
f
MHz
SD16
0.5
SD16_A, input range
PARAMETER
TEST CONDITIONS
SD16BUFx = 00
V
MIN
AV -0.1V
TYP
MAX
UNIT
CC
AV
CC
SS
Absolute input
V
V
V
I
voltage range
SD16BUFx > 00
AV +0.2V
SS
AV -- 1 . 2 V
CC
SD16BUFx = 00
AV -0.1V
SS
AV
CC
Common-mode
input voltage range
V
IC
SD16BUFx > 00
AV +0.2V
SS
AV -- 1 . 2 V
CC
Differential full
scale input voltage
range
Bipolar mode, SD16UNI = 0
Unipolar mode, SD16UNI = 1
-- V
/2GAIN
0
+V
+V
/2GAIN
/2GAIN
mV
mV
REF
REF
REF
V
ID,FSR
SD16GAINx = 1
SD16GAINx = 2
SD16GAINx = 4
500
250
125
62
31
15
200
75
Differential input
voltage range for
specified
performance
(see Note 1)
V
SD16REFON = 1
SD16GAINx = 8
mV
ID
SD16GAINx = 16
SD16GAINx = 32
SD16GAINx = 1
SD16GAINx = 32
3 V
3 V
f
= 1 MHz,
SD16
k
Input impedance
(one input pin to
SD16BUFx = 00
= 1 MHz,
Z
I
f
SD16
AV
)
SS
SD16GAINx = 1
3 V
10
M
SD16BUFx = 01
SD16GAINx = 1
SD16GAINx = 32
3 V
3 V
300
100
400
150
f
= 1 MHz,
SD16
k
Differential input
impedance (IN+ to
IN--)
SD16BUFx = 00
= 1 MHz,
Z
ID
f
SD16
SD16GAINx = 1
3 V
10
M
SD16BUFx > 00
NOTES: 1. The analog input range depends on the reference voltage applied to V
. If V
REF
is sourced externally, the full-scale range is defined
REF
by V
= +(V
/2)/GAIN and V
= --(V
/2)/GAIN. The analog input range should not exceed 80% of V
or V
.
FSR+
REF
FSR--
REF
FSR+
FSR--
42
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16_A, performance (fSD16 = 30kHz, SD16REFON = 1, SD16BUFx = 01)
PARAMETER
TEST CONDITIONS
V
MIN
TYP
84
MAX
UNIT
CC
SD16GAINx = 1,Signal Amplitude = 500mV
SD16OSRx = 256
3 V
3 V
SD16GAINx = 1,Signal Amplitude = 500mV
SD16OSRx = 512
Signal-to-noise +
distortion ratio
84
SINAD
f
= 2.8Hz
dB
IN
SD16GAINx = 1,Signal Amplitude = 500mV
SD16OSRx = 1024
3 V
3 V
3 V
84
1.00
15
Nominal gain
SD16GAINx = 1, SD16OSRx = 1024
0.97
1.02
Gain temperature
drift
dG/dT
SD16GAINx = 1, SD16OSRx = 1024 (see Note 1)
ppm/_C
Gain supply voltage SD16GAINx = 1, SD16OSRx = 1024, V = 2.5 V to 3.6 V
CC
dG/dV
0.35
%/V
CC
drift
(see Note 2)
NOTES: 1. Calculated using the box method: (MAX(--40...85_C) -- MIN(--40...85_C))/MIN(--40...85_C)/(85C -- (--40_C))
2. Calculated using the box method: (MAX(2.5...3.6V) -- MIN(2.5...3.6V))/MIN(2.5...3.6V)/(3.6V -- 2.5 V)
SD16_A, performance (fSD16 = 1MHz, SD16OSRx = 256, SD16REFON = 1, SD16BUFx = 00)
PARAMETER
TEST CONDITIONS
SD16GAINx = 1,Signal Amplitude = 500mV
SD16GAINx = 2,Signal Amplitude = 250mV
SD16GAINx = 4,Signal Amplitude = 125mV
SD16GAINx = 8,Signal Amplitude = 62mV
SD16GAINx = 16,Signal Amplitude = 31mV
SD16GAINx = 32,Signal Amplitude = 15mV
SD16GAINx = 1
V
MIN
83.5
81.5
76
TYP
85
MAX
UNIT
CC
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
84
79.5
76.5
73
Signal-to-noise +
distortion ratio
f
= 50Hz,
IN
SINAD
dB
100Hz
73
69
62
69
0.97
1.90
3.76
7.36
1.00
1.96
3.86
7.62
1.02
2.02
3.96
7.84
SD16GAINx = 2
SD16GAINx = 4
G
Nominal gain
Offset error
SD16GAINx = 8
SD16GAINx = 16
14.56 15.04 15.52
SD16GAINx = 32
27.20 28.35 29.76
SD16GAINx = 1
0.2
1.5
E
%FSR
OS
SD16GAINx = 32
Offset error
temperature
coefficient
SD16GAINx = 1
3 V
3 V
4
20
ppm
FSR/_C
dE /dT
OS
SD16GAINx = 32
20
100
SD16GAINx = 1, Common-mode input signal:
3 V
3 V
3 V
90
75
80
V
= 500 mV, f = 50 Hz, 100 Hz
ID
IN
Common-mode
rejection ratio
CMRR
PSRR
dB
dB
SD16GAINx = 32, Common-mode input signal:
= 16 mV, f = 50 Hz, 100 Hz
V
ID
IN
Power supply
rejection ratio
SD16GAINx = 1
NOTES: 1. Calculated using the box method: (MAX(--40...85_C) -- MIN(--40...85_C)) / MIN(--40...85_C) / (85_C -- (--40_C))
2. Calculated using the ADC output code and the box method:
(MAX-code(2.5...3.6V) -- MIN-code(2.5...3.6V)) / MIN-code(2.5...3.6V) / (3.6V -- 2.5 V)
43
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16_A, linearity (fSD16 = 1MHz, SD16REFON = 1, SD16BUFx = 00)
PARAMETER
TEST CONDITIONS
V
MIN
TYP
1.5
MAX
UNIT
CC
SD16OSR = 256, SD16GAINx = 000b,
Signal Amplitude = 500 mV
3 V
3 V
3 V
3 V
LSB
SD16OSR = 256, SD16GAINx = 101b,
Signal Amplitude = 15 mV
6
0.8
3.5
INL
Integral non-linearity
SD16OSR = 1024, SD16GAINx = 000b,
Signal Amplitude = 500 mV
LSB
SD16OSR = 1024, SD16GAINx = 101b,
Signal Amplitude = 15 mV
typical characteristics -- SD16_A SINAD performance over OSR
100.0
95.0
90.0
85.0
80.0
75.0
70.0
65.0
60.0
55.0
50.0
10.00
100.00
OSR
1000.00
Figure 19. SINAD performance over OSR, fSD16 = 1MHz, SD16REFON = 1, SD16GAINx = 1
SD16_A, temperature sensor and built-in VCC sense
PARAMETER
Sensor temperature
TEST CONDITIONS
V
MIN
TYP
MAX
UNIT
CC
TC
See Note 1
See Note 1
1.18
1.32
1.46 mV/K
Sensor
coefficient
V
Sensor offset voltage
--100
435
355
320
0.08
100
515
435
400
0.1
mV
Offset,sensor
Temperature sensor voltage at T = 85C
3 V
3 V
3 V
475
395
360
1/11
A
Sensor output voltage
(see Note 3)
Temperature sensor voltage at T = 25C
V
V
mV
V
A
Sensor
Temperature sensor voltage at T = 0C (see Note 1)
A
V
divider at input 5
f
= 32kHz, SD16OSRx = 256, SD16REFON = 1
SD16
CC,Sense
CC
NOTES: 1. Not production tested, limits characterized.
2. The following formula can be used to calculate the temperature sensor output voltage:
V
= TC
( 273 + T [C] ) + V
[mV]
Sensor,typ
Sensor
Offset,sensor
3. Results based on characterization and/or production test, not TC
or V
.
Offset,sensor
Sensor
44
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16_A, built-in voltage reference
PARAMETER
TEST CONDITIONS
V
MIN
TYP
MAX
UNIT
CC
Internal reference
voltage
V
SD16REFON = 1, SD16VMIDON = 0
3 V
1.14
1.20
1.26
V
REF
Reference supply
current
I
SD16REFON = 1, SD16VMIDON = 0
3 V
3 V
175
260
A
REF
TC
Temperature coefficient
SD16REFON = 1, SD16VMIDON = 0 (see Note 1)
SD16REFON = 1, SD16VMIDON = 0 (see Note 2)
18
50 ppm/K
nF
C
V
load capacitance
100
REF
REF
V
maximum load
REF(I)
I
t
SD16REFON = 1, SD16VMIDON = 0
3 V
200
nA
LOAD
current
SD16REFON = 0-->1, SD16VMIDON = 0,
Turn on time
3 V
3 V
5
ms
ON
C
REF
= 100nF
PSRR
Line regulation
SD16REFON = 1, SD16VMIDON = 0
100
uV/V
NOTES: 1. Calculated using the box method: (MAX(--40...85_C) -- MIN(--40...85_C))/MIN(--40...85_C)/(85C -- (--40_C))
2. There is no capacitance required on V
voltage noise.
. However, a capacitance of at least 100nF is recommended to reduce any reference
REF
SD16_A, reference output buffer
PARAMETER
TEST CONDITIONS
SD16REFON = 1, SD16VMIDON = 1
V
MIN
TYP
1.2
MAX
UNIT
CC
Reference buffer output
voltage
V
3 V
3 V
V
REF,BUF
Reference Supply +
I
Reference output buffer SD16REFON = 1, SD16VMIDON = 1
quiescent current
385
600
A
REF,BUF
Required load
capacitance on V
C
SD16REFON = 1, SD16VMIDON = 1
470
nF
mA
mV
s
REF(O)
REF
Maximum load current
on V
I
SD16REFON = 1, SD16VMIDON = 1
|I | = 0 to 1mA
3 V
3 V
3 V
1
LOAD,Max
REF
Maximum voltage
variation vs load current
-- 1 5
+15
LOAD
SD16REFON = 0-->1, SD16VMIDON = 1,
= 470nF
t
Turn on time
100
ON
C
REF
SD16_A, external reference input
PARAMETER
TEST CONDITIONS
V
MIN
1.0
TYP
MAX
1.5
UNIT
V
CC
V
Input voltage range
Input current
SD16REFON = 0
SD16REFON = 0
3 V
3 V
1.25
REF(I)
I
50
nA
REF(I)
45
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, supply specifications
PARAMETER
TEST CONDITIONS
V
MIN
TYP
MAX
UNIT
CC
AV
DV
,
CC
CC =
AV
Analog supply voltage
2.20
3.60
V
CC
AV = DV
= 0 V
SS
SS
DAC12AMPx = 2, DAC12IR = 0,
DAC12_xDAT = 0800h
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.7 V
50
50
110
110
DAC12AMPx = 2, DAC12IR = 1,
DAC12_xDAT = 0800h, V
AV
AV
AV
Supply current
REF,DAC12 =
CC
CC
CC
I
A
DD
(see Notes 1 and 2)
DAC12AMPx = 5, DAC12IR = 1,
DAC12_xDAT = 0800h, V
200
700
70
440
REF,DAC12 =
DAC12AMPx = 7, DAC12IR = 1,
DAC12_xDAT = 0800h, V
1500
REF,DAC12 =
Power supply rejection
ratio (see Notes 3 and 4)
DAC12_xDAT = 800h, V
= 1.2 V,
REF,DAC12
PSRR
dB
AV = 100 mV
CC
NOTES: 1. No load at the output pin assuming that the control bits for the shared pins are set properly.
2. Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input
specifications.
3. PSRR = 20*logAV /V
}.
CC
DAC12_xOUT
4.
V
is applied externally. The internal reference is not used.
REF
46
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (see Figure 20)
PARAMETER
Integral nonlinearity
TEST CONDITIONS
= 1.2 V or V = 2.5 V
V
MIN
TYP
MAX
UNIT
CC
V
REF,DAC12
REF,ext
INL
2.7 V
2.7 V
2.7 V
2.7 V
2.0
8.0
LSB
(see Note 1)
DAC12AMPx = 7, DAC12IR = 1
= 1.2 V
V
REF,ext
-- 1
0.4
0.4
0.4
+1.3
1.0
1.0
LSB
LSB
LSB
DAC12AMPx = 7, DAC12IR = 1
= 2.5 V
Differential nonlinearity
(see Note 1)
DNL
DNL
V
REF,ext
DAC12AMPx = 7, DAC12IR = 1
= 1.2 V
Differential nonlinearity
(see Note 1)
V
REF,DAC12
DAC12AMPx = 7, DAC12IR = 1
Offset voltage without
calibration
V
= 1.2 V
REF,DAC12
2.7 V
2.7 V
20
DAC12AMPx = 7, DAC12IR = 1
(see Notes 1, 2)
E
mV
O
Offset voltage with
calibration
V
= 1.2 V
REF,DAC12
2.5
DAC12AMPx = 7, DAC12IR = 1
(see Notes 1, 2)
Offset error temperature
coefficient (see Note 1)
d
/d
/d
2.7 V
2.7 V
2.7 V
30
V/C
E(O)
T
T
E
Gain error (see Note 1)
V
= 1.2 V
REF,DAC12
3.50 % FSR
G
Gain temperature
ppm of
FSR/C
d
10
E(G)
coefficient (see Note 1)
DAC12AMPx = 2
2.7 V
2.7 V
2.7 V
100
Time for offset calibration
(see Note 3)
DAC12AMPx = 3,5
DAC12AMPx = 4,6,7
32
6
t
ms
Offset_Cal
NOTES: 1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and
“b” of the first order equation: y = a + b*x. V = E + (1 + E ) * (V /4095) * DAC12_xDAT, DAC12IR = 1.
DAC12_xOUT
O
G
REF,DAC12
2. The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON
3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifieris switched off with DAC12AMPx
= {0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may
effect accuracy and is not recommended.
DAC V
OUT
DAC Output
V
R+
R
=
Load
Ideal transfer
function
AV
CC
2
Offset Error
Positive
Gain Error
DAC Code
C
= 100pF
Load
Negative
Figure 20. Linearity Test Load Conditions and Gain/Offset Definition
47
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (continued)
TYPICAL INL ERROR
vs
DIGITAL INPUT DATA
4
V
= 2.2 V, V
= 1.2 V
REF
CC
DAC12AMPx = 7
DAC12IR = 1
3
2
1
0
-- 1
-- 2
-- 3
-- 4
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT -- Digital Code
TYPICAL DNL ERROR
vs
DIGITAL INPUT DATA
2.0
1.5
V
= 2.2 V, V
= 1.2 V
REF
CC
DAC12AMPx = 7
DAC12IR = 1
1.0
0.5
0.0
-- 0 . 5
-- 1 . 0
-- 1 . 5
-- 2 . 0
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT -- Digital Code
48
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, output specifications
PARAMETER
TEST CONDITIONS
No Load, V = AV
V
MIN
TYP
MAX
UNIT
CC
,
CC
REF,DAC12
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
0
0.005
No Load, V
= AV
,
CC
REF,DAC12
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
AV --0.05
AV
CC
CC
Output voltage
range (see Note 1,
Figure 23)
V
V
O
R
Load
= 3 k, V
= AV
,
CC
REF,DAC12
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
0
0.1
R
Load
= 3 k, V
= AV
,
CC
REF,DAC12
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
2.2 V/3 V
2.2 V/3 V
AV --0.13
AV
CC
CC
Max DAC12 load
capacitance
C
100
pF
L(DAC12)
2.2V
3V
-- 0 . 5
-- 1 . 0
+0.5
+1.0
Max DAC12 load
current
I
mA
L(DAC12)
R
= 3 k, V
0.3 V,
O/P(DAC12)
Load
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
150
150
1
250
250
4
DAC12AMPx = 2, DAC12_xDAT = 0h
= 3 k, V AV -- 0 . 3 V
R
Load
Output resistance
(see Figure 23)
O/P(DAC12)
CC
R
O/P(DAC12)
DAC12_xDAT = 0FFFh
= 3 k,
R
Load
0.3V V
AV -- 0.3V
CC
O/P(DAC12)
NOTES: 1. Data is valid after the offset calibration of the output amplifier.
R
O/P(DAC12_x)
Max
R
Load
I
Load
AV
CC
DAC12
2
C
= 100pF
O/P(DAC12_x)
Min
Load
0.3
AV
--0.3V
V
CC
OUT
AV
CC
Figure 23. DAC12_x Output Resistance Tests
49
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
12-bit DAC, reference input specifications
PARAMETER
TEST CONDITIONS
DAC12IR = 0 (see Notes 1 and 2)
DAC12IR = 1 (see Notes 3 and 4)
V
MIN
TYP
MAX
UNIT
CC
2.2 V/3 V
2.2 V/3 V
AV /3 AV +0.2
Reference input
voltage range
CC
CC
V
V
REF
AV
AV +0.2
CC
CC
DAC12IR = 0, SD16VMIDON = 1
(see Note 5)
2.2 V/3 V
2.2 V/3 V
20
40
M
k
Reference input
resistance
Ri
(VREF)
DAC12IR = 1, SD16VMIDON = 1
48
56
NOTES: 1. For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AV ).
CC
2. The maximum voltage applied at reference input voltage terminal V
= [AV -- V
] / [3*(1 + E )].
E(O) G
REF
CC
3. For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AV ).
CC
4. The maximum voltage applied at reference input voltage terminal V
5. Characterized, not production tested
= [AV -- V
] / (1 + E ).
E(O) G
REF
CC
12-bit DAC, dynamic specifications (VREF,DAC12 = AVCC, DAC12IR = 1) (see Figure 24 and Figure 25)
PARAMETER
TEST CONDITIONS
DAC12AMPx = 0 {2, 3, 4}
V
MIN
TYP
60
15
6
MAX
120
30
UNIT
CC
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
DAC12_xDAT = 800h,
Error < 0.5 LSB
DAC12
on-time
DAC12AMPx = 0 {5, 6}
DAC12AMPx = 0 7
DAC12AMPx = 2
t
t
t
s
V(O)
ON
(see Note 1, Figure 24)
12
100
40
15
5
200
80
Settling
DAC12_xDAT =
DAC12AMPx = 3,5
DAC12AMPx = 4,6,7
DAC12AMPx = 2
s
s
S(FS)
time,full-scale 80h F7Fh 80h
30
DAC12_xDAT =
Settling time,
DAC12AMPx = 3,5
DAC12AMPx = 4,6,7
DAC12AMPx = 2
2
3F8h 408h 3F8h
code to code
S(C-C)
BF8h C08h BF8h
1
0.05
0.35
1.5
0.12
0.7
2.7
600
150
30
DAC12_xDAT =
DAC12AMPx = 3,5
DAC12AMPx = 4,6,7
DAC12AMPx = 2
SR
Slew Rate
V/s
nV-s
80h F7Fh 80h
DAC12_xDAT =
DAC12AMPx = 3,5
DAC12AMPx = 4,6,7
Glitch energy: full-scale
80h F7Fh 80h
NOTES: 1.
R
Load
and C
connected to AV (not AV /2) in Figure 24.
Load SS CC
2. Slew rate applies to output voltage steps > = 200 mV.
Conversion 1
Conversion 2
Conversion 3
+/-- 1/2 LSB
V
+/-- 1/2 LSB
DAC Output
OUT
Glitch
Energy
R
= 3 k
Load
I
Load
AV
CC
2
C
= 100pF
Load
R
O/P(DAC12.x)
t
t
settleHL
settleLH
Figure 24. Settling Time and Glitch Energy Testing
50
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
Conversion 1
Conversion 2
Conversion 3
V
OUT
90%
90%
10%
10%
t
t
SRHL
SRLH
Figure 25. Slew Rate Testing
12-bit DAC, dynamic specifications continued (TA = 25C unless otherwise noted)
PARAMETER
TEST CONDITIONS
V
MIN
MAX
UNIT
CC
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2, DAC12IR = 1,
DAC12_xDAT = 800h
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
40
3-dB bandwidth,
DAC12AMPx = {5, 6}, DAC12SREFx = 2, DAC12IR = 1,
DAC12_xDAT = 800h
V
= 1.5 V,
DC
180
550
BW
kHz
--3dB
V
AC
= 0.1V
PP
(see Figure 26)
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
NOTES: 1.
R
LOAD
= 3 k, C
= 100 pF
LOAD
R
= 3 k
Load
I
Load
Ve
REF+
AV
CC
DAC12_x
2
DACx
AC
DC
C
= 100pF
Load
Figure 26. Test Conditions for 3-dB Bandwidth Specification
51
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
operational amplifier OA, supply specifications
PARAMETER
TEST CONDITIONS
V
MIN
TYP
MAX
3.6
UNIT
CC
V
Supply voltage range
2.2
V
CC
Fast Mode
180
110
50
290
190
80
Medium Mode
Slow Mode
I
Supply current (see Note 1)
Power supply rejection ratio
2.2 V/3 V
2.2 V/3 V
A
CC
PSRR
Non-inverting
70
dB
NOTES: 1. Corresponding pins configured as OA inputs and outputs respectively.
operational amplifier OA, input/output specification
PARAMETER
TEST CONDITIONS
V
MIN
-- 0 . 1
-- 5
TYP
MAX
UNIT
CC
V
Input voltage range
V
-- 1 . 2
5
V
I/P
CC
T
= --40 to +55_C
0.5
5
A
Input leakage current
(see Notes 1 and 2)
I
2.2 V/3 V
nA
Ikg
T
A
= +55 to +85_C
-- 2 0
20
Fast Mode
50
Medium Mode
Slow Mode
Fast Mode
80
f
= 1 kHz
V(I/P)
140
30
V
V
Voltage noise density, I/P
nV/Hz
n
Medium Mode
Slow Mode
50
f
= 10 kHz
V(I/P)
65
Offset voltage, I/P
2.2 V/3 V
2.2 V/3 V
10
mV
IO
Offset temperature drift, I/P
see Note 3
10
V/C
Offset voltage drift
with supply, I/P
0.3 V V V -- 1 . 0 V
IN CC
2.2 V/3 V
2.2 V/3 V
1.5
mV/V
V
V 10%, T = 25C
CC
A
Fast Mode, I
--500 A
--150 A
+500 A
+150 A
V
V
-- 0 . 2
-- 0 . 1
V
V
SOURCE
CC
CC
CC
CC
V
V
High-level output voltage, O/P
OH
OL
Slow Mode, I
SOURCE
SOURCE
Fast Mode, I
V
V
0.2
0.1
SS
SS
Low-level output voltage, O/P
Common-mode rejection ratio
2.2 V/3 V
2.2 V/3 V
V
Slow Mode, I
Noninverting
SOURCE
CMRR
70
dB
NOTES: 1. ESD damage can degrade input current leakage.
2. The input bias current is overridden by the input leakage current.
3. Calculated using the box method
4. Specification valid for voltage-follower OAx configuration
52
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
operational amplifier OA, dynamic specifications
PARAMETER
TEST CONDITIONS
Fast Mode
V
MIN
TYP
1.2
MAX
UNIT
CC
Medium Mode
Slow Mode
0.8
0.3
100
60
SR
Slew rate
V/s
Open-loop voltage gain
Phase margin
dB
deg
dB
m
C
C
= 50 pF
= 50 pF
L
Gain margin
20
L
Noninverting, Fast Mode,
= 47 k, C = 50 pF
2.2
1.4
R
L
L
Noninverting, Medium Mode,
= 300 k, C = 50pF
Gain-bandwidth product
(see Figure 27 and Figure 28)
GBW
2.2 V/3 V
MHz
R
L
L
Non-inverting, Slow Mode,
0.5
10
R
L
= 300 k, C = 50pF
L
t
t
Enable time on
Enable time off
t
, Noninverting, Gain = 1
on
2.2 V/3 V
2.2 V/3 V
20
s
s
en(on)
en(off)
1
TYPICAL PHASE vs FREQUENCY
TYPICAL OPEN-LOOP GAIN vs FREQUENCY
0
-- 5 0
140
120
100
80
Fast Mode
Fast Mode
60
--100
--150
--200
--250
40
Medium Mode
20
Medium Mode
Slow Mode
0
Slow Mode
-- 2 0
-- 4 0
-- 6 0
-- 8 0
1
10
100
1000
10000
100000
1
10
100
1000
10000
100000
Input Frequency -- kHz
Input Frequency -- kHz
Figure 27
Figure 28
53
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
switches between OA terminals and pins
PARAMETER
TEST CONDITIONS
V
MIN
TYP
MAX
3.6
UNIT
CC
V
Supply voltage range
--
2.2
V
CC
T
= --40C to 55C
= 55C to 85C
1
10
50
100
A
Input leakage current
(see Note 1)
I
I
nA
lkg
IN
T
A
Input current
Input switched to ON
= 100 A
0
A
k
R
On resistance
I
1
ON
IN
NOTES: 1. ESD damage can degrade input current leakage.
typical characteristics
RON vs VCOM
RON vs VCOM
3000.0
1700.0
1600.0
1500.0
1400.0
1300.0
1200.0
1100.0
1000.0
900.0
2750.0
Typical
V
= 3V
CC
Typical
T
= 25C
A
2500.0
2250.0
2000.0
1750.0
1500.0
1250.0
1000.0
750.0
V
= 2.2 V
CC
V
= 2.7 V
CC
V
= 3 V
CC
V
= 3.6 V
CC
T
= 85C
= 25C
A
T
A
T
A
= --40C
500.0
800.0
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6
V
-- Common Mode Input Voltage (V)
V
-- Common Mode Input Voltage (V)
COM
COM
Figure 29
Figure 30
54
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
Timer_A
PARAMETER
TEST CONDITIONS
Internal: SMCLK, ACLK,
External: TACLK, INCLK,
V
MIN
MAX UNIT
CC
2.2 V
3 V
8
f
t
Timer_A clock frequency
Timer_A, capture timing
MHz
10
TA
Duty cycle = 50% 10%
TA0, TA1, TA2
2.2 V/3 V
20
ns
TA,cap
Timer_B
PARAMETER
TEST CONDITIONS
V
MIN
MAX UNIT
CC
Internal: SMCLK, ACLK,
External: TBCLK,
Duty cycle = 50% 10%
2.2 V
3 V
8
f
Timer_B clock frequency
Timer_B, capture timing
MHz
10
TB
t
TB0, TB1, TB2
2.2 V/3 V
20
ns
TB,cap
55
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (UART mode)
PARAMETER
TEST CONDITIONS
V
MIN
TYP
MAX UNIT
CC
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% 10%
f
USCI input clock frequency
f
MHz
MHz
USCI
SYSTEM
Maximum BITCLK clock frequency
(equals baudrate in MBaud) (see
Note 1)
fmax,
2.2V /3 V
2
BITCLK
2.2 V
3 V
50
50
150
100
ns
ns
UART receive deglitch time
(see Note NO TAG)
t
NOTES: 1. The DCO wake-up time must be considered in LPM3/4 for baudrates above 1 MHz.
2. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed.
USCI (SPI master mode) (see Figure 31 and Figure 32)
PARAMETER
TEST CONDITIONS
SMCLK, ACLKm
Duty cycle = 50% 10%
V
MIN
MAX UNIT
CC
f
t
t
t
USCI input clock frequency
f
MHz
USCI
SYSTEM
2.2 V
3 V
110
75
0
ns
ns
ns
ns
ns
ns
SOMI input data setup time
SOMI input data hold time
SU,MI
2.2 V
3 V
HD,MI
0
2.2 V
3 V
30
20
SIMO output data valid time
UCLK edge to SIMO valid, C = 20 pF
L
VALID,MO
1
NOTE: fUCxCLK
=
with tLO∕HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
2tLO∕HI
For the slave’s parameters t
and t
refer to the SPI parameters of the attached slave.
VALID,SO(Slave)
SU,SI(Slave)
USCI (SPI slave mode) (see Figure 33 and Figure 34)
PARAMETER
TEST CONDITIONS
V
MIN
TYP
MAX UNIT
CC
STE lead time
STE low to clock
t
t
t
t
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
50
ns
STE,LEAD
STE,LAG
STE,ACC
STE,DIS
STE lag time
Last clock to STE high
10
ns
ns
ns
STE access time
STE low to SOMI data out
50
50
STE disable time
STE high to SOMI high impedance
2.2 V
3 V
20
15
10
10
ns
ns
ns
ns
t
t
t
SIMO input data setup time
SIMO input data hold time
SU,SI
2.2 V
3 V
HD,SI
2.2 V
3 V
75
50
110
75
ns
ns
UCLK edge to SOMI valid,
= 20 pF
SOMI output data valid time
VALID,SO
C
L
1
NOTE: fUCxCLK
=
with tLO∕HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
2tLO∕HI
For the master’s parameters t
and t
refer to the SPI parameters of the attached master.
VALID,MO(Master)
SU,MI(Master)
56
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
1/f
UCxCLK
CKPL=0
CKPL=1
UCLK
t
t
t
LO/HI
LO/HI
SU,MI
t
HD,MI
SOMI
SIMO
t
VALID,MO
Figure 31. SPI Master Mode, CKPH = 0
1/f
UCxCLK
CKPL=0
CKPL=1
UCLK
t
t
LO/HI
LO/HI
t
HD,MI
t
SU,MI
SOMI
SIMO
t
VALID,MO
Figure 32. SPI Master Mode, CKPH = 1
57
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
t
t
STE,LAG
STE,LEAD
STE
1/f
UCxCLK
CKPL=0
CKPL=1
UCLK
t
t
t
LO/HI
LO/HI
SU,SI
t
HD,SI
SIMO
SOMI
t
t
t
STE,DIS
STE,ACC
VALID,SO
Figure 33. SPI Slave Mode, CKPH = 0
t
t
STE,LAG
STE,LEAD
STE
1/f
UCxCLK
CKPL=0
CKPL=1
UCLK
t
t
LO/HI
LO/HI
t
HD,SI
t
SU,SI
SIMO
SOMI
t
t
t
STE,DIS
STE,ACC
VALID,SO
Figure 34. SPI Slave Mode, CKPH = 1
58
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (I2C mode) (see Figure 35)
PARAMETER
TEST CONDITIONS
V
MIN
TYP
MAX UNIT
MHz
CC
Internal: SMCLK, ACLK
External: UCLK
f
USCI input clock frequency
f
SYSTEM
USCI
Duty cycle = 50% 10%
f
t
SCL clock frequency
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V
0
4.0
0.6
4.7
0.6
0
400 kHz
SCL
f
f
f
f
100kHz
> 100kHz
100kHz
> 100kHz
s
s
s
s
ns
ns
s
SCL
SCL
SCL
SCL
Hold time (repeated) START
HD,STA
t
Setup time for a repeated START
SU,STA
t
t
t
Data hold time
HD,DAT
SU,DAT
SU,STO
Data setup time
Setup time for STOP
250
4.0
50
150
100
600
600
ns
ns
Pulse width of spikes suppressed by
input filter
t
SP
3 V
50
t
t
t
SU,STA HD,STA
HD,STA
SDA
SCL
1/f
t
SP
SCL
t
t
SU,STO
SU,DAT
t
HD,DAT
Figure 35. I2C Mode Timing
59
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
flash memory
TEST
CONDITIONS
PARAMETER
V
MIN
TYP
MAX
UNIT
CC
V
CC(PGM/
ERASE)
Program and Erase supply voltage
Flash Timing Generator frequency
2.2
3.6
V
f
I
I
t
t
257
476
5
kHz
mA
FTG
Supply current from DV during program
2.5 V/3.6V
2.5 V/3.6V
2.5 V/3.6V
2.5 V/3.6V
3
3
PGM
CC
Supply current from DV during erase
CC
7
mA
ERASE
CPT
Cumulative program time
Cumulative mass erase time
Program/Erase endurance
Data retention duration
see Note 1
see Note 2
10
ms
200
ms
CMErase
4
5
10
10
cycles
years
t
T = 25C
J
100
Retention
t
t
t
t
t
t
Word or byte program time
35
30
Word
st
Block program time for 1 byte or word
Block, 0
Block program time for each additional byte or word
Block program end-sequence wait time
Mass erase time
21
Block, 1-63
Block, End
Mass Erase
Seg Erase
see Note 3
t
FTG
6
5297
4819
Segment erase time
NOTES: 1. The cumulative program time must not be exceeded when writingto a64--byte flashblock. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/f ,max = 5297x1/476kHz). To
FTG
achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controller’s state machine (t
= 1/f
).
FTG
FTG
JTAG interface
TEST
CONDITIONS
PARAMETER
V
MIN
TYP
MAX
UNIT
CC
2.2 V
3 V
0
0
5
10
90
MHz
MHz
k
f
TCK input frequency
See Note 1
TCK
R
Internal pull-up resistance on TMS, TCK, TDI/TCLK See Note 2
may be restricted to meet the timing requirements of the module selected.
2.2 V/ 3 V
25
60
Internal
NOTES: 1.
f
TCK
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
V
MIN
MAX
UNIT
CC
V
V
Supply voltage during fuse-blow condition
Voltage level on TDI/TCLK for fuse-blow: F versions
Supply current into TDI/TCLK during fuse blow
Time to blow fuse
T
A
= 25C
2.5
6
V
V
CC(FB)
FB
7
100
1
I
t
mA
ms
FB
FB
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
60
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P1 pin schematic: P1.0, input/output with Schmitt trigger
CAPD.0
P1DIR.0
0
1
Direction
0: Input
1: Output
Pad Logic
P1SEL2.0
Module X OUT
0
1
1
0
P1OUT.0
P1SEL.0
P1.0/TA0/OA0RFB
Bus
Keeper
EN
P1IN.0
EN
Module X IN
P1IRQ.0
D
P1IE.0
EN
Set
Q
SWCTL1.SWCTL8
P1IFG.0
OA0
P1SEL.0
P1IES.0
Interrupt
Edge Select
Port P1 (P1.0) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
CAPD.x
P1DIR.x
P1SEL.x
P1SEL2.x
P1.0/TA0/OA0RFB
0
P1.x (I/O)
0
0
0
x
I: 0, O: 1
0
1
1
1
0
0
0
1
Timer_A3.CCI0A
Timer_A3.TA0
OA0RFB
0
1
x
61
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P1 pin schematic: P1.1, input/output with Schmitt trigger
CAPD.1
Direction
0: Input
1: Output
Pad Logic
P1DIR.1
0
1
P1SEL2.1
Module X OUT
0
1
1
0
MCLK
P1OUT.1
P1.1/TA0/MCLK/
OA1RFB
Bus
Keeper
EN
P1SEL.1
P1IN.1
EN
Module X IN
P1IRQ.1
D
P1IE.1
EN
Set
Q
SWCTL1.SWCTL12
P1IFG.1
OA1
P1SEL.1
P1IES.1
Interrupt
Edge Select
Port P1 (P1.1) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
CAPD.x
P1DIR.x
P1SEL.x
P1SEL2.x
P1.1/TA0/MCLK
OA1RFB
1
P1.x (I/O)
0
0
0
x
0
I: 0, O: 1
0
1
1
1
1
0
0
0
1
1
Timer_A3.CCI0A
Timer_A3.TA0
OA1RFB
0
1
0
1
MCLK
62
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P1 pin schematic: P1.2 input/output with Schmitt trigger
INCH
Pad Logic
1
A4-
DVSS
0
SD16AE.2
CAPD.2
0
1
P1DIR.2
Direction
0: Input
1: Output
0
1
P1OUT.2
Module X OUT
P1.2/TA1/A4-/OA0I3
Bus
Keeper
EN
P1SEL.2
P1IN.2
EN
D
Module X IN
P1IRQ.2
P1IE.2
EN
Set
Q
OA0
P1IFG.2
P1SEL.2
P1IES.2
Interrupt
Edge Select
Port P1 (P1.2) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
P1SEL2.x = 0 P1SEL2.x = 0
CAPD.x
P1DIR.x
P1SEL.x
OAN (OA0)
SD16AE.x
P1.2/TA1/A4--/OA0I3
2
P1.x (I/O)
0
0
0
x
x
I: 0, O: 1
0
1
1
x
x
xx
xx
xx
xx
10
0
0
0
1
1
Timer_A3.CCI1A
Timer_A3.TA1
A4--
0
1
x
x
OA0I3
NOTES: 1. x: Don’t care.
63
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P1 pin schematic: P1.3, input/output with Schmitt trigger
INCH =4
A4+
Pad Logic
SD16AE.3
CAPD.3
0
1
P1DIR.3
Direction
0: Input
1: Output
0
1
P1OUT.3
Module X OUT
P1.3/TBOUTH/
SVSOUT/A4+/OA1I3
Bus
Keeper
EN
P1SEL.3
P1IN.3
EN
D
Module X IN
P1IRQ.3
P1IE.3
EN
Set
Q
OA1
P1IFG.3
P1SEL.3
P1IES.3
Interrupt
Edge Select
Port P1 (P1.3) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
P1SEL2.x = 0 P1SEL2.x = 0
CAPD.x
P1DIR.x
P1SEL.x
OAN (OA1)
SD16AE.x
P1.3/TBOUTH/
SVSOUT/A4+/OA1I3
3
P1.x (I/O)
0
0
0
x
x
I: 0, O: 1
0
1
1
x
x
xx
xx
xx
xx
10
0
0
0
1
1
TBOUTH
SVSOUT
A4+
0
1
x
x
OA1I3
NOTES: 1. x: Don’t care.
64
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P1 pin schematic: P1.4, input/output with Schmitt trigger
Pad Logic
DAC12_1OUT
DAC12OPS
INCH=3
1
A3-
0
DVSS
SD16AE.4
CAPD.4
P1DIR.4
0
1
Direction
0: Input
1: Output
P1OUT.4
0
1
Module X OUT
P1.4/TBCLK/
SMCLK/A3-/
OA1I0/DAC1
Bus
Keeper
EN
P1SEL.4
P1IN.4
EN
D
Module X IN
P1IRQ.4
P1IE.4
EN
Set
Q
OA1
P1IFG.4
P1SEL.4
P1IES.4
Interrupt
Edge Select
Port P1 (P1.4) pin functions
CONTROL BITS / SIGNALS
P1SEL2.x = 0 P1SEL2.x = 0
P1SEL2.x = 0
DAC12OPS
(DAC12_1)
PIN NAME (P1.X)
X
FUNCTION
CAPD.x
P1DIR.x
P1SEL.x
SD16AE.x
OAP (OA1)
P1.4TBCLK/SMCLK/
A3--/OA1I0/DAC1
4
P1.x (I/O)
I: 0, O: 1
0
1
1
x
x
x
0
0
0
1
1
x
xx
xx
xx
xx
00
xx
0
0
0
0
0
1
TBCLK
SMCLK
A3--
0
1
x
x
x
OA1I0
DAC1
NOTES: 1. x: Don’t care.
65
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P1 pin schematic: P1.5, input/output with Schmitt trigger
INCH =3
Pad Logic
Ax+
SD16AE.5
CAPD.5
0
1
P1DIR.5
Direction
0: Input
1: Output
0
1
P1OUT.5
Module X OUT
P1.5/TACLK/ACLK/A3+
Bus
Keeper
EN
P1SEL.5
P1IN.5
EN
D
Module X IN
P1IRQ.5
P1IE.5
EN
Set
Q
P1IFG.5
P1SEL.5
P1IES.5
Interrupt
Edge Select
Port P1 (P1.5) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
P1SEL2.x = 0
SD16AE.x
CAPD.x
P1DIR.x
P1SEL.x
P1.5/TACLK/ACLK/
A3+
5
P1.x (I/O)
0
0
0
x
I: 0, O: 1
0
1
1
x
0
0
0
1
TACLK
ACLK
A3+
0
1
x
NOTES: 1. x: Don’t care.
66
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P1 pin schematic: P1.6, input/output with Schmitt trigger
Pad Logic
To Comparator_A
From Comparator_A
CAPD.6
DAC12_0OUT
DAC12OPS
1
A2-
DVSS
0
INCH=2
SD16AE.6
P1DIR.6
0
1
Direction
0: Input
1: Output
P1OUT.6
0/1
0
1
P1.6/CA0/A2-/
OA0I0/DAC0
Bus
Keeper
EN
P1SEL.6
P1IN.6
EN
D
Module X IN
P1IRQ.6
P1IE.6
EN
Set
Q
OA0
P1IFG.6
P1SEL.6
P1IES.6
Interrupt
Edge Select
67
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
Port P1 (P1.6) pin functions
CONTROL BITS / SIGNALS
P1SEL2.x = 0
DAC12OPS
(DAC12_0)
PIN NAME (P1.X)
X
FUNCTION
P1SEL2.x = 0
CAPD.x
P1SEL2.x = 0 P1SEL2.x = 0
P1DIR.x
P1SEL.x
SD16AE.x
OAP (OA0)
P1.6/CA0/A2--/OA0I0/
DAC0
6
P1.x (I/O)
CA0
I: 0, O: 1
0
x
x
x
x
0
0
x
1
x
x
xx
xx
xx
00
xx
0
x
x
x
1
x
x
x
x
1 or selected
A2--
x
x
x
OA0I0
DAC0
NOTES: 1. x: Don’t care.
68
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P1 pin schematic: P1.7, input/output with Schmitt trigger
Pad Logic
To Comparator_A
From Comparator_A
CAPD.7
SD16AE.7
INCH=2
A2+
P1DIR.7
0
1
Direction
0: Input
1: Output
P1OUT.7
0/1
0
1
P1.7/CA1/A2+
Bus
Keeper
EN
P1SEL.7
P1IN.7
EN
D
Module X IN
P1IRQ.7
P1IE.7
EN
Set
Q
P1IFG.7
P1SEL.7
P1IES.7
Interrupt
Edge Select
Port P1 (P1.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
P1SEL2.x = 0
P1SEL.x
P1SEL2.x = 0
SD16AE.x
P1DIR.x
CAPD.x
P1.7/CA1/A2+
7
P1.x (I/O)
CA1
I: 0, O: 1
0
x
x
0
0
x
1
x
x
1 or selected
x
A2+
NOTES: 1. x: Don’t care.
69
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P2 pin schematic: P2.0 to P2.1, input/output with Schmitt trigger
Pad Logic
LCDS0
Segment Sx
P2DIR.x
0
1
Direction
0: Input
1: Output
P2OUT.x
0
1
Module X OUT
P2.0/TA2/S1
P2.1/TB0/S0
Bus
Keeper
EN
P2SEL.x
P2IN.x
EN
Module X IN
P2IRQ.x
D
P2IE.x
EN
Set
Q
P2IFG.x
P2SEL.x
P2IES.x
Interrupt
Edge Select
Port P2 (P2.0 to P2.1) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.X)
X
FUNCTION
P2DIR.x
P2SEL.x
LCDS0
P2.0/TA2/S1
0
P2.x (I/O)
I: 0, O: 1
0
1
1
x
0
1
1
x
0
0
0
1
0
0
0
1
Timer_A3.CCI2A
Timer_A3.TA2
S1
0
1
x
P2.1/TB0/S0
1
P2.x (I/O)
I: 0, O: 1
Timer_B3.CCI0A
Timer_B3.TB0
S0
0
1
x
NOTES: 1. x: Don’t care.
70
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P2 pin schematic: P2.2 to P2.3, input/output with Schmitt trigger
P2DIR.x
0
1
Direction
0: Input
1: Output
Pad Logic
Module X OUT
P2OUT.x
0
1
P2.2/TB1
P2.3/TB2
P2SEL.x
P2IN.x
EN
Module X IN
P2IRQ.x
D
P2IE.x
EN
Set
Q
P2IFG.x
P2SEL.x
P2IES.x
Interrupt
Edge Select
Port P2 (P2.2 to P2.3) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.X)
X
FUNCTION
P2DIR.x
P2SEL.x
P2.2/TB1
2
P2.x (I/O)
I: 0, O: 1
0
1
1
0
1
1
Timer_B3.CCI1A
Timer_B3.TB1
P2.x (I/O)
0
1
P2.3/TB2
3
I: 0, O: 1
Timer_B3.CCI2A
TimerB3.TB2
0
1
71
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P2 pin schematic: P2.4 and P2.5, input/output with Schmitt trigger
P2DIR.x
0
1
Direction
0: Input
1: Output
Pad Logic
Module
direction
P2OUT.x
0
1
Module X OUT
P2.4/UCA0TXD/UCA0SIMO
P2.5/UCA0RXD/UCA0SOMI
P2SEL.x
P2IN.x
EN
Module X IN
P2IRQ.x
D
P2IE.x
EN
Set
Q
P2IFG.x
P2SEL.x
P2IES.x
Interrupt
Edge Select
Port P2 (P2.4 and P2.5) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.X)
X
FUNCTION
P2DIR.x
P2SEL.x
P2.4/UCA0TXD/
UCA0SIMO
4
P2.x (I/O)
I: 0, O: 1
0
1
0
1
UCA0TXD/UCA0SIMO (see Notes 2)
P2.x (I/O)
x
I: 0, O: 1
x
P2.5/UCA0RXD/
UCA0SOMI
5
UCA0RXD/UCA0SOMI (see Notes 2)
NOTES: 1. x: Don’t care.
2. The pin direction is controlled by the USCI module.
72
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P2 pin schematic: P2.6 and P2.7, inpututput with Schmitt trigger
LCDS0
Pad Logic
Segment Sy
P2DIR.x
0
1
Direction
0: Input
1: Output
P2OUT.x
0/1
0
1
P2.6/CAOUT/S2
P2.7/S3
Bus
Keeper
EN
P2SEL.x
P2IN.x
P2IE.x
EN
Set
P2IRQ.x
Q
P2IFG.x
P2SEL.x
P2IES.x
Interrupt
Edge Select
Port P2 (P2.6 and P2.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.X)
X
FUNCTION
P2DIR.x
P2SEL.x
LCDS0
P2.6/CAOUT/S2
6
P2.x (I/O)
CAOUT
S2
I: 0, O: 1
0
1
x
0
1
x
0
0
1
0
0
1
1
x
P2.7/S3
7
P2.x (I/O)
I: 0, O: 1
V
1
x
ss
S3
NOTES: 1. x: Don’t care.
73
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P3 pin schematic: P3.0 and P3.3, input/output with Schmitt trigger
Pad Logic
P3DIR.x
0
1
Direction
0: Input
1: Output
Module
direction
P3OUT.x
0
1
Module X OUT
P3.0/UCB0STE/UCA0CLK
P3.3/UCB0CLK/UCA0STE
P3SEL.x
P3IN.x
EN
D
Module X IN
Port P3 (P3.0 and P3.3) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P3.X)
X
FUNCTION
P3DIR.x
P3SEL.x
P3.0/UCB0STE/
UCA0CLK
0
P3.x (I/O)
I: 0, O: 1
0
1
0
1
UCB0STE/UCA0CLK (see Note 2)
P3.x (I/O)
x
I: 0, O: 1
x
P3.3/UCB0CLK/
UCA0STE
3
UCB0CLK/UCA0STE (see Note 2)
NOTES: 1. x: Don’t care.
2. The pin direction is controlled by the USCI module.
74
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P3 pin schematic: P3.1 and P3.2, input/output with Schmitt trigger
Pad Logic
LCDS24
Segment Sy
P3DIR.x
0
1
Direction
0: Input
1: Output
Module
direction
P3OUT.x
0
1
Module X OUT
P3.1/UCB0SIMO/UCB0SDA/S26
P3.2/UCB0SOMI/UCB0SCL/S27
Bus
Keeper
EN
P3SEL.x
P3IN.x
EN
D
Module X IN
Port P3 (P3.1 and P3.2) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P3.X)
X
FUNCTION
P3DIR.x
P3SEL.x
LCDS24
P3.1/UCB0SIMO/
UCB0SDA/S26
1
P3.x (I/O)
I: 0, O: 1
0
1
x
0
1
x
0
0
1
0
0
1
UCB0SIMO/UCB0SDA (see Notes 2 and 3)
x
S26
x
P3.2/UCB00SOMI/
UCB0SCL/S27
2
P3.x (I/O)
I: 0, O: 1
UCB0SOMI/UCB0SCL (see Notes 2 and 3)
S27
x
x
NOTES: 1. x: Don’t care.
2. The pin direction is controlled by the USCI module.
3. In case the I2C functionality is selected the output drives only the logical 0 to V level.
SS
75
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P3 pin schematic: P3.4 to P3.7, input/output with Schmitt trigger
LCDS28
Pad Logic
Segment Sy
P3DIR.x
0
1
Direction
0: Input
1: Output
P3OUT.x
0
1
Module X Out
P3.4/S28
P3.5/S29
P3.6/S30
P3.7/S31
Bus
Keeper
EN
P3SEL.x
P3IN.x
Port P3 (P3.4 to P3.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P3.X)
X
FUNCTION
P3DIR.x
P3SEL.x
LCDS28
P3.4/S28
4
P3.x (I/O)
S28
I: 0, O: 1
0
x
0
x
0
x
0
x
0
1
0
1
0
1
0
1
x
P3.5/S29
P3.6/S30
P3.7/S31
5
6
7
P3.x (I/O)
S29
I: 0, O: 1
x
P3.x (I/O)
S30
I: 0, O: 1
x
I: 0, O: 1
x
P3.x (I/O)
S31
NOTES: 1. x: Don’t care.
76
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P4 pin schematic: P4.0 to P4.7, input/output with Schmitt trigger
LCDS4/8
Pad Logic
Segment Sy
P4DIR.x
0
1
Direction
0: Input
1: Output
P4OUT.x
0/1
0
1
P4.0/S11
P4.1/S10
P4.2/S9
P4.3/S8
P4.4/S7
P4.5/S6
P4.6/S5
P4.7/S4
Bus
Keeper
EN
P4SEL.x
P4IN.x
Port P4 (P4.0 and P4.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P4.X)
X
FUNCTION
P4DIR.x
P4SEL.x
LCDS4/8
P4.0/S11
0
P4.x (I/O)
S11
I: 0, O: 1
0
x
0
x
0
x
0
x
0
x
0
x
0
x
0
x
0 (LCDS8)
1 (LCDS8)
0 (LCDS8)
1 (LCDS8)
0 (LCDS8)
1 (LCDS8)
0 (LCDS8)
1 (LCDS8)
0 (LCDS4)
1 (LCDS4)
0 (LCDS4)
1 (LCDS4)
0 (LCDS4)
1 (LCDS4)
0 (LCDS4)
1 (LCDS4)
x
P4.1/S10
P4.2/S9
P4.3/S8
P4.4/S7
P4.5/S6
P4.6/S5
P4.7/S4
1
2
3
4
5
6
7
P4.x (I/O)
S10
I: 0, O: 1
x
P4.x (I/O)
S9
I: 0, O: 1
x
P4.x (I/O)
S8
I: 0, O: 1
x
P4.x (I/O)
S7
I: 0, O: 1
x
P4.x (I/O)
S6
I: 0, O: 1
x
P4.x (I/O)
S5
I: 0, O: 1
x
I: 0, O: 1
x
P4.x (I/O)
S4
NOTES: 1. x: Don’t care.
77
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P5 pin schematic: P5.0 and P5.1, input/output with Schmitt trigger
LCDS20
Pad Logic
Segment Sy
P5DIR.x
0
1
Direction
0: Input
1: Output
P5OUT.x
0/1
0
1
P5.0/S20
P5.1/S21
Bus
Keeper
EN
P5SEL.x
P5IN.x
Port P5 (P5.0 and P5.1) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P5.X)
X
FUNCTION
P5DIR.x
P5SEL.x
LCDS20
P5.0/S20
0
P5.x (I/O)
S20
I: 0, O: 1
0
x
0
x
0
1
0
1
x
I: 0, O: 1
x
P5.1/S21
1
P5.x (I/O)
S21
NOTES: 1. x: Don’t care.
78
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P5 pin schematic: P5.2 to P5.7, input/output with Schmitt trigger
Pad Logic
LCD Signal
P5DIR.x
0
1
Direction
0: Input
1: Output
P5OUT.x
0/1
0
1
P5.2/COM1
P5.3/COM2
P5.4/COM3
P5.5/R23
Bus
Keeper
EN
P5SEL.x
P5IN.x
P5.6/LCDREF/R13
P5.7/R03
Port P5 (P5.2 to P5.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P5.X)
X
FUNCTION
P5DIR.x
P5SEL.x
P5.2/COM1
2
P5.x (I/O)
COM1
I: 0, O: 1
0
1
0
1
0
1
0
1
0
1
0
1
x
P5.3/COM2
P5.4/COM3
P5.5/R23
3
4
5
6
7
P5.x (I/O)
COM2
I: 0, O: 1
x
P5.x (I/O)
COM3
I: 0, O: 1
x
P5.x (I/O)
R23
I: 0, O: 1
x
P5.6/LCDREF/R13
P5.7/R03
P5.x (I/O)
R13 or LCDREF
P5.x (I/O)
R03
I: 0, O: 1
x
I: 0, O: 1
x
NOTES: 1. x: Don’t care.
79
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P6 pin schematic: P6.0 and P6.3, input/output with Schmitt trigger
INCH=y
Ay+
Pad Logic
P6DIR.x
0
1
Direction
0: Input
1: Output
P6OUT.x
0
1
Module X OUT
P6.0/A0+/OA0O
P6.3/A1+/OA1O
Bus
Keeper
EN
P6SEL.x
P6IN.x
OAx
Port P6 (P6.0 and P6.3) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X)
X
FUNCTION
P6DIR.x
P6SEL.x
P6.0/A0+/OA0O
0
P6.x (I/O)
A0+
I: 0, O: 1
0
1
1
0
1
1
x
OA0O
P6.x (I/O)
A1+
x
P6.3/A1+/OA1O
3
I: 0, O: 1
x
x
OA1O
NOTES: 1. x: Don’t care.
80
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P6 pin schematic: P6.1 and P6.4, input/output with Schmitt trigger
Pad Logic
Ay-
INCH=y
P6DIR.x
0
1
Direction
0: Input
1: Output
P6OUT.x
0/1
0
1
P6.1/A0-/OA0FB
P6.4/A1-/OA1FB
Bus
Keeper
EN
P6SEL.x
P6IN.x
OAx
Port P6 (P6.1 and P6.4) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X)
X
FUNCTION
P6DIR.x
P6SEL.x
P6.1/A0--/OA0FB
1
P6.x (I/O)
A0--
I: 0, O: 1
0
1
1
0
1
1
x
OA0FB
P6.x (I/O)
A1--
x
P6.4/A1--/OA1FB
4
I: 0, O: 1
x
x
OA1FB
NOTES: 1. x: Don’t care.
81
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P6 pin schematic: P6.2, P6.5 and P6.6, input/output with Schmitt trigger
P6DIR.x
0
1
Direction
0: Input
1: Output
Pad Logic
P6.2/OA0I1 (SW0A)
P6.5/OA0I2 (SW0B)
P6.6/OA1I1 (SW1A)
P6OUT.x
0/1
0
1
Bus
Keeper
EN
P6SEL.x
P6IN.x
OAx
Port P6 (P6.2, P6.5 and P6.6) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X)
X
FUNCTION
P6DIR.x
P6SEL.x
P6.2/OA0I1
2
P6.x (I/O)
OA0I1
I: 0, O: 1
0
1
0
1
0
1
x
P6.5/OA0I2
P6.6/OA1I1
5
6
P6.x (I/O)
OA0I2
I: 0, O: 1
x
I: 0, O: 1
x
P6.x (I/O)
OA1I1
NOTES: 1. x: Don’t care.
82
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P6 pin schematic: P6.7, input/output with Schmitt trigger
VLDx = 1111
To SVS Mux
P6DIR.7
0
1
Pad Logic
Direction
0: Input
1: Output
P6.7/OA1I2/SVSIN
(SW1B)
P6OUT.7
0
1
Module X OUT
Bus
Keeper
EN
P6SEL.7
P6IN.7
OAx
Port P6 (P6.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X)
X
FUNCTION
P6DIR.x
P6SEL.x
VLDx
P6.7/OA1I2/SVSIN
7
P6.x (I/O)
I: 0, O: 1
0
1
1
x
x
OA1I2
SVSIN
x
x
1111
NOTES: 1. x: Don’t care.
83
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Segment pin schematic: Sx, dedicated Segment Pins
LCDS12/16/20/24
Segment Sx
Pad Logic
Sx
Sx pin functions
CONTROL BITS /
SIGNALS
PIN NAME
X
FUNCTION
LCDSy
Sx
Sx
Sx
Sx
Sx
Sx
Sx
Sx
Sx
Sx
Sx
Sx
12
Sx
1 (LCDS12)
0 (LCDS12)
1 (LCDS12)
0 (LCDS12)
1 (LCDS12)
0 (LCDS12)
1 (LCDS12)
0 (LCDS12)
1 (LCD16)
3-state
Sx
13
14
15
16
17
18
19
22
23
24
25
3-state
Sx
3-state
Sx
3-state
Sx
3-state
Sx
0 (LCD16)
1 (LCD16)
3-state
Sx
0 (LCD16)
1 (LCD16)
3-state
Sx
0 (LCD16)
1 (LCDS16)
0 (LCDS16)
1 (LCDS20)
0 (LCDS20)
1 (LCDS20)
0 (LCDS20)
1 (LCDS24)
0 (LCDS24)
1 (LCDS24)
0 (LCDS24)
3-state
Sx
3-state
Sx
3-state
Sx
3-state
Sx
3-state
Segment pin schematic: COM0, dedicated COM0 pin
Pad Logic
COM0
COM0
Sx pin functions
PIN NAME
COM0
X
FUNCTION
--
COM0
84
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
JTAG pins: TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger
TDO
Controlled by JTAG
Controlled by JTAG
JTAG
TDO/TDI
Controlled
by JTAG
DV
DV
CC
CC
TDI
Fuse
Burn & Test
Fuse
Test
and
TDI/TCLK
DV
CC
Emulation
Module
TMS
TCK
TMS
TCK
DV
CC
During Programming Activity and
During Blowing of the Fuse, Pin
TDO/TDI Is Used to Apply the Test
Input Data for JTAG Circuitry
JTAG fuse check mode
For details on the JTAG fuse check mode, see the MSP430 Memory Programming User’s Guide (SLAU265)
chapter ”Fuse Check and Reset of the JTAG State Machine (TAP Controller)”.
85
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
Data Sheet Revision History
LITERATURE
NUMBER
SUMMARY
SLAS580
Product Preview release
SLAS580A
SLAS580B
Changes throughout to update Product Preview
Production Data release
In recommended operating conditions table, changed maximum LFXT1 crystal frequency, f
from 8 MHz to 6 MHz (page 24)
,
with XT1 selected
(LFXT1)
SLAS580C
SLAS580D
Changed limits on t
parameter (page 32)
d(SVSon)
Corrected measurement pin name for “Duty cycle, LF mode” parameter (page 37)
86
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
1-Mar-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
MSP430FG477IPN
MSP430FG477IPNR
MSP430FG477IZQW
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
PN
PN
80
80
119
1000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
SNAGCU Level-3-260C-168 HR
BGA
MICROSTAR
JUNIOR
ZQW
113
Green (RoHS
& no Sb/Br)
MSP430FG477IZQWR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR
MSP430FG478IPN
MSP430FG478IPNR
MSP430FG478IZQW
ACTIVE
ACTIVE
ACTIVE
LQFP
PN
PN
80
80
119
1000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
SNAGCU Level-3-260C-168 HR
LQFP
Green (RoHS
& no Sb/Br)
BGA
MICROSTAR
JUNIOR
ZQW
113
Green (RoHS
& no Sb/Br)
MSP430FG478IZQWR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR
MSP430FG479IPN
MSP430FG479IPNR
MSP430FG479IZQW
ACTIVE
ACTIVE
ACTIVE
LQFP
PN
PN
80
80
119
1000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
SNAGCU Level-3-260C-168 HR
LQFP
Green (RoHS
& no Sb/Br)
BGA
MICROSTAR
JUNIOR
ZQW
113
Green (RoHS
& no Sb/Br)
MSP430FG479IZQWR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Mar-2011
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
60
M
0,08
41
61
40
0,13 NOM
80
21
1
20
Gage Plane
9,50 TYP
0,25
12,20
SQ
11,80
0,05 MIN
0°–7°
14,20
SQ
13,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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