MSP430FR2032_技术文档

Support &

Community

Product

Folder

Order

Now

Tools &

Software

Technical

Documents

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

MSP430FR203x 混合信号微控制器

1 器件概述

1.1 特性

1

• 嵌入式微控制器

• 时钟系统 (CS)

– 频率高达 16MHz 的 16 位精简指令集计算机

(RISC) 架构

– 片上 32kHz RC 振荡器 (REFO)

– 带有锁频环 (FLL) 的片上 16MHz 数控振荡器

– 3.6V 至 1.8V 的宽电源电压范围（最低电源电压

受限于 SVS 电平，请参阅 SVS 规格）

• 经优化的低功耗模式（3V）

– 工作状态：126µA/MHz

– 待机

(DCO)

– 室温下的精度为 ±1%（具有片上基准）

– 片上超低频 10kHz 振荡器 (VLO)

– 片上高频调制振荡器时钟 (MODCLK)

– 外部 32kHz 晶振 (XT1)

– LPM3.5（具有 VLO）：0.4µA

– 可编程 MCLK 预分频器（1 至 128）

– 实时时钟 (RTC) 计数器（LPM3.5，采用

32768Hz 晶振）：0.77μA

– 通过可编程预分频器（1、2、4 或 8）从 MCLK

获得的 SMCLK

– 关断 (LPM4.5)：15nA

• 低功耗铁电 RAM (FRAM)

– 容量高达 15.5KB 的非易失性存储器

– 内置错误修正码 (ECC)

• 通用输入/输出和引脚功能

– 共计 60 个 I/O（64 引脚封装）

– 16 个中断引脚（P1 和 P2）可以将 MCU 从

LPM 唤醒

– 可配置的写保护

– 所有 I/O 均为电容式触控 I/O

• 开发工具和软件

– 免费的专业开发环境

• 系列成员（另请参阅器件比较）

– 对程序、常量和存储的统一存储

– 耐写次数达 10¹⁵

– 抗辐射和非磁性

• 智能数字外设

次

– MSP430FR2033：15KB 程序 FRAM + 512B 信

息 FRAM + 2KB RAM

– 红外调制逻辑

– MSP430FR2032：8KB 程序 FRAM + 512B 信息

– 两个 16 位定时器，每个定时器有 3 个捕捉/比较

寄存器 (Timer_A3)

FRAM + 1KB RAM

• 封装选项

– 一个仅用作计数器的 16 位 RTC 计数器

– 16 位循环冗余校验 (CRC)

• 增强型串行通信

– 64 引脚：LQFP (PM)

– 56 引脚：TSSOP (G56)

– 48 引脚：TSSOP (G48)

– 增强型 USCI A (eUSCI_A) 支持 UART、IrDA 和

SPI

– 增强型 USCI B (eUSCI_B) 支持 SPI 和 I²C

• 高性能模拟

– 10 通道 10 位模数转换器 (ADC)

– 1.5V 的内部基准电压

– 采样与保持 200ksps

1.2 应用

•

烟雾或火灾探测器

玻璃破裂探测器

•

温度传感器或控制器

数据存储、数据集成

人机界面 (HMI) 控制器

工业传感器管理

系统监测器、低功耗控制器

1.3 说明

TI 的 MSP430™系列低功耗微控制器种类繁多，各成员器件配备不同的外设集以满足各类应用的需求的需

求。该架构与多种低功耗模式配合使用，经过优化，可在便携式测量应用延长电池寿命。此器件具有一个

强大的 16 位精简指令集 (RISC) CPU，使用 16 位寄存器以及常数发生器，以便获得最高编码效率。DCO

可使器件在不到 10µs 的时间内从低功率模式唤醒并进入工作模式。

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLASE45

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

有关完整的模块说明，请参阅《MSP430FR4xx 和 MSP430FR2xx 系列器件用户指南》。

器件信息⁽¹⁾

封装

器件型号

MSP430FR2033IPM

MSP430FR2033IG56

MSP430FR2033IG48

MSP430FR2032IPM

MSP430FR2032IG56

MSP430FR2032IG48

封装尺寸⁽²⁾

LQFP (64)

TSSOP (56)

TSSOP (48)

LQFP (64)

TSSOP (56)

TSSOP (48)

10mm x 10mm

14.0mm x 6.1mm

12.5mm x 6.1mm

10mm x 10mm

14.0mm x 6.1mm

12.5mm x 6.1mm

(1) 要获得最新的产品、封装和订购信息，请参见封装选项附录（节 9），或者访问德州仪器 (TI) 网站

www.ti.com.cn。

(2) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参见机械数据（节 9）。

2

器件概述

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

1.4 功能方框图

图 1-1 给出了功能框图。

XIN

XOUT

P1.x, P2.x

P3.x, P4.x

P5.x, P6.x

P7.x, P8.x

Capacitive Touch I/O

XT1

ADC

FRAM

RAM

I/O Ports

P1, P2

2×8 IOs,

Interrupt

and Wakeup,

PA

I/O Ports

P3, P4

2×8 IOs

I/O Ports

P5, P6

2×8 IOs

I/O Ports

P7, P8

1×8 IOs

1×4 IOs

PD

DVCC

DVSS

Up to 10

channels,

single ended,

10 bit,

15KB+512B

8KB+512B

2KB

1KB

Clock

System

Control

Power

Management

Module

PB

1×16 IOs

PC

1×16 IOs

200 ksps

1×12 IOs

RST/NMI

1×16 IOs

MAB

MDB

16-MHz CPU

with

16 registers

EEM

RTC

Counter

SYS

CRC16

TA0

TA1

eUSCI_A0

eUSCI_B0

(SPI, I²C)

TCK

TMS

16-bit

Cyclic

Redundancy

Check

16-bit

Real-Time

Clock

JTAG

SBW

Timer_A

3 CC

Registers

Timer_A

3 CC

Registers

TDI/TCLK

TDO

(UART,

IrDA, SPI)

SBWTCK

SBWTDIO

Watchdog

LPM3.5 Domain

图 1-1. 功能框图

•

该器件具有一对主电源（DVCC 和 DVSS），分别为数字和模拟模块供电。推荐的旁路电容和去耦电容

分别为 4.7µF 至 10µF 和 0.1µF，精度为 ±5%。

•

P1 和 P2 特有引脚中断功能，可将 MCU 从 LPM3.5 模式唤醒。

每个 Timer_A3 均有 3 个 CC 寄存器，不过只有 CCR1 和 CCR2 从外部连接。CCR0 寄存器仅用于内部

周期时序和产生中断。

•

在 LPM3.5 模式下，RTC 计数器可继续工作，而其余外设会停止工作。

在 TSSOP-56 和 TSSOP-48 封装中，并非所有 I/O 均已打线接合（请参见Table 4-1）。所有 I/O 均可

配置为电容式触摸 I/O。

器件概述

3

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

内容

1

器件概述.................................................... 1

1.1 特性 ................................................... 1

1.2 应用 ................................................... 1

1.3 说明 ................................................... 1

1.4 功能方框图............................................ 3

修订历史记录............................................... 5

Device Comparison ..................................... 7

3.1 Related Products ..................................... 7

Terminal Configuration and Functions.............. 8

4.1 Pin Diagrams ......................................... 8

4.2 Signal Descriptions.................................. 11

4.3 Pin Multiplexing ..................................... 14

4.4 Connection of Unused Pins ......................... 14

Specifications ........................................... 15

5.1 Absolute Maximum Ratings......................... 15

5.2 ESD Ratings ........................................ 15

5.3 Recommended Operating Conditions............... 15

5.12 Timing and Switching Characteristics ............... 20

Detailed Description ................................... 34

6.1 CPU ................................................. 34

6.2 Operating Modes.................................... 34

6.3 Interrupt Vector Addresses.......................... 35

6.4 Bootloader (BSL).................................... 36

6.5 JTAG Standard Interface............................ 36

6.6 Spy-Bi-Wire Interface (SBW)........................ 37

6.7 FRAM................................................ 37

6.8 Memory Protection .................................. 37

6.9 Peripherals .......................................... 38

6.10 Device Descriptors (TLV) ........................... 62

6.11 Memory.............................................. 63

6.12 Identification ......................................... 70

Applications, Implementation, and Layout........ 71

6

2

3

4

5

7

8

7.1

Device Connection and Layout Fundamentals...... 71

7.2

Peripheral- and Interface-Specific Design

Information .......................................... 74

5.4

Active Mode Supply Current Into V_CCExcluding

External Current..................................... 16

5.5 Active Mode Supply Current Per MHz .............. 16

器件和文档支持 .......................................... 76

8.1 开始使用............................................. 76

8.2 器件命名规则 ........................................ 76

8.3 工具和软件 .......................................... 77

8.4 文档支持............................................. 79

8.5 相关链接............................................. 80

8.6 社区资源............................................. 81

8.7 商标.................................................. 81

8.8 静电放电警告 ........................................ 81

8.9 Glossary ............................................. 81

机械、封装和可订购信息................................ 82

5.6

5.7

5.8

5.9

Low-Power Mode LPM0 Supply Currents Into V_CC

Excluding External Current.......................... 16

Low-Power Mode LPM3 and LPM4 Supply Currents

(Into V_CC) Excluding External Current .............. 17

Low-Power Mode LPMx.5 Supply Currents (Into

V_CC) Excluding External Current.................... 17

Typical Characteristics, Low-Power Mode Supply

Currents ............................................. 18

5.10 Typical Characteristics - Current Consumption Per

Module .............................................. 19

5.11 Thermal Characteristics............................. 19

9

4

内容

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

2 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

从修订版本 D 更改为修订版本 E

Changes from January 22, 2019 to December 9, 2019

Page

•

Changed the note that begins "Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset..." in

Section 5.3, Recommended Operating Conditions ............................................................................. 15

Added the note that begins "TI recommends that power to the DVCC pin must not exceed the limits..." in

Section 5.3, Recommended Operating Conditions ............................................................................. 15

Changed the note that begins "A capacitor tolerance of ±20% or better is required..." in Section 5.3,

Recommended Operating Conditions ............................................................................................ 15

Added the note "See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing" to

Table 5-3, XT1 Crystal Oscillator (Low Frequency) ............................................................................ 22

Changed the note that begins "Requires external capacitors at both terminals..." in Table 5-3, XT1 Crystal

Oscillator (Low Frequency) ........................................................................................................ 22

Added the t_(int)parameter in Table 5-8, Digital Inputs ......................................................................... 24

Added the t_TA,capparameter in Table 5-10, Timer_A............................................................................ 25

Corrected the test conditions for the R_I,MUXparameter in Table 5-17, ADC, Power Supply and Input Range

Conditions ............................................................................................................................ 31

Added the note that begins "t_Sample= ln(2ⁿ⁺¹) × τ ..." in Table 5-18, ADC, 10-Bit Timing Parameters.................... 31

•

从修订版本 C 更改为修订版本 D

Changes from August 30, 2018 to January 21, 2019

Page

•

已通篇将调制振荡器 (MODOSC) 更改为调制振荡器时钟 (MODCLK) ......................................................... 1

Added "or memory corruption" to note (1) in Section 5.1, Absolute Maximum Ratings ................................... 15

Added the note that begins "The VLO clock frequency is reduced by..." after Table 5-6, Internal Very-Low-Power

Low-Frequency Oscillator (VLO) ................................................................................................. 23

Added the t_TA,capparameter in Table 5-10, Timer_A............................................................................ 25

Changed the parameter symbol from R_Ito R_I,MUXin Table 5-17, ADC, Power Supply and Input Range Conditions.. 31

Added the R_I,Miscparameter in Table 5-17, ADC, Power Supply and Input Range Conditions ........................... 31

Removed ADCDIV from the formula for the t_CONVERTTYP value, because ADCCLK is after division, in Table 5-

18, ADC, 10-Bit Timing Parameters .............................................................................................. 31

Added note (2) for R_Icalculation in Table 5-18, ADC, 10-Bit Timing Parameters.......................................... 31

Removed "±3°C" on both temperatures in the note that begins "The device descriptor structure contains..." in

Table 5-19, ADC, 10-Bit Linearity Parameters ................................................................................. 32

Add "10b" for ADCSSEL bit in Table 6-6, Clock Distribution .................................................................. 39

Added Figure 6-1, Clock Distribution Block Diagram........................................................................... 39

Corrected the spelling of the IRDSSEL bit in the paragraph that begins "The IR functions are controlled by..." in

Section 6.9.8, Timers (Timer0_A3, Timer1_A3)................................................................................. 44

Changed two instances of "ADC 1.5-V Reference Temperature" to "ADC 1.5-V Reference Temperature Sensor"

in Table 6-29, Device Descriptors................................................................................................. 62

•

从修订版本 B 更改为修订版本 C

Changes from August 15, 2015 to August 29, 2018

Page

•

Updated Section 3.1, Related Products ........................................................................................... 7

Replaced all notes on Section 5.11, Thermal Characteristics ................................................................ 19

Added note to V_SVSH-and V_SVSH+parameters in Table 5-1, PMM, SVS and BOR.......................................... 20

Added the t_TA,capparameter in Table 5-10, Timer_A............................................................................ 25

Updated the link to the BSL user's guide in Section 6.4, Bootloader (BSL)................................................. 36

Changed all instances of "bootstrap loader" to "bootloader" throughout document........................................ 36

Corrected the ADCINCHx column heading in Table 6-12, ADC Channel Connections ................................... 45

修订历史记录

5

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

•

更新了节 8，器件和文档支持中的特定于器件的信息和链接 .................................................................. 76

从修订版本 A 更改为修订版本 B

Changes from December 23, 2014 to August 14, 2015

Page

•

Corrected "10-BIT ADC CHANNELS" column for MSP430FR2032IPM in Table 3-1, Device Comparison .............. 7

Added T_stgMIN and MAX values.................................................................................................. 15

Added Section 5.2, ESD Ratings.................................................................................................. 15

Changed all graphs in Section 5.9, Typical Characteristics, Low-Power Mode Supply Currents, for new

measurements ...................................................................................................................... 18

Added V_{REF, 1.2V}parameter to Table 5-1, PMM, SVS and BOR............................................................... 20

Added the t_TA,capparameter in Table 5-10, Timer_A............................................................................ 25

Changed t_STE,LEADMIN value at 2 V from 40 ns to 50 ns ...................................................................... 28

Changed t_STE,LEADMIN value at 3 V from 24 ns to 45 ns ...................................................................... 28

Changed t_VALID,SOMAX value at 2 V from 55 ns to 65 ns...................................................................... 28

Changed t_VALID,SOMAX value at 3 V from 30 ns to 40 ns...................................................................... 28

Changed the f_ADCOSCTYP value from 4.5 MHz to 5.0 MHz.................................................................... 31

In Table 6-1, Operating Modes, changed the entry for "Power Consumption at 25°C, 3 V" in AM from

•

100 µA/MHz to 126 µA/MHz ....................................................................................................... 34

In Table 6-1, Operating Modes, added "with RTC only" to the entry for "Power Consumption at 25°C, 3 V" in

LPM3.5 ............................................................................................................................... 34

In Table 6-2, Interrupt Sources, Flags, and Vectors, removed "FRAM access time error" (ACCTEIFG) from the

"System NMI" row .................................................................................................................. 35

•

从初始发行版更改为修订版本 A

Changes from October 3, 2014 to December 22, 2014

Page

•

Moved T_stgto Absolute Maximum Ratings ....................................................................................... 15

Added the t_TA,capparameter in Table 5-10, Timer_A............................................................................ 25

Changed link to BSL user's guide in Section 6.4, Bootloader (BSL) ......................................................... 36

Added note (1) to Table 6-6 ....................................................................................................... 39

Changed the values of ADC Calibration Tag and ADC Calibration Length in the ADC Calibration row................. 62

Added Calibration Tag, Calibration Length, and 1.5-V Reference in the Reference and DCO Calibration row ........ 63

Added row for BSL memory to Table 6-30....................................................................................... 63

6

修订历史记录

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

3 Device Comparison

Table 3-1 summarizes the features of the available family members.

Table 3-1. Device Comparison⁽¹⁾⁽²⁾

PROGRAM

FRAM +

INFORMATION (BYTES)

FRAM (BYTES)

SRAM

10-BIT ADC

CHANNELS

DEVICE

TA0, TA1

eUSCI_A

eUSCI_B

I/O

PACKAGE

PM

(LQFP64)

MSP430FR2033IPM

MSP430FR2033IG56

MSP430FR2033IG48

MSP430FR2032IPM

MSP430FR2032IG56

MSP430FR2032IG48

15360 + 512

8192 + 512

2048

1024

3 × CCR⁽³⁾

1

10

8

60

52

44

60

52

44

G56

(TSSOP56)

G48

(TSSOP48)

8

PM

(LQFP64)

10

8

G56

(TSSOP56)

G48

(TSSOP48)

8

(1) For the most current device, package, and ordering information, see the Package Option Addendum in 节 9, or see the TI website at

www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/packaging.

(3) A CCR register is a configurable register that provides internal and external capture or compare inputs, or internal and external PWM

outputs.

3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

TI 16-bit and 32-bit microcontrollers

High-performance low-power solutions to enable the autonomous future

Products for MSP430 ultra-low-power sensing & measurement MCUs

One platform. One ecosystem. Endless possibilities.

Companion products for MSP430FR2033

Review products that are frequently purchased or used with this product.

Reference designs for MSP430FR2033

Find reference designs leveraging the best in TI technology to solve your system-level challenges.

Device Comparison

7

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

4 Terminal Configuration and Functions

4.1 Pin Diagrams

Figure 4-1 shows the 64-pin PM package.

P4.7

P4.6

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P6.0

P6.1

P6.2

P6.3

P6.4

P6.5

P6.6

P6.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

2

P4.5

3

P4.4

4

P4.3

5

P4.2/XOUT

P4.1/XIN

6

7

DVSS

8

DVCC

9

RST/NMI/SBWTDIO

TEST/SBWTCK

P4.0/TA1.1

P8.3/TA1.2

P8.2/TA1CLK

P8.1/ACLK/A9

P8.0/SMCLK/A8

10

11

12

13

14

15

16

Figure 4-1. 64-Pin PM (LQFP) Designation (Top View)

8

Terminal Configuration and Functions

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

Figure 4-2 shows the 56-pin G56 package.

P7.5

1

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

P3.0

P7.4

P7.3

2

P3.1

3

P3.2

P7.2

4

P3.3

P7.1

5

P3.4

P7.0

6

P3.5

P4.7

7

P3.6

P4.6

8

P3.7

P4.5

9

P6.0

P4.4

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

P6.1

P4.3

P6.2

P4.2/XOUT

P4.1/XIN

P6.3

P6.4

DVSS

P6.5

DVCC

P2.0

RST/NMI/SBWTDIO

TEST/SBWTCK

P4.0/TA1.1

P2.1

P2.2

P2.3

P8.3/TA1.2

P2.4

P8.2/TA1CLK

P1.7/TA0.1/TDO/A7

P1.6/TA0.2/TDI/TCLK/A6

P1.5/TA0CLK/TMS/A5

P1.4/MCLK/TCK/A4/VREF+

P1.3/UCA0STE/A3

P1.2/UCA0CLK/A2

P2.5

P2.6

P2.7

P5.0/UCB0STE

P5.1/UCB0CLK

P5.2/UCB0SIMO/UCB0SDA

P5.3/UCB0SOMI/UCB0SCL

P5.4

P1.1/UCA0RXD/UCA0SOMI/A1/Veref+

P1.0/UCA0TXD/UCA0SIMO/A0/Veref–

P5.5

Figure 4-2. 56-Pin DGG (TSSOP) Designation (Top View)

Terminal Configuration and Functions

9

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

Figure 4-3 shows the 48-pin G48 package.

P3.1

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

P3.2

P3.0

2

P3.3

P7.3

3

P3.4

P7.2

P7.1

4

P3.5

5

P3.6

P7.0

6

P3.7

P4.7

7

P6.0

P4.6

8

P6.1

P4.5

9

P6.2

P4.4

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

P6.3

P4.3

P2.0

P4.2/XOUT

P2.1

P4.1/XIN

P2.2

DVSS

P2.3

DVCC

P2.4

RST/NMI/SBWTDIO

TEST/SBWTCK

P4.0/TA1.1

P2.5

P2.6

P2.7

P1.7/TA0.1/TDO/A7

P1.6/TA0.2/TDI/TCLK/A6

P1.5/TA0CLK/TMS/A5

P1.4/MCLK/TCK/A4/VREF+

P1.3/UCA0STE/A3

P1.2/UCA0CLK/A2

P5.0/UCB0STE

P5.1/UCB0CLK

P5.2/UCB0SIMO/UCB0SDA

P5.3/UCB0SOMI/UCB0SCL

P1.0/UCA0TXD/UCA0SIMO/A0/Veref–

P1.1/UCA0RXD/UCA0SOMI/A1/Veref+

Figure 4-3. 48-Pin DGG (TSSOP) Designation (Top View)

10

Terminal Configuration and Functions

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

4.2 Signal Descriptions

Table 4-1 describes the signals for all device variants and package options.

Table 4-1. Signal Descriptions

TERMINAL

PACKAGE SUFFIX

I/O

DESCRIPTION

NAME

PM

G56

7

G48

P4.7

P4.6

P4.5

P4.4

P4.3

1

2

3

4

5

7

8

I/O

General-purpose I/O

8

9

10

11

10

11

P4.2/XOUT

P4.1/XIN

6

7

12

13

12

13

I/O

Output terminal for crystal oscillator

General-purpose I/O

Input terminal for crystal oscillator

Power ground

DVSS

DVCC

8

9

14

15

14

15

Power supply

Reset input, active low

RST/NMI/SBWTDIO

10

16

I/O

Nonmaskable interrupt input

Spy-Bi-Wire data input/output

Test Mode pin – selected digital I/O on JTAG pins

TEST/SBWTCK

P4.0/TA1.1

11

12

13

14

17

18

19

20

17

18

I

Spy-Bi-Wire input clock

General-purpose I/O

I/O

Timer TA1 CCR1 capture: CCI1A input, compare: Out1 outputs

General-purpose I/O

P8.3/TA1.2⁽¹⁾

P8.2/TA1CLK⁽¹⁾

Timer TA1 CCR2 capture: CCI2A input, compare: Out2 outputs

General-purpose I/O

Timer clock input TACLK for TA1

General-purpose I/O

P8.1/ACLK/A9⁽¹⁾

15

16

I/O

ACLK output

Analog input A9

General-purpose I/O

P8.0/SMCLK/A8⁽¹⁾

SMCLK output

Analog input A8

General-purpose I/O⁽²⁾

Timer TA0 CCR1 capture: CCI1A input, compare: Out1 outputs

Test data output

P1.7/TA0.1/TDO/A7⁽²⁾

17

18

21

22

19

20

I/O

Analog input A7

General-purpose I/O⁽²⁾

Timer TA0 CCR2 capture: CCI2A input, compare: Out2 outputs

Test data input or test clock input

P1.6/TA0.2/TDI/TCLK/A6⁽²⁾

Analog input A6

(1) Any pin that is not bonded out in a smaller package must be initialized by software after reset to achieve the lowest leakage current.

(2) Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to

prevent collisions.

Terminal Configuration and Functions

11

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

Table 4-1. Signal Descriptions (continued)

TERMINAL

PACKAGE SUFFIX

I/O

DESCRIPTION

NAME

PM

G56

G48

General-purpose I/O⁽²⁾

Timer clock input TACLK for TA0

Test mode select

P1.5/TA0CLK/TMS/A5⁽²⁾

19

20

23

21

22

I/O

Analog input A5

General-purpose I/O⁽²⁾

MCLK output

Test clock

P1.4/MCLK/TCK/A4/VREF+⁽²⁾

24

I/O

Analog input A4

Output of positive reference voltage with ground as reference

General-purpose I/O

P1.3/UCA0STE/A3

P1.2/UCA0CLK/A2

21

22

25

26

23

24

I/O

eUSCI_A0 SPI slave transmit enable

Analog input A3

General-purpose I/O

eUSCI_A0 SPI clock input/output

Analog input A2

General-purpose I/O

eUSCI_A0 UART receive data

P1.1/UCA0RXD/UCA0SOMI/

A1/Veref+

23

24

27

28

25

26

I/O

eUSCI_A0 SPI slave out/master in

Analog input A1, and ADC positive reference

General-purpose I/O

eUSCI_A0 UART transmit data

P1.0/UCA0TXD/UCA0SIMO/

A0/Veref-

eUSCI_A0 SPI slave in/master out

Analog input A0, and ADC negative reference

General-purpose I/O

P5.7⁽¹⁾

P5.6⁽¹⁾

P5.5⁽¹⁾

P5.4⁽¹⁾

25

26

27

28

I/O

General-purpose I/O

29

30

General-purpose I/O

P5.3/UCB0SOMI/UCB0SCL

P5.2/UCB0SIMO/UCB0SDA

P5.1/UCB0CLK

29

30

31

32

31

32

33

34

27

28

29

30

I/O

eUSCI_B0 SPI slave out/master in; eUSCI_B0 I²C clock

General-purpose I/O

eUSCI_B0 SPI slave in/master out; eUSCI_B0 I²C data

General-purpose I/O

eUSCI_B0 clock input/output

General-purpose I/O

P5.0/UCB0STE

eUSCI_B0 slave transmit enable

General-purpose I/O

P2.7

P2.6

P2.5

P2.4

P2.3

P2.2

P2.1

33

34

35

36

37

38

39

35

36

37

38

39

40

41

31

32

33

34

35

36

37

I/O

12

Terminal Configuration and Functions

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

Table 4-1. Signal Descriptions (continued)

TERMINAL

PACKAGE SUFFIX

I/O

DESCRIPTION

NAME

PM

40

G56

G48

P2.0

42

38

I/O

General-purpose I/O

P6.7⁽¹⁾

P6.6⁽¹⁾

P6.5⁽¹⁾

P6.4⁽¹⁾

P6.3

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

43

44

45

46

47

48

49

50

51

52

53

54

55

56

39

40

41

42

43

44

45

46

47

48

1

P6.2

P6.1

P6.0

P3.7

P3.6

P3.5

P3.4

P3.3

P3.2

P3.1

P3.0

2

P7.7⁽¹⁾

P7.6⁽¹⁾

P7.5⁽¹⁾

P7.4⁽¹⁾

P7.3

1

2

3

4

5

6

3

4

5

6

P7.2

P7.1

P7.0

Terminal Configuration and Functions

13

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

4.3 Pin Multiplexing

Pin multiplexing for these devices is controlled by both register settings and operating modes (for

example, if the device is in test mode). For details of the settings for each pin and diagrams of the

multiplexed ports, see Section 6.9.12.

4.4 Connection of Unused Pins

Table 4-2 shows the correct termination of unused pins.

Table 4-2. Connection of Unused Pins⁽¹⁾

POTENTIAL

Open

COMMENT

Px.0 to Px.7

RST/NMI

TEST

Set to port function, output direction (PxDIR.n = 1)

47-kΩ pullup or internal pullup selected with 10-nF (or 1.1-nF) pulldown⁽²⁾

DVCC

Open

This pin always has an internal pulldown enabled.

(1) Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection

guidelines.

(2) The pulldown capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode with TI tools like

FET interfaces or GANG programmers.

14

Terminal Configuration and Functions

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

Voltage applied at DVCC pin to V_SS

Voltage applied to any pin⁽²⁾

–0.3

4.1

V

V_CC+ 0.3

(4.1 Maximum)

–0.3

V

Diode current at any device pin

±2

85

mA

°C

Maximum junction temperature, T_J

(3)

Storage temperature, T_stg

–40

125

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage or memory corruption to the device.

These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect

device reliability.

(2) All voltages referenced to V_SS

.

(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

5.2 ESD Ratings

VALUE

±1000

±250

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as

±1000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V

may actually have higher performance.

5.3 Recommended Operating Conditions

Typical values are specified at V_CC= 3.3 V and T_A= 25°C (unless otherwise noted)

MIN

NOM

MAX UNIT

V_CC

V_SS

T_A

Supply voltage applied at DVCC pin^(1)(2)(3)(4)

Supply voltage applied at DVSS pin

Operating free-air temperature

1.8

3.6

V

0

–40

4.7

85

°C

µF

T_J

Operating junction temperature

Recommended capacitor at DVCC⁽⁵⁾

C_DVCC

10

No FRAM wait states

(NWAITSx = 0)

0

8

f_SYSTEM

Processor frequency (maximum MCLK frequency)⁽⁶⁾

MHz

With FRAM wait states

(NWAITSx = 1)⁽⁷⁾

16⁽⁸⁾

f_ACLK

Maximum ACLK frequency

Maximum SMCLK frequency

40

16⁽⁸⁾

kHz

f_SMCLK

MHz

(1) Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset even within the recommended supply voltage range. Following the

data sheet recommendation for capacitor C_DVCClimits the slopes accordingly.

(2) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.

(3) TI recommends that power to the DVCC pin must not exceed the limits specified in Recommended Operating Conditions. Exceeding the

specified limits can cause malfunction of the device including erroneous writes to RAM and FRAM.

(4) The minimum supply voltage is defined by the SVS levels. See the SVS threshold parameters in Table 5-1.

(5) A capacitor tolerance of ±20% or better is required. A low-ESR ceramic capacitor of 100 nF (minimum) should be placed as close as

possible (within a few millimeters) to the respective pin pair.

(6) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

(7) Wait states only occur on actual FRAM accesses (that is, on FRAM cache misses). RAM and peripheral accesses are always executed

without wait states.

(8) If clock sources such as HF crystals or the DCO with frequencies >16 MHz are used, the clock must be divided in the clock system to

comply with this operating condition.

Specifications

15

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

5.4 Active Mode Supply Current Into V_CCExcluding External Current⁽¹⁾

FREQUENCY (f_MCLK= f_SMCLK

)

1 MHz

0 WAIT STATES

(NWAITSx = 0)

8 MHz

0 WAIT STATES

(NWAITSx = 0)

16 MHz

1 WAIT STATE

(NWAITSx = 1)

EXECUTION

MEMORY

TEST

CONDITIONS

PARAMETER

UNIT

TYP

504

516

209

217

231

MAX

TYP

2874

2919

633

MAX

TYP

3156

3205

1056

1074

1450

MAX

3700

3 V, 25°C

3 V, 85°C

3 V, 25°C

3 V, 85°C

3 V, 25°C

FRAM

0% cache hit ratio

I_{AM, FRAM}(0%)

µA

1298

FRAM

100% cache hit ratio

I_{AM, FRAM}(100%)

µA

647

(2)

I_{AM, RAM}

RAM

809

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current. Characterized with program executing typical data

processing.

f_ACLK= 32786 Hz, f_MCLK= f_SMCLK= f_DCOat specified frequency

Program and data entirely reside in FRAM. All execution is from FRAM.

(2) Program and data reside entirely in RAM. All execution is from RAM. No access to FRAM.

5.5 Active Mode Supply Current Per MHz

V_CC= 3 V, T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

TYP

UNIT

µA/MHz

((I_{AM, 75% cache hit rate}at 8 MHz) –

(I_{AM, 75% cache hit rate}at 1 MHz))

/ 7 MHz

Active mode current consumption per MHz,

execution from FRAM, no wait states⁽¹⁾

dI_AM,FRAM/df

126

(1) All peripherals are turned on in default settings.

5.6 Low-Power Mode LPM0 Supply Currents Into V_CCExcluding External Current

V_CC= 3 V, T_A= 25°C (unless otherwise noted)⁽¹⁾⁽²⁾

FREQUENCY (f_SMCLK

8 MHz

)

PARAMETER

V_CC

1 MHz

TYP

16 MHz

TYP MAX

UNIT

MAX

TYP

307

318

MAX

2 V

3 V

158

169

415

427

I_LPM0

Low-power mode LPM0 supply current

µA

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) Current for watchdog timer clocked by SMCLK included.

f_ACLK= 32786 Hz, f_MCLK= 0 MHz, f_SMCLKat specified frequency.

16

Specifications

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

5.7 Low-Power Mode LPM3 and LPM4 Supply Currents (Into V_CC) Excluding External Current

(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

–40°C

TYP MAX

25°C

TYP

85°C

TYP

PARAMETER

V_CC

UNIT

MAX

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

1.13

1.06

0.92

0.86

1.08

0.65

0.63

0.51

0.50

1.31

1.21

1.00

1.25

0.75

0.73

0.58

0.57

1.99

3.00

2.94

2.89

2.75

3.04

1.88

1.85

1.51

1.49

I_LPM3,XT1

Low-power mode 3, includes SVS^(2)(3)(4)

µA

1.75

I_LPM3,VLO

I_{LPM3, RTC}

I_{LPM4, SVS}

Low-power mode 3, VLO, excludes SVS⁽⁵⁾

Low-power mode 3, RTC, excludes SVS⁽⁶⁾

Low-power mode 4, includes SVS

µA

I_LPM4

Low-power mode 4, excludes SVS

µA

(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current

(2) Not applicable for devices with HF crystal oscillator only.

(3) Characterized with a Golledge MS1V-TK/I_32.768KHZ crystal with a load capacitance chosen to closely match the required load.

(4) Low-power mode 3, includes SVS test conditions:

Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),

f_XT1= 32768 Hz, f_ACLK= f_XT1, f_MCLK= f_SMCLK= 0 MHz

(5) Low-power mode 3, VLO, excludes SVS test conditions:

Current for watchdog timer clocked by VLO included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),

f_XT1= 0 Hz, f_ACLK= f_MCLK= f_SMCLK= 0 MHz

(6) RTC periodically wakes up every second with external 32768-Hz as source.

5.8 Low-Power Mode LPMx.5 Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

–40°C

TYP MAX

25°C

TYP

85°C

TYP

PARAMETER

V_CC

UNIT

µA

MAX

Low-power mode 3.5, includes SVS^{(1)(2) (3)}

(also see Figure 5-2)

3 V

2 V

3 V

2 V

3 V

2 V

0.71

0.66

0.77

0.70

1.25

1.06

0.95

0.32

0.24

2.06

I_{LPM3.5, XT1}

I_{LPM4.5, SVS}

I_LPM4.5

0.23

0.25 0.375

0.20

0.43

Low-power mode 4.5, includes SVS⁽⁴⁾

Low-power mode 4.5, excludes SVS⁽⁵⁾

µA

0.20

0.010

0.008

0.015 0.070 0.073 0.140

0.013 0.060

µA

(1) Not applicable for devices with HF crystal oscillator only.

(2) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance chosen to closely match the required load.

(3) Low-power mode 3.5, includes SVS test conditions:

Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

f_XT1= 32768 Hz, f_ACLK= f_XT1, f_MCLK= f_SMCLK= 0 MHz

(4) Low-power mode 4.5, includes SVS test conditions:

Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

f_XT1= 0 Hz, f_ACLK= f_MCLK= f_SMCLK= 0 MHz

(5) Low-power mode 4.5, excludes SVS test conditions:

Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

f_XT1= 0 Hz, f_ACLK= f_MCLK= f_SMCLK= 0 MHz

Specifications

17

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

5.9 Typical Characteristics, Low-Power Mode Supply Currents

5

4.5

4

3

2.5

2

3.5

3

2.5

2

1.5

1

1.5

1

0.5

0

0.5

0

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80

Temperature (°C)

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80

Temperature (°C)

LPM3

SVS disabled

DVCC = 3 V

LPM3.5

12.5-pF crystal on XT1

DVCC = 3 V

SVS enabled

RTC counter on

Figure 5-1. LPM3 Supply Current vs Temperature

Figure 5-2. LPM3.5 Supply Current vs Temperature

0.5

0.45

0.4

0.35

0.3

0.25

0.2

0.15

0.1

0.05

0

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80

Temperature (°C)

LPM4.5

DVCC = 3 V

SVS enabled

Figure 5-3. LPM4.5 Supply Current vs Temperature

18

Specifications

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

5.10 Typical Characteristics - Current Consumption Per Module

MODULE

Timer_A

TEST CONDITIONS

REFERENCE CLOCK

Module input clock

TYP

5

UNIT

µA/MHz

nA

eUSCI_A

eUSCI_B

RTC

UART mode

SPI mode

Module input clock

32 kHz

7

5

I²C mode, 100 kbaud

5

85

8.5

CRC

From start to end of operation

MCLK

µA/MHz

5.11 Thermal Characteristics

THERMAL METRIC⁽¹⁾

PACKAGE

VALUE⁽²⁾

61.7

25.4

32.7

32.4

2.5

UNIT

°C/W

θ_JA

Junction-to-ambient thermal resistance, still air

Junction-to-case (top) thermal resistance

θ_{JC, (TOP)}

θ_JB

Junction-to-board thermal resistance

LQFP-64 (PM)

Ψ_JB

Junction-to-board thermal characterization parameter

Junction-to-top thermal characterization parameter

Junction-to-ambient thermal resistance, still air

Junction-to-case (top) thermal resistance

Ψ_JT

θ_JA

62.4

18.7

31.4

31.1

0.8

θ_{JC, (TOP)}

θ_JB

Junction-to-board thermal resistance

TSSOP-56 (DGG56)

TSSOP-48 (DGG48)

Ψ_JB

Junction-to-board thermal characterization parameter

Junction-to-top thermal characterization parameter

Junction-to-ambient thermal resistance, still air

Junction-to-case (top) thermal resistance

Ψ_JT

θ_JA

68.9

23

θ_{JC, (TOP)}

θ_JB

Junction-to-board thermal resistance

35.8

35.3

1.1

Ψ_JB

Junction-to-board thermal characterization parameter

Junction-to-top thermal characterization parameter

Ψ_JT

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) The values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC (Rθ_JC) value, which is based on a JEDEC-

defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

Specifications

19

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

5.12 Timing and Switching Characteristics

5.12.1 Power Supply Sequencing

Figure 5-4 shows the power supply reset parameters.

V

Power Cycle Reset

V_SVS+

SVS Reset

BOR Reset

V_SVS–

V_BOR

t_BOR

t

Figure 5-4. Power Cycle, SVS, and BOR Reset Conditions

Table 5-1. PMM, SVS and BOR

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

0.1

10

TYP

MAX UNIT

V_{BOR, safe}

t_{BOR, safe}

I_SVSH,AM

Safe BOR power-down level⁽¹⁾

Safe BOR reset delay⁽²⁾

V

ms

SVS_Hcurrent consumption, active mode

SVS_Hcurrent consumption, low-power modes

SVS_Hpower-down level⁽³⁾

V_CC= 3.6 V

1.5

µA

nA

V

I_SVSH,LPM

V_SVSH-

240

1.81

1.88

70

1.71

1.76

1.87

1.99

V_SVSH+

SVS_Hpower-up level⁽³⁾

V

V_{SVSH_hys}

t_{PD,SVSH, AM}

t_{PD,SVSH, LPM}

V_{REF, 1.2V}

SVS_Hhysteresis

mV

µs

V

SVS_Hpropagation delay, active mode

SVS_Hpropagation delay, low-power modes

1.2-V REF voltage⁽⁴⁾

10

100

1.158

1.200

1.242

(1) A safe BOR can be correctly generated only if DVCC drops below this voltage before it rises.

(2) When an BOR occurs, a safe BOR can be correctly generated only if DVCC is kept low longer than this period before it reaches V_SVSH+

(3) For additional information, see the Dynamic Voltage Scaling Power Solution for MSP430 Devices With Single-Channel LDO Reference

Design.

.

(4) This is a characterized result with external 1-mA load to ground from –40°C to 85°C.

20

Specifications

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

5.12.2 Reset Timing

Table 5-2. Wake-Up Times From Low-Power Modes and Reset

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEST

CONDITIONS

PARAMETER

V_CC

3 V

3V

MIN

TYP

MAX UNIT

Additional wake-up time to activate the FRAM in AM

if previously disabled by the FRAM controller or from

a LPM if immediate activation is selected for

wakeup⁽¹⁾

t_{WAKE-UP FRAM}

10

µs

200 ns +

2.5/f_DCO

t_{WAKE-UP LPM0}

Wake-up time from LPM0 to active mode⁽¹⁾

(2)

t_{WAKE-UP LPM3}

t_{WAKE-UP LPM4}

t_{WAKE-UP LPM3.5}

Wake-up time from LPM3 to active mode

3 V

10

µs

ms

Wake-up time from LPM4 to active mode

(2)

Wake-up time from LPM3.5 to active mode

350

1

SVSHE = 1

SVSHE = 0

(2)

t_{WAKE-UP LPM4.5}

Wake-up time from LPM4.5 to active mode

Wake-up time from RST or BOR event to active

mode

t_{WAKE-UP-RESET}

t_RESET

3 V

1

ms

µs

(2)

Pulse duration required at RST/NMI pin to accept a

reset

2

(1) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first

externally observable MCLK clock edge.

(2) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first

instruction of the user program is executed.

Specifications

21

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

5.12.3 Clock Specifications

Table 5-3. XT1 Crystal Oscillator (Low Frequency)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾⁽²⁾

PARAMETER

TEST CONDITIONS

LFXTBYPASS = 0

MIN

TYP

MAX UNIT

f_{XT1, LF}

XT1 oscillator crystal, low frequency

32768

Hz

Measured at MCLK,

f_LFXT= 32768 Hz

DC_{XT1, LF}

XT1 oscillator LF duty cycle

30%

70%

XT1 oscillator logic-level square-wave

input frequency

(3)(4)

f_XT1,SW

DC_{XT1, SW}

OA_LFXT

C_L,eff

LFXTBYPASS = 1

32768

Hz

LFXT oscillator logic-level square-

wave input duty cycle

40%

60%

Oscillation allowance for LF crystals

LFXTBYPASS = 0, LFXTDRIVE = {3},

f_LFXT= 32768 Hz, C_L,eff= 12.5 pF

200

1

kΩ

(5)

Integrated effective load

capacitance⁽⁶⁾

(7)

See

pF

f_OSC= 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {3},

T_A= 25°C, C_L,eff= 12.5 pF

(8)

t_START,LFXT

f_Fault,LFXT

Start-up time

1000

ms

(9)

Oscillator fault frequency

XTS = 0⁽¹⁰⁾

0

3500

Hz

(1) To improve EMI on the LFXT oscillator, the following guidelines should be observed.

•

Keep the trace between the device and the crystal as short as possible.

Design a good ground plane around the oscillator pins.

Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.

If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.

(2) See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing.

(3) When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics

defined in the Schmitt-trigger inputs section of this data sheet. Duty cycle requirements are defined by DC_{LFXT, SW}

.

(4) Maximum frequency of operation of the entire device cannot be exceeded.

(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the

LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following

guidelines, but should be evaluated based on the actual crystal selected for the application:

•

For LFXTDRIVE = {0}, C_L,eff= 3.7 pF

For LFXTDRIVE = {1}, 6 pF ≤ C_L,eff≤ 9 pF

For LFXTDRIVE = {2}, 6 pF ≤ C_L,eff≤ 10 pF

For LFXTDRIVE = {3}, 6 pF ≤ C_L,eff≤ 12 pF

(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

(7) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended

effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF. The PCB adds

additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance

of the selected crystal is met.

(8) Includes start-up counter of 1024 clock cycles.

(9) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specification may set the

flag. A static condition or stuck at fault condition sets the flag.

(10) Measured with logic-level input frequency but also applies to operation with crystals.

22

Specifications

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

Table 5-4. DCO FLL, Frequency

over recommended operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

–1.0%

–2.0%

TYP

MAX UNIT

1.0%

FLL lock frequency, 16 MHz, 25°C

FLL lock frequency, 16 MHz, –40°C to 85°C

Measured at MCLK, Internal

trimmed REFO as reference

2.0%

f_{DCO, FLL}

3 V

Measured at MCLK,

XT1 crystal as reference

FLL lock frequency, 16 MHz, –40°C to 85°C

–0.5%

40%

0.5%

60%

f_DUTY

Duty cycle

50%

0.25%

0.022%

120

Jitter_cc

Jitter_long

t_{FLL, lock}

Cycle-to-cycle jitter, 16 MHz

Long-term jitter, 16 MHz

FLL lock time

Measured at MCLK,

XT1 crystal as reference

3 V

ms

Table 5-5. REFO

over recommended operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A= 25°C

V_CC

MIN

TYP

15

MAX UNIT

µA

I_REFO

REFO oscillator current consumption

REFO calibrated frequency

3 V

Measured at MCLK

–40°C to 85°C

Measured at MCLK⁽¹⁾

32768

Hz

f_REFO

REFO absolute calibrated tolerance

REFO frequency temperature drift

1.8 V to 3.6 V

3 V

–3.5%

3.5%

df_REFO/d_T

0.01

1

%/°C

df_REFO

/

Measured at MCLK at

25°C⁽²⁾

REFO frequency supply voltage drift

1.8 V to 3.6 V

%/V

d_VCC

f_DC

REFO duty cycle

Measured at MCLK

40%

50%

50

60%

µs

t_START

REFO start-up time

40% to 60% duty cycle

(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))

(2) Calculated using the box method: (MAX(2 V to 3.6 V) – MIN(2 V to 3.6 V)) / MIN(2 V to 3.6 V) / (3.6 V – 2 V)

Table 5-6. Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

VLO frequency

VLO frequency temperature drift

TEST CONDITIONS

V_CC

3 V

MIN

TYP

10

MAX UNIT

kHz

f_VLO

Measured at MCLK

df_VLO/d_T

Measured at MCLK⁽¹⁾

Measured at MCLK⁽²⁾

Measured at MCLK

3 V

0.5

4

%/°C

df_VLO/dV_CCVLO frequency supply voltage drift

f_VLO,DCDuty cycle

1.8 V to 3.6 V

3 V

%/V

50%

(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))

(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

NOTE

The VLO clock frequency is reduced by 15% (typical) when the device switches from active

mode to LPM3 or LPM4, because the reference changes. This lower frequency is not a

violation of the VLO specifications (see Table 5-6).

Table 5-7. Module Oscillator Clock (MODCLK)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

MODCLK frequency

V_CC

3 V

MIN

TYP

4.8

MAX UNIT

5.8 MHz

%/℃

f_MODCLK

3.8

f_MODCLK/dT

MODCLK frequency temperature drift

MODCLK frequency supply voltage drift

Duty cycle

0.102

1.8 V to

3.6 V

f_MODCLK/dV_CC

f_MODCLK,DC

1.02

50%

%/V

60%

3 V

40%

Specifications

23

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

5.12.4 Digital I/Os

Table 5-8. Digital Inputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

2 V

3 V

2 V

3 V

2 V

3 V

MIN

0.90

1.35

0.50

0.75

0.3

TYP

MAX UNIT

1.50

V

V_IT+

V_IT–

V_hys

Positive-going input threshold voltage

2.25

1.10

V

Negative-going input threshold voltage

1.65

0.8

V

Input voltage hysteresis (V_IT+– V_IT–

Pullup or pulldown resistor

)

0.4

1.2

For pullup: V_IN= V_SS

For pulldown: V_IN= V_CC

R_Pull

C_I,dig

C_I,ana

20

35

3

50

20

kΩ

pF

nA

Input capacitance, digital only port pins

V_IN= V_SSor V_CC

Input capacitance, port pins with shared analog

functions

I_lkg(Px.y)High-impedance leakage current⁽¹⁾⁽²⁾

V_IN= V_SSor V_CC

5

2 V, 3 V

–20

50

Ports with interrupt capability

(see block diagram and

terminal function descriptions)

External interrupt timing (external trigger pulse

t_(int)

ns

duration to set interrupt flag)⁽³⁾

(1) The leakage current is measured with V_SSor V_CCapplied to the corresponding pins, unless otherwise noted.

(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is

disabled.

(3) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t_(int)is met. It may be set by trigger signals

shorter than t_(int)

.

Table 5-9. Digital Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_(OHmax)= –3 mA⁽¹⁾

I_(OHmax)= –5 mA⁽¹⁾

I_(OLmax)= 3 mA⁽¹⁾

V_CC

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

MIN

1.4

2.4

0.0

16

TYP

MAX UNIT

2.0

V

V_OH

High-level output voltage

3.0

0.60

V

V_OL

Low-level output voltage

I_(OHmax)= 5 mA⁽¹⁾

0.60

f_{Port_CLK}

t_rise,dig

t_fall,dig

Clock output frequency

C_L= 20 pF⁽²⁾

C_L= 20 pF

MHz

ns

16

10

7

Port output rise time, digital only port pins

Port output fall time, digital only port pins

10

5

ns

(1) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop

specified.

(2) The port can output frequencies at least up to the specified limit and might support higher frequencies.

24

Specifications

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

5.12.4.1 Digital I/O Typical Characteristics

25

10

7.5

5

T_A= 85°C

T_A= 25°C

20

T_A= 25°C

15

10

5

2.5

0

0.5

1

1.5

2

2.5

3

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

Low-Level Output Voltage (V)

Figure 5-5. Typical Low-Level Output Current vs Low-Level

Output Voltage (DVCC = 3 V)

Low-Level Output Voltage (V)

Figure 5-6. Typical Low-Level Output Current vs Low-Level

Output Voltage (DVCC = 2 V)

0

T_A= 85°C

-5

T_A= 25°C

-2.5

-10

-5

-7.5

-10

-15

-20

-25

0

0.5

1

1.5

2

2.5

3

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

High-Level Output Voltage (V)

Figure 5-7. Typical High-Level Output Current vs High-Level

Output Voltage (DVCC = 3 V)

High-Level Output Voltage (V)

Figure 5-8. Typical High-Level Output Current vs High-Level

Output Voltage (DVCC = 2 V)

5.12.5 Timer_A

Table 5-10. Timer_A Recommended Operating Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

Internal: SMCLK or ACLK,

External: TACLK,

Duty cycle = 50% ±10%

f_TA

Timer_A input clock frequency

2 V, 3 V

16 MHz

ns

All capture inputs, minimum pulse

duration required for capture

t_TA,capTimer_A capture timing

2 V, 3 V

20

Specifications

25

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

5.12.6 eUSCI

Table 5-11. eUSCI (UART Mode) Recommended Operating Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

Internal: SMCLK or MODCLK,

External: UCLK,

f_eUSCIeUSCI input clock frequency

2 V, 3 V

16 MHz

Duty cycle = 50% ±10%

BITCLK clock frequency

f_BITCLK

2 V, 3 V

5

MHz

(equals baud rate in Mbaud)

Table 5-12. eUSCI (UART Mode) Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

UCGLITx = 0

V_CC

TYP UNIT

12

UCGLITx = 1

UCGLITx = 2

UCGLITx = 3

40

ns

68

(1)

t_t

UART receive deglitch time

2 V, 3 V

110

(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are

correctly recognized, their duration should exceed the maximum specification of the deglitch time.

Table 5-13. eUSCI (SPI Master Mode) Recommended Operating Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX UNIT

Internal: SMCLK or MODCLK,

Duty cycle = 50% ±10%

f_eUSCI

eUSCI input clock frequency

8

MHz

Table 5-14. eUSCI (SPI Master Mode) Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX

UNIT

UCxCLK

cycles

t_STE,LEAD

t_STE,LAG

STE lead time, STE active to clock

UCSTEM = 1, UCMODEx = 01 or 10

1

UCxCLK

cycles

STE lag time, Last clock to STE inactive

SOMI input data setup time

UCSTEM = 1, UCMODEx = 01 or 10

1

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

45

35

0

t_SU,MI

ns

t_HD,MI

SOMI input data hold time

SIMO output data valid time⁽²⁾

SIMO output data hold time⁽³⁾

0

20

UCLK edge to SIMO valid,

C_L= 20 pF

t_VALID,MO

0

t_HD,MO

C_L= 20 pF

(1) f_UCxCLK= 1/2t_LO/HIwith t_LO/HI= max(t_{VALID,MO(eUSCI)}+ t_SU,SI(Slave), t_SU,MI(eUSCI)+ t_{VALID,SO(Slave)}

)

For the slave parameters t_SU,SI(Slave)and t_{VALID,SO(Slave)}, see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams

in Figure 5-9 and Figure 5-10.

(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data

on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-

9 and Figure 5-10.

26

Specifications

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_LOW/HIGH

t_SU,MI

t_HD,MI

SOMI

SIMO

t_VALID,MO

Figure 5-9. SPI Master Mode, CKPH = 0

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_LOW/HIGH

t_HD,MI

t_SU,MI

SOMI

SIMO

t_VALID,MO

Figure 5-10. SPI Master Mode, CKPH = 1

Specifications

27

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

Table 5-15. eUSCI (SPI Slave Mode) Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

MIN

55

MAX UNIT

t_STE,LEAD

t_STE,LAG

t_STE,ACC

t_STE,DIS

t_SU,SI

STE lead time, STE active to clock

ns

45

20

STE lag time, Last clock to STE inactive

ns

20

65

ns

40

STE access time, STE active to SOMI data out

40

ns

35

STE disable time, STE inactive to SOMI high

impedance

4

SIMO input data setup time

SIMO input data hold time

SOMI output data valid time⁽²⁾

ns

12

t_HD,SI

65

ns

40

UCLK edge to SOMI valid,

C_L= 20 pF

t_VALID,SO

5

(3)

t_HD,SO

SOMI output data hold time

C_L= 20 pF

ns

(1) f_UCxCLK= 1/2t_LO/HIwith t_LO/HI≥ max(t_{VALID,MO(Master)}+ t_SU,SI(eUSCI), t_{SU,MI(Master)}+ t_{VALID,SO(eUSCI)}

)

For the master parameters t_{SU,MI(Master)}and t_{VALID,MO(Master)}, see the SPI parameters of the attached master.

(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams

in Figure 5-11 and Figure 5-12.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-11

and Figure 5-12.

28

Specifications

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

t_STE,LEAD

t_STE,LAG

STE

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_SU,SIMO

t_HD,SIMO

t_LOW/HIGH

SIMO

SOMI

t_ACC

t_VALID,SOMI

t_DIS

Figure 5-11. SPI Slave Mode, CKPH = 0

t_STE,LEAD

t_STE,LAG

STE

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_LOW/HIGH

t_HD,SI

t_SU,SI

SIMO

SOMI

t_ACC

t_DIS

t_VALID,SO

Figure 5-12. SPI Slave Mode, CKPH = 1

Specifications

29

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

Table 5-16. eUSCI (I²C Mode) Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-13)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK or MODCLK,

External: UCLK,

f_eUSCI

eUSCI input clock frequency

16 MHz

Duty cycle = 50% ±10%

f_SCL

SCL clock frequency

2 V, 3 V

0

4.0

0.6

4.7

0.6

0

400 kHz

µs

f_SCL= 100 kHz

f_SCL> 100 kHz

f_SCL= 100 kHz

f_SCL> 100 kHz

t_HD,STA

Hold time (repeated) START

t_SU,STA

Setup time for a repeated START

2 V, 3 V

µs

t_HD,DAT

t_SU,DAT

Data hold time

Data setup time

2 V, 3 V

ns

250

4.0

0.6

50

f_SCL= 100 kHz

f_SCL> 100 kHz

UCGLITx = 0

UCGLITx = 1

UCGLITx = 2

UCGLITx = 3

UCCLTOx = 1

UCCLTOx = 2

UCCLTOx = 3

t_SU,STO

Setup time for STOP

2 V, 3 V

µs

600

25

300

ns

Pulse duration of spikes suppressed by

input filter

t_SP

2 V, 3 V

12.5

6.3

150

75

27

30

33

t_TIMEOUT

Clock low time-out

2 V, 3 V

ms

t_HD,STA

t_SU,STA

t_HD,STA

t_BUF

SDA

t_LOW

t_HIGH

t_SP

SCL

t_SU,DAT

t_SU,STO

t_HD,DAT

Figure 5-13. I²C Mode Timing

30

Specifications

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

5.12.7 ADC

Table 5-17. ADC, Power Supply and Input Range Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

2.0

0

TYP

MAX UNIT

DV_CC

V_(Ax)

ADC supply voltage

Analog input voltage range

3.6

V

All ADC pins

DV_CC

Operating supply current into

DVCC terminal, reference

current not included, repeat-

single-channel mode

2 V

3 V

185

207

f_ADCCLK= 5 MHz, ADCON = 1,

REFON = 0, SHT0 = 0, SHT1 = 0,

ADCDIV = 0, ADCCONSEQx = 10b

I_ADC

µA

Only one terminal Ax can be selected at one

time from the pad to the ADC capacitor array,

including wiring and pad

C_I

R_I,MUX

R_I,Misc

Input capacitance

2.2 V

1.6

34

2.0

2

pF

Input MUX ON resistance

DV_CC= 2 V, 0 V ≤ V_Ax≤ DV_CC

kΩ

Input miscellaneous

resistance

Table 5-18. ADC, 10-Bit Timing Parameters

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

For specified performance of ADC linearity

parameters

2 V to

3.6 V

f_ADCCLK

f_ADCOSC

0.45

5

5.5 MHz

Internal ADC oscillator

(MODCLK)

2 V to

3.6 V

ADCDIV = 0, f_ADCCLK= f_ADCOSC

4.5

5.0

5.5 MHz

REFON = 0, Internal oscillator,

10 ADCCLK cycles, 10-bit mode,

f_ADCOSC= 4.5 MHz to 5.5 MHz

2 V to

3.6 V

2.18

2.67

µs

t_CONVERT

Conversion time

External f_ADCCLKfrom ACLK, MCLK, or SMCLK,

ADCSSEL ≠ 0

2 V to

3.6 V

(1)

The error in a conversion started after t_ADCONis less

than ±0.5 LSB,

Reference and input signal already settled

R_S= 1000 Ω, R_I⁽²⁾= 36000 Ω, C_I= 3.5 pF,

approximately 8 Tau (t) are required for an error of

less than ±0.5 LSB⁽³⁾

Turn-on settling time of

the ADC

t_ADCON

100

ns

µs

2 V

3 V

1.5

2.0

t_Sample

Sampling time

(1) 12 × 1/f_ADCCLK

(2) R_I= R_I,MUX+ R_I,Misc

(3) t_Sample= ln(2ⁿ⁺¹) × τ, where n = ADC resolution, τ = (R_I+ R_S) × C_I

Specifications

31

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

MAX UNIT

Table 5-19. ADC, 10-Bit Linearity Parameters

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

2.4 V to

3.6 V

Integral linearity error (10-bit mode)

–2

2

E_I

V_DVCCas reference

LSB

2

2 V to

3.6 V

Integral linearity error (8-bit mode)

Differential linearity error (10-bit mode)

Differential linearity error (8-bit mode)

Offset error (10-bit mode)

–2

–1

2.4 V to

3.6 V

1

E_D

LSB

1

2 V to

3.6 V

–1

2.4 V to

3.6 V

–6.5

6.5

mV

6.5

E_O

2 V to

3.6 V

Offset error (8-bit mode)

V_DVCCas reference

–2.0

–3.0%

–2.0

2.0 LSB

3.0%

2.4 V to

3.6 V

Gain error (10-bit mode)

Internal 1.5-V reference

V_DVCCas reference

E_G

2.0 LSB

3.0%

2 V to

3.6 V

Gain error (8-bit mode)

Internal 1.5-V reference

V_DVCCas reference

–3.0%

–2.0

2.0 LSB

3.0%

2.4 V to

3.6 V

Total unadjusted error (10-bit mode)

Total unadjusted error (8-bit mode)

Internal 1.5-V reference

V_DVCCas reference

–3.0%

–2.0

E_T

2.0 LSB

3.0%

2 V to

3.6 V

Internal 1.5-V reference

ADCON = 1, INCH = 0Ch, T_A= 0°C

ADCON = 1, INCH = 0Ch

–3.0%

(1)

V_SENSOR

See

3 V

1.013

3.35

mV

(2)

TC_SENSORSee

mV/°C

ADCON = 1, INCH = 0Ch, Error of

conversion result ≤ 1 LSB, AM and all

LPM above LPM3

3 V

30

t_SENSOR

(sample)

Sample time required if channel 12 is

selected⁽³⁾

µs

ADCON = 1, INCH = 0Ch, Error of

conversion result ≤ 1 LSB, LPM3

100

(1) The temperature sensor offset can vary significantly. TI recommends a single-point calibration to minimize the offset error of the built-in

temperature sensor.

(2) The device descriptor structure contains calibration values for 30°C and 85°C for each of the available reference voltage levels. The

sensor voltage can be computed as V_SENSE= TC_SENSOR× (Temperature, °C) + V_SENSOR, where TC_SENSORand V_SENSORcan be

computed from the calibration values for higher accuracy.

(3) The typical equivalent impedance of the sensor is 700 kΩ. The sample time required includes the sensor-on time t_SENSOR(on)

.

32

Specifications

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

5.12.8 FRAM

Table 5-20. FRAM

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Read and write endurance

TEST CONDITIONS

MIN

10¹⁵

100

40

MAX UNIT

cycles

T_J= 25°C

t_Retention

Data retention duration

T_J= 70°C

T_J= 85°C

years

10

5.12.9 Emulation and Debug

Table 5-21. JTAG and Spy-Bi-Wire Interface Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Spy-Bi-Wire input frequency

V_CC

MIN

0

TYP

MAX UNIT

f_SBW

2 V, 3 V

10 MHz

t_SBW,Low

t_{SBW, En}

t_SBW,Rst

Spy-Bi-Wire low clock pulse duration

0.028

15

110

100

16

µs

(1)

Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)

Spy-Bi-Wire return to normal operation time

15

0

2 V

3 V

(2)

f_TCK

TCK input frequency, 4-wire JTAG

MHz

0

16

R_internal

Internal pulldown resistance on TEST

2 V, 3 V

20

35

50

kΩ

(1) Tools that access the Spy-Bi-Wire interface must wait for the t_SBW,Entime after pulling the TEST/SBWTCK pin high before applying the

first SBWTCK clock edge.

(2) f_TCKmay be restricted to meet the timing requirements of the module selected.

Specifications

33

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

6 Detailed Description

6.1 CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All

operations, other than program-flow instructions, are performed as register operations in conjunction with

seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-

register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter (PC), stack pointer (SP), status register

(SR), and constant generator (CG), respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be handled

with all instructions.

6.2 Operating Modes

The MSP430 has one active mode and several software selectable low-power modes of operation. An

interrupt event can wake up the device from low-power mode LPM0 or LPM3, service the request, and

restore back to the low-power mode on return from the interrupt program. Low-power modes LPM3.5 and

LPM4.5 disable the core supply to minimize power consumption.

Table 6-1. Operating Modes

AM

LPM0

CPU OFF

16 MHz

20 µA/MHz

instant

LPM3

STANDBY

40 kHz

1.2 µA

10 µs

LPM4

OFF

0

LPM3.5

LPM4.5

SHUTDOWN

0

MODE

ACTIVE

MODE

ONLY RTC

COUNTER

Maximum System Clock

Power Consumption at 25°C, 3 V

Wake-up time

16 MHz

126 µA/MHz

N/A

40 kHz

0.6 µA

without SVS

0.77 µA with

RTC only

13 nA

without SVS

10 µs

150 µs

RTC Counter,

I/O

Wake-up events

N/A

All

I/O

Full

Regulation

Full

Regulation

Partial Power Partial Power Partial Power

Regulator

Power Down

Down

Optional

On

Down

Optional

On

Down

Optional

On

Power

SVS

On

Optional

On

Brown Out

MCLK

SMCLK

FLL

Active

Optional

On

Off

Optional

Off

DCO

Off

Clock

MODCLK

REFO

Off

Optional

Off

ACLK

Off

XT1CLK

VLOCLK

CPU

Off

Optional

Off

FRAM

On

Off

Core

RAM

On

Off

Backup Memory⁽¹⁾

On

Off

(1) Backup memory contains one 32-byte register in the peripheral memory space. See Table 6-31 and Table 6-49 for its memory

allocation.

34

Detailed Description

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

Table 6-1. Operating Modes (continued)

AM

LPM0

LPM3

LPM4

LPM3.5

LPM4.5

MODE

Timer0_A3

ACTIVE

MODE

ONLY RTC

COUNTER

CPU OFF

STANDBY

OFF

SHUTDOWN

Optional

Off

Timer1_A3

WDT

Off

eUSCI_A0

eUSCI_B0

CRC

Off

Peripherals

Off

ADC

Optional

Off

RTC Counter

State Held

General Digital

Input/Output

On

Optional

State Held

Optional

State Held

Off

State Held

Off

I/O

Capacitive Touch I/O

Optional

6.3 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h. The

vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence

Table 6-2. Interrupt Sources, Flags, and Vectors

SYSTEM

INTERRUPT

WORD

ADDRESS

INTERRUPT SOURCE

INTERRUPT FLAG

PRIORITY

System Reset

Power up, Brownout, Supply supervisor,

External reset RST,

SVSHIFG

PMMRSTIFG

Watchdog time-out, Key violation,

FRAM uncorrectable bit error detection,

Software POR,

WDTIFG

PMMPORIFG, PMMBORIFG

SYSRSTIV

Reset

FFFEh

63, Highest

FLL unlock error

FLLUNLOCKIFG

System NMI

Vacant memory access,

JTAG mailbox,

VMAIFG

JMBINIFG, JMBOUTIFG

CBDIFG, UBDIFG

Nonmaskable

FFFCh

FFFAh

62

61

FRAM bit error detection

User NMI

External NMI,

Oscillator Fault

NMIIFG

OFIFG

Timer0_A3

Timer1_A3

TA0CCR0 CCIFG0

Maskable

FFF8h

FFF6h

FFF4h

FFF2h

60

59

58

57

TA0CCR1 CCIFG1, TA0CCR2

CCIFG2, TA0IFG (TA0IV)

TA1CCR0 CCIFG0

TA1CCR1 CCIFG1, TA1CCR2

CCIFG2, TA1IFG (TA1IV)

RTC Counter

RTCIFG

WDTIFG

Maskable

FFF0h

FFEEh

56

55

Watchdog Timer Interval mode

UCTXCPTIFG, UCSTTIFG,

UCRXIFG, UCTXIFG (UART mode)

UCRXIFG, UCTXIFG (SPI mode)

(UCA0IV))

eUSCI_A0 Receive or Transmit

Maskable

FFECh

54

Detailed Description

35

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

PRIORITY

Table 6-2. Interrupt Sources, Flags, and Vectors (continued)

SYSTEM

INTERRUPT

WORD

ADDRESS

INTERRUPT SOURCE

INTERRUPT FLAG

UCB0RXIFG, UCB0TXIFG (SPI

mode)

UCALIFG, UCNACKIFG,

UCSTTIFG, UCSTPIFG,

UCRXIFG0, UCTXIFG0,

UCRXIFG1, UCTXIFG1,

UCRXIFG2, UCTXIFG2,

UCRXIFG3, UCTXIFG3,

UCCNTIFG, UCBIT9IFG (I²C mode)

(UCB0IV)

eUSCI_B0 Receive or Transmit

Maskable

FFEAh

53

ADCIFG0, ADCINIFG, ADCLOIFG,

ADCHIIFG, ADCTOVIFG,

ADCOVIFG (ADCIV)

ADC

Maskable

FFE8h

52

P1

P2

P1IFG.0 to P1IFG.7 (P1IV)

P2IFG.0 to P2IFG.7 (P2IV)

Reserved

Maskable

FFE6h

FFE4h

51

50, Lowest

Reserved

FFE2h to FF88h

0FF86h

BSL Signature 2

BSL Signature 1

0FF84h

Signatures

JTAG Signature 2

JTAG Signature 1

0FF82h

0FF80h

6.4 Bootloader (BSL)

The BSL enables users to program the FRAM or RAM using a UART serial interface. Access to the device

memory through the BSL is protected by an user-defined password. Table 6-3 lists the BSL pin

requirements. BSL entry requires

a specific entry sequence on the RST/NMI/SBWTDIO and

TEST/SBWTCK pins. For a complete description of the features of the BSL and its implementation, see

the MSP430 FRAM Devices Bootloader (BSL) User's Guide.

Table 6-3. BSL Pin Requirements and Functions

DEVICE SIGNAL

BSL FUNCTION

Entry sequence signal

Data transmit

RST/NMI/SBWTDIO

TEST/SBWTCK

P1.0

P1.1

VCC

VSS

Data receive

Power supply

Ground supply

6.5 JTAG Standard Interface

The MSP430 family supports the standard JTAG interface which requires four signals for sending and

receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to

enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with

MSP430 development tools and device programmers. Table 6-4 lists the JTAG pin requirements. For

further details on interfacing to development tools and device programmers, see the MSP430 Hardware

Tools User's Guide. For a complete description of the features of the JTAG interface and its

implementation, see MSP430 Programming With the JTAG Interface.

36

Detailed Description

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

Table 6-4. JTAG Pin Requirements and Function

DEVICE SIGNAL

P1.4/MCLK/TCK/A4/VREF+

P1.5/TA0CLK/TMS/A5

P1.6/TA0.2/TDI/TCLK/A6

P1.7/TA0.1/TDO/A7

TEST/SBWTCK

DIRECTION

JTAG FUNCTION

JTAG clock input

JTAG state control

JTAG data input/TCLK input

JTAG data output

Enable JTAG pins

External reset

IN

OUT

IN

RST/NMI/SBWTDIO

VCC

IN

Power supply

VSS

Ground supply

6.6 Spy-Bi-Wire Interface (SBW)

The MSP430 family supports the 2-wire Spy-Bi-Wire interface. Spy-Bi-Wire can be used to interface with

MSP430 development tools and device programmers. Table 6-5 shows the Spy-Bi-Wire interface pin

requirements. For further details on interfacing to development tools and device programmers, see the

MSP430 Hardware Tools User's Guide.

Table 6-5. Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL

TEST/SBWTCK

RST/NMI/SBWTDIO

VCC

DIRECTION

IN

SBW FUNCTION

Spy-Bi-Wire clock input

Spy-Bi-Wire data input/output

Power supply

IN, OUT

VSS

Ground supply

6.7 FRAM

The FRAM can be programmed using the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the

CPU. Features of the FRAM include:

•

Byte and word access capability

Programmable wait state generation

Error correction coding (ECC)

6.8 Memory Protection

The device features memory protection that can restrict user access and enable write protection:

•

Securing the whole memory map to prevent unauthorized access from JTAG port or BSL, by writing

JTAG and BSL signatures using the JTAG port, SBW, the BSL, or in-system by the CPU.

•

Write protection enabled to prevent unwanted write operation to FRAM contents by setting the control

bits in System Configuration register 0. For more detailed information, see the SYS chapter in the

MSP430FR4xx and MSP430FR2xx Family User's Guide.

NOTE

The FRAM is protected by default on PUC. To write to FRAM during code execution, the

application must first clear the corresponding PFWP or DFWP bit in System Configuration

Register 0 to unprotect the FRAM.

Detailed Description

37

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

6.9 Peripherals

Peripherals are connected to the CPU through data, address, and control buses. All peripherals can be

handled by using all instructions in the memory map. For complete module description, see the

MSP430FR4xx and MSP430FR2xx Family User's Guide.

6.9.1 Power Management Module (PMM) and On-chip Reference Voltages

The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM

also includes supply voltage supervisor (SVS) and brownout protection. The brownout reset circuit (BOR)

is implemented to provide the proper internal reset signal to the device during power-on and power-off.

The SVS circuitry detects if the supply voltage drops below a user-selectable safe level. SVS circuitry is

available on the primary supply.

The device contains two on-chip reference: 1.5 V for internal reference and 1.2 V for external reference.

The 1.5-V reference is internally connected to ADC channel 13. DVCC is internally connected to ADC

channel 15. When DVCC is set as the reference voltage for ADC conversion, the DVCC can be easily

represent as Equation 1 by using ADC sampling 1.5-V reference without any external components

support.

DVCC = (1023 × 1.5 V) ÷ 1.5-V Reference ADC result

(1)

A 1.2-V reference voltage can be buffered and output to P1.4/MCLK/TCK/A4/VREF+, when the ADC

channel 4 is selected as the function. For more detailed information, see the MSP430FR4xx and

MSP430FR2xx Family User's Guide.

6.9.2 Clock System (CS) and Clock Distribution

The clock system includes a 32-kHz crystal oscillator (XT1), an internal very low-power low-frequency

oscillator (VLO), an integrated 32-kHz RC oscillator (REFO), an integrated internal digitally controlled

oscillator (DCO) that may use frequency-locked loop (FLL) locking with internal or external 32-kHz

reference clock, and on-chip asynchronous high-speed clock (MODCLK). The clock system is designed to

target cost-effective designs with minimal external components. A fail-safe mechanism is designed for

XT1. The clock system module offers the following clock signals.

•

Main Clock (MCLK): the system clock used by the CPU and all relevant peripherals accessed by the

bus. All clock sources except MODCLK can be selected as the source with a predivider of 1, 2, 4, 8,

16, 32, 64, or 128.

•

Sub-Main Clock (SMCLK): the subsystem clock used by the peripheral modules. SMCLK derives from

the MCLK with a predivider of 1, 2, 4, or 8. This means SMCLK is always equal to or less than MCLK.

Auxiliary Clock (ACLK): this clock is derived from the external XT1 clock or internal REFO clock up to

40 kHz.

All peripherals may have one or several clock sources depending on specific functionality. Table 6-6

shows the clock distribution used in this device.

38

Detailed Description

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

Table 6-6. Clock Distribution

CLOCK

SOURCE

SELECT

BITS

MCLK

SMCLK

ACLK

MODCLK

XT1CLK⁽¹⁾

VLOCLK

EXTERNAL PIN

Frequency

Range

DC to

16 MHz

DC to

16 MHz

DC to

40 kHz

DC to

40 kHz

10 kHz

±50%

5 MHz ±10%

CPU

N/A

Default

FRAM

RAM

N/A

CRC

N/A

I/O

N/A

TA0

TASSEL

UCSSEL

WDTSSEL

ADCSSEL

RTCSS

10b

01b

00b (TA0CLK pin)

00b (TA1CLK pin)

00b (UCA0CLK pin)

00b (UCB0CLK pin)

TA1

eUSCI_A0

eUSCI_B0

WDT

10b or 11b

00b

01b

10b

11b

ADC

10b or 11b

01b

00b

RTC

10b

(1) To enable XT1 functionality, configure P4SEL0.1 (XIN) and P4SEL0.2 (XOUT) before configuring the Clock System registers.

CPU

FRAM

SRAM

CRC

I/O

MCLK

Timer_A

0

Timer_A

1

eUSCI_

A0

eUSCI_

B0

WDT

RTC

ADC10

Clock System (CS)

SMCLK

ACLK

VLOCLK

MODCLK

XT1CLK

Figure 6-1. Clock Distribution Block Diagram

Detailed Description

39

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

6.9.3 General-Purpose Input/Output Port (I/O)

There are up to 60 I/O ports implemented, depending on the package.

•

P1, P2, P3, P4, P5, P6, and P7 are full 8-bit ports; P8 has 4 bits implemented.

All individual I/O bits are independently programmable.

Any combination of input, output, and interrupt conditions is possible.

Programmable pullup or pulldown on all ports.

Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for P1 and P2.

Read and write access to port-control registers is supported by all instructions.

Ports can be accessed byte-wise or word-wise in pairs.

Capacitive Touch I/O functionality is supported on all pins.

NOTE

Configuration of digital I/Os after BOR reset

To prevent any cross currents during start-up of the device, all port pins are high-impedance

with Schmitt triggers and module functions disabled. To enable the I/O functions after a BOR

reset, the ports must be configured first and then the LOCKLPM5 bit must be cleared. For

details, see the Configuration After Reset section in the Digital I/O chapter of the

MSP430FR4xx and MSP430FR2xx Family User's Guide.

40

Detailed Description

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

6.9.4 Watchdog Timer (WDT)

The primary function of the WDT module is to perform a controlled system restart after a software problem

occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not

needed in an application, the module can be configured as interval timer and can generate interrupts at

selected time intervals.

Table 6-7. WDT Clocks

NORMAL OPERATION

WDTSSEL

(WATCHDOG AND INTERVAL TIMER MODE)

00

01

10

11

SMCLK

ACLK

VLOCLK

6.9.5 System Module (SYS)

The SYS module handles many of the system functions within the device. These include Power-On Reset

(POR) and Power-Up Clear (PUC) handling, NMI source selection and management, reset interrupt vector

generators, bootloader entry mechanisms, and configuration management (device descriptors). SYS also

includes a data exchange mechanism through SBW called a JTAG mailbox mail box that can be used in

the application.

Table 6-8. System Module Interrupt Vector Registers

INTERRUPT VECTOR

ADDRESS

INTERRUPT EVENT

VALUE

PRIORITY

REGISTER

No interrupt pending

Brownout (BOR)

00h

02h

Highest

RSTIFG RST/NMI (BOR)

PMMSWBOR software BOR (BOR)

LPMx.5 wakeup (BOR)

Security violation (BOR)

Reserved

04h

06h

08h

0Ah

0Ch

0Eh

10h

SVSHIFG SVSH event (BOR)

Reserved

12h

SYSRSTIV, System Reset

015Eh

PMMSWPOR software POR (POR)

WDTIFG watchdog time-out (PUC)

WDTPW password violation (PUC)

FRCTLPW password violation (PUC)

Uncorrectable FRAM bit error detection

Peripheral area fetch (PUC)

PMMPW PMM password violation (PUC)

Reserved

14h

16h

18h

1Ah

1Ch

1Eh

20h

22h

FLL unlock (PUC)

24h

Reserved

26h to 3Eh

Lowest

Detailed Description

41

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

Table 6-8. System Module Interrupt Vector Registers (continued)

INTERRUPT VECTOR

REGISTER

ADDRESS

INTERRUPT EVENT

VALUE

PRIORITY

No interrupt pending

SVS low-power reset entry

Uncorrectable FRAM bit error detection

Reserved

00h

02h

Highest

04h

06h

Reserved

08h

Reserved

0Ah

Reserved

0Ch

SYSSNIV, System NMI

015Ch

Reserved

0Eh

Reserved

10h

VMAIFG Vacant memory access

JMBINIFG JTAG mailbox input

JMBOUTIFG JTAG mailbox output

Correctable FRAM bit error detection

Reserved

12h

14h

16h

18h

1Ah to 1Eh

00h

Lowest

Highest

Lowest

No interrupt pending

NMIIFG NMI pin or SVS_Hevent

OFIFG oscillator fault

Reserved

02h

SYSUNIV, User NMI

015Ah

04h

06h to 1Eh

6.9.6 Cyclic Redundancy Check (CRC)

The 16-bit cyclic redundancy check (CRC) module produces a signature based on a sequence of data

values and can be used for data checking purposes. The CRC generation polynomial is compliant with

CRC-16-CCITT standard of x¹⁶+ x¹²+ x⁵+ 1.

6.9.7 Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)

The eUSCI modules are used for serial data communications. The eUSCI_A module supports either

UART or SPI communications. The eUSCI_B module supports either SPI or I²C communications.

Additionally, eUSCI_A supports automatic baud-rate detection and IrDA.

Table 6-9. eUSCI Pin Configurations

P1.0

P1.1

P1.2

P1.3

UART

TXD

RXD

–

SPI

SIMO

SOMI

SCLK

STE

eUSCI_A0

eUSCI_B0

–

I²C

SPI

P5.0

P5.1

P5.2

P5.3

–

STE

–

SCLK

SIMO

SOMI

SDA

SCL

42

Detailed Description

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

6.9.8 Timers (Timer0_A3, Timer1_A3)

The Timer0_A3 and Timer1_A3 modules are 16-bit timers and counters with three capture/compare

registers each. Each timer can support multiple captures or compares, PWM outputs, and interval timing.

Each timer has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow

conditions and from each of the capture/compare registers. The CCR0 registers on both TA0 and TA1 are

not externally connected and can only be used for hardware period timing and interrupt generation. In Up

mode, they can be used to set the overflow value of the counter.

Table 6-10. Timer0_A3 Signal Connections

DEVICE INPUT

SIGNAL

MODULE INPUT

NAME

MODULE OUTPUT

SIGNAL

DEVICE OUTPUT

SIGNAL

PORT PIN

MODULE BLOCK

P1.5

TA0CLK

TACLK

ACLK

ACLK (internal)

SMCLK (internal)

Timer

N/A

TA0

TA1

SMCLK

From Capacitive

Touch I/O (internal)

INCLK

CCI0A

CCI0B

Timer1_A3 CCI0B

input

CCR0

CCR1

DVSS

DVCC

TA0.1

GND

VCC

P1.7

P1.6

CCI1A

TA0.1

Timer1_A3 CCI1B

input

From RTC (internal)

CCI1B

DVSS

DVCC

TA0.2

GND

VCC

CCI2A

TA0.2

Timer1_A3 INCLK

Timer1_A3 CCI2B

input,

From Capacitive

Touch I/O (internal)

CCI2B

CCR2

TA2

IR Input

DVSS

DVCC

GND

VCC

Detailed Description

43

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

Table 6-11. Timer1_A3 Signal Connections

DEVICE INPUT

SIGNAL

MODULE INPUT

NAME

MODULE OUTPUT

SIGNAL

DEVICE OUTPUT

SIGNAL

PORT PIN

MODULE BLOCK

P8.2

TA1CLK

TACLK

ACLK

ACLK (internal)

SMCLK (internal)

Timer

N/A

TA0

TA1

TA2

SMCLK

Timer0_A3 CCR2B

output (internal)

INCLK

CCI0A

CCI0B

Timer0_A3 CCR0B

output (internal)

CCR0

CCR1

CCR2

DVSS

DVCC

TA1.1

GND

VCC

P4.0

P8.3

CCI1A

TA1.1

Timer0_A3 CCR1B

output (internal)

CCI1B

To ADC trigger

DVSS

DVCC

TA1.2

GND

VCC

CCI2A

TA1.2

Timer0_A3 CCR2B

output (internal)

CCI2B

IR Input

DVSS

DVCC

GND

VCC

The interconnection of Timer0_A3 and Timer1_A3 can be used to modulate the eUSCI_A pin of

UCA0TXD/UCA0SIMO in either ASK or FSK mode. This configuration helps an application easily acquire

a modulated infrared command for directly driving an external IR diode.

The IR functions are controlled by the following bits in the System Configuration 1 (SYSCFG1) register:

IREN (enable), IRPSEL (polarity select), IRMSEL (mode select), IRDSSEL (data select), and IRDATA

(data). For more information, see the SYS chapter in the MSP430FR4xx and MSP430FR2xx Family

User's Guide.

44

Detailed Description

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

6.9.9 Real-Time Clock (RTC) Counter

The RTC counter is a 16-bit modulo counter that is functional in AM, LPM0, LPM3, and LPM3.5. The RTC

can periodically wake up the CPU from LPM0, LPM3, or LPM3.5 based on timing from a low-power clock

source such as the XT1 and VLO clocks. In AM, RTC can be driven by SMCLK to generate high-

frequency timing events and interrupts. The RTC overflow events trigger:

•

Timer0_A3 CCR1B

ADC conversion trigger when ADCSHSx bits are set as 01b

6.9.10 10-Bit Analog Digital Converter (ADC)

The 10-bit ADC module supports fast 10-bit analog-to-digital conversions with single-ended input. The

module implements a 10-bit SAR core, sample select control, reference generator and a conversion result

buffer. A window comparator with a lower and upper limit allows CPU independent result monitoring with

three window comparator interrupt flags.

The ADC supports 10 external inputs and four internal inputs (see Table 6-12).

Table 6-12. ADC Channel Connections

ADCINCHx

ADC CHANNELS

EXTERNAL PIN OUT

0

1

A0/Veref–

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P8.0⁽²⁾

P8.1⁽²⁾

N/A

A1/Veref+

2

A2

3

A3

A4⁽¹⁾

4

5

A5

6

A6

7

A7

8

A8

9

A9

Not used

10

11

12

13

14

15

Not used

N/A

On-chip temperature sensor

Reference voltage (1.5 V)

DVSS

N/A

DVCC

N/A

(1) When A4 is used, the PMM 1.2-V reference voltage can be output to this pin by setting the PMM

control register. The 1.2-V voltage can be directly measured by A4 channel.

(2) P8.0 and P8.1 are only available in the LQFP-64 package.

The A/D conversion can be started by software or a hardware trigger. Table 6-13 shows the trigger

sources that are available.

Table 6-13. ADC Trigger Signal Connections

ADCSHSx

TRIGGER SOURCE

BINARY

DECIMAL

00

01

10

11

0

1

2

3

ADCSC bit (software trigger)

RTC event

TA1.1B

TA1.2B

Detailed Description

45

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

6.9.11 Embedded Emulation Module (EEM)

The EEM supports real-time in-system debugging. The EEM on these devices has the following features:

•

Three hardware triggers or breakpoints on memory access

One hardware trigger or breakpoint on CPU register write access

Up to four hardware triggers can be combined to form complex triggers or breakpoints

One cycle counter

Clock control on module level

46

Detailed Description

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

6.9.12 Input/Output Diagrams

6.9.12.1 Port P1 Input/Output With Schmitt Trigger

A0 to A7

From ADC A

P1REN.x

P1DIR.x

0

1

From Module

DVSS

DVCC

0

1

P1OUT.x

0

1

From Module

P1SEL0.x

EN

D

To module

P1IN.x

P1IE.x

Bus

Keeper

P1 Interrupt

D

S

Q

P1.0/UCA0TXD/UCA0SIMO/A0

P1.1/UCA0RXD/UCA0SOMI/A1

P1.2/UCA0CLK/A2

P1IFG.x

P1.3/UCA0STE/A3

Edge

Select

P1.4/MCLK/TCK/A4/VREF+

P1.5/TA0CLK/TMS/A5

P1.6/TA0.2/TDI/TCLK/A6

P1.7/TA0.1/TDO/A7

P1IES.x

From JTAG

To JTAG

Figure 6-2. Port P1 Input/Output With Schmitt Trigger

Detailed Description

47

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

Table 6-14. Port P1 Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME (P1.x)

x

FUNCTION

P1.0 (I/O)

P1DIR.x

P1SEL0.x

ADCPCTLx⁽²⁾

JTAG

N/A

I: 0; O: 1

0

1

X

0

1

X

0

1

X

0

1

X

0

P1.0/UCA0TXD/UCA0SIMO/A0

0

UCA0TXD/UCA0SIMO

A0

X

0

N/A

X

1 (x = 0)

N/A

P1.1 (I/O)

UCA0RXD/UCA0SOMI

A1

I: 0; O: 1

0

N/A

P1.1/UCA0RXD/UCA0SOMI/A1

P1.2/UCA0CLK/A2

1

2

3

X

0

N/A

X

1 (x = 1)

N/A

P1.2 (I/O)

UCA0CLK

A2

I: 0; O: 1

0

N/A

X

0

N/A

X

1 (x = 2)

N/A

P1.3 (I/O)

UCA0STE

A3

I: 0; O: 1

0

N/A

P1.3/UCA0STE/A3

X

0

1 (x = 3)

0

N/A

X

N/A

P1.4 (I/O)

VSS

I: 0; O: 1

Disabled

0

1

0

Disabled

P1.4/MCLK/TCK/A4/VREF+

P1.5/TA0CLK/TMS/A5

4

5

6

7

MCLK

1

A4, VREF+

JTAG TCK

P1.5 (I/O)

TA0CLK

VSS

X

0

1 (x = 4)

Disabled

TCK

X

0

I: 0; O: 1

Disabled

0

1

0

Disabled

1

A5

X

0

1 (x = 5)

Disabled

TMS

JTAG TMS

P1.6 (I/O)

TA0.CCI2A

TA0.2

X

0

I: 0; O: 1

Disabled

0

1

0

Disabled

P1.6/TA0.2/TDI/TCLK/A6

1

A6

X

0

1 (x = 6)

Disabled

TDI/TCLK

Disabled

JTAG TDI/TCLK

P1.7 (I/O)

TA0.CCI1A

TA0.1

X

0

I: 0; O: 1

0

1

0

Disabled

P1.7/TA0.1/TDO/A7

(1) X = don't care

A7

X

1 (x = 7)

X

Disabled

TDO

JTAG TDO

(2) Setting the ADCPCTLx bit in SYSCFG2 register disables both the output driver and the input Schmitt trigger to prevent leakage when

analog signals are applied.

48

Detailed Description

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

6.9.12.2 Port P2 Input/Output With Schmitt Trigger

P2REN.x

P2DIR.x

DVSS

DVCC

0

1

P2OUT.x

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

P2IN.x

P2IE.x

Bus

Keeper

P2 Interrupt

1

D

S

Q

P2IFG.x

P2IES.x

1

Edge

Select

Figure 6-3. Port P2 Input/Output With Schmitt Trigger

Table 6-15. Port P2 Pin Functions

CONTROL BITS AND

SIGNALS

PIN NAME (P2.x)

x

FUNCTION

P2DIR.x

I: 0; O: 1

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

0

1

2

3

4

5

6

7

P2.0 (I/O)

P2.1 (I/O)

P2.2 (I/O)

P2.3 (I/O)

P2.4 (I/O)

P2.5 (I/O)

P2.6 (I/O)

P2.7 (I/O)

Detailed Description

49

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

6.9.12.3 Port P3 Input/Output With Schmitt Trigger

P3REN.x

P3DIR.x

DVSS

DVCC

0

1

P3OUT.x

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

P3IN.x

Bus

Keeper

Figure 6-4. Port P3 Input/Output With Schmitt Trigger

Table 6-16. Port P3 Pin Functions

CONTROL BITS AND

SIGNALS

PIN NAME (P3.x)

x

FUNCTION

P3DIR.x

I: 0; O: 1

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

0

1

2

3

4

5

6

7

P3.0 (I/O)

P3.1 (I/O)

P3.2 (I/O)

P3.3 (I/O)

P3.4 (I/O)

P3.5 (I/O)

P3.6 (I/O)

P3.7 (I/O)

50

Detailed Description

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

6.9.12.4 Port P4.0 Input/Output With Schmitt Trigger

P4REN.x

P4DIR.x

0

1

From Module

DVSS

DVCC

0

1

P4OUT.x

0

1

From Module

P4SEL0.x

EN

D

To module

P4IN.x

Bus

Keeper

P4.0/TA1.1

Figure 6-5. Port P4.0 Input/Output With Schmitt Trigger

Table 6-17. Port P4.0 Pin Functions

CONTROL BITS AND SIGNALS

PIN NAME (P4.x)

x

FUNCTION

P4DIR.x

P4SEL0.x

P4.0 (I/O)

TA1.CCI1A

TA1.1

I: 0; O: 1

0

P4.0/TA1.1

0

1

Detailed Description

51

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

6.9.12.5 Port P4.1 and P4.2 Input/Output With Schmitt Trigger

XIN, XOUT

P4REN.x

P4DIR.x

DVSS

DVCC

0

1

P4OUT.x

P4SEL0.x

P4IN.x

Bus

Keeper

P4.1/XIN

P4.2/XOUT

Figure 6-6. Port P4.1 and P4.2 Input/Output With Schmitt Trigger

Table 6-18. Port P4.1 and P4.2 Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME (P4.x)

x

1

2

FUNCTION

P4DIR.x

I: 0; O: 1

X

P4SEL0.x

P4.1 (I/O)

XIN

0

1

0

1

P4.1/XIN

P4.2 (I/O)

XOUT

I: 0; O: 1

X

P4.2/XOUT

(1) X = don't care

52

Detailed Description

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

6.9.12.6 Port 4.3, P4.4, P4.5, P4.6, and P4.7 Input/Output With Schmitt Trigger

P4REN.x

P4DIR.x

DVSS

DVCC

0

1

P4OUT.x

P4.3

P4.4

P4.5

P4.6

P4.7

P4IN.x

Bus

Keeper

Figure 6-7. Port 4.3, P4.4, P4.5, P4.6, and P4.7 Input/Output With Schmitt Trigger

Table 6-19. Port P4.3, P4.4, P4.5, P4.6, and P4.7 Pin Functions

CONTROL BITS AND

SIGNALS

P4DIR.x

I: 0; O: 1

PIN NAME (P4.x)

x

FUNCTION

P4.3

P4.4

P4.5

P4.6

P4.7

3

4

5

6

7

P4.3 (I/O)

P4.4 (I/O)

P4.5 (I/O)

P4.6 (I/O)

P4.7 (I/O)

Detailed Description

53

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

6.9.12.7 Port P5.0, P5.1, P5.2, and P5.3 Input/Output With Schmitt Trigger

P5REN.x

P5DIR.x

0

1

From Module

DVSS

DVCC

0

1

P5OUT.x

0

1

From Module

P5.0/UCB0STE

P5.1/UCB0CLK

P5SEL0.x

P5.2/UCB0SIMO/UCB0SDA

P5.3/UCB0SOMI/UCB0SCL

EN

D

To module

P5IN.x

Bus

Keeper

Figure 6-8. Port P5.0, P5.1, P5.2, and P5.3 Input/Output With Schmitt Trigger

Table 6-20. Port P5.0, P5.1, P5.2, and P5.3 Pin Functions

CONTROL BITS AND SIGNALS

PIN NAME (P5.x)

x

0

1

2

3

FUNCTION

P5DIR.x

P5SEL0.x

P5.0 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

P5.0/UCB0STE

UCB0STE

0

P5.1 (I/O)

I: 0; O: 1

P5.1/UCB0CLK

UCB0CLK

0

P5.2 (I/O)

I: 0; O: 1

P5.2/UCB0SIMO/UCB0SDA

P5.3/UCB0SOMI/UCB0SCL

UCB0SIMO/UCB0SDA

P5.3 (I/O)

0

I: 0; O: 1

0

UCB0SOMI/UCB0SCL

54

Detailed Description

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

6.9.12.8 Port P5.4, P5.5, P5.6, and P5.7 Input/Output With Schmitt Trigger

P5REN.x

P5DIR.x

DVSS

DVCC

0

1

P5OUT.x

P5.4

P5.5

P5.6

P5.7

P5IN.x

Bus

Keeper

Figure 6-9. Port P5.4, P5.5, P5.6, and P5.7 Input/Output With Schmitt Trigger

Table 6-21. Port P5.4, P5.5, P5.6, and P5.7 Pin Functions

CONTROL BITS AND

SIGNALS

PIN NAME (P5.x)

x

FUNCTION

P5DIR.x

I: 0; O: 1

P5.4

P5.5

P5.6

P5.7

4

5

6

7

P5.4 (I/O)

P5.5 (I/O)

P5.6 (I/O)

P5.7 (I/O)

Detailed Description

55

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

6.9.12.9 Port P6.0, P6.1, P6.2, and P6.3 Input/Output With Schmitt Trigger

P6REN.x

P6DIR.x

DVSS

DVCC

0

1

P6OUT.x

P6.0

P6.1

P6.2

P6.3

P6IN.x

Bus

Keeper

Figure 6-10. Port P6.0, P6.1, P6.2, and P6.3 Input/Output With Schmitt Trigger

Table 6-22. Port P6 Pin Functions

CONTROL BITS AND

SIGNALS

P6DIR.x

I: 0; O: 1

PIN NAME (P6.x)

x

FUNCTION

P6.0

P6.1

P6.2

P6.3

0

1

2

3

P6.0 (I/O)

P6.1 (I/O)

P6.2 (I/O)

P6.3 (I/O)

56

Detailed Description

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

6.9.12.10 Port P6.4, P6.5, P6.6, and P6.7 Input/Output With Schmitt Trigger

P6REN.x

P6DIR.x

DVSS

DVCC

0

1

P6OUT.x

P6.4

P6.5

P6.6

P6.7

P6IN.x

Bus

Keeper

Figure 6-11. Port P6.4, P6.5, P6.6, and P6.7 Input/Output With Schmitt Trigger

Table 6-23. Port P6.4, P6.5, P6.6, and P6.7 Pin Functions

CONTROL BITS AND

SIGNALS

P6DIR.x

I: 0; O: 1

PIN NAME (P6.x)

x

FUNCTION

P6.4

P6.5

P6.6

P6.7

4

5

6

7

P6.4 (I/O)

P6.5 (I/O)

P6.6 (I/O)

P6.7 (I/O)

Detailed Description

57

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

6.9.12.11 Port P7.0, P7.1, P7.2, and P7.3 Input/Output With Schmitt Trigger

P7REN.x

P7DIR.x

DVSS

DVCC

0

1

P7OUT.x

P7.0

P7.1

P7.2

P7.3

P7IN.x

Bus

Keeper

Figure 6-12. Port P7.0, P7.1, P7.2, and P7.3 Input/Output With Schmitt Trigger

Table 6-24. Port P7.0, P7.1, P7.2, and P7.3 Pin Functions

CONTROL BITS AND

SIGNALS

P7DIR.x

I: 0; O: 1

PIN NAME (P7.x)

x

FUNCTION

P7.0

P7.1

P7.2

P7.3

0

1

2

3

P7.0 (I/O)

P7.1 (I/O)

P7.2 (I/O)

P7.3 (I/O)

58

Detailed Description

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

6.9.12.12 Port P7.4, P7.5, P7.6, and P7.7 Input/Output With Schmitt Trigger

P7REN.x

P7DIR.x

DVSS

DVCC

0

1

P7OUT.x

P7.4

P7.5

P7.6

P7.7

P7IN.x

Bus

Keeper

Figure 6-13. Port P7.4, P7.5, P7.6, and P7.7 Input/Output With Schmitt Trigger

Table 6-25. Port P7.4, P7.5, P7.6, and P7.7 Pin Functions

CONTROL BITS AND

SIGNALS

P7DIR.x

I: 0; O: 1

PIN NAME (P7.x)

x

FUNCTION

P7.4

P7.5

P7.6

P7.7

4

5

6

7

P7.4 (I/O)

P7.5 (I/O)

P7.6 (I/O)

P7.7 (I/O)

Detailed Description

59

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

6.9.12.13 Port P8.0 and P8.1 Input/Output With Schmitt Trigger

A8, A9

From ADC A

P8REN.x

P8DIR.x

0

1

From Module

DVSS

DVCC

0

1

P8OUT.x

0

1

From MCLK, ACLK

P8SEL0.x

EN

D

To module

P8IN.x

Bus

Keeper

P8.0/SMCLK/A8

P8.1/ACLK/A9

Figure 6-14. Port P8.0 and P8.1 Input/Output With Schmitt Trigger

Table 6-26. Port P8.0 and P8.1 Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME (P8.x)

x

FUNCTION

P8DIR.x

P8SEL0.x

ADCPCTLx⁽²⁾

P8.0 (I/O)

VSS

I: 0; O: 1

0

P8.0/SMCLK/A8

0

1

0

SMCLK

A8

1

X

0

1 (x = 8)

0

P8.1 (I/O)

VSS

I: 0; O: 1

0

1

P8.1/ACLK/A9

1

0

ACLK

A9

X

1 (x = 9)

(1) X = don't care

(2) Setting the ADCPCTLx bit in SYSCFG2 register disables both the output driver and the input Schmitt trigger to prevent leakage when

analog signals are applied.

60

Detailed Description

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

6.9.12.14 Port P8.2 and P8.3 Input/Output With Schmitt Trigger

P8REN.x

P8DIR.x

0

1

From Module

DVSS

DVCC

0

1

P8OUT.x

0

1

From Module

P8SEL0.x

EN

D

To module

P8IN.x

Bus

Keeper

P8.2/TA1CLK

P8.3/TA1.2

Figure 6-15. Port P8.2 and P8.3 Input/Output With Schmitt Trigger

Table 6-27. Port P8.2 and P8.3 Pin Functions

CONTROL BITS AND SIGNALS

PIN NAME (P8.x)

x

FUNCTION

P8DIR.x

P8SEL0.x

P8.2 (I/O)

TA1 CLK

VSS

I: 0; O: 1

0

P8.2/TA1CLK

2

0

1

0

1

P8.3 (I/O)

TA1.CCI2A

TA1.2

I: 0; O: 1

P8.3/TA1.2

3

0

1

Detailed Description

61

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

6.10 Device Descriptors (TLV)

Table 6-28 lists the Device IDs of the MSP430FR203x device variants. Table 6-29 lists the contents of the

device descriptor tag-length-value (TLV) structure for MSP430FR203x devices.

Table 6-28. Device IDs

DEVICE ID

DEVICE

1A04h

75h

1A05h

82h

MSP430FR2033

MSP430FR2032

78h

82h

Table 6-29. Device Descriptors

MSP430FR203x

ADDRESS

DESCRIPTION

Info Length

VALUE

06h

1A00h

1A01h

1A02h

1A03h

1A04h

1A05h

1A06h

1A07h

1A08h

1A09h

1A0Ah

1A0Bh

1A0Ch

1A0Dh

1A0Eh

1A0Fh

1A10h

1A11h

1A12h

1A13h

1A14h

1A15h

1A16h

1A17h

1A18h

1A19h

1A1Ah

1A1Bh

1A1Ch

1A1Dh

CRC Length

CRC Value⁽¹⁾

06h

Per unit

Information Block

Device ID

See Table 6-28

Hardware Revision

Firmware Revision

Die Record Tag

Per unit

08h

Die Record Length

0Ah

Per unit

11h

Lot Wafer ID

Die Record

Die X Position

Die Y Position

Test Result

ADC Calibration Tag

ADC Calibration Length

08h

Per unit

ADC Gain Factor

ADC Calibration

ADC Offset

ADC 1.5-V Reference Temperature Sensor 30°C

ADC 1.5-V Reference Temperature Sensor 85°C

(1) The CRC value covers the checksum from 1A04h to 1A77h by applying the CRC-CCITT-16 polynomial of x¹⁶+ x¹²+ x⁵+ 1.

62 Detailed Description

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

Table 6-29. Device Descriptors (continued)

MSP430FR203x

DESCRIPTION

ADDRESS

1A1Eh

1A1Fh

1A20h

VALUE

12h

Calibration Tag

Calibration Length

04h

Per unit

Reference and DCO

Calibration

1.5-V Reference Factor

1A21h

1A22h

DCO Tap Settings for 16 MHz, Temperature 30°C⁽²⁾

1A23h

(2) This value can be directly loaded into DCO bits in CSCTL0 register to get accurate 16-MHz frequency at room temperature, especially

when MCU exits from LPM3 and below. TI suggests using a predivider to decrease the frequency, if the temperature drift might result an

overshoot beyond 16 MHz.

6.11 Memory

Table 6-30 summarizes the memory map of the MSP430FR203x devices.

Table 6-30. Memory Organization

ACCESS

MSP430FR2033

MSP430FR2032

Memory (FRAM)

Main: interrupt vectors and signatures

Main: code memory

15KB

FFFFh to FF80h

FFFFh to C400h

8KB

FFFFh to FF80h

FFFFh to E000h

Read/Write

(Optional Write Protect)⁽¹⁾

2KB

27FFh to 2000h

1KB

23FFh to 2000h

RAM

Read/Write

512B

19FFh to 1800h

512B

19FFh to 1800h

Information Memory (FRAM)

Bootloader (BSL) Memory (ROM)

Peripherals

(Optional Write Protect)⁽²⁾

1KB

13FFh to 1000h

1KB

13FFh to 1000h

Read only

4KB

0FFFh to 0000h

4KB

0FFFh to 0000h

Read/Write

(1) The Program FRAM can be write protected by setting PFWP bit in SYSCFG0 register. See the SYS chapter in the MSP430FR4xx and

MSP430FR2xx Family User's Guide for more details

(2) The Information FRAM can be write protected by setting DFWP bit in SYSCFG0 register. See the SYS chapter in the MSP430FR4xx

and MSP430FR2xx Family User's Guide for more details

Detailed Description

63

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

6.11.1 Peripheral File Map

Table 6-31 shows the base address and the memory size of the register region for each peripheral, and

Table 6-32 through Table 6-50 show all of the available registers for each peripheral and their address

offsets.

Table 6-31. Peripherals Summary

MODULE NAME

Special Functions

PMM

BASE ADDRESS

0100h

SIZE

REGISTERS

Table 6-32

Table 6-33

Table 6-34

Table 6-35

Table 6-36

Table 6-37

Table 6-38

Table 6-39

Table 6-40

Table 6-41

Table 6-42

Table 6-43

Table 6-44

Table 6-45

Table 6-46

Table 6-47

Table 6-48

Table 6-49

Table 6-50

0010h

0020h

0030h

0020h

0010h

0008h

0002h

0020h

0010h

0030h

0010h

0020h

0030h

0020h

0040h

0120h

SYS

0140h

CS

0180h

FRAM

01A0h

01C0h

01CCh

0200h

CRC

WDT

Port P1, P2

Port P3, P4

Port P5, P6

Port P7, P8

Capacitive Touch I/O

Timer0_A3

Timer1_A3

RTC

0220h

0240h

0260h

02E0h

0300h

0340h

03C0h

0500h

eUSCI_A0

eUSCI_B0

Backup Memory

ADC

0540h

0660h

0700h

64

Detailed Description

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

Table 6-32. Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION

REGISTER

SFRIE1

OFFSET

00h

SFR interrupt enable

SFR interrupt flag

SFRIFG1

SFRRPCR

02h

SFR reset pin control

04h

Table 6-33. PMM Registers (Base Address: 0120h)

REGISTER DESCRIPTION

REGISTER

PMMCTL0

PMMCTL1

PMMCTL2

PMMIFG

OFFSET

00h

PMM control 0

PMM control 1

PMM control 2

PMM interrupt flags

PM5 control 0

02h

04h

0Ah

PM5CTL0

10h

Table 6-34. SYS Registers (Base Address: 0140h)

REGISTER DESCRIPTION

REGISTER

SYSCTL

OFFSET

00h

System control

Bootloader configuration area

JTAG mailbox control

JTAG mailbox input 0

JTAG mailbox input 1

JTAG mailbox output 0

JTAG mailbox output 1

Bus Error vector generator

User NMI vector generator

System NMI vector generator

Reset vector generator

System configuration 0

System configuration 1

System configuration 2

SYSBSLC

SYSJMBC

SYSJMBI0

SYSJMBI1

SYSJMBO0

SYSJMBO1

SYSBERRIV

SYSUNIV

SYSSNIV

02h

06h

08h

0Ah

0Ch

0Eh

18h

1Ah

1Ch

1Eh

20h

SYSRSTIV

SYSCFG0

SYSCFG1

SYSCFG2

22h

24h

Table 6-35. CS Registers (Base Address: 0180h)

REGISTER DESCRIPTION

REGISTER

CSCTL0

CSCTL1

CSCTL2

CSCTL3

CSCTL4

CSCTL5

CSCTL6

CSCTL7

CSCTL8

OFFSET

00h

CS control register 0

CS control register 1

CS control register 2

CS control register 3

CS control register 4

CS control register 5

CS control register 6

CS control register 7

CS control register 8

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

Table 6-36. FRAM Registers (Base Address: 01A0h)

REGISTER DESCRIPTION

REGISTER

FRCTL0

OFFSET

00h

FRAM control 0

General control 0

General control 1

GCCTL0

GCCTL1

04h

06h

Detailed Description

65

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

Table 6-37. CRC Registers (Base Address: 01C0h)

REGISTER DESCRIPTION

REGISTER

CRC16DI

OFFSET

CRC data input

00h

02h

04h

06h

CRC data input reverse byte

CRC initialization and result

CRC result reverse byte

CRCDIRB

CRCINIRES

CRCRESR

Table 6-38. WDT Registers (Base Address: 01CCh)

REGISTER DESCRIPTION

REGISTER

OFFSET

Watchdog timer control

WDTCTL

00h

Table 6-39. Port P1, P2 Registers (Base Address: 0200h)

REGISTER DESCRIPTION

REGISTER

P1IN

OFFSET

00h

Port P1 input

Port P1 output

P1OUT

P1DIR

P1REN

P1SEL0

P1IV

02h

Port P1 direction

04h

Port P1 pulling register enable

Port P1 selection 0

06h

0Ah

0Eh

18h

Port P1 interrupt vector word

Port P1 interrupt edge select

Port P1 interrupt enable

Port P1 interrupt flag

Port P2 input

P1IES

P1IE

1Ah

1Ch

01h

P1IFG

P2IN

Port P2 output

P2OUT

P2DIR

P2REN

P2SEL0

P2IV

03h

Port P2 direction

05h

Port P2 pulling register enable

Port P2 selection 0⁽¹⁾

Port P2 interrupt vector word

Port P2 interrupt edge select

Port P2 interrupt enable

Port P2 interrupt flag

07h

0Bh

1Eh

19h

P2IES

P2IE

1Bh

1Dh

P2IFG

(1) Port P2 selection register does not feature any valid bits. P2SEL0 presents for 16-bit Port A operation with P1SEL0.

Table 6-40. Port P3, P4 Registers (Base Address: 0220h)

REGISTER DESCRIPTION

REGISTER

P3IN

OFFSET

00h

Port P3 input

Port P3 output

Port P3 direction

P3OUT

P3DIR

02h

04h

Port P3 pulling register enable

Port P3 selection 0⁽¹⁾

Port P4 input

P3REN

P3SEL0

P4IN

06h

0Ah

01h

Port P4 output

P4OUT

P4DIR

03h

Port P4 direction

05h

Port P4 pulling register enable

Port P4 selection 0

P4REN

P4SEL0

07h

0Bh

(1) Port P3 selection register does not feature any valid bits. P3SEL0 presents for 16-bit Port B operation with P4SEL0.

66

Detailed Description

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

Table 6-41. Port P5, P6 Registers (Base Address: 0240h)

REGISTER DESCRIPTION

REGISTER

P5IN

OFFSET

00h

Port P5 input

Port P5 output

Port P5 direction

P5OUT

P5DIR

02h

04h

Port P5 pulling register enable

Port P5 selection 0

Port P6 input

P5REN

P5SEL0

P6IN

06h

0Ah

01h

Port P6 output

P6OUT

P6DIR

03h

Port P6 direction

05h

Port P6 pulling register enable

Port P6 selection 0⁽¹⁾

P6REN

P6SEL0

07h

0Bh

(1) Port P6 selection register does not feature any valid bits. P6SEL0 presents for 16-bit Port C operation with P5SEL0.

Table 6-42. Port P7, P8 Registers (Base Address: 0260h)

REGISTER DESCRIPTION

REGISTER

P7IN

OFFSET

00h

Port P7 input

Port P7 output

Port P7 direction

P7OUT

P7DIR

02h

04h

Port P7 pulling register enable

Port P7 selection 0⁽¹⁾

Port P8 input

P7REN

P7SEL0

P8IN

06h

0Ah

01h

Port P8 output

P8OUT

P8DIR

03h

Port P8 direction

05h

Port P8 pulling register enable

Port P8 selection 0

P8REN

P8SEL0

07h

0Bh

(1) Port P7 selection register does not feature any valid bits. P7SEL0 presents for 16-bit Port D operation with P8SEL0.

Table 6-43. Capacitive Touch I/O Registers (Base Address: 02E0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Capacitive Touch I/O 0 control

CAPTIO0CTL

0Eh

Table 6-44. Timer0_A3 Registers (Base Address: 0300h)

REGISTER DESCRIPTION

REGISTER

TA0CTL

OFFSET

00h

TA0 control

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

TA0 counter register

TA0CCTL0

TA0CCTL1

TA0CCTL2

TA0R

02h

04h

06h

10h

Capture/compare register 0

Capture/compare register 1

Capture/compare register 2

TA0 expansion register 0

TA0 interrupt vector

TA0CCR0

TA0CCR1

TA0CCR2

TA0EX0

12h

14h

16h

20h

TA0IV

2Eh

Detailed Description

67

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

Table 6-45. Timer1_A3 Registers (Base Address: 0340h)

REGISTER DESCRIPTION

REGISTER

TA1CTL

OFFSET

TA1 control

00h

02h

04h

06h

10h

12h

14h

16h

20h

2Eh

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

TA1 counter register

TA1CCTL0

TA1CCTL1

TA1CCTL2

TA1R

Capture/compare register 0

Capture/compare register 1

Capture/compare register 2

TA1 expansion register 0

TA1 interrupt vector

TA1CCR0

TA1CCR1

TA1CCR2

TA1EX0

TA1IV

Table 6-46. RTC Registers (Base Address: 03C0h)

REGISTER DESCRIPTION

REGISTER

RTCCTL

RTCIV

OFFSET

00h

RTC control

RTC interrupt vector

RTC modulo

04h

RTCMOD

RTCCNT

08h

RTC counter

0Ch

Table 6-47. eUSCI_A0 Registers (Base Address: 0500h)

REGISTER DESCRIPTION

REGISTER

UCA0CTLW0

UCA0CTLW1

UCA0BR0

OFFSET

00h

eUSCI_A control word 0

eUSCI_A control word 1

eUSCI_A control rate 0

eUSCI_A control rate 1

eUSCI_A modulation control

eUSCI_A status

02h

06h

UCA0BR1

07h

UCA0MCTLW

UCA0STAT

UCA0RXBUF

UCA0TXBUF

UCA0ABCTL

lUCA0IRTCTL

IUCA0IRRCTL

UCA0IE

08h

0Ah

0Ch

0Eh

10h

eUSCI_A receive buffer

eUSCI_A transmit buffer

eUSCI_A LIN control

eUSCI_A IrDA transmit control

eUSCI_A IrDA receive control

eUSCI_A interrupt enable

eUSCI_A interrupt flags

eUSCI_A interrupt vector word

12h

13h

1Ah

1Ch

1Eh

UCA0IFG

UCA0IV

Table 6-48. eUSCI_B0 Registers (Base Address: 0540h)

REGISTER DESCRIPTION

REGISTER

UCB0CTLW0

UCB0CTLW1

UCB0BR0

OFFSET

00h

eUSCI_B control word 0

eUSCI_B control word 1

eUSCI_B bit rate 0

02h

06h

eUSCI_B bit rate 1

UCB0BR1

07h

eUSCI_B status word

UCB0STATW

UCB0TBCNT

UCB0RXBUF

UCB0TXBUF

UCB0I2COA0

08h

eUSCI_B byte counter threshold

eUSCI_B receive buffer

eUSCI_B transmit buffer

eUSCI_B I2C own address 0

0Ah

0Ch

0Eh

14h

68

Detailed Description

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

Table 6-48. eUSCI_B0 Registers (Base Address: 0540h) (continued)

REGISTER DESCRIPTION

REGISTER

UCB0I2COA1

UCB0I2COA2

UCB0I2COA3

UCB0ADDRX

UCB0ADDMASK

UCB0I2CSA

UCB0IE

OFFSET

16h

eUSCI_B I2C own address 1

eUSCI_B I2C own address 2

eUSCI_B I2C own address 3

eUSCI_B receive address

eUSCI_B address mask

18h

1Ah

1Ch

1Eh

eUSCI_B I2C slave address

eUSCI_B interrupt enable

eUSCI_B interrupt flags

20h

2Ah

UCB0IFG

2Ch

2Eh

eUSCI_B interrupt vector word

UCB0IV

Table 6-49. Backup Memory Registers (Base Address: 0660h)

REGISTER DESCRIPTION

REGISTER

BAKMEM0

BAKMEM1

BAKMEM2

BAKMEM3

BAKMEM4

BAKMEM5

BAKMEM6

BAKMEM7

BAKMEM8

BAKMEM9

BAKMEM10

BAKMEM11

BAKMEM12

BAKMEM13

BAKMEM14

BAKMEM15

OFFSET

00h

Backup Memory 0

Backup Memory 1

Backup Memory 2

Backup Memory 3

Backup Memory 4

Backup Memory 5

Backup Memory 6

Backup Memory 7

Backup Memory 8

Backup Memory 9

Backup Memory 10

Backup Memory 11

Backup Memory 12

Backup Memory 13

Backup Memory 14

Backup Memory 15

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

12h

14h

16h

18h

1Ah

1Ch

1Eh

Table 6-50. ADC Registers (Base Address: 0700h)

REGISTER DESCRIPTION

REGISTER

ADCCTL0

ADCCTL1

ADCCTL2

ADCLO

OFFSET

00h

ADC control register 0

ADC control register 1

02h

ADC control register 2

04h

ADC window comparator low threshold

ADC window comparator high threshold

ADC memory control register 0

ADC conversion memory register

ADC interrupt enable

06h

ADCHI

08h

ADCMCTL0

ADCMEM0

ADCIE

0Ah

12h

1Ah

1Ch

1Eh

ADC interrupt flags

ADCIFG

ADC interrupt vector word

ADCIV

Detailed Description

69

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

6.12 Identification

6.12.1 Revision Identification

The device revision information is shown as part of the top-side marking on the device package. The

device-specific errata sheet describes these markings. For links to the errata sheets for the devices in this

data sheet, see 节 8.4.

The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For

details on this value, see the "Hardware Revision" entries in Section 6.10.

6.12.2 Device Identification

The device type can be identified from the top-side marking on the device package. The device-specific

errata sheet describes these markings. For links to the errata sheets for the devices in this data sheet, see

节 8.4.

A device identification value is also stored in the Device Descriptor structure in the Info Block section. For

details on this value, see the "Device ID" entries in Section 6.10.

6.12.3 JTAG Identification

Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in

detail in the MSP430 Programming With the JTAG Interface.

70

Detailed Description

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

7 Applications, Implementation, and Layout

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

7.1 Device Connection and Layout Fundamentals

This section discusses the recommended guidelines when designing with the MSP430FR413x devices.

These guidelines are to make sure that the device has proper connections for powering, programming,

debugging, and optimum analog performance.

7.1.1 Power Supply Decoupling and Bulk Capacitors

TI recommends connecting a combination of a 10-µF plus a 100-nF low-ESR ceramic decoupling

capacitor to the DVCC and DVSS pins. Higher-value capacitors may be used but can impact supply rail

ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple

(within a few millimeters).

DVCC

+

Power Supply

Decoupling

DVSS

10 µF

100 nF

Figure 7-1. Power Supply Decoupling

7.1.2 External Oscillator

This device supports only a low-frequency crystal (32 kHz) on the XIN and XOUT pins. External bypass

capacitors for the crystal oscillator pins are required.

It is also possible to apply digital clock signals to the XIN input pin that meet the specifications of the

respective oscillator if the appropriate XT1BYPASS mode is selected. In this case, the associated XOUT

pin can be used for other purposes. If they are left unused, they must be terminated according to

Section 4.4.

Figure 7-2 shows a typical connection diagram.

XIN

XOUT

C_L1

C_L2

Figure 7-2. Typical Crystal Connection

See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal

oscillator with the MSP430 devices.

Applications, Implementation, and Layout

71

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

7.1.3 JTAG

With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or

MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the

connections also support the MSP-GANG production programmers, thus providing an easy way to

program prototype boards, if desired. Figure 7-3 shows the connections between the 14-pin JTAG

connector and the target device required to support in-system programming and debugging for 4-wire

JTAG communication. Figure 7-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).

The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are

identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSP-

FET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an

alternate connection (pin 4 instead of pin 2). The VCC-sense feature senses the local VCC present on the

target board (that is, a battery or other local power supply) and adjusts the output signals accordingly.

Figure 7-3 and Figure 7-4 show a jumper block that supports both scenarios of supplying VCC to the

target board. If this flexibility is not required, the desired VCC connections may be hard-wired to eliminate

the jumper block. Pins 2 and 4 must not be connected at the same time.

For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User’s

Guide.

V_CC

Important to connect

MSP430FRxxx

J1 (see Note A)

DVCC

J2 (see Note A)

R1

47 kW

JTAG

RST/NMI/SBWTDIO

VCC TOOL

TDO/TDI

TDI

TDO/TDI

TDI

2

1

VCC TARGET

4

3

TMS

6

5

7

TEST

TCK

8

TCK

GND

RST

10

12

14

9

11

13

TEST/SBWTCK

DVSS

C1

1 nF

(see Note B)

A. If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,

make connection J2.

B. The upper limit for C1 is 1.1 nF when using current TI tools.

Figure 7-3. Signal Connections for 4-Wire JTAG Communication

72

Applications, Implementation, and Layout

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

V_CC

Important to connect

MSP430FRxxx

J1 (see Note A)

J2 (see Note A)

DVCC

R1

47 kΩ

(see Note B)

JTAG

VCC TOOL

VCC TARGET

TDO/TDI

2

1

3

5

7

9

RST/NMI/SBWTDIO

4

6

TCK

8

GND

10

12

14

11

13

TEST/SBWTCK

DVSS

C1

1 nF

(see Note B)

A. Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the

debug or programming adapter.

B. The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during

JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with

the device. The upper limit for C1 is 1.1 nF when using current TI tools.

Figure 7-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)

7.1.4 Reset

The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function

Register (SFR), SFRRPCR.

In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing

specifications generates a BOR-type device reset.

Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is

edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the

external NMI. When an external NMI event occurs, the NMIIFG is set.

The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either

pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.

If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an

external 47-kΩ pullup resistor to the RST/NMI pin with a 1.1-nF pulldown capacitor. The pulldown

capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or

in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers.

See the MSP430FR4xx and MSP430FR2xx Family User's Guide for more information on the referenced

control registers and bits.

7.1.5 Unused Pins

For details on the connection of unused pins, see Section 4.4.

Applications, Implementation, and Layout

73

Submit Documentation Feedback

Product Folder Links: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

7.1.6 General Layout Recommendations

•

Proper grounding and short traces for external crystal to reduce parasitic capacitance. See MSP430

32-kHz Crystal Oscillators for recommended layout guidelines.

•

Proper bypass capacitors on DVCC and reference pins, if used.

Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital

switching signals such as PWM or JTAG signals away from the oscillator circuit.

•

Proper ESD level protection should be considered to protect the device from unintended high-voltage

electrostatic discharge. See MSP430 System-Level ESD Considerations for guidelines.

7.1.7 Do's and Don'ts

During power up, power down, and device operation, DVCC must not exceed the limits specified in

Section 5.1, Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the

device including erroneous writes to RAM and FRAM.

7.2 Peripheral- and Interface-Specific Design Information

7.2.1 ADC Peripheral

7.2.1.1 Partial Schematic

Figure 7-5 shows the recommended circuit for external reference inputs to the ADC.

DVSS

Using an external

VREF+/VEREF+

positive reference

+

100 nF

10 µF

Using an external

negative reference

VEREF-

+

10 µF

100 nF

Figure 7-5. ADC Grounding and Noise Considerations

7.2.1.2 Design Requirements

As with any high-resolution ADC, appropriate PCB layout and grounding techniques should be followed to

eliminate ground loops, unwanted parasitic effects, and noise.

Ground loops are formed when return current from the ADC flows through paths that are common with

other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset

voltages that can add to or subtract from the reference or input voltages of the ADC. The general

guidelines in Section 7.1.1 combined with the connections shown in Section 7.2.1.1 prevent this.

In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital

switching or switching power supplies can corrupt the conversion result. TI recommends a noise-free

design using separate analog and digital ground planes with a single-point connection to achieve high

accuracy.

Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used. The

internal reference module has a maximum drive current as described in the sections ADC Pin Enable and

1.2-V Reference Settings of the MSP430FR4xx and MSP430FR2xx Family User's Guide.

74

Applications, Implementation, and Layout

提交文档反馈意见

产品主页链接: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are

selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage

enters the device. In this case, the 10-µF capacitor is used to buffer the reference pin and filter any low-

frequency ripple. A bypass capacitor of 100 nF is used to filter out any high-frequency noise.

7.2.1.3 Layout Guidelines

Components that are shown in the partial schematic (see Figure 7-5) should be placed as close as

possible to the respective device pins to avoid long traces, because they add additional parasitic

capacitance, inductance, and resistance on the signal.

Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),

because the high-frequency switching can be coupled into the analog signal.

Applications, Implementation, and Layout

75

提交文档反馈意见

产品主页链接: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

8 器件和文档支持

8.1 开始使用

有关可帮助您开发的 MSP430 系列器件、工具和库的介绍，请参阅 MSP430™ 超低功耗感应和测量 MCU

概述。

8.2 器件命名规则

为了标示产品开发周期所处的阶段，TI 为所有 MSP MCU 器件的部件号分配了前缀。每个 MSP MCU 商用

系列产品成员都具有以下两个前缀之一：MSP 或 XMS。这些前缀代表了产品开发的发展阶段，即从工程原

型 (XMS) 直到完全合格的生产器件 (MSP)。

XMS - 实验器件，不一定代表最终器件的电气规格

MSP - 完全合格的生产器件

XMS 器件在供货时附带如下免责声明：

“开发中的产品用于内部评估用途。”

MSP 器件的特性已经全部明确，并且器件的质量和可靠性已经完全论证。TI 的标准保修证书对该器件适

用。

预测显示原型器件 (XMS) 的故障率大于标准生产器件。由于这些器件的预计最终使用故障率尚不确定，德

州仪器 (TI) 建议不要将它们用于任何生产系统。请仅使用合格的生产器件。

TI 器件的命名规则还包括一个带有器件系列名称的后缀。此后缀表示温度范围、封装类型和配送形式。提

供了解读完整器件名称的图例。

MSP 430 FR

2

033

I

PM

R

Distribution Format

Processor Family

Platform

Memory Type

Packaging

Temperature Range

Series

Feature Set

Processor Family

Platform

MSP = Mixed-Signal Processor

XMS = Experimental Silicon

430 = TI’s 16-Bit MSP430 Low-Power Microcontroller Platform

Memory Type

Series

FR = FRAM

2 = FRAM 2 series up to 16 MHz without LCD

Feature Set

First and Second Digits: ADC Channels / 16-bit Timers / I/Os Third Digit: FRAM (KB) / SRAM (KB)

3 = 16 / 2

2 = 8 / 1

03 = Up to 10 / 3 / Up to 60

Temperature Range

Packaging

I = –40°C to 85°C

http://www.ti.com/packaging

Distribution Format

T = Small reel

R = Large reel

No marking = Tube or tray

图 8-1. 器件命名规则

76

器件和文档支持

提交文档反馈意见

产品主页链接: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

8.3 工具和软件

表 8-1 列出了 MSP430FR203x 微控制器所调试调控功能。请参阅《适用于 MSP430™ MCU 的 Code

Composer Studio™ IDE》用户指南，以了解有关可用功能的详细信息。

表 8-1. 硬件特性

四线制

JTAG

两线制

JTAG

断点

(N)

状态序列发生

器

LPMX.5 调试

支持

MSP430 架构

范围断点

有

时钟控制

是

跟踪缓冲器

否

MSP430Xv2

有

3

否

设计套件与评估模块

MSP430FR4133 LaunchPad 开发套件

MSP-EXP430FR4133 LaunchPad 开发套件是适用于 MSP430FR4133 微控制器的简单易用的评估模块

(EVM)。它包含在基于 FRAM 的 MSP430 超低功耗 (ULP) 微控制器 (MCU) 平台上进行开发所需的全部资

源，包括用于编程、调试和能量测量的板载仿真。

适用于 MSP430FR2x/4x MCU 的 MSP-TS430PM64D 目标开发板

MSP-TS430PM64D 是一款独立的 64 引脚 ZIF 插座目标板，用于通过 JTAG 接口或 Spy Bi-Wire（2 线

JTAG）协议对 MSP430 MCU 系统内置器件进行编程和调试。

适用于 MSP430FR2x/4x MCU 的 MSP-FET430U64D 目标开发板（64 引脚）和 MSP-FET 编程器捆绑包

MSP-FET430U64D 是一款捆绑套件，包含 MSP-FET 仿真器和 MSP-TS430PM64D 64 引脚 ZIF 插座目标

板，用于通过 JTAG 接口或 Spy Bi-Wire（2 线式 JTAG）协议对 MSP430 MCU 系统内置器件进行编程和

调试。

软件

MSP430Ware™ 软件

MSP430Ware 软件集合了所有 MSP430 器件的代码示例、数据表以及其他设计资源，打包提供给用户。除

了提供已有 MSP430 MCU 设计资源的完整集合外，MSP430Ware 软件还包含名为 MSP 驱动程序库的高级

API。借助该库可以轻松地对 MSP430 硬件进行编程。MSP430Ware 软件以 CCS 组件或独立软件包两种形

式提供。

MSP430FR413x、MSP430FR203x 代码示例

根据不同应用需求配置各集成外设的每个 MSP 器件均具备相应的 C 代码示例。

适用于 MSP 超低功耗微控制器的 FRAM 嵌入式软件实用程序

TI FRAM 实用程序软件旨在用作不断扩充的嵌入式软件实用程序集合，其中的实用程序充分利用了 FRAM

的超低功耗和近乎无限次的写入寿命。这些实用程序适用于 MSP430FRxx FRAM 微控制器并提供示例代

码，以帮助开始进行应用程序开发。

器件和文档支持

77

提交文档反馈意见

产品主页链接: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

MSP430 Touch Pro GUI

MSP430 Touch Pro 工具是基于 PC 的工具，可用于检验电容式触控按钮、滑块和滚轮设计。此工具可接收

并显示 CapTouch 传感器数据，帮助用户快速轻松地评估、诊断和调整按钮、滑块和滚轮设计。

MSP430 触控电源设计器 GUI

使用 MSP430 电容式触控电源设计器，可以计算给定的 MSP430 电容式触控系统的估计平均电流消耗。通

过输入系统参数（如工作电压、频率、按钮数量和按钮选通时间），用户可以在数分钟内估计给定的器件系

列的指定电容式触控配置的功耗。

适用于 MSP 微控制器的数字信号处理 (DSP) 库

数字信号处理库是一组经高度优化的函数，可针对 MSP430 和 MSP432 微控制器对定点数执行许多常见的

信号处理运算。该函数集通常用于以要求完成实时密集处理转换，从而以最低能耗实现高精度的应用。针

对定点数学对 MSP 固有硬件的最佳利用可以极大地提高性能。

MSP 驱动程序库

MSP 驱动程序库的抽象 API 提供易用的函数调用，无需直接操纵 MSP430 硬件的位与字节。完整的文档通

过具有帮助意义的 API 指南交付，其中包括有关每个函数调用和经过验证的参数的详细信息。开发人员可使

用驱动程序库函数以尽可能低的费用编写全部项目。

MSP EnergyTrace 技术

适用于 MSP430 微控制器的 EnergyTrace 技术是基于电能的代码分析工具，适用于测量和显示应用的电能

系统配置并帮助优化应用以实现超低功耗。

ULP（超低功耗）Advisor

ULP Advisor™软件是一款辅助工具，旨在指导开发人员编写更为高效的代码，从而充分利用 MSP430 和

MSP432 微控制器独特功能。ULP Advisor 的目标人群是微控制器的资深开发者和开发新手，可以根据详

尽的 ULP 检验表检查代码，以便最大限度地减少应用程序的能耗。在编译时，ULP Advisor 会提供通知和

备注以突出显示代码中可以进一步优化的区域，进而实现更低功耗。

适用于 MSP 的定点数学库

MSP IQmath 和 Qmath 库是为 C 语言开发者提供的一套经过高度优化的高精度数学运算函数集合，能够将

浮点算法无缝嵌入 MSP430 和 MSP432 器件的定点代码中。这些例程通常用于计算密集型实时应用，而

优化的执行速度、高精度以及超低能耗通常是影响这些实时应用的关键因素。与使用浮点数学算法编写的同

等代码相比，使用 IQmath 和 Qmath 库可以大幅提高执行速度并显著降低能耗。

适用于 MSP430 的浮点数学库

TI 在低功耗和低成本微控制器领域锐意创新，为您提供 MSPMATHLIB。该标量函数的浮点数学库能够利用

我们的器件的智能外设，其速度最高可为标准 MSP430 数学函数的 26 倍。Mathlib 能够轻松集成到您的设

计中。该运算库免费使用并集成在 Code Composer Studio IDE 和 IAR Embedded Workbench IDE 中。

78

器件和文档支持

提交文档反馈意见

产品主页链接: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

开发工具

适用于 MSP 微控制器的 Code Composer Studio™ 集成开发环境

Code Composer Studio (CCS) 集成开发环境 (IDE) 支持所有 MSP 微控制器器件。CCS 包含一整套用于开

发和调试嵌入式应用的嵌入式软件实用程序。CCS 包含了优化的 C/C++ 编译器、源代码编辑器、项目构建

环境、调试器、描述器以及其他众多功能。

命令行编程器

MSP Flasher 是一款基于 shell 的开源接口，可使用 JTAG 或 Spy-Bi-Wire (SBW) 通信通过 FET 编程器或

eZ430 对 MSP 微控制器进行编程。MSP Flasher 可用于将二进制文件（.txt 或 .hex 文件）直接下载到

MSP 微控制器，而无需使用 IDE。

MSP MCU 编程器和调试器

MSP-FET 是一款强大的仿真开发工具（通常称为调试探针），可帮助用户在 MSP 低功耗微控制器 (MCU)

中快速开发应用。创建 MCU 软件通常需要将生成的二进制程序下载到 MSP 器件中，从而进行验证和调

试。

MSP-GANG 生产编程器

MSP Gang 编程器是一款 MSP430 或 MSP432 器件编程器，可同时对多达八个完全相同的 MSP430 或

MSP432 闪存或 FRAM 器件进行编程。MSP Gang 编程器可使用标准的 RS-232 或 USB 连接与主机 PC

相连并提供灵活的编程选项，允许用户完全自定义流程。

8.4 文档支持

以下文档描述了 MSP430FR203x 微控制器。www.ti.com.cn 网站上提供了这些文档的副本。

接收文档更新通知

要接收文档更新通知（包括芯片勘误表），请转至 ti.com.cn 上您的器件对应的产品文件夹（关于产品文件

夹的链接，请参见节 8.5）。请单击右上角的“通知我”按钮。点击注册后，即可收到产品信息更改每周摘要

（如有）。有关更改的详细信息，请查阅已修订文档的修订历史记录。

勘误

《MSP430FR2033 器件勘误表》

介绍了这款器件所有芯片修订版本的功能规格的已知例外情况。

《MSP430FR2032 器件勘误表》

介绍了这款器件所有芯片修订版本的功能规格的已知例外情况。

用户指南

《MSP430FR4xx 和 MSP430FR2xx 系列用户指南》

可说明。

《MSP430 FRAM 器件引导加载程序 (BSL) 用户指南》

MSP430 MCU 上的引导加载程序 (BSL) 允许用户在原型设计、投产和维护等各阶段与 MSP430 MCU 中的

嵌入式存储器进行通信。可编程存储器（FRAM 存储器）和数据存储器 (RAM) 均可按要求予以修改。

器件和文档支持

79

提交文档反馈意见

产品主页链接: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

《通过 JTAG 接口对 MSP430 进行编程》

此文档介绍了使用 JTAG 通信端口擦除、编程和验证基于 MSP430 闪存和 FRAM 的微控制器系列的存储器

模块所需的功能。此外，该文档还介绍了如何编程所有 MSP430 器件上均具备的 JTAG 访问安全保险丝。

此文档介绍了使用标准四线制 JTAG 接口和两线制 JTAG 接口（也称为 Spy-Bi-Wire (SBW)）的器件访问。

《MSP430 硬件工具用户指南》

此手册介绍了 TI MSP-FET430 闪存仿真工具 (FET) 的硬件。FET 是针对 MSP430 超低功耗微控制器的程

序开发工具。文中对提供的接口类型，即并行端口接口和 USB 接口进行了说明。

应用报告

MSP430 FRAM 技术 – 操作方法和最佳实践

FRAM 采用非易失性存储器技术，行为与 SRAM 类似，支持大量新应用，还改变了固件的设计方式。该应

用程序报告从嵌入式软件开发方面概述了 FRAM 技术在 MSP430 中的使用方法和最佳实践。其中介绍了如

何按照应用程序特定的代码、常量、数据空间要求实施存储器布局以及如何使用 FRAM 优化应用程序的能

耗。

《MSP430 32kHz 晶体振荡器》

选择合适的晶体、正确的负载电路和适当的电路板布局是实现稳定的晶体振荡器的关键。该应用报告总结了

晶体振荡器的功能，介绍了用于选择合适的晶体以实现 MSP430 超低功耗运行的参数。此外，还给出了正

确电路板布局的提示和示例。此外，为了确保振荡器在大规模生产后能够稳定运行，还可能需要进行一些振

荡器测试，该文档中提供了有关这些测试的详细信息。

《MSP430 系统级 ESD 注意事项》

随着芯片技术向更低电压方向发展以及设计具有成本效益的超低功耗组件的需求的出现，系统级 ESD 要求

变得越来越苛刻。该应用报告介绍了三个不同的 ESD 主题，旨在帮助电路板设计人员和 OEM 理解并设计

出稳健耐用的系统级设计。

8.5 相关链接

表 8-2 列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品

的快速链接。

表 8-2. 相关链接

器件

产品文件夹

请单击此处

立即订购

请单击此处

技术文档

请单击此处

工具和软件

请单击此处

支持和社区

请单击此处

MSP430FR2033

MSP430FR2032

80

器件和文档支持

提交文档反馈意见

产品主页链接: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

www.ti.com.cn

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

8.6 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术

规范，并且不一定反映 TI 的观点；请参见 TI 的《使用条款》。

TI E2E™ 社区

TI 的工程师交流 (E2E) 社区. 此社区的创建目的是为了促进工程师之间协作。在 e2e.ti.com 中，您可以提

问、共享知识、拓展思路，在同领域工程师的帮助下解决问题。

TI 嵌入式处理器维基网页

德州仪器 (TI) 嵌入式处理器维基网页。此网站的建立是为了帮助开发人员熟悉德州仪器 (TI) 的嵌入式处理

器，并且也为了促进与这些器件相关的硬件和软件的总体知识的创新和增长。

8.7 商标

MSP430, MSP430Ware, ULP Advisor, 适用于 MSP 微控制器的 Code Composer Studio, E2E are

trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

8.8 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

8.9 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

提交文档反馈意见

器件和文档支持

81

产品主页链接: MSP430FR2033 MSP430FR2032

MSP430FR2033, MSP430FR2032

ZHCSDF2E –OCTOBER 2014–REVISED DECEMBER 2019

www.ti.com.cn

9 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通

知，且不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

82

机械、封装和可订购信息

提交文档反馈意见

产品主页链接: MSP430FR2033 MSP430FR2032

PACKAGE OUTLINE

PM0064A

LQFP - 1.6 mm max height

SCALE 1.400

PLASTIC QUAD FLATPACK

10.2

9.8

B

NOTE 3

64

49

PIN 1 ID

1

48

10.2

9.8

12.2

TYP

11.8

NOTE 3

33

16

32

17

A

0.27

0.17

64X

60X 0.5

4X 7.5

0.08

C A B

C

(0.13) TYP

SEATING PLANE

0.08

SEE DETAIL A

0.25

GAGE PLANE

(1.4)

1.6 MAX

0.05 MIN

0.75

0.45

0 -7

DETAIL

SCALE: 14

A

DETAIL A

TYPICAL

4215162/A 03/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MS-026.

www.ti.com

EXAMPLE BOARD LAYOUT

PM0064A

LQFP - 1.6 mm max height

PLASTIC QUAD FLATPACK

SYMM

49

64

64X (1.5)

1

48

64X (0.3)

SYMM

(11.4)

60X (0.5)

(R0.05) TYP

33

16

17

32

(11.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

0.05 MAX

ALL AROUND

EXPOSED METAL

METAL

0.05 MIN

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4215162/A 03/2017

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

7. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).

www.ti.com

EXAMPLE STENCIL DESIGN

PM0064A

LQFP - 1.6 mm max height

PLASTIC QUAD FLATPACK

SYMM

64

49

64X (1.5)

1

48

64X (0.3)

SYMM

(11.4)

60X (0.5)

(R0.05) TYP

16

33

17

32

(11.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:8X

4215162/A 03/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DGG0056A

TSSOP - 1.2 mm max height

S

C

A

L

E

1

.

2

0

SMALL OUTLINE PACKAGE

C

8.3

7.9

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

A

54X 0.5

56

1

14.1

13.9

NOTE 3

2X

13.5

28

B

29

0.27

0.17

6.2

6.0

56X

1.2 MAX

0.08

C A

B

(0.15) TYP

0.25

GAGE PLANE

0 - 8

SEE DETAIL A

0.15

0.05

0.75

0.50

DETAIL A

TYPICAL

4222167/A 07/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

www.ti.com

EXAMPLE BOARD LAYOUT

DGG0056A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

56X (1.5)

SYMM

1

56

56X (0.3)

54X (0.5)

(R0.05)

TYP

SYMM

28

29

(7.5)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

METAL

SOLDER MASK

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4222167/A 07/2015

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DGG0056A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

56X (1.5)

SYMM

1

56

56X (0.3)

54X (0.5)

(R0.05) TYP

SYMM

28

29

(7.5)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:6X

4222167/A 07/2015

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DGG0048A

TSSOP - 1.2 mm max height

S

C

A

L

E

1

.

3

5

0

SMALL OUTLINE PACKAGE

C

8.3

7.9

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

A

46X 0.5

48

1

12.6

12.4

NOTE 3

2X

11.5

24

B

25

0.27

0.17

48X

6.2

6.0

1.2

1.0

0.08

C A B

(0.15) TYP

0.25

GAGE PLANE

0 - 8

SEE DETAIL A

0.15

0.75

0.05

0.50

DETAIL A

TYPICAL

4214859/B 11/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

www.ti.com

EXAMPLE BOARD LAYOUT

DGG0048A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

48X (1.5)

SYMM

1

48

48X (0.3)

46X (0.5)

(R0.05)

TYP

SYMM

24

25

(7.5)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

METAL

SOLDER MASK

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214859/B 11/2020

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DGG0048A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

48X (1.5)

SYMM

1

48

48X (0.3)

46X (0.5)

SYMM

(R0.05) TYP

24

25

(7.5)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:6X

4214859/B 11/2020

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

MECHANICAL DATA

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998

DGG (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,27

0,17

M

0,08

0,50

48

25

6,20

6,00

8,30

7,90

0,15 NOM

Gage Plane

0,25

1

24

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

48

56

64

DIM

A MAX

12,60

12,40

14,10

13,90

17,10

16,90

A MIN

4040078/F 12/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	MSP430FR2032
厂家：	TEXAS INSTRUMENTS
描述：	具有 8KB FRAM、1KB SRAM、10 位 ADC、UART/SPI/I2C、红外逻辑和计时器的 16MHz MCU 静态存储器
文件：	总99页 (文件大小：1903K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MSP430FR2032 [TI]

相关型号：

MSP430FR2032IG48

MSP430FR2032IG48R

MSP430FR2032IG56

MSP430FR2032IG56R

MSP430FR2032IPMR

MSP430FR2033

MSP430FR2033IG48

MSP430FR2033IG48R

MSP430FR2033IG56

MSP430FR2033IG56R

MSP430FR2033IPM

MSP430FR2033IPMR