MSP430FR2353TPT [TI]
具有 16KB FRAM、运算放大器/PGA、12 位 DAC 和 12 位 ADC 的 24MHz 105°C 集成模拟微控制器 | PT | 48 | -40 to 105;型号: | MSP430FR2353TPT |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 16KB FRAM、运算放大器/PGA、12 位 DAC 和 12 位 ADC 的 24MHz 105°C 集成模拟微控制器 | PT | 48 | -40 to 105 放大器 控制器 微控制器 运算放大器 |
文件: | 总145页 (文件大小:3423K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
MSP430FR235x、MSP430FR215x 混合信号微控制器
1 器件概述
1.1 特性
1
– 多个输入信号选项
• 嵌入式微控制器
– 可配置的高功率和低功率模式
– 可配置 PGA 模式支持
– 16 位 RISC 架构,频率最高可达 24MHz
– 扩展温度范围:–40°C 至 105°C
–
同相模式:×1、×2、×3、×5、×9、×17、
×26、×33
反相模式:×1、×2、×4、×8、×16、×
25、×32
– 3.6V 至 1.8V 的宽电源电压范围(工作电压受限
于 SVS 电平,参阅 VSVSH- 和 VSVSH+,见
PMM、SVS 和 BOR)
–
• 经优化的低功耗模式(3V)
– 工作模式:142µA/MHz
– 待机:
– 用于进行失调电压和偏置设置的内置 12 位基
准 DAC
– 具有可选基准电压的 12 位电压 DAC 模式
– 具有 32768Hz 晶体的 LPM3:1.43µA(SVS
处于启用状态)
• 智能数字外设
– 三个 16 位计时器,每个计时器有 3 个捕捉/比较
寄存器 (Timer_B3)
– 具有 32768Hz 晶体的 LPM3.5:620nA(SVS
处于启用状态)
– 一个 16 位计时器,每个计时器有 7 个捕捉/比较
寄存器 (Timer_B7)
– 一个仅用作计数器的 16 位实时钟计数器 (RTC)
– 16 位循环冗余校验器 (CRC)
– 中断比较控制器 (ICC),可启用嵌套硬件中断
– 32 位硬件乘法器 (MPY32)
– 曼彻斯特编解码器 (MFM)
– 关断 (LPM4.5):42nA(SVS 处于启用状态)
• 低功耗铁电 RAM (FRAM)
– 容量高达 32KB 的非易失性存储器
– 内置错误修正码 (ECC)
– 可配置的写保护
– 对程序、常量和存储的统一存储
– 耐写次数达 1015
– 抗辐射和非磁性
• 易于使用
次
• 增强型串行通信
– 两个增强型 USCI_A (eUSCI_A) 模块支持
UART、IrDA 和 SPI
– 20KB ROM 库包含驱动程序库和 FFT 库
• 高性能模拟
– 两个增强型 USCI_B (eUSCI_B) 模块支持 SPI 和
I2C
– 一个 12 通道 12 位模数转换器 (ADC)
– 内部共享基准(1.5、2.0 或 2.5V)
– 采样与保持 200ksps
– 两个增强型比较器 (eCOMP)
– 集成 6 位数模转换器 (DAC) 作为基准电压
– 可编程迟滞
• 时钟系统 (CS)
– 片上 32kHz RC 振荡器 (REFO)
– 带有锁频环 (FLL) 的片上 24MHz 数控振荡器
(DCO)
– 室温下的精度为 ±1%(具有片上基准)
– 片上超低频 10kHz 振荡器 (VLO)
– 片上高频调制振荡器 (MODOSC)
– 外部 32kHz 晶振 (LFXT)
– 可配置的高功率和低功率模式
– 一个具有 100ns 的快速响应时间
– 一个具有 1µs 的响应时间以及 1.5µA 的低功
耗
– 外部高频晶体振荡器,频率最高可达 24MHz
(HFXT)
– 四个智能模拟组合 (SAC-L3)(仅限
MSP430FR235x 器件)
– 可编程 MCLK 预分频器(1 至 128)
– 源自具有可编程预分频器(1、2、4 或 8)的
MCLK 的 SMCLK
– 支持通用运算放大器 (OA)
– 轨至轨输入和输出
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLASEC4
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
• 通用输入/输出和引脚功能
– 48 引脚封装上的 44 个 I/O
• 系列成员(另请参阅 器件比较)
– MSP430FR2355:32KB 的程序 FRAM、512B
的数据 FRAM、4KB 的 RAM
– MSP430FR2353:16KB 的程序 FRAM、512B
的数据 FRAM、2KB 的 RAM
– MSP430FR2155:32KB 的程序 FRAM、512B
的数据 FRAM、4KB 的 RAM
– MSP430FR2153:16KB 的程序 FRAM、512B
的数据 FRAM、2KB 的 RAM
– 32 个中断引脚(P1、P2、P3 和 P4)可以将
MCU 从 LPM 唤醒
• 开发工具和软件(另外请参阅 工具和软件)
– LaunchPad™开发套件 (MSP‑EXP430FR2355)
– 目标开发板 (MSP‑TS43048PT)
– 免费的专业开发环境
• 封装选项
– 48 引脚:LQFP (PT)
– 40 引脚:VQFN (RHA)
– 38 引脚:TSSOP (DBT)
– 32 引脚:VQFN (RSM)
1.2 应用
•
•
•
•
烟雾和热量探测器
传感器变送器
断路器
•
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•
•
有线工业通信
光学模块
电池组管理
收费标签
传感器信号调节
1.3 说明
MSP430FR215x 和 MSP430FR235x 微控制器 (MCU) 均属于 MSP430™MCU 超值系列超低功耗低成本器
件产品系列,该产品系列适用于检测和测量 应用。MSP430FR235x MCU 集成了四个称之为智能模拟组合
的可配置信号链模块,每个组合均可用作 12 位 DAC 或可配置可编程增益运算放大器,以满足系统的特定
需求,同时缩减 BOM 并减小 PCB 尺寸。该器件还包含一个 12 位 SAR ADC 和两个比较器。
MSP430FR215x 和 MSP430FR235x MCU 都支持 –40° 至 105°C 的扩展温度范围,因此更高温度的工业
应用 可从这些器件的 FRAM 数据记录功能受益。该扩展温度范围使开发人员可以满足烟雾探测器、传感器
变送器和断路器等 应用 的要求。
MSP430FR215x 和 MSP430FR235x MCU 具有功能强大的 16 位 RISC CPU、16 位寄存器和常数发生器,
有助于实现最大编码效率。数控振荡器 (DCO) 通常可以使器件在不到 10µs 的时间内从低功耗模式唤醒至激
活模式。
MSP430 超低功耗 (ULP) FRAM 微控制器平台将独特的嵌入式 FRAM 和整体超低功耗系统架构相结合,从
而使系统设计人员能够在降低能耗的情况下提升性能。FRAM 技术将 RAM 的低功耗快速写入、灵活性和耐
用性与闪存的非易失性相结合。
MSP430FR215x 和 MSP430FR235x MCU 由广泛的硬件和软件生态系统提供支持,随附参考设计和代码示
例,便于您快速开始设计。开发套件包括 MSP-EXP430FR2355 LaunchPad™开发套件和 MSP-
TS430PT48 48 引脚目标开发板。TI 还提供免费的 MSP430Ware™ 软件,该软件以 Code Composer
Studio™ IDE 台式机和云版本组件的形式提供(位于 TI Resource Explorer)。 E2E™ 支持论坛还为
MSP430 MCU 提供广泛的在线配套资料、培训和在线支持。
有关完整的模块说明,请参阅《MSP430FR4xx 和 MSP430FR2xx 系列器件用户指南》。
2
器件概述
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
器件信息(1)
器件型号
工作温度
封装
封装尺寸(2)
MSP430FR2355TPT
MSP430FR2353TPT
MSP430FR2155TPT
MSP430FR2153TPT
MSP430FR2355TRHA
MSP430FR2353TRHA
MSP430FR2155TRHA
MSP430FR2153TRHA
MSP430FR2355TDBT
MSP430FR2353TDBT
MSP430FR2155TDBT
MSP430FR2153TDBT
MSP430FR2355TRSM
MSP430FR2353TRSM
MSP430FR2155TRSM
MSP430FR2153TRSM
-40°C 至 105°C
LQFP (48)
7mm × 7mm
-40°C 至 105°C
-40°C 至 105°C
-40°C 至 105°C
VQFN (40)
TSSOP (38)
VQFN (32)
6mm × 6mm
9.7mm × 4.4mm
4mm × 4mm
(1) 要获得最新的产品、封装和订购信息,请参见封装选项附录(节 9),或者访问德州仪器 (TI) 网站
www.ti.com.cn。
(2) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸,请参见机械数据(节 9中)。
CAUTION
系统级静电放电 (ESD) 保护必须符合器件级 ESD 规范,以防发生电气过载或对
数据或代码存储器造成干扰。有关更多信息,请参阅《MSP430™ 系统级 ESD
注意事项》。
版权 © 2018–2019, Texas Instruments Incorporated
器件概述
3
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
1.4 功能方框图
图 1-1 显示了 MSP430FR235x 功能方框图。
XIN XOUT
P1.x, P2.x
P3.x, P4.x
P5.x, P6.x
HF, LF XT1
SAC0, SAC1,
SAC2, SAC3
eCOMP0
eCOMP1
I/O Ports
P1, P2
2×8 IOs
Interrupt
and Wakeup
PA
I/O Ports
P3, P4
2×8 IOs
Interrupt
and Wakeup
PB
ADC
I/O Ports
P5, P6
1×5 IOs
1×7 IOs
PC
FRAM
RAM
DVCC
DVSS
ROM
20KB
Up to 12-ch
Single-end
12 bit
Configurable
OA, PGA,
12-bit DAC
Combo
Enhanced
Comparator
with 6-bit
DAC
24-MHz
Clock
System
Power
Management
Module
32KB + 512B
16KB + 512B
4KB
2KB
200 ksps
1×12 IOs
1×16 IOs
1×16 IOs
RST/NMI
MAB
MDB
24-MHz CPU
including
16 registers
EEM
RTC
Counter
BAKMEM
SYS
Infrared
MFM
TB0
TB1
TB2
Timer_B
MPY32
CRC16
ICC
TB3
Timer_B
eUSCI_A0
eUSCI_A1
TCK
TMS
eUSCI_B0
eUSCI_B1
32 Bytes
Backup
Memory
16-bit
Real-Time
Clock
16-bit
Cyclic
Redundancy
Check
JTAG
SBW
32-bit
Hardware
Multiplier
Interrupt
Compare
Controller
TDI/TCLK
TDO
7 CC
Registers
(UART,
IrDA, SPI)
(SPI, I2C)
3 CC
Registers
SBWTCK
SBWTDIO
Watchdog
LPM3.5 Domain
图 1-1. MSP430FR235x 功能方框图
图 1-2 显示了 MSP430FR215x 功能方框图。
XIN XOUT
P1.x, P2.x
P3.x, P4.x
P5.x, P6.x
HF, LF XT1
eCOMP0
eCOMP1
I/O Ports
P1, P2
2×8 IOs
Interrupt
and Wakeup
PA
I/O Ports
P3, P4
2×8 IOs
Interrupt
and Wakeup
PB
ADC
I/O Ports
P5, P6
1×5 IOs
1×7 IOs
PC
FRAM
ROM
RAM
DVCC
DVSS
Up to 12-ch
Single-end
12 bit
Enhanced
Comparator
with 6-bit
DAC
24-MHz
Clock
System
Power
Management
Module
32KB + 512B
16KB + 512B
4KB
2KB
20KB
200 ksps
1×12 IOs
1×16 IOs
1×16 IOs
RST/NMI
MAB
MDB
24-MHz CPU
including
16 registers
EEM
RTC
Counter
BAKMEM
SYS
Infrared
MFM
TB0
TB1
TB2
Timer_B
MPY32
CRC16
ICC
TB3
Timer_B
eUSCI_A0
eUSCI_A1
TCK
TMS
eUSCI_B0
eUSCI_B1
32 Bytes
Backup
Memory
16-bit
Real-Time
Clock
16-bit
Cyclic
Redundancy
Check
JTAG
SBW
32-bit
Hardware
Multiplier
Interrupt
Compare
Controller
TDI/TCLK
TDO
7 CC
Registers
(UART,
IrDA, SPI)
(SPI, I2C)
3 CC
Registers
SBWTCK
SBWTDIO
Watchdog
LPM3.5 Domain
图 1-2. MSP430FR215x 功能方框图
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MCU 具有一个 DVCC 和 DVSS 引脚主电源对,用于为数字模块和模拟模块供电。推荐的旁路电容和去
耦电容分别为 4.7µF 至 10µF 和 0.1µF,精度为 ±5%。
P1、P2、P3 和 P4 具有引脚中断功能,可以将 MCU 从所有 LPM(包括 LPM4、LPM3.5 和 LPM4.5)
唤醒。
每个 Timer_B3 具有三个捕捉/比较寄存器。仅 CCR1 和 CCR2 从外部连接。Timer_B7 有 7 个捕捉/比
较寄存器。仅 CCR1 至 CCR6 从外部连接。CCR0 寄存器仅用于内部周期时序和中断生成。
在 LPM3.5 模式下,RTC 计数器与备用存储器可继续工作,而其余外设停止工作。
4
器件概述
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
内容
1
器件概述.................................................... 1
1.1 特性 ................................................... 1
5.12 Timing and Switching Characteristics ............... 33
Detailed Description ................................... 61
6.1 CPU ................................................. 61
6.2 Operating Modes.................................... 61
6.3 Interrupt Vector Addresses.......................... 63
6.4 Memory Organization ............................... 65
6.5 Bootloader (BSL).................................... 65
6.6 JTAG Standard Interface............................ 66
6.7 Spy-Bi-Wire Interface (SBW)........................ 66
6.8 FRAM................................................ 66
6.9 Memory Protection .................................. 67
6.10 Peripherals .......................................... 67
6.11 Input/Output Diagrams .............................. 95
6.12 Device Descriptors (TLV) .......................... 107
6.13 Identification........................................ 109
Applications, Implementation, and Layout ...... 110
6
1.2 应用 ................................................... 2
1.3 说明 ................................................... 2
1.4 功能方框图............................................ 4
修订历史记录............................................... 6
Device Comparison ..................................... 8
3.1 Related Products ..................................... 9
Terminal Configuration and Functions ............ 10
4.1 Pin Diagrams........................................ 10
4.2 Pin Attributes ........................................ 18
4.3 Signal Descriptions.................................. 22
4.4 Pin Multiplexing ..................................... 26
4.5 Buffer Type.......................................... 26
4.6 Connection of Unused Pins ......................... 26
Specifications ........................................... 27
5.1 Absolute Maximum Ratings ........................ 27
5.2 ESD Ratings ........................................ 27
5.3 Recommended Operating Conditions............... 27
2
3
4
5
7
8
7.1
Device Connection and Layout Fundamentals .... 110
7.2
Peripheral- and Interface-Specific Design
Information ......................................... 113
7.3 ROM Libraries ..................................... 114
7.4 Typical Applications................................ 114
器件和文档支持......................................... 115
8.1 使用入门 ........................................... 115
8.2 器件命名规则....................................... 115
8.3 工具和软件 ......................................... 116
8.4 文档支持 ........................................... 118
8.5 相关链接 ........................................... 118
8.6 商标 ................................................ 120
8.7 静电放电警告....................................... 120
8.8 Glossary............................................ 120
机械、封装和可订购信息 .............................. 121
5.4
Active Mode Supply Current Into VCC Excluding
External Current..................................... 28
5.5 Active Mode Supply Current Per MHz .............. 28
5.6
5.7
5.8
5.9
Low-Power Mode LPM0 Supply Currents Into VCC
Excluding External Current.......................... 28
Low-Power Mode LPM3 and LPM4 Supply Currents
(Into VCC) Excluding External Current .............. 29
Low-Power Mode LPMx.5 Supply Currents (Into
VCC) Excluding External Current.................... 30
Production Distribution of LPM Supply Currents.... 31
5.10 Typical Characteristics - Current Consumption Per
Module .............................................. 32
5.11 Thermal Resistance Characteristics ................ 32
9
版权 © 2018–2019, Texas Instruments Incorporated
内容
5
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
2 修订历史记录
从修订版本 C 更改为修订版本 D
Changes from March 6, 2019 to December 10, 2019
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修正了 图 1-1 中的 ROM 规格MSP430FR235x 功能方框图 和 图 1-2 MSP430FR215x 功能方框图...................... 4
Added a note on all VQFN pinouts to indicate that the thermal pad should be connected to VSS ...................... 11
Corrected 图 4-4, 32-Pin RSM (VQFN) (Top View) – MSP430FR235x...................................................... 13
Changed the note that begins "Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset..." in
Section 5.3, Recommended Operating Conditions ............................................................................. 27
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Added the note that begins "TI recommends that power to the DVCC pin must not exceed the limits..." in
Section 5.3, Recommended Operating Conditions ............................................................................. 27
Changed the note that begins "A capacitor tolerance of ±20% or better is required..." in Section 5.3,
Recommended Operating Conditions ............................................................................................ 27
Combined former sections 5.8 and 5.10 into 节 5.9, Production Distribution of LPM Supply Currents ................. 31
Corrected the "SVS disabled" condition for 图 5-1 ............................................................................. 31
Added the note "See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing" to 表
5-3, XT1 Crystal Oscillator (Low Frequency) ................................................................................... 35
Changed the note that begins "Requires external capacitors at both terminals..." in 表 5-3, XT1 Crystal Oscillator
(Low Frequency) .................................................................................................................... 35
Added the tTB,cap parameter in 表 5-13, Timer_B................................................................................ 45
Corrected the test conditions for the RI parameter in 表 5-20, ADC, Power Supply and Input Range Conditions..... 51
Removed ADCDIV from the equation for the ADC conversion time because ADCCLK is after division in 表 5-21,
ADC, Timing Parameters........................................................................................................... 51
Added the note that begins "tSample = ln(2n+1) × τ ..." in 表 5-21, ADC, Timing Parameters ............................... 51
Changed the unit from "nV" to "µV" for the "Input noise voltage" in the 表 5-25, SAC, OA .............................. 55
Changed the unit from "nv/Hz" to "nV/√Hz" for the "Input noise voltage density" in the 表 5-25, SAC, OA ............ 55
Removed the Iref trim parameter from 表 5-27, FRAM ......................................................................... 57
Changed the bitfield name from RTCCLK to RTCCKSEL in the table note on 表 6-9, Clock Distribution ............. 68
Added 节 6.10.17, Cross-Chip Interconnection (SACx are MSP430FR235x Devices Only).............................. 83
Added P1SELC information in 表 6-41, Port P1, P2 Registers (Base Address: 0200h) .................................. 86
Added P2SELC information in 表 6-41, Port P1, P2 Registers (Base Address: 0200h) .................................. 86
Added P3SELC information in 表 6-42, Port P3, P4 Registers (Base Address: 0220h) .................................. 87
Added P4SELC information in 表 6-42, Port P3, P4 Registers (Base Address: 0220h) .................................. 87
Added P5SELC information in 表 6-43, Port P5, P6 Registers (Base Address: 0240h) .................................. 87
Added P6SELC information in 表 6-43, Port P5, P6 Registers (Base Address: 0240h) .................................. 87
Changed CRC covered end address to 0x1AF7 in table note (1) in 表 6-70, Device Descriptors ..................... 107
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从修订版本 B 更改为修订版本 C
Changes from July 3, 2018 to March 5, 2019
Page
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•
增加了 32 引脚 VQFN (RSM) 封装信息,见 节 1.1, 特性 ....................................................................... 2
在器件信息表中增加了 32 引脚 VQFN (RSM) 封装信息,见 节 1.3(说明部分) ........................................... 3
Added 32-pin VQFN (RSM) package information in 表 3-1, Device Comparison ........................................... 8
Added 图 4-4, 32-Pin RSM (VQFN) (Top View) – MSP430FR235x.......................................................... 13
Added 图 4-8, 32-Pin RSM (VQFN) (Top View) – MSP430FR215x.......................................................... 17
Added 32-pin VQFN (RSM) package information in 节 4.2, Pin Attributes .................................................. 18
Added 32-pin VQFN (RSM) package information in 节 4.3, Signal Descriptions........................................... 22
Added 32-pin VQFN (RSM) package information in Section 5.11, Thermal Resistance Characteristics ............... 32
Added the tTB,cap parameter in 表 5-13, Timer_B................................................................................ 45
Removed the Iref trim parameter from 表 5-27, FRAM ......................................................................... 57
6
修订历史记录
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
从修订版本 A 更改为修订版本 B
Changes from June 20, 2018 to July 2, 2018
Page
•
•
•
•
Added the tTB,cap parameter in 表 5-13, Timer_B................................................................................ 45
Removed the Iref trim parameter from 表 5-27, FRAM ......................................................................... 57
更新了节 8.3工具和软件 .......................................................................................................... 116
在节 8.4文档支持 中添加了勘误表............................................................................................... 118
从初始发行版更改为修订版本 A
Changes from May 11, 2018 to June 19, 2018
Page
•
•
•
•
•
•
•
将文档状态更改为“生产数据” ........................................................................................................ 1
Added missing UCB0SCL signal to P1.3/UCB0SOMI/UCB0SCL/OA0+/A3 in pinout figures............................. 11
Added the tTB,cap parameter in 表 5-13, Timer_B................................................................................ 45
Removed the Iref trim parameter from 表 5-27, FRAM ......................................................................... 57
Added row for "Driver library and FFT library" in 表 6-4, Memory Organization ........................................... 65
Added 节 7.3, ROM Libraries .................................................................................................... 114
Corrected the title and link to reference design in 表 7-1, Tools and Reference Designs ............................... 114
版权 © 2018–2019, Texas Instruments Incorporated
修订历史记录
7
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
3 Device Comparison
表 3-1 summarizes the features of the available family members.
表 3-1. Device Comparison(1) (2)
12-BIT ADC
CHANNELS
DEVICE
PROGRAM FRAM SRAM (bytes)
TB0, TB1, TB2
TB3
eUSCI_A eUSCI_B
SAC
eCOMP
I/Os
PACKAGE
MSP430FR2355PT
MSP430FR2353PT
MSP430FR2355RHA
MSP430FR2353RHA
MSP430FR2355DBT
MSP430FR2353DBT
MSP430FR2355RSM
MSP430FR2353RSM
MSP430FR2155PT
MSP430FR2153PT
MSP430FR2155RHA
MSP430FR2153RHA
MSP430FR2155DBT
MSP430FR2153DBT
MSP430FR2155RSM
MSP430FR2153RSM
32KB + 512B
16KB + 512B
32KB + 512B
16KB + 512B
32KB + 512B
16KB + 512B
32KB + 512B
16KB + 512B
32KB + 512B
16KB + 512B
32KB + 512B
16KB + 512B
32KB + 512B
16KB + 512B
32KB + 512B
16KB + 512B
4096
2048
4096
2048
4096
2048
4096
2048
4096
2048
4096
2048
4096
2048
4096
2048
3 × CCR(3)
3 × CCR(3)
3 × CCR(3)
3 × CCR(3)
3 × CCR(3)
3 × CCR(3)
3 × CCR(3)
3 × CCR(3)
3 × CCR(3)
3 × CCR(3)
3 × CCR(3)
3 × CCR(3)
3 × CCR(3)
3 × CCR(3)
3 × CCR(3)
3 × CCR(3)
7 × CCR(3)
7 × CCR(3)
7 × CCR(3)
7 × CCR(3)
7 × CCR(3)
7 × CCR(3)
7 × CCR(3)
7 × CCR(3)
7 × CCR(3)
7 × CCR(3)
7 × CCR(3)
7 × CCR(3)
7 × CCR(3)
7 × CCR(3)
7 × CCR(3)
7 × CCR(3)
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
12
12
10
10
10
10
8
4
4
4
4
4
4
4
4
–
–
–
–
–
–
–
–
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
44
44
36
36
34
34
28
28
44
44
36
36
34
34
28
28
48 PT (LQFP)
48 PT (LQFP)
2
40 RHA (VQFN)
40 RHA (VQFN)
38 DBT (TSSOP)
38 DBT (TSSOP)
32 RSM (VQFN)
32 RSM (VQFN)
48 PT (LQFP)
2
2
2
2(4)
2(4)
2
8
12
12
10
10
10
10
8
2
48 PT (LQFP)
2
40 RHA (VQFN)
40 RHA (VQFN)
38 DBT (TSSOP)
38 DBT (TSSOP)
32 RSM (VQFN)
32 RSM (VQFN)
2
2
2
2(4)
2(4)
8
(1) For the most current device, package, and ordering information, see the Package Option Addendum in 节 9, or see the TI web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging.
(3) A CCR register is a configurable register that provides internal and external capture or compare inputs, or internal and external PWM outputs. Not all CCR channels are package specific.
See the definition in 节 4.3.
(4) eUSCI_B1 supports only I2C function.
8
Device Comparison
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
3.1 Related Products
For information about other devices in this family of products or related products, see the following links.
TI 16-bit and 32-bit microcontrollers
High-performance, low-power solutions to enable the autonomous future
Products for MSP430 ultra-low-power sensing & measurement microcontrollers
One platform. One ecosystem. Endless possibilities.
Companion products for MSP430FR2355
Review products that are frequently purchased or used with this product.
Reference designs for MSP430FR2355
Find reference designs leveraging the best in TI technology to solve your system-level challenges.
版权 © 2018–2019, Texas Instruments Incorporated
Device Comparison
9
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
4 Terminal Configuration and Functions
4.1 Pin Diagrams
图 4-1 shows the pinout of the 48-pin PT package for the MSP430FR235x MCUs.
P1.2/UCB0SIMO/UCB0SDA/TB0TRG/OA0-/A2/Veref-
P1.1/UCB0CLK/ACLK/OA0O/COMP0.1/A1
P1.0/UCB0STE/SMCLK/COMP0.0/A0/Veref+
TEST/SBWTCK
1
36
35
34
33
32
31
30
29
28
27
26
25
P3.6/OA3-
2
P3.7/OA3+
3
P1.4/UCA0STE/TCK/A4
P1.5/UCA0CLK/TMS/OA1O/A5
4
RST/NMI/SBWTDIO
5
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/OA1-/A6
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/OA1+/A7/VREF+
P2.0/TB1.1/COMP0.O
DVCC
6
MSP430FR2355TPT
MSP430FR2353TPT
DVSS
7
P2.7/TB0CLK/XIN
8
P2.1/TB1.2/COMP1.O
P2.6/MCLK/XOUT
9
P2.2/TB1CLK
P2.5/COMP1.0
10
11
12
P2.3/TB1TRG
P2.4/COMP1.1
P4.0/UCA1STE/ISOTXD/ISORXD
P4.1/UCA1CLK
P4.7/UCB1SOMI/UCB1SCL
图 4-1. 48-Pin PT (LQFP) (Top View) – MSP430FR235x
10
Terminal Configuration and Functions
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MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
图 4-2 shows the pinout of the 40-pin RHA package for the MSP430FR235x MCUs.
1
2
P1.1/UCB0CLK/ACLK/OA0O/COMP0.1/A1
P1.0/UCB0STE/SMCLK/COMP0.0/A0/Veref+
TEST/SBWTCK
30
29
28
27
26
25
24
23
22
21
P3.6/OA3-
P3.7/OA3+
3
P1.4/UCA0STE/TCK/A4
4
P1.5/UCA0CLK/TMS/OA1O/A5
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/OA1-/A6
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/OA1+/A7/VREF+
P2.0/TB1.1/COMP0.O
RST/NMI/SBWTDIO
DVCC
5
MSP430FR2355TRHA
MSP430FR2353TRHA
6
DVSS
7
P2.7/TB0CLK/XIN
P2.6/MCLK/XOUT
P2.5/COMP1.0
P2.4/COMP1.1
8
P2.1/TB1.2/COMP1.O
9
P2.2/TB1CLK
10
P2.3/TB1TRG
NOTE: Connect the exposed thermal pad to VSS.
图 4-2. 40-Pin RHA (VQFN) (Top View) – MSP430FR235x
版权 © 2018–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
11
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
图 4-3 shows the pinout of the 38-pin DBT package for the MSP430FR235x MCUs.
P3.2/OA2-
P3.1/OA2O
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
P3.3/OA2+
2
P5.0/TB2.1/MFM.RX/A8
P5.1/TB2.2/MFM.TX/A9
P3.4/SMCLK
P3.0/MCLK
3
P1.3/UCB0SOMI/UCB0SCL/OA0+/A3
P1.2/UCB0SIMO/UCB0SDA/TB0TRG/OA0-/A2/Veref-
P1.1/UCB0CLK/ACLK/OA0O/COMP0.1/A1
P1.0/UCB0STE/SMCLK/COMP0.0/A0/Veref+
TEST/SBWTCK
4
5
P3.5/OA3O
6
P3.6/OA3-
7
P3.7/OA3+
8
P1.4/UCA0STE/TCK/A4
P1.5/UCA0CLK/TMS/OA1O/A5
RST/NMI/SBWTDIO
9
MSP430FR2355TDBT
MSP430FR2353TDBT
DVCC
10
11
12
13
14
15
16
17
18
19
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/OA1-/A6
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/OA1+/A7/VREF+
P2.0/TB1.1/COMP0.O
DVSS
P2.7/TB0CLK/XIN
P2.6/MCLK/XOUT
P2.1/TB1.2/COMP1.O
P2.5/COMP1.0
P2.2/TB1CLK
P2.4/COMP1.1
P2.3/TB1TRG
P4.7/UCB1SOMI/UCB1SCL
P4.6/UCB1SIMO/UCB1SDA
P4.5/UCB1CLK
P4.0/UCA1STE/ISOTXD/ISORXD
P4.1/UCA1CLK
P4.2/UCA1RXD/UCA1SOMI/UCA1RXD
P4.3/UCA1TXD/UCA1SIMO/UCA1TXD
P4.4/UCB1STE
图 4-3. 38-Pin DBT (TSSOP) (Top View) – MSP430FR235x
12
Terminal Configuration and Functions
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
图 4-4 shows the pinout of the 32-pin RSM package for the MSP430FR235x MCUs.
P1.1/UCB0CLK/ACLK/OA0O/COMP0.1/A1
P1.0/UCB0STE/SMCLK/COMP0.0/A0/Veref+
1
2
3
4
5
6
24
23
22
21
20
19
18
17
P3.6/OA3-
P3.7/OA3+
P1.4/UCA0STE/TCK/A4
P1.5/UCA0CLK/TMS/OA1O/A5
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/OA1-/A6
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/OA1+/A7/VREF+
P2.0/TB1.1/COMP0.O
TEST/SBWTCK
RST/NMI/SBWTDIO
DVCC
DVSS
P2.7/TB0CLK/XIN
P2.6/MCLK/XOUT
MSP430FR2355TRSM
MSP430FR2353TRSM
7
8
P2.1/TB1.2/COMP1.O
NOTE: Connect the exposed thermal pad to VSS.
图 4-4. 32-Pin RSM (VQFN) (Top View) – MSP430FR235x
版权 © 2018–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
13
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
图 4-5 shows the pinout of the 48-pin PT package for the MSP430FR215x MCUs.
P1.2/UCB0SIMO/UCB0SDA/TB0TRG/A2/Veref-
P1.1/UCB0CLK/ACLK/COMP0.1/A1
P1.0/UCB0STE/SMCLK/COMP0.0/A0/Veref+
TEST/SBWTCK
1
36
35
34
33
32
31
30
29
28
27
26
25
P3.6
2
P3.7
3
P1.4/UCA0STE/TCK/A4
P1.5/UCA0CLK/TMS/A5
4
RST/NMI/SBWTDIO
5
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/A7/VREF+
P2.0/TB1.1/COMP0.O
DVCC
6
MSP430FR2155TPT
MSP430FR2153TPT
DVSS
7
P2.7/TB0CLK/XIN
8
P2.1/TB1.2/COMP1.O
P2.6/MCLK/XOUT
9
P2.2/TB1CLK
P2.5/COMP1.0
10
11
12
P2.3/TB1TRG
P2.4/COMP1.1
P4.0/UCA1STE/ISOTXD/ISORXD
P4.1/UCA1CLK
P4.7/UCB1SOMI/UCB1SCL
图 4-5. 48-Pin PT (LQFP) (Top View) – MSP430FR215x
14
Terminal Configuration and Functions
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
图 4-6 shows the pinout of the 40-pin RHA package for the MSP430FR215x MCUs.
1
2
P1.1/UCB0CLK/ACLK/COMP0.1/A1
P1.0/UCB0STE/SMCLK/COMP0.0/A0/Veref+
TEST/SBWTCK
30
29
28
27
26
25
24
23
22
21
P3.6
P3.7
3
P1.4/UCA0STE/TCK/A4
4
P1.5/UCA0CLK/TMS/A5
RST/NMI/SBWTDIO
DVCC
5
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/A7/VREF+
P2.0/TB1.1/COMP0.O
MSP430FR2155TRHA
MSP430FR2153TRHA
6
DVSS
7
P2.7/TB0CLK/XIN
P2.6/MCLK/XOUT
P2.5/COMP1.0
P2.4/COMP1.1
8
P2.1/TB1.2/COMP1.O
9
P2.2/TB1CLK
10
P2.3/TB1TRG
NOTE: Connect the exposed thermal pad to VSS.
图 4-6. 40-Pin RHA (VQFN) (Top View) – MSP430FR215x
版权 © 2018–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
15
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
图 4-7 shows the pinout of the 38-pin DBT package for the MSP430FR215x MCUs.
P3.2
P3.1
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
P3.3
2
P5.0/TB2.1/MFM.RX/A8
P5.1/TB2.2/MFM.TX/A9
P3.4/SMCLK
P3.5
P3.0/MCLK
3
P1.3/UCB0SOMI/UCB0SCL/A3
P1.2/UCB0SIMO/UCB0SDA/TB0TRG/A2/Veref-
P1.1/UCB0CLK/ACLK/COMP0.1/A1
P1.0/UCB0STE/SMCLK/COMP0.0/A0/Veref+
TEST/SBWTCK
4
5
6
P3.6
7
P3.7
8
P1.4/UCA0STE/TCK/A4
P1.5/UCA0CLK/TMS/A5
RST/NMI/SBWTDIO
9
MSP430FR2155TDBT
MSP430FR2153TDBT
DVCC
10
11
12
13
14
15
16
17
18
19
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/A7/VREF+
P2.0/TB1.1/COMP0.O
DVSS
P2.7/TB0CLK/XIN
P2.6/MCLK/XOUT
P2.1/TB1.2/COMP1.O
P2.5/COMP1.0
P2.2/TB1CLK
P2.4/COMP1.1
P2.3/TB1TRG
P4.7/UCB1SOMI/UCB1SCL
P4.6/UCB1SIMO/UCB1SDA
P4.5/UCB1CLK
P4.0/UCA1STE/ISOTXD/ISORXD
P4.1/UCA1CLK
P4.2/UCA1RXD/UCA1SOMI/UCA1RXD
P4.3/UCA1TXD/UCA1SIMO/UCA1TXD
P4.4/UCB1STE
图 4-7. 38-Pin DBT (TSSOP) (Top View) – MSP430FR215x
16
Terminal Configuration and Functions
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
图 4-8 shows the pinout of the 32-pin RSM package for the MSP430FR215x MCUs.
P1.1/UCB0CLK/ACLK/COMP0.1/A1
P1.0/UCB0STE/SMCLK/COMP0.0/A0/Veref+
1
2
3
4
5
6
24
23
22
21
20
19
18
17
P3.6
P3.7
TEST/SBWTCK
RST/NMI/SBWTDIO
DVCC
DVSS
P2.7/TB0CLK/XIN
P2.6/MCLK/XOUT
P1.4/UCA0STE/TCK/A4
P1.5/UCA0CLK/TMS/A5
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/A7/VREF+
P2.0/TB1.1/COMP0.O
MSP430FR2155TRSM
MSP430FR2153TRSM
7
8
P2.1/TB1.2/COMP1.O
NOTE: Connect the exposed thermal pad to VSS.
图 4-8. 32-Pin RSM (VQFN) (Top View) – MSP430FR215x
版权 © 2018–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
17
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
4.2 Pin Attributes
表 4-1 lists the attributes of all pins.
表 4-1. Pin Attributes
PIN NUMBER
SIGNAL
TYPE(3)
POWER
SOURCE
RESET STATE
AFTER BOR(5)
SIGNAL NAME(1) (2)
BUFFER TYPE(4)
PT
RHA
DBT
RSM
P1.2 (RD)
I/O
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
OFF
UCB0SIMO
UCB0SDA
TB0TRG
OA0-(6)
A2
–
–
1
40
5
32
–
I
–
I
Analog
–
Veref-
I
Analog
–
P1.1 (RD)
UCB0CLK
ACLK
OA0O(6)
COMP0_1
A1
I/O
I/O
O
O
I
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
–
2
3
1
2
6
7
1
2
–
Analog
–
I
Analog
–
P1.0 (RD)
UCB0STE
SMCLK
COMP0_0
A0
I/O
I/O
O
I
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
–
–
I
Analog
–
Veref+
I
Analog
–
TEST (RD)
SBWTCK
RST (RD)
NMI
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Power
OFF
–
4
5
3
4
8
9
3
4
I
I/O
I
OFF
–
SBWTDIO
DVCC
I/O
P
–
6
7
5
6
10
11
5
6
N/A
N/A
OFF
–
DVSS
P
Power
P2.7 (RD)
TB0CLK
XIN
I/O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
8
9
7
8
12
13
7
8
I
–
P2.6 (RD)
MCLK
I/O
O
O
I/O
I
OFF
–
XOUT
–
P2.5 (RD)
COMP1.0
P2.4 (RD)
COMP1.1
OFF
–
10
11
9
14
15
9
I/O
I
LVCMOS
Analog
OFF
–
10
10
(1) Signals names with (RD) denote the reset default pin name.
(2) To determine the pin mux encodings for each pin, see 节 6.11.
(3) Signal types: I = input, O = output, I/O = input or output
(4) Buffer types: LVCMOS, analog, or power
(5) Reset states:
OFF = High-impedance input with pullup or pulldown disabled (if available)
N/A = Not applicable
(6) MSP430FR235x devices only
18
Terminal Configuration and Functions
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
表 4-1. Pin Attributes (continued)
PIN NUMBER
SIGNAL
TYPE(3)
POWER
SOURCE
RESET STATE
AFTER BOR(5)
SIGNAL NAME(1) (2)
BUFFER TYPE(4)
PT
RHA
DBT
RSM
P4.7 (RD)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
OFF
–
12
11
16
11
UCB1SOMI(7)
UCB1SCL
P4.6 (RD)
UCB1SIMO(7)
UCB1SDA
P4.5 (RD)
UCB1CLK
P4.4 (RD)
UCB1STE
P6.6 (RD)
TB3CLK
–
OFF
–
13
12
17
12
–
OFF
–
14
15
16
17
18
19
20
21
22
13
14
–
18
19
–
–
–
–
–
–
–
–
–
–
OFF
–
OFF
–
P6.5 (RD)
TB3.6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
OFF
–
–
–
P6.4 (RD)
TB3.5
OFF
–
–
–
P6.3 (RD)
TB3.4
OFF
–
–
–
P6.2 (RD)
TB3.3
OFF
–
–
–
P6.1 (RD)
TB3.2
OFF
–
15
16
–
P6.0 (RD)
TB3.1
OFF
–
–
P4.3 (RD)
UCA1TXD
UCA1SIMO
UCA1TXD
P4.2 (RD)
UCA1RXD
UCA1SOMI
UCA1RXD
P4.1 (RD)
UCA1CLK
P4.0 (RD)
UCA1STE
ISOTXD
OFF
–
23
17
20
13
I/O
O
–
–
I/O
I
OFF
–
24
25
26
18
19
20
21
22
23
14
15
16
I/O
I
–
–
I/O
I/O
I/O
I/O
O
OFF
–
OFF
–
–
ISORXD
I
–
P2.3 (RD)
TB1TRG
P2.2 (RD)
TB1CLK
I/O
I
OFF
–
27
28
21
22
24
25
–
–
I/O
I
OFF
–
P2.1(RD)
TB1.2
I/O
I/O
O
OFF
–
29
23
26
17
COMP1.O
–
(7) Not applicable in RSM package.
版权 © 2018–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
19
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes (continued)
PIN NUMBER
SIGNAL
TYPE(3)
POWER
SOURCE
RESET STATE
AFTER BOR(5)
SIGNAL NAME(1) (2)
BUFFER TYPE(4)
PT
RHA
DBT
RSM
P2.0 (RD)
I/O
I/O
O
I/O
O
I/O
I/O
O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
OFF
30
24
27
18
TB1.1
–
COMP0.O
P1.7 (RD)
UCA0TXD
UCA0SIMO
TB0.2
–
OFF
–
–
–
31
25
28
19
TDO
OA1+(6)
–
–
A7
I
Analog
–
VREF+
P1.6 (RD)
UCA0RXD
UCA0SOMI
TB0.1
O
I/O
I
Analog
–
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
I/O
I/O
I
–
–
32
26
29
20
TDI
–
TCLK
OA1-(6)
I
–
–
I
A6
I
Analog
–
P1.5 (RD)
UCA0CLK
TMS
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
33
34
27
28
30
31
21
22
–
OA1O(6)
O
I
-
A5
Analog
–
P1.4 (RD)
UCA0STE
TCK
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
–
A4
I
–
P3.7 (RD)
OA3+(6)
P3.6 (RD)
OA3-(6)
P3.5 (RD)
OA3O(6)
P3.4 (RD)
SMCLK
P5.4 (RD)
P5.3 (RD)
TB2TRG
A11
I/O
I
LVCMOS
Analog
OFF
–
35
36
37
29
30
31
32
33
34
23
24
25
I/O
I
LVCMOS
Analog
OFF
–
I/O
O
I/O
O
I/O
I/O
I
LVCMOS
Analog
OFF
–
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
38
39
32
–
35
–
26
–
OFF
OFF
–
40
41
–
–
–
–
–
–
I
–
P5.2 (RD)
TB2CLK
A10
I/O
I
LVCMOS
LVCMOS
Analog
OFF
–
I
–
20
Terminal Configuration and Functions
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
表 4-1. Pin Attributes (continued)
PIN NUMBER
SIGNAL
TYPE(3)
POWER
SOURCE
RESET STATE
AFTER BOR(5)
SIGNAL NAME(1) (2)
BUFFER TYPE(4)
PT
RHA
DBT
RSM
P5.1 (RD)
I/O
I/O
O
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
OFF
TB2.2
–
–
42
33
36
–
MFM.TX
A9
I
–
P5.0 (RD)
TB2.1
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
43
34
37
–
MFM.RX
A8
–
I
–
P3.3 (RD)
OA2+(6)
P3.2 (RD)
OA2-(6)
P3.1 (RD)
OA2O(6)
P3.0 (RD)
MCLK
I/O
I
LVCMOS
Analog
OFF
–
44
45
46
47
35
36
37
38
38
1
27
28
29
30
I/O
I
LVCMOS
Analog
OFF
–
I/O
O
LVCMOS
Analog
OFF
–
2
I/O
O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
3
P1.3 (RD)
UCB0SOMI
UCB0SCL
OA0+(6)
A3
I/O
I/O
I/O
I
OFF
–
48
39
4
31
–
–
I
Analog
–
版权 © 2018–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
21
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
4.3 Signal Descriptions
表 4-2 describes the signals for all device variants and package options.
表 4-2. Signal Descriptions
PIN NUMBER(1)
PIN
FUNCTION
SIGNAL NAME
DESCRIPTION
TYPE(2)
PT
3
RHA
2
DBT
7
RSM
2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I
I
Analog input A0
Analog input A1
Analog input A2
Analog input A3
Analog input A4
Analog input A5
Analog input A6
Analog input A7
Analog input A8
Analog input A9
Analog input A10
Analog input A11
2
1
6
1
1
40
39
28
27
26
25
34
33
–
5
32
31
22
21
20
19
–
I
48
34
33
32
31
43
42
41
40
3
4
I
31
30
29
28
37
36
–
I
I
I
ADC
I
I
–
I
A10
–
I
A11
–
–
–
I
Veref+
Veref-
C0
2
7
2
I
ADC positive reference
ADC negative reference
Comparator input channel C0
Comparator input channel C1
Comparator output channel COUT
Comparator input channel C0
Comparator input channel C1
Comparator output channel COUT
SAC0, OA positive input
SAC0, OA negative input
SAC0, OA output
1
40
2
5
32
2
I
3
7
I
eCOMP0
eCOMP1
SAC0(3)
SAC1(3)
SAC2(3)
SAC3(3)
C1
2
1
6
1
I
COUT
C0
30
10
11
29
48
1
24
9
27
14
15
26
4
18
9
O
I
C1
10
23
39
40
1
10
17
31
32
1
I
COUT
OA0+
OA0-
OA0O
OA1+
OA1-
OA1O
OA2+
OA2-
OA2O
OA3+
OA3-
OAO
ACLK
O
I
5
I
2
6
O
I
31
32
33
44
45
46
35
36
37
2
25
26
27
35
36
37
29
30
31
1
28
29
30
38
1
19
20
21
27
28
29
23
24
25
1
SAC1, OA positive input
SAC1, OA negative input
SAC1, OA output
I
O
I
SAC2, OA positive input
SAC2, OA negative input
SAC2, OA output
I
2
O
I
32
33
34
6
SAC3, OA positive input
SAC3, OA negative input
SAC3, OA output
I
O
O
O
O
O
O
I
ACLK output
9
8
13
3
8
MCLK
MCLK output
47
3
38
2
30
2
Clock
7
SMCLK
SMCLK output
38
8
32
7
35
12
13
26
7
XIN
Input terminal for crystal oscillator
Output terminal for crystal oscillator
XOUT
9
8
8
O
(1) Any pin that is not bonded out in a smaller package must be initialized by software after reset to achieve the lowest leakage current.
(2) I = input, O = output, I/O = input/output, P = power
(3) MSP430FR235x devices only
22
Terminal Configuration and Functions
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
FUNCTION
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
表 4-2. Signal Descriptions (continued)
PIN NUMBER(1)
PIN
SIGNAL NAME
SBWTCK
DESCRIPTION
TYPE(2)
PT
4
RHA
3
DBT
8
RSM
3
I
I/O
I
Spy-Bi-Wire input clock
Spy-Bi-Wire data input/output
Test clock
SBWTDIO
TCK
5
4
9
4
34
32
32
31
33
4
28
26
26
25
27
3
31
29
29
28
30
8
22
20
20
19
21
3
TCLK
TDI
I
Test clock input
Debug
I
Test data input
TDO
O
I
Test data output
TMS
Test mode select
TEST
NMI
I
Test mode pin – selected digital I/O on JTAG pins
Nonmaskable interrupt input
Reset input, active-low
Power supply
5
4
9
4
I
System
Power
RST
5
4
9
4
I/O
P
P
DVCC
DVSS
6
5
10
11
5
7
6
6
Power ground
Output of positive reference voltage with ground as
reference
VREF+
31
25
28
19
P
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
3
2
7
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
2
1
6
1
1
40
39
28
27
26
25
24
23
22
21
10
9
5
32
31
22
21
20
19
18
17
–
48
34
33
32
31
30
29
28
27
11
10
9
4
GPIO, Port 1
GPIO, Port 2
GPIO, Port 3
(4)
31
30
29
28
27
26
25
24
15
14
13
12
3
General-purpose I/O
(4)
General-purpose I/O
General-purpose I/O(4)
General-purpose I/O(4)
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
–
10
9
8
8
8
7
7
47
46
45
44
38
37
36
35
38
37
36
35
32
31
30
29
30
29
28
27
26
25
24
23
2
1
38
35
34
33
32
(4) Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to
prevent collisions.
Functions shared with these four pins cannot be debugged if 4-wire JTAG is used for debug.
版权 © 2018–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
23
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
表 4-2. Signal Descriptions (continued)
PIN NUMBER(1)
PIN
FUNCTION
SIGNAL NAME
P4.0
DESCRIPTION
TYPE(2)
PT
26
25
24
23
15
14
13
12
43
42
41
40
39
22
21
20
19
18
17
16
31
32
23
24
RHA
20
19
18
17
14
13
12
11
34
33
–
DBT
23
22
21
20
19
18
17
16
37
36
–
RSM
16
15
14
13
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
General-purpose I/O
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P5.0
P5.1
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
eUSCI_A0 UART transmit data
eUSCI_A0 UART receive data
eUSCI_A1 UART transmit data
eUSCI_A1 UART receive data
GPIO, Port 4
–
12
11
–
–
GPIO, Port 5 P5.2
–
P5.3
–
–
–
P5.4
–
–
–
P6.0
16
15
–
–
–
P6.1
–
–
P6.2
–
–
GPIO, Port 6 P6.3
–
–
–
P6.4
P6.5
P6.6
–
–
–
–
–
–
–
–
–
UCA0TXD
25
26
17
18
28
29
20
21
19
20
13
14
UCA0RXD
UCA1TXD
UCA1RXD
I
UART
ISO
O
I
ISO transmit data (the logical AND product of
UCA1TXD and TB3.2B)
ISOTXD
26
20
23
16
O
ISORXD
26
34
33
32
31
26
25
24
23
3
20
28
27
26
25
20
19
18
17
2
23
31
30
29
28
23
22
21
20
7
16
22
21
20
19
16
15
14
13
2
I
ISO receive data (to UCA1RXD and TB3.CCI2B)
eUSCI_A0 SPI slave transmit enable
eUSCI_A0 SPI clock input/output
eUSCI_A0 SPI slave out/master in
eUSCI_A0 SPI slave in/master out
eUSCI_A1 SPI slave transmit enable
eUSCI_A1 SPI clock input/output
eUSCI_A1 SPI slave out/master in
eUSCI_A1 SPI slave in/master out
eUSCI_B0 slave transmit enable
eUSCI_B0 clock input/output
UCA0STE
UCA0CLK
UCA0SOMI
UCA0SIMO
UCA1STE
UCA1CLK
UCA1SOMI
UCA1SIMO
UCB0STE
UCB0CLK
UCB0SIMO
UCB0SOMI
UCB1STE
UCB1CLK
UCB1SIMO
UCB1SOMI
UCB0SCL
UCB0SDA
UCB1SCL
UCB1SDA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SPI
2
1
6
1
1
40
39
14
13
12
11
39
40
11
12
5
32
31
–
eUSCI_B0 SPI slave in/master out
eUSCI_B0 SPI slave out/master in
eUSCI_B1 slave transmit enable
eUSCI_B1 clock input/output
48
15
14
13
12
48
1
4
19
18
17
16
4
–
–
eUSCI_B1 SPI slave in/master out
eUSCI_B1 SPI slave out/master in
eUSCI_B0 I2C clock
eUSCI_B0 I2C data
eUSCI_B1 I2C clock
–
31
32
11
12
5
I2C
12
13
16
17
eUSCI_B1 I2C data
24
Terminal Configuration and Functions
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www.ti.com.cn
FUNCTION
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
表 4-2. Signal Descriptions (continued)
PIN NUMBER(1)
PIN
SIGNAL NAME
TB0.1
DESCRIPTION
TYPE(2)
PT
RHA
DBT
RSM
Timer TB0 CCR1
capture: CCI1A input, compare: Out1 output
32
26
29
20
I/O
I/O
Timer TB0 CCR2
capture: CCI2A input
compare: Out2 output
TB0.2
31
25
28
19
TB0TRG
TB0CLK
1
8
40
7
5
32
7
I
I
TB0 external trigger input for TB0OUTH
Timer clock input TBCLK for TB0
12
Timer TB1 CCR1
TB1.1
TB1.2
30
29
24
23
27
26
18
17
I/O
I/O
capture: CCI1A input
compare: Out1 output
Timer TB1 CCR2
capture: CCI2A input
compare: Out2 output
TB1CLK
TB1TRG
28
27
22
21
25
24
–
–
I
I
Timer clock input TBCLK for TB1
TB1 external trigger input for TB1OUTH
Timer TB2 CCR1
TB2.1
TB2.2
43
42
34
33
37
36
–
–
I/O
I/O
capture: CCI1A input
compare: Out1 output
Timer TB2 CCR2
capture: CCI2A input
compare: Out2 output
Timer_B
TB2CLK
TB2TRG
41
40
–
–
–
–
–
–
I
I
Timer clock input TBCLK for TB2
TB2 external trigger input for TB2OUTH
Timer TB3 CCR1
TB3.1
TB3.2
TB3.3
TB3.4
TB3.5
TB3.6
22
21
20
19
18
17
16
15
–
–
–
–
–
–
–
–
–
–
–
–
–
I/O
I/O
I/O
I/O
I/O
I/O
capture: CCI1A input
compare: Out1 output
Timer TB3 CCR2
capture: CCI2A input
compare: Out2 output
Timer TB3 CCR3
capture: CCI3A input
compare: Out3 output
Timer TB3 CCR4
capture: CCI4A input
compare: Out4 output
–
Timer TB3 CCR5
capture: CCI5A input
compare: Out5 outputs
–
Timer TB3 CCR6
capture: CCI6A input
compare: Out6 output
–
TB3CLK
TX
16
42
43
–
–
–
–
–
I
O
I
Timer clock input TBCLK for TB3
Manchester function module transmit
Manchester function module receive
33
34
36
37
MFM
RX
VQFN
thermal pad
–
Pad
–
Pad
–
Connect the exposed thermal pad to VSS.
版权 © 2018–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
25
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www.ti.com.cn
4.4 Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and diagrams of the
multiplexed ports, see 节 6.11.
4.5 Buffer Type
表 4-3 defines the pin buffer types that are listed in 表 4-1.
表 4-3. Buffer Type
NOMINAL
OUTPUT DRIVE
STRENGTH
(mA)
BUFFER TYPE
(STANDARD)
NOMINAL
VOLTAGE
PU OR PD
STRENGTH
(µA)
OTHER
CHARACTERISTICS
HYSTERESIS
PU OR PD
LVCMOS
Analog
3.0 V
3.0 V
Y(1)
N
Programmable
N/A
See 节 5.12.5
See 节 5.12.5
See the analog modules in
节 5 for details
N/A
N/A
SVS enables hysteresis on
DVCC
Power (DVCC)
Power (AVCC)
3.0 V
3.0 V
N
N
N/A
N/A
N/A
N/A
N/A
N/A
(1) Only for input pins
4.6 Connection of Unused Pins
表 4-4 lists the correct termination of unused pins.
表 4-4. Connection of Unused Pins(1)
PIN
POTENTIAL
Open
COMMENT
Set to port function, output direction (PxDIR.n = 1)
47-kΩ pullup or internal pullup selected with 10-nF (or 1.1-nF) pulldown(2)
Px.0 to Px.7
RST/NMI
TEST
DVCC
Open
This pin always has an internal pulldown enabled.
(1) Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection
guidelines.
(2) The pulldown capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode with TI tools like
FET interfaces or GANG programmers.
26
Terminal Configuration and Functions
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ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
5 Specifications
5.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
DEVICE
GRADE
MIN
–0.3
–0.3
MAX
UNIT
V
Voltage applied at DVCC pin to VSS
Voltage applied to any pin(2)
T
4.1
VCC + 0.3
4.1 V Max
T
V
Current across the whole chip including IO currents
Diode current at any device pin
T
T
T
T
+50
±2
mA
mA
°C
Maximum junction temperature, TJ
115
125
(3)
Storage temperature, Tstg
–40
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.
(2) All voltages referenced to VSS
.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2 ESD Ratings
over operating free-air temperature range (unless otherwise noted)
DEVICE
GRADE
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
T
T
±1000
±250
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±250 V may actually have higher performance.
5.3 Recommended Operating Conditions
DEVICE
GRADE
MIN NOM
MAX UNIT
VCC
VSS
TA
Supply voltage applied at DVCC pin(1) (2)(3) (4)
Supply voltage applied at DVSS pin
Operating free-air temperature
T
T
T
T
T
1.8
3.6
V
V
0
–40
–40
105
115
°C
°C
µF
TJ
Operating junction temperature
Recommended capacitor at DVCC(5)
CDVCC
4.7
10
No FRAM wait states
(NWAITSx = 0)
T
T
T
0
8
With FRAM wait states
(NWAITSx = 1)(7)
fSYSTEM Processor frequency (maximum MCLK frequency)(4)(6)
0
0
16 MHz
24(8)
With FRAM wait states
(NWAITSx = 2)(7)
(1) Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset even within the recommended supply voltage range. Following the
data sheet recommendation for capacitor CDVCC limits the slopes accordingly.
(2) Modules can have a different supply voltage range specification. See the specification of the respective module in this data sheet.
(3) TI recommends that power to the DVCC pin must not exceed the limits specified in Recommended Operating Conditions. Exceeding the
specified limits can cause malfunction of the device including erroneous writes to RAM and FRAM.
(4) The minimum supply voltage is defined by the SVS levels. See the SVS threshold parameters in 表 5-1.
(5) A capacitor tolerance of ±20% or better is required. A low-ESR ceramic capacitor of 100 nF (minimum) should be placed as close as
possible (within a few millimeters) to the respective pin pair.
(6) Modules can have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(7) Wait states only occur on actual FRAM accesses (that is, on FRAM cache misses). RAM and peripheral accesses are always executed
without wait states.
(8) If clock sources such as HF crystals or the DCO with frequencies >24 MHz are used, the clock must be divided in the clock system to
comply with this operating condition.
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Specifications
27
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MAX UNIT
Recommended Operating Conditions (continued)
DEVICE
GRADE
MIN NOM
fACLK
Maximum ACLK frequency
Maximum SMCLK frequency
T
T
40 kHz
24(8) MHz
fSMCLK
5.4 Active Mode Supply Current Into VCC Excluding External Current
over operating free-air temperature range (unless otherwise noted)(1)
Frequency (fMCLK = fSMCLK
)
1 MHz
0 WAIT
STATES
8 MHz
0 WAIT
STATES
16 MHz
1 WAIT
STATE
24 MHz
2 WAIT
STATES
EXECUTION
MEMORY
TEST
CONDITIONS
DEVICE
GRADE
PARAMETER
UNIT
(NWAITSx (NWAITSx (NWAITSx (NWAITSx
= 0) = 0) = 1) = 2)
TYP MAX TYP MAX TYP MAX TYP MAX
3.0 V, 25°C
3.0 V, 85°C
3.0 V, 105°C
3.0 V, 25°C
3.0 V, 85°C
3.0 V, 105°C
3.0 V, 25°C
T
T
T
T
T
T
T
555
575
583
261
272
283
285
3084
3207
3233
724
3411
3519
3545
1245
1267
1281
1627
3692
3807
3833
1772
1800
1817
2355
FRAM
0% cache hit ratio
IAM, FRAM(0%)
µA
FRAM
100% cache hit ratio
IAM, FRAM(100%)
742
µA
µA
753
(2)
IAM, RAM
RAM
917
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. Characterized with program executing typical data
processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency
Program and data entirely reside in FRAM. All execution is from FRAM.
(2) Program and data reside entirely in RAM. All execution is from RAM. No access to FRAM.
5.5 Active Mode Supply Current Per MHz
VCC = 3.0 V, TA = 25°C (unless otherwise noted)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Active mode current consumption
(IAM, 75% cache hit rate at 8 MHz –
dIAM,FRAM/df
per MHz, execution from FRAM, no wait IAM, 75% cache hit rate at 1 MHz)
T
142
µA/MHz
states(1)
/ 7 MHz
(1) All peripherals are turned on in default settings.
5.6 Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
(2)
VCC = 3.0 V, TA = 25°C (unless otherwise noted)(1)
FREQUENCY (fSMCLK
8 MHz 16 MHz
TYP MAX TYP MAX TYP MAX TYP MAX
)
DEVICE
GRADE
PARAMETER
VCC
1 MHz
24 MHz
UNIT
2.0 V
3.0 V
T
T
199
211
312
324
437
449
637
649
ILPM0
Low-power mode 0 supply current
µA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Current for watchdog timer clocked by SMCLK included.
fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK at specified frequency.
28
Specifications
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ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
5.7 Low-Power Mode LPM3 and LPM4 Supply Currents (Into VCC) Excluding External Current
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
–40°C
TYP MAX
25°C
TYP
85°C
TYP
105°C
TYP MAX
DEVICE
GRADE
PARAMETER
VCC
UNIT
MAX
MAX
Low-power mode 3,
includes SVS(2) (3) (4)
ILPM3,XT1
ILPM3,XT1
ILPM3,VLO
ILPM3,VLO
ILPM3, RTC
ILPM3, RTC
ILPM4, SVS
ILPM4, SVS
T
T
T
T
T
T
T
T
T
T
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
1.21
1.18
1.01
0.99
1.15
1.13
0.74
0.72
0.56
0.55
1.49
1.45
1.29
1.26
1.43
1.41
1.00
0.98
0.82
0.81
6.35 21.85 13.29 47.87
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
Low-power mode 3,
includes SVS(2) (3) (4)
6.28
13.17
Low-power mode 3, VLO,
excludes SVS(5)
6.15 21.65
6.09
13.1 47.67
12.98
Low-power mode 3, VLO,
excludes SVS(5)
Low-power mode 3, RTC,
excludes SVS(6)
6.29
13.24
Low-power mode 3, RTC,
excludes SVS(6)
6.23
13.13
Low-power mode 4,
includes SVS
5.83
12.73
Low-power mode 4,
includes SVS
5.77
12.62
Low-power mode 4,
excludes SVS
ILPM4
ILPM4
,
,
5.64
12.54
Low-power mode 4,
excludes SVS
5.59
12.45
Low-power mode 4, RTC
is sourced from VLO,
excludes SVS(7)
ILPM4, RTC, VLO
ILPM4, RTC, VLO
ILPM4, RTC, XT1
ILPM4, RTC, XT1
T
T
T
T
3.0 V
2.0 V
3.0 V
2.0 V
0.66
0.66
1.06
1.05
0.93
0.92
1.34
1.33
5.76
5.71
6.21
6.16
12.67
12.58
13.15
13.05
µA
µA
µA
µA
Low-power mode 4, RTC
is sourced from VLO,
excludes SVS(7)
Low-power mode 4, RTC
is sourced from XT1,
excludes SVS(8)
Low-power mode 4, RTC
is sourced from XT1,
excludes SVS(8)
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current
(2) Not applicable for devices with HF crystal oscillator only.
(3) Characterized with a Seiko Crystal SC-32S crystal with a load capacitance chosen to closely match the required load.
(4) Low-power mode 3, includes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(5) Low-power mode 3, VLO, excludes SVS test conditions:
Current for watchdog timer clocked by VLO included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
(6) RTC wakes every second with external 32768-Hz clock as source.
(7) Low-power mode 4, VLO, excludes SVS test conditions:
Current for RTC clocked by VLO included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 32768 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
(8) Low-power mode 4, XT1, excludes SVS test conditions:
Current for RTC clocked by XT1 included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 32768 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
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Specifications
29
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
5.8 Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
–40°C
25°C
85°C
105°C
TYP MAX
DEVICE
GRADE
PARAMETER
VCC
UNIT
TYP MAX
TYP MAX
TYP MAX
Low-power mode 3.5,
ILPM3.5, XT1 includes SVS(1) (2) (3)
(also see 图 5-3)
T
T
3.0 V
0.57
0.55
0.62
0.59
0.89
0.84
2.06
0.63
1.27
1.19
3.21
1.13
µA
µA
Low-power mode 3.5,
ILPM3.5, XT1 includes SVS(1) (2) (3)
(also see 图 5-3)
2.0 V
Low-power mode 4.5,
ILPM4.5, SVS
T
T
T
T
3.0 V
2.0 V
3.0 V
2.0 V
0.27
0.25
0.29
0.27
0.41
0.37
0.61
0.55
µA
µA
µA
µA
includes SVS(4)
Low-power mode 4.5,
ILPM4.5, SVS
includes SVS(4)
Low-power mode 4.5,
ILPM4.5
0.031
0.025
0.042
0.036
0.153 0.343 0.337 0.832
0.128 0.289
excludes SVS(5)
Low-power mode 4.5,
ILPM4.5
excludes SVS(5)
(1) Not applicable for devices with HF crystal oscillator only
(2) Characterized with a Seiko Crystal SC-32S crystal with a load capacitance chosen to closely match the required load.
(3) Low-power mode 3.5, includes SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(4) Low-power mode 4.5, includes SVS test conditions:
Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
(5) Low-power mode 4.5, excludes SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
30
Specifications
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
5.9 Production Distribution of LPM Supply Currents
VCC = 3 V
16
16
14
12
10
8
14
12
10
8
6
6
4
4
2
2
0
0
-40 -30 -20 -10
0
10 25 30 40 50 60 70 85 95 105
-40 -30 -20 -10
0
10 25 30 40 50 60 70 85 95 105
Temperature (°C)
Temperature (°C)
RTC enabled
12.5-pF crystal
SVS disabled
RTC enabled
12.5-pF crystal
SVS disabled
图 5-2. Population vs Low-Power Mode 4 Supply Current
图 5-1. Population vs Low-Power Mode 3 Supply Current
4
3.5
3
0.4
0.35
0.3
0.25
0.2
2.5
2
1.5
1
0.15
0.1
0.5
0.05
0
0
-40 -30 -20 -10 0 10 25 30 40 50 60 70 85 95 105
-40 -30 -20 -10 0 10 25 30 40 50 60 70 85 95 105
Temperature (°C)
Temperature (°C)
RTC enabled
12.5-pF crystal
SVS enabled
RTC disabled
SVS disabled
图 5-3. LPM3.5 Supply Current vs Temperature
图 5-4. LPM4.5 Supply Current vs Temperature
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Specifications
31
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ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
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5.10 Typical Characteristics - Current Consumption Per Module
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
MODULE
TEST CONDITIONS
REFERENCE CLOCK
TYP
UNIT
Timer_B
Module input clock
T
T
T
T
T
T
T
5
7
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
nA
eUSCI_A
eUSCI_A
eUSCI_B
eUSCI_B
RTC
UART mode
Module input clock
Module input clock
Module input clock
Module input clock
32 kHz
SPI mode
5
SPI mode
I2C mode, 100 kbaud
5
5
85
8.5
CRC
From start to end of operation
MCLK
µA/MHz
5.11 Thermal Resistance Characteristics
THERMAL METRIC(1)
VALUE(2)
67.6
31.6
67.0
32.3
24.0
24.1
19.8
27.8
31.6
12.6
27.3
11.8
UNIT
QFP 48 pin (PT)
QFN 40 pin (RHA)
RθJA
RθJC
RθJB
Junction-to-ambient thermal resistance, still air
ºC/W
TSSOP 38 pin (DBT)
QFN 32 pin (RSM)
QFP 48 pin (PT)
QFN 40 pin (RHA)
TSSOP 38 pin (DBT)
QFN 32 pin (RSM)
QFP 48 pin (PT)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ºC/W
ºC/W
QFN 40 pin (RHA)
TSSOP 38 pin (DBT)
QFN 32 pin (RSM)
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC (RθJC) value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC
standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
32
Specifications
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
5.12 Timing and Switching Characteristics
5.12.1 Power Supply Sequencing
图 5-5 shows the power cycle and reset conditions.
V
Power Cycle Reset
SVS Reset
BOR Reset
VSVS+
VSVS–
VBOR
tBOR
t
图 5-5. Power Cycle, SVS, and BOR Reset Conditions
表 5-1 lists the characteristics of the SVS and BOR.
表 5-1. PMM, SVS and BOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
DEVICE
GRADE
PARAMETER
MIN
TYP
MAX UNIT
VBOR, safe
tBOR, safe
ISVSH,AM
Safe BOR power-down level(1)
Safe BOR reset delay(2)
T
T
T
T
T
T
T
T
T
0.1
10
V
ms
SVSH current consumption, active mode
SVSH current consumption, low-power modes
SVSH power-down level(3)
VCC = 3.6 V
VCC = 3.6 V
1.5
µA
nA
V
ISVSH,LPM
VSVSH-
240
1.80
1.88
100
1.71
1.76
1.87
1.99
VSVSH+
SVSH power-up level(3)
V
VSVSH_hys
tPD,SVSH, AM
tPD,SVSH, LPM
SVSH hysteresis
mV
µs
µs
SVSH propagation delay, active mode
SVSH propagation delay, low-power modes
10
100
(1) A safe BOR can only be correctly generated only if DVCC must drop below this voltage before it rises.
(2) When an BOR occurs, a safe BOR can only be correctly generated only if DVCC is kept low longer than this period before it reaches
VSVSH+.
(3) For additional information, see the Dynamic Voltage Scaling Power Solution for MSP430 Devices With Single-Channel LDO Reference
Design.
版权 © 2018–2019, Texas Instruments Incorporated
Specifications
33
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
5.12.2 Reset Timing
表 5-2 lists the device wake-up times.
表 5-2. Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
DEVICE
GRADE
PARAMETER
VCC
MIN
TYP
MAX UNIT
(Additional) wake-up time to activate
the FRAM in AM if previously
disabled through the FRAM
controller or from a LPM if
immediate activation is selected for
wake-up(1)
tWAKE-UP FRAM
T
3 V
10
µs
Wake-up time from LPM0 to active
mode
200 ns +
2.5 / fDCO
tWAKE-UP LPM0
tWAKE-UP LPM3
tWAKE-UP LPM4
tWAKE-UP LPM3.5
T
T
T
T
3 V
3 V
3 V
3 V
(1)
Wake-up time from LPM3 to active
10
10
µs
µs
µs
(1)
mode
Wake-up time from LPM4 to active
(2)
mode
Wake-up time from LPM3.5 to
350
(2)
active mode
SVSHE = 1
SVSHE = 0
T
T
3 V
3 V
350
1
µs
Wake-up time from LPM4.5 to
active mode
tWAKE-UP LPM4.5
(2)
ms
Wake-up time from RST or BOR
event to active mode
tWAKE-UP-RESET
tRESET
T
T
3 V
1
ms
µs
(2)
Pulse duration required at RST/NMI
pin to accept a reset
2
(1) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first
externally observable MCLK clock edge.
(2) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
34
Specifications
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
5.12.3 Clock Specifications
表 5-3 lists the characteristics of XT1 in low-frequency mode.
表 5-3. XT1 Crystal Oscillator (Low Frequency)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fXT1, LF
XT1 oscillator crystal, low frequency
XT1 oscillator LF duty cycle
LFXTBYPASS = 0
T
32768
Hz
Measured at MCLK,
fLFXT = 32768 Hz
DCXT1, LF
T
T
T
30%
70%
XT1 oscillator logic-level square-wave
input frequency
fXT1,SW
LFXTBYPASS = 1(3)(4)
32768
Hz
LFXT oscillator logic-level square-wave
input duty cycle
DCXT1,SW
LFXTBYPASS = 1
40%
60%
LFXTBYPASS = 0,
LFXTDRIVE = {3},
fLFXT = 32768 Hz,
CL,eff = 12.5 pF
(7)
OALFXT
Oscillation allowance for LF crystals(5)
Integrated effective load capacitance(6)
T
T
T
T
200
1
kΩ
pF
ms
Hz
CL,eff
fOSC = 32768 Hz,
LFXTBYPASS = 0,
LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF
XTS = 0(10)
tSTART,LFXT Start-up time(8)
Oscillator fault frequency(9)
1000
fFault,LFXT
0
3500
(1) To improve EMI on the LFXT oscillator, observe the following guidelines.
•
•
•
•
•
•
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing.
(3) When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT,SW
.
(4) Maximum frequency of operation of the entire device cannot be exceeded.
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
•
•
•
•
For LFXTDRIVE = {0}, CL,eff = 3.7 pF
For LFXTDRIVE = {1}, 6 pF ≤ CL,eff ≤ 9 pF
For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 10 pF
For LFXTDRIVE = {3}, 6 pF ≤ CL,eff ≤ 12 pF
(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
(7) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF. The PCB adds
additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance
of the selected crystal is met.
(8) Includes startup counter of 1024 clock cycles.
(9) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specifications might set the
flag. A static condition or stuck at fault condition sets the flag.
(10) Measured with logic-level input frequency but also applies to operation with crystals.
版权 © 2018–2019, Texas Instruments Incorporated
Specifications
35
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
表 5-4 lists the characteristics of XT1 in high-frequency mode.
表 5-4. XT1 Crystal Oscillator (High Frequency)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
MIN
1
TYP
MAX
UNIT
XT1BYPASS = 0, XTS = 1,
XT1HFFREQ = 00
T
4
6
XT1BYPASS = 0, XTS = 1,
XT1HFFREQ = 01
T
T
T
4.01
6.01
16.01
HFXT oscillator crystal
frequency, crystal mode
fHFXT
MHz
XT1BYPASS = 0, XTS = 1,
XT1HFFREQ = 10
16
24
XT1BYPASS = 0, XTS = 1,
XT1HFFREQ = 11
HFXT oscillator logic-
level square-wave input XT1BYPASS = 1, XTS = 1
frequency, bypass mode
(2) (3)
fHFXT,SW
T
T
T
T
1
40%
40%
24
60%
60%
MHz
HFXT oscillator duty
cycle.
Measured at ACLK,
fHFXT,HF = 4 MHz(4)
DCHFXT
HFXT oscillator logic-
level square-wave input XT1BYPASS = 1
duty cycle
DCHFXT,SW
Oscillation allowance for XT1BYPASS = 0, XT1HFSEL = 1
OAHFXT
3.1
1.6
Ω
HFXT crystals(5)
fHFXT,HF = 24 MHz, CL,eff = 18 pF
fOSC = 4 MHz, XTS = 1(4)
XT1BYPASS = 0,
XT1HFFREQ = 00,
XT1DRIVE = 3, TA = 25°C,
CL,eff = 18 pF
fOSC = 24 MHz, XTS = 1(4)
XT1BYPASS = 0,
T
T
tSTART,HFXT
Start-up time(6)
ms
XT1HFFREQ = 00,
XT1DRIVE = 3, TA = 25°C,
CL,eff = 18 pF
1.1
1
Integrated effective load
capacitance(7) (8)
CL,eff
T
T
pF
Oscillator fault
fFault,HFXT
0
800
kHz
frequency(9) (10)
(1) To improve EMI on the HFXT oscillator, observe the following guidelines.
•
•
•
•
•
•
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) When XT1BYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics defined
in the Schmitt-trigger Inputs section of this datasheet. Duty cycle requirements are defined by DCHFXT,SW
.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) The 4-MHz crystal used for lab characterization is the Abracon HC49/U AB-4.000MHZ-B2. The 16-MHz crystal used for lab
characterization is the Abracon HC49/U AB-16.000MHZ-B2.
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
(6) Includes startup counter of 4096 clock cycles.
(7) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the oscillator frequency through
MCLK or SMCLK. For a correct setup, the effective load capacitance should always match the specification of the used crystal.
(8) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Recommended values supported are
14 pF, 16 pF, and 18 pF. The maximum shunt capacitance is 7 pF.
(9) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specifications might set the
flag. A static condition or stuck at fault condition sets the flag.
(10) Measured with logic-level input frequency but also applies to operation with crystals.
36
Specifications
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
表 5-5 lists the frequency characteristics of the DCO FLL.
表 5-5. DCO FLL, Frequency
Over recommended operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
VCC
MIN
–1.0%
–2.0%
–0.5%
40%
TYP
MAX UNIT
1.0%
Measured at MCLK, internal
trimmed REFO as reference
fDCO, FLL FLL lock frequency, 24 MHz, 25°C
fDCO, FLL FLL lock frequency, 24 MHz
fDCO, FLL FLL lock frequency, 24 MHz
T
T
T
T
T
T
T
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
Measured at MCLK, internal
trimmed REFO as reference
2.0%
Measured at MCLK, XT1
crystal as reference
0.5%
Measured at MCLK, XT1
crystal as reference
fDUTY
Duty cycle
50%
0.50%
0.022%
200
60%
Measured at MCLK, XT1
crystal as reference
Jittercc
Jitterlong
tFLL, lock
Cycle-to-cycle jitter, 24 MHz
Long-term Jitter, 24 MHz
FLL lock time
Measured at MCLK, XT1
crystal as reference
Measured at MCLK, XT1
crystal as reference
ms
表 5-6 lists the frequency characteristics of the DCO.
表 5-6. DCO Frequency
Over recommended operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
12.6
20.5
29.9
48.2
10.5
17.2
25.1
40.4
8.3
MAX UNIT
DCORSEL = 111b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
T
T
T
T
T
T
T
T
T
T
T
T
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
DCORSEL = 111b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
fDCO, 24MHz DCO frequency 24 MHz
MHz
DCORSEL = 111b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
DCORSEL = 111b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
DCORSEL = 110b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
DCORSEL = 110b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
fDCO, 20MHz DCO frequency 20 MHz
MHz
DCORSEL = 110b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
DCORSEL = 110b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
DCORSEL = 101b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
DCORSEL = 101b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
13.6
19.9
32.2
fDCO, 16MHz DCO frequency 16 MHz
MHz
DCORSEL = 101b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
DCORSEL = 101b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
版权 © 2018–2019, Texas Instruments Incorporated
Specifications
37
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
表 5-6. DCO Frequency (continued)
Over recommended operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
6.2
10.2
15
MAX UNIT
DCORSEL = 100b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
T
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
DCORSEL = 100b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
fDCO, 12MHz DCO frequency 12 MHz
MHz
DCORSEL = 100b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
DCORSEL = 100b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
24.3
4.2
6.9
10
DCORSEL = 011b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
DCORSEL = 011b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
fDCO, 8MHz DCO frequency 8 MHz
fDCO, 4MHz DCO frequency 4 MHz
fDCO, 2MHz DCO frequency 2 MHz
fDCO, 1MHz DCO frequency 1 MHz
MHz
MHz
MHz
MHz
DCORSEL = 011b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
DCORSEL = 011b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
16.4
2
DCORSEL = 010b,, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
DCORSEL = 010b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
3.4
5
DCORSEL = 010b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
DCORSEL = 010b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
8.2
1
DCORSEL = 001b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
DCORSEL = 001b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
1.7
2.5
4.2
0.5
0.85
1.2
2.1
DCORSEL = 001b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
DCORSEL = 001b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
DCORSEL = 000b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
DCORSEL = 000b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
DCORSEL = 000b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
DCORSEL = 000b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
38
Specifications
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
50
DCOFTRIM = 7
40
30
20
10
0
DCOFTRIM = 7
DCOFTRIM = 7
DCOFTRIM = 7
DCOFTRIM = 7
DCOFTRIM = 0
DCOFTRIM = 7
DCOFTRIM = 0
DCOFTRIM = 0
DCOFTRIM = 7
DCOFTRIM = 0
DCOFTRIM = 0
DCOFTRIM = 7
DCOFTRIM = 0
DCOFTRIM = 0
DCOFTRIM = 0
0
511
0
511
0
511
0
511
0
511
0
511
0
511
0
511
DCO
0
1
2
3
4
5
6
7
DCORSEL
(1MHz)
(2MHz)
(4MHz)
(8MHz)
(12MHz)
(16MHz)
(20MHz)
(24MHz)
图 5-6. Typical DCO Frequency
版权 © 2018–2019, Texas Instruments Incorporated
Specifications
39
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
表 5-7 lists the characteristics of the REFO.
表 5-7. REFO
over recommended operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
TA = 25°C, HP mode (REFLP = 0)
TA = 25°C, LP mode (REFLP = 1)
Measured at MCLK
VCC
MIN
TYP
15
MAX UNIT
REFO oscillator current
consumption
T
3.0 V
3.0 V
3.0 V
IREFO
µA
REFO oscillator current
consumption
T
T
T
T
T
T
T
T
1
REFO calibrated
frequency
32768
Hz
+3.5%
%/°C
fREFO
REFO absolute
calibrated tolerance
1.8 V to
3.6 V
–40°C to 105°C
–3.5%
40%
REFO frequency
temperature drift
dfREFO/dT
dfREFO/dVCC
fDC
Measured at MCLK(1)
3.0 V
0.01
1
REFO frequency supply
voltage drift
1.8 V to
3.6 V
Measured at MCLK at 25°C(2)
Measured at MCLK
%/V
1.8 V to
3.6 V
REFO duty cycle
50%
72
60%
40% to 60% duty cycle, HP mode
(REFLP = 0)
3.0 V
3.0 V
tSTART
REFO start-up time
µs
40% to 60% duty cycle, LP mode
(REFLP = 1)
75
(1) Calculated using the box method: (MAX(–40°C to 105°C) – MIN(–40°C to 105°C)) / MIN(–40°C to 105°C) / (105°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
表 5-8 lists the characteristics of the VLO.
表 5-8. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fVLO
VLO frequency
VLO frequency temperature drift
Measured at MCLK
Measured at MCLK(1)
T
T
3.0 V
3.0 V
10
kHz
dfVLO/dT
0.5
%/°C
1.8 V to
3.6 V
dfVLO/dVCC VLO frequency supply voltage drift
fVLO,DC Duty cycle
Measured at MCLK(2)
Measured at MCLK
T
T
4
%/V
3.0 V
50%
(1) Calculated using the box method: (MAX(–40°C to 105°C) – MIN(–40°C to 105°C)) / MIN(–40°C to 105°C) / (105°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
注
The VLO clock frequency is reduced by 15% (typical) when the device switches from active
mode to LPM3 or LPM4, because the reference changes. This lower frequency is not a
violation of the VLO specifications (see 表 5-8).
40
Specifications
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
表 5-9 lists the characteristics of the MODOSC.
表 5-9. Module Oscillator (MODOSC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
PARAMETER
VCC
MIN
TYP
MAX
UNIT
fMODOSC
MODOSC frequency
MODOSC frequency temperature drift(1)
T
T
3.0 V
3.0 V
3.0
3.8
4.6
MHz
fMODOSC/dT
0.102
%/℃
1.8 V to
3.6 V
fMODOSC/dVCC MODOSC frequency supply voltage drift
fMODOSC,DC Duty cycle
T
T
1.17
50%
%/V
3.0 V
40%
60%
(1) Calculated using the box method: (MAX(–40°C to 105°C) – MIN(–40°C to 105°C)) / MIN(–40°C to 105°C) / (105°C – (–40°C))
5.12.4 Internal Shared Reference
表 5-10 lists the characteristics of the internal shared reference.
表 5-10. Internal Shared Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
TJ = 30℃
VCC
MIN
TYP
788
MAX UNIT
Temperature sensor
voltage
2.0 V,
3.0 V
VSENSOR
T
mV
mV/°C
V
Temperature sensor
coefficient
TCSENSOR
VeCOMP, LP
VREF+, Output
TJ = 30℃
TJ = 30℃
TJ = 30℃
T
T
T
2.32
1.20
1.20
Low-power threshold
for eCOMP
2.0 V,
3.0 V
Positive output
reference at VREF+ pin
2.0 V,
3.0 V
V
The following parameters are for the 1.5-V, 2.0-V, and 2.5-V internal reference only and cannot be output to the VREF+ pin.
REFVSEL = {2} for 2.5 V,
INTREFEN = 1
T
T
T
T
3.0 V
2.5 V
1.8 V
2.5
2.0
1.5
30
±1.5%
Positive built-in
REFVSEL = {1} for 2.0 V,
INTREFEN = 1
VREF+, built-in
reference voltage as
internal reference
±1.5%
±1.8%
130
V
REFVSEL = {0} for 1.5 V,
INTREFEN = 1
From 0.1 Hz to 10 Hz,
REFVSEL = {0}
(1)
Noise
RMS noise at VREF
µV
TA = 25 °C , ADC ON,
REFVSEL = {0}, INTREFEN = 1,
EXTREFEN=0
VREF ADC BUF_INT
buffer offset(2)
VOS_BUF_INT
T
T
–16
–16
+16
+16
mV
TA = 25 °C, REFVSEL = {0} ,
EXTREFEN = 1,
INTREFEN = 1 or ADC ON
VREF ADC BUF_EXT
buffer offset(3)
VOS_BUF_EXT
DVCC(min)
IREF+
mV
V
REFVSEL = {0} for 1.5 V
T
T
T
1.8
2.2
2.7
DVCC minimum
voltage, Positive built-in REFVSEL = {1} for 2.0 V
reference active
REFVSEL = {2} for 2.5 V
Operating supply
current into DVCC
INTREFEN = 1
T
T
3 V
3 V
19
26
µA
µA
terminal(4)
Operating supply
ADC ON, EXTREFEN = 0,
REFVSEL = {0, 1, 2}
IREF+_ADC_BUF current into DVCC
247
400
terminal(4)
(1) Internal reference noise affects ADC performance when ADC uses internal reference.
(2) Buffer offset affects ADC gain error and thus total unadjusted error.
(3) Buffer offset affects ADC gain error and thus total unadjusted error.
(4) The internal reference current is supplied through the DVCC terminal.
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Specifications
41
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
表 5-10. Internal Shared Reference (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
REFVSEL = {0, 1, 2},
DVCC = DVCC(min) for each
reference level,
VREF maximum load
current, VREF+
terminal
IO(VREF+)
T
3 V
–1000
+10
µA
INTREFEN = EXTREFEN = 1
REFVSEL = {0, 1, 2},
IO(VREF+) = +10 µA or –1000 µA,
DVCC = DVCC(min) for each
reference level,
ΔVout/
ΔIo(VREF+)
Load-current regulation,
VREF+ terminal
T
3 V
1500 µV/mA
INTREFEN = EXTREFEN = 1
Capacitance at VREF+
and VREF- terminals
CVREF+/-
INTREFEN = EXTREFEN = 1
T
T
3 V
3 V
0
100
pF
REFVSEL = {0, 1, 2},
Temperature coefficient
of built-in reference
TCREF+
INTREFEN = EXTREFEN = 1,
24
50 ppm/K
TA = –40°C to 105°C(5)
DVCC = DVCC (min) to DVCC(max)
TA = 25°C, REFVSEL = {0, 1, 2},
INTREFEN = EXTREFEN = 1
,
Power supply rejection
ratio (DC)
PSRR_DC
PSRR_AC
tSETTLE
T
T
T
3 V
3 V
3 V
100
3.0
75
400
µV/V
mV/V
µs
Power supply rejection
ratio (ac)
dDVCC= 0.1 V at 1 kHz
DVCC = DVCC(min) to DVCC(max)
REFVSEL = {0, 1, 2},
INTREFEN = 0 → 1
,
Settling time of
100
reference voltage(6)
(5) Calculated using the box method: (MAX(–40°C to 105°C) – MIN(–40°C to 105°C)) / MIN(–40°C to 105°C) / (105°C – (–40°C))
(6) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
42
Specifications
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
5.12.5 General-Purpose I/Os
表 5-11 lists the characteristics of the digital inputs.
表 5-11. Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
T
T
T
T
T
T
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
0.90
1.35
0.50
0.75
0.3
1.50
V
VIT+
VIT–
Vhys
Positive-going input threshold voltage
2.25
1.10
V
Negative-going input threshold voltage
1.65
0.8
V
Input voltage hysteresis (VIT+ – VIT–
Pullup or pulldown resistor
)
0.4
1.2
For pullup: VIN = VSS
For pulldown: VIN = VCC
,
RPull
CI,dig
CI,ana
T
T
T
20
35
3
50
kΩ
pF
pF
Input capacitance, digital only port pins
VIN = VSS or VCC
Input capacitance, port pins with shared
analog functions
VIN = VSS or VCC
5
2.0 V,
3.0 V
Ilkg(Px.y) High-impedance leakage current(1)(2)
T
T
–30
50
+30
nA
ns
Ports with interrupt
capability (see block
diagram and terminal
function descriptions)
External interrupt timing (external trigger
2.0 V,
3.0 V
t(int)
pulse duration to set interrupt flag)(3)
(1) The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
(3) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It can be set by trigger signals
shorter than t(int)
.
表 5-12 lists the characteristics of the digital outputs.
表 5-12. Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA(1)
I(OHmax) = –5 mA(1)
I(OLmax) = 3 mA(1)
I(OLmax) = 5 mA(1)
VCC
MIN
TYP
MAX UNIT
T
T
T
T
T
T
T
T
T
T
T
T
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
1.4
2.4
0.0
0.0
16
2.0
V
VOH
High-level output voltage
3.0
0.60
V
VOL
Low-level output voltage
0.60
Applicable to all IO ports, CL = 20
pF(2)
16
fPort_CLK Clock output frequency
MHz
24
IOs multiplexed with MCLK and
SMCLK, CL = 10 pF(2)
24
10
7
Port output rise time, digital
only port pins
trise,dig
CL = 20 pF
CL = 20 pF
ns
ns
10
5
Port output fall time, digital
only port pins
tfall,dig
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
(2) The port can output frequencies at least up to the specified limit and might support higher frequencies.
版权 © 2018–2019, Texas Instruments Incorporated
Specifications
43
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
5.12.6 Digital I/O Typical Characteristics
25
20
15
10
5
10
7.5
5
T
T
T
T
A
A
A
A
= -40°C
= 25°C
= 85°C
= 105°C
T
T
T
T
A
A
A
A
= -40°C
= 25°C
= 85°C
= 105°C
2.5
0
0
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
0
0.5
1
1.5
2
2.5
3
Low-Level Output Voltage (V)
Low-Level Output Voltage (V)
DVCC = 2 V
DVCC = 3 V
图 5-7. Typical Low-Level Output Current
图 5-8. Typical Low-Level Output Current
vs
vs
Low-Level Output Voltage
Low-Level Output Voltage
0
-2.5
-5
0
-5
T
T
T
T
A
A
A
A
= -40°C
= 25°C
= 85°C
= 105°C
T
T
T
T
A
A
A
A
= -40°C
= 25°C
= 85°C
= 105°C
-10
-15
-20
-25
-30
-
-7.5
-10
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
0
0.5
1
1.5
2
2.5
3
High-Level Output Voltage (V)
High-Level Output Voltage (V)
DVCC = 3 V
DVCC = 2 V
图 5-9. Typical High-Level Output Current
图 5-10. Typical High-Level Output Current
vs
vs
High-Level Output Voltage
High-Level Output Voltage
44
Specifications
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
5.12.7 Timer_B
表 5-13 lists the frequency characteristics of Timer_B.
表 5-13. Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK or ACLK,
External: TBCLK,
Duty cycle = 50% ±10%
2.0 V,
3.0 V
fTB
Timer_B input clock frequency
Timer_B capture timing
T
24
MHz
ns
All capture inputs, minimum pulse
duration required for capture
2.0 V,
3.0 V
tTB,cap
T
20
5.12.8 eUSCI
表 5-14 lists the supported frequencies of the eUSCI in UART mode.
表 5-14. eUSCI (UART Mode) Clock Frequencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK or MODCLK,
External: UCLK,
Duty cycle = 50% ±10%
2.0 V,
3.0 V
feUSCI
eUSCI input clock frequency
T
24
5
MHz
MHz
BITCLK clock frequency
(equals baud rate in Mbaud)
2.0 V,
3.0 V
fBITCLK
T
表 5-15 lists the switching characteristics of the eUSCI in UART mode.
表 5-15. eUSCI (UART Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
UCGLITx = 0
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
12
40
2.0 V,
3.0 V
(1)
tt
UART receive deglitch time
T
ns
68
110
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To make sure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
版权 © 2018–2019, Texas Instruments Incorporated
Specifications
45
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
表 5-16 lists the supported frequencies of the eUSCI in SPI master mode.
表 5-16. eUSCI (SPI Master Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK,
Duty cycle = 50% ±10%
feUSCI
eUSCI input clock frequency
T
8
MHz
表 5-17 lists the switching characteristics of the eUSCI in SPI master mode.
表 5-17. eUSCI (SPI Master Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
VCC
MIN
1
TYP
MAX
UNIT
UCSTEM = 1,
UCMODEx = 01 or 10
UCxCLK
cycles
tSTE,LEAD
tSTE,LAG
tSU,MI
STE lead time, STE active to clock
T
STE lag time, Last clock to STE
inactive
UCSTEM = 1,
UCMODEx = 01 or 10
UCxCLK
cycles
T
T
1
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
60
42
0
SOMI input data setup time
SOMI input data hold time
ns
ns
tHD,MI
T
T
T
0
UCLK edge to SIMO
valid,
CL = 20 pF
20
20
tVALID,MO
SIMO output data valid time(2)
SIMO output data hold time(3)
ns
ns
3.0 V
2.0 V
3.0 V
–9.0
–6.0
tHD,MO
CL = 20 pF
(1) fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)
)
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in 图 5-11 and 图 5-12.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in 图 5-11
and 图 5-12.
46
Specifications
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
图 5-11. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLOW/HIGH
tLOW/HIGH
tHD,MI
tSU,MI
SOMI
tVALID,MO
SIMO
图 5-12. SPI Master Mode, CKPH = 1
版权 © 2018–2019, Texas Instruments Incorporated
Specifications
47
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
表 5-18 lists the switching characteristics of the eUSCI in SPI slave mode.
表 5-18. eUSCI (SPI Slave Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
55
45
20
20
tSTE,LEAD STE lead time, STE active to clock
T
ns
STE lag time, last clock to STE
tSTE,LAG
inactive
T
T
T
T
T
T
T
ns
65
ns
40
STE access time, STE active to SOMI
tSTE,ACC
data out
40
ns
35
STE disable time, STE inactive to
tSTE,DIS
SOMI high impedance
10
6
tSU,SI
SIMO input data setup time
SIMO input data hold time
ns
ns
12
12
tHD,SI
69
ns
42
UCLK edge to SOMI valid,
CL = 20 pF
tVALID,SO SOMI output data valid time(2)
5
5
(3)
tHD,SO
SOMI output data hold time
CL = 20 pF
ns
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)
)
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in 图 5-13 and 图 5-14.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in 图 5-13 and
图 5-14.
48
Specifications
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tSU,SIMO
tHD,SIMO
tLOW/HIGH
tLOW/HIGH
SIMO
tACC
tVALID,SOMI
tDIS
SOMI
图 5-13. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tACC
tDIS
tVALID,SO
SOMI
图 5-14. SPI Slave Mode, CKPH = 1
版权 © 2018–2019, Texas Instruments Incorporated
Specifications
49
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
表 5-19 lists the switching characteristics of the eUSCI in I2C mode.
表 5-19. eUSCI (I2C Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see 图 5-15)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Internal: SMCLK or MODCLK,
External: UCLK
Duty cycle = 50% ±10%
2.0 V,
3.0 V
feUSCI
eUSCI input clock frequency
T
24
MHz
2.0 V,
3.0 V
fSCL
SCL clock frequency
T
T
0
400
kHz
µs
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
4.0
0.6
4.7
0.6
2.0 V,
3.0 V
tHD,STA
Hold time (repeated) START
Setup time for a repeated
START
2.0 V,
3.0 V
tSU,STA
T
µs
2.0 V,
3.0 V
tHD,DAT
tSU,DAT
tSU,STO
Data hold time
Data setup time
T
T
0
ns
ns
2.0 V,
3.0 V
250
fSCL = 100 kHz
fSCL > 100 kHz
UCGLITx = 0
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
UCCLTOx = 1
UCCLTOx = 2
UCCLTOx = 3
4.0
0.6
50
2.0 V,
3.0 V
Setup time for STOP
T
T
µs
ns
600
300
150
75
25
Pulse duration of spikes
suppressed by input filter
2.0 V,
3.0 V
tSP
12.5
6.3
36
40
44
2.0 V,
3.0 V
tTIMEOUT Clock low time-out
T
ms
tHD,STA
tSU,STA
tHD,STA
tBUF
SDA
SCL
tLOW
tHIGH
tSP
tSU,DAT
tSU,STO
tHD,DAT
图 5-15. I2C Mode Timing
50
Specifications
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
5.12.9 ADC
表 5-20 lists the input characteristics of the ADC.
表 5-20. ADC, Power Supply and Input Range Conditions
over operating free-air temperature range (unless otherwise noted)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
DVCC ADC supply voltage(1)
T
T
2.0
0
3.6
V
V
V(Ax)
Analog input voltage range
All ADC pins
DVCC
Operating supply current into
DVCC terminal, reference
current not included, repeat-
single-channel mode
fADCCLK = 5 MHz, ADCON = 1,
REFON = 0, SHT0 = 0,
SHT1 = 0, ADCDIV = 0,
ADCCONSEQx = 10b
2.0 V
3.0 V
185
280
IADC
T
µA
Only one terminal Ax can be
selected at one time from the
pad to the ADC capacitor
CI
RI
Input capacitance
T
T
2.2 V
4.5
5.5
2
pF
array, including wiring and pad
Input MUX ON resistance
DVCC = 2 V, 0 V ≤ VAx ≤ DVCC
kΩ
(1) This specifies the ADC functional range with 8-bit resolution at 8-bit ENOB. 表 5-22 specifies 10- and 12-bit linearity parameters for
better ENOB requirements.
表 5-21 lists the timing parameters of the ADC.
表 5-21. ADC, Timing Parameters
over operating free-air temperature range (unless otherwise noted)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
6.0
UNIT
ADC clock
frequency
ADC clock, 10-bit mode
2.4 V to
3.6 V
fADCCLK
T
MHz
ADC clock, 12-bit mode
4.4
The error in a conversion started after
tADCON is less than ±0.5 LSB,
Reference and input signal already settled
Turn-on settling
time of the ADC
tSettling
T
T
100
ns
µs
RS = 1000 Ω, RI = 4000 Ω,
CI = 5.5 pF, Cexternal = 8.0 pF,
Approximately 7.62 Tau (t) are required for
an error of less than ±0.5 LSB, 10-bit
mode(2)
2.4 V to
3.6 V
0.52
tSample Sampling time(1)
RS = 1000 Ω, RI = 4000 Ω,
CI = 5.5 pF, Cexternal = 8.0 pF,
Approximately 9.01 Tau (t) are required for
an error of less than ±0.5 LSB, 12-bit
mode(2)
2.4 V to
3.6 V
T
0.61
(1) This excludes the ADC conversion time. The ADC conversion time is specified as (N + 2) × 1/fADCCLK
.
(2) tSample = ln(2n+1) × τ, where n = ADC resolution, τ = (RI + RS) × CI
版权 © 2018–2019, Texas Instruments Incorporated
Specifications
51
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
表 5-22 lists the linearity parameters of the ADC.
表 5-22. ADC, Linearity Parameters
over operating free-air temperature range (unless otherwise noted)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Integral linearity error(12-bit mode)
Integral linearity error (10-bit mode)
Differential linearity error(12-bit mode)
Differential linearity error (10-bit mode)
Offset error(12-bit mode)
Veref+ reference
Veref+ reference
Veref+ reference
Veref+ reference
Veref+ reference
Veref+ reference
Veref+ as reference
Veref+ as reference
Veref+ as reference
Veref+ as reference
–2.5
–2
2.5
LSB
2
2.4 V to
3.6 V
EI
T
–1
1
2.4 V to
3.6 V
ED
EO
EG
ET
T
T
T
T
LSB
1
–1
–1.5
–6.0
–3.0
–1.5
–4.0
–2.0
1.5
mV
6.0
2.4 V to
3.6 V
Offset error (10-bit mode)
Gain error (12-bit mode)
3.0
2.4 V to
3.6 V
LSB
1.5
Gain error (10-bit mode)
Total unadjusted error (12-bit mode)
Total unadjusted error (10-bit mode)
4.0
2.4 V to
3.6 V
LSB
2.0
52
Specifications
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
5.12.10 Enhanced Comparator (eCOMP)
表 5-23 lists the characteristics of eCOMP0.
表 5-23. eCOMP0
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VCC
VIC
Supply voltage
T
T
2.0
0
3.6
V
V
Common mode input range
VCC
CPEN = 1, CPHSEL= 00
0
10
20
30
CPEN = 1, CPHSEL= 01
VHYS
DC input hysteresis
T
T
mV
CPEN = 1, CPHSEL= 10
CPEN = 1, CPHSEL= 11
CPEN = 1, CPMSEL = 0
–30
–40
+30
+40
35
VOFFSET
Input offset voltage
mV
µA
CPEN = 1, CPMSEL = 1
VIC = VCC/2, CPEN = 1, CPMSEL = 0
VIC = VCC/2, CPEN = 1, CPMSEL = 1
24
1.6
1
Quiescent current draw from
VCC, only Comparator
ICOMP
CIN
T
T
T
5
Input channel capacitance(1)
pF
kΩ
On (switch closed)
Off (switch open)
10
20
1
Input channel series
resistance
RIN
50
MΩ
CPMSEL = 0, CPFLT = 0,
Overdrive = 20 mV
Propagation delay, response
time
tPD
T
T
µs
µs
CPMSEL = 1, CPFLT = 0,
Overdrive = 20 mV
3.2
8.5
1.4
CPEN = 0→1, CPMSEL = 0,
V+ and V- from pads, Overdrive = 20 mV
tEN_CP
Comparator enable time
CPEN = 0→1, CPMSEL = 1,
V+ and V- from pads, Overdrive = 20 mV
CPEN = 0→1, CPDACEN = 0→1,
CPMSEL = 0, CPDACREFS = 1,
CPDACBUF1 = 0F, Overdrive = 20 mV
8.5
Comparator with reference
DAC enable time
tEN_CP_DAC
T
T
µs
µs
CPEN = 0→1, CPDACEN = 0→1,
CPMSEL = 1,
CPDACREFS = 1, CPDACBUF1 = 0F,
Overdrive = 20 mV
101
CPMSEL = 0, CPFLTDY = 00,
Overdrive = 20 mV, CPFLT = 1
0.7
1.1
1.9
3.4
CPMSEL = 0, CPFLTDY = 01,
Overdrive = 20 mV, CPFLT = 1
Propagation delay with
analog filter active
tFDLY
CPMSEL = 0, CPFLTDY = 10,
Overdrive = 20 mV, CPFLT = 1
CPMSEL = 0, CPFLTDY = 11,
Overdrive = 20 mV, CPFLT = 1
INL
Integral nonlinearity
T
T
–0.5
–0.5
0.5
0.5
LSB
LSB
DNL
Differential nonlinearity
(1) For details on the eCOMP CIN, model , see 图 5-16.
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Specifications
53
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
表 5-24 lists the characteristics of eCOMP1.
表 5-24. eCOMP1
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VCC
VIC
Supply voltage
T
T
2.0
0
3.6
V
V
Common mode input range
VCC
CPEN = 1, CPHSEL= 00
0
10
20
30
CPEN = 1, CPHSEL= 01
VHYS
DC input hysteresis
T
T
mV
CPEN = 1, CPHSEL= 10
CPEN = 1, CPHSEL= 11
CPEN = 1, CPMSEL = 0
–30
–40
+30
+40
209
30
VOFFSET
Input offset voltage
mV
µA
CPEN = 1, CPMSEL = 1
VIC = VCC/2, CPEN = 1, CPMSEL = 0
VIC = VCC/2, CPEN = 1, CPMSEL = 1
162
20
1
Quiescent current draw from
VCC, only Comparator
ICOMP
CIN
T
T
T
Input channel capacitance(1)
pF
kΩ
On (switch closed)
Off (switch open)
1
5
RIN
Input channel series resistance
50
MΩ
CPMSEL = 0, CPFLT = 0,
Overdrive = 20 mV, DVCC = 3.0 V
0.1
Propagation delay, response
time
tPD
T
T
µs
µs
CPMSEL = 1, CPFLT = 0,
Overdrive = 20 mV
0.32
8.5
CPEN = 0→1, CPMSEL = 0,
V+ and V- from pads, Overdrive = 20 mV
tEN_CP
Comparator enable time
CPEN = 0→1, CPMSEL = 1,
V+ and V- from pads, Overdrive = 20 mV
4.8
CPEN = 0→1, CPDACEN = 0→1,
CPMSEL = 0, CPDACREFS = 1,
CPDACBUF1 = 0F, Overdrive = 20 mV
8.5
Comparator with reference DAC
enable time
tEN_CP_DAC
T
T
µs
ns
CPEN = 0→1, CPDACEN = 0→1,
CPMSEL = 1, CPDACREFS = 1,
CPDACBUF1 = 0F, Overdrive = 20 mV
101
CPMSEL = 0, CPFLTDY = 00,
Overdrive = 20 mV, CPFLT = 1
150
350
CPMSEL = 0, CPFLTDY = 01,
Overdrive = 20 mV, CPFLT = 1
Propagation delay with analog
filter active
tFDLY
CPMSEL = 0, CPFLTDY = 10,
Overdrive = 20 mV, CPFLT = 1
1000
1900
CPMSEL = 0, CPFLTDY = 11,
Overdrive = 20 mV, CPFLT = 1
INL
Integral nonlinearity
T
T
–0.5
–0.5
0.5
0.5
LSB
LSB
DNL
Differential nonlinearity
(1) For details on the eCOMP CIN, model, see 图 5-16.
MSP430
VI = External source voltage
RS = External source resistance
RI = Internal MUX-on input resistance
CIN = Input capacitance
CPAD = PAD capacitance
RS
RI
VI
VC
CPext = Parasitic capacitance, external
VC = Capacitance-charging voltage
Cpext
CPAD
CIN
图 5-16. eCOMP Input Circuit
54
Specifications
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
5.12.11 Smart Analog Combo (SAC) (MSP430FR235x Devices Only)
表 5-25 lists the characteristics of the SAC OA.
表 5-25. SAC, OA
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VCC
VOS
Supply voltage
T
T
2.0
–5
3.6
5
V
Input offset voltage
mV
OAPM = 0(1)
OAPM = 1(1)
3
5
dVOS/dT
Offset drift
T
µV/℃
IB
Input bias current
T
T
50
pA
V
VCC
0.1
+
VCM
Input voltage range
–0.1
OAPM = 0
OAPM = 1
350
120
IIDD
Quiescent current
T
T
µA
µV
f = 0.1 Hz to 10 Hz,
Vin = VCC/2, OAPM = 0
Input noise voltage
40
ENI
f = 1 kHz, Vin = VCC/2, OAPM = 0
f = 10 kHz, Vin = VCC/2, OAPM = 0
OAPM = 0
64
28
70
80
70
80
2.8
1.0
100
100
65
3
Input noise voltage density
nV/√Hz
CMRR
PSRR
GBW
Common-mode rejection ratio
Power supply rejection ratio
Gain-bandwidth
T
T
T
dB
dB
OAPM = 1
OAPM = 0
OAPM = 1
OAPM = 0
MHz
OAPM = 1
OAPM = 0
AOL
Open-loop voltage gain
Phase margin
T
T
T
dB
deg
V/µs
OAPM = 1
φM
CL = 50 pF , RL = 2 kΩ
CL = 50 pF, OAPM = 0, step = 1
CL = 50 pF, OAPM = 1, step = 1
Common mode
Positive slew rate
Input capacitance
1
Cin
VO
T
T
3
pF
Voltage output swing from
supply rails
RL = 10 kΩ
40
1
100
mV
To 0.1% final value, G = +1, 1-V setup
CL = 50 pF, OAPM = 0
tST
OA settling time
T
T
µs
To 0.1% final value, G = +1, 1-V setup
CL = 50 pF, OAPM = 1
4.5
THD
Total harmonic distortion
All gains
–60
dB
(1) Calculated using the box method: (MAX(–40°C to 105°C) – MIN(–40°C to 105°C)) / MIN(–40°C to 105°C) / (105°C – (–40°C))
Specifications
版权 © 2018–2019, Texas Instruments Incorporated
55
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
表 5-25. SAC, OA (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Gain = 1, inverting mode, follower mode
Gain = 2, noninverting mode
Gain = 2, inverting mode
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0.99
1.98
1
2
1.01
2.02
1.98
2
2.02
Gain = 3, noninverting mode
Gain = 4, inverting mode
2.97
3
3.03
3.96
4
4.04
Gain = 5, noninverting mode
Gain = 8, inverting mode
4.95
5
5.05
7.92
8
8.08
Gclose loop PGA closed-loop gain
Gain = 9, noninverting mode
Gain = 16, inverting mode
Gain = 17, noninverting mode
Gain = 25, inverting mode
Gain = 26, noninverting mode
Gain = 32, inverting mode
Gain = 33, noninverting mode
8.91
9
9.09
15.84
16.83
24.75
25.74
31.68
32.67
16
17
25
26
32
33
16.16
17.17
25.25
26.26
32.32
33.33
表 5-26 lists the characteristics of the SAC DAC.
表 5-26. SAC, DAC
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VCC
Supply voltage
T
2.4
3.6
V
Quiescent current of resistor
ladder into VREF_INT
IIDDR
T
T
5
µA
Low-power mode
0.2
1
IIOAD
OA + DAC output load current
mA
µs
High-power mode
OAPM = 1
OAPM = 0
OAPM = 1
477
160
10
OA + DAC settling time, full
scale
DACDAT =
0x80h→0xF7Fh→0x80h
tST(FS)
T
T
DACDAT =
0x3F8h→408h→0x3F8h
or
2
2
OA + DAC settling time, code
to code
tST(C-C)
µs
OAPM = 0
5
DACDAT =
0xBF8h→C08h→0xBF8h
INL
OA + DAC integral nonlinearity DACSREF = DVCC, DVCC = 3.0 V
T
T
–4
–1
0
4
1
LSB
LSB
OA + DAC differential
DACSREF = DVCC, DVCC = 3.0 V
nonlinearity
DNL
No load, DACSREF = DVCC, DACDAT = 0
0.005
0.1
RLOAD = 3 kΩ , DACSREF = DVCC,
0
VOUT
Output voltage range
DACDAT = 0
T
V
RLOAD = 3 kΩ , DACSREF = DVCC,
DACDAT = 0FFFh
DVCC –
0.1
DVCC
56
Specifications
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
5.12.12 FRAM
表 5-27 lists the characteristics of the FRAM.
表 5-27. FRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Read and write endurance
T
T
T
T
T
T
T
T
T
T
1015
100
40
cycles
TJ = 25°C
TJ = 70°C
TJ = 115°C
tRetention
Data retention duration
years
10
(1)
(1)
(1)
IWRITE
IERASE
tWRITE
Current to write into FRAM
Erase current
IREAD
IREAD
IREAD
nA
nA
ns
N/A(2)
N/A(2)
N/A(2)
(3)
(3)
(3)
Write time
tREAD
tREAD
tREAD
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
NWAITSx = 0
NWAITSx = 1
NWAITSx = 2
1/fSYSTEM
2/fSYSTEM
3/fSYSTEM
1/fSYSTEM
2/fSYSTEM
3/fSYSTEM
1/fSYSTEM
2/fSYSTEM
3/fSYSTEM
TREAD
Read time
ns
(1) Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read
current IREAD is included in the active mode current consumption IAM, FRAM parameters.
(2) FRAM does not require a special erase sequence.
(3) Writing into FRAM is as fast as reading.
(4) The maximum read (and write) speed is specified by fSYSTEM using the appropriate wait state settings (NWAITSx).
版权 © 2018–2019, Texas Instruments Incorporated
Specifications
57
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
5.12.13 Emulation and Debug
表 5-28 lists the characteristics of the SBW interface.
表 5-28. JTAG, Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see 图 5-17)
DEVICE
GRADE
PARAMETER
Spy-Bi-Wire input frequency
VCC
MIN
0
TYP
MAX UNIT
2.0 V,
3.0 V
fSBW
T
8
MHz
µs
2.0 V,
3.0 V
tSBW,Low
tSU,SBWTDIO
tHD,SBWTDIO
tValid,SBWTDIO
tSBW, En
Spy-Bi-Wire low clock pulse duration
T
T
T
T
T
T
T
0.028
4
15
SBWTDIO setup time (before falling edge of SBWTCK in
TMS and TDI slot Spy-Bi-Wire)
2.0 V,
3.0 V
ns
SBWTDIO hold time (after rising edge of SBWTCK in TMS
and TDI slot Spy-Bi-Wire)
2.0 V,
3.0 V
19
ns
SBWTDIO data valid time (after falling edge of SBWTCK in
TDO slot Spy-Bi-Wire)
2.0 V,
3.0 V
31
110
100
50
ns
Spy-Bi-Wire enable time (TEST high to acceptance of first
2.0 V,
3.0 V
µs
(1)
clock edge)
2.0 V,
3.0 V
tSBW,Ret
Spy-Bi-Wire return to normal operation time(2)
Internal pulldown resistance on TEST
15
20
µs
2.0 V,
3.0 V
Rinternal
35
kΩ
(1) Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) Maximum tSBW,Rst time after pulling or releasing the TEST/SBWTCK pin low, the Spy-Bi-Wire pins revert from their Spy-Bi-Wire function
to their application function. This time applies only if the Spy-Bi-Wire mode was selected.
tSBW,EN
tSBW,Low
1/fSBW
tSBW,High
tSBW,Ret
TEST/SBWTCK
tEN,SBWTDIO
tValid,SBWTDIO
RST/NMI/SBWTDIO
tSU,SBWTDIO
tHD,SBWTDIO
图 5-17. JTAG Spy-Bi-Wire Timing
58
Specifications
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
表 5-29 lists the characteristics of the 4-wire JTAG interface.
表 5-29. JTAG, 4-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see 图 5-18)
DEVICE
GRADE
PARAMETER
VCC
MIN
0
TYP
MAX UNIT
2.0 V,
3.0 V
(1)
fTCK
TCK input frequency
I, T
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
kΩ
2.0 V,
3.0 V
tTCK,Low
tTCK,high
tSU,TMS
tHD,TMS
tSU,TDI
Spy-Bi-Wire low clock pulse duration
Spy-Bi-Wire high clock pulse duration
TMS setup time (before rising edge of TCK)
TMS hold time (after rising edge of TCK)
TDI setup time (before rising edge of TCK)
TDI hold time (after rising edge of TCK)
I, T
I, T
I, T
I, T
I, T
I, T
I, T
I, T
I, T
I, T
I, T
15
15
11
3
2.0 V,
3.0 V
2.0 V,
3.0 V
2.0 V,
3.0 V
2.0 V,
3.0 V
13
5
2.0 V,
3.0 V
tHD,TDI
TDO high impedance to valid output time (after falling edge of
TCK)
2.0 V,
3.0 V
tz-Valid,TDO
tValid,TDO
tValid-Z,TDO
tJTAG,Ret
Rinternal
26
26
2.0 V,
3.0 V
TDO to new valid output time (after falling edge of TCK)
TDO valid to high impedance output time (after falling edge of
TCK)
2.0 V,
3.0 V
26
2.0 V,
3.0 V
Spy-Bi-Wire return to normal operation time
Internal pulldown resistance on TEST
15
20
100
50
2.0 V,
3.0 V
35
(1) Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
版权 © 2018–2019, Texas Instruments Incorporated
Specifications
59
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
1/fTCK
tTCK,Low
tTCK,High
TCK
TMS
tSU,TMS
tHD,TMS
TDI
(or TDO as TDI)
tSU,TDI
tHD,TDI
TDO
tZ-Valid,TDO
tValid,TDO
tValid-Z,TDO
tJTAG,Ret
TEST
图 5-18. JTAG 4-Wire Timing
60
Specifications
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
6 Detailed Description
6.1 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-
register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter (PC), stack pointer (SP), status register
(SR), and constant generator (CG), respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
6.2 Operating Modes
The MCUs have one active mode and several software-selectable low-power modes of operation. An
interrupt event can wake the device from a low-power mode (LPM0, LPM3, or LPM4), service the request,
and return to the low-power mode on return from the interrupt program. Low-power modes LPM3.5 and
LPM4.5 disable the core supply to minimize power consumption.
表 6-1. Operating Modes
AM
LPM0
CPU OFF
24 MHz
LPM3
LPM4
OFF
0
LPM3.5
LPM4.5
SHUTDOWN
0
MODE
Maximum system clock
ACTIVE
MODE
ONLY RTC
COUNTER
STANDBY
24 MHz
40 kHz
40 kHz
1.43 µA with
142 µA/MHz 40 µA/MHz RTC counter
only in LFXT
620 nA with
RTC counter
only in LFXT
0.82 µA
without SVS
42 nA
without SVS
Power consumption at 25°C, 3 V
Wake-up time
N/A
Instant
10 µs
10 µs
I/O
350 µs
350 µs
I/O
RTC counter,
I/O
Wake-up events
N/A
All
All
Full
regulation
Full
regulation
Partial power Partial power Partial power
Regulator
Power down
down
Optional
On
down
Optional
On
down
Optional
On
Power
SVS
On
On
On
Optional
On
Brownout
MCLK
SMCLK
FLL
On
Active
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
On
Off
Off
Off
Off
Off
Active
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Off
Off
Off
Off
Off
Off
Off
Off
Off
DCO
Off
Off
Off
Off
MODCLK
Off
Off
Off
Off
Clock(1)
REFO
Optional
Active
Off
Off
Off
Off
ACLK
Off
Off
Off
XT1HFCLK(2)
XT1LFCLK
VLOCLK
CPU
Off
Off
Off
Optional
Optional
Off
Off
Optional
Optional
Off
Off
Off
Off
Off
Off
FRAM
On
On
Off
Off
Off
Off
Core
RAM
On
On
On
On
Off
Off
Backup Memory(3)
On
On
On
On
On
Off
(1) The status shown for LPM4 applies to internal clocks only.
(2) HFXT must be disabled before entering into LPM3, LPM4, or LPMx.5 mode.
(3) Backup memory contains one 32-byte register in the peripheral memory space. See 表 6-33 and 表 6-54 for its memory allocation.
版权 © 2018–2019, Texas Instruments Incorporated
Detailed Description
61
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
表 6-1. Operating Modes (continued)
AM
LPM0
LPM3
LPM4
OFF
LPM3.5
LPM4.5
MODE
ACTIVE
MODE
ONLY RTC
COUNTER
CPU OFF
STANDBY
SHUTDOWN
Timer0_B3
Timer1_B3
Timer2_B3
Timer3_B7
WDT
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
On
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
eUSCI_A0
eUSCI_A1
eUSCI_B0
eUSCI_B1
CRC
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Peripherals
ICC
Off
Off
Off
Off
MPY32
Off
Off
Off
Off
ADC
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
State held
Off
Off
Off
eCOMP0
eCOMP1
Optional
Optional
Optional
Optional
Optional
Optional
Optional
State held
Off
Off
Off
Off
(4)
SAC0
Off
Off
SAC1(4)
SAC2(4)
SAC3(4)
Off
Off
Off
Off
Off
Off
RTC Counter
General digital input/output
Optional
State held
Off
I/O
State held
(4) MSP430FR235x devices only
注
XT1CLK and VLOCLK can be active during LPM4 if requested by low-frequency peripherals.
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6.3 Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see 表
6-2). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
表 6-2. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
System Reset
Power up, brownout, supply supervisor
External reset RST
Watchdog time-out, key violation
FRAM uncorrectable bit error detection
Software POR, BOR
SVSHIFG
PMMRSTIFG
WDTIFG
Reset
FFFEh
63, Highest
PMMPORIFG, PMMBORIFG
SYSRSTIV
FLLULPUC
FLL unlock error
System NMI
Vacant memory access
JTAG mailbox
FRAM access time error
FRAM bit-error detection
VMAIFG
JMBINIFG, JMBOUTIFG
CBDIFG, UBDIFG
Non-Maskable
Non-Maskable
FFFCh
FFFAh
62
61
User NMI
External NMI
Oscillator fault
NMIIFG
OFIFG
Timer0_B3
Timer0_B3
Timer1_B3
Timer1_B3
Timer2_B3
Timer2_B3
Timer3_B7
TB0CCR0 CCIFG0
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
FFF8h
FFF6h
FFF4h
FFF2h
FFF0h
FFEEh
FFECh
60
59
58
57
56
55
54
TB0CCR1 CCIFG1, TB0CCR2
CCIFG2, TB0IFG (TB0IV)
TB1CCR0 CCIFG0
TB1CCR1 CCIFG1, TB1CCR2
CCIFG2, TB1IFG (TB1IV)
TB2CCR0 CCIFG0
TB2CCR1 CCIFG1, TB2CCR2
CCIFG2, TB2IFG (TB2IV)
TB3CCR0 CCIFG0
TB3CCR1 CCIFG1, TB3CCR2
CCIFG2, TB3CCR3 CCIFG3,
TB3CCR4 CCIFG4, TB3CCR5
CCIFG5, TB3CCR6 CCIFG6, TB3IFG
(TB3IV)
Timer3_B7
Maskable
FFEAh
53
RTC counter
RTCIFG
WDTIFG
Maskable
Maskable
FFE8h
FFE6h
52
51
Watchdog timer interval mode
UCTXCPTIFG, UCSTTIFG, UCRXIFG,
UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
(UCA0IV))
eUSCI_A0 receive or transmit
eUSCI_A1 receive or transmit
Maskable
Maskable
FFE4h
FFE2h
50
49
UCTXCPTIFG, UCSTTIFG, UCRXIFG,
UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
(UCA0IV))
UCB0RXIFG, UCB0TXIFG (SPI mode)
UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1, UCRXIFG2,
UCTXIFG2, UCRXIFG3, UCTXIFG3,
UCCNTIFG,
eUSCI_B0 receive or transmit
Maskable
FFE0h
48
UCBIT9IFG,UCCLTOIFG(I2C mode)
(UCB0IV)
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PRIORITY
47
表 6-2. Interrupt Sources, Flags, and Vectors (continued)
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
UCB1RXIFG, UCB1TXIFG (SPI mode)
UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1, UCRXIFG2,
UCTXIFG2, UCRXIFG3, UCTXIFG3,
UCCNTIFG,
eUSCI_B1 receive or transmit
Maskable
FFDEh
UCBIT9IFG,UCCLTOIFG(I2C mode)
(UCB0IV)
ADCIFG0, ADCINIFG, ADCLOIFG,
ADCHIIFG, ADCTOVIFG, ADCOVIFG
(ADCIV)
ADC
Maskable
FFDCh
46
eCOMP0_eCOMP1
SAC0_SAC2(1)
CPIIFG, CPIFG (CP1IV, CP0IV)
Maskable
Maskable
FFDAh
FFD8h
45
44
SAC2DACSTS DACIFG (SAC2IV)
SAC0DACSTS DACIFG, SAC0IV)
SAC3DACSTS DACIFG (SAC3IV)
SAC1DACSTS DACIFG, SAC1IV)
SAC1_SAC3(1)
Maskable
FFD6h
43
P1
P2
P1IFG.0 to P1IFG.7 (P1IV)
P2IFG.0 to P2IFG.7 (P2IV)
P3IFG.0 to P3IFG.7 (P3IV)
P4IFG.0 to P4IFG.7 (P4IV)
Reserved
Maskable
Maskable
Maskable
Maskable
Maskable
FFD4h
FFD2h
42
41
40
39
P3
FFD0h
P4
FFCEh
Reserved
FFCCh to FF88h
(1) MSP430FR235x devices only
表 6-3 lists the BSL signature settings. The BSL setting on MSP430FR2355 can be customized by using
BSL configuration and I2C address. See the MSP430 FRAM Device Bootloader (BSL) User's Guide for
more details.
表 6-3. BSL Signatures
SIGNATURE
BSL I2C Address(1)
BSL Config
WORD ADDRESS
FFA0h
0FF8Ah
BSL Config Signature
BSL Signature2
BSL Signature1
JTAG Signature2
JTAG Signature1
0FF88h
0FF86h
0FF84h
0FF82h
0FF80h
(1) 7-bit address BSL I2C interface
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6.4 Memory Organization
表 6-4 summarizes the memory map of the devices.
表 6-4. Memory Organization
ACCESS
MSP430FR2355
MSP430FR2353
Memory (FRAM)
Main: interrupt vectors and signatures
Main: code memory
32KB
FFFFh to FF80h
FFFFh to 8000h
16KB
FFFFh to FF80h
FFFFh to C000h
Read/Write
(Optional Write Protect)(1)
4KB
2FFFh to 2000h
2KB
27FFh to 2000h
RAM
Read/Write
Read/Write(2)
Read only
Read/Write
Read/Write
Read
512 bytes
19FFh to 1800h
512 bytes
19FFh to 1800h
Information memory (FRAM)
Driver library and FFT library (ROM)
Peripherals
20KB
FAC00h to FFBFFh
20KB
FAC00h to FFBFFh
4KB
0FFFh to 0020h
4KB
0FFFh to 0020h
26 bytes
001Fh to 0006h
26 bytes
001Fh to 0006h
Tiny RAM
6 bytes
0005h to 0000h
6 bytes
0005h to 0000h
Reserved(3)
(1) The program FRAM can be write protected by setting PFWP bit in SYSCFG0 register. See the SYS chapter in MSP430FR4xx and
MSP430FR2xx Family User's Guide for more details.
(2) The information FRAM can be write protected by setting DFWP bit in SYSCFG0 register. See the SYS chapter in MSP430FR4xx and
MSP430FR2xx Family User's Guide for more details.
(3) Reads as D032h at 00h (opcode: BIS.W LPM4, SR), reads as 00F0h at 02h (opcode: BIS.W LPM4, SR), and reads as 3FFFh at 04h
(opcode: JMP$)
6.5 Bootloader (BSL)
The BSL enables users to program the FRAM memory or RAM using a UART or I2C serial interface.
Access to the device memory through the BSL is protected by an user-defined password. Use of the BSL
requires four pins (see 表 6-5 and 表 6-6). BSL entry requires a specific entry sequence on the
RST/NMI/SBWTDIO and TEST/SBWTCK pins. For complete description of the features of the BSL and its
implementation, see MSP430 FRAM Devices Bootloader (BSL) User's Guide.
表 6-5. UART BSL Pin Requirements and Functions
DEVICE SIGNAL
RST/NMI/SBWTDIO
TEST/SBWTCK
P1.7
BSL FUNCTION
Entry sequence signal
Entry sequence signal
Data transmit
P1.6
Data receive
DVCC
Power supply
DVSS
Ground supply
表 6-6. I2C BSL Pin Requirements and Functions
DEVICE SIGNAL
RST/NMI/SBWTDIO
TEST/SBWTCK
P1.2
BSL FUNCTION
Entry sequence signal
Entry sequence signal
Data receive and transmit
Clock
P1.3
DVCC
Power supply
DVSS
Ground supply
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6.6 JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430 development tools and device programmers. 表 6-7 lists the JTAG pin requirements. For further
details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools
User's Guide.
表 6-7. JTAG Pin Requirements and Function
DEVICE SIGNAL
P1.4/UCA0STE/TCK/A4
DIRECTION
JTAG FUNCTION
JTAG clock input
JTAG state control
JTAG data input, TCLK input
JTAG data output
Enable JTAG pins
External reset
IN
IN
IN
OUT
IN
IN
–
P1.5/UCA0CLK/TMS/OA1O/A5
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/OA1-/A6
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/OA1+/A7/VREF+
TEST/SBWTCK
RST/NMI/SBWTDIO
DVCC
Power supply
DVSS
–
Ground supply
6.7 Spy-Bi-Wire Interface (SBW)
The MSP430 family supports the two wire Spy-Bi-Wire interface. Spy-Bi-Wire can be used to interface
with MSP430 development tools and device programmers. 表 6-8 shows the Spy-Bi-Wire interface pin
requirements. For further details on interfacing to development tools and device programmers, see the
MSP430 Hardware Tools User's Guide.
表 6-8. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RST/NMI/SBWTDIO
DVCC
DIRECTION
SBW FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input and output
Power supply
IN
IN, OUT
–
–
DVSS
Ground supply
6.8 FRAM
The FRAM can be programmed using the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. Features of the FRAM include:
•
•
•
Byte and word access capability
Programmable wait state generation
Error correction coding (ECC)
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6.9 Memory Protection
The device features memory protection of user access authority and write protection include:
•
Securing the whole memory map to prevent unauthorized access from JTAG port or BSL, by writing
JTAG and BSL signatures using the JTAG port, SBW, the BSL, or in-system by the CPU.
•
Write protection enabled to prevent unwanted write operation to FRAM contents by setting the control
bits with accordingly password in System Configuration register 0. For more detailed information, see
the SYS chapter in the MSP430FR4xx and MSP430FR2xx Family User's Guide.
6.10 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. All peripherals can be
handled by using all instructions in the memory map. For complete module description, see the
MSP430FR4xx and MSP430FR2xx Family User's Guide.
6.10.1 Power Management Module (PMM) and On-Chip Reference Voltages
The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM
also includes supply voltage supervisor (SVS) and brownout protection. The brownout reset circuit (BOR)
is implemented to provide the proper internal reset signal to the device during power-on and power-off.
The SVS circuitry detects if the supply voltage drops below a user-selectable safe level. SVS circuitry is
available on the primary supply.
The device contains three on-chip references:
•
•
•
Internal shared reference (1.5 V, 2.0 V, or 2.5 V)
1.2 V for external reference (VREF pin)
1.2 V low-power reference for eCOMP
The internal shared reference is controlled by PMM settings to select 1.5 V, 2.0 V, or 2.5 V. This reference
is internally connected to ADC channel 13. DVCC is internally connected to ADC channel 15. When
DVCC is set as the reference voltage for ADC conversion, the DVCC can be easily represent as 公式 1 by
using ADC sampling reference without any external components support.
DVCC = (4095 × reference voltage) ÷ ADC result
(1)
The internal shared reference (1.5 V, 2.0 V, or 2.5 V ) is also internally connected to the built-in DAC of
the comparator and SAC (MSP430FR235x devices only) built-in 12-bit DAC as the reference voltage. The
source can be selected by setting the specific register configuration of each module For more information,
see the MSP430FR4xx and MSP430FR2xx Family User's Guide.
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/OA1+/A7/VREF+ can support a buffered external 1.2-V output
when EXTREFEN = 1 in the PMMCTL2 register. ADC channel 7 can also be selected to monitor this
voltage. For more information, see the MSP430FR4xx and MSP430FR2xx Family User's Guide.
An additional low-power 1.2-V reference is internally connected to eCOMP0 and eCOMP1. This reference
is activated by enabling eCOMP with the channel as threshold source. See 节 6.10.13 for more details.
6.10.2 Clock System (CS) and Clock Distribution
The clock system includes a 32-kHz low-frequency or up to 24-MHz high-frequency crystal oscillator
(XT1), an internal very low-power low-frequency oscillator (VLO), an integrated 32-kHz RC oscillator
(REFO), an integrated internal digitally controlled oscillator (DCO) that can use frequency-locked loop
(FLL) locking with internal or external 32-kHz reference clock, and on-chip asynchronous high-speed clock
(MODOSC). The clock system is designed to target cost-effective designs with minimal external
components. A fail-safe mechanism is designed for XT1. The clock system module supports the following
clock signals.
•
Main Clock (MCLK): the system clock used by the CPU and all relevant peripherals accessed by the
bus. All clock sources except MODOSC can be selected as the source with a predivider of 1, 2, 4, 8,
16, 32, 64, or 128.
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•
•
Sub-Main Clock (SMCLK): the subsystem clock used by the peripheral modules. SMCLK derives from
the MCLK with a predivider of 1, 2, 4, or 8. This means SMCLK is always equal to or less than MCLK.
Auxiliary Clock (ACLK): this clock derived from the external XT1 clock, internal VLO, or internal REFO
clock up to 40 kHz.
All peripherals have one or several clock sources, depending on specific functionality. 表 6-9 lists the clock
distribution used in this device.
表 6-9. Clock Distribution
CLOCK
SOURCE
SELECT BITS
EXTERNAL
MCLK
SMCLK
ACLK
MODCLK
VLOCLK
PIN
Frequency
Range
DC to 24 MHz
DC to 24 MHz
DC to 40 kHz
3.8 MHz ±21%
10 kHz ±50%
–
CPU
FRAM
RAM
CRC
MPY32
ICC
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Default
Default
Default
Default
Default
Default
Default
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
I/O
00b (TB0CLK
pin)
TB0
TBSSEL
TBSSEL
TBSSEL
TBSSEL
UCSSEL
UCSSEL
UCSSEL
UCSSEL
–
–
–
–
–
–
–
–
10b
10b
01b
01b
01b
01b
01b
01b
01b
01b
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00b (TB1CLK
pin)
TB1
00b (TB2CLK
pin)
TB2
10b
00b (TB3CLK
pin)
TB3
10b
00b (UCA0CLK
pin)
eUSCI_A0
eUSCI_A1
eUSCI_B0
eUSCI_B1
10b or 11b
10b or 11b
10b or 11b
10b or 11b
00b (UCA1CLK
pin)
00b (UCB0CLK
pin)
00b (UCB1CLK
pin)
MFM
N/A
–
–
–
–
Default
00b
–
–
–
–
–
–
–
–
WDT
WDTSSEL
ADCSSEL
RTCSS
01b
10b
–
ADC
10b or 11b
01b(1)
01b
01b(1)
00b
–
RTC Counter
11b
(1) Controlled by the RTCCKSEL bit in the SYSCFG2 register.
表 6-10. XTCLK Distribution
XTHFCLK
XTLFCLK
XTLFCLK (LPMx.5)
CLOCK SOURCE
SELECT BITS
OPERATION MODE
MCLK
AM to LPM0
AM to LPM3
AM to LPM3.5
SELMS
SELMS
SELREF
SELA
10b
10b
0b
0b
–
10b
10b
0b
10b
10b
0b
SMCLK
REFO
ACLK
RTC
0b
0b
RTCSS
10b
10b
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6.10.3 General-Purpose Input/Output Port (I/O)
Up to 44 I/O ports are implemented.
•
•
•
P1, P2, P3, and P4 are full 8-bit ports; P5 and P6 feature up to 5-bit and 7-bit ports, respectively.
All individual I/O bits are independently programmable.
Any combination of input, output, is possible for P1, P2, P3, P4, P5, and P6. Interrupt conditions are
possible in P1, P2, P3, and P4.
•
•
Programmable pullup or pulldown on all ports.
Edge-selectable interrupt and LPM3.5, LPM4 and LPM4.5 wake-up input capability is available in P1,
P2, P3, and P4.
•
•
Read and write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise or word-wise in pairs.
注
Configuration of digital I/Os after BOR reset
To prevent cross currents during start-up of the device, all port pins are high-impedance with
Schmitt triggers and module functions disabled. To enable the I/O functions after a BOR
reset, first configure the ports and then clear the LOCKLPM5 bit. For details, see the
Configuration After Reset section in the Digital I/O chapter of the MSP430FR4xx and
MSP430FR2xx Family User's Guide.
6.10.4 Watchdog Timer (WDT)
The primary function of the WDT module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not
needed in an application, the module can be configured as interval timer and can generate interrupts at
selected time intervals.
表 6-11 lists the clock sources that can be used by the WDT.
表 6-11. WDT Clocks
NORMAL OPERATION
WDTSSEL
(WATCHDOG AND INTERVAL
TIMER MODE)
00
01
10
11
SMCLK
ACLK
VLOCLK
Reserved
6.10.5 System Module (SYS)
The SYS module handles many of the system functions within the device. These include power-on reset
(POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector
generators (see 表 6-12), bootloader entry mechanisms, and configuration management (device
descriptors). SYS also includes a data exchange mechanism through SBW called a JTAG mailbox that
can be used in the application.
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表 6-12. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER
ADDRESS
INTERRUPT EVENT
No interrupt pending
VALUE
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
PRIORITY
Brownout (BOR)
Highest
RSTIFG RST/NMI (BOR)
PMMSWBOR software BOR (BOR)
LPMx.5 wake up (BOR)
Security violation (BOR)
Reserved
SVSHIFG SVSH event (BOR)
Reserved
Reserved
SYSRSTIV, System Reset
015Eh
PMMSWPOR software POR (POR)
WDTIFG watchdog time-out (PUC)
WDTPW password violation (PUC)
FRCTLPW password violation (PUC)
Uncorrectable FRAM bit error detection
Peripheral area fetch (PUC)
PMMPW PMM password violation
(PUC)
20h
Reserved
FLL unlock (PUC)
22h
24h
Reserved
26h to 3Eh
00h
Lowest
Highest
No interrupt pending
SVS low-power reset entry
Uncorrectable FRAM bit error detection
Reserved
02h
04h
06h
Reserved
08h
Reserved
0Ah
Reserved
0Ch
SYSSNIV, System NMI
015Ch
Reserved
0Eh
Reserved
10h
VMAIFG Vacant memory access
JMBINIFG JTAG mailbox input
JMBOUTIFG JTAG mailbox output
Correctable FRAM bit error detection
Reserved
12h
14h
16h
18h
1Ah to 1Eh
00h
Lowest
Highest
Lowest
No interrupt pending
NMIIFG NMI pin or SVSH event
OFIFG oscillator fault
Reserved
02h
SYSUNIV, User NMI
015Ah
04h
06h to 1Eh
6.10.6 Cyclic Redundancy Check (CRC)
The 16-bit cyclic redundancy check (CRC) module produces a signature based on a sequence of data
values and can be used for data checking purposes. The CRC generation polynomial is compliant with
CRC-16-CCITT standard of x16 + x12 + x5 + 1.
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6.10.7 Interrupt Compare Controller (ICC)
The Interrupt Compare Controller (ICC) allows all maskable interrupt sources to be scheduled in a
preemptive mechanism. Each interrupt source is specified as a source of ICC module. Each source
supports a 4-level software interrupt priority other than the one tired with interrupt vector. When ICC
module is enabled, the ISR in lower software priority can be interrupted by higher priority. It is required to
enable GIE in ISR for proper ICC operation. For details, see the ICC chapter of the MSP430FR4xx and
MSP430FR2xx Family User's Guide. 表 6-13 lists the ICC source configurations.
表 6-13. ICC Interrupt Source Assignments
INTERRUPT
SOURCE
SYSTEM
INTERRUPT
WORD
ADDRESS
REGISTER
BITS
INTERRUPT FLAG
PRIORITY
ILSR0
ILSR1
ILSR2
ILSR3
P4
P3
P2
P1
P4IFG.0 to P4IFG.7 (P4IV)
P3IFG.0 to P3IFG.7 (P3IV)
P2IFG.0 to P2IFG.7 (P2IV)
P1IFG.0 to P1IFG.7 (P1IV)
Maskable
Maskable
Maskable
Maskable
FFCEh
FFD0h
FFD2h
FFD4h
39
40
41
42
SAC3 DAC,
ILSR4
ILSR5
ILSR6
DACIFG, (SAC3IV, SAC1IV)(1)
DACIFG (SAC2IV, SAC0IV)(1)
CPIIFG, CPIFG (CP1IV, CP0IV)
Maskable
Maskable
Maskable
FFD6h
FFD8h
FFDAh
43
44
45
SAC1 DAC(1)
ICCILRS0
SAC2 DAC,
SAC0 DAC(1)
eCOMP1,
eCOMP0
ADCIFG0, ADCINIFG, ADCLOIFG,
ADCHIIFG, ADCTOVIFG, ADCOVIFG
(ADCIV)
ILSR7
ADC
Maskable
FFDCh
46
UCB1RXIFG, UCB1TXIFG (SPI mode)
UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1, UCRXIFG2,
UCTXIFG2, UCRXIFG3, UCTXIFG3,
UCCNTIFG,
eUSCI_B1
Receive or
Transmit
ILSR8
Maskable
FFDEh
47
UCBIT9IFG,UCCLTOIFG(I2C mode)
(UCB0IV)
UCB0RXIFG, UCB0TXIFG (SPI mode)
UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1, UCRXIFG2,
UCTXIFG2, UCRXIFG3, UCTXIFG3,
UCCNTIFG,
eUSCI_B0
Receive or
Transmit
ILSR9
Maskable
FFE0h
48
UCBIT9IFG,UCCLTOIFG(I2C mode)
(UCB0IV)
UCTXCPTIFG, UCSTTIFG, UCRXIFG,
UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
(UCA0IV))
eUSCI_A1
Receive or
Transmit
ICCILRS1
ILSR10
ILSR11
Maskable
Maskable
FFE2h
FFE4h
49
50
UCTXCPTIFG, UCSTTIFG, UCRXIFG,
UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
(UCA0IV))
eUSCI_A0
Receive or
Transmit
Watchdog Timer
Interval mode
ILSR12
ILSR13
WDTIFG
Maskable
Maskable
FFE6h
FFE8h
51
52
RTC Counter
Timer3_B7
Timer3_B7
RTCIFG
TB3CCR1 CCIFG1, TB3CCR2
CCIFG2, TB3CCR3 CCIFG3,
TB3CCR4 CCIFG4, TB3CCR5
CCIFG5, TB3CCR6 CCIFG6, TB3IFG
(TB3IV)
ILSR14
ILSR15
Maskable
Maskable
FFEAh
FFECh
53
54
TB3CCR0 CCIFG0
(1) MSP430FR235x devices only
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PRIORITY
表 6-13. ICC Interrupt Source Assignments (continued)
INTERRUPT
SOURCE
SYSTEM
INTERRUPT
WORD
ADDRESS
REGISTER
BITS
INTERRUPT FLAG
TB2CCR1 CCIFG1, TB2CCR2
CCIFG2, TB2IFG (TB2IV)
ILSR16
ILSR17
ILSR18
ILSR19
ILSR20
Timer2_B3
Timer2_B3
Timer1_B3
Timer1_B3
Timer0_B3
Maskable
Maskable
Maskable
Maskable
Maskable
FFEEh
FFF0h
FFF2h
FFF4h
FFF6h
55
56
57
58
59
TB2CCR0 CCIFG0
TB1CCR1 CCIFG1, TB1CCR2
CCIFG2, TB1IFG (TB1IV)
TB1CCR0 CCIFG0
ICCILRS2
TB0CCR1 CCIFG1, TB0CCR2
CCIFG2, TB0IFG (TB0IV)
ILSR21
ILSR22
ILSR23
ILSR24
ILSR25
ILSR26
ILSR27
ILSR28
ILSR29
ILSR30
ILSR31
Timer0_B3
N/A
TB0CCR0 CCIFG0
Maskable
N/A
FFF8h
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
60
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
ICCILRS3
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
6.10.8 Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_A1,
eUSCI_B0, eUSCI_B1)
The eUSCI modules are used for serial data communications (see 表 6-14). The eUSCI_A module
supports either UART or SPI communications. The eUSCI_B module supports either SPI or I2C
communications. Additionally, eUSCI_A supports automatic baud-rate detection and IrDA..
表 6-14. eUSCI Pin Configurations
PIN
P1.7
P1.6
P1.5
P1.4
PIN
UART
SPI
SIMO
SOMI
SCLK
STE
TXD
eUSCI_A0
eUSCI_A1
eUSCI_B0
eUSCI_B1
RXD
–
–
UART
SPI
P4.3
P4.2
P4.1
P4.0
PIN
TXD or TXD
SIMO
SOMI
SCLK
STE
RXD or RXD
–
–
I2C
SCL
SDA
–
SPI
P1.3
P1.2
P1.1
P1.0
PIN
SOMI
SIMO
SCLK
STE
–
I2C
SCL
SDA
–
SPI
P4.7
P4.6
P4.5
P4.4
SOMI
SIMO
SCLK
STE
–
72
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The eUSCI_A1 can work as UART in inverting polarity mode by port settings (see 表 6-15). When
PSEL = 01b, the normal UART or SPI mode is used. When PSEL = 10b, the inverted UART mode is
enabled to transmit and receive data in inverted polarity. In this mode, eUSCI_A1 can also wake up the
device from LPM3 by detecting a rising edge of start bit according the falling edge in normal mode.
表 6-15. eUSCI_A1 UART Polarity Configurations
eUSCI_A1
P4.3
PSEL = 01b
TXD
PSEL = 10b
TXD
P4.4
RXD
RXD
6.10.9 Timers (Timer0_B3, Timer1_B3, Timer2_B3, Timer3_B7)
The Timer0_B3, Timer1_B3, and Timer2_B3 modules are 16-bit timers and counters with three
capture/compare registers each. Timer3_B7 is a 16-bit timers with seven capture/compare registers each.
Each can support multiple captures or compares, PWM outputs, and interval timing (see 表 6-16, 表 6-17,
表 6-18, and 表 6-19). Each has extensive interrupt capabilities. Interrupts can be generated from the
counter on overflow conditions and from each of the capture/compare registers. The CCR0 registers on all
timers are not externally connected and can only be used for hardware period timing and interrupt
generation. In Up Mode, they can be used to set the overflow value of the counter.
表 6-16. Timer0_B3 Signal Connections
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
PORT PIN
MODULE BLOCK
P2.7
TB0CLK
ACLK (internal)
SMCLK (internal)
N/A
TBCLK
ACLK
Timer
N/A
SMCLK
INCLK
CCI0A
From RTC (internal)
Not used
Timer1_B3 CCI0B
input
ACLK (internal)
CCI0B
CCR0
CCR1
TB0
DVSS
DVCC
TB0.1
GND
VCC
P1.6
P1.7
CCI1A
TB0.1
From eCOMP0.O
(internal)
Timer1_B3 CCI1B
input
CCI1B
TB1
TB2
DVSS
DVCC
TB0.2
GND
VCC
CCI2A
TB0.2
Timer1_B3 INCLK
Timer1_B3 CCI2B
input,
N/A
CCI2B
CCR2
IR carrier input
DVSS
DVCC
GND
VCC
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表 6-17. Timer1_B3 Signal Connections
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
PORT PIN
MODULE BLOCK
P2.2
TB1CLK
TBCLK
ACLK
ACLK (internal)
SMCLK (internal)
Timer
N/A
SMCLK
Timer0_B3 CCR2B
output (internal)
INCLK
CCI0A
CCI0B
Timer3_B7 CCR0B
output (internal)
Not used
Not used
Timer0_B3 CCR0B
output (internal)
CCR0
TB0
DVSS
DVCC
TB1.1
GND
VCC
P2.0
P2.1
CCI1A
TB1.1
Timer0_B3 CCR1B
output (internal)
CCI1B
To ADC trigger
CCR1
CCR2
TB1
TB2
DVSS
DVCC
TB1.2
GND
VCC
CCI2A
TB1.2
Timer0_B3 CCR2B
output (internal)
CCI2B
IR coding input
DVSS
DVCC
GND
VCC
表 6-18. Timer2_B3 Signal Connections
DEVICE INPUT
SIGNAL
MODULE INPUT
MODULE BLOCK
NAME
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
PORT PIN
P2.7
TB2CLK
ACLK (internal)
SMCLK (internal)
TB2CLK
TBCLK
ACLK
Timer
N/A
TB0
SMCLK
INCLK
Not used
CCI0A
GND
CCR0
Not used
DVSS
DVCC
VCC
MFM Complete Event
TB2.1
CCI0B
CCI1A
MFM start trigger
TB2.1
P5.0
P5.1
From eCOMP1.O
(internal)
To SAC DAC update
trigger 10b(1)
CCI1B
CCR1
CCR2
TB1
TB2
DVSS
DVCC
TB2.2
GND
VCC
CCI2A
TB2.2
To SAC DAC update
trigger 11b(1)
Not used
CCI2B
DVSS
DVCC
GND
VCC
(1) MSP430FR235x devices only
74
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ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
表 6-19. Timer3_B7 Signal Connections
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
PORT PIN
MODULE BLOCK
P6.6
TB3CLK
ACLK (internal)
SMCLK (internal)
TB3CLK
Not used
Not used
DVSS
TBCLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
N/A
TB0
TB1
Not used
To Timer1_B3 CCI0A
CCR0
CCR1
DVCC
VCC
P6.0
TB3.1
CCI1A
CCI1B
GND
TB3.1
Not used
DVSS
DVCC
VCC
P6.1
P4.0
TB3.2
CCI2A
TB3.2
AND UCA1TXD
ISOTXD
ISORXD
CCI2B
CCR2
TB2
DVSS
DVCC
TB3.3
GND
VCC
P6.2
P6.3
P6.4
P6.5
CCI3A
CCI3B
GND
VCC
TB3.3
Not used
DVSS
CCR3
CCR4
CCR5
CCR6
TB3
TB4
TB5
TB6
DVCC
TB3.4
CCI4A
CCI4B
GND
VCC
TB3.4
Not used
DVSS
Not used
DVCC
TB3.5
CCI5A
CCI5B
GND
VCC
TB3.5
Not used
DVSS
Not used
DVCC
TB3.6
CCI6A
CCI6B
GND
VCC
TB3.6
Not used
DVSS
Not used
DVCC
The interconnection of Timer0_B3 and Timer1_B3 can be used to modulate the eUSCI_A pin of
UCA0TXD/UCA0SIMO in either ASK or FSK mode, with which a user can easily acquire a modulated
infrared command for directly driving an external IR diode. The IR functions are fully controlled by SYS
configuration registers 1 including IREN (enable), IRPSEL (polarity select), IRMSEL (mode select),
IRDSSEL (data select), and IRDATA (data) bits. For more information, see the SYS chapter in the
MSP430FR4xx and MSP430FR2xx Family User's Guide.
The Timer_B module feature the function to put Timer_B all outputs into a high impedance state when the
selected source is triggered. The source can be selected from external pin or internal of the device, it is
controlled by TBxTRG in SYS. For more information, see the SYS chapter in the MSP430FR4xx and
MSP430FR2xx Family User's Guide.
The Timer2_B3 CCR0 is tied with the Manchester function module (MFM).
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表 6-20 lists the Timer_B high-impedance trigger sources.
表 6-20. TBxOUTH
TBxOUTH TRIGGER SOURCE
TIMER_B PAD OUTPUT HIGH
IMPEDANCE
TBxTRGSEL
SELECTION
TB0TRGSEL = 0
TB0TRGSEL= 1
TB1TRGSEL = 0
TB1TRGSEL = 1
TB2TRGSEL = 0
TB2TRGSEL = 1
TB3TRGSEL = 0
TB3TRGSEL = 1
eCOMP0 output (internal)
P1.6, P1.7
P2.0, P2.1
P1.2
eCOMP0 output (internal)
P2.3
eCOMP1 output (internal)
P5.3
P5.0, P5.1
eCOMP1 output (internal)
N/A
P6.0, P6.1, P6.2, P6.3, P6.4, P6.5
6.10.10 Backup Memory (BKMEM)
The BKMEM supports data retention functionality during LPM3.5 mode. This device provides up to
32 bytes that are retained during LPM3.5.
6.10.11 Real-Time Clock (RTC) Counter
The RTC counter is a 16-bit modulo counter that is functional in AM, LPM0, LPM3, LPM4, and LPM3.5.
This module can periodically wake up the CPU from LPM0, LPM3, LPM4, and LPM3.5 based on timing
from a low-power clock source such as the XT1, ACLK, and VLO clocks. In AM, RTC can be driven by
SMCLK to generate high-frequency timing events and interrupts. ACLK and SMCLK both can source to
the RTC; however, only one of them can be selected at a time. The RTC overflow events can trigger:
•
•
Timer0_B3 CCI0A
ADC conversion trigger when ADCSHSx bits are set as 01b
76
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ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
6.10.12 12-Bit Analog-to-Digital Converter (ADC)
The 12-bit ADC module supports fast 12-bit analog-to-digital conversions with single-ended input. The
module implements a 12-bit SAR core, sample select control, reference generator and a conversion result
buffer. A window comparator with a lower and upper limits allows CPU-independent result monitoring with
three window comparator interrupt flags.
The ADC supports 12 external inputs and four internal inputs (see 表 6-21).
表 6-21. ADC Channel Connections
ADCINCHx
ADC CHANNELS
EXTERNAL PIN OUTPUT
0
1
A0/Veref+
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P5.0
P5.1
P5.2
P5.3
N/A
A1/
2
A2/Veref-
3
A3
4
A4
5
A5
6
A6
A7(1)
7
8
A8
9
A9
10
11
12
A10
A11
On-chip temperature sensor
Internal shared reference voltage
(1.5 V, 2.0 V, or 2.5 V)
13
N/A
14
15
DVSS
DVCC
N/A
N/A
(1) When A7 is used, the PMM 1.2-V reference voltage can be output to this pin by setting the PMM
control register. The 1.2-V voltage can be measured by channel A7.
The analog-to-digital conversion can be started by software or a hardware trigger. 表 6-22 lists the trigger
sources that are available.
表 6-22. ADC Trigger Signal Connections
ADCSHSx
TRIGGER SOURCE
BINARY
DECIMAL
00
01
10
11
0
1
2
3
ADCSC bit (software trigger)
RTC event
TB1.1B
eCOMP0 COUT
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6.10.13 Enhanced Comparator
This device features two enhanced comparators: eCOMP0 and eCOMP1. The enhanced comparator is an
analog voltage comparator with a built-in 6-bit DAC as an internal voltage reference. The integrated 6-bit
DAC can be set to 64 steps for the comparator reference voltage. This module has 4-level programmable
hysteresis and configurable power modes: high-power mode or low-power mode.
The eCOMP0 supports a propagation delay up to 1 µs in high-power mode. In low-power mode, eCOMP0
supports 3.2-µs delay with 1.5-µA leakage at room temperature, which can be an ideal wake-up source in
LPM3 for a voltage monitor.
The eCOMP1 supports a propagation delay up to 100 ns in high-power mode. In low-power mode,
eCOMP1 supports 320-ns delay with 10-µA leakage at room temperature.
Both eCOMP0 and eCOMP1 contains a programmable 6-bit DAC that can use internal shared reference
(1.5, 2.0, or 2.5-V) for high precision comparison threshold. In addition to internal shared reference, a low-
power 1.2-V reference is fixed at channel 2 of both inverting and non-inverting path that allows the DAC
turned off for saving powers.
The eCOMP0 supports external inputs and internal inputs (see 表 6-23) and outputs (see 表 6-25)
表 6-23. eCOMP0 Input Channel Connections
CPPSEL
000
eCOMP0 CHANNELS
P1.0/COMP0.0/A0
P1.1/OA0O/COMP0.1/A1
Low-power 1.2-V reference
N/A
CPNSEL
000
eCOMP0 CHANNELS
P1.0/COMP0.0/A0
P1.1/OA0O/COMP0.1/A1
Low-power 1.2-V reference
N/A
001
001
010
010
011
011
100
N/A
100
N/A
101
P1.1/OA0O/COMP0.1/A1
eCOMP0 6-bit DAC
101
P3.1/OA2O
110
110
eCOMP0 6-bit DAC
表 6-24. eCOMP1 Input Channel Connections
CPPSEL
000
eCOMP1 CHANNELS
CPNSEL
000
eCOMP1 CHANNELS
P2.5/COMP1.0
P2.4/COMP1.1
Low-power 1.2-V reference
N/A
P2.5/COMP1.0
P2.4/COMP1.1
Low-power 1.2-V reference
N/A
001
001
010
010
011
011
100
N/A
100
N/A
101
P1.5/OA1O/A5
eCOMP1 6-bit DAC
101
P3.5/OA3O
110
110
eCOMP1 6-bit DAC
表 6-25. eCOMP0 Output Channel Connections
ECOMP0 OUT
EXTERNAL PINOUT, MODULE
1
2
3
4
P2.0
TB0.1B, TB0 (TB0OUTH), TB1 (TB1OUTH), ADC trigger
Reserved
Reserved
78
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ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
表 6-26. eCOMP1 Output Channel Connections
ECOMP1 OUT
EXTERNAL PINOUT, MODULE
1
2
3
4
P2.1
TB2.1B, TB2 (TB2OUTH), TB3 (TB3OUTH)
Reserved
MFM input
6.10.14 Manchester Function Module (MFM)
The MFM is a dedicated module residing between a pair of pins and eUSCI_B1 to encode and decode
Manchester-coded data. For more information, see the MFM chapter in the MSP430FR4xx and
MSP430FR2xx Family User's Guide.
When enabled by setting PSEL, the MFM module receives and transmits data through
P5.0/TB2.1/MFM.RX/A8 and P5.1/TB2.2/MFM.TX/A9, respectively. The MFM always works in SPI master
mode, and the eUSCI_B1 must be configured in 4-wire SPI slave mode.
6.10.15 Smart Analog Combo (SAC) (MSP430FR235x Devices Only)
The MSP430FR235x devices integrate four SAC modules: SAC0, SAC1, SAC2, and SAC3. The SAC
integrates a high-performance low-power operational amplifier. SAC-L3 supports a hybrid configuration of
general-purpose amplifier, 12-bit voltage reference DAC, and a multiplex switch array. For more
information, see the SAC chapter in the MSP430FR4xx and MSP430FR2xx Family User's Guide. Only
MSP430FR235x devices implement the SAC modules. MSP430FR215x devices do not support SAC
modules.
The SAC0 and SAC2 are interconnected and support external inputs and internal inputs (see 表 6-27 and
表 6-28).
表 6-27. SAC0 Channel Connections
PSEL
00
SAC0 OA NONINVERTING CHANNELS
P1.3/OA0+/A3
NSEL
00
SAC0 OA INVERTING CHANNELS
P1.2/OA0-/A2
01
SAC0 12-bit DAC
01
PGA feedback
10
P3.1/OA2O, SAC2 OA output
N/A
10
P3.1/OA2O, SAC2 OA output
N/A
11
11
表 6-28. SAC2 Channel Connections
PSEL
00
SAC2 OA NONINVERTING CHANNELS
NSEL
00
SAC2 OA INVERTING CHANNELS
P3.3/OA2+
P3.2/OA2-
01
SAC2 12-bit DAC
01
PGA feedback
10
P1.1/UCB0CLK/ACLK/OA0O/COMP0.1/A1, SAC0 OA output
N/A
10
P1.1/UCB0CLK/ACLK/OA0O/COMP0.1/A1, SAC0 OA output
N/A
11
11
The SAC1 and SAC3 are interconnected and support external inputs and internal inputs (see 表 6-29 and
表 6-30).
表 6-29. SAC1 Channel Connections
PSEL
00
SAC1 OA NONINVERTING CHANNELS
P1.7/OA1+/A7
NSEL
00
SAC1 OA INVERTING CHANNELS
P1.6/OA1-/A6
01
SAC1 12-bit DAC
01
PGA feedback
10
P3.5/OA3O, SAC3 OA output
N/A
10
P3.5/OA3O, SAC3 OA output
N/A
11
11
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表 6-30. SAC3 Channel Connections
PSEL
00
SAC3 OA NONINVERTING CHANNELS
P3.7/OA3+
NSEL
00
SAC3 OA INVERTING CHANNELS
P3.6/OA3-
PGA feedback
01
SAC3 12-bit DAC
01
10
P1.5/OA1O/A5, SAC1 OA output
N/A
10
P1.5/OA1O/A5, SAC1 OA output
N/A
11
11
Each SAC DAC supports two selectable voltage references (see 表 6-31).
表 6-31. SACx DAC Reference Selection
DACSREF
SACx DAC REFERENCE SELECTION
DVCC
0
1
Internal shared reference (1.5, 2.0, or 2.5 V )
SAC1 DAC REFERENCE
DVCC
DACSREF
0
1
Internal shared reference (1.5, 2.0, or 2.5 V )
SAC2 DAC REFERENCE
DVCC
DACSREF
0
1
Internal shared reference (1.5, 2.0, or 2.5 V )
SAC3 DAC REFERENCE
DVCC
DACSREF
0
1
Internal shared reference (1.5, 2.0, or 2.5 V )
Each SAC DAC supports one software trigger and two hardware trigger from chip signals.
表 6-32. SACx DAC Hardware Trigger Selection
DACLSEL
SAC0 DAC HARDWARE TRIGGER
DACLSEL
SAC1 DAC HARDWARE TRIGGER
00
Writing SAC0DACDAT register
00
Writing SAC1DACDAT register
01
N/A
01
N/A
10
TB2.1
10
TB2.1
11
TB2.2
11
TB2.2
DACLSEL
SAC2 DAC HARDWARE TRIGGER
DACLSEL
SAC3 DAC HARDWARE TRIGGER
00
01
10
11
Writing SAC2DACDAT register
00
01
10
11
Writing SAC3DACDAT register
N/A
N/A
TB2.1
TB2.2
TB2.1
TB2.2
80
Detailed Description
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MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
6.10.16 eCOMP0, eCOMP1, SAC0, SAC1, SAC2, and SAC3 Interconnection
(MSP430FR235x Devices Only)
The high-performance analog modules of eCOMP0, SAC0, and SAC2 are internally connected (see 图 6-
1).
P2.0/COMP0.O
P1.0/COMP0.0/A0
P1.1/OA0O/COMP0.1/A1
P1.3/OA0+/A3
00
01
10
SAC0
12-bit DAC
+
SAC0
OA
–
P1.2/OA0-/A2
00
01
10
000
001
010
101
110
eCOMP0
6-bit DAC
SAC0
PGA
+
To Timer
Capture
Polarity
Selection
eCOMP0
–
P3.1/OA2O
P3.3/OA2+
P3.2/OA2-
000
001
010
101
110
Low-power
1.2V
00
01
10
SAC2
12-bit DAC
+
SAC2
OA
–
00
01
10
SAC2
PGA
图 6-1. eCOMP0, SAC0, SAC2 Interconnection
版权 © 2018–2019, Texas Instruments Incorporated
Detailed Description
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MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
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www.ti.com.cn
The high-performance analog modules of eCOMP1, SAC1, and SAC3 are internally connected (see 图 6-
2):
P2.1/COMP1.O
P2.5/COMP1.0
P2.4/COMP1.1
P1.5/OA1O/A5
P1.7/OA1+/A7
00
01
10
SAC1
12-bit
DAC
+
SAC1
OA
–
P1.6/OA1-/A6
00
01
10
000
001
010
101
110
eCOMP1
6-bit
DAC
SAC1
PGA
+
Polarity
Selection
To Timer
Capture
eCOMP1
–
P3.5/OA3O
P3.7/OA3+
P3.6/OA3-
000
001
010
101
110
Low-power
1.2 V
00
01
10
SAC3
12-bit
DAC
+
SAC3
OA
–
00
01
10
SAC3
PGA
图 6-2. eCOMP1, SAC1, SAC3 Interconnection
82
Detailed Description
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
6.10.17 Cross-Chip Interconnection (SACx are MSP430FR235x Devices Only)
This section describes the cross-chip interconnections in a full-featured view.
Timer_B0
Timer_B1
TB0CLK
ACLK
00
01
10
11
TB1CLK
ACLK
00
01
10
11
16-bit Counter
SMCLK
16-bit Counter
P1.0/A0
from CapTouch
DVSS
SMCLK
P2.0/COMP0.O
P1.1/A1
P1.2/A2
RTC
ACLK
DVSS
DVCC
00
01
10
11
P1.0/COMP0.0/A0
TB0.0A
TB0.0B
00
01
10
11
CCR0
P1.3/A3
TB1.0A
TB1.0B
CCR0
DVSS
DVCC
P1.4/A4
P1.5/A5
P1.1/OA0O/COMP0.1/A1
RTC
Counter
P1.6
00
01
10
11
RTC
Overflow
P1.6/A6
Software trigger
from RTC
from COMP
TB0.1A
TB0.1B
P1.6
P2.0
00
01
10
11
00
01
10
11
CCR1
DVSS
DVCC
TB1.1A
TB1.1B
P2.0
12-bit
ADC
CCR1
P1.7/A7
from TB1.1B
from COMP
DVSS
DVCC
P1.3/OA0+/A3
00
01
10
P5.0/A8
DACLSEL
HW Trigger
Selection
P5.1/A9
SAC0
12-bit DAC
from TB2.1B
from TB2.2B
P1.7
from CapTouch
DVSS
00
01
10
11
+
10
11
SAC0
OA
–
TB0.2A
TB0.2B
P1.7
P2.1
00
01
10
11
CCR2
P5.2/A10
TB1.2A
TB1.2B
P2.1
CCR2
P1.2/OA0-/A2
00
01
10
DVCC
DVSS
DVCC
P5.3/A11
TB0OUTH
TB1OUTH
On-chip Temperature Sensor (A12)
1.5-V Reference Voltage (A13)
DVSS (A14)
TB1TRG
TB0TRG
000
001
010
101
110
0
1
1
0
C0O
C0O
DVCC (A15)
eCOMP0
6-bit DAC
SAC0
PGA
TB0TRGSEL
TB1TRGSEL
+
Polarity
Selection
eCOMP0
–
P3.1/OA2O
000
001
010
101
110
Low-power
1.2V
Coding
P3.3/OA2+
00
01
10
DACLSEL
Infrared
Logic
Carrier
Data
P1.7/UCA0TXD/UCA0SIMO
SAC2
12-bit DAC
from TB2.1B
from TB2.2B
UCA0TXD/UCA0SIMO
+
10
11
eUSCI_A0
SAC2
OA
–
P3.2/OA2-
00
01
10
UCB1SOMI
UCB1SIMO
UCB1CLK
UCB1STE
RX
P5.0/MFM.RX
Manchester
Function Module
(MFM)
eUSCI_B1
(SPI Slave)
TX
P5.1/MFM.TX
Transmit Transmit
Complete Event Start Trigger
SAC2
PGA
Timer_B3
Timer_B2
P2.1/COMP1.O
P2.5/COMP1.0
P2.4/COMP1.1
P1.5/OA1O/A5
TB2CLK
00
01
10
11
TB3CLK
00
01
10
11
ACLK
ACLK
16-Bit Counter
16-bit Counter
SMCLK
SMCLK
TBD
00
01
10
11
00
01
10
11
MFM Complete Event
DVSS
TB2.0A
CCR0
TB2.0B
TB3.0A
TB3.0B
CCR0
CCR1
CCR2
MFM
Start
Trigger
DVSS
DVCC
DVCC
P5.0
00
01
10
11
P6.0
00
01
10
11
TB2.1A
CCR1
TB2.1B
P5.0
TB3.1A
TB3.1B
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
DVSS
DVCC
to SAC DAC Update Trigger 10DVSS
DVCC
UCA1TXD
UCA1RXD
eUSCI_A1
(UART)
P1.7/OA1+/A7
00
01
10
DACLSEL
SAC1
12-bit DAC
from TB2.1B
from TB2.2B
P5.1
00
01
10
11
P6.1
00
01
10
11
+
10
11
PDIR4.0
P4.0/UCA1STE/ISOTXD/ISORXD
SAC1
OA
–
TB2.2A
CCR2
TB2.2B
P5.1
TB3.2A
TB3.2B
DVSS
DVCC
to SAC DAC Update Trigger 11DVSS
P1.6/OA1-/A6
00
01
10
DVCC
TB2OUTH
TB1OUTH
P6.2
00
01
10
11
000
001
010
101
110
TB3.3A
TB3.3B
CCR3
CCR4
CCR5
CCR6
DVSS
DVCC
eCOMP1
6-bit DAC
SAC1
PGA
TB2TRG
+
eCOMP1
1
Polarity
Selection
0
P6.3
00
01
10
11
P3.5/OA3O
–
TB3.4A
TB3.4B
000
001
010
101
110
DVSS
DVCC
TB2TRGSEL
Low-power
1.2V
1
0
TB3OUTH
P3.7/OA3+
00
01
10
P6.4
00
01
10
11
TB3TRGSEL
DACLSEL
TB3.5A
TB3.5B
DVSS
DVCC
SAC3
12-bit DAC
from TB2.1B
from TB2.2B
+
10
11
SAC3
OA
–
P3.6/OA3-
00
01
10
P6.5
00
01
10
11
TB3.6A
TB3.6B
DVSS
DVCC
SAC3
PGA
图 6-3. Cross-Chip Interconnection
版权 © 2018–2019, Texas Instruments Incorporated
Detailed Description
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ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
6.10.18 Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The EEM on these devices has the following features:
•
•
•
•
•
Three hardware triggers or breakpoints on memory access
One hardware trigger or breakpoint on CPU register write access
Up to four hardware triggers can be combined to form complex triggers or breakpoints
One cycle counter
Clock control on module level
6.10.19 Peripheral File Map
表 6-33 lists the base address and the memory size of each peripheral's registers.
表 6-33. Peripherals Summary
MODULE NAME
Special Functions (see 表 6-34)
BASE ADDRESS
0100h
0120h
0140h
0180h
01A0h
01C0h
01CCh
0200h
0220h
0240h
0300h
0380h
03C0h
0400h
0440h
04C0h
0500h
0540h
0580h
05C0h
0660h
06C0h
0700h
08E0h
0900h
0C80h
0C90h
0CA0h
0CB0h
SIZE
0010h
0020h
0040h
0020h
0010h
0008h
0002h
0020h
0020h
0020h
0010h
0030h
0030h
0030h
0030h
0030h
0020h
0030h
0020h
0030h
0020h
0010h
0040h
0020h
0020h
0010h
0010h
0010h
0010h
PMM (see 表 6-35)
SYS (see 表 6-36)
CS (see 表 6-37)
FRAM (see 表 6-38)
CRC (see 表 6-39)
WDT (see 表 6-40)
Port P1, P2 (see 表 6-41)
Port P3, P4 (see 表 6-42)
Port P5, P6 (see 表 6-43)
RTC (see 表 6-44)
Timer0_B3 (see 表 6-45)
Timer1_B3 (see 表 6-46)
Timer2_B3 (see 表 6-47)
Timer3_B7 (see 表 6-48)
MPY32 (see 表 6-49)
eUSCI_A0 (see 表 6-50)
eUSCI_B0 (see 表 6-51)
eUSCI_A1 (see 表 6-52)
eUSCI_B1 (see 表 6-53)
Backup Memory (see 表 6-54)
ICC (see 表 6-55)
ADC (see 表 6-56)
eCOMP0 (see 表 6-57)
eCOMP1 (see 表 6-58)
SAC0 (see 表 6-59)(1)
SAC1 (see 表 6-60)(1)
SAC2 (see 表 6-61)(1)
SAC3 (see 表 6-62)(1)
(1) MSP430FR235x devices only
84
Detailed Description
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www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
表 6-34. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
00h
SFR interrupt enable
SFR interrupt flag
SFRIE1
SFRIFG1
SFRRPCR
02h
SFR reset pin control
04h
表 6-35. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
ACRONYM
PMMCTL0
PMMCTL1
PMMCTL2
PMMIFG
OFFSET
00h
PMM control 0
PMM control 1
PMM control 2
PMM interrupt flags
PM5 control 0
02h
04h
0Ah
PM5CTL0
10h
表 6-36. SYS Registers (Base Address: 0140h)
REGISTER DESCRIPTION
ACRONYM
SYSCTL
OFFSET
00h
System control
Bootloader configuration area
JTAG mailbox control
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
JTAG mailbox output 1
User NMI vector generator
System NMI vector generator
Reset vector generator
System configuration 0
System configuration 1
System configuration 2
System configuration 3
SYSBSLC
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSUNIV
SYSSNIV
SYSRSTIV
SYSCFG0
SYSCFG1
SYSCFG2
SYSCFG3
02h
06h
08h
0Ah
0Ch
0Eh
1Ah
1Ch
1Eh
20h
22h
24h
26h
表 6-37. CS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
ACRONYM
CSCTL0
CSCTL1
CSCTL2
CSCTL3
CSCTL4
CSCTL5
CSCTL6
CSCTL7
CSCTL8
OFFSET
00h
CS control 0
CS control 1
CS control 2
CS control 3
CS control 4
CS control 5
CS control 6
CS control 7
CS control 8
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
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Detailed Description
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www.ti.com.cn
表 6-38. FRAM Registers (Base Address: 01A0h)
REGISTER DESCRIPTION
ACRONYM
FRCTL0
OFFSET
FRAM control 0
General control 0
General control 1
00h
04h
06h
GCCTL0
GCCTL1
表 6-39. CRC Registers (Base Address: 01C0h)
REGISTER DESCRIPTION
ACRONYM
CRC16DI
OFFSET
00h
CRC data input
CRC data input reverse byte
CRC initialization and result
CRC result reverse byte
CRCDIRB
CRCINIRES
CRCRESR
02h
04h
06h
表 6-40. WDT Registers (Base Address: 01CCh)
REGISTER DESCRIPTION
ACRONYM
OFFSET
Watchdog timer control
WDTCTL
00h
表 6-41. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
ACRONYM
P1IN
OFFSET
00h
02h
04h
06h
0Ah
0Ch
0Eh
16h
18h
1Ah
1Ch
01h
03h
05h
07h
0Bh
0Dh
1Eh
17h
19h
1Bh
1Dh
Port P1 input
Port P1 output
P1OUT
P1DIR
P1REN
P1SEL0
P1SEL1
P1IV
Port P1 direction
Port P1 pulling enable
Port P1 selection 0
Port P1 selection 1
Port P1 interrupt vector word
Port P1 complement selection
Port P1 interrupt edge select
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
P1SELC
P1IES
P1IE
P1IFG
P2IN
Port P2 output
P2OUT
P2DIR
P2REN
P2SEL0
P2SEL1
P2IV
Port P2 direction
Port P2 pulling enable
Port P2 selection 0
Port P2 selection 1
Port P2 interrupt vector word
Port P2 complement selection
Port P2 interrupt edge select
Port P2 interrupt enable
Port P2 interrupt flag
P2SELC
P2IES
P2IE
P2IFG
86
Detailed Description
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www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
表 6-42. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
00h
02h
04h
06h
0Ah
0Ch
0Eh
16h
18h
1Ah
1Ch
01h
03h
05h
07h
0Bh
0Dh
1Eh
17h
19h
1Bh
1Dh
Port P3 input
P3IN
P3OUT
P3DIR
P3REN
P3SEL0
P3SEL1
P3IV
Port P3 output
Port P3 direction
Port P3 pulling enable
Port P3 selection 0
Port P3 selection 1
Port P3 interrupt vector word
Port P3 complement selection
Port P3 interrupt edge select
Port P3 interrupt enable
Port P3 interrupt flag
Port P4 input
P3SELC
P3IES
P3IE
P3IFG
P4IN
Port P4 output
P4OUT
P4DIR
P4REN
P4SEL0
P4SEL1
P4IV
Port P4 direction
Port P4 pulling enable
Port P4 selection 0
Port P4 selection 1
Port P4 interrupt vector word
Port P4 complement selection
Port P4 interrupt edge select
Port P4 interrupt enable
Port P4 interrupt flag
P4SELC
P4IES
P4IE
P4IFG
表 6-43. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
ACRONYM
P5IN
OFFSET
00h
Port P5 input
Port P5 output
P5OUT
P5DIR
02h
Port P5 direction
04h
Port P5 pulling enable
Port P5 selection 0
Port P5 selection 1
Port P5 complement selection
Port P6 input
P5REN
P5SEL0
P5SEL1
P5SELC
P6IN
06h
0Ah
0Ch
16h
01h
Port P6 output
P6OUT
P6DIR
03h
Port P6 direction
05h
Port P6 pulling enable
Port P6 selection 0
Port P6 selection 1
Port P6 complement selection
P6REN
P6SEL0
P6SEL1
P6SELC
07h
0Bh
0Dh
17h
表 6-44. RTC Registers (Base Address: 0300h)
REGISTER DESCRIPTION
ACRONYM
RTCCTL
RTCIV
OFFSET
00h
RTC control
RTC interrupt vector
RTC modulo
04h
RTCMOD
RTCCNT
08h
RTC counter
0Ch
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Detailed Description
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ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
表 6-45. Timer0_B3 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
ACRONYM
TB0CTL
OFFSET
TB0 control
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TB0 counter
TB0CCTL0
TB0CCTL1
TB0CCTL2
TB0R
Capture/compare 0
Capture/compare 1
Capture/compare 2
TB0 expansion 0
TB0CCR0
TB0CCR1
TB0CCR2
TB0EX0
TB0 interrupt vector
TB0IV
表 6-46. Timer1_B3 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
ACRONYM
TB1CTL
OFFSET
00h
TB1 control
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TB1 counter
TB1CCTL0
TB1CCTL1
TB1CCTL2
TB1R
02h
04h
06h
10h
Capture/compare 0
Capture/compare 1
Capture/compare 2
TB1 expansion 0
TB1CCR0
TB1CCR1
TB1CCR2
TB1EX0
12h
14h
16h
20h
TB1 interrupt vector
TB1IV
2Eh
表 6-47. Timer2_B3 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
ACRONYM
TB2CTL
OFFSET
00h
TB2 control
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TB2 counter
TB2CCTL0
TB2CCTL1
TB2CCTL2
TB2R
02h
04h
06h
10h
Capture/compare 0
Capture/compare 1
Capture/compare 2
TB2 expansion 0
TB2CCR0
TB2CCR1
TB2CCR2
TB2EX0
12h
14h
16h
20h
TB2 interrupt vector
TB2IV
2Eh
88
Detailed Description
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ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
表 6-48. Timer3_B7 Registers (Base Address: 0440h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Eh
TB3 control
TB3CTL
TB3CCTL0
TB3CCTL1
TB3CCTL2
TB3CCTL3
TB3CCTL4
TB3CCTL5
TB3CCTL6
TB3R
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
Capture/compare control 3
Capture/compare control 4
Capture/compare control 5
Capture/compare control 6
TB3 counter
Capture/compare 0
TB3CCR0
TB3CCR1
TB3CCR2
TB3CCR3
TB3CCR4
TB3CCR5
TB3CCR6
TB3EX0
Capture/compare 1
Capture/compare 2
Capture/compare 3
Capture/compare 4
Capture/compare 5
Capture/compare 6
TB3 expansion 0
TB3 interrupt vector
TB3IV
表 6-49. MPY32 Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
ACRONYM
MPY
OFFSET
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
16-bit operand 1 – multiply
16-bit operand 1 – signed multiply
16-bit operand 1 – multiply accumulate
16-bit operand 1 – signed multiply accumulate
16-bit operand 2
MPYS
MAC
MACS
OP2
16 × 16 result low word
RESLO
RESHI
16 × 16 result high word
16 × 16 sum extension
SUMEXT
MPY32L
MPY32H
MPYS32L
MPYS32H
MAC32L
MAC32H
MACS32L
MACS32H
OP2L
32-bit operand 1 – multiply low word
32-bit operand 1 – multiply high word
32-bit operand 1 – signed multiply low word
32-bit operand 1 – signed multiply high word
32-bit operand 1 – multiply accumulate low word
32-bit operand 1 – multiply accumulate high word
32-bit operand 1 – signed multiply accumulate low word
32-bit operand 1 – signed multiply accumulate high word
32-bit operand 2 – low word
32-bit operand 2 – high word
OP2H
32 × 32 result 0 – least significant word
32 × 32 result 1
RES0
RES1
32 × 32 result 2
RES2
32 × 32 result 3 – most significant word
MPY32 control 0
RES3
MPY32CTL0
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Detailed Description
89
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
表 6-50. eUSCI_A0 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
eUSCI_A control word 0
ACRONYM
UCA0CTLW0
UCA0CTLW1
UCA0BR0
OFFSET
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ah
1Ch
1Eh
eUSCI_A control word 1
eUSCI_A control rate 0
eUSCI_A control rate 1
eUSCI_A modulation control
eUSCI_A status
UCA0BR1
UCA0MCTLW
UCA0STAT
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL
lUCA0IRTCTL
IUCA0IRRCTL
UCA0IE
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
UCA0IFG
UCA0IV
表 6-51. eUSCI_B0 Registers (Base Address: 0540h)
REGISTER DESCRIPTION
ACRONYM
UCB0CTLW0
UCB0CTLW1
UCB0BR0
OFFSET
00h
eUSCI_B control word 0
eUSCI_B control word 1
eUSCI_B bit rate 0
02h
06h
eUSCI_B bit rate 1
UCB0BR1
07h
eUSCI_B status word
UCB0STATW
UCB0TBCNT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA0
UCB0I2COA1
UCB0I2COA2
UCB0I2COA3
UCB0ADDRX
UCB0ADDMASK
UCB0I2CSA
UCB0IE
08h
eUSCI_B byte counter threshold
eUSCI_B receive buffer
eUSCI_B transmit buffer
eUSCI_B I2C own address 0
eUSCI_B I2C own address 1
eUSCI_B I2C own address 2
eUSCI_B I2C own address 3
eUSCI_B receive address
eUSCI_B address mask
eUSCI_B I2C slave address
eUSCI_B interrupt enable
eUSCI_B interrupt flags
eUSCI_B interrupt vector word
0Ah
0Ch
0Eh
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Ah
2Ch
2Eh
UCB0IFG
UCB0IV
90
Detailed Description
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
表 6-52. eUSCI_A1 Registers (Base Address: 0580h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
00h
eUSCI_A control word 0
eUSCI_A control word 1
eUSCI_A control rate 0
eUSCI_A control rate 1
eUSCI_A modulation control
eUSCI_A status
UCA1CTLW0
UCA1CTLW1
UCA1BR0
02h
06h
UCA1BR1
07h
UCA1MCTLW
UCA1STAT
UCA1RXBUF
UCA1TXBUF
UCA1ABCTL
lUCA1IRTCTL
IUCA1IRRCTL
UCA1IE
08h
0Ah
0Ch
0Eh
10h
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
12h
13h
1Ah
1Ch
1Eh
UCA1IFG
UCA1IV
表 6-53. eUSCI_B1 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
ACRONYM
UCB1CTLW0
UCB1CTLW1
UCB1BR0
OFFSET
00h
eUSCI_B control word 0
eUSCI_B control word 1
eUSCI_B bit rate 0
02h
06h
eUSCI_B bit rate 1
UCB1BR1
07h
eUSCI_B status word
UCB1STATW
UCB1TBCNT
UCB1RXBUF
UCB1TXBUF
UCB1I2COA0
UCB1I2COA1
UCB1I2COA2
UCB1I2COA3
UCB1ADDRX
UCB1ADDMASK
UCB1I2CSA
UCB1IE
08h
eUSCI_B byte counter threshold
eUSCI_B receive buffer
eUSCI_B transmit buffer
eUSCI_B I2C own address 0
eUSCI_B I2C own address 1
eUSCI_B I2C own address 2
eUSCI_B I2C own address 3
eUSCI_B receive address
eUSCI_B address mask
eUSCI_B I2C slave address
eUSCI_B interrupt enable
eUSCI_B interrupt flags
eUSCI_B interrupt vector word
0Ah
0Ch
0Eh
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Ah
2Ch
2Eh
UCB1IFG
UCB1IV
版权 © 2018–2019, Texas Instruments Incorporated
Detailed Description
91
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
表 6-54. Backup Memory Registers (Base Address: 0660h)
REGISTER DESCRIPTION
ACRONYM
BAKMEM0
BAKMEM1
BAKMEM2
BAKMEM3
BAKMEM4
BAKMEM5
BAKMEM6
BAKMEM7
BAKMEM8
BAKMEM9
BAKMEM10
BAKMEM11
BAKMEM12
BAKMEM13
BAKMEM14
BAKMEM15
OFFSET
Backup memory 0
Backup memory 1
Backup memory 2
Backup memory 3
Backup memory 4
Backup memory 5
Backup memory 6
Backup memory 7
Backup memory 8
Backup memory 9
Backup memory 10
Backup memory 11
Backup memory 12
Backup memory 13
Backup memory 14
Backup memory 15
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
表 6-55. ICC Registers (Base Address: 06C0h)
REGISTER DESCRIPTION
ACRONYM
ICCSC
OFFSET
00h
ICC status and control
ICC mask virtual stack
ICCMVS
02h
ICC interrupt level setting 0
ICC interrupt level setting 1
ICC interrupt level setting 2
ICC interrupt level setting 3
ICCILSR0
ICCILSR1
ICCILSR2
ICCILSR3
04h
06h
08h
0Ah
表 6-56. ADC Registers (Base Address: 0700h)
REGISTER DESCRIPTION
ACRONYM
ADCCTL0
ADCCTL1
ADCCTL2
ADCLO
OFFSET
00h
ADC control 0
ADC control 1
02h
ADC control 2
04h
ADC window comparator low threshold
ADC window comparator high threshold
ADC memory control 0
ADC conversion memory
ADC interrupt enable
06h
ADCHI
08h
ADCMCTL0
ADCMEM0
ADCIE
0Ah
12h
1Ah
1Ch
1Eh
ADC interrupt flags
ADCIFG
ADC interrupt vector word
ADCIV
92
Detailed Description
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
表 6-57. eCOMP0 Registers (Base Address: 08E0h)
REGISTER DESCRIPTION
ACRONYM
CP0CTL0
OFFSET
00h
Comparator control 0
Comparator control 1
Comparator interrupt
CP0CTL1
02h
CP0INT
06h
Comparator interrupt vector
Comparator built-in DAC control
Comparator built-in DAC data
CP0IV
08h
CP0DACCTL
CP0DACDATA
10h
12h
表 6-58. eCOMP1 Registers (Base Address: 0900h)
REGISTER DESCRIPTION
ACRONYM
CP1CTL0
OFFSET
00h
Comparator control 0
Comparator control 1
CP1CTL1
02h
Comparator interrupt
CP1INT
06h
Comparator interrupt vector
Comparator built-in DAC control
Comparator built-in DAC data
CP1IV
08h
CP1DACCTL
CP1DACDATA
10h
12h
表 6-59. SAC0 Registers (Base Address: 0C80h, MSP430FR235x Devices Only)
REGISTER DESCRIPTION
ACRONYM
SAC0OA
OFFSET
00h
SAC0 OA control
SAC0 PGA control
SAC0 DAC control
SAC0 DAC data
SAC0PGA
SAC0DAC
SAC0DAT
SAC0DATSTS
SAC0IV
02h
04h
06h
SAC0 DAC status
SAC0 interrupt vector
08h
0Ah
表 6-60. SAC1 Registers (Base Address: 0C90h, MSP430FR235x Devices Only)
REGISTER DESCRIPTION
ACRONYM
SAC1OA
OFFSET
00h
SAC1 OA control
SAC1 PGA control
SAC1 DAC control
SAC1 DAC data
SAC1PGA
SAC1DAC
SAC1DAT
SAC1DATSTS
SAC1IV
02h
04h
06h
SAC1 DAC status
SAC1 interrupt vector
08h
0Ah
表 6-61. SAC2 Registers (Base Address: 0CA0h, MSP430FR235x Devices Only)
REGISTER DESCRIPTION
ACRONYM
SAC2OA
OFFSET
00h
SAC2 OA control
SAC2 PGA control
SAC2 DAC control
SAC2 DAC data
SAC2PGA
SAC2DAC
SAC2DAT
SAC2DATSTS
SAC2IV
02h
04h
06h
SAC2 DAC status
SAC2 interrupt vector
08h
0Ah
版权 © 2018–2019, Texas Instruments Incorporated
Detailed Description
93
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
表 6-62. SAC3 Registers (Base Address: 0CB0h, MSP430FR235x Devices Only)
REGISTER DESCRIPTION
ACRONYM
SAC3OA
OFFSET
SAC3 OA control
SAC3 PGA control
SAC3 DAC control
SAC3 DAC data
00h
02h
04h
06h
08h
0Ah
SAC3PGA
SAC3DAC
SAC3DAT
SAC3DATSTS
SAC3IV
SAC3 DAC status
SAC3 interrupt vector
94
Detailed Description
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
6.11 Input/Output Diagrams
6.11.1 Port P1 Input/Output With Schmitt Trigger
图 6-4 shows the port diagram. 表 6-63 summarizes the selection of the port function.
A0..A7
OA0+, OA0-, OA0O
OA1+, OA1-, OA1O
COMP0.0, COMP0.1
P1REN.x
P1DIR.x
From Module 1
From Module 2
00
01
10
DVSS
DVCC
0
1
P1OUT.x
From Module 1
From Module 2
00
01
10
P1SEL0
P1SEL1
EN
D
To module
P1IN.x
P1IE.x
Bus
Keeper
P1 Interrupt
D
S
Q
P1.0/UCB0STE/SMCLK/COMP0.0/A0/Veref+
P1.1/UCB0CLK/ACLK/OA0O/COMP0.1/A1
P1.2/UCB0SIMO/UCB0SDA/TB0TRG/OA0-/A2/Veref-
P1.3/UCB0SOMI/UCB0SCL/A3
P1IFG.x
Edge
Select
P1.4/UCA0STE/TCK/A4
P1.5/UCA0CLK/TMS/A5
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/A7/VREF+
P1IES.x
From JTAG
To JTAG
图 6-4. Port P1 Input/Output With Schmitt Trigger
版权 © 2018–2019, Texas Instruments Incorporated
Detailed Description
95
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
表 6-63. Port P1 Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SELx
00
JTAG
N/A
P1.0 (I/O)
UCB0STE
SMCLK
VSS
I: 0; O: 1
X
01
N/A
P1.0/UCB0STE/SMCLK/
COMP0.0/A0/Veref+
0
1
10
N/A
0
COMP0.0, A0/Veref+
P1.1 (I/O)
X
11
0
N/A
N/A
N/A
I: 0; O: 1
UCB0CLK
X
01
P1.1/UCB0CLK/ACLK/
OA0O/COMP0.1/A1
1
ACLK
1
10
N/A
VSS
0
OA0O(2), COMP0.1, A1
X
11
00
01
10
11
00
01
11
00
01
11
X
N/A
N/A
P1.2 (I/O)
I: 0; O: 1
P1.2/UCB0SIMO/
UCB0SDA/TB0TRG/
OA0-/A2/Veref-
UCB0SIMO/UCB0SDA
TB0TRG
OA0-(2), A2/Veref-
X
N/A
2
3
4
0
N/A
X
N/A
P1.3 (I/O)
I: 0; O: 1
N/A
P1.3/UCB0SOMI/
UCB0SCL/OA0+/A3
UCB0SOMI/UCB0SCL
OA0+(2), A3
P1.4 (I/O)
X
N/A
X
N/A
I: 0; O: 1
Disabled
Disabled
Disabled
TCK
UCA0STE
X
P1.4/UCA0STE/TCK/A4
A4
X
JTAG TCK
X
P1.5 (I/O)
I: 0; O: 1
00
01
11
X
Disabled
Disabled
Disabled
TMS
UCA0CLK
OA1O(2), A5
X
P1.5/UCA0CLK/TMS/
OA1O/A5
5
6
X
JTAG TMS
X
P1.6 (I/O)
I: 0; O: 1
00
01
Disabled
Disabled
UCA0RXD/UCA0SOMI
TB0.CCI1A
X
P1.6/UCA0RXD/
UCA0SOMI/TB0.1/TDI/
TCLK/OA1-/A6
0
10
Disabled
TB0.1
1
OA1-(2), A6
JTAG TDI/TCLK
P1.7 (I/O)
X
11
X
Disabled
TDI/TCLK
Disabled
Disabled
X
I: 0; O: 1
00
01
UCA0TXD/UCA0SIMO
TB0.CCI2A
X
0
P1.7/UCA0TXD/
UCA0SIMO/TB0.2/TDO/
OA1+/A7/VREF+
7
10
Disabled
TB0.2
1
OA1+(2), A7, VREF+
X
X
11
X
Disabled
TDO
JTAG TDO
(1) X = don't care
(2) MSP430FR235x devices only
96
Detailed Description
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
6.11.2 Port P2 Input/Output With Schmitt Trigger
图 6-5 shows the port diagram. 表 6-64 summarizes the selection of the port function.
COMP1.0, COMP1.1
P2REN.x
P2DIR.x
From Module 1
From Module 2
00
01
10
DVSS
DVCC
0
1
P2OUT.x
From Module 1
From Module 2
00
01
10
P2SEL0
P2SEL1
EN
D
To module
P2IN.x
P2IE.x
Bus
Keeper
P2 Interrupt
D
S
Q
P2.0/TB1.1/COMP0.O
P2.1/TB1.2/COMP1.O
P2.2/TB1CLK
P2.3/TB1TRG
P2.4/COMP1.1
P2.5/COMP1.0
P2.6/MCLK/XOUT
P2.7/TB0CLK/XIN
P2IFG.x
P2IES.x
Edge
Select
图 6-5. Port P2 Input/Output With Schmitt Trigger
版权 © 2018–2019, Texas Instruments Incorporated
Detailed Description
97
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
表 6-64. Port P2 Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SELx
P2.0 (I/O)
TB1.CCI1A
TB1.1
I: 0; O: 1
00
0
P2.0/TB1.1/COMP0.O
0
01
1
COMP0.O
P2.1 (I/O)0
TB1.CCI2A
TB1.2
1
10
00
I: 0; O: 1
0
P2.1/TB1.2
1
01
1
COMP1.O
P2.2 (I/O)
TB1CLK
P2.3 (I/O)
TB1TRG
VSS
1
10
00
01
00
I: 0; O: 1
P2.2/TB1CLK
2
3
0
I: 0; O: 1
P2.3/UCB0CLK/TB1TRG
0
01
1
P2.4 (I/O)
COMP1.1
P2.5 (I/O)
COMP1.0
P2.6 (I/O)
MCLK
I: 0; O: 1
00
11
00
11
00
P2.4/COMP1.1
P2.5/COMP1.0
4
5
X
I: 0; O: 1
X
I: 0; O: 1
1
P2.6/MCLK/XOUT
6
7
01
VSS
0
XOUT
X
10
00
P2.7 (I/O)
TB0CLK
VSS
I: 0; O: 1
0
1
X
P2.7/TB0CLK/XIN
(1) X = don't care
01
10
XIN
98
Detailed Description
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
6.11.3 Port P3 Input/Output With Schmitt Trigger
图 6-6 shows the port diagram. 表 6-65 summarizes the selection of the port function.
OA2O, OA2-, OA2+
OA3O, OA3-, OA3+
P3REN.x
P3DIR.x
From Module 1
From Module 2
00
01
10
DVSS
DVCC
0
1
P3OUT.x
From Module 1
From Module 2
00
01
10
P3SEL0
P3SEL1
EN
D
To module
P3IN.x
P3IE.x
Bus
Keeper
P3 Interrupt
D
S
Q
P3.0/MCLK
P3.1/OA2O
P3.2/OA2-
P3.3/OA2+
P3.4/SMCLK
P3.5/OA3O
P3.6/OA3-
P3.7/OA3+
P3IFG.x
P3IES.x
Edge
Select
图 6-6. Port P3 Input/Output With Schmitt Trigger
版权 © 2018–2019, Texas Instruments Incorporated
Detailed Description
99
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
表 6-65. Port P3 Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P3.x)
x
FUNCTION
P3DIR.x
P3SELx
P3.0 (I/O)
MCLK
I: 0; O: 1
00
P3.0/MCLK
0
1
01
VSS
0
P3.1 (I/O)
OA2O(2)
P3.2 (I/O)
OA2-(2)
I: 0; O: 1
00
11
00
11
00
11
00
P3.1/OA2O
P3.2/OA2-
P3.3/OA2+
1
2
3
X
I: 0; O: 1
X
P3.3 (I/O)
OA2+(2)
P3.4 (I/O)
SMCLK
VSS
I: 0; O: 1
X
I: 0; O: 1
P3.4/SMCLK
4
1
01
0
P3.5 (I/O)
OA3O(2)
P3.6 (I/O)
OA3-(2)
I: 0; O: 1
00
11
00
11
00
11
P3.5/OA3O
P3.6/OA3-
5
6
7
X
I: 0; O: 1
X
P3.7 (I/O)
OA3+(2)
I: 0; O: 1
X
P3.7/OA3+
(1) X = don't care
(2) MSP430FR235x devices only
100
Detailed Description
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com.cn
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
6.11.4 Port P4 Input/Output With Schmitt Trigger
图 6-7 shows the port diagram. 表 6-66 summarizes the selection of the port function.
P4REN.x
P4DIR.x
From Module 1
From Module 2
00
01
10
DVSS
DVCC
0
1
P4OUT.x
From Module 1
From Module 2
00
01
10
P4SEL0
P4SEL1
EN
D
To module
P4IN.x
P4IE.x
Bus
Keeper
P4 Interrupt
D
S
Q
P4.0/UCA1STE/ISOTXD/ISORXD
P4.1/UCA1CLK
P4IFG.x
P4IES.x
P4.2/UCA1RXD/UCA1SOMI/UCA1RXD
P4.3/UCA1TXD/UCA1SIMO/UCA1TXD
P4.4/UCB1STE
P4.5/UCB1CLK
P4.6/UCB1SIMO/UCB1SDA
P4.7/UCB1SOMI/UCB1SCL
Edge
Select
图 6-7. Port P4 Input/Output With Schmitt Trigger
版权 © 2018–2019, Texas Instruments Incorporated
Detailed Description
101
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
www.ti.com.cn
表 6-66. Port P4 Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x
P4SELx
P4.0 (I/O)
UCA1STE
I: 0; O: 1
00
01
X
P4.0/UCA1STE
0
UCA1RXD, TB3.CCI2B
UCA1TXD logic-AND TB3.2B
P4.1 (I/O)
0
10
1
I: 0; O: 1
00
01
00
01
10
00
01
10
00
01
00
01
00
01
00
01
P4.1/UCA1CLK
1
2
UCA1CLK
X
P4.2 (I/O)
I: 0; O: 1
P4.2/UCA1RXD/
UCA1SOMI/UCA1RXD
UCA1RXD/UCA1SOMI
UCA1RXD
X
X
P4.3 (I/O)
I: 0; O: 1
P4.3/UCA1TXD/
UCA1SIMO/UCA1TXD
3
UCA1TXD/UCA1SIMO
UCA1TXD
X
X
P4.4 (I/O)
I: 0; O: 1
P4.4/UCB1STE
4
5
6
7
UCB1STE
X
P4.5 (I/O)
I: 0; O: 1
P4.5/UCB1CLK
UCB1CLK
X
I: 0; O: 1
X
P4.6 (I/O)
P4.6/UCB1SIMO/UCB1SDA
UCB1SIMO/UCB1SDA
P4.7 (I/O)
I: 0; O: 1
X
P4.7/UCB1SOMI/UCB1SCL
(1) X = don't care
UCB1SOMI/UCB1SCL
102
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6.11.5 Port P5 Input/Output With Schmitt Trigger
图 6-8 shows the port diagram. 表 6-67 summarizes the selection of the port function.
A8, A9, A10, A11
P5REN.x
P5DIR.x
From Module 1
From Module 2
00
01
10
DVSS
DVCC
0
1
P5OUT.x
From Module 1
From Module 2
00
01
10
P5SEL0
P5SEL1
EN
D
To module
P5IN.x
Bus
Keeper
P5.0/TB2.1/MFM.RX/A8
P5.1/TB2.2/MFM.TX/A9
P5.2/TB2CLK/A10
P5.3/TB2TRG/A11
P5.4
图 6-8. Port P5 Input/Output With Schmitt Trigger
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表 6-67. Port P5 Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SELx
P5.0 (I/O)
TB2.CCI1A
TB2.1
I: 0; O: 1
00
I
01
P5.0/TB2.1/MFM.RX/A8
0
O
MFM.RX
A8
X
10
11
00
X
P5.1 (I/O)
TB2.CCI2A
TB2.2
I: 0; O: 1
I
01
P5.1/TB2.2/MFM.TX/A9
1
2
O
MFM.TX
A9
X
10
11
00
X
P5.2 (I/O)
TB2CLK
VSS
I: 0; O: 1
I
P5.2/TB2CLK/A10
P5.3/TB2TRG/A11
01
O
A10
X
11
00
P5.3 (I/O)
TB2TRG
VSS
I: 0; O: 1
I
3
4
01
O
X
A11
11
00
P5.4
P5.4 (I/O)
I: 0; O: 1
(1) X = don't care
104
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6.11.6 Port P6 Input/Output With Schmitt Trigger
图 6-9 shows the port diagram. 表 6-68 summarizes the selection of the port function.
P6REN.x
P6DIR.x
From Module 1
From Module 2
00
01
10
DVSS
DVCC
0
1
P6OUT.x
From Module 1
From Module 2
00
01
10
P6SEL0
P6SEL1
EN
D
To module
P6IN.x
Bus
Keeper
P6.0/TB3.1
P6.1/TB3.2
P6.2/TB3.3
P6.3/TB3.4
P6.4/TB3.5
P6.5/TB3.6
P6.6/TB3CLK
图 6-9. Port P6 Input/Output With Schmitt Trigger
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表 6-68. Port P6 Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P6.x)
x
FUNCTION
P6DIR.x
P6SELx
P6.0 (I/O)
TB3.CCI1A
TB3.1
I: 0; O: 1
00
01
00
01
00
01
00
01
00
01
00
01
00
01
P6.0/TB3.1
0
0
1
P6.1 (I/O)
TB3.CCI2A
TB3.2
I: 0; O: 1
P6.1/TB3.2
P6.2/TB3.3
P6.3/TB3.4
P6.4/TB3.5
P6.5/TB3.6
1
2
3
4
5
6
0
1
P6.2 (I/O)
TB3.CCI3A
TB3.3
I: 0; O: 1
0
1
P6.3 (I/O)
TB3.CCI4A
TB3.4
I: 0; O: 1
0
1
P6.4 (I/O)
TB3.CCI5A
TB3.5
I: 0; O: 1
0
1
P6.5 (I/O)
TB3.CCI6A
TB3.6
I: 0; O: 1
0
1
P6.6 (I/O)
TB3CLK
VSS
I: 0; O: 1
P6.6/TB3CLK
0
1
(1) X = don't care
106
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6.12 Device Descriptors (TLV)
表 6-69 lists the Device IDs. 表 6-70 lists the contents of the device descriptor tag-length-value (TLV)
structure.
表 6-69. Device IDs
DEVICE ID
DEVICE
1A04h
0C
1A05h
83
MSP430FR2355
MSP430FR2353
MSP430FR2155
MSP430FR2153
0D
83
1E
83
1D
83
表 6-70. Device Descriptors
DESCRIPTION
ADDRESS
VALUE
06h
Info length
1A00h
1A01h
1A02h
1A03h
1A04h
1A05h
1A06h
1A07h
1A08h
1A09h
1A0Ah
1A0Bh
1A0Ch
1A0Dh
1A0Eh
1A0Fh
1A10h
1A11h
1A12h
1A13h
CRC length
06h
Per unit
Per unit
CRC value(1)
Information block
(2)
Device ID
See
Hardware revision
Firmware revision
Die record tag
Per unit
Per unit
08h
Die record length
0Ah
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Lot wafer ID
Die record
Die X position
Die Y position
Test result
(1) CRC value covers the checksum from 0x1A04h to 0x1AF7h by applying CRC-CCITT-16 polynomial of x16 + x12 + x5 + 1
(2) MSP430FR235x devices only
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表 6-70. Device Descriptors (continued)
DESCRIPTION
ADC calibration tag
ADDRESS
VALUE
1A14h
1A15h
1A16h
1A17h
1A18h
1A19h
1A1Ah
1A1Bh
1A1Ch
1A1Dh
1A1Eh
1A1Fh
1A20h
1A21h
1A22h
1A23h
1A24h
1A25h
1A26h
1A27h
1A28h
1A29h
1A2Ah
1A2Bh
1A2Ch
1A2Dh
1A2Eh
1A2Fh
1A30h
1A31h
11h
ADC calibration length
10h
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
12h
ADC gain factor
ADC offset
ADC internal shared 1.5-V reference, temperature 30°C
ADC internal shared 1.5-V reference, high temperature(3)
ADC internal shared 2.0-V reference, temperature 30°C
ADC internal shared 2.0-V reference, high temperature(3)
ADC internal shared 2.5-V reference, temperature 30°C
ADC internal shared 2.5-V reference, high temperature(3)
ADC calibration
Calibration tag
Calibration length
0Ah
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Internal shared 1.5-V reference factor
Internal shared 2.0-V reference factor
Internal shared 2.5-V reference factor
DCO tap settings for 16 MHz, temperature 30°C
Reference and DCO
calibration
(4)
DCO tap settings for 24 MHz, temperature 30°C
(3) The calibration value is device dependent at 105°C.
(4) This value can be directly loaded into the DCO bits in the CSCTL0 register to get an accurate 24-MHz frequency at room temperature,
especially when MCU exits from LPM3 and below. TI also suggests to use a predivider to decrease the frequency if the temperature drift
might result an overshoot faster than 24 MHz.
108
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6.13 Identification
6.13.1 Revision Identification
The device revision information is shown as part of the top-side marking on the device package. The
device-specific errata sheet describes these markings. For links to all of the errata sheets for the devices
in this data sheet, see 节 8.4.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Hardware Revision" entries in 节 6.12.
6.13.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific
errata sheet describes these markings. For links to all of the errata sheets for the devices in this data
sheet, see 节 8.4.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Device ID" entries in 节 6.12.
6.13.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in
detail in the MSP430 Programming With the JTAG Interface.
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7 Applications, Implementation, and Layout
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI's customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their implementation to confirm system functionality.
7.1 Device Connection and Layout Fundamentals
This section discusses the recommended guidelines when designing with the MSP430 MCU. These
guidelines are to make sure that the device has proper connections for powering, programming,
debugging, and optimum analog performance.
7.1.1 Power Supply Decoupling and Bulk Capacitors
It is recommended to connect a combination of a 10-µF plus a 100-nF low-ESR ceramic decoupling
capacitor to the DVCC pin. Higher-value capacitors can be used but can impact supply rail ramp-up time.
Place the decoupling capacitors as close as possible to the pins that they decouple (within a few
millimeters).
DVCC
Digital
+
Power Supply
Decoupling
DVSS
10 µF
100 nF
图 7-1. Power Supply Decoupling
7.1.2 External Oscillator
Depending on the device variant (see 节 3), the device can support a low-frequency crystal (32 kHz) on
the LFXT pins, a high-frequency crystal on the HFXT pins, or both. External bypass capacitors for the
crystal oscillator pins are required.
It is also possible to apply digital clock signals to the LFXIN and HFXIN input pins that meet the
specifications of the respective oscillator if the appropriate LFXTBYPASS or HFXTBYPASS mode is
selected. In this case, the associated LFXOUT and HFXOUT pins can be used for other purposes. If they
are left unused, they must be terminated according to 节 4.6.
图 7-2 shows a typical connection diagram.
LFXIN
or
LFXOUT
or
HFXIN
HFXOUT
CL1
CL2
图 7-2. Typical Crystal Connection
110
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See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal
oscillator with MSP430 MCUs.
7.1.3 JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or
MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the
connections also support the MSP-GANG production programmers, thus providing an easy way to
program prototype boards, if desired. 图 7-3 shows the connections between the 14-pin JTAG connector
and the target device required to support in-system programming and debugging for 4-wire JTAG
communication. 图 7-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are
identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSP-
FET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an
alternate connection (pin 4 instead of pin 2). The VCC-sense feature senses the local VCC present on the
target board (that is, a battery or other local power supply) and adjusts the output signals accordingly. 图
7-3 and 图 7-4 show a jumper block that supports both scenarios of supplying VCC to the target board. If
this flexibility is not required, the desired VCC connections can be hard-wired to eliminate the jumper block.
Pins 2 and 4 must not be connected at the same time.
For additional design information regarding the JTAG interface, see the MSP430 hardware tools user’s
guide.
VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
DVCC
J2 (see Note A)
R1
47 kW
JTAG
RST/NMI/SBWTDIO
VCC TOOL
TDO/TDI
TDI
TDO/TDI
TDI
2
1
VCC TARGET
4
3
TMS
TMS
6
5
7
TEST
TCK
8
TCK
GND
RST
10
12
14
9
11
13
TEST/SBWTCK
DVSS
C1
1 nF
(see Note B)
Copyright © 2016, Texas Instruments Incorporated
A. If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,
make connection J2.
B. The upper limit for C1 is 1.1 nF when using current TI tools.
图 7-3. Signal Connections for 4-Wire JTAG Communication
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VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
J2 (see Note A)
DVCC
R1
47 kΩ
(see Note B)
JTAG
VCC TOOL
TDO/TDI
2
1
3
5
7
9
RST/NMI/SBWTDIO
VCC TARGET
4
6
TCK
8
GND
10
12
14
11
13
TEST/SBWTCK
DVSS
C1
1 nF
(see Note B)
Copyright © 2016, Texas Instruments Incorporated
A. Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the
debug or programming adapter.
B. The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access, and any capacitance that is attached to this signal can affect the ability to establish a connection with
the device. The upper limit for C1 is 1.1 nF when using current TI tools.
图 7-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
7.1.4 Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the special function
register (SFR), SFRRPCR.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing
specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is
edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the
external NMI. When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either
pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.
If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an
external 47-kΩ pullup resistor to the RST/NMI pin with a 2.2-nF pulldown capacitor. The pulldown
capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or
in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers.
See the MSP430FR4xx and MSP430FR2xx Family User's Guide for more information on the referenced
control registers and bits.
7.1.5 Unused Pins
For details on the connection of unused pins, see节 4.6.
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7.1.6 General Layout Recommendations
•
Proper grounding and short traces for external crystal to reduce parasitic capacitance. See MSP430
32-kHz Crystal Oscillators for recommended layout guidelines.
•
•
Proper bypass capacitors on DVCC, AVCC, and reference pins if used.
Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital
switching signals such as PWM or JTAG signals away from the oscillator circuit and ADC signals.
•
Proper ESD level protection should be considered to protect the device from unintended high-voltage
electrostatic discharge. See MSP430 System-Level ESD Considerations for guidelines.
7.1.7 Do's and Don'ts
During power up, power down, and device operation, the voltage difference between AVCC and DVCC
must not exceed the limits specified in the Absolute Maximum Ratings section. Exceeding the specified
limits can cause malfunction of the device including erroneous writes to RAM and FRAM.
7.2 Peripheral- and Interface-Specific Design Information
7.2.1 ADC Peripheral
7.2.1.1 Partial Schematic
DVSS
Using an external
VREF+/VEREF+
positive reference
+
100 nF
10 µF
Using an external
negative reference
VEREF-
+
10 µF
100 nF
图 7-5. ADC Grounding and Noise Considerations
7.2.1.2 Design Requirements
As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should
be followed to eliminate ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with
other analog or digital circuitry. This current can generate small unwanted offset voltages that can add to
or subtract from the reference or input voltages of the ADC. The general guidelines in 节 7.1.1 combined
with the connections shown in 图 7-5 prevent these offset voltages.
In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital
switching or switching power supplies can corrupt the conversion result. TI recommends a noise-free
design using separate analog and digital ground planes with a single-point connection to achieve high
accuracy.
图 7-5 shows the recommended decoupling circuit when an external voltage reference is used. The
internal reference module has a maximum drive current as described in the sections ADC Pin Enable and
1.2-V Reference Settings of the MSP430FR4xx and MSP430FR2xx Family User's Guide.
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The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are
selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage
enters the device. In this case, the 10-µF capacitor buffers the reference pin and filters low-frequency
ripple, and the 100-nF bypass capacitor filters high-frequency noise.
7.2.1.3 Layout Guidelines
Components that are shown in the partial schematic (see 图 7-5) should be placed as close as possible to
the respective device pins to avoid long traces, because they add additional parasitic capacitance,
inductance, and resistance on the signal.
Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),
because the high-frequency switching can be coupled into the analog signal.
7.3 ROM Libraries
The MSP430FR235x and MSP430FR215x devices in the MSP430FR4xx family have MSP430 Driver
Library and FFT Library in ROM.
MSP430 software libraries in ROM are tested to work with both Code Composer Studio and IAR
Embedded Workbench toolchains.
•
For the ROM image to be compatible between CCS and IAR tool chains, there are certain project
properties restrictions. See the TI.com attribute guide for more details.
•
To use DriverLib in ROM, #include "rom_driverlib.h". Header file checks continue to provide helpful
hints at build time until the user application adheres to __cc_rom.
•
•
To use FFTLib in ROM, #include "DSPLib.h". FFTLib is a subset of the MSP software library DSPLib.
For more information, see the MSP430 Driver Library for MSP430FR2xx_4xx ROM README and
MSP DSP Library ROM README in MSP430Ware. The library ROM image is located above the 64KB
memory address. Application code using ROM must be large code model (20-bit address pointer rather
than 16-bit address pointer).
Benefits of ROM library use include:
•
Code execution at clock speeds that exceed 8 MHz is faster from ROM than from FRAM, because the
code avoids FRAM wait states (except FRAM controller cache hits). Without FRAM wait states, code
execution performance is limited by only the processor clock, which is generally faster than other
subsystems. Executing code from RAM gives comparable performance, but the available RAM size is
typically more limited.
•
More nonvolatile storage (FRAM) available in the device is left for application code.
7.4 Typical Applications
表 7-1 lists TI reference designs that use the MSP430FR235x devices in real-world application scenarios.
Consult these designs for additional guidance regarding schematic, layout, and software implementation.
For the most up-to-date list of available TI reference designs, visit the TI reference designs library.
表 7-1. Tools and Reference Designs
DESIGN NAME
LINK
TIDM-01000
MSP-EXP430FR2355
4- to 20-mA Loop-Powered RTD Temperature Transmitter Reference Design With MSP430 Smart Analog Combo
MSP430FR2355 LaunchPad development kit
114
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8 器件和文档支持
8.1 使用入门
有关 MSP430™系列器件以及开发协助工具和库的更多信息,请访问 MSP430 超低功耗传感和测量 MCU
概述。
8.2 器件命名规则
为了标示产品开发周期所处的阶段,TI 为所有 MSP MCU 器件的部件号分配了前缀。每个 MSP MCU 商用
系列产品成员都具有以下两个前缀之一:MSP 或 XMS。这些前缀代表了产品开发的发展阶段,即从工程原
型 (XMS) 直到完全合格的生产器件 (MSP)。
XMS - 实验器件,不一定代表最终器件的电气规格
MSP - 完全合格的生产器件
XMS 器件在供货时附带如下免责声明:
“开发中的产品用于内部评估用途。”
MSP 器件的特性已经全部明确,并且器件的质量和可靠性已经完全论证。TI 的标准保修证书对该器件适
用。
预测显示原型器件 (XMS) 的故障率大于标准生产器件。由于这些器件的预计最终使用故障率尚不确定,德
州仪器 (TI) 建议不要将它们用于任何生产系统。请仅使用合格的生产器件。
TI 器件的命名规则还包括一个带有器件系列名称的后缀。此后缀表示温度范围、封装类型和配送形式。图 8-
1 提供了解读完整器件名称的图例。
MSP 430 FR
2
355 T PT
R
Processor Family
Distribution Format
Platform
Packaging
Memory Type
Temperature Range
Series
Feature Set
Processor Family
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
Platform
430 = MSP430 16-Bit Low-Power Microcontroller
FR = FRAM
Memory Type
Series
2 = FRAM 2 Series, up to 24 MHz without LCD
First and Second Digits:
SAC Level / ADC Channels / COMP / 16-bit Timers / I/Os FRAM (KB) / SRAM (KB)
Feature Set
Third Digit:
35 = SAC-L3 / Up to 12 / 2 / 4 / Up to 44
15 = No SAC / Up to 12 / 2 / 4 / Up to 44
5 = 32 / 4
3 = 16 / 2
Temperature Range T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Distribution Format
T = Small reel
R = Large reel
No marking = Tube or tray
图 8-1. 器件命名规则
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8.3 工具和软件
请参阅《适用于 MSP430™ MCU 的 Code Composer Studio™ IDE 用户指南》,以了解有关可用 功能)的
详细信息。
表 8-1 列出了 MSP430FR235x 和 MSP430FR215x 微控制器所 支持的 调试特性。
表 8-1. 硬件 特性
四线制
JTAG
两线制
JTAG
断点
(N)
跟踪缓冲 LPMx.5 调试支
MSP430 架构
范围断点
有
时钟控制
是
状态序列发生器
否
EEM 版本
器
持
MSP430Xv2
有
有
3
否
否
S
设计套件与评估模块
MSP430FR2355 LaunchPad 开发套件
MSP-EXP430FR2355 LaunchPad 开发套件是一个易于使用的评估模块 (EVM),该模块包含了在超低功耗
MSP430FR215x 和 MSP430FR235x FRAM 微控制器系列上开始进行开发所需要的所有资源,包括用于编
程、调试和能量测量的板载调试探针。
MSP-TS430PT48 目标开发板
MSP-TS430PT48 目标开发板是一款 48 引脚 ZIF 插座目标板,用于通过 JTAG 接口或 Spy-Bi-Wire(双线
制 JTAG)协议对 MSP430 MCU 进行系统内编程和调试。
软件
MSP430Ware™ 软件
MSP430Ware 软件集合了所有 MSP430 器件的代码示例、数据表以及其他设计资源,打包提供给用户。除
了提供已有 MSP430 设计资源的完整集合外,MSP430Ware 软件还包含名为 MSP 驱动程序库的高级
API。借助该库可以轻松地对 MSP430 硬件进行编程。MSP430Ware 软件以 CCS 组件或独立软件包两种形
式提供。
MSP430FR235x 和 MSP430FR215x 代码示例
根据不同应用需求配置各集成外设的每个 MSP 器件均具备相应的 C 代码示例。
MSP 驱动程序库
MSP 驱动程序库的抽象 API 提供易用的函数调用,无需直接操纵 MSP430 硬件的位与字节。完整的文档通
过具有帮助意义的 API 指南交付,其中包括有关每个函数调用和经过验证的参数的详细信息。开发人员可以
使用驱动程序库功能,以最低开销编写完整项目。
MSP EnergyTrace™ 技术
适用于 MSP430 微控制器的 EnergyTrace 技术是基于电能的代码分析工具,适用于测量和显示应用的电能
系统配置并帮助优化应用以实现超低功耗。
ULP(超低功耗)Advisor
ULP Advisor™软件是一款辅助工具,旨在指导开发人员编写更为高效的代码,从而充分利用 MSP430 和
MSP432 微控制器 独特 的超低 功耗™特性。ULP Advisor 的目标人群是微控制器的资深开发者和开发新
手,可以根据详尽的 ULP 检验表检查代码,以便最大限度地减少应用程序的能耗。在编译时,ULP Advisor
会提供通知和备注以突出显示代码中可以进一步优化的区域,进而实现更低功耗。
适用于 MSP 超低功耗微控制器的 FRAM 嵌入式软件实用程序
FRAM 实用程序旨在作为不断扩充的嵌入式软件实用程序集合,其中的实用程序充分利用 FRAM 的超低功
耗和近乎无限次的写入寿命。这些实用程序适用于 MSP430FRxx FRAM 微控制器并提供示例代码协助应用
程序开发。其中的实用程序包含功耗计算实用程序 (CTPL)。CTPL 是一套实用程序 API 集,通过 CTPL 能
够轻松使用 LPMx.5 低功耗模式以及强大的关断模式,允许应用程序在检测到功率损耗时节约能耗并恢复关
键的系统元件。
IEC60730 软件包
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IEC60730 MSP430 软件包经过专门开发,用于协助客户达到 IEC 60730-1:2010(家用及类似用途的自动化
电气控制 - 第 1 部分:一般要求)B 类产品的要求。其中涵盖家用电器、电弧检测器、电源转换器、电动工
具、电动自行车及其他诸多产品。IEC60730 MSP430 软件包可以嵌入在 MSP430 MCU 中 运行的客户应
用, 从而帮助客户简化其消费类器件在功能安全方面遵循 IEC 60730-1:2010 B 类规范的认证工作。
适用于 MSP 的定点数学库
MSP IQmath 和 Qmath 库是为 C 语言开发者提供的一套经过高度优化的高精度数学运算函数集合,能够将
浮点算法无缝嵌入 MSP430 和 MSP432 器件的定点代码中。这些例程通常用于计算密集型实时 应用, 而
优化的执行速度、高精度以及超低能耗通常是影响这些实时应用的关键因素。与使用浮点数学算法编写的同
等代码相比,使用 IQmath 和 Qmath 库可以大幅提高执行速度并显著降低能耗。
适用于 MSP430 的浮点数学库
TI 在低功耗和低成本微控制器领域锐意创新,为您提供 MSPMATHLIB。此标量函数的浮点数学库,能够充
分利用器件的智能外设,使速度最高达到标准 MSP430 数学函数的 26 倍。Mathlib 能够轻松集成到您的设
计中。该运算库免费使用并集成在 Code Composer Studio IDE 和 IAR Embedded Workbench IDE 中。
开发工具
适用于 MSP 微控制器的 Code Composer Studio™ 集成开发环境
Code Composer Studio (CCS) 集成开发环境 (IDE) 支持所有 MSP 微控制器器件。CCS 包含一整套用于开
发和调试嵌入式 应用的工具。它包含了优化的 C/C++ 编译器、源代码编辑器、项目构建环境、调试器、描
述器以及其他多种 功能。
IAR Embedded Workbench® IDE
适用于 MSP430 MCU 的 IAR Embedded Workbench IDE 是一套用于构建和调试基于 MSP430 微控制器的
嵌入式 应用 的完整 C/C++ 编译器工具链。该调试器可用于源代码和反汇编代码,而且支持复杂代码和数据
断点。它还提供了硬件仿真器,可在未连接实际目标的情况下进行调试。
Uniflash 独立闪存工具
UniFlash 独立闪存工具用于在 TI MCU 上对片上闪存进行编程。Uniflash 具有 GUI、命令行和脚本界面。
Uniflash 软件工具支持两种使用方式:TI 云工具或者从 TI 网页下载的桌面应用。
MSP MCU 编程器和调试器
MSP-FET 是一款强大的仿真开发工具(通常称为调试探针),可帮助用户在 MSP 低功耗微控制器 (MCU)
中快速开发应用。创建 MCU 软件通常需要将生成的二进制程序下载到 MSP 器件中,从而进行验证和调
试。
MSP-GANG 生产编程器
MSP Gang 编程器是一款 MSP430 或 MSP432 器件编程器,可同时对多达八个完全相同的 MSP430 或
MSP432 闪存或 FRAM 器件进行编程。MSP Gang 编程器可使用标准的 RS-232 或 USB 连接与主机 PC
相连并提供灵活的编程选项,允许用户完全自定义流程。
TIREX Resource Explorer (TIRex)
用于查找器件和开发板的示例、库、可执行代码和文档的在线门户。您可以直接在 Code Composer Studio
IDE 内访问 TIRex,也可以在“TI 云工具”中访问 TIRex。
TI 云工具
快速在 dev.ti.com 上开始开发。首先使用 Resource Explorer 界面快速找到您需要的所有文件。然后使用行
业领先的 Code Composer Studio Cloud IDE 在云中编辑、生成和调试嵌入式 应用 。
GCC - 适用于 MSP 的编译器
MSP430 和 MSP432 GCC 开源包是一个完整的调试器和开源 C/C++ 编译器工具链,用于基于 MSP430 和
MSP432 微控制器构建和调试嵌入式 应用 。这些免费的 GCC 编译器支持所有 MSP430 和 MSP432 器件
且没有代码大小限制。此外,这些编译器可以通过命令行独立使用,也可在 Code Composer Studio v6.0 或
更高版本中使用。不管您使用的是 Windows®、 Linux® 还是 macOS®环境,马上开始吧。
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8.4 文档支持
以下文档介绍了 MSP430FR235x 和 MSP430FR215x 微控制器。
接收文档更新通知
要接收文档更新通知(包括芯片勘误表),请转至 ti.com.cn 上您的器件对应的产品文件夹(关于产品文件
夹的链接,请参见节 8.5)。请单击右上角的“通知我”按钮。点击注册后,即可收到产品信息更改每周摘要
(如有)。有关更改的详细信息,请查看任意修订文档的修订历史记录。
勘误表
《MSP430FR2355 器件勘误表》
介绍了这款器件所有芯片修订版本的功能规格的已知例外情况。
《MSP430FR2353 器件勘误表》
介绍了这款器件所有芯片修订版本的功能规格的已知例外情况。
《MSP430FR2155 器件勘误表》
介绍了这款器件所有芯片修订版本的功能规格的已知例外情况。
《MSP430FR2153 器件勘误表》
介绍了这款器件所有芯片修订版本的功能规格的已知例外情况。
用户指南
《MSP430FR4xx 和 MSP430FR2xx 系列用户指南》
详细 说明 了该器件系列提供的所有模块和外设。
《MSP430 FRAM 器件引导加载程序 (BSL)》用户指南
MSP430 MCU 上的引导加载程序 (BSL) 允许用户在原型设计、投产和维护等各阶段与 MSP430 MCU 中的
嵌入式存储器进行通信。可编程存储器(FRAM 存储器)和数据存储器 (RAM) 均可按要求予以修改。
《通过 JTAG 接口对 MSP430 进行编程》
此文档介绍了使用 JTAG 通信端口擦除、编程和验证基于 MSP430 闪存和 FRAM 的微控制器系列的存储器
模块所需的功能。此外,该文档还介绍了如何编程所有 MSP430 器件上均具备的 JTAG 访问安全保险丝。
此文档介绍了使用标准四线制 JTAG 接口和两线制 JTAG 接口(也称为 Spy-Bi-Wire (SBW))的器件访问。
《MSP430 硬件工具用户指南》
此手册介绍了 TI MSP-FET430 闪存仿真工具 (FET) 的硬件。FET 是针对 MSP430 超低功耗微控制器的程
序开发工具。文中对提供的接口类型,即并行端口接口和 USB 接口进行了说明。
应用报告
《MSP430 32kHz 晶体振荡器》
选择合适的晶体、正确的负载电路和适当的电路板布局是实现稳定的晶体振荡器的关键。该应用报告总结了
晶体振荡器的功能,介绍了用于选择合适的晶体以实现 MSP430 超低功耗运行的参数。此外,还给出了正
确电路板布局的提示和示例。此外,为了确保振荡器在大规模生产后能够稳定运行,还可能需要进行一些振
荡器测试,该文档中提供了有关这些测试的详细信息。
《MSP430 系统级 ESD 注意事项》
随着芯片技术向更低电压方向发展以及设计具有成本效益的超低功耗组件的需求的出现,系统级 ESD 要求
变得越来越苛刻。该应用报告介绍了不同的 ESD 主题,旨在帮助电路板设计人员和 OEM 理解并设计出稳
健耐用的系统级设计。
8.5 相关链接
表 8-2 列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件,以及立即订购快速访问。
118
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ZHCSI67D –MAY 2018–REVISED DECEMBER 2019
表 8-2. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
请单击此处
工具和软件
请单击此处
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
请单击此处
MSP430FR2355
MSP430FR2353
MSP430FR2155
MSP430FR2153
版权 © 2018–2019, Texas Instruments Incorporated
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8.6 商标
LaunchPad, MSP430, MSP430Ware, Code Composer Studio, E2E, EnergyTrace, ULP Advisor, 功耗, 适用
于 MSP 微控制器的 Code Composer Studio are trademarks of Texas Instruments.
macOS is a registered trademark of Apple, Inc.
IAR Embedded Workbench is a registered trademark of IAR Systems.
Linux is a registered trademark of Linus Torvalds.
Windows is a registered trademark of Microsoft Corporation.
8.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
8.8 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
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9 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MSP430FR2153TDBT
MSP430FR2153TDBTR
MSP430FR2153TPT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
LQFP
DBT
DBT
PT
38
38
48
48
40
40
32
32
38
38
48
48
40
40
32
32
38
38
48
48
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
430FR2153
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
2000 RoHS & Green
250 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
430FR2153
430FR2153
430FR2153
FR2153
MSP430FR2153TPTR
MSP430FR2153TRHAR
MSP430FR2153TRHAT
MSP430FR2153TRSMR
MSP430FR2153TRSMT
MSP430FR2155TDBT
MSP430FR2155TDBTR
MSP430FR2155TPT
LQFP
PT
1000 RoHS & Green
2500 RoHS & Green
VQFN
VQFN
VQFN
VQFN
TSSOP
TSSOP
LQFP
RHA
RHA
RSM
RSM
DBT
DBT
PT
250
RoHS & Green
FR2153
3000 RoHS & Green
FR2153
250
50
RoHS & Green
RoHS & Green
FR2153
430FR2155
430FR2155
430FR2155
430FR2155
FR2155
2000 RoHS & Green
250 RoHS & Green
MSP430FR2155TPTR
MSP430FR2155TRHAR
MSP430FR2155TRHAT
MSP430FR2155TRSMR
MSP430FR2155TRSMT
MSP430FR2353TDBT
MSP430FR2353TDBTR
MSP430FR2353TPT
LQFP
PT
1000 RoHS & Green
2500 RoHS & Green
VQFN
VQFN
VQFN
VQFN
TSSOP
TSSOP
LQFP
RHA
RHA
RSM
RSM
DBT
DBT
PT
250
RoHS & Green
FR2155
3000 RoHS & Green
FR2155
250
50
RoHS & Green
RoHS & Green
FR2155
430FR2353
430FR2353
430FR2353
430FR2353
2000 RoHS & Green
250 RoHS & Green
1000 RoHS & Green
MSP430FR2353TPTR
LQFP
PT
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jul-2022
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MSP430FR2353TRHAR
MSP430FR2353TRHAT
MSP430FR2353TRSMR
MSP430FR2353TRSMT
MSP430FR2355TDBT
MSP430FR2355TDBTR
MSP430FR2355TPT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
TSSOP
TSSOP
LQFP
RHA
RHA
RSM
RSM
DBT
DBT
PT
40
40
32
32
38
38
48
48
40
40
32
32
2500 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
FR2353
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
FR2353
FR2353
250
50
RoHS & Green
RoHS & Green
FR2353
430FR2355
430FR2355
430FR2355
430FR2355
FR2355
2000 RoHS & Green
250 RoHS & Green
MSP430FR2355TPTR
MSP430FR2355TRHAR
MSP430FR2355TRHAT
MSP430FR2355TRSMR
MSP430FR2355TRSMT
LQFP
PT
1000 RoHS & Green
2500 RoHS & Green
VQFN
VQFN
VQFN
VQFN
RHA
RHA
RSM
RSM
250
3000 RoHS & Green
250 RoHS & Green
RoHS & Green
FR2355
FR2355
FR2355
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jul-2022
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430FR2153TDBTR TSSOP
DBT
PT
38
48
40
40
32
32
38
48
48
40
40
32
38
48
48
40
2000
1000
2500
250
330.0
330.0
330.0
180.0
330.0
180.0
330.0
330.0
330.0
330.0
180.0
180.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
12.4
12.4
16.4
16.4
16.4
16.4
16.4
12.4
16.4
16.4
16.4
16.4
6.9
9.6
6.3
6.3
4.25
4.25
6.9
9.6
9.6
6.3
6.3
4.25
6.9
9.6
9.6
6.3
10.2
9.6
1.8
1.9
1.1
1.1
1.15
1.15
1.8
1.9
1.9
1.1
1.1
1.15
1.8
1.9
1.9
1.1
12.0
12.0
12.0
12.0
8.0
16.0
16.0
16.0
16.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
12.0
16.0
16.0
16.0
16.0
Q1
Q2
Q2
Q2
Q2
Q2
Q1
Q2
Q2
Q2
Q2
Q2
Q1
Q2
Q2
Q2
MSP430FR2153TPTR
MSP430FR2153TRHAR
MSP430FR2153TRHAT
LQFP
VQFN
VQFN
RHA
RHA
RSM
RSM
DBT
PT
6.3
6.3
MSP430FR2153TRSMR VQFN
MSP430FR2153TRSMT VQFN
MSP430FR2155TDBTR TSSOP
3000
250
4.25
4.25
10.2
9.6
8.0
2000
1000
1000
2500
250
12.0
12.0
12.0
12.0
12.0
8.0
MSP430FR2155TPTR
MSP430FR2155TPTR
MSP430FR2155TRHAR
MSP430FR2155TRHAT
MSP430FR2155TRSMT
LQFP
LQFP
VQFN
VQFN
VQFN
PT
9.6
RHA
RHA
RSM
DBT
PT
6.3
6.3
250
4.25
10.2
9.6
MSP430FR2353TDBTR TSSOP
2000
1000
1000
2500
12.0
12.0
12.0
12.0
MSP430FR2353TPTR
MSP430FR2353TPTR
MSP430FR2353TRHAR
LQFP
LQFP
VQFN
PT
9.6
RHA
6.3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430FR2353TRHAT
MSP430FR2353TRSMR VQFN
MSP430FR2353TRSMT VQFN
MSP430FR2355TDBTR TSSOP
VQFN
RHA
RSM
RSM
DBT
PT
40
32
32
38
48
48
40
40
32
250
3000
250
180.0
330.0
180.0
330.0
330.0
330.0
330.0
180.0
180.0
16.4
12.4
12.4
16.4
16.4
16.4
16.4
16.4
12.4
6.3
4.25
4.25
6.9
6.3
4.25
4.25
10.2
9.6
1.1
1.15
1.15
1.8
12.0
8.0
16.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
12.0
Q2
Q2
Q2
Q1
Q2
Q2
Q2
Q2
Q2
8.0
2000
1000
1000
2500
250
12.0
12.0
12.0
12.0
12.0
8.0
MSP430FR2355TPTR
MSP430FR2355TPTR
MSP430FR2355TRHAR
MSP430FR2355TRHAT
MSP430FR2355TRSMT
LQFP
LQFP
VQFN
VQFN
VQFN
9.6
1.9
PT
9.6
9.6
1.9
RHA
RHA
RSM
6.3
6.3
1.1
6.3
6.3
1.1
250
4.25
4.25
1.15
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSP430FR2153TDBTR
MSP430FR2153TPTR
MSP430FR2153TRHAR
MSP430FR2153TRHAT
MSP430FR2153TRSMR
MSP430FR2153TRSMT
MSP430FR2155TDBTR
MSP430FR2155TPTR
MSP430FR2155TPTR
MSP430FR2155TRHAR
MSP430FR2155TRHAT
MSP430FR2155TRSMT
MSP430FR2353TDBTR
MSP430FR2353TPTR
MSP430FR2353TPTR
MSP430FR2353TRHAR
MSP430FR2353TRHAT
MSP430FR2353TRSMR
TSSOP
LQFP
VQFN
VQFN
VQFN
VQFN
TSSOP
LQFP
LQFP
VQFN
VQFN
VQFN
TSSOP
LQFP
LQFP
VQFN
VQFN
VQFN
DBT
PT
38
48
40
40
32
32
38
48
48
40
40
32
38
48
48
40
40
32
2000
1000
2500
250
350.0
350.0
367.0
210.0
367.0
210.0
350.0
336.6
350.0
367.0
210.0
210.0
350.0
350.0
336.6
367.0
210.0
367.0
350.0
350.0
367.0
185.0
367.0
185.0
350.0
336.6
350.0
367.0
185.0
185.0
350.0
350.0
336.6
367.0
185.0
367.0
43.0
43.0
35.0
35.0
35.0
35.0
43.0
31.8
43.0
35.0
35.0
35.0
43.0
43.0
31.8
35.0
35.0
35.0
RHA
RHA
RSM
RSM
DBT
PT
3000
250
2000
1000
1000
2500
250
PT
RHA
RHA
RSM
DBT
PT
250
2000
1000
1000
2500
250
PT
RHA
RHA
RSM
3000
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSP430FR2353TRSMT
MSP430FR2355TDBTR
MSP430FR2355TPTR
MSP430FR2355TPTR
MSP430FR2355TRHAR
MSP430FR2355TRHAT
MSP430FR2355TRSMT
VQFN
TSSOP
LQFP
LQFP
VQFN
VQFN
VQFN
RSM
DBT
PT
32
38
48
48
40
40
32
250
2000
1000
1000
2500
250
210.0
350.0
350.0
336.6
367.0
210.0
210.0
185.0
350.0
350.0
336.6
367.0
185.0
185.0
35.0
43.0
43.0
31.8
35.0
35.0
35.0
PT
RHA
RHA
RSM
250
Pack Materials-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
MSP430FR2153TDBT
MSP430FR2155TDBT
MSP430FR2353TDBT
MSP430FR2355TDBT
DBT
DBT
DBT
DBT
TSSOP
TSSOP
TSSOP
TSSOP
38
38
38
38
50
50
50
50
530
530
530
530
10.2
10.2
10.2
10.2
3600
3600
3600
3600
3.5
3.5
3.5
3.5
Pack Materials-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
MSP430FR2153TPT
MSP430FR2153TPT
MSP430FR2155TPT
MSP430FR2155TPT
MSP430FR2353TPT
MSP430FR2353TPT
MSP430FR2355TPT
MSP430FR2355TPT
PT
PT
PT
PT
PT
PT
PT
PT
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
48
48
48
48
48
48
48
48
250
250
250
250
250
250
250
250
10 x 25
10 x 25
10 x 25
10 x 25
10 x 25
10 x 25
10 x 25
10 x 25
150
150
150
150
150
150
150
150
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
11.1 11.25
11.1 11.25
11.1 11.25
11.1 11.25
11.1 11.25
11.1 11.25
11.1 11.25
11.1 11.25
Pack Materials-Page 6
PACKAGE OUTLINE
PT0048A
LQFP - 1.6 mm max height
S
C
A
L
E
2
.
0
0
0
LOW PROFILE QUAD FLATPACK
9.2
8.8
7.2
6.8
B
A
9.2
8.8
7.2
6.8
0.27
48X
0.17
0.08
C A B
44X 0.5
4X 5.5
SEE DETAIL A
1.6 MAX
C
SEATING PLANE
0.1 C
1.45
1.35
0.25
GAGE PLANE
0.75
0.45
0.5 MIN
0 -7
A15.000
DETAIL A
4215159/A 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MS-026.
4. This may also be a thermally enhanced plastic package with leads conected to the die pads.
www.ti.com
EXAMPLE BOARD LAYOUT
PT0048A
LQFP - 1.6 mm max height
LOW PROFILE QUAD FLATPACK
PKG
SYMM
48
37
SEE SOLDER MASK
DETAILS
48X (1.6)
1
36
48X (0.3)
44X (0.5)
PKG SYMM
(8.2)
(R0.05) TYP
12
25
13
24
(8.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE 10.000
0.05 MAX
ALLAROUND
0.05 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL EDGE
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4215159/A 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PT0048A
LQFP - 1.6 mm max height
LOW PROFILE QUAD FLATPACK
PKG
SYMM
48
37
48X (1.6)
1
36
48X (0.3)
44X (0.5)
PKG SYMM
(8.2)
(R0.05) TYP
12
25
13
24
(8.2)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 10X
4215159/A 12/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
RSM 32
4 x 4, 0.4 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224982/A
www.ti.com
PACKAGE OUTLINE
RSM0032B
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
B
4.1
3.9
A
0.45
0.25
0.25
0.15
PIN 1 INDEX AREA
DETAIL
OPTIONAL TERMINAL
TYPICAL
4.1
3.9
(0.1)
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2.8 0.05
2X 2.8
(0.2) TYP
4X (0.45)
28X 0.4
9
16
SEE SIDE WALL
DETAIL
8
17
EXPOSED
THERMAL PAD
2X
SYMM
33
2.8
24
0.25
32X
1
SEE TERMINAL
DETAIL
0.15
0.1
C A B
25
32
PIN 1 ID
(OPTIONAL)
0.05
SYMM
0.45
0.25
32X
4219108/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RSM0032B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.8)
SYMM
32
25
32X (0.55)
1
32X (0.2)
24
(
0.2) TYP
VIA
(1.15)
SYMM
33
(3.85)
28X (0.4)
17
8
(R0.05)
TYP
9
16
(1.15)
(3.85)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219108/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RSM0032B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.715)
4X ( 1.23)
(R0.05) TYP
25
32
32X (0.55)
1
24
32X (0.2)
(0.715)
(3.85)
33
SYMM
28X (0.4)
17
8
METAL
TYP
16
9
SYMM
(3.85)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 33:
77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219108/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DBT0038A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SEATING
PLANE
6.55
6.25
TYP
C
A
0.1 C
PIN 1 INDEX AREA
38 X 0.5
38
1
2X
9
9.75
9.65
NOTE 3
19
B
20
0.23
38 X
0.17
4.45
1.2 MAX
0.1
C A B
4.35
NOTE 4
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
4220221/A 05/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DBT0038A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
38 X (1.5)
SYMM
(R0.05) TYP
38
1
38 X (0.3)
38 X (0.5)
SYMM
19
20
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220221/A 05/2020
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBT0038A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
38 X (1.5)
SYMM
(R0.05) TYP
38
1
38 X (0.3)
38 X (0.5)
SYMM
19
20
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220221/A 05/2020
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
RHA 40
6 x 6, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225870/A
www.ti.com
PACKAGE OUTLINE
RHA0040E
VQFN - 1 mm max height
S
C
A
L
E
2
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.15
5.85
A
B
PIN 1 INDEX AREA
6.15
5.85
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2X 4.5
3.52 0.1
SYMM
EXPOSED
THERMAL PAD
(0.1) TYP
11
20
10
21
SYMM
41
2X 4.5
2.62 0.1
30
36X 0.5
1
0.30
0.18
40X
31
40
PIN 1 ID
0.1
C A B
0.5
0.3
0.05
40X
4219054/A 04/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHA0040E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.52)
SYMM
SEE SOLDER MASK
DETAIL
31
40
40X (0.6)
40X (0.24)
1
30
36X (0.5)
(2.62)
41
SYMM
(5.8)
(1.06)
(
0.2) TYP
VIA
(R0.05) TYP
21
10
11
20
(0.6)
TYP
(0.91)
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219054/A 04/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHA0040E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.2)
31
40
40X (0.6)
30
40X (0.24)
1
36X (0.5)
(0.675)
(5.8)
41
SYMM
6X (1.15)
(R0.05) TYP
21
10
20
11
SYMM
6X (1)
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 15X
EXPOSED PAD 41
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219054/A 04/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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