MSP430G2253IN20 [TI]
MIXED SIGNAL MICROCONTROLLER; 混合信号微控制器型号: | MSP430G2253IN20 |
厂家: | TEXAS INSTRUMENTS |
描述: | MIXED SIGNAL MICROCONTROLLER |
文件: | 总68页 (文件大小:884K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MSP430G2x53
MSP430G2x13
www.ti.com
SLAS735A –APRIL 2011–REVISED MAY 2011
MIXED SIGNAL MICROCONTROLLER
1
FEATURES
•
Low Supply-Voltage Range: 1.8 V to 3.6 V
Ultra-Low Power Consumption
•
Universal Serial Communication Interface
(USCI)
•
–
Enhanced UART Supporting Auto Baudrate
Detection (LIN)
IrDA Encoder and Decoder
Synchronous SPI
I2C™
–
–
–
Active Mode: 230 µA at 1 MHz, 2.2 V
Standby Mode: 0.5 µA
Off Mode (RAM Retention): 0.1 µA
–
–
–
•
•
Five Power-Saving Modes
Ultra-Fast Wake-Up From Standby Mode in
Less Than 1 µs
16-Bit RISC Architecture, 62.5-ns Instruction
Cycle Time
•
•
On-Chip Comparator for Analog Signal
Compare Function or Slope Analog-to-Digital
(A/D) Conversion
10-Bit 200-ksps Analog-to-Digital (A/D)
Converter With Internal Reference,
Sample-and-Hold, and Autoscan (See Table 1)
Brownout Detector
Serial Onboard Programming,
No External Programming Voltage Needed,
Programmable Code Protection by Security
Fuse
•
•
Basic Clock Module Configurations
–
Internal Frequencies up to 16 MHz With
Four Calibrated Frequency
Internal Very-Low-Power Low-Frequency
(LF) Oscillator
32-kHz Crystal
External Digital Clock Source
•
•
–
–
–
•
•
Two 16-Bit Timer_A With Three
Capture/Compare Registers
Up to 24 Touch-Sense-Enabled I/O Pins
•
On-Chip Emulation Logic With Spy-Bi-Wire
Interface
Family Members are Summarized in Table 1
Package Options
•
•
–
–
–
TSSOP: 20 Pin, 28 Pin
PDIP: 20 Pin
QFN: 32 Pin
•
For Complete Module Descriptions, See the
MSP430x2xx Family User’s Guide (SLAU144)
DESCRIPTION
The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.
The MSP430G2x13 and MSP430G2x53 series are ultra-low-power mixed signal microcontrollers with built-in
16-bit timers, up to 24 I/O touch-sense-enabled pins, a versatile analog comparator, and built-in communication
capability using the universal serial communication interface. In addition the MSP430G2x53 family members
have a 10-bit analog-to-digital (A/D) converter. For configuration details see Table 1.
Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values,
and then process the data for display or for transmission to a host system.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
MSP430G2x53
MSP430G2x13
SLAS735A –APRIL 2011–REVISED MAY 2011
www.ti.com
Table 1. Available Options(1)(2)
Flash
(KB)
RAM
(B)
COMP_A+ ADC10
Channel Channel
USCI
A0/B0
Package
Type
Device
BSL
EEM
Timer_A
Clock
I/O
MSP430G2553IRHB32
MSP430G2553IPW28
MSP430G2553IPW20
MSP430G2553IN20
MSP430G2453IRHB32
MSP430G2453IPW28
MSP430G2453IPW20
MSP430G2453IN20
MSP430G2353IRHB32
MSP430G2353IPW28
MSP430G2353IPW20
MSP430G2353IN20
MSP430G2253IRHB32
MSP430G2253IPW28
MSP430G2253IPW20
MSP430G2253IN20
MSP430G2153IRHB32
MSP430G2153IPW28
MSP430G2153IPW20
MSP430G2153IN20
MSP430G2513IRHB32
MSP430G2513IPW28
MSP430G2513IPW20
MSP430G2513IN20
MSP430G2413IRHB32
MSP430G2413IPW28
MSP430G2413IPW20
MSP430G2413IN20
MSP430G2313IRHB32
MSP430G2313IPW28
MSP430G2313IPW20
MSP430G2313IN20
MSP430G2213IRHB32
MSP430G2213IPW28
MSP430G2213IPW20
MSP430G2213IN20
MSP430G2113IRHB32
MSP430G2113IPW28
MSP430G2113IPW20
MSP430G2113IN20
24
24
16
16
24
24
16
16
24
24
16
16
24
24
16
16
24
24
16
16
24
24
16
16
24
24
16
16
24
24
16
16
24
24
16
16
24
24
16
16
32-QFN
28-TSSOP
20-TSSOP
20-PDIP
LF,
DCO,
VLO
1
1
16
512
512
256
256
256
512
512
256
256
256
2x TA3
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
-
1
1
1
1
1
1
1
1
1
1
32-QFN
LF,
DCO,
VLO
28-TSSOP
20-TSSOP
20-PDIP
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
4
2x TA3
2x TA3
2x TA3
2x TA3
2x TA3
2x TA3
2x TA3
2x TA3
2x TA3
32-QFN
LF,
DCO,
VLO
28-TSSOP
20-TSSOP
20-PDIP
32-QFN
LF,
DCO,
VLO
28-TSSOP
20-TSSOP
20-PDIP
2
32-QFN
LF,
DCO,
VLO
28-TSSOP
20-TSSOP
20-PDIP
1
32-QFN
LF,
DCO,
VLO
28-TSSOP
20-TSSOP
20-PDIP
16
8
32-QFN
LF,
DCO,
VLO
28-TSSOP
20-TSSOP
20-PDIP
-
32-QFN
LF,
DCO,
VLO
28-TSSOP
20-TSSOP
20-PDIP
4
-
32-QFN
LF,
DCO,
VLO
28-TSSOP
20-TSSOP
20-PDIP
2
-
32-QFN
LF,
DCO,
VLO
28-TSSOP
20-TSSOP
20-PDIP
1
-
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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MSP430G2x53
MSP430G2x13
www.ti.com
SLAS735A –APRIL 2011–REVISED MAY 2011
Device Pinout, MSP430G2x13 and MSP430G2x53, 20-Pin Devices, TSSOP and PDIP
DVCC
P1.0/TA0CLK/ACLK/A0/CA0
1
2
20
19
18
17
16
15
14
13
12
11
DVSS
XIN/P2.6/TA0.1
P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1/CA1
P1.2/TA0.1/UCA0TXD/PUCA0SIMO/A2/CA2
P1.3/ADC10CLK/CAOUT/VREF-/VEREF-/A3/CA3
P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/CA4/TCK
P1.5/TA0.0/UCB0CLK/UCA0STE/A5/CA5/TMS
P2.0/TA1.0
3
XOUT/P2.7
4
TEST/SBWTCK
N20
PW20
(TOP VIEW)
5
RST/NMI/SBWTDIO
6
P1.7/CAOUT/UCB0SIMO/UCB0SDA/A7/CA7/TDO/TDI
P1.6/TA0.1/UCB0SOMI/UCB0SCL/A6/CA6/TDI/TCLK
7
8
P2.5/TA1.2
P2.4/TA1.2
P2.3/TA1.0
P2.1/TA1.1
9
P2.2/TA1.1
10
NOTE: ADC10 is available on MSP430G2x53 devices only.
NOTE: The pulldown resistors of port P3 should be enabled by setting P3REN.x = 1.
Device Pinout, MSP430G2x13 and MSP430G2x53, 28-Pin Devices, TSSOP
DVCC
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DVSS
P1.0/TA0CLK/ACLK/A0/CA0
XIN/P2.6/TA0.1
P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1/CA1
3
XOUT/P2.7
P1.2/TA0.1/UCA0TXD/PUCA0SIMO/A2/CA2
4
TEST/SBWTCK
P1.3/ADC10CLK/CAOUT/VREF-/VEREF-/A3/CA3
5
RST/NMI/SBWTDIO
P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/CA4/TCK
6
P1.7/CAOUT/UCB0SIMO/UCB0SDA/A7/CA7/TDO/TDI
PW28
(TOP VIEW)
P1.6/TA0.1/UCB0SOMI/UCB0SCL/A6/CA6/TDI/TCLK
P1.5/TA0.0/UCB0CLK/UCA0STE/A5/CA5/TMS
7
8
P3.7/TA1CLK/CAOUT
P3.6/TA0.2
P3.1/TA1.0
P3.0/TA0.2
P2.0/TA1.0
P2.1/TA1.1
P2.2/TA1.1
P3.2/TA1.1
P3.3/TA1.2
9
10
11
12
13
14
P3.5/TA0.1
P2.5/TA1.2
P2.4/TA1.2
P2.3/TA1.0
P3.4/TA0.0
NOTE: ADC10 is available on MSP430G2x53 devices only.
Device Pinout, MSP430G2x13 and MSP430G2x53, 32-Pin Devices, QFN
32 31 30 29 28 27 26 25
P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1/CA1
P1.2/TA0.1/UCA0TXD/UCA0SIMO/A2/CA2
P1.3/ADC10CLK/CAOUT/VREF-/VEREF-/A3/CA3
P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/CA4/TCK
P1.5/TA0.0/UCB0CLK/UCA0STE/A5/CA5/TMS
P3.1/TA1.0
1
2
3
4
5
6
7
8
24 TEST/SBWTCK
23 RST/NMI/SBWTDIO
P1.7/CAOUT/UCB0SIMO/UCB0SDA/A7/CA7/TDO/TDI
21 P1.6/TA0.1/UCB0SOMI/UCB0SCL/A6/CA6/TDI/TCLK
P3.7/TA1CLK/CAOUT
19 P3.6/TA0.2
22
RHB32
(TOP VIEW)
20
P3.0/TA0.2
18
17
P3.5/TA0.1
P2.5/TA1.2
NC
9
10 11 12 13 14 15 16
NOTE: ADC10 is available on MSP430G2x53 devices only.
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MSP430G2x53
MSP430G2x13
SLAS735A –APRIL 2011–REVISED MAY 2011
www.ti.com
Functional Block Diagram, MSP430G2x53
XIN XOUT
DVCC
DVSS
P1.x
8
P2.x
P3.x
8
8
ACLK
Port P3
8 I/O
Port P1
Port P2
Clock
System
Flash
ADC
SMCLK
RAM
8 I/O
Interrupt
capability
pullup/down pullup/down
resistors
resistors
8 I/O
Interrupt
capability
16KB
8KB
4KB
2KB
10-Bit
8 Ch.
Autoscan
1 ch DMA
512B
256B
pullup/
pulldown
resistors
MCLK
16MHz
CPU
MAB
MDB
incl. 16
Registers
USCI A0
Emulation
2BP
UART/
LIN, IrDA,
SPI
Timer0_A3 Timer1_A3
Watchdog
WDT+
Comp_A+
Brownout
Protection
3 CC
Registers
3 CC
Registers
JTAG
Interface
8 Channels
15-Bit
USCI B0
SPI, I2C
Spy-Bi-
Wire
RST/NMI
NOTE: Port P3 is available on 28-pin and 32-pin devices only.
Functional Block Diagram, MSP430G2x13
XIN XOUT
DVCC
DVSS
P1.x
8
P2.x
P3.x
8
8
ACLK
Port P3
8 I/O
Port P1
Port P2
Clock
System
Flash
SMCLK
RAM
8 I/O
Interrupt
capability
pullup/down pullup/down
resistors
resistors
8 I/O
Interrupt
capability
16KB
8KB
4KB
2KB
512B
256B
pullup/
pulldown
resistors
MCLK
16MHz
CPU
MAB
MDB
incl. 16
Registers
USCI A0
Emulation
2BP
UART/
LIN, IrDA,
SPI
Timer0_A3 Timer1_A3
Watchdog
WDT+
Comp_A+
Brownout
Protection
3 CC
Registers
3 CC
Registers
JTAG
Interface
8 Channels
15-Bit
USCI B0
SPI, I2C
Spy-Bi-
Wire
RST/NMI
NOTE: Port P3 is available on 28-pin and 32-pin devices only.
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MSP430G2x53
MSP430G2x13
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SLAS735A –APRIL 2011–REVISED MAY 2011
Table 2. Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
NAME
PW20,
N20
PW28
RHB32
P1.0/
General-purpose digital I/O pin
TA0CLK/
ACLK/
Timer0_A, clock signal TACLK input
ACLK signal output
ADC10 analog input A0(1)
Comparator_A+, CA0 input
General-purpose digital I/O pin
2
2
3
31
I/O
I/O
A0
CA0
P1.1/
TA0.0/
Timer0_A, capture: CCI0A input, compare: Out0 output
USCI_A0 receive data input in UART mode,
USCI_A0 slave data out/master in SPI mode
ADC10 analog input A1(1)
UCA0RXD/
UCA0SOMI/
A1/
3
1
2
3
CA1
Comparator_A+, CA1 input
P1.2/
General-purpose digital I/O pin
TA0.1/
Timer0_A, capture: CCI1A input, compare: Out1 output
USCI_A0 transmit data output in UART mode,
USCI_A0 slave data in/master out in SPI mode,
ADC10 analog input A2(1)
UCA0TXD/
UCA0SIMO/
A2/
4
5
4
5
I/O
I/O
CA2
Comparator_A+, CA2 input
P1.3/
General-purpose digital I/O pin
ADC10CLK/
A3/
ADC10, conversion clock output(1)
ADC10 analog input A3(1)
(1)
VREF-/VEREF-/
CA3/
ADC10 negative reference voltage
Comparator_A+, CA3 input
CAOUT
P1.4/
Comparator_A+, output
General-purpose digital I/O pin
SMCLK signal output
SMCLK/
UCB0STE/
UCA0CLK/
A4/
USCI_B0 slave transmit enable
USCI_A0 clock input/output
ADC10 analog input A4(1)
6
6
4
I/O
VREF+/VEREF+/
CA4/
ADC10 positive reference voltage(1)
Comparator_A+, CA4 input
TCK
JTAG test clock, input terminal for device programming and test
General-purpose digital I/O pin
Timer0_A, compare: Out0 output
USCI_B0 clock input/output,
P1.5/
TA0.0/
UCB0CLK/
UCA0STE/
A5/
7
7
5
I/O
USCI_A0 slave transmit enable
ADC10 analog input A5(1)
CA5/
Comparator_A+, CA5 input
TMS
JTAG test mode select, input terminal for device programming and test
(1) MSP430G2x53 devices only
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MSP430G2x53
MSP430G2x13
SLAS735A –APRIL 2011–REVISED MAY 2011
www.ti.com
Table 2. Terminal Functions (continued)
TERMINAL
NO.
I/O
DESCRIPTION
NAME
PW20,
N20
PW28
RHB32
P1.6/
General-purpose digital I/O pin
Timer0_A, compare: Out1 output
ADC10 analog input A6(1)
TA0.1/
A6/
CA6/
14
22
21
I/O
Comparator_A+, CA6 input
UCB0SOMI/
UCB0SCL/
TDI/TCLK
P1.7/
USCI_B0 slave out/master in SPI mode,
USCI_B0 SCL I2C clock in I2C mode
JTAG test data input or test clock input during programming and test
General-purpose digital I/O pin
A7/
ADC10 analog input A7(1)
CA7/
Comparator_A+, CA7 input
CAOUT/
UCB0SIMO/
UCB0SDA/
TDO/TDI
Comparator_A+, output
15
23
22
I/O
USCI_B0 slave in/master out in SPI mode
USCI_B0 SDA I2C data in I2C mode
JTAG test data output terminal or test data input during programming and
test(2)
P2.0/
TA1.0
P2.1/
TA1.1
P2.2/
TA1.1
P2.3/
TA1.0
P2.4/
TA1.2
P2.5/
TA1.2
XIN/
General-purpose digital I/O pin
8
10
11
12
16
17
18
9
I/O
I/O
I/O
I/O
I/O
I/O
Timer1_A, capture: CCI0A input, compare: Out0 output
General-purpose digital I/O pin
9
10
11
15
16
17
Timer1_A, capture: CCI1A input, compare: Out1 output
General-purpose digital I/O pin
10
11
12
13
Timer1_A, capture: CCI1B input, compare: Out1 output
General-purpose digital I/O pin
Timer1_A, capture: CCI0B input, compare: Out0 output
General-purpose digital I/O pin
Timer1_A, capture: CCI2A input, compare: Out2 output
General-purpose digital I/O pin
Timer1_A, capture: CCI2B input, compare: Out2 output
Input terminal of crystal oscillator
P2.6/
TA0.1
XOUT/
P2.7
19
27
26
I/O
General-purpose digital I/O pin
Timer0_A, compare: Out1 output
Output terminal of crystal oscillator(3)
18
-
26
9
25
7
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O pin
P3.0/
TA0.2
P3.1/
TA1.0
P3.2/
TA1.1
P3.3/
TA1.2
P3.4/
TA0.0
General-purpose digital I/O pin
Timer0_A, capture: CCI2A input, compare: Out2 output
General-purpose digital I/O pin
-
8
6
Timer1_A, compare: Out0 output
General-purpose digital I/O pin
-
13
14
15
12
13
14
Timer1_A, compare: Out1 output
General-purpose digital I/O
-
Timer1_A, compare: Out2 output
General-purpose digital I/O
-
Timer0_A, compare: Out0 output
(2) TDO or TDI is selected via JTAG instruction.
(3) If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection
to this pad after reset.
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MSP430G2x53
MSP430G2x13
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SLAS735A –APRIL 2011–REVISED MAY 2011
Table 2. Terminal Functions (continued)
TERMINAL
NO.
I/O
DESCRIPTION
NAME
PW20,
N20
PW28
RHB32
P3.5/
General-purpose digital I/O
Timer0_A, compare: Out1 output
General-purpose digital I/O
Timer0_A, compare: Out2 output
General-purpose digital I/O
Timer0_A, clock signal TACLK input
Comparator_A+, output
-
-
19
20
18
I/O
I/O
TA0.1
P3.6/
19
20
TA0.2
P3.7/
TA1CLK/
CAOUT
RST/
-
21
I/O
Reset
NMI/
16
17
24
25
23
24
I
I
Nonmaskable interrupt input
SBWTDIO
TEST/
Spy-Bi-Wire test data input/output during programming and test
Selects test mode for JTAG pins on Port 1. The device protection fuse is
connected to TEST.
SBWTCK
DVCC
DVSS
Spy-Bi-Wire test clock input during programming and test
Supply voltage
1
1
29, 30
27, 28
8, 32
Pad
NA
NA
NA
NA
20
NA
NA
28
NA
NA
Ground reference
NC
Not connected
QFN Pad
QFN package pad. Connection to VSS is recommended.
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MSP430G2x53
MSP430G2x13
SLAS735A –APRIL 2011–REVISED MAY 2011
www.ti.com
SHORT-FORM DESCRIPTION
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
Program Counter
PC/R0
SP/R1
Stack Pointer
Status Register
SR/CG1/R2
CG2/R3
R4
Constant Generator
The CPU is integrated with 16 registers that provide
reduced
instruction
execution
time.
The
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
register-to-register operation execution time is one
cycle of the CPU clock.
R5
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
R6
R7
R8
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
R9
R10
R11
R12
R13
R14
R15
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data.
Instruction Set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 3 shows examples of the three types of
instruction formats; Table 4 shows the address
modes.
Table 3. Instruction Word Formats
INSTRUCTION FORMAT
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
EXAMPLE
ADD R4,R5
CALL R8
JNE
OPERATION
R4 + R5 ---> R5
PC -->(TOS), R8--> PC
Jump-on-equal bit = 0
Table 4. Address Mode Descriptions(1)
ADDRESS MODE
Register
S
✓
✓
✓
✓
✓
D
✓
✓
✓
✓
SYNTAX
MOV Rs,Rd
EXAMPLE
MOV R10,R11
MOV 2(R5),6(R6)
OPERATION
R10 -- --> R11
Indexed
MOV X(Rn),Y(Rm)
MOV EDE,TONI
MOV &MEM,&TCDAT
MOV @Rn,Y(Rm)
M(2+R5) -- --> M(6+R6)
M(EDE) -- --> M(TONI)
M(MEM) -- --> M(TCDAT)
M(R10) -- --> M(Tab+R6)
Symbolic (PC relative)
Absolute
Indirect
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
M(R10) -- --> R11
R10 + 2-- --> R10
Indirect autoincrement
Immediate
✓
✓
MOV @Rn+,Rm
MOV #X,TONI
#45 -- --> M(TONI)
(1) S = source, D = destination
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Operating Modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
•
Active mode (AM)
All clocks are active
Low-power mode 0 (LPM0)
–
•
–
–
CPU is disabled
ACLK and SMCLK remain active, MCLK is disabled
•
•
Low-power mode 1 (LPM1)
–
–
–
CPU is disabled
ACLK and SMCLK remain active, MCLK is disabled
DCO's dc generator is disabled if DCO not used in active mode
Low-power mode 2 (LPM2)
–
–
–
–
CPU is disabled
MCLK and SMCLK are disabled
DCO's dc generator remains enabled
ACLK remains active
•
•
Low-power mode 3 (LPM3)
–
–
–
–
CPU is disabled
MCLK and SMCLK are disabled
DCO's dc generator is disabled
ACLK remains active
Low-power mode 4 (LPM4)
–
–
–
–
–
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO's dc generator is disabled
Crystal oscillator is stopped
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Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed), the
CPU goes into LPM4 immediately after power-up.
Table 5. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
Power-Up
External Reset
Watchdog Timer+
Flash key violation
PC out-of-range(1)
PORIFG
RSTIFG
WDTIFG
KEYV(2)
Reset
0FFFEh
31, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
(non)-maskable
(non)-maskable
(non)-maskable
0FFFCh
30
ACCVIFG(2)(3)
Timer1_A3
Timer1_A3
TACCR0 CCIFG(4)
TACCR2 TACCR1 CCIFG, TAIFG(2)(4)
CAIFG(4)
maskable
maskable
maskable
maskable
maskable
0FFFAh
0FFF8h
0FFF6h
0FFF4h
0FFF2h
29
28
27
26
25
Comparator_A+
Watchdog Timer+
Timer0_A3
WDTIFG
TACCR0 CCIFG(4)
Timer0_A3
TACCR2 TACCR1 CCIFG, TAIFG
maskable
maskable
maskable
maskable
0FFF0h
0FFEEh
0FFECh
0FFEAh
24
23
22
21
(5)(4)
USCI_A0/USCI_B0 receive
USCI_B0 I2C status
UCA0RXIFG, UCB0RXIFG(2)(5)
UCA0TXIFG, UCB0TXIFG(2)(6)
ADC10IFG(4)
USCI_A0/USCI_B0 transmit
USCI_B0 I2C receive/transmit
ADC10
(MSP430G2x53 only)
0FFE8h
0FFE6h
0FFE4h
0FFE2h
0FFE0h
0FFDEh
20
19
18
17
16
15
I/O Port P2 (up to eight flags)
I/O Port P1 (up to eight flags)
P2IFG.0 to P2IFG.7(2)(4)
P1IFG.0 to P1IFG.7(2)(4)
maskable
maskable
(7)
See
(8)
See
0FFDEh to
0FFC0h
14 to 0, lowest
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
(2) Multiple source flags
(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
(4) Interrupt flags are located in the module.
(5) In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
(6) In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
(7) This location is used as bootstrap loader security key (BSLSKEY). A 0xAA55 at this location disables the BSL completely. A zero (0h)
disables the erasure of the flash if an invalid password is supplied.
(8) The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
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Special Function Registers (SFRs)
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw:
Bit can be read and written.
rw-0,1:
rw-(0,1):
Bit can be read and written. It is reset or set by PUC.
Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Table 6. Interrupt Enable Register 1 and 2
Address
00h
7
6
5
4
3
2
1
0
ACCVIE
rw-0
NMIIE
rw-0
OFIE
rw-0
WDTIE
rw-0
WDTIE
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in
interval timer mode.
OFIE
Oscillator fault interrupt enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
NMIIE
ACCVIE
Address
7
6
5
4
3
2
1
0
01h
UCB0TXIE
rw-0
UCB0RXIE
rw-0
UCA0TXIE
rw-0
UCA0RXIE
rw-0
UCA0RXIE
UCA0TXIE
UCB0RXIE
UCB0TXIE
USCI_A0 receive interrupt enable
USCI_A0 transmit interrupt enable
USCI_B0 receive interrupt enable
USCI_B0 transmit interrupt enable
Table 7. Interrupt Flag Register 1 and 2
Address
02h
7
6
5
4
3
2
1
0
NMIIFG
rw-0
RSTIFG
rw-(0)
PORIFG
rw-(1)
OFIFG
rw-1
WDTIFG
rw-(0)
WDTIFG
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.
OFIFG
Flag set on oscillator fault.
PORIFG
RSTIFG
NMIIFG
Power-On Reset interrupt flag. Set on VCC power-up.
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up.
Set via RST/NMI pin
Address
03h
7
6
5
4
3
2
1
0
UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG
rw-1 rw-0 rw-1 rw-0
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
USCI_A0 receive interrupt flag
USCI_A0 transmit interrupt flag
USCI_B0 receive interrupt flag
USCI_B0 transmit interrupt flag
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Memory Organization
Table 8. Memory Organization
MSP430G2153
MSP430G2113
MSP430G2253
MSP430G2213
MSP430G2353
MSP430G2313
MSP430G2453
MSP430G2413
MSP430G2553
MSP430G2513
Memory
Size
Flash
Flash
Size
1kB
2kB
4kB
8kB
16kB
Main: interrupt vector
Main: code memory
Information memory
0xFFFF to 0xFFC0
0xFFFF to 0xFC00
256 Byte
0xFFFF to 0xFFC0
0xFFFF to 0xF800
256 Byte
0xFFFF to 0xFFC0
0xFFFF to 0xF000
256 Byte
0xFFFF to 0xFFC0
0xFFFF to 0xE000
256 Byte
0xFFFF to 0xFFC0
0xFFFF to 0xC000
256 Byte
Flash
Size
010FFh to 01000h
256 Byte
010FFh to 01000h
256 Byte
010FFh to 01000h
256 Byte
010FFh to 01000h
512 Byte
010FFh to 01000h
512 Byte
RAM
0x02FF to 0x0200
01FFh to 0100h
0FFh to 010h
0Fh to 00h
0x02FF to 0x0200
01FFh to 0100h
0FFh to 010h
0Fh to 00h
0x02FF to 0x0200
01FFh to 0100h
0FFh to 010h
0Fh to 00h
0x03FF to 0x0200
01FFh to 0100h
0FFh to 010h
0Fh to 00h
0x03FF to 0x0200
01FFh to 0100h
0FFh to 010h
0Fh to 00h
Peripherals
16-bit
8-bit
8-bit SFR
Bootstrap Loader (BSL)
The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to
the MSP430 memory via the BSL is protected by user-defined password. For complete description of the
features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader User's
Guide (SLAU319).
Table 9. BSL Function Pins
20-PIN PW PACKAGE
20-PIN N PACKAGE
BSL FUNCTION
28-PIN PACKAGE PW
32-PIN PACKAGE RHB
Data transmit
Data receive
3 - P1.1
3 - P1.1
7 - P1.5
1 - P1.1
5 - P1.5
7 - P1.5
Flash Memory
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
•
Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
•
•
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also
called information memory.
•
Segment A contains calibration data. After reset segment A is protected against programming and erasing. It
can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is
required.
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO).
The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic
clock module provides the following clock signals:
•
•
•
Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.
Main DCO Characteristics
•
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
•
•
DCO control bits DCOx have a step size as defined by parameter SDCO.
Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
32 × f
× f
DCO(RSEL,DCO+1)
DCO(RSEL,DCO)
f
=
average
MOD × f
+ (32 – MOD) × f
DCO(RSEL,DCO+1)
DCO(RSEL,DCO)
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Calibration Data Stored in Information Memory Segment A
Calibration data is stored for both the DCO and for ADC10 organized in a tag-length-value structure.
Table 10. Tags Used by the ADC Calibration Tags
NAME
ADDRESS
0x10F6
0x10DA
-
VALUE
0x01
DESCRIPTION
TAG_DCO_30
TAG_ADC10_1
TAG_EMPTY
DCO frequency calibration at VCC = 3 V and TA = 30°C at calibration
ADC10_1 calibration tag
0x08
0xFE
Identifier for empty memory areas
Table 11. Labels Used by the ADC Calibration Tags
ADDRESS
LABEL
SIZE
CONDITION AT CALIBRATION / DESCRIPTION
OFFSET
0x0010
0x000E
0x000C
0x000A
0x0008
0x0006
0x0004
0x0002
0x0009
0x0008
0x0007
0x0006
0x0005
0x0004
0x0003
0x0002
CAL_ADC_25T85
CAL_ADC_25T30
word
word
word
word
word
word
word
word
byte
byte
byte
byte
byte
byte
byte
byte
INCHx = 0x1010, REF2_5 = 1, TA = 85°C
INCHx = 0x1010, REF2_5 = 1, TA = 30°C
CAL_ADC_25VREF_FACTOR
CAL_ADC_15T85
REF2_5 = 1, TA = 30°C, IVREF+ = 1 mA
INCHx = 0x1010, REF2_5 = 0, TA = 85°C
CAL_ADC_15T30
INCHx = 0x1010, REF2_5 = 0, TA = 30°C
CAL_ADC_15VREF_FACTOR
CAL_ADC_OFFSET
CAL_ADC_GAIN_FACTOR
CAL_BC1_1MHZ
REF2_5 = 0, TA = 30°C, IVREF+ = 0.5 mA
External VREF = 1.5 V, fADC10CLK = 5 MHz
External VREF = 1.5 V, fADC10CLK = 5 MHz
-
-
-
-
-
-
-
-
CAL_DCO_1MHZ
CAL_BC1_8MHZ
CAL_DCO_8MHZ
CAL_BC1_12MHZ
CAL_DCO_12MHZ
CAL_BC1_16MHZ
CAL_DCO_16MHZ
Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
Digital I/O
Up to three 8-bit I/O ports are implemented:
•
•
•
•
•
•
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt condition (port P1 and port P2 only) is possible.
Edge-selectable interrupt input capability for all bits of port P1 and port P2 (if available).
Read/write access to port-control registers is supported by all instructions.
Each I/O has an individually programmable pullup/pulldown resistor.
Each I/O has an individually programmable pin oscillator enable bit to enable low-cost touch sensing.
WDT+ Watchdog Timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be disabled or configured as an interval timer and can
generate interrupts at selected time intervals.
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Timer_A3 (TA0, TA1)
Timer0/1_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 12. Timer0_A3 Signal Connections
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
NAME
MODULE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
MODULE
BLOCK
PW20, N20
PW28
RHB32
PW20, N20
PW28
RHB32
P1.0-2
P1.0-2
P1.0-31
TACLK
ACLK
SMCLK
TACLK
TA0.0
ACLK
VSS
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
CCR0
CCR1
CCR2
NA
PinOsc
P1.1-3
PinOsc
P1.1-3
PinOsc
P1.1-1
P1.1-3
P1.5-7
P1.1-3
P1.5-7
P3.4-15
P1.1-1
P1.5-5
P3.4-14
TA0
TA1
TA2
VCC
VCC
P1.2-4
PinOsc
P1.2-4
P1.2-2
TA0.1
CAOUT
VSS
CCI1A
CCI1B
GND
P1.2-4
P1.6-14
P2.6-19
P1.2-4
P1.6-22
P2.6-27
P3.5-19
P3.0-9
P1.2-2
P1.6-21
P2.6-26
P3.5-18
P3.0-7
VCC
VCC
P3.0-9
PinOsc
P3.0-7
PinOsc
TA0.2
TA0.2
VSS
CCI2A
CCI2B
GND
P3.6-20
P3.6-19
VCC
VCC
Table 13. Timer1_A3 Signal Connections
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
NAME
MODULE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
MODULE
BLOCK
PW20, N20
PW28
RHB32
PW20, N20
PW28
RHB32
-
P3.7-21
P3.7-20
TACLK
ACLK
SMCLK
TACLK
TA1.0
TA1.0
VSS
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
CCR0
CCR1
CCR2
NA
-
P3.7-21
P2.0-10
P2.3-16
P3.7-20
P2.0-9
P2.0-8
P2.3-11
P2.0-8
P2.0-10
P2.3-16
P3.1-8
P2.0-9
P2.3-15
P3.1-6
P2.3-12
P2.3-11
TA0
TA1
TA2
VCC
VCC
P2.1-9
P1.7-23
P2.2-12
P2.1-10
P2.2-11
TA1.1
TA1.1
VSS
CCI1A
CCI1B
GND
P2.1-9
P1.7-23
P2.2-12
P3.2-13
P2.1-10
P2.2-11
P3.2-12
P2.2-10
P2.2-10
VCC
VCC
P2.4-12
P2.5-13
P2.4-17
P2.5-18
P2.4-16
P2.5-17
TA1.2
TA1.2
VSS
CCI2A
CCI2B
GND
P2.4-12
P2.5-13
P2.4-17
P2.5-18
P3.3-14
P2.4-16
P2.5-17
P3.3-13
VCC
VCC
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Universal Serial Communications Interface (USCI)
The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as
UART, enhanced UART with automatic baudrate detection (LIN), and IrDA. Not all packages support the USCI
functionality.
USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.
USCI_B0 provides support for SPI (3 or 4 pin) and I2C.
Comparator_A+
The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
ADC10 (MSP430G2x53 Only)
The ADC10 module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator, and data transfer controller (DTC) for automatic conversion
result handling, allowing ADC samples to be converted and stored without any CPU intervention.
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Peripheral File Map
Table 14. Peripherals With Word Access
REGISTER
OFFSET
NAME
MODULE
REGISTER DESCRIPTION
ADC10
ADC data transfer start address
ADC memory
ADC10SA
ADC10MEM
ADC10CTL1
ADC10CTL0
TACCR2
TACCR1
TACCR0
TAR
1BCh
1B4h
(MSP430G2x53 devices only)
ADC control register 1
ADC control register 0
Capture/compare register
Capture/compare register
Capture/compare register
Timer_A register
1B2h
1B0h
Timer1_A3
0196h
0194h
0192h
0190h
0186h
0184h
0182h
0180h
011Eh
0176h
0174h
0172h
0170h
0166h
0164h
0162h
0160h
012Eh
012Ch
012Ah
0128h
0120h
Capture/compare control
Capture/compare control
Capture/compare control
Timer_A control
TACCTL2
TACCTL1
TACCTL0
TACTL
Timer_A interrupt vector
Capture/compare register
Capture/compare register
Capture/compare register
Timer_A register
TAIV
Timer0_A3
TACCR2
TACCR1
TACCR0
TAR
Capture/compare control
Capture/compare control
Capture/compare control
Timer_A control
TACCTL2
TACCTL1
TACCTL0
TACTL
Timer_A interrupt vector
Flash control 3
TAIV
Flash Memory
FCTL3
Flash control 2
FCTL2
Flash control 1
FCTL1
Watchdog Timer+
Watchdog/timer control
WDTCTL
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Table 15. Peripherals With Byte Access
REGISTER
NAME
MODULE
REGISTER DESCRIPTION
OFFSET
USCI_B0
USCI_B0 transmit buffer
USCI_B0 receive buffer
USCI_B0 status
UCB0TXBUF
UCB0RXBUF
UCB0STAT
UCB0CIE
UCB0BR1
UCB0BR0
UCB0CTL1
UCB0CTL0
UCB0SA
UCB0OA
UCA0TXBUF
UCA0RXBUF
UCA0STAT
UCA0MCTL
UCA0BR1
UCA0BR0
UCA0CTL1
UCA0CTL0
UCA0IRRCTL
UCA0IRTCTL
UCA0ABCTL
ADC10AE0
ADC10AE1
ADC10DTC1
ADC10DTC0
CAPD
06Fh
06Eh
06Dh
06Ch
06Bh
06Ah
069h
068h
011Ah
0118h
067h
066h
065h
064h
063h
062h
061h
060h
05Fh
05Eh
05Dh
04Ah
04Bh
049h
048h
05Bh
05Ah
059h
053h
058h
057h
056h
043h
010h
01Bh
01Ah
019h
018h
042h
02Fh
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
USCI B0 I2C Interrupt enable
USCI_B0 bit rate control 1
USCI_B0 bit rate control 0
USCI_B0 control 1
USCI_B0 control 0
USCI_B0 I2C slave address
USCI_B0 I2C own address
USCI_A0 transmit buffer
USCI_A0 receive buffer
USCI_A0 status
USCI_A0
USCI_A0 modulation control
USCI_A0 baud rate control 1
USCI_A0 baud rate control 0
USCI_A0 control 1
USCI_A0 control 0
USCI_A0 IrDA receive control
USCI_A0 IrDA transmit control
USCI_A0 auto baud rate control
ADC analog enable 0
ADC analog enable 1
ADC data transfer control register 1
ADC data transfer control register 0
Comparator_A+ port disable
Comparator_A+ control 2
Comparator_A+ control 1
Basic clock system control 3
Basic clock system control 2
Basic clock system control 1
DCO clock frequency control
Port P3 selection 2. pin
Port P3 resistor enable
Port P3 selection
ADC10
(MSP430G2x53 devices only)
Comparator_A+
CACTL2
CACTL1
Basic Clock System+
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
P3SEL2
Port P3
(28-pin PW and 32-pin RHB only)
P3REN
P3SEL
Port P3 direction
P3DIR
Port P3 output
P3OUT
Port P3 input
P3IN
Port P2
Port P2 selection 2
P2SEL2
Port P2 resistor enable
Port P2 selection
P2REN
P2SEL
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
P2IE
P2IES
P2IFG
Port P2 direction
P2DIR
Port P2 output
P2OUT
Port P2 input
P2IN
18
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SLAS735A –APRIL 2011–REVISED MAY 2011
Table 15. Peripherals With Byte Access (continued)
REGISTER
NAME
MODULE
REGISTER DESCRIPTION
OFFSET
Port P1
Port P1 selection 2
P1SEL2
P1REN
P1SEL
P1IE
041h
027h
026h
025h
024h
023h
022h
021h
020h
003h
002h
001h
000h
Port P1 resistor enable
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
P1IES
P1IFG
P1DIR
P1OUT
P1IN
Port P1 output
Port P1 input
Special Function
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
IFG2
IFG1
IE2
IE1
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MSP430G2x53
MSP430G2x13
SLAS735A –APRIL 2011–REVISED MAY 2011
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Absolute Maximum Ratings(1)
Voltage applied at VCC to VSS
–0.3 V to 4.1 V
Voltage applied to any pin(2)
–0.3 V to VCC + 0.3 V
±2 mA
Diode current at any device pin
Unprogrammed device
Programmed device
–55°C to 150°C
–40°C to 85°C
(3)
Storage temperature range, Tstg
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Recommended Operating Conditions
MIN NOM
MAX UNIT
During program execution
1.8
3.6
VCC
Supply voltage
V
During flash
programming/erase
2.2
3.6
VSS
TA
Supply voltage
0
V
Operating free-air temperature
I version
–40
85
6
°C
VCC = 1.8 V,
Duty cycle = 50% ± 10%
dc
dc
dc
Processor frequency (maximum MCLK frequency using the VCC = 2.7 V,
USART module)(1)(2)
Duty cycle = 50% ± 10%
fSYSTEM
12 MHz
16
VCC = 3.3 V,
Duty cycle = 50% ± 10%
(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend:
16 MHz
Supply voltage range,
during flash memory
programming
12 MHz
Supply voltage range,
during program execution
6 MHz
3.3 V 3.6 V
2.7 V
Supply Voltage - V
1.8 V
2.2 V
Note: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 1. Safe Operating Area
20
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Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX UNIT
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 0 Hz,
2.2 V
230
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
Active mode (AM)
current at 1 MHz
IAM,1MHz
µA
3 V
330
420
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
Typical Characteristics, Active Mode Supply Current (Into VCC)
5.0
4.0
3.0
2.0
1.0
0.0
4.0
3.0
2.0
1.0
0.0
f
= 16 MHz
DCO
T
= 85 °C
= 25 °C
A
T
A
V
= 3 V
CC
f
= 12 MHz
DCO
T
= 85 °C
= 25 °C
A
T
A
f
= 8 MHz
DCO
2.0
f
= 1 MHz
V
CC
= 2.2 V
DCO
1.5
2.5
3.0
3.5
4.0
0.0
4.0
8.0
12.0
16.0
V
CC
− Supply Voltage − V
f
DCO
− DCO Frequency − MHz
Figure 2. Active Mode Current vs VCC, TA = 25°C
Figure 3. Active Mode Current vs DCO Frequency
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MSP430G2x53
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SLAS735A –APRIL 2011–REVISED MAY 2011
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Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(2)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX UNIT
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
Low-power mode 0
(LPM0) current(3)
ILPM0,1MHz
25°C
2.2 V
56
µA
fMCLK = fSMCLK = 0 MHz,
fDCO = 1 MHz,
fACLK = 32768 Hz,
Low-power mode 2
(LPM2) current(4)
ILPM2
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
25°C
2.2 V
22
µA
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 32768 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
Low-power mode 3
(LPM3) current(4)
ILPM3,LFXT1
ILPM3,VLO
ILPM4
25°C
25°C
2.2 V
2.2 V
2.2 V
0.7
0.5
1.5
0.7
µA
µA
µA
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from internal LF oscillator (VLO),
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
Low-power mode 3
current, (LPM3)(4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
25°C
85°C
0.1
0.8
0.5
1.7
Low-power mode 4
(LPM4) current(5)
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
(3) Current for brownout and WDT clocked by SMCLK included.
(4) Current for brownout and WDT clocked by ACLK included.
(5) Current for brownout included.
Typical Characteristics, Low-Power Mode Supply Currents
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
Vcc = 3.6 V
Vcc = 3 V
Vcc = 3.6 V
Vcc = 3 V
Vcc = 2.2 V
Vcc = 2.2 V
Vcc = 1.8 V
Vcc = 1.8 V
60 80
-40
-20
0
20
TA – Temperature – °C
Figure 5. LPM4 Current vs Temperature
40
-40
-20
0
20
40
60
80
TA – Temperature – °C
Figure 4. LPM3 Current vs Temperature
22
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Schmitt-Trigger Inputs, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
0.45 VCC
1.35
TYP
MAX UNIT
0.75 VCC
VIT+
Positive-going input threshold voltage
V
V
3 V
2.25
0.55 VCC
1.65
0.25 VCC
0.75
VIT–
Negative-going input threshold voltage
3 V
3 V
Vhys
RPull
CI
Input voltage hysteresis (VIT+ – VIT–
Pullup/pulldown resistor
Input capacitance
)
0.3
1
V
For pullup: VIN = VSS
For pulldown: VIN = VCC
3 V
20
35
5
50
kΩ
pF
VIN = VSS or VCC
Leakage Current, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
±50 nA
(1) (2)
Ilkg(Px.y)
High-impedance leakage current
3 V
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
Outputs, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –6 mA(1)
I(OLmax) = 6 mA(1)
VCC
3 V
3 V
MIN
TYP
MAX UNIT
VOH
VOL
High-level output voltage
Low-level output voltage
V
CC – 0.3
V
V
VSS + 0.3
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
Output Frequency, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Px.y, CL = 20 pF, RL = 1 kΩ(1) (2)
Px.y, CL = 20 pF(2)
VCC
3 V
3 V
MIN
TYP
12
MAX UNIT
MHz
Port output frequency
(with load)
fPx.y
fPort_CLK
Clock output frequency
16
MHz
(1) A resistive divider with two 0.5-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the
divider.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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Typical Characteristics, Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL LOW-LEVEL OUTPUT CURRENT
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
50
40
30
20
10
0
30
25
20
15
10
5
V
= 2.2 V
V
= 3 V
CC
CC
T
= 25°C
= 85°C
A
T
= 25°C
= 85°C
P1.7
A
P1.7
T
A
T
A
0
0
0.5
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
3
3.5
V
OL
− Low-Level Output Voltage − V
V
OL
− Low-Level Output Voltage − V
Figure 6.
Figure 7.
TYPICAL HIGH-LEVEL OUTPUT CURRENT
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
vs
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
0
−5
0
−10
−20
−30
−40
−50
V
= 2.2 V
V
= 3 V
CC
CC
P1.7
P1.7
−10
−15
−20
−25
T
A
= 85°C
T
= 85°C
A
T
A
= 25°C
0.5
T
= 25°C
0.5
A
0
1
1.5
2
2.5
0
1
1.5
2
2.5
3
3.5
V
OH
− High-Level Output Voltage − V
V
OH
− High-Level Output Voltage − V
Figure 8.
Figure 9.
24
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Pin-Oscillator Frequency – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
1400
900
MAX UNIT
P1.y, CL = 10 pF, RL = 100 kΩ(1)(2)
P1.y, CL = 20 pF, RL = 100 kΩ(1)(2)
P2.0 to P2.5, CL = 10 pF, RL = 100 kΩ(1)(2)
P2.0 to P2.5, CL = 20 pF, RL = 100 kΩ(1)(2)
foP1.x
Port output oscillation frequency
3 V
kHz
1800
1000
foP2.x
foP2.6/7
foP3.x
Port output oscillation frequency
Port output oscillation frequency
Port output oscillation frequency
kHz
kHz
kHz
3 V
3 V
P2.6 and P2.7, CL = 20 pF, RL = 100
700
kΩ(1)(2)
P3.y, CL = 10 pF, RL = 100 kΩ(1)(2)
P3.y, CL = 20 pF, RL = 100 kΩ(1)(2)
1800
1000
(1) A resistive divider with two 0.5-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the
divider.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Typical Characteristics, Pin-Oscillator Frequency
TYPICAL OSCILLATING FREQUENCY
TYPICAL OSCILLATING FREQUENCY
vs
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
1.50
1.35
1.20
1.05
0.90
0.75
0.60
0.45
0.30
0.15
0.00
1.50
1.35
1.20
1.05
0.90
0.75
0.60
0.45
0.30
0.15
0.00
V
CC
= 3.0 V
V
CC
= 2.2 V
P1.y
P1.y
P2.0 ... P2.5
P2.6, P2.7
P2.0 ... P2.5
P2.6, P2.7
10
50
100
10
50
100
C
LOAD
− External Capacitance − pF
C
LOAD
− External Capacitance − pF
A. One output active at a time.
A. One output active at a time.
Figure 10.
Figure 11.
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POR/Brownout Reset (BOR)(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
0.7 ×
V(B_IT--)
VCC(start)
See Figure 12
dVCC/dt ≤ 3 V/s
V
V(B_IT–)
Vhys(B_IT–)
td(BOR)
See Figure 12 through Figure 14
See Figure 12
dVCC/dt ≤ 3 V/s
dVCC/dt ≤ 3 V/s
1.35
140
V
mV
µs
See Figure 12
2000
Pulse length needed at RST/NMI pin to
accepted reset internally
t(reset)
2.2 V
2
µs
(1) The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT–)
+
Vhys(B_IT–)is ≤ 1.8 V.
V
CC
V
hys(B_IT−)
V
(B_IT−)
V
CC(start)
1
0
t
d(BOR)
Figure 12. POR/Brownout Reset (BOR) vs Supply Voltage
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Typical Characteristics, POR/Brownout Reset (BOR)
V
t
CC
pw
2
3 V
V
= 3 V
Typical Conditions
CC
1.5
1
V
CC(drop)
0.5
0
0.001
1
1000
1 ns
1 ns
− Pulse Width − µs
t
− Pulse Width − µs
t
pw
pw
Figure 13. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
V
t
CC
pw
2
1.5
1
3 V
V
= 3 V
CC
Typical Conditions
V
CC(drop)
0.5
t = t
f
r
0
0.001
1
1000
t
t
r
f
t
− Pulse Width − µs
t
− Pulse Width − µs
pw
pw
Figure 14. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
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DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
1.8
2.2
3
TYP
MAX UNIT
RSELx < 14
RSELx = 14
RSELx = 15
3.6
VCC
Supply voltage
3.6
3.6
V
fDCO(0,0)
fDCO(0,3)
fDCO(1,3)
fDCO(2,3)
fDCO(3,3)
fDCO(4,3)
fDCO(5,3)
fDCO(6,3)
fDCO(7,3)
fDCO(8,3)
fDCO(9,3)
fDCO(10,3)
fDCO(11,3)
fDCO(12,3)
fDCO(13,3)
fDCO(14,3)
fDCO(15,3)
fDCO(15,7)
DCO frequency (0, 0)
DCO frequency (0, 3)
DCO frequency (1, 3)
DCO frequency (2, 3)
DCO frequency (3, 3)
DCO frequency (4, 3)
DCO frequency (5, 3)
DCO frequency (6, 3)
DCO frequency (7, 3)
DCO frequency (8, 3)
DCO frequency (9, 3)
DCO frequency (10, 3)
DCO frequency (11, 3)
DCO frequency (12, 3)
DCO frequency (13, 3)
DCO frequency (14, 3)
DCO frequency (15, 3)
DCO frequency (15, 7)
RSELx = 0, DCOx = 0, MODx = 0
RSELx = 0, DCOx = 3, MODx = 0
RSELx = 1, DCOx = 3, MODx = 0
RSELx = 2, DCOx = 3, MODx = 0
RSELx = 3, DCOx = 3, MODx = 0
RSELx = 4, DCOx = 3, MODx = 0
RSELx = 5, DCOx = 3, MODx = 0
RSELx = 6, DCOx = 3, MODx = 0
RSELx = 7, DCOx = 3, MODx = 0
RSELx = 8, DCOx = 3, MODx = 0
RSELx = 9, DCOx = 3, MODx = 0
RSELx = 10, DCOx = 3, MODx = 0
RSELx = 11, DCOx = 3, MODx = 0
RSELx = 12, DCOx = 3, MODx = 0
RSELx = 13, DCOx = 3, MODx = 0
RSELx = 14, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 7, MODx = 0
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
0.06
0.07
0.14 MHz
0.17 MHz
MHz
0.15
0.21
0.30
0.41
0.58
MHz
MHz
MHz
MHz
0.54
0.80
1.06 MHz
1.50 MHz
MHz
1.6
2.3
MHz
3.4
MHz
4.25
MHz
4.30
6.00
8.60
12.0
16.0
7.30 MHz
9.60 MHz
13.9 MHz
18.5 MHz
26.0 MHz
7.8
Frequency step between
range RSEL and RSEL+1
SRSEL
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
3 V
1.35
ratio
Frequency step between
tap DCO and DCO+1
SDCO
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
Measured at SMCLK output
3 V
3 V
1.08
50
ratio
%
Duty cycle
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Calibrated DCO Frequencies, Tolerance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX UNIT
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
1-MHz tolerance over
temperature(1)
0°C to 85°C
3 V
-3
±0.5
3
3
6
3
3
6
3
3
6
3
3
6
%
%
%
%
%
%
%
%
%
%
%
%
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
1-MHz tolerance over VCC
1-MHz tolerance overall
30°C
1.8 V to 3.6 V
1.8 V to 3.6 V
3 V
-3
-6
-3
-3
-6
-3
-3
-6
-3
-3
-6
±2
±3
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
0°C to 85°C
30°C
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
8-MHz tolerance over
temperature(1)
±0.5
±2
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
8-MHz tolerance over VCC
8-MHz tolerance overall
2.2 V to 3.6 V
2.2 V to 3.6 V
3 V
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
0°C to 85°C
30°C
±3
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
12-MHz tolerance over
temperature(1)
±0.5
±2
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
12-MHz tolerance over VCC
12-MHz tolerance overall
2.7 V to 3.6 V
2.7 V to 3.6 V
3 V
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
0°C to 85°C
30°C
±3
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
16-MHz tolerance over
temperature(1)
±0.5
±2
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
16-MHz tolerance over VCC
16-MHz tolerance overall
3.3 V to 3.6 V
3.3 V to 3.6 V
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
±3
(1) This is the frequency change from the measured frequency at 30°C over temperature.
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MSP430G2x53
MSP430G2x13
SLAS735A –APRIL 2011–REVISED MAY 2011
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Wake-Up From Lower-Power Modes (LPM3/4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
DCO clock wake-up time from
LPM3/4(1)
BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz
tDCO,LPM3/4
tCPU,LPM3/4
3 V
1.5
µs
1/fMCLK
+
CPU wake-up time from LPM3/4(2)
tClock,LPM3/4
(1) The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge
observable externally on a clock pin (MCLK or SMCLK).
(2) Parameter applicable only if DCOCLK is used for MCLK.
Typical Characteristics, DCO Clock Wake-Up Time From LPM3/4
10.00
RSELx = 0...11
RSELx = 12...15
1.00
0.10
0.10
1.00
DCO Frequency − MHz
Figure 15. DCO Wake-Up Time From LPM3 vs DCO Frequency
10.00
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SLAS735A –APRIL 2011–REVISED MAY 2011
Crystal Oscillator, XT1, Low-Frequency Mode(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
LFXT1 oscillator crystal
frequency, LF mode 0, 1
fLFXT1,LF
XTS = 0, LFXT1Sx = 0 or 1
1.8 V to 3.6 V
32768
Hz
LFXT1 oscillator logic level
fLFXT1,LF,logic
square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3
LF mode
1.8 V to 3.6 V 10000
32768 50000
Hz
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
500
200
Oscillation allowance for
LF crystals
OALF
kΩ
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
XTS = 0, XCAPx = 0
XTS = 0, XCAPx = 1
XTS = 0, XCAPx = 2
XTS = 0, XCAPx = 3
1
5.5
8.5
11
Integrated effective load
capacitance, LF mode(2)
CL,eff
pF
XTS = 0, Measured at P2.0/ACLK,
fLFXT1,LF = 32768 Hz
Duty cycle
fFault,LF
LF mode
2.2 V
2.2 V
30
10
50
70
%
Oscillator fault frequency,
LF mode(3)
XTS = 0, XCAPx = 0, LFXT1Sx = 3(4)
10000
Hz
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
(3) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(4) Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLO frequency
VLO frequency temperature drift
TA
VCC
3 V
MIN
TYP
12
MAX UNIT
20 kHz
%/°C
fVLO
-40°C to 85°C
-40°C to 85°C
25°C
4
dfVLO/dT
3 V
0.5
4
dfVLO/dVCC VLO frequency supply voltage drift
1.8 V to 3.6 V
%/V
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SMCLK, duty cycle = 50% ± 10%
TA0, TA1
VCC
MIN
TYP
fSYSTEM
MAX UNIT
fTA
Timer_A input clock frequency
Timer_A capture timing
MHz
ns
tTA,cap
3 V
20
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MSP430G2x53
MSP430G2x13
SLAS735A –APRIL 2011–REVISED MAY 2011
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USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fUSCI
USCI input clock frequency
SMCLK, duty cycle = 50% ± 10%
fSYSTEM
MHz
Maximum BITCLK clock frequency
(equals baudrate in MBaud)(1)
UART receive deglitch time(2)
fmax,BITCLK
tτ
3 V
3 V
2
MHz
50
100
600
ns
(1) The DCO wake-up time must be considered in LPM3/4 for baud rates above 1 MHz.
(2) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their width should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 16 and
Figure 17)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fUSCI
USCI input clock frequency
SOMI input data setup time
SOMI input data hold time
SIMO output data valid time
SMCLK, duty cycle = 50% ± 10%
fSYSTEM MHz
tSU,MI
3 V
3 V
3 V
75
0
ns
ns
tHD,MI
tVALID,MO
UCLK edge to SIMO valid, CL = 20 pF
20
ns
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
SIMO
tHD,MO
tVALID,MO
Figure 16. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,MI
tSU,MI
SOMI
SIMO
tHD,MO
tVALID,MO
Figure 17. SPI Master Mode, CKPH = 1
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SLAS735A –APRIL 2011–REVISED MAY 2011
USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 18 and
Figure 19)
PARAMETER
TEST CONDITIONS
VCC
3 V
3 V
3 V
MIN
TYP
MAX UNIT
tSTE,LEAD
tSTE,LAG
tSTE,ACC
STE lead time, STE low to clock
STE lag time, Last clock to STE high
STE access time, STE low to SOMI data out
50
ns
ns
ns
10
50
50
STE disable time, STE high to SOMI high
impedance
tSTE,DIS
3 V
ns
tSU,SI
tHD,SI
SIMO input data setup time
SIMO input data hold time
3 V
3 V
15
10
ns
ns
UCLK edge to SOMI valid,
CL = 20 pF
tVALID,SO
SOMI output data valid time
3 V
50
75
ns
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tSU,SI
tLO/HI
tLO/HI
tHD,SI
SIMO
SOMI
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
Figure 18. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
SOMI
tHD,MO
tVALID,SO
tSTE,ACC
tSTE,DIS
Figure 19. SPI Slave Mode, CKPH = 1
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MSP430G2x53
MSP430G2x13
SLAS735A –APRIL 2011–REVISED MAY 2011
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USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 20)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fSYSTEM MHz
400 kHz
fUSCI
fSCL
USCI input clock frequency
SCL clock frequency
SMCLK, duty cycle = 50% ± 10%
3 V
3 V
0
4.0
0.6
4.7
0.6
0
f
f
f
f
SCL ≤ 100 kHz
SCL > 100 kHz
SCL ≤ 100 kHz
SCL > 100 kHz
tHD,STA
Hold time (repeated) START
µs
µs
tSU,STA
Setup time for a repeated START
3 V
tHD,DAT
tSU,DAT
tSU,STO
Data hold time
3 V
3 V
3 V
ns
ns
µs
Data setup time
Setup time for STOP
250
4.0
Pulse width of spikes suppressed by
input filter
tSP
3 V
50
100
600
ns
tHD,STA
tSU,STA
tHD,STA
tBUF
SDA
SCL
tLOW
tHIGH
tSP
tSU,DAT
tSU,STO
tHD,DAT
Figure 20. I2C Mode Timing
Comparator_A+
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
(1)
I(DD)
CAON = 1, CARSEL = 0, CAREF = 0
3 V
45
µA
I(Refladder/
RefDiode)
V(IC)
CAON = 1, CARSEL = 0, CAREF = 1/2/3,
No load at CA0 and CA1
3 V
3 V
3 V
45
µA
Common–mode input voltage
CAON = 1
0
VCC-1
V
PCA0 = 1, CARSEL = 1, CAREF = 1,
No load at CA0 and CA1
V(Ref025)
V(Ref050)
V(RefVT)
(Voltage at 0.25 VCC node) / VCC
0.24
0.48
490
PCA0 = 1, CARSEL = 1, CAREF = 2,
No load at CA0 and CA1
(Voltage at 0.5 VCC node) / VCC
See Figure 21 and Figure 22
3 V
3 V
PCA0 = 1, CARSEL = 1, CAREF = 3,
No load at CA0 and CA1, TA = 85°C
mV
V(offset)
Vhys
Offset voltage(2)
Input hysteresis
3 V
3 V
±10
mV
mV
CAON = 1
0.7
TA = 25°C, Overdrive 10 mV,
Without filter: CAF = 0
120
1.5
ns
Response time
(low-high and high-low)
t(response)
3 V
TA = 25°C, Overdrive 10 mV,
With filter: CAF = 1
µs
(1) The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.y) specification.
(2) The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements. The
two successive measurements are then summed together.
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Typical Characteristics – Comparator_A+
650
650
VCC = 3 V
VCC = 2.2 V
600
550
500
450
400
600
Typical
Typical
550
500
450
400
-45
-25
-5
15
35
55
75
95
115
-45
-25
-5
15
35
55
75
95
115
TA – Free-Air Temperature – °C
TA – Free-Air Temperature – °C
Figure 21. V(RefVT) vs Temperature, VCC = 3 V
Figure 22. V(RefVT) vs Temperature, VCC = 2.2 V
100
VCC = 1.8 V
VCC = 2.2 V
VCC = 3 V
10
VCC = 3.6 V
1
0
0.4
0.6
0.8
1
0.2
VIN/VCC – Normalized Input Voltage – V/V
Figure 23. Short Resistance vs VIN/VCC
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MSP430G2x53
MSP430G2x13
SLAS735A –APRIL 2011–REVISED MAY 2011
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MAX UNIT
10-Bit ADC, Power Supply and Input Range Conditions (MSP430G2x53 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VSS = 0 V
TA
VCC
3 V
3 V
MIN
TYP
VCC
VAx
Analog supply voltage
2.2
3.6
V
V
All Ax terminals, Analog inputs
selected in ADC10AE register
Analog input voltage(2)
ADC10 supply current(3)
0
VCC
fADC10CLK = 5.0 MHz,
ADC10ON = 1, REFON = 0,
ADC10SHT0 = 1, ADC10SHT1 = 0,
ADC10DIV = 0
IADC10
25°C
25°C
0.6
mA
mA
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REF2_5V = 0,
REFON = 1, REFOUT = 0
0.25
0.25
Reference supply current,
reference buffer disabled(4)
IREF+
3 V
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REF2_5V = 1,
REFON = 1, REFOUT = 0
fADC10CLK = 5.0 MHz,
Reference buffer supply
ADC10ON = 0, REFON = 1,
IREFB,0
25°C
25°C
3 V
3 V
1.1
0.5
mA
mA
current with ADC10SR = 0(4) REF2_5V = 0, REFOUT = 1,
ADC10SR = 0
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REFON = 1,
Reference buffer supply
IREFB,1
current with ADC10SR = 1(4) REF2_5V = 0, REFOUT = 1,
ADC10SR = 1
Only one terminal Ax can be selected
CI
RI
Input capacitance
at one time
25°C
25°C
3 V
3 V
27
pF
Input MUX ON resistance
0 V ≤ VAx ≤ VCC
1000
Ω
(1) The leakage current is defined in the leakage current table with Px.y/Ax parameter.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
(3) The internal reference supply current is not included in current consumption parameter IADC10
.
(4) The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
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SLAS735A –APRIL 2011–REVISED MAY 2011
10-Bit ADC, Built-In Voltage Reference (MSP430G2x53 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VREF+ ≤ 1 mA, REF2_5V = 0
VCC
MIN
2.2
TYP
MAX UNIT
I
I
I
I
Positive built-in reference
analog supply voltage range
VCC,REF+
V
VREF+ ≤ 1 mA, REF2_5V = 1
2.9
VREF+ ≤ IVREF+max, REF2_5V = 0
VREF+ ≤ IVREF+max, REF2_5V = 1
1.41
2.35
1.5
2.5
1.59
V
Positive built-in reference
voltage
VREF+
3 V
3 V
2.65
Maximum VREF+ load
current
ILD,VREF+
±1
±2
mA
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≉ 0.75 V,
REF2_5V = 0
VREF+ load regulation
3 V
3 V
LSB
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≉ 1.25 V,
REF2_5V = 1
±2
IVREF+ = 100 µA→900 µA,
VAx ≉ 0.5 × VREF+,
Error of conversion result ≤ 1 LSB,
VREF+ load regulation
response time
400
ns
ADC10SR = 0
Maximum capacitance at
pin VREF+
CVREF+
TCREF+
I
VREF+ ≤ ±1 mA, REFON = 1, REFOUT = 1
3 V
3 V
100
pF
ppm/
°C
Temperature coefficient
IVREF+ = const with 0 mA ≤ IVREF+ ≤ 1 mA
±100
Settling time of internal
reference voltage to 99.9%
VREF
IVREF+ = 0.5 mA, REF2_5V = 0,
REFON = 0 → 1
tREFON
3.6 V
3 V
30
2
µs
µs
IVREF+ = 0.5 mA,
REF2_5V = 1, REFON = 1,
REFBURST = 1, ADC10SR = 0
Settling time of reference
buffer to 99.9% VREF
tREFBURST
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MSP430G2x53
MSP430G2x13
SLAS735A –APRIL 2011–REVISED MAY 2011
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MAX UNIT
10-Bit ADC, External Reference(1) (MSP430G2x53 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
VEREF+ > VEREF–,
SREF1 = 1, SREF0 = 0
1.4
VCC
Positive external reference input
voltage range
VEREF+
V
(2)
VEREF– ≤ VEREF+ ≤ VCC – 0.15 V,
SREF1 = 1, SREF0 = 1
1.4
0
3
(3)
Negative external reference input
VEREF–
ΔVEREF
VEREF+ > VEREF–
1.2
V
V
(4)
voltage range
Differential external reference
input voltage range,
(5)
VEREF+ > VEREF–
1.4
VCC
ΔVEREF = VEREF+ – VEREF–
0 V ≤ VEREF+ ≤ VCC
SREF1 = 1, SREF0 = 0
,
3 V
±1
IVEREF+
Static input current into VEREF+
µA
µA
0 V ≤ VEREF+ ≤ VCC – 0.15 V ≤ 3 V,
3 V
3 V
0
SREF1 = 1, SREF0 = 1(3)
IVEREF–
Static input current into VEREF–
0 V ≤ VEREF– ≤ VCC
±1
(1) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply
current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
(4) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(5) The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
10-Bit ADC, Timing Parameters (MSP430G2x53 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
0.45
0.45
TYP
MAX
6.3
UNIT
ADC10SR = 0
ADC10SR = 1
ADC10 input clock
frequency
For specified performance of
ADC10 linearity parameters
fADC10CLK
fADC10OSC
3 V
MHz
1.5
ADC10 built-in oscillator ADC10DIVx = 0, ADC10SSELx = 0,
3 V
3 V
3.7
6.3
MHz
µs
frequency
fADC10CLK = fADC10OSC
ADC10 built-in oscillator, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
2.06
3.51
tCONVERT
Conversion time
13 ×
fADC10CLK from ACLK, MCLK, or SMCLK:
ADC10DIV ×
1/fADC10CLK
ADC10SSELx ≠ 0
Turn-on settling time of
the ADC
(1)
tADC10ON
100
ns
(1) The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
10-Bit ADC, Linearity Parameters (MSP430G2x53 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Integral linearity error
Differential linearity error
Offset error
TEST CONDITIONS
VCC
3 V
3 V
3 V
3 V
3 V
MIN
TYP
MAX UNIT
±1 LSB
±1 LSB
±1 LSB
±2 LSB
±5 LSB
EI
ED
EO
EG
ET
Source impedance RS < 100 Ω
Gain error
±1.1
±2
Total unadjusted error
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SLAS735A –APRIL 2011–REVISED MAY 2011
10-Bit ADC, Temperature Sensor and Built-In VMID (MSP430G2x53 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
3 V
3 V
3 V
3 V
3 V
MIN
TYP
60
MAX UNIT
Temperature sensor supply
current(1)
REFON = 0, INCHx = 0Ah,
TA = 25°C
ISENSOR
TCSENSOR
tSensor(sample)
IVMID
µA
mV/°C
µs
(2)
ADC10ON = 1, INCHx = 0Ah
ADC10ON = 1, INCHx = 0Ah,
Error of conversion result ≤ 1 LSB
3.55
Sample time required if channel
30
(3)
10 is selected
(4)
Current into divider at channel 11 ADC10ON = 1, INCHx = 0Bh
µA
ADC10ON = 1, INCHx = 0Bh,
VCC divider at channel 11
VMID
1.5
V
V
MID ≉ 0.5 × VCC
Sample time required if channel
11 is selected
ADC10ON = 1, INCHx = 0Bh,
Error of conversion result ≤ 1 LSB
tVMID(sample)
3 V
1220
ns
(5)
(1) The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature sensor
input (INCH = 0Ah).
(2) The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor (273 + T [°C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV]
(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
(4) No additional current is needed. The VMID is used during sampling.
.
(5) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(PGM/ERASE) Program and erase supply voltage
2.2
3.6
476
5
V
kHz
mA
fFTG
Flash timing generator frequency
Supply current from VCC during program
Supply current from VCC during erase
Cumulative program time(1)
257
IPGM
2.2 V/3.6 V
2.2 V/3.6 V
2.2 V/3.6 V
2.2 V/3.6 V
1
1
IERASE
tCPT
7
mA
10
ms
tCMErase
Cumulative mass erase time
20
104
100
ms
Program/erase endurance
105
cycles
years
tFTG
tFTG
tRetention
tWord
Data retention duration
TJ = 25°C
(2)
Word or byte program time
30
25
(2)
(2)
tBlock, 0
Block program time for first byte or word
Block program time for each additional byte or
word
tBlock, 1-63
18
tFTG
(2)
(2)
(2)
tBlock, End
tMass Erase
tSeg Erase
Block program end-sequence wait time
Mass erase time
6
10593
4819
tFTG
tFTG
tFTG
Segment erase time
(1) The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
(2) These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG).
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RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
CPU halted
MIN
MAX
UNIT
(1)
V(RAMh)
RAM retention supply voltage
1.6
V
(1) This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
0
TYP
MAX
20
UNIT
MHz
µs
fSBW
Spy-Bi-Wire input frequency
2.2 V
2.2 V
tSBW,Low Spy-Bi-Wire low clock pulse length
0.025
15
Spy-Bi-Wire enable time
tSBW,En
2.2 V
1
µs
(TEST high to acceptance of first clock edge(1)
)
tSBW,Ret
fTCK
Spy-Bi-Wire return to normal operation time
TCK input frequency(2)
2.2 V
2.2 V
2.2 V
15
0
100
5
µs
MHz
kΩ
RInternal
Internal pulldown resistance on TEST
25
60
90
(1) Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before
applying the first SBWCLK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
JTAG Fuse(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
MIN
2.5
6
MAX
UNIT
V
VCC(FB)
VFB
Supply voltage during fuse-blow condition
Voltage level on TEST for fuse blow
Supply current into TEST during fuse blow
Time to blow fuse
7
100
1
V
IFB
mA
ms
tFB
(1) Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to
bypass mode.
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SLAS735A –APRIL 2011–REVISED MAY 2011
PORT SCHEMATICS
Port P1 Pin Schematic: P1.0 to P1.2, Input/Output With Schmitt Trigger
To Comparator
From Comparator
To ADC10 *
INCHx = y *
CAPD.y
or ADC10AE0.y *
PxSEL2.y
PxSEL.y
PxDIR.y
0
From Timer
1
Direction
0: Input
1: Output
1
2
3
From USCI
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
0
1
1
PxOUT.y
0
1
From Timer
2
3
Bus
Keeper
EN
P1.0/TA0CLK/ACLK/
A0*/CA0
0
P1.1/TA0.0/UCA0RXD/
UCA0SOMI/A1*/CA1
P1.2/TA0.1/UCA0TXD/
UCA0SIMO/A2*/CA2
TAx.y
TAxCLK
PxIN.y
EN
To Module
PxIRQ.y
D
PxIE.y
EN
Set
Q
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
* Note: MSP430G2x53 devices only. MSP430G2x13 devices have no ADC10.
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MSP430G2x13
SLAS735A –APRIL 2011–REVISED MAY 2011
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CAPD.y
Table 16. Port P1 (P1.0 to P1.2) Pin Functions
CONTROL BITS / SIGNALS(1)
PIN NAME
(P1.x)
x
FUNCTION
ADC10AE.x
P1DIR.x
P1SEL.x
P1SEL2.x
INCH.x=1(2)
P1.0/
P1.x (I/O)
I: 0; O: 1
0
1
1
X
X
0
0
1
1
1
1
X
X
0
0
1
1
1
1
X
X
0
0
0
0
X
X
1
0
0
0
1
1
X
X
1
0
0
0
1
1
X
X
1
0
0
TA0CLK/
ACLK/
TA0.TACLK
ACLK
0
0
0
1
0
0
0
A0(2)
/
A0
X
1 (y = 0)
0
CA0/
CA0
X
0
1 (y = 0)
Pin Osc
P1.1/
Capacitive sensing
P1.x (I/O)
TA0.0
X
0
0
I: 0; O: 1
0
0
TA0.0/
1
0
0
TA0.CCI0A
UCA0RXD
UCA0SOMI
A1
0
0
0
UCA0RXD/
UCA0SOMI/
from USCI
0
0
1
from USCI
0
0
A1(2)
CA1/
/
X
1 (y = 1)
0
CA1
X
0
1 (y = 1)
Pin Osc
P1.2/
Capacitive sensing
P1.x (I/O)
TA0.1
X
0
0
I: 0; O: 1
0
0
TA0.1/
1
0
0
TA0.CCI1A
UCA0TXD
UCA0SIMO
A2
0
0
0
UCA0TXD/
from USCI
0
0
2
UCA0SIMO/
from USCI
0
0
A2(2)
/
X
X
X
1 (y = 2)
0
1 (y = 2)
0
CA2/
CA2
0
0
Pin Osc
(1) X = don't care
Capacitive sensing
(2) MSP430G2x53 devices only
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SLAS735A –APRIL 2011–REVISED MAY 2011
Port P1 Pin Schematic: P1.3, Input/Output With Schmitt Trigger
SREF2 *
VSS
0
1
To ADC10 VREF- *
To Comparator
from Comparator
To ADC10 *
INCHx = y *
CAPD.y
or ADC10AE0.y *
PxSEL2.y PxSEL.y
PxDIR.y
0,2,3
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
0
1
1
PxOUT.y
0
1
From ADC10 *
2
3
Bus
Keeper
EN
P1.3/ADC10CLK*/CAOUT/
A3*/VREF-*/VEREF-*/CA3
From Comparator
TAx.y
TAxCLK
PxIN.y
EN
D
To Module
PxIRQ.y
PxIE.y
EN
Set
Q
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
* Note: MSP430G2x53 devices only. MSP430G2x13 devices have no ADC10.
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MSP430G2x13
SLAS735A –APRIL 2011–REVISED MAY 2011
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CAPD.y
Table 17. Port P1 (P1.3) Pin Functions
CONTROL BITS / SIGNALS(1)
PIN NAME
x
FUNCTION
ADC10AE.x
(P1.x)
P1DIR.x
P1SEL.x
P1SEL2.x
INCH.x=1(2)
P1.3/
ADC10CLK(2)
A3(2)
VREF-(2)
P1.x (I/O)
I: 0; O: 1
0
1
0
0
0
0
/
ADC10CLK
A3
1
X
X
X
X
X
0
0
/
X
X
X
X
0
X
X
X
X
1
1 (y = 3)
0
/
3
VREF-
1
1
0
0
0
VEREF-(2)
/
VEREF-
CA3
0
1 (y = 3)
0
CA3/
Pin Osc
Capacitive sensing
(1) X = don't care
(2) MSP430G2x53 devices only
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MSP430G2x13
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SLAS735A –APRIL 2011–REVISED MAY 2011
Port P1 Pin Schematic: P1.4, Input/Output With Schmitt Trigger
From/To ADC10 Ref+ *
To Comparator
from Comparator
To ADC10 *
INCHx = y *
CAPD.y
or ADC10AE0.y *
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
0
1
1
PxOUT.y
SMCLK
0
1
2
3
Bus
Keeper
EN
P1.4/SMCLK/TA0.2/A4*/
VREF+*/VEREF+*/CA4/TCK
From Module
TAx.y
TAxCLK
PxIN.y
EN
D
To Module
PxIRQ.y
PxIE.y
EN
Q
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
From JTAG
To JTAG
* Note: MSP430G2x52 devices only. MSP430G2x12 devices have no ADC10.
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SLAS735A –APRIL 2011–REVISED MAY 2011
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CAPD.y
Table 18. Port P1 (P1.4) Pin Functions
CONTROL BITS / SIGNALS(1)
PIN NAME
x
FUNCTION
ADC10AE.x
INCH.x=1(2)
(P1.x)
P1DIR.x
P1SEL.x
P1SEL2.x
JTAG Mode
P1.4/
P1.x (I/O)
SMCLK
UCB0STE
UCA0CLK
VREF+
VEREF+
A4
I: 0; O: 1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
SMCLK/
1
0
0
UCB0STE/
UCA0CLK/
VREF+(2)
VEREF+(2)
from USCI
1
1
0
0
from USCI
1
1
0
0
/
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
4
/
1
0
A4(2)
CA4
/
1 (y = 4)
0
1 (y = 4)
0
CA4
0
0
TCK/
TCK
Capacitive
sensing
Pin Osc
X
0
1
0
0
0
(1) X = don't care
(2) MSP430G2x53 devices only
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MSP430G2x13
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SLAS735A –APRIL 2011–REVISED MAY 2011
Port P1 Pin Schematic: P1.5 to P1.7, Input/Output With Schmitt Trigger
To Comparator
From Comparator
To ADC10 *
INCHx = y *
CAPD.y
ADC10AE0.y *
PxSEL2.y
PxSEL.y
PxDIR.y
0
1
From Module
Direction
0: Input
1: Output
2
3
From Module
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
0
1
1
PxOUT.y
0
1
From Module
2
3
Bus
Keeper
EN
From Module
P1.5/TA0.0/UCB0CLK/UCA0STE/
A5*/CA5/TMS
P1.6/TA0.1/UCB0SOMI/UCB0SCL/
A6*/CA6/TDI/TCLK
P1.7/CAOUT/UCB0SIMO/UCB0SDA/
A7*/CA7/TDO/TDI
TAx.y
TAxCLK
PxIN.y
EN
D
To Module
PxIRQ.y
PxIE.y
EN
Set
Q
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
From JTAG
To JTAG
* Note: MSP430G2x53 devices only. MSP430G2x13 devices have no ADC10.
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MSP430G2x13
SLAS735A –APRIL 2011–REVISED MAY 2011
www.ti.com
CAPD.y
Table 19. Port P1 (P1.5 to P1.7) Pin Functions
CONTROL BITS / SIGNALS(1)
PIN NAME
(P1.x)
x
FUNCTION
ADC10AE.x
P1DIR.x
P1SEL.x
P1SEL2.x
JTAG Mode
INCH.x=1(2)
P1.5/
P1.x (I/O)
TA0.0
I: 0; O: 1
0
1
0
0
0
0
0
0
0
0
0
1
0
TA0.0/
1
0
0
UCB0CLK/
UCA0STE/
UCB0CLK
UCA0STE
A5
from USCI
1
1
0
0
from USCI
1
1
0
0
A5(2)
CA5
TMS
/
X
X
X
X
X
X
X
X
X
1 (y = 5)
0
1 (y = 5)
0
5
CA5
0
0
TMS
Capacitive
sensing
Pin Osc
X
0
1
0
0
0
P1.6/
P1.x (I/O)
TA0.1
I: 0; O: 1
0
1
0
0
0
0
0
0
0
0
0
1
0
TA0.1/
1
0
0
UCB0SOMI/
UCB0SCL/
UCB0SOMI
UCB0SCL
A6
from USCI
1
1
0
0
from USCI
1
1
0
0
A6(2)
/
X
X
X
X
X
X
X
X
X
1 (y = 6)
0
1 (y = 6)
0
6
CA6
CA6
0
0
TDI/TCLK/
Pin Osc
TDI/TCLK
Capacitive
sensing
X
0
1
0
0
0
P1.7/
P1.x (I/O)
UCB0SIMO
UCB0SDA
A7
I: 0; O: 1
0
1
0
1
0
0
0
0
0
0
0
1
0
UCB0SIMO/
UCB0SDA/
from USCI
0
0
from USCI
1
1
0
0
A7(2)
/
X
X
1
X
X
1
X
X
0
1 (y = 7)
0
7
CA7
CA7
0
0
0
1 (y = 7)
CAOUT
CAOUT
TDO/TDI
0
0
TDO/TDI/
X
X
X
Capacitive
sensing
Pin Osc
X
0
1
0
0
0
(1) X = don't care
(2) MSP430G2x53 devices only
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MSP430G2x13
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SLAS735A –APRIL 2011–REVISED MAY 2011
Port P2 Pin Schematic: P2.0 to P2.5, Input/Output With Schmitt Trigger
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
0
1
1
PxOUT.y
0
From Timer
1
2
3
P2.0/TA1.0
P2.1/TA1.1
P2.2/TA1.1
P2.3/TA1.0
P2.4/TA1.2
P2.5/TA1.2
0
TAx.y
TAxCLK
PxIN.y
EN
D
To Module
PxIRQ.y
PxIE.y
EN
Set
Q
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
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Table 20. Port P2 (P2.0 to P2.5) Pin Functions
CONTROL BITS / SIGNALS(1)
PIN NAME
(P2.x)
x
FUNCTION
P2DIR.x
P2SEL.x
P2SEL2.x
P2.0/
P2.x (I/O)
I: 0; O: 1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
TA1.0/
Timer1_A3.CCI0A
Timer1_A3.TA0
Capacitive sensing
P2.x (I/O)
0
0
1
2
3
4
5
1
Pin Osc
P2.1/
X
I: 0; O: 1
TA1.1/
Timer1_A3.CCI1A
Timer1_A3.TA1
Capacitive sensing
P2.x (I/O)
0
1
Pin Osc
P2.2/
X
I: 0; O: 1
TA1.1/
Timer1_A3.CCI1B
Timer1_A3.TA1
Capacitive sensing
P2.x (I/O)
0
1
Pin Osc
P2.3/
X
I: 0; O: 1
TA1.0/
Timer1_A3.CCI0B
Timer1_A3.TA0
Capacitive sensing
P2.x (I/O)
0
1
Pin Osc
P2.4/
X
I: 0; O: 1
TA1.2/
Timer1_A3.CCI2A
Timer1_A3.TA2
Capacitive sensing
P2.x (I/O)
0
1
Pin Osc
P2.5/
X
I: 0; O: 1
TA1.2/
Timer1_A3.CCI2B
Timer1_A3.TA2
Capacitive sensing
0
1
Pin Osc
X
(1) X = don't care
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MSP430G2x13
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SLAS735A –APRIL 2011–REVISED MAY 2011
Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger
XOUT/P2.7
LF off
PxSEL.6 and PxSEL.7
BCSCTL3.LFXT1Sx = 11
0
LFXT1CLK
1
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
0
1
1
PxOUT.y
0
1
From Module
2
3
XIN/P2.6/TA0.1
TAx.y
TAxCLK
PxIN.y
EN
D
To Module
PxIRQ.y
PxIE.y
EN
Set
Q
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
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Table 21. Port P2 (P2.6) Pin Functions
CONTROL BITS / SIGNALS(1)
PIN NAME
(P2.x)
x
FUNCTION
P2SEL.6
P2SEL.7
P2SEL2.6
P2SEL2.7
P2DIR.x
1
1
0
0
XIN
XIN
0
0
X
0
0
P2.6
P2.x (I/O)
I: 0; O: 1
6
1
0
0
0
TA0.1
Pin Osc
Timer0_A3.TA1
Capacitive sensing
1
0
X
1
X
X
(1) X = don't care
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SLAS735A –APRIL 2011–REVISED MAY 2011
Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger
XIN
LF off
PxSEL.6 and PxSEL.7
BCSCTL3.LFXT1Sx = 11
LFXT1CLK
PxDIR.y
0
1
from P2.6
PxSEL.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
0
1
1
PxOUT.y
0
1
From Module
2
3
XOUT/P2.7
TAx.y
TAxCLK
PxIN.y
EN
D
To Module
PxIRQ.y
PxIE.y
EN
Set
Q
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
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MSP430G2x53
MSP430G2x13
SLAS735A –APRIL 2011–REVISED MAY 2011
www.ti.com
Table 22. Port P2 (P2.7) Pin Functions
CONTROL BITS / SIGNALS(1)
PIN NAME
(P2.x)
x
FUNCTION
P2SEL.6
P2SEL.7
P2SEL2.6
P2SEL2.7
P2DIR.x
1
1
0
0
XOUT/
P2.7/
XOUT
1
I: 0; O: 1
X
0
X
0
0
7
P2.x (I/O)
0
X
1
X
Pin Osc
Capacitive sensing
(1) X = don't care
54
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MSP430G2x53
MSP430G2x13
www.ti.com
SLAS735A –APRIL 2011–REVISED MAY 2011
Port P3 Pin Schematic: P3.0 to P3.7, Input/Output With Schmitt Trigger (RHB Package Only)
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
0
1
1
PxOUT.y
0
1
From Module
2
3
P3.0/TA0.2
P3.1/TA1.0
P3.2/TA1.1
P3.3/TA1.2
P3.4/TA0.0
P3.5/TA0.1
TAx.y
TAxCLK
P3.6/TA0.2
P3.7/TA1CLK/CAOUT
PxIN.y
EN
D
To Module
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MSP430G2x53
MSP430G2x13
SLAS735A –APRIL 2011–REVISED MAY 2011
www.ti.com
Table 23. Port P3 (P3.0 to P3.7) Pin Functions (RHB Package Only)
CONTROL BITS / SIGNALS(1)
PIN NAME
(P3.x)
x
FUNCTION
P3DIR.x
P3SEL.x
P3SEL2.x
P3.0/
P3.x (I/O)
I: 0; O: 1
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
1
TA0.2/
Timer0_A3.CCI2A
Timer0_A3.TA2
Capacitive sensing
P3.x (I/O)
0
0
1
Pin Osc
P3.1/
X
I: 0; O: 1
TA1.0/
Pin Osc
P3.2/
1
2
3
4
5
6
Timer1_A3.TA0
Capacitive sensing
P3.x (I/O)
1
X
I: 0; O: 1
TA1.1/
Pin Osc
P3.3/
Timer1_A3.TA1
Capacitive sensing
P3.x (I/O)
1
X
I: 0; O: 1
TA1.2/
Pin Osc
P3.4/
Timer1_A3.TA2
Capacitive sensing
P3.x (I/O)
1
X
I: 0; O: 1
TA0.0/
Pin Osc
P3.5/
Timer0_A3.TA0
Capacitive sensing
P3.x (I/O)
1
X
I: 0; O: 1
TA0.1/
Pin Osc
P3.6/
Timer0_A3.TA1
Capacitive sensing
P3.x (I/O)
1
X
I: 0; O: 1
TA0.2/
Pin Osc
P3.7/
Timer0_A3.TA2
Capacitive sensing
P3.x (I/O)
1
X
I: 0; O: 1
TA1CLK/
CAOUT/
Pin Osc
Timer1_A3.TACLK
Comparator output
Capacitive sensing
0
1
7
X
(1) X = don't care
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MSP430G2x53
MSP430G2x13
www.ti.com
SLAS735A –APRIL 2011–REVISED MAY 2011
REVISION HISTORY
REVISION
DESCRIPTION
SLAS735
Initial release
Changed Control Bits / Signals column in Table 18
Changed Pin Name and Function columns in Table 23
SLAS735A
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PACKAGE OPTION ADDENDUM
www.ti.com
28-May-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
MSP430G2153IN20
MSP430G2153IPW20
ACTIVE
ACTIVE
PDIP
N
20
20
20
70
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
TSSOP
PW
Green (RoHS
& no Sb/Br)
MSP430G2153IPW20R
MSP430G2153IPW28
MSP430G2153IPW28R
MSP430G2153IRHB32R
MSP430G2153IRHB32T
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
QFN
PW
PW
20
28
28
32
32
2000
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
PW
2000
3000
250
Green (RoHS
& no Sb/Br)
RHB
RHB
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
MSP430G2213IN20
MSP430G2213IPW20
ACTIVE
ACTIVE
PDIP
N
20
20
20
70
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
TSSOP
PW
Green (RoHS
& no Sb/Br)
MSP430G2213IPW20R
MSP430G2213IPW28
MSP430G2213IPW28R
MSP430G2213IRHB32R
MSP430G2213IRHB32T
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
QFN
PW
PW
20
28
28
32
32
2000
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
PW
2000
3000
250
Green (RoHS
& no Sb/Br)
RHB
RHB
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
MSP430G2253IN20
MSP430G2253IPW20
ACTIVE
ACTIVE
PDIP
N
20
20
20
70
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
TSSOP
PW
Green (RoHS
& no Sb/Br)
MSP430G2253IPW20R
MSP430G2253IPW28
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
20
28
2000
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-May-2011
Status (1)
ACTIVE
ACTIVE
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
MSP430G2253IPW28R
MSP430G2253IRHB32R
MSP430G2253IRHB32T
TSSOP
QFN
PW
RHB
RHB
28
32
32
2000
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
QFN
Green (RoHS
& no Sb/Br)
MSP430G2313IN20
MSP430G2313IPW20
ACTIVE
ACTIVE
PDIP
N
20
20
20
70
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
TSSOP
PW
Green (RoHS
& no Sb/Br)
MSP430G2313IPW20R
MSP430G2313IPW28
MSP430G2313IPW28R
MSP430G2313IRHB32R
MSP430G2313IRHB32T
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
QFN
PW
PW
20
28
28
32
32
2000
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
PW
2000
3000
250
Green (RoHS
& no Sb/Br)
RHB
RHB
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
MSP430G2353IN20
MSP430G2353IPW20
ACTIVE
ACTIVE
PDIP
N
20
20
20
70
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
TSSOP
PW
Green (RoHS
& no Sb/Br)
MSP430G2353IPW20R
MSP430G2353IPW28
MSP430G2353IPW28R
MSP430G2353IRHB32R
MSP430G2353IRHB32T
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
QFN
PW
PW
20
28
28
32
32
2000
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
PW
2000
3000
250
Green (RoHS
& no Sb/Br)
RHB
RHB
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
MSP430G2413IN20
MSP430G2413IPW20
ACTIVE
ACTIVE
PDIP
N
20
20
20
70
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
TSSOP
PW
Green (RoHS
& no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
28-May-2011
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
MSP430G2413IPW20R
MSP430G2413IPW28
MSP430G2413IPW28R
MSP430G2413IRHB32R
MSP430G2413IRHB32T
TSSOP
TSSOP
TSSOP
QFN
PW
PW
20
28
28
32
32
2000
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
PW
2000
3000
250
Green (RoHS
& no Sb/Br)
RHB
RHB
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
MSP430G2453IN20
MSP430G2453IPW20
ACTIVE
ACTIVE
PDIP
N
20
20
20
70
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
TSSOP
PW
Green (RoHS
& no Sb/Br)
MSP430G2453IPW20R
MSP430G2453IPW28
MSP430G2453IPW28R
MSP430G2453IRHB32R
MSP430G2453IRHB32T
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
QFN
PW
PW
20
28
28
32
32
2000
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
PW
2000
3000
250
Green (RoHS
& no Sb/Br)
RHB
RHB
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
MSP430G2513IN20
MSP430G2513IPW20
ACTIVE
ACTIVE
PDIP
N
20
20
20
70
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
TSSOP
PW
Green (RoHS
& no Sb/Br)
MSP430G2513IPW20R
MSP430G2513IPW28
MSP430G2513IPW28R
MSP430G2513IRHB32R
MSP430G2513IRHB32T
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
QFN
PW
PW
20
28
28
32
32
2000
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
PW
2000
3000
250
Green (RoHS
& no Sb/Br)
RHB
RHB
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
28-May-2011
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
MSP430G2553CY
PREVIEW
DIESALE
Y
0
1
Green (RoHS
& no Sb/Br)
Call TI
N / A for Pkg Type
MSP430G2553CYS
MSP430G2553GACYS
MSP430G2553IN20
MSP430G2553IPW20
PREVIEW WAFERSALE
PREVIEW WAFERSALE
YS
YS
N
0
0
1
1
TBD
TBD
Call TI
Call TI
Call TI
Call TI
ACTIVE
ACTIVE
PDIP
20
20
20
70
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
TSSOP
PW
Green (RoHS
& no Sb/Br)
MSP430G2553IPW20R
MSP430G2553IPW28
MSP430G2553IPW28R
MSP430G2553IRHB32R
MSP430G2553IRHB32T
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
QFN
PW
PW
20
28
28
32
32
2000
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
PW
2000
3000
250
Green (RoHS
& no Sb/Br)
RHB
RHB
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
28-May-2011
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
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TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 5
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