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MSP430G2332QPW2REP [TI]

增强型混合信号微控制器 | PW | 20 | -40 to 125;
MSP430G2332QPW2REP
型号： MSP430G2332QPW2REP
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

增强型混合信号微控制器 | PW | 20 | -40 to 125

控制器 微控制器 光电二极管 外围集成电路 装置
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MSP430G2332-EP  
www.ti.com.cn  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
混合信号微控制器  
1
特性  
23  
•
低电源电压范围: 1.8 V 至 3.6 V  
超低功耗  
•
串行板上编程，  
无需外部编程电压，  
•
利用安全熔丝实现可编程代码保护  
具有两线制JTA（SBW）接口的片载仿真逻辑电路  
系列成员汇总于Table 1  
–
运行模式： 220 μA （在 1 MHz 频率和 2.2 V  
电压条件下）  
•
•
•
–
–
待机模式： 0.5 μA  
封装选项  
关闭模式 （RAM 保持）： 0.1 μA  
–
薄型小外形尺寸封装 (TSSOP)：20 引脚  
•
•
•
•
5 种节能模式  
•
完整的模块说明，请见 《MSP430x2xx 系列产品  
用户指南》 （文献编号SLAU144）  
可在不到 1μs 的时间里超快速地从待机模式唤醒  
16 位 RISC 架构、62.5ns 指令周期时间  
基本时钟模块配置  
支持国防、航天和医疗应用  
–
–
–
–
带有四个已校准频率的高达 16MHz 的内部频率  
内部超低功耗低频 (LF) 振荡器  
•
•
•
•
受控基线  
一个组装和测试场所  
一个制造场所  
(1)  
32kHz 晶振  
外部数字时钟源  
Available in Extended (–40°C to 125°C)  
Temperature Range  
•
•
•
一个具有 3 个捕获/比较寄存器的 16 位 Timer_A  
多达 16 个触感使能输入输出 (I/O) 引脚  
(2)  
•
•
•
产品生命周期有所延长  
拓展的产品变更通知  
产品可追溯性  
支持 SPI 和 I2C 的通用串行接口 (USI)（请  
见Table 1）  
•
•
带内部基准、采样与保持以及自动扫描功能的 10  
位 200ksps 模数 (A/D) 转换器（请见 Table 1）  
欠压检测器  
(1) 晶体振荡器不能在超过 105°C 的环境中运行  
(2) 可定制工作温度范围  
说明  
德州仪器公司 MSP430™ 系列超低功耗微控制器包含多种器件，这些器件特有面向多种应用的不同外设集。 为了  
延长便携式应用中所用电池的寿命，对这个含 5 种低功耗模式的架构进行了优化。 该器件具有一个强大的 16 位  
RISC CPU，16 位寄存器和有助于获得最大编码效率的常数发生器。 The digitally controlled oscillator (DCO)  
allows wake-up from low-power modes to active mode in less than 1 µs.  
MSP430G2332 系列微控制器是超低功耗混合信号微控制器，此微控制器带有内置的  
16 位定时器，和高达 16 个 I/O 触感使能引脚以及使用通用串行通信接口的内置通信功能。 MSP430G2332 系列  
带有一个 10 位模数 (A/D) 转换器。 配置详细信息，请见Table 1。 典型应用包括低成本传感器系统，此类系统负  
责捕获模拟信号、将之转换为数字值、随后对数据进行处理以进行显示或传送至主机系统。  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
MSP430 is a trademark of Texas Instruments.  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2012, Texas Instruments Incorporated  
English Data Sheet: SLAS885  
MSP430G2332-EP  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
www.ti.com.cn  
Table 1. Available Options  
Flash  
(kB)  
RAM  
(B)  
ADC10  
Channel  
Device  
EEM  
Timer_A  
USI  
CLOCK  
I/O  
Package Type  
MSP430G2332QPW2EP  
1
4
256  
1x TA3  
8
1
LF, DCO, VLO  
16  
20-TSSOP  
Table 2. ORDERING INFORMATION(1)  
TA  
PACKAGE  
TSSOP - PW  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
VID NUMBER  
MSP430G2332QPW2REP  
MSP430G2332QPW2EP  
Tape and Reel, 2000  
Tube, 70  
V62/12625-01XE  
–40°C to 125°C  
G2332EP  
V62/12625-01XE-T  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
Web site at www.ti.com.  
2
Copyright © 2012, Texas Instruments Incorporated  
MSP430G2332-EP  
www.ti.com.cn  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more  
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.  
DEVICE PINOUTS  
PW PACKAGE  
(TOP VIEW)  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
DVCC  
DVSS  
P1.0/TA0CLK/ACLK/A0  
XIN/P2.6/TA0.1  
3
P1.1/TA0.0/A1  
XOUT/P2.7  
4
P1.2/TA0.1/A2  
TEST/SBWTCK  
5
P1.3/ADC10CLK/VREF-/VEREF-/A3  
RST/NMI/SBWTDIO  
6
P1.4/TA0.2/SMCLK/A4/VREF+/VEREF+/TCK  
P1.7/SDI/SDA/A7/TDO/TDI  
7
P1.6/TA0.1/SDO/SCL/A6/TDI/TCLK  
P1.5/TA0.0/SCLK/A5/TMS  
8
P2.0  
P2.1  
P2.2  
P2.5  
P2.4  
P2.3  
9
10  
Copyright © 2012, Texas Instruments Incorporated  
3
MSP430G2332-EP  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
www.ti.com.cn  
FUNCTIONAL BLOCK DIAGRAMS  
Functional Block Diagram  
XIN XOUT  
DVCC  
DVSS  
P1.x  
8
P2.x  
up to 8  
ACLK  
Port P2  
Port P1  
Flash  
RAM  
ADC  
Clock  
System  
SMCLK  
up to 8 I/O  
Interrupt  
8 I/O  
Interrupt  
8KB  
4KB  
2KB  
1KB  
256B  
256B  
256B  
128B  
10-Bit  
8 Ch.  
capability  
pullup/down  
resistors  
capability  
pullup/down  
resistors  
Autoscan  
1 ch DMA  
MCLK  
16MHz  
CPU  
MAB  
incl. 16  
Registers  
MDB  
Emulation  
2BP  
USI  
Watchdog Timer0_A3  
WDT+  
3 CC  
Brownout  
Protection  
Universal  
Serial  
JTAG  
Interface  
15-Bit  
Registers  
Interface  
SPI, I2C  
Spy-Bi  
Wire  
RST/NMI  
NOTE: Port P2: Two pins are available on the 14-pin package option. Eight pins are available on the 20-pin package option.  
4
Copyright © 2012, Texas Instruments Incorporated  
MSP430G2332-EP  
www.ti.com.cn  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
TERMINAL FUNCTIONS  
Table 3. Terminal Functions  
TERMINAL  
NAME  
NO.  
I/O  
DESCRIPTION  
PW20  
P1.0/  
General-purpose digital I/O pin  
Timer0_A, clock signal TACLK input  
ACLK signal output  
TA0CLK/  
ACLK/  
A0  
2
I/O  
ADC10 analog input A0  
P1.1/  
General-purpose digital I/O pin  
TA0.0/  
A1  
3
4
I/O  
I/O  
Timer0_A, capture: CCI0A input, compare: Out0 output  
ADC10 analog input A1  
P1.2/  
General-purpose digital I/O pin  
TA0.1/  
A2  
Timer0_A, capture: CCI1A input, compare: Out1 output  
ADC10 analog input A2  
P1.3/  
General-purpose digital I/O pin  
ADC10CLK/  
A3/  
ADC10, conversion clock output  
5
6
I/O  
I/O  
ADC10 analog input A3  
VREF-/VEREF  
P1.4/  
ADC10 negative reference voltage  
General-purpose digital I/O pin  
TA0.2/  
SMCLK/  
A4/  
Timer0_A, capture: CCI2A input, compare: Out2 output  
SMCLK signal output  
ADC10 analog input A4  
VREF+/VEREF+/  
TCK  
ADC10 positive reference voltage  
JTAG test clock, input terminal for device programming and test  
General-purpose digital I/O pin  
P1.5/  
TA0.0/  
A5/  
Timer0_A, compare: Out0 output  
7
I/O  
I/O  
I/O  
ADC10 analog input A5  
SCLK/  
TMS  
USI: clk input in I2C mode; clk in/output in SPI mode  
JTAG test mode select, input terminal for device programming and test  
General-purpose digital I/O pin  
P1.6/  
TA0.1/  
A6/  
Timer0_A, compare: Out1 output  
ADC10 analog input A6  
SDO/  
SCL/  
14  
15  
USI: Data output in SPI mode  
USI: I2C clock in I2C mode  
TDI/  
JTAG test data input or test clock input during programming and test  
TCLK  
P1.7/  
General-purpose digital I/O pin  
ADC10 analog input A7  
A7/  
SDI/  
USI: Data input in SPI mode  
SDA/  
USI: I2C data in I2C mode  
TDO/TDI(1)  
JTAG test data output terminal or test data input during programming and test  
General-purpose digital I/O pin  
General-purpose digital I/O pin  
General-purpose digital I/O pin  
General-purpose digital I/O pin  
General-purpose digital I/O pin  
General-purpose digital I/O pin  
P2.0  
8
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
P2.1  
9
P2.2  
10  
11  
12  
13  
P2.3  
P2.4  
P2.5  
(1) TDO or TDI is selected via JTAG instruction.  
Copyright © 2012, Texas Instruments Incorporated  
5
MSP430G2332-EP  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
www.ti.com.cn  
Table 3. Terminal Functions (continued)  
TERMINAL  
NAME  
NO.  
I/O  
DESCRIPTION  
PW20  
XIN/  
Input terminal of crystal oscillator  
General-purpose digital I/O pin  
Timer0_A, compare: Out1 output  
Output terminal of crystal oscillator(2)  
General-purpose digital I/O pin  
Reset  
P2.6/  
TA0.1  
XOUT/  
P2.7  
19  
18  
16  
17  
I/O  
I/O  
RST/  
NMI/  
I
I
Nonmaskable interrupt input  
SBWTDIO/  
TEST/  
Spy-Bi-Wire test data input/output during programming and test  
Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.  
SBWTCK  
DVCC  
Spy-Bi-Wire test clock input during programming and test  
1
NA  
20  
NA  
-
NA  
NA  
NA  
NA  
NA  
NA  
Supply voltage  
AVCC  
Supply voltage  
DVSS  
Ground reference  
AVSS  
Ground reference  
NC  
Not connected  
QFN Pad  
-
QFN package pad connection to VSS recommended.  
(2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to  
this pad after reset.  
6
Copyright © 2012, Texas Instruments Incorporated  
MSP430G2332-EP  
www.ti.com.cn  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
SHORT-FORM DESCRIPTION  
CPU  
The MSP430™ CPU has a 16-bit RISC architecture  
that is highly transparent to the application. All  
operations, other than program-flow instructions, are  
performed as register operations in conjunction with  
seven addressing modes for source operand and four  
addressing modes for destination operand.  
Program Counter  
Stack Pointer  
PC/R0  
SP/R1  
SR/CG1/R2  
CG2/R3  
R4  
Status Register  
The CPU is integrated with 16 registers that provide  
reduced instruction execution time. The register-to-  
register operation execution time is one cycle of the  
CPU clock.  
Constant Generator  
General-Purpose Register  
General-Purpose Register  
General-Purpose Register  
General-Purpose Register  
General-Purpose Register  
General-Purpose Register  
General-Purpose Register  
General-Purpose Register  
General-Purpose Register  
General-Purpose Register  
General-Purpose Register  
General-Purpose Register  
R5  
Four of the registers, R0 to R3, are dedicated as  
program counter, stack pointer, status register, and  
constant generator, respectively. The remaining  
registers are general-purpose registers.  
R6  
R7  
Peripherals are connected to the CPU using data,  
address, and control buses, and can be handled with  
all instructions.  
R8  
R9  
The instruction set consists of the original 51  
instructions with three formats and seven address  
modes and additional instructions for the expanded  
address range. Each instruction can operate on word  
and byte data.  
R10  
R11  
R12  
R13  
Instruction Set  
The instruction set consists of 51 instructions with  
three formats and seven address modes. Each  
instruction can operate on word and byte data.  
Table 4 shows examples of the three types of  
instruction formats; Table 5 shows the address  
modes.  
R14  
R15  
Table 4. Instruction Word Formats  
FORMAT  
EXAMPLE  
ADD R4,R5  
CALL R8  
JNE  
OPERATION  
Dual operands, source-destination  
Single operands, destination only  
Relative jump, un/conditional  
R4 + R5 → R5  
PC → (TOS), R8 → PC  
Jump-on-equal bit = 0  
Table 5. Address Mode Descriptions(1)  
ADDRESS MODE  
Register  
S
D
✓
✓
✓
✓
SYNTAX  
MOV Rs,Rd  
EXAMPLE  
MOV R10,R11  
MOV 2(R5),6(R6)  
OPERATION  
R10 → R11  
✓
✓
✓
✓
✓
Indexed  
MOV X(Rn),Y(Rm)  
MOV EDE,TONI  
MOV &MEM,&TCDAT  
MOV @Rn,Y(Rm)  
M(2+R5) → M(6+R6)  
M(EDE) → M(TONI)  
M(MEM) → M(TCDAT)  
M(R10) → M(Tab+R6)  
Symbolic (PC relative)  
Absolute  
Indirect  
MOV @R10,Tab(R6)  
MOV @R10+,R11  
MOV #45,TONI  
M(R10) → R11  
R10 + 2 → R10  
Indirect autoincrement  
Immediate  
✓
✓
MOV @Rn+,Rm  
MOV #X,TONI  
#45 → M(TONI)  
(1) S = source, D = destination  
Copyright © 2012, Texas Instruments Incorporated  
7
 
 
MSP430G2332-EP  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
www.ti.com.cn  
Operating Modes  
The MSP430 devices have one active mode and five software selectable low-power modes of operation. An  
interrupt event can wake up the device from any of the low-power modes, service the request, and restore back  
to the low-power mode on return from the interrupt program.  
The following six operating modes can be configured by software:  
•
Active mode (AM)  
All clocks are active  
Low-power mode 0 (LPM0)  
–
•
–
–
CPU is disabled  
ACLK and SMCLK remain active, MCLK is disabled  
•
•
Low-power mode 1 (LPM1)  
–
–
–
CPU is disabled  
ACLK and SMCLK remain active, MCLK is disabled  
DCO's dc generator is disabled if DCO not used in active mode  
Low-power mode 2 (LPM2)  
–
–
–
–
CPU is disabled  
MCLK and SMCLK are disabled  
DCO's dc generator remains enabled  
ACLK remains active  
•
•
Low-power mode 3 (LPM3)  
–
–
–
–
CPU is disabled  
MCLK and SMCLK are disabled  
DCO's dc generator is disabled  
ACLK remains active  
Low-power mode 4 (LPM4)  
–
–
–
–
–
CPU is disabled  
ACLK is disabled  
MCLK and SMCLK are disabled  
DCO's dc generator is disabled  
Crystal oscillator is stopped  
8
Copyright © 2012, Texas Instruments Incorporated  
MSP430G2332-EP  
www.ti.com.cn  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
Interrupt Vector Addresses  
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h.  
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.  
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed) the  
CPU goes into LPM4 immediately after power-up.  
Table 6. Interrupt Sources, Flags, and Vectors  
SYSTEM  
INTERRUPT  
WORD  
ADDRESS  
INTERRUPT SOURCE  
INTERRUPT FLAG  
PRIORITY  
Power-Up  
External Reset  
Watchdog Timer+  
Flash key violation  
PC out-of-range(1)  
PORIFG  
RSTIFG  
WDTIFG  
KEYV(2)  
Reset  
0FFFEh  
31, highest  
NMI  
Oscillator fault  
Flash memory access violation  
NMIIFG  
OFIFG  
(non)-maskable  
(non)-maskable  
(non)-maskable  
0FFFCh  
30  
ACCVIFG(2)(3)  
0FFFAh  
0FFF8h  
0FFF6h  
0FFF4h  
0FFF2h  
29  
28  
27  
26  
25  
Watchdog Timer+  
Timer0_A3  
WDTIFG  
TACCR0 CCIFG(4)  
maskable  
maskable  
Timer0_A3  
TACCR2 TACCR1 CCIFG.  
TAIFGTable 4(4)  
maskable  
0FFF0h  
24  
0FFEEh  
0FFECh  
0FFEAh  
0FFE8h  
0FFE6h  
0FFE4h  
0FFE2h  
0FFE0h  
23  
22  
21  
20  
19  
18  
17  
16  
ADC10  
ADC10IFG(4)  
maskable  
maskable  
maskable  
maskable  
USI  
USIIFG, USISTTIFG(2)(4)  
P2IFG.0 to P2IFG.7(2)(4)  
P1IFG.0 to P1IFG.7(2)(4)  
I/O Port P2 (up to eight flags)  
I/O Port P1 (up to eight flags)  
(5)  
See  
0FFDEh to  
0FFC0h  
15 to 0, lowest  
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from  
within unused address ranges.  
(2) Multiple source flags  
(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.  
(4) Interrupt flags are located in the module.  
(5) The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if  
necessary.  
Copyright © 2012, Texas Instruments Incorporated  
9
MSP430G2332-EP  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
www.ti.com.cn  
Special Function Registers (SFRs)  
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits  
not allocated to a functional purpose are not physically present in the device. Simple software access is provided  
with this arrangement.  
Legend  
rw:  
Bit can be read and written.  
rw-0,1:  
rw-(0,1):  
Bit can be read and written. It is reset or set by PUC.  
Bit can be read and written. It is reset or set by POR.  
SFR bit is not present in device.  
Table 7. Interrupt Enable Register 1 and 2  
Address  
00h  
7
6
5
4
3
2
1
0
ACCVIE  
rw-0  
NMIIE  
rw-0  
OFIE  
rw-0  
WDTIE  
rw-0  
WDTIE  
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in  
interval timer mode.  
OFIE  
Oscillator fault interrupt enable  
(Non)maskable interrupt enable  
Flash access violation interrupt enable  
NMIIE  
ACCVIE  
Address  
7
6
5
4
3
2
1
0
01h  
Table 8. Interrupt Flag Register 1 and 2  
Address  
02h  
7
6
5
4
3
2
1
0
NMIIFG  
rw-0  
RSTIFG  
rw-(0)  
PORIFG  
rw-(1)  
OFIFG  
rw-1  
WDTIFG  
rw-(0)  
WDTIFG  
Set on watchdog timer overflow (in watchdog mode) or security key violation.  
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.  
OFIFG  
Flag set on oscillator fault.  
PORIFG  
RSTIFG  
NMIIFG  
Power-On Reset interrupt flag. Set on VCC power-up.  
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up.  
Set via RST/NMI pin  
Address  
03h  
7
6
5
4
3
2
1
0
10  
Copyright © 2012, Texas Instruments Incorporated  
MSP430G2332-EP  
www.ti.com.cn  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
Memory Organization  
Table 9. Memory Organization  
MSP430G2332  
4kB  
Memory  
Size  
Flash  
Flash  
Size  
Main: interrupt vector  
Main: code memory  
Information memory  
0xFFFF to 0xFFC0  
0xFFFF to 0xF000  
256 Byte  
Flash  
Size  
010FFh to 01000h  
256 B  
RAM  
0x02FF to 0x0200  
01FFh to 0100h  
0FFh to 010h  
0Fh to 00h  
Peripherals  
16-bit  
8-bit  
8-bit SFR  
Flash Memory  
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can  
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:  
•
Flash memory has n segments of main memory and four segments of information memory (A to D) of  
64 bytes each. Each segment in main memory is 512 bytes in size.  
•
•
Segments 0 to n may be erased in one step, or each segment may be individually erased.  
Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also  
called information memory.  
•
Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It  
can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is  
required.  
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Peripherals  
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all  
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).  
Oscillator and System Clock  
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal  
oscillator, an internal very-low-power low-frequency oscillator, and an internal digitally controlled oscillator (DCO).  
The basic clock module is designed to meet the requirements of both low system cost and low power  
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic  
clock module provides the following clock signals:  
•
•
•
Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.  
Main clock (MCLK), the system clock used by the CPU.  
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.  
The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.  
Calibration Data Stored in Information Memory Segment A  
Calibration data is stored for both the DCO and for ADC10 organized in a tag-length-value structure.  
Table 10. Tags Used by the ADC Calibration Tags  
NAME  
ADDRESS  
0x10F6  
0x10DA  
-
VALUE  
0x01  
DESCRIPTION  
DCO frequency calibration at VCC = 3 V and TA = 30°C at calibration  
ADC10_1 calibration tag  
TAG_DCO_30  
TAG_ADC10_1  
TAG_EMPTY  
0x10  
0xFE  
Identifier for empty memory areas  
Table 11. Labels Used by the ADC Calibration Tags  
LABEL  
CONDITION AT CALIBRATION / DESCRIPTION  
SIZE  
word  
word  
word  
word  
word  
word  
word  
word  
byte  
byte  
byte  
byte  
byte  
byte  
byte  
byte  
ADDRESS OFFSET  
0x0010  
CAL_ADC_25T85  
CAL_ADC_25T30  
INCHx = 0x1010, REF2_5 = 1, TA = 85°C  
INCHx = 0x1010, REF2_5 = 1, TA = 30°C  
0x000E  
0x000C  
0x000A  
0x0008  
CAL_ADC_25VREF_FACTOR  
CAL_ADC_15T85  
REF2_5 = 1, TA = 30°C, I(VREF+) = 1 mA  
INCHx = 0x1010, REF2_5 = 0, TA = 85°C  
CAL_ADC_15T30  
INCHx = 0x1010, REF2_5 = 0, TA = 30°C  
CAL_ADC_15VREF_FACTOR  
CAL_ADC_OFFSET  
CAL_ADC_GAIN_FACTOR  
CAL_BC1_1MHz  
REF2_5 = 0, TA = 30°C, I(VREF+) = 0.5 mA  
0x0006  
External VREF = 1.5 V, f(ADC10CLK) = 5 MHz  
0x0004  
External VREF = 1.5 V, f(ADC10CLK) = 5 MHz  
0x0002  
-
-
-
-
-
-
-
-
0x0009  
CAL_DCO_1MHz  
0x00008  
0x0007  
CAL_BC1_8MHz  
CAL_DCO_8MHz  
0x0006  
CAL_BC1_12MHz  
0x0005  
CAL_DCO_12MHz  
CAL_BC1_16MHz  
0x0004  
0x0003  
CAL_DCO_16MHz  
0x0002  
12  
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Main DCO Characteristics  
•
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14  
overlaps RSELx = 15.  
•
•
DCO control bits DCOx have a step size as defined by parameter SDCO.  
Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK  
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:  
32 × f  
× f  
DCO(RSEL,DCO+1)  
DCO(RSEL,DCO)  
f
=
average  
MOD × f  
+ (32 – MOD) × f  
DCO(RSEL,DCO+1)  
DCO(RSEL,DCO)  
Brownout  
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and  
power off.  
Digital I/O  
There are two 8-bit I/O ports implemented:  
•
•
•
•
•
•
All individual I/O bits are independently programmable.  
Any combination of input, output, and interrupt condition(port P1 and port P2 only) is possible.  
Edge-selectable interrupt input capability for all the eight bits of port P1 and port P2, if available.  
Read/write access to port-control registers is supported by all instructions.  
Each I/O has an individually programmable pullup/pulldown resistor.  
Each I/O has an individually programmable pin-oscillator enable bit to enable low-cost touch sensing.  
WDT+ Watchdog Timer  
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a  
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog  
function is not needed in an application, the module can be disabled or configured as an interval timer and can  
generate interrupts at selected time intervals.  
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Timer0_A3  
Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer0_A3 can support multiple  
capture/compares, PWM outputs, and interval timing. Timer0_A3 also has extensive interrupt capabilities.  
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare  
registers.  
Table 12. Timer0_A3 Signal Connections(1)  
OUTPUT PIN  
NUMBER  
INPUT PIN NUMBER  
DEVICE INPUT  
SIGNAL  
MODULE INPUT  
NAME  
MODULE OUTPUT  
SIGNAL  
MODULE BLOCK  
PW20  
PW20  
P1.0-2  
TACLK  
ACLK  
TACLK  
ACLK  
SMCLK  
INCLK  
CCI0A  
CCI0B  
GND  
Timer  
NA  
SMCLK  
PinOsc  
P1.1-3  
TA0.0  
ACLK  
VSS  
P1.1-3  
P1.5-7  
CCR0  
CCR1  
CCR2  
TA0  
TA1  
TA2  
VCC  
VCC  
P1.2-4  
TA0.1  
CAOUT  
VSS  
CCI1A  
CCI1B  
GND  
P1.2-4  
P1.6-14  
P2.6-19  
VCC  
VCC  
P1.4-6  
PinOsc  
TA0.2  
TA0.2  
VSS  
CCI2A  
CCI2B  
GND  
P1.4-6  
VCC  
VCC  
(1) Only one pin-oscillator must be enabled at a time.  
USI  
The universal serial interface (USI) module is used for serial data communication and provides the basic  
hardware for synchronous communication protocols like SPI and I2C.  
ADC10  
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR  
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion  
result handling, allowing ADC samples to be converted and stored without any CPU intervention.  
14  
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Peripheral File Map  
Table 13. Peripherals With Word Access  
REGISTER  
NAME  
MODULE  
ADC10  
REGISTER DESCRIPTION  
OFFSET  
01BCh  
ADC data transfer start address  
ADC10SA  
ADC memory  
ADC10MEM  
ADC10CTL1  
ADC10CTL0  
TACCR2  
TACCR1  
TACCR0  
TAR  
01B4h  
01B2h  
01B0h  
0176h  
0174h  
0172h  
0170h  
0166h  
0164h  
0162h  
0160h  
012Eh  
012Ch  
012Ah  
0128h  
0120h  
ADC control register 1  
ADC control register 0  
Capture/compare register  
Capture/compare register  
Capture/compare register  
Timer_A register  
Timer0_A3  
Capture/compare control  
Capture/compare control  
Capture/compare control  
Timer_A control  
TACCTL2  
TACCTL1  
TACCTL0  
TACTL  
Timer_A interrupt vector  
Flash control 3  
TAIV  
Flash Memory  
FCTL3  
Flash control 2  
FCTL2  
Flash control 1  
FCTL1  
Watchdog Timer+  
Watchdog/timer control  
WDTCTL  
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OFFSET  
Table 14. Peripherals With Byte Access  
REGISTER  
NAME  
MODULE  
REGISTER DESCRIPTION  
ADC10  
USI  
Analog enable 0  
ADC10AE0  
04Ah  
ADC data transfer control register 1  
ADC data transfer control register 0  
USI control 0  
ADC10DTC1  
ADC10DTC0  
USICTL0  
USICTL1  
USICKCTL  
USICNT  
USISR  
BCSCTL3  
BCSCTL2  
BCSCTL1  
DCOCTL  
P2SEL2  
P2REN  
P2SEL  
P2IE  
049h  
048h  
078h  
079h  
07Ah  
07Bh  
07Ch  
053h  
058h  
057h  
056h  
042h  
02Fh  
02Eh  
02Dh  
02Ch  
02Bh  
02Ah  
029h  
028h  
041h  
027h  
026h  
025h  
024h  
023h  
022h  
021h  
020h  
003h  
002h  
001h  
000h  
USI control 1  
USI clock control  
USI bit counter  
USI shift register  
Basic Clock System+  
Basic clock system control 3  
Basic clock system control 2  
Basic clock system control 1  
DCO clock frequency control  
Port P2 selection 2  
Port P2  
Port P2 resistor enable  
Port P2 selection  
Port P2 interrupt enable  
Port P2 interrupt edge select  
Port P2 interrupt flag  
Port P2 direction  
P2IES  
P2IFG  
P2DIR  
Port P2 output  
P2OUT  
P2IN  
Port P2 input  
Port P1  
Port P1 selection 2  
P1SEL2  
P1REN  
P1SEL  
P1IE  
Port P1 resistor enable  
Port P1 selection  
Port P1 interrupt enable  
Port P1 interrupt edge select  
Port P1 interrupt flag  
Port P1 direction  
P1IES  
P1IFG  
P1DIR  
Port P1 output  
P1OUT  
P1IN  
Port P1 input  
Special Function  
SFR interrupt flag 2  
SFR interrupt flag 1  
SFR interrupt enable 2  
SFR interrupt enable 1  
IFG2  
IFG1  
IE2  
IE1  
16  
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Absolute Maximum Ratings(1)  
Voltage applied at VCC to VSS  
Voltage applied to any pin(2)  
–0.3 V to 4.1 V  
–0.3 V to VCC + 0.3 V  
±2 mA  
Diode current at any device pin  
Unprogrammed device  
Programmed device  
–55°C to 150°C  
–55°C to 150°C  
(3)  
Storage temperature range, Tstg  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is  
applied to the TEST pin when blowing the JTAG fuse.  
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow  
temperatures not higher than classified on the device label on the shipping boxes or reels.  
xxx  
A. See data sheet for absolute maximum and minimum recommended operating conditions.  
B. Silicon operating life design goal is 10 years at 110°C junction temperature (does not include package interconnect  
life).  
C. The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the  
dominant failure mechanism affecting device wearout for the specific device process and design characteristics.  
Figure 1. Operating Life Derating Chart  
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UNITS  
THERMAL INFORMATION  
MSP430G2332-EP  
THERMAL METRIC(1)  
PW  
20 PINS  
98.7  
θJA  
Junction-to-ambient thermal resistance(2)  
θJCtop  
θJB  
Junction-to-case (top) thermal resistance(3)  
Junction-to-board thermal resistance(4)  
Junction-to-top characterization parameter(5)  
Junction-to-board characterization parameter(6)  
Junction-to-case (bottom) thermal resistance(7)  
26.8  
41.2  
°C/W  
ψJT  
1.1  
ψJB  
40.5  
θJCbot  
N/A  
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.  
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as  
specified in JESD51-7, in an environment described in JESD51-2a.  
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-  
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.  
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB  
temperature, as described in JESD51-8.  
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted  
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).  
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted  
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).  
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific  
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.  
Spacer  
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Recommended Operating Conditions  
MIN NOM  
MAX UNIT  
During program execution  
1.8  
2.2  
0
3.6  
V
VCC  
Supply voltage  
During flash programming/erase  
3.6  
VSS  
TA  
Supply voltage  
V
Operating free-air temperature  
-40  
125  
6
°C  
VCC = 1.8 V,  
Duty cycle = 50% ± 10%  
dc  
dc  
dc  
Processor frequency (maximum MCLK frequency  
using the USART module)(1)(2)  
VCC = 2.7 V,  
Duty cycle = 50% ± 10%  
fSYSTEM  
12 MHz  
16  
VCC = 3.3 V,  
Duty cycle = 50% ± 10%  
(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the  
specified maximum frequency.  
(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.  
Legend:  
16 MHz  
Supply voltage range,  
during flash memory  
programming  
12 MHz  
Supply voltage range,  
during program execution  
6 MHz  
3.3 V 3.6 V  
2.7 V  
Supply Voltage - V  
1.8 V  
2.2 V  
Note: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC  
of 2.2 V.  
Figure 2. Safe Operating Area  
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Electrical Characteristics  
Active Mode Supply Current Into VCC Excluding External Current  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
TYP  
MAX UNIT  
fDCO = fMCLK = fSMCLK = 1 MHz,  
fACLK = 32768 Hz,  
2.2 V  
220  
Program executes in flash,  
BCSCTL1 = CALBC1_1MHZ,  
DCOCTL = CALDCO_1MHZ,  
CPUOFF = 0, SCG0 = 0, SCG1 = 0,  
OSCOFF = 0  
Active mode (AM)  
current (1 MHz)  
IAM,1MHz  
µA  
3 V  
320  
400  
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.  
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external  
load capacitance is chosen to closely match the required 9 pF.  
Typical Characteristics – Active Mode Supply Current (Into VCC)  
5.0  
4.0  
3.0  
2.0  
1.0  
0.0  
4.0  
3.0  
2.0  
1.0  
0.0  
f
= 16 MHz  
DCO  
T
= 85 °C  
= 25 °C  
A
T
A
V
= 3 V  
CC  
f
= 12 MHz  
DCO  
T
= 85 °C  
= 25 °C  
A
T
A
f
= 8 MHz  
DCO  
2.0  
f
= 1 MHz  
V
CC  
= 2.2 V  
DCO  
1.5  
2.5  
3.0  
3.5  
4.0  
0.0  
4.0  
8.0  
12.0  
16.0  
V
CC  
− Supply Voltage − V  
f
DCO  
− DCO Frequency − MHz  
Figure 3. Active Mode Current vs VCC, TA = 25°C  
Figure 4. Active Mode Current vs DCO Frequency  
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Low-Power Mode Supply Currents (Into VCC) Excluding External Current  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)  
PARAMETER  
TEST CONDITIONS  
TA  
VCC  
MIN  
TYP  
MAX UNIT  
fMCLK = 0 MHz,  
fSMCLK = fDCO = 1 MHz,  
fACLK = 32768 Hz,  
BCSCTL1 = CALBC1_1MHZ,  
DCOCTL = CALDCO_1MHZ,  
CPUOFF = 1, SCG0 = 0, SCG1 = 0,  
OSCOFF = 0  
Low-power mode 0  
(LPM0) current(2)  
ILPM0,1MHz  
25°C  
2.2 V  
55  
µA  
fMCLK = fSMCLK = 0 MHz,  
fDCO = 1 MHz,  
fACLK = 32768 Hz,  
Low-power mode 2  
(LPM2) current(3)  
ILPM2  
BCSCTL1 = CALBC1_1MHZ,  
DCOCTL = CALDCO_1MHZ,  
CPUOFF = 1, SCG0 = 0, SCG1 = 1,  
OSCOFF = 0  
25°C  
2.2 V  
22  
µA  
fDCO = fMCLK = fSMCLK = 0 MHz,  
fACLK = 32768 Hz,  
CPUOFF = 1, SCG0 = 1, SCG1 = 1,  
OSCOFF = 0  
25°C  
125°C  
25°C  
0.7  
1.5  
Low-power mode 3  
(LPM3) current(3)  
ILPM3,LFXT1  
ILPM3,VLO  
ILPM4  
2.2 V  
2.2 V  
2.2 V  
µA  
24  
fDCO = fMCLK = fSMCLK = 0 MHz,  
fACLK from internal LF oscillator (VLO),  
CPUOFF = 1, SCG0 = 1, SCG1 = 1,  
OSCOFF = 0  
0.5  
3
0.7  
Low-power mode 3  
current, (LPM3)(3)  
µA  
125°C  
9.3  
fDCO = fMCLK = fSMCLK = 0 MHz,  
fACLK = 0 Hz,  
CPUOFF = 1, SCG0 = 1, SCG1 = 1,  
OSCOFF = 1  
25°C  
85°C  
0.1  
0.8  
3
0.5  
1.5  
8
µA  
µA  
Low-power mode 4  
(LPM4) current(4)  
125°C  
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.  
(2) Current for brownout and WDT clocked by SMCLK included.  
(3) Current for brownout and WDT clocked by ACLK included.  
(4) Current for brownout included.  
Typical Characteristics Low-Power Mode Supply Currents  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
2.0  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0.0  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
VCC = 3.6 V  
VCC = 3.6 V  
VCC = 3 V  
VCC = 3 V  
VCC = 2.2 V  
VCC = 2.2 V  
VCC = 1.8 V  
VCC = 1.8 V  
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0  
− Temperature −  
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0  
T
C
A
T
A
− Temperature − °C  
Figure 5. LPM3 Current vs Temperature  
Figure 6. LPM4 Current vs Temperature  
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MAX UNIT  
Schmitt-Trigger Inputs – Ports Px  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
0.45 VCC  
1.35  
TYP  
0.75 VCC  
VIT+  
Positive-going input threshold voltage  
V
V
3 V  
2.25  
0.55 VCC  
1.65  
0.25 VCC  
0.75  
VIT–  
Negative-going input threshold voltage  
3 V  
3 V  
Vhys  
RPull  
CI  
Input voltage hysteresis (VIT+ – VIT–  
Pullup/pulldown resistor  
Input capacitance  
)
0.3  
1
V
For pullup: VIN = VSS  
For pulldown: VIN = VCC  
3 V  
20  
35  
5
50  
kΩ  
pF  
VIN = VSS or VCC  
Leakage Current – Ports Px  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
TA = -40°C to 85°C  
TA = 125°C(1)(2)  
VCC  
MIN  
MAX UNIT  
±50  
nA  
Ilkg(Px.x)  
High-impedance leakage current(1)(2)  
3 V  
±120  
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.  
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input, and the pullup/pulldown resistor is  
disabled.  
Outputs – Ports Px  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
I(OHmax) = –6 mA(1)  
I(OLmax) = 6 mA(1)  
VCC  
3 V  
3 V  
MIN  
TYP  
VCC – 0.3  
VSS + 0.3  
MAX UNIT  
VOH  
VOL  
High-level output voltage  
Low-level output voltage  
V
V
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop  
specified.  
Output Frequency – Ports Px  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
Px.y, CL = 20 pF, RL = 1 kΩ(1) (2)  
Px.y, CL = 20 pF(2)  
VCC  
3 V  
3 V  
MIN  
TYP  
12  
MAX UNIT  
MHz  
fPx.y  
Port output frequency (with load)  
Clock output frequency  
fPort_CLK  
16  
MHz  
(1) A resistive divider with two 0.5-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the  
divider.  
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.  
22  
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Typical Characteristics – Outputs  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
TYPICAL LOW-LEVEL OUTPUT CURRENT  
vs  
LOW-LEVEL OUTPUT VOLTAGE  
TYPICAL LOW-LEVEL OUTPUT CURRENT  
vs  
LOW-LEVEL OUTPUT VOLTAGE  
50.0  
40.0  
30.0  
20.0  
10.0  
0.0  
30.0  
25.0  
20.0  
15.0  
10.0  
5.0  
V
= 2.2 V  
V
= 3 V  
CC  
CC  
T
= 25°C  
= 85°C  
A
T
= 25°C  
= 85°C  
P1.7  
A
P1.7  
T
A
T
A
0.0  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
V
OL  
− Low-Level Output Voltage − V  
V
OL  
− Low-Level Output Voltage − V  
Figure 7.  
Figure 8.  
TYPICAL HIGH-LEVEL OUTPUT CURRENT  
vs  
HIGH-LEVEL OUTPUT VOLTAGE  
TYPICAL HIGH-LEVEL OUTPUT CURRENT  
vs  
HIGH-LEVEL OUTPUT VOLTAGE  
0.0  
−5.0  
0.0  
−10.0  
−20.0  
−30.0  
−40.0  
−50.0  
V
= 2.2 V  
V
= 3 V  
CC  
CC  
P1.7  
P1.7  
−10.0  
−15.0  
−20.0  
−25.0  
T
A
= 85°C  
T
= 85°C  
A
T
A
= 25°C  
0.5  
T
= 25°C  
0.5  
A
0.0  
1.0  
1.5  
2.0  
2.5  
0.0  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
V
OH  
− High-Level Output Voltage − V  
V
OH  
− High-Level Output Voltage − V  
Figure 9.  
Figure 10.  
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Pin-Oscillator Frequency – Ports Px  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
P1.y, CL = 10 pF, RL = 100 kΩ(1)(2)  
P1.y, CL = 20 pF, RL = 100 kΩ(1)(2)  
VCC  
MIN  
TYP  
1400  
900  
MAX UNIT  
foP1.x  
Port output oscillation frequency  
3 V  
kHz  
P2.0 to P2.5, CL = 10 pF, RL = 100 kΩ(1)(2)  
P2.0 to P2.5, CL = 20 pF, RL = 100 kΩ(1)(2)  
P2.6 and P2.7, CL = 20 pF, RL = 100 kΩ(1)(2)  
1800  
1000  
700  
foP2.x  
Port output oscillation frequency  
Port output oscillation frequency  
3 V  
3 V  
kHz  
kHz  
foP2.6/7  
(1) A resistive divider with two 100-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the  
divider.  
(2) The output voltage oscillates with a typical amplitude of 700 mV at the specified toggle frequency.  
Typical Characteristics – Pin-Oscillator Frequency  
TYPICAL OSCILLATING FREQUENCY  
vs  
LOAD CAPACITANCE  
TYPICAL OSCILLATING FREQUENCY  
vs  
LOAD CAPACITANCE  
1.50  
1.35  
1.20  
1.05  
0.90  
0.75  
0.60  
0.45  
0.30  
0.15  
0.00  
1.50  
1.35  
1.20  
1.05  
0.90  
0.75  
0.60  
0.45  
0.30  
0.15  
0.00  
V
CC  
= 2.2 V  
V
CC  
= 3.0 V  
P1.y  
P1.y  
P2.0 ... P2.5  
P2.6, P2.7  
P2.0 ... P2.5  
P2.6, P2.7  
10  
50  
100  
10  
50  
100  
C
LOAD  
− External Capacitance − pF  
C
LOAD  
− External Capacitance − pF  
Figure 11.  
Figure 12.  
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ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
POR/Brownout Reset (BOR)(1)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
See Figure 13  
TEST CONDITIONS  
dVCC/dt ≤ 3 V/s  
VCC  
MIN  
TYP  
MAX UNIT  
VCC(start)  
V(B_IT–)  
Vhys(B_IT–)  
td(BOR)  
0.7 × V(B_IT–)  
1.40  
V
V
See Figure 13 through Figure 15  
See Figure 13  
dVCC/dt ≤ 3 V/s  
dVCC/dt ≤ 3 V/s  
140  
mV  
See Figure 13  
2000  
µs  
Pulse length needed at RST/NMI pin to  
accepted reset internally(2)  
t(reset)  
2.2 V  
2
µs  
(1) The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT–)  
Vhys(B_IT–) is ≤ 1.8 V.  
+
(2) Minimum and maximum parameters are characterized up to TA = 105°C, unless otherwise noted.  
V
CC  
V
hys(B_IT−)  
V
(B_IT−)  
V
CC(start)  
1
0
t
d(BOR)  
Figure 13. POR/Brownout Reset (BOR) vs Supply Voltage  
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Typical Characteristics – POR/Brownout Reset (BOR)  
V
t
CC  
pw  
2
3 V  
V
= 3 V  
Typical Conditions  
CC  
1.5  
1
V
CC(drop)  
0.5  
0
0.001  
1
1000  
1 ns  
1 ns  
− Pulse Width − µs  
t
− Pulse Width − µs  
t
pw  
pw  
Figure 14. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal  
V
t
CC  
pw  
2
1.5  
1
3 V  
V
= 3 V  
CC  
Typical Conditions  
V
CC(drop)  
0.5  
t = t  
f
r
0
0.001  
1
1000  
t
t
r
f
t
− Pulse Width − µs  
t
− Pulse Width − µs  
pw  
pw  
Figure 15. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal  
26  
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ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
DCO Frequency  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
1.8  
2.2  
3
TYP  
MAX UNIT  
RSELx < 14  
RSELx = 14  
RSELx = 15  
3.6  
3.6  
3.6  
V
V
V
VCC  
Supply voltage  
fDCO(0,0)  
fDCO(0,3)  
fDCO(1,3)  
fDCO(2,3)  
fDCO(3,3)  
fDCO(4,3)  
fDCO(5,3)  
fDCO(6,3)  
fDCO(7,3)  
fDCO(8,3)  
fDCO(9,3)  
fDCO(10,3)  
fDCO(11,3)  
fDCO(12,3)  
fDCO(13,3)  
fDCO(14,3)  
fDCO(15,3)  
fDCO(15,7)  
DCO frequency (0, 0)  
DCO frequency (0, 3)  
DCO frequency (1, 3)  
DCO frequency (2, 3)  
DCO frequency (3, 3)  
DCO frequency (4, 3)  
DCO frequency (5, 3)  
DCO frequency (6, 3)  
DCO frequency (7, 3)  
DCO frequency (8, 3)  
DCO frequency (9, 3)  
DCO frequency (10, 3)  
DCO frequency (11, 3)  
DCO frequency (12, 3)  
DCO frequency (13, 3)  
DCO frequency (14, 3)  
DCO frequency (15, 3)  
DCO frequency (15, 7)  
RSELx = 0, DCOx = 0, MODx = 0  
RSELx = 0, DCOx = 3, MODx = 0  
RSELx = 1, DCOx = 3, MODx = 0  
RSELx = 2, DCOx = 3, MODx = 0  
RSELx = 3, DCOx = 3, MODx = 0  
RSELx = 4, DCOx = 3, MODx = 0  
RSELx = 5, DCOx = 3, MODx = 0  
RSELx = 6, DCOx = 3, MODx = 0  
RSELx = 7, DCOx = 3, MODx = 0  
RSELx = 8, DCOx = 3, MODx = 0  
RSELx = 9, DCOx = 3, MODx = 0  
RSELx = 10, DCOx = 3, MODx = 0  
RSELx = 11, DCOx = 3, MODx = 0  
RSELx = 12, DCOx = 3, MODx = 0  
RSELx = 13, DCOx = 3, MODx = 0  
RSELx = 14, DCOx = 3, MODx = 0  
RSELx = 15, DCOx = 3, MODx = 0  
RSELx = 15, DCOx = 7, MODx = 0  
3 V  
3 V  
3 V  
3 V  
3 V  
3 V  
3 V  
3 V  
3 V  
3 V  
3 V  
3 V  
3 V  
3 V  
3 V  
3 V  
3 V  
3 V  
0.06  
0.07  
0.14 MHz  
0.17 MHz  
MHz  
0.15  
0.21  
0.30  
0.41  
0.58  
MHz  
MHz  
MHz  
MHz  
0.54  
0.80  
1.06 MHz  
1.50 MHz  
MHz  
1.6  
2.3  
MHz  
3.4  
MHz  
4.25  
MHz  
4.30  
6.00  
8.60  
12.0  
16.0  
7.30 MHz  
9.60 MHz  
13.9 MHz  
18.5 MHz  
26.0 MHz  
Frequency step between  
range RSEL and RSEL+1  
SRSEL  
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)  
3 V  
1.35  
ratio  
Frequency step between  
tap DCO and DCO+1  
SDCO  
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)  
Measured at SMCLK output  
3 V  
3 V  
1.08  
50  
ratio  
%
Duty cycle  
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MAX UNIT  
Calibrated DCO Frequencies – Tolerance  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
TA  
VCC  
MIN  
TYP  
BCSCTL1= CALBC1_1MHZ,  
DCOCTL = CALDCO_1MHZ,  
calibrated at 30°C and 3 V  
1-MHz tolerance over  
temperature(1)  
-40°C to 125°C  
3 V  
-3  
±0.5  
+3  
+3  
+6  
+3  
+3  
+6  
+3  
+3  
+6  
+3  
+3  
+6  
%
%
%
%
%
%
%
%
%
%
%
%
BCSCTL1= CALBC1_1MHZ,  
DCOCTL = CALDCO_1MHZ,  
calibrated at 30°C and 3 V  
1-MHz tolerance over VCC  
1-MHz tolerance overall  
30°C  
1.8 V to 3.6 V  
1.8 V to 3.6 V  
3 V  
-3  
-6  
-3  
-3  
-6  
-3  
-3  
-6  
-3  
-3  
-6  
±2  
±3  
BCSCTL1= CALBC1_1MHZ,  
DCOCTL = CALDCO_1MHZ,  
calibrated at 30°C and 3 V  
-40°C to 125°C  
-40°C to 125°C  
30°C  
BCSCTL1= CALBC1_8MHZ,  
DCOCTL = CALDCO_8MHZ,  
calibrated at 30°C and 3 V  
8-MHz tolerance over  
temperature(1)  
±0.5  
±2  
BCSCTL1= CALBC1_8MHZ,  
DCOCTL = CALDCO_8MHZ,  
calibrated at 30°C and 3 V  
8-MHz tolerance over VCC  
8-MHz tolerance overall  
2.2 V to 3.6 V  
2.2 V to 3.6 V  
3 V  
BCSCTL1= CALBC1_8MHZ,  
DCOCTL = CALDCO_8MHZ,  
calibrated at 30°C and 3 V  
-40°C to 125°C  
-40°C to 125°C  
30°C  
±3  
BCSCTL1= CALBC1_12MHZ,  
DCOCTL = CALDCO_12MHZ,  
calibrated at 30°C and 3 V  
12-MHz tolerance over  
temperature(1)  
±0.5  
±2  
BCSCTL1= CALBC1_12MHZ,  
DCOCTL = CALDCO_12MHZ,  
calibrated at 30°C and 3 V  
12-MHz tolerance over VCC  
12-MHz tolerance overall  
2.7 V to 3.6 V  
2.7 V to 3.6 V  
3.3 V  
BCSCTL1= CALBC1_12MHZ,  
DCOCTL = CALDCO_12MHZ,  
calibrated at 30°C and 3 V  
-40°C to 125°C  
-40°C to 125°C  
30°C  
±3  
BCSCTL1= CALBC1_16MHZ,  
DCOCTL = CALDCO_16MHZ,  
calibrated at 30°C and 3 V  
16-MHz tolerance over  
temperature(1)  
±0.5  
±2  
BCSCTL1= CALBC1_16MHZ,  
DCOCTL = CALDCO_16MHZ,  
calibrated at 30°C and 3 V  
16-MHz tolerance over VCC  
16-MHz tolerance overall  
3.3 V to 3.6 V  
3.3 V to 3.6 V  
BCSCTL1= CALBC1_16MHZ,  
DCOCTL = CALDCO_16MHZ,  
calibrated at 30°C and 3 V  
-40°C to 125°C  
±3  
(1) This is the frequency change from the measured frequency at 30°C over temperature.  
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Wake-Up From Lower-Power Modes (LPM3/4)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
TYP  
MAX UNIT  
DCO clock wake-up time from  
LPM3/4(1)  
BCSCTL1 = CALBC1_1MHZ,  
DCOCTL = CALDCO_1MHZ  
tDCO,LPM3/4  
tCPU,LPM3/4  
3 V  
1.5  
µs  
1/fMCLK  
+
CPU wake-up time from LPM3/4(2)  
tClock,LPM3/4  
(1) The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock  
edge observable externally on a clock pin (MCLK or SMCLK).  
(2) Parameter applicable only if DCOCLK is used for MCLK.  
Typical Characteristics – DCO Clock Wake-Up Time From LPM3/4  
10.00  
RSELx = 0...11  
RSELx = 12...15  
1.00  
0.10  
0.10  
1.00  
DCO Frequency − MHz  
Figure 16. DCO Wake-Up Time From LPM3 vs DCO Frequency  
10.00  
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Crystal Oscillator, XT1, Low-Frequency Mode(1) (2)  
over recommended ranges of supply voltage and up to operating free-air temperature, TA = 105°C (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
TYP  
MAX UNIT  
LFXT1 oscillator crystal  
frequency, LF mode 0, 1  
fLFXT1,LF  
XTS = 0, LFXT1Sx = 0 or 1  
1.8 V to 3.6 V  
32768  
Hz  
LFXT1 oscillator logic level  
fLFXT1,LF,logic  
square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3  
LF mode  
1.8 V to 3.6 V 10000  
1.8 V to 3.6 V  
32768 50000  
32768  
Hz  
Hz  
LFXT1 oscillator logic level  
XTS = 0, XCAPx = 0, LFXT1Sx = 3,  
square wave input frequency,  
TA = -40°C to 125°C  
fLFXT1,LF,logic  
LF mode  
XTS = 0, LFXT1Sx = 0,  
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF  
500  
200  
Oscillation allowance for  
LF crystals  
OALF  
kΩ  
XTS = 0, LFXT1Sx = 0,  
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF  
XTS = 0, XCAPx = 0  
XTS = 0, XCAPx = 1  
XTS = 0, XCAPx = 2  
XTS = 0, XCAPx = 3  
1
5.5  
8.5  
11  
Integrated effective load  
capacitance, LF mode(3)  
CL,eff  
pF  
XTS = 0, Measured at P2.0/ACLK,  
fLFXT1,LF = 32768 Hz  
Duty cycle  
fFault,LF  
LF mode  
2.2 V  
2.2 V  
30  
10  
50  
70  
%
Oscillator fault frequency,  
LF mode(4)  
XTS = 0, XCAPx = 0, LFXT1Sx = 3(5)  
10000  
Hz  
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.  
(a) Keep the trace between the device and the crystal as short as possible.  
(b) Design a good ground plane around the oscillator pins.  
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.  
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.  
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.  
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.  
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This  
signal is no longer required for the serial programming adapter.  
(2) Crystal oscillator cannot be operated beyond 105°C. Parameters are characterized up to TA = 105°C, unless otherwise noted.  
(3) Includes parasitic bond and package capacitance (approximately 2 pF per pin).  
Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a  
correct setup, the effective load capacitance should always match the specification of the used crystal.  
(4) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.  
Frequencies in between might set the flag.  
(5) Measured with logic-level input frequency but also applies to operation with crystals.  
Internal Very-Low-Power Low-Frequency Oscillator (VLO)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TA  
VCC  
MIN  
TYP  
MAX UNIT  
-40°C to 85°C  
125°C  
4
12  
20  
fVLO  
VLO frequency  
3 V  
kHz  
23  
dfVLO/dT  
VLO frequency temperature drift(1)  
VLO frequency supply voltage drift(2)  
-40°C to 125°C  
25°C  
3 V  
0.5  
4
%/°C  
%/V  
dfVLO/dVCC  
1.8 V to 3.6 V  
(1) Calculated using the box method: (MAX(-40°C to 125°C) - MIN(-40°C to 125°C)) / MIN(-40°C to 125°C) / (125°C - (-40°C))  
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) - MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V - 1.8 V)  
Timer_A  
over recommended ranges of supply voltage and up to operating free-air temperature, TA = 105°C (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
TYP  
MAX UNIT  
SMCLK  
Duty cycle = 50% ± 10%  
fTA  
Timer_A input clock frequency  
Timer_A capture timing(1)  
fSYSTEM  
MHz  
ns  
tTA,cap  
TA0, TA1  
3 V  
20  
(1) Parameter characterized up to TA = 105°C, unless otherwise noted.  
30  
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ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
USI, Universal Serial Interface(1)  
over recommended ranges of supply voltage and up to operating free-air temperature, TA = 105°C (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
TYP  
MAX UNIT  
External: SCLK,  
Duty cycle = 50% ± 10%  
SPI slave mode  
fUSI  
USI module clock frequency  
fSYSTEM  
MHz  
f(SCLK)  
VOL,I2C  
Serial clock frequency, slave mode  
Low-level output voltage on SDA and SCL  
3 V  
3 V  
6
MHz  
V
USI module in I2C mode,  
I(OLmax) = 1.5 mA  
VSS  
+ 0.4  
VSS  
(1) Parameters are characterized up to TA = 105°C, unless otherwise noted.  
Typical Characteristics – USI Low-Level Output Voltage on SDA and SCL  
5.0  
4.0  
3.0  
2.0  
1.0  
0.0  
5.0  
V
CC  
= 2.2 V  
V
CC  
= 3 V  
T
A
= 25°C  
4.0  
3.0  
2.0  
1.0  
0.0  
T
= 25°C  
A
T
= 85°C  
A
T
= 85°C  
A
0.0  
0.2  
0.4  
0.6  
0.8  
1.0  
0.0  
0.2  
0.4  
0.6  
0.8  
1.0  
V
OL  
− Low-Level Output Voltage − V  
V
OL  
− Low-Level Output Voltage − V  
Figure 17. USI Low-Level Output Voltage vs Output Current  
Figure 18. USI Low-Level Output Voltage vs Output Current  
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MAX UNIT  
10-Bit ADC, Power Supply and Input Range Conditions  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)  
PARAMETER  
TEST CONDITIONS  
VSS = 0 V  
TA  
VCC  
3 V  
3 V  
MIN  
TYP  
VCC  
VAx  
Analog supply voltage  
2.2  
3.6  
V
V
All Ax terminals, Analog inputs  
selected in ADC10AE register  
Analog input voltage(2)  
0
VCC  
fADC10CLK = 5.0 MHz,  
ADC10ON = 1, REFON = 0,  
ADC10SHT0 = 1, ADC10SHT1 = 0,  
ADC10DIV = 0  
IADC10 ADC10 supply current(3)  
-40°C to 125°C  
-40°C to 125°C  
0.6  
mA  
mA  
fADC10CLK = 5.0 MHz,  
ADC10ON = 0, REF2_5V = 0,  
REFON = 1, REFOUT = 0  
0.25  
0.25  
Reference supply current,  
IREF+  
3 V  
reference buffer disabled(4)  
fADC10CLK = 5.0 MHz,  
ADC10ON = 0, REF2_5V = 1,  
REFON = 1, REFOUT = 0  
fADC10CLK = 5.0 MHz,  
Reference buffer supply  
IREFB,0  
ADC10ON = 0, REFON = 1,  
-40°C to 125°C  
-40°C to 125°C  
3 V  
3 V  
1.1  
0.5  
mA  
mA  
current with ADC10SR = 0(4) REF2_5V = 0, REFOUT = 1,  
ADC10SR = 0  
fADC10CLK = 5.0 MHz,  
ADC10ON = 0, REFON = 1,  
Reference buffer supply  
IREFB,1  
current with ADC10SR = 1(4) REF2_5V = 0, REFOUT = 1,  
ADC10SR = 1  
Only one terminal Ax can be  
Input capacitance  
CI  
RI  
-40°C to 125°C  
-40°C to 125°C  
3 V  
3 V  
27  
pF  
selected at one time  
Input MUX ON resistance  
0 V ≤ VAx ≤ VCC  
1000  
Ω
(1) The leakage current is defined in the leakage current table with Px.x/Ax parameter.  
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.  
(3) The internal reference supply current is not included in current consumption parameter IADC10  
.
(4) The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a  
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.  
32  
Copyright © 2012, Texas Instruments Incorporated  
MSP430G2332-EP  
www.ti.com.cn  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
10-Bit ADC, Built-In Voltage Reference  
over recommended ranges of supply voltage and up to operating free-air temperature, TA = 105°C (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VREF+ ≤ 1 mA, REF2_5V = 0  
VCC  
MIN  
2.2  
TYP  
MAX UNIT  
I
I
I
I
Positive built-in reference  
analog supply voltage range  
VCC,REF+  
V
VREF+ ≤ 1 mA, REF2_5V = 1  
3
VREF+ ≤ IVREF+max, REF2_5V = 0  
VREF+ ≤ IVREF+max, REF2_5V = 1  
1.37  
2.29  
1.5  
2.5  
1.61  
V
Positive built-in reference  
voltage  
VREF+  
3 V  
3 V  
2.7  
Maximum VREF+ load  
current(1)  
ILD,VREF+  
±1  
±2  
mA  
IVREF+ = 500 µA ± 100 µA,  
Analog input voltage VAx ≈ 0.75 V,  
REF2_5V = 0  
VREF+ load regulation(1)  
3 V  
3 V  
LSB  
IVREF+ = 500 µA ± 100 µA,  
Analog input voltage VAx ≈ 1.25 V,  
REF2_5V = 1  
±2  
IVREF+ = 100 µA→900 µA,  
VAx ≈ 0.5 × VREF+,  
Error of conversion result ≤ 1 LSB,  
VREF+ load regulation  
response time  
400  
ns  
ADC10SR = 0  
Maximum capacitance at  
pin VREF+(1)  
CVREF+  
TCREF+  
I
VREF+ ≤ ±1 mA, REFON = 1, REFOUT = 1  
3 V  
3 V  
100  
pF  
ppm/  
°C  
Temperature coefficient  
IVREF+ = const with 0 mA ≤ IVREF+ ≤ 1 mA  
±170  
Settling time of internal  
reference voltage to 99.9%  
VREF  
IVREF+ = 0.5 mA, REF2_5V = 0,  
REFON = 0 → 1  
tREFON  
3.6 V  
3 V  
30  
2
µs  
µs  
IVREF+ = 0.5 mA,  
REF2_5V = 1, REFON = 1,  
REFBURST = 1, ADC10SR = 0  
Settling time of reference  
buffer to 99.9% VREF(1)  
tREFBURST  
(1) Minimum and maximum parameters are characterized up to TA = 105°C, unless otherwise noted.  
Copyright © 2012, Texas Instruments Incorporated  
33  
MSP430G2332-EP  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
www.ti.com.cn  
10-Bit ADC, External Reference(1)  
over recommended ranges of supply voltage and up to operating free-air temperature, TA = 105°C (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
TYP  
MAX UNIT  
VEREF+ > VEREF–,  
SREF1 = 1, SREF0 = 0  
1.4  
VCC  
Positive external reference input  
voltage range(2)  
VEREF+  
V
VEREF– ≤ VEREF+ ≤ VCC – 0.15 V,  
SREF1 = 1, SREF0 = 1  
1.4  
0
3
(3)  
Negative external reference input  
voltage range(4)  
VEREF–  
VEREF+ > VEREF–  
1.2  
V
V
Differential external reference  
input voltage range,  
(5)  
ΔVEREF  
VEREF+ > VEREF–  
1.4  
VCC  
ΔVEREF = VEREF+ – VEREF–  
0 V ≤ VEREF+ ≤ VCC  
SREF1 = 1, SREF0 = 0  
,
±1  
IVEREF+  
Static input current into VEREF+  
Static input current into VEREF–  
3 V  
3 V  
µA  
µA  
0 V ≤ VEREF+ ≤ VCC – 0.15 V ≤ 3 V,  
0
SREF1 = 1, SREF0 = 1(3)  
IVEREF–  
0 V ≤ VEREF– ≤ VCC  
±1  
(1) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the  
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the  
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.  
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced  
accuracy requirements.  
(3) Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply  
current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.  
(4) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced  
accuracy requirements.  
(5) The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with  
reduced accuracy requirements.  
10-Bit ADC, Timing Parameters  
over recommended ranges of supply voltage and up to operating free-air temperature, TA = 105°C (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
0.45  
0.45  
TYP  
MAX  
6.3  
UNIT  
ADC10SR = 0  
ADC10SR = 1  
ADC10 input clock  
frequency  
For specified performance of  
ADC10 linearity parameters  
fADC10CLK  
fADC10OSC  
3 V  
MHz  
1.5  
ADC10 built-in oscillator ADC10DIVx = 0, ADC10SSELx = 0,  
3 V  
3 V  
3.35  
2.06  
6.9  
MHz  
µs  
frequency  
fADC10CLK = fADC10OSC  
ADC10 built-in oscillator, ADC10SSELx = 0,  
fADC10CLK = fADC10OSC  
3.51  
tCONVERT  
Conversion time  
13 ×  
fADC10CLK from ACLK, MCLK, or SMCLK:  
ADC10DIV ×  
1/fADC10CLK  
ADC10SSELx ≠ 0  
Turn-on settling time of  
the ADC  
(1)  
tADC10ON  
See  
100  
ns  
(1) The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already  
settled.  
10-Bit ADC, Linearity Parameters  
over recommended ranges of supply voltage and up to operating free-air temperature, TA = 105°C (unless otherwise noted)  
PARAMETER  
Integral linearity error  
Differential linearity error  
Offset error  
TEST CONDITIONS  
VCC  
3 V  
3 V  
3 V  
3 V  
3 V  
MIN  
TYP  
MAX UNIT  
±1 LSB  
±1 LSB  
±1 LSB  
±2 LSB  
±5 LSB  
EI  
ED  
EO  
EG  
ET  
Source impedance RS < 100 Ω  
Gain error  
±1.1  
±2  
Total unadjusted error  
34  
Copyright © 2012, Texas Instruments Incorporated  
MSP430G2332-EP  
www.ti.com.cn  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
10-Bit ADC, Temperature Sensor and Built-In VMID  
over recommended ranges of supply voltage and up to operating free-air temperature, TA = 105°C (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
3 V  
3 V  
3 V  
3 V  
3 V  
MIN  
TYP  
MAX UNIT  
Temperature sensor supply  
current(1)  
REFON = 0, INCHx = 0Ah,  
TA = 25°C  
ISENSOR  
TCSENSOR  
tSensor(sample)  
IVMID  
60  
µA  
mV/°C  
µs  
(2)  
ADC10ON = 1, INCHx = 0Ah  
ADC10ON = 1, INCHx = 0Ah,  
Error of conversion result ≤ 1 LSB  
3.55  
Sample time required if channel  
30  
(3)  
10 is selected  
(4)  
Current into divider at channel 11 ADC10ON = 1, INCHx = 0Bh  
µA  
ADC10ON = 1, INCHx = 0Bh,  
VCC divider at channel 11  
VMID  
1.5  
V
V
MID ≈ 0.5 × VCC  
Sample time required if channel  
11 is selected  
ADC10ON = 1, INCHx = 0Bh,  
Error of conversion result ≤ 1 LSB  
tVMID(sample)  
3 V  
1220  
ns  
(5)  
(1) The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is  
high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature sensor  
input (INCH = 0Ah).  
(2) The following formula can be used to calculate the temperature sensor output voltage:  
VSensor,typ = TCSensor (273 + T [°C] ) + VOffset,sensor [mV] or  
VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV]  
(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)  
(4) No additional current is needed. The VMID is used during sampling.  
.
(5) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.  
Flash Memory(1)(2)  
over recommended ranges of supply voltage and up to operating free-air temperature, TA = 105°C (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
2.2  
TYP  
MAX UNIT  
3.6  
476 kHz  
VCC(PGM/ERASE)  
fFTG  
Program and erase supply voltage  
Flash timing generator frequency  
Supply current from VCC during program  
Supply current from VCC during erase  
Cumulative program time(3)  
V
257  
IPGM  
2.2 V, 3.6 V  
2.2 V, 3.6 V  
2.2 V, 3.6 V  
2.2 V, 3.6 V  
1
1
5
7
mA  
mA  
IERASE  
tCPT  
10  
ms  
tCMErase  
Cumulative mass erase time  
Program and erase endurance  
Data retention duration  
20  
104  
100  
ms  
-40°C ≤ TJ ≤105°C  
105  
cycles  
years  
tFTG  
tFTG  
tRetention  
tWord  
TJ = 25°C  
(4)  
Word or byte program time  
See  
30  
25  
(4)  
tBlock, 0  
Block program time for first byte or word  
See  
Block program time for each additional  
byte or word  
(4)  
tBlock, 1-63  
See  
18  
tFTG  
(4)  
tBlock, End  
tMass Erase  
tSeg Erase  
Block program end-sequence wait time  
Mass erase time  
See  
6
10593  
4819  
tFTG  
tFTG  
tFTG  
(4)  
See  
(4)  
Segment erase time  
See  
(1) Parameters are characterized up to TA = 105°C unless otherwise noted.  
(2) Additional flash retention documentation located in application report SLAA392.  
(3) The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming  
methods: individual word/byte write and block write modes.  
(4) These values are hardwired into the flash controller's state machine (tFTG = 1/fFTG).  
Copyright © 2012, Texas Instruments Incorporated  
35  
MSP430G2332-EP  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
www.ti.com.cn  
RAM  
over recommended ranges of supply voltage and up to operating free-air temperature, TA = 105°C (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
CPU halted  
MIN  
MAX  
UNIT  
(1)  
V(RAMh)  
RAM retention supply voltage  
1.6  
V
(1) This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should  
happen during this supply voltage condition.  
JTAG and Spy-Bi-Wire Interface  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
0
TYP  
MAX  
20  
UNIT  
MHz  
µs  
fSBW  
Spy-Bi-Wire input frequency  
2.2 V  
2.2 V  
tSBW,Low Spy-Bi-Wire low clock pulse length  
0.025  
15  
Spy-Bi-Wire enable time  
tSBW,En  
2.2 V  
1
µs  
(TEST high to acceptance of first clock edge(1)  
)
tSBW,Ret  
fTCK  
Spy-Bi-Wire return to normal operation time  
TCK input frequency(2)  
TA = -40°C to 105°C  
TA = -40°C to 105°C  
2.2 V  
2.2 V  
2.2 V  
15  
0
100  
5
µs  
MHz  
kΩ  
RInternal  
Internal pulldown resistance on TEST  
25  
60  
90  
(1) Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before  
applying the first SBWCLK clock edge.  
(2) fTCK may be restricted to meet the timing requirements of the module selected.  
JTAG Fuse(1)  
TA = 25°C, over recommended ranges of supply voltage (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
TA = 25°C  
MIN  
2.5  
6
MAX  
UNIT  
V
VCC(FB)  
VFB  
Supply voltage during fuse-blow condition  
Voltage level on TEST for fuse blow  
Supply current into TEST during fuse blow  
Time to blow fuse  
7
100  
1
V
IFB  
mA  
ms  
tFB  
(1) Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to  
bypass mode.  
36  
Copyright © 2012, Texas Instruments Incorporated  
MSP430G2332-EP  
www.ti.com.cn  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
PIN SCHEMATICS  
Port P1 Pin Schematic: P1.0 to P1.2, Input/Output With Schmitt Trigger  
To ADC10  
INCHx = y  
ADC10AE0.y  
PxSEL2.y  
PxSEL.y  
PxDIR.y  
0
1
Direction  
0: Input  
1: Output  
0
2
3
PxSEL2.y  
PxSEL.y  
PxREN.y  
0
1
1
0
1
PxSEL2.y  
PxSEL.y  
DVSS  
DVCC  
0
1
1
PxOUT.y  
0
1
From Module  
2
3
Bus  
Keeper  
EN  
P1.0/TA0CLK/ACLK/A0  
P1.1/TA0.0/A1  
P1.2/TA0.1/A2  
0
TAx.y  
TAxCLK  
PxIN.y  
EN  
To Module  
PxIRQ.y  
D
PxIE.y  
EN  
Set  
Q
PxIFG.y  
PxSEL.y  
PxIES.y  
Interrupt  
Edge  
Select  
Copyright © 2012, Texas Instruments Incorporated  
37  
MSP430G2332-EP  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
www.ti.com.cn  
Table 15. Port P1 (P1.0 to P1.2) Pin Functions  
CONTROL BITS / SIGNALS(1)  
PIN NAME (P1.x)  
x
FUNCTION  
P1DIR.x  
P1SEL.x  
P1SEL2.x  
P1.0/  
P1.x (I/O)  
TA0.TACLK  
ACLK  
I: 0; O: 1  
0
1
1
X
0
0
1
1
X
0
0
1
1
X
0
0
0
0
X
1
0
0
0
X
1
0
0
0
X
1
TA0CLK/  
ACLK/  
A0/  
0
0
1
A0  
X
Pin Osc  
P1.1/  
Capacitive sensing  
P1.x (I/O)  
TA0.0  
x
I: 0; O: 1  
TA0.0/  
1
2
1
TA0.CCI0A  
A1  
0
A1/  
X
Pin Osc  
P1.2/  
Capacitive sensing  
P1.x (I/O)  
TA0.1  
X
I: 0; O: 1  
TA0.1/  
1
0
TA0.CCI1A  
A2  
A2/  
X
X
Pin Osc  
Capacitive sensing  
(1) X = don't care  
38  
Copyright © 2012, Texas Instruments Incorporated  
MSP430G2332-EP  
www.ti.com.cn  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
Port P1 Pin Schematic: P1.3, Input/Output With Schmitt Trigger  
SREF2  
VSS  
0
1
To ADC10 VREF-  
To ADC10  
INCHx = y  
ADC10AE0.y  
PxDIR.y  
PxSEL2.y PxSEL.y  
0,2,3  
1
Direction  
0: Input  
1: Output  
PxSEL2.y  
PxSEL.y  
PxREN.y  
0
1
1
0
1
PxSEL2.y  
PxSEL.y  
DVSS  
DVCC  
0
1
1
PxOUT.y  
0
1
From ADC10 *  
2
3
Bus  
Keeper  
EN  
P1.3/ADC10CLK/A3/  
VREF-/VEREF-  
TAx.y  
TAxCLK  
PxIN.y  
EN  
To Module  
PxIRQ.y  
D
PxIE.y  
EN  
Set  
Q
PxIFG.y  
Interrupt  
Edge  
Select  
PxSEL.y  
PxIES.y  
Copyright © 2012, Texas Instruments Incorporated  
39  
MSP430G2332-EP  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
www.ti.com.cn  
Table 16. Port P1 (P1.3) Pin Functions  
CONTROL BITS / SIGNALS(1)  
PIN NAME  
(P1.x)  
x
FUNCTION  
ADC10AE.x  
(INCH.x=1)  
P1DIR.x  
P1SEL.x  
P1SEL2.x  
P1.3/  
P1.x (I/O)  
ADC10CLK  
A3  
I: 0; O: 1  
0
1
0
0
0
ADC10CLK/  
A3/  
1
X
X
X
X
0
X
X
X
0
X
X
X
1
1 (y = 3)  
3
VREF-/  
VEREF-/  
Pin Osc  
VREF-  
1
1
0
VEREF-  
Capacitive sensing  
(1) X = don't care  
40  
Copyright © 2012, Texas Instruments Incorporated  
MSP430G2332-EP  
www.ti.com.cn  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
Port P1 Pin Schematic: P1.4, Input/Output With Schmitt Trigger  
From/To ADC10 Ref+  
To ADC10  
INCHx = y  
ADC10AE0.y  
PxSEL.y  
PxDIR.y  
0
1
Direction  
0: Input  
1: Output  
PxSEL2.y  
PxSEL.y  
PxREN.y  
0
1
1
0
1
PxSEL2.y  
PxSEL.y  
DVSS  
DVCC  
0
1
1
PxOUT.y  
SMCLK  
0
1
2
3
Bus  
Keeper  
EN  
P1.4/SMCLK/TA0.2/A4/  
VREF+/VEREF+/TCK  
from Timer  
TAx.y  
TAxCLK  
PxIN.y  
EN  
D
To Module  
PxIRQ.y  
PxIE.y  
EN  
Q
Set  
PxIFG.y  
PxSEL.y  
PxIES.y  
Interrupt  
Edge  
Select  
From JTAG  
To JTAG  
Table 17. Port P1 (P1.4) Pin Functions  
CONTROL BITS / SIGNALS(1)  
PIN NAME (P1.x)  
x
FUNCTION  
ADC10AE.x  
(INCH.x=1)  
P1DIR.x  
P1SEL.x  
P1SEL2.x  
JTAG Mode  
P1.4/  
P1.x (I/O)  
SMCLK  
I: 0; O: 1  
0
1
1
1
X
X
X
X
0
0
0
1
1
X
X
X
X
1
0
0
0
0
0
0
0
0
1
0
SMCLK/  
TA0.2/  
1
1
0
TA0.2  
0
TA0.CCI2A  
VREF+  
0
0
VREF+/  
VEREF+/  
A4/  
4
X
X
X
X
X
1
VEREF+  
A4  
1
1 (y = 4)  
TCK/  
TCK  
0
0
Pin Osc  
Capacitive sensing  
(1) X = don't care  
Copyright © 2012, Texas Instruments Incorporated  
41  
MSP430G2332-EP  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
www.ti.com.cn  
Port P1 Pin Schematic: P1.5 to P1.7, Input/Output With Schmitt Trigger  
To ADC10  
INCHx = y  
ADC10AE0.y  
PxSEL2.y  
PxSEL.y  
PxDIR.y  
0
From Module  
1
Direction  
0: Input  
1: Output  
2
3
PxSEL2.y  
PxSEL.y  
PxREN.y  
0
1
1
0
1
PxSEL2.y  
PxSEL.y  
DVSS  
DVCC  
0
1
1
PxOUT.y  
0
1
From Module  
2
3
Bus  
Keeper  
EN  
P1.5/TA0.0/SCLK/A5/TMS  
P1.6/TA0.1/SDO/SCL/A6/TDI/TCLK  
P1.7//SDI/SDA/A7/TDO/TDI  
0
TAx.y  
TAxCLK  
PxIN.y  
EN  
D
To Module  
PxIRQ.y  
PxIE.y  
EN  
Set  
Q
PxIFG.y  
PxSEL.y  
PxIES.y  
Interrupt  
Edge  
Select  
From JTAG  
To JTAG  
42  
Copyright © 2012, Texas Instruments Incorporated  
MSP430G2332-EP  
www.ti.com.cn  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
Table 18. Port P1 (P1.5 to P1.7) Pin Functions  
CONTROL BITS / SIGNALS(1)  
PIN NAME  
(P1.x)  
x
FUNCTION  
ADC10AE.x  
(INCH.x=1)  
P1DIR.x  
P1SEL.x  
P1SEL2.x  
USIP.x  
JTAG Mode  
P1.5/  
P1.x (I/O)  
I: 0; O: 1  
0
1
1
X
X
0
0
1
1
1
X
X
0
0
1
1
X
X
0
0
0
0
X
X
1
0
0
0
0
X
X
1
0
0
0
X
X
1
0
0
1
0
0
0
0
0
!
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
TA0.0/  
SCLK/  
A5/  
TA0.0  
1
0
SPI mode  
A5  
from USI  
0
5
X
1 (y = 5)  
TMS/  
TMS  
X
0
Pin Osc  
P1.6/  
Capacitive sensing  
P1.x (I/O)  
TA0.1  
X
0
I: 0; O: 1  
0
TA0.1/  
SDO/  
1
0
SPI mode  
I2C mode  
A6  
from USI  
0
SCL/  
6
from USI  
!
0
A6/  
X
0
0
0
0
1
1
0
0
0
1 (y = 6)  
TDI/TCLK/  
Pin Osc  
P1.7/  
TDI/TCLK  
Capacitive sensing  
P1.x (I/O)  
SPI mode  
SPI mode  
A7  
X
0
X
0
I: 0; O: 1  
0
SDI/  
from USI  
0
SDA/  
from USI  
0
7
A7/  
X
X
X
1 (y = 7)  
TDO/TDI/  
Pin Osc  
TDO/TDI  
Capacitive sensing  
0
0
(1) X = don't care  
Copyright © 2012, Texas Instruments Incorporated  
43  
MSP430G2332-EP  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
www.ti.com.cn  
Port P2 Pin Schematic: P2.0 to P2.5, Input/Output With Schmitt Trigger  
PxSEL.y  
PxDIR.y  
0
1
Direction  
0: Input  
1: Output  
PxSEL2.y  
PxSEL.y  
PxREN.y  
0
1
1
0
1
PxSEL2.y  
PxSEL.y  
DVSS  
DVCC  
0
1
1
PxOUT.y  
0
1
0
2
3
P2.0  
P2.1  
P2.2  
P2.3  
P2.4  
P2.5  
0
TAx.y  
TAxCLK  
PxIN.y  
EN  
D
To Module  
PxIRQ.y  
PxIE.y  
EN  
Set  
Q
PxIFG.y  
Interrupt  
Edge  
Select  
PxSEL.y  
PxIES.y  
44  
Copyright © 2012, Texas Instruments Incorporated  
MSP430G2332-EP  
www.ti.com.cn  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
Table 19. Port P2 (P2.0 to P2.5) Pin Functions  
CONTROL BITS / SIGNALS(1)  
PIN NAME  
(P2.x)  
x
0
1
2
3
4
5
FUNCTION  
P2DIR.x  
P2SEL.x  
P2SEL2.x  
P2.0/  
P2.x (I/O)  
I: 0; O: 1  
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
Pin Osc  
P2.1/  
Capacitive sensing  
P2.x (I/O)  
X
I: 0; O: 1  
Pin Osc  
P2.2/  
Capacitive sensing  
P2.x (I/O)  
X
I: 0; O: 1  
Pin Osc  
P2.3/  
Capacitive sensing  
P2.x (I/O)  
X
I: 0; O: 1  
Pin Osc  
P2.4/  
Capacitive sensing  
P2.x (I/O)  
X
I: 0; O: 1  
X
Pin Osc  
P2.5/  
Capacitive sensing  
P2.x (I/O)  
I: 0; O: 1  
X
Pin Osc  
Capacitive sensing  
(1) X = don't care  
Copyright © 2012, Texas Instruments Incorporated  
45  
MSP430G2332-EP  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
www.ti.com.cn  
Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger  
XOUT/P2.7  
LF off  
PxSEL.6 & PxSEL.7  
BCSCTL3.LFXT1Sx = 11  
0
LFXT1CLK  
1
PxSEL.y  
PxDIR.y  
0
1
Direction  
0: Input  
1: Output  
PxSEL2.y  
PxSEL.y  
PxREN.y  
0
1
1
0
1
PxSEL2.y  
PxSEL.y  
DVSS  
DVCC  
0
1
1
PxOUT.y  
0
1
From Module  
2
3
XIN/P2.6/TA0.1  
0
TAx.y  
TAxCLK  
PxIN.y  
EN  
D
To Module  
PxIRQ.y  
PxIE.y  
EN  
Set  
Q
PxIFG.y  
Interrupt  
Edge  
Select  
PxSEL.y  
PxIES.y  
Table 20. Port P2 (P2.6) Pin Functions  
CONTROL BITS / SIGNALS(1)  
PIN NAME  
(P2.x)  
x
FUNCTION  
P2SEL.6  
P2SEL.7  
P2SEL2.6  
P2SEL2.7  
P2DIR.x  
1
1
0
0
XIN/  
XIN  
0
0
X
0
0
P2.6/  
P2.x (I/O)  
I: 0; O: 1  
6
1
0
0
0
TA0.1/  
Timer0_A3.TA1  
Capacitive sensing  
1
0
X
1
X
Pin Osc  
X
(1) X = don't care  
46  
Copyright © 2012, Texas Instruments Incorporated  
MSP430G2332-EP  
www.ti.com.cn  
ZHCSA51A –AUGUST 2012–REVISED OCTOBER 2012  
Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger  
XIN/P2.6/TA0.1  
LF off  
PxSEL.6 & PxSEL.7  
BCSCTL3.LFXT1Sx = 11  
0
LFXT1CLK  
1
from P2.6  
PxSEL.y  
PxDIR.y  
0
1
Direction  
0: Input  
1: Output  
PxSEL2.y  
PxSEL.y  
PxREN.y  
0
1
1
0
1
PxSEL2.y  
PxSEL.y  
DVSS  
DVCC  
0
1
1
PxOUT.y  
0
1
From Module  
2
3
XOUT/P2.7  
TAx.y  
TAxCLK  
PxIN.y  
EN  
D
To Module  
PxIRQ.y  
PxIE.y  
EN  
Set  
Q
PxIFG.y  
Interrupt  
Edge  
Select  
PxSEL.y  
PxIES.y  
Table 21. Port P2 (P2.7) Pin Functions  
CONTROL BITS / SIGNALS(1)  
PIN NAME  
(P2.x)  
x
FUNCTION  
P2SEL.6  
P2SEL.7  
P2SEL2.6  
P2SEL2.7  
P2DIR.x  
1
1
0
0
XOUT/  
XOUT  
X
I: 0; O: 1  
X
X
0
0
0
P2.7/  
7
P2.x (I/O)  
X
0
X
1
Pin Osc  
Capacitive sensing  
(1) X = don't care  
Copyright © 2012, Texas Instruments Incorporated  
47  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
MSP430G2332QPW2EP  
MSP430G2332QPW2REP  
V62/12625-01XE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
PW  
PW  
PW  
PW  
20  
20  
20  
20  
70  
RoHS & Green  
NIPDAU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
G2332EP  
2000 RoHS & Green  
2000 RoHS & Green  
NIPDAU  
NIPDAU  
NIPDAU  
G2332EP  
G2332EP  
G2332EP  
V62/12625-01XE-T  
70  
RoHS & Green  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF MSP430G2332-EP :  
Catalog: MSP430G2332  
•
NOTE: Qualified Version Definitions:  
Catalog - TI's standard catalog product  
•
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
3-Jun-2022  
TAPE AND REEL INFORMATION  
REEL DIMENSIONS  
TAPE DIMENSIONS  
K0  
P1  
W
B0  
Reel  
Diameter  
Cavity  
A0  
A0 Dimension designed to accommodate the component width  
B0 Dimension designed to accommodate the component length  
K0 Dimension designed to accommodate the component thickness  
Overall width of the carrier tape  
W
P1 Pitch between successive cavity centers  
Reel Width (W1)  
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE  
Sprocket Holes  
Q1 Q2  
Q3 Q4  
Q1 Q2  
Q3 Q4  
User Direction of Feed  
Pocket Quadrants  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
MSP430G2332QPW2REP TSSOP  
PW  
20  
2000  
330.0  
16.4  
6.95  
7.1  
1.6  
8.0  
16.0  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
3-Jun-2022  
TAPE AND REEL BOX DIMENSIONS  
Width (mm)  
H
W
L
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
TSSOP PW 20  
SPQ  
Length (mm) Width (mm) Height (mm)  
356.0 356.0 35.0  
MSP430G2332QPW2REP  
2000  
Pack Materials-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
3-Jun-2022  
TUBE  
T - Tube  
height  
L - Tube length  
W - Tube  
width  
B - Alignment groove width  
*All dimensions are nominal  
Device  
Package Name Package Type  
Pins  
SPQ  
L (mm)  
W (mm)  
T (µm)  
B (mm)  
MSP430G2332QPW2EP  
V62/12625-01XE-T  
PW  
PW  
TSSOP  
TSSOP  
20  
20  
70  
70  
530  
530  
10.2  
10.2  
3600  
3600  
3.5  
3.5  
Pack Materials-Page 3  
PACKAGE OUTLINE  
PW0020A  
TSSOP - 1.2 mm max height  
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE  
SEATING  
PLANE  
C
6.6  
6.2  
TYP  
A
0.1 C  
PIN 1 INDEX AREA  
18X 0.65  
20  
1
2X  
5.85  
6.6  
6.4  
NOTE 3  
10  
B
11  
0.30  
20X  
4.5  
4.3  
NOTE 4  
0.19  
1.2 MAX  
0.1  
C A B  
(0.15) TYP  
SEE DETAIL A  
0.25  
GAGE PLANE  
0.15  
0.05  
0.75  
0.50  
A
20  
0 -8  
DETAIL A  
TYPICAL  
4220206/A 02/2017  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not  
exceed 0.15 mm per side.  
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.  
5. Reference JEDEC registration MO-153.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
PW0020A  
TSSOP - 1.2 mm max height  
SMALL OUTLINE PACKAGE  
SYMM  
20X (1.5)  
(R0.05) TYP  
20  
1
20X (0.45)  
SYMM  
18X (0.65)  
11  
10  
(5.8)  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE: 10X  
METAL UNDER  
SOLDER MASK  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL  
EXPOSED METAL  
EXPOSED METAL  
0.05 MAX  
ALL AROUND  
0.05 MIN  
ALL AROUND  
NON-SOLDER MASK  
DEFINED  
SOLDER MASK  
DEFINED  
15.000  
(PREFERRED)  
SOLDER MASK DETAILS  
4220206/A 02/2017  
NOTES: (continued)  
6. Publication IPC-7351 may have alternate designs.  
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
PW0020A  
TSSOP - 1.2 mm max height  
SMALL OUTLINE PACKAGE  
20X (1.5)  
SYMM  
(R0.05) TYP  
20  
1
20X (0.45)  
SYMM  
18X (0.65)  
10  
11  
(5.8)  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
SCALE: 10X  
4220206/A 02/2017  
NOTES: (continued)  
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
9. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
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