MSP430X11X_16 [TI]
MIXED SIGNAL MICROCONTROLLERS;型号: | MSP430X11X_16 |
厂家: | TEXAS INSTRUMENTS |
描述: | MIXED SIGNAL MICROCONTROLLERS |
文件: | 总33页 (文件大小:548K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇꢇꢆ
ꢀ ꢈꢉꢊ ꢋ ꢁꢈ ꢌ ꢍꢎꢏ ꢀ ꢈꢐꢑꢒ ꢐꢒ ꢍ ꢓꢑ ꢒ ꢏꢏꢊ ꢑ ꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
D
D
Low Supply Voltage Range 2.5 V to 5.5 V
D
D
D
Serial Onboard Programming
Ultralow-Power Consumption:
− Active Mode: 330 µA at 1 MHz, 3 V
− Standby Mode: 1.5 µA
− Off Mode (RAM Retention): 0.1 µA
Wake-up From Standby Mode in less
Program Code Protection by Security Fuse
Family Members Include:
MSP430C111: 2k Byte ROM,128 Byte RAM
MSP430C112: 4k Byte ROM, 256 Byte RAM
MSP430P112: 4k Byte OTP, 256 Byte RAM
D
D
D
than 6 µs
D
D
EPROM Version Available for Prototyping:
− PMS430E112: 4k Byte EPROM, 256 Byte
RAM
16-Bit RISC Architecture, 200 ns Instruction
Cycle Time
Basic Clock Module Configurations:
− Various Internal Resistors
− Single External Resistor
− 32 kHz Crystal
Available in a 20-Pin Plastic Small-Outline
Wide Body (SOWB) Package, 20-Pin
Ceramic Dual-In-Line (CDIP) Package
(EPROM Only)
− High Frequency Crystal
− Resonator
− External Clock Source
D
For Complete Module Descriptions, Refer
to the MSP430x1xx Family User’s Guide,
Literature Number SLAU049
D
16-Bit Timer_A With Three
Capture/Compare Registers
DW PACKAGE
(TOP VIEW)
description
The Texas Instruments MSP430 family of ultralow
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TEST/VPP
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI
P1.5/TA0/TMS
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
P2.4/TA2
P2.3/TA1
power microcontrollers consist of several devices
featuring different sets of peripherals targeted for
various applications. The architecture, combined
with five low power modes is optimized to achieve
extended battery life in portable measurement
applications. The device features a powerful
16-bit RISC CPU, 16-bit registers, and constant
generators that attribute to maximum code
efficiency. The digitally controlled oscillator (DCO)
allows wake-up from low-power modes to active
mode in less than 6µs.
V
CC
P2.5/R
OSC
SS
V
XOUT/TCLK
XIN
RST/NMI
P2.0/ACLK
P2.1/INCLK
P2.2/TA0
The MSP430x11x series is an ultra low-power mixed signal microcontroller with a built in 16-bit timer and
fourteen I/O pins.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data and display them or transmit them to a host system. Stand alone RF sensor front-end is another
area of application.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢂ
ꢂ
ꢑ
ꢒ
ꢤ
ꢋ
ꢟ
ꢔ
ꢐ
ꢝ
ꢓ
ꢞ
ꢈ
ꢘ
ꢒ
ꢖ
ꢍ
ꢗ
ꢋ
ꢎ
ꢓ
ꢎ
ꢕ
ꢖ
ꢠ
ꢗ
ꢘ
ꢞ
ꢙ
ꢚ
ꢛ
ꢛ
ꢜ
ꢜ
ꢕ
ꢕ
ꢘ
ꢘ
ꢖ
ꢖ
ꢕ
ꢝ
ꢝ
ꢡ
ꢞ
ꢟ
ꢙ
ꢙ
ꢠ
ꢠ
ꢖ
ꢜ
ꢛ
ꢚ
ꢝ
ꢝ
ꢘ
ꢗ
ꢡ
ꢓꢠ
ꢟ
ꢢ
ꢝ
ꢣ
ꢕ
ꢞ
ꢛ
ꢝ
ꢜ
ꢕ
ꢜ
ꢘ
ꢙ
ꢖ
ꢟ
ꢤ
ꢛ
ꢖ
ꢜ
ꢜ
ꢠ
ꢝ
ꢥ
Copyright 1998 − 2004, Texas Instruments Incorporated
ꢙ
ꢘ
ꢞ
ꢜ
ꢘ
ꢙ
ꢚ
ꢜ
ꢘ
ꢝ
ꢡ
ꢕ
ꢗ
ꢕ
ꢞ
ꢠ
ꢙ
ꢜ
ꢦ
ꢜ
ꢠ
ꢙ
ꢘ
ꢗ
ꢆ
ꢛ
ꢈ
ꢖ
ꢚ
ꢠ
ꢝ
ꢜ
ꢛ
ꢖ
ꢤ
ꢛ
ꢙ
ꢤ
ꢧ
ꢛ
ꢜ ꢠ ꢝ ꢜꢕ ꢖꢩ ꢘꢗ ꢛ ꢣꢣ ꢡꢛ ꢙ ꢛ ꢚ ꢠ ꢜ ꢠ ꢙ ꢝ ꢥ
ꢙ
ꢙ
ꢛ
ꢖ
ꢜ
ꢨ
ꢥ
ꢂ
ꢙ
ꢘ
ꢤ
ꢟ
ꢞ
ꢜ
ꢕ
ꢘ
ꢖ
ꢡ
ꢙ
ꢘ
ꢞ
ꢠ
ꢝ
ꢝ
ꢕ
ꢖ
ꢩ
ꢤ
ꢘ
ꢠ
ꢝ
ꢖ
ꢘ
ꢜ
ꢖ
ꢠ
ꢞ
ꢠ
ꢝ
ꢝ
ꢛ
ꢙ
ꢕ
ꢣ
ꢨ
ꢕ
ꢖ
ꢞ
ꢣ
ꢟ
ꢤ
ꢠ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢆ
ꢀ ꢈ ꢉ ꢊꢋ ꢁꢈ ꢌꢍ ꢎ ꢏ ꢀꢈ ꢐ ꢑꢒꢐ ꢒꢍ ꢓꢑ ꢒꢏ ꢏꢊ ꢑꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
AVAILABLE OPTIONS
PACKAGED DEVICES
CDIP
20-Pin
(JL)
SOWB
20-Pin
(DW)
T
A
MSP430C111IDW
MSP430C112IDW
MSP430P112IDW
−40°C to 85°C
25°C
—
PMS430E112JL
functional block diagram
P1
XIN XOUT/TCLK
V
RST/NMI
P2
V
CC
SS
JTAG
8
6
R
OSC
Oscillator
ACLK
2/4KB
ROM
256B RAM
128B RAM
I/O Port 1
8 I/Os, with 6 I/Os, with
Interrupt
Capability
I/O Port 2
System
Clock
SMCLK
Interrupt
Capability
4KB OTP
MCLK
MAB,
4 Bit
Test
MAB,16-Bit
JTAG
CPU
MCB
Incl. 16 Reg.
Bus
Conv
MDB, 16-Bit
MDB, 8 Bit
TEST/VPP
Watchdog
Timer
Timer_A3
3 CC Reg
POR
15/16-Bit
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇꢇꢆ
ꢀ ꢈꢉꢊ ꢋ ꢁꢈ ꢌ ꢍꢎꢏ ꢀ ꢈꢐꢑꢒ ꢐꢒ ꢍꢓ ꢑꢒ ꢏꢏ ꢊꢑ ꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
13
14
15
16
17
P1.0/TACLK
P1.1/TA0
I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input
I/O General-purpose digital I/O pin/Timer_A, Capture: CCI0A input, Compare: Out0 output
I/O General-purpose digital I/O pin/Timer_A, Capture: CCI1A input, Compare: Out1 output
I/O General-purpose digital I/O pin/Timer_A, Capture: CCI2A input, Compare: Out2 output
P1.2/TA1
P1.3/TA2
P1.4/SMCLK/TCK
I/O General-purpose digital I/O pin/SMCLK signal output/Test clock, input terminal for device programming
and test
P1.5/TA0/TMS
18
I/O General-purpose digital I/O pin/Timer_A, Compare: Out0 output/test mode select, input terminal for
device programming and test.
P1.6/TA1/TDI
19
20
I/O General-purpose digital I/O pin/Timer_A, Compare: Out1 output/test data input terminal.
P1.7/TA2/TDO/TDI
I/O General-purpose digital I/O pin/Timer_A, Compare: Out2 output/test data output terminal or data input
during programming.
P2.0/ACLK
P2.1/INCLK
P2.2/TA0
8
9
I/O General-purpose digital I/O pin/ACLK output
I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK
10
11
12
3
I/O General-purpose digital I/O pin/Timer_A, Capture: CCI0B input, Compare: Out0 output
I/O General-purpose digital I/O pin/Timer_A, Capture: CCI1B input, Compare: Out1 output
I/O General-purpose digital I/O pin/Timer_A, Compare: Out2 output
P2.3/TA1
P2.4/TA2
P2.5/R
OSC
I/O General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal frequency
RST/NMI
7
I
I
Reset or nonmaskable interrupt input
TEST/VPP
1
Selects test mode for JTAG pins on Port1/programming voltage input during EPROM programming
V
V
2
Supply voltage
CC
4
Ground reference
SS
XIN
6
I
Input terminal of crystal oscillator
XOUT/TCLK
5
I/O Output terminal of crystal oscillator or test clock input
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢆ
ꢀ ꢈ ꢉ ꢊꢋ ꢁꢈ ꢌꢍ ꢎ ꢏ ꢀꢈ ꢐ ꢑꢒꢐ ꢒꢍ ꢓꢑ ꢒꢏ ꢏꢊ ꢑꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
short-form description
CPU
Program Counter
Stack Pointer
PC/R0
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
R4
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
R5
R6
R7
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
R8
R9
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
R10
R11
instruction set
R12
R13
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
R14
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
e.g. ADD R4,R5
R4 + R5 −−−> R5
e.g. CALL
e.g. JNE
R8
PC −−>(TOS), R8−−> PC
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
Register
S
D
SYNTAX
MOV Rs,Rd
EXAMPLE
MOV R10,R11
MOV 2(R5),6(R6)
OPERATION
D D
R10 −−> R11
Indexed
D D
MOV X(Rn),Y(Rm)
MOV EDE,TONI
M(2+R5)−−> M(6+R6)
M(EDE) −−> M(TONI)
M(MEM) −−> M(TCDAT)
M(R10) −−> M(Tab+R6)
Symbolic (PC relative) D D
Absolute
Indirect
D D MOV &MEM,&TCDAT
D
D
D
MOV @Rn,Y(Rm)
MOV @Rn+,Rm
MOV #X,TONI
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
Indirect
autoincrement
M(R10) −−> R11
R10 + 2−−> R10
Immediate
#45 −−> M(TONI)
NOTE: S = source
D = destination
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇꢇꢆ
ꢀ ꢈꢉꢊ ꢋ ꢁꢈ ꢌ ꢍꢎꢏ ꢀ ꢈꢐꢑꢒ ꢐꢒ ꢍꢓ ꢑꢒ ꢏꢏ ꢊꢑ ꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D
D
Active mode AM;
All clocks are active
Low-power mode 0 (LPM0);
−
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
D
D
Low-power mode 1 (LPM1);
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DCO’s dc-generator is disabled if DCO not used in active mode
Low-power mode 2 (LPM2);
−
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D
D
Low-power mode 3 (LPM3);
−
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
Low-power mode 4 (LPM4);
−
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢆ
ꢀ ꢈ ꢉ ꢊꢋ ꢁꢈ ꢌꢍ ꢎ ꢏ ꢀꢈ ꢐ ꢑꢒꢐ ꢒꢍ ꢓꢑ ꢒꢏ ꢏꢊ ꢑꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the ROM with an address range of
0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction
sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up, external reset, watchdog
Reset
0FFFEh
15, highest
WDTIFG (see Note1)
(non)-maskable,
(non)-maskable
NMI, oscillator fault
0FFFCh
14
NMIIFG, OFIFG (see Note 1)
0FFFAh
0FFF8h
0FFF6h
0FFF4h
0FFF2h
13
12
11
10
9
Watchdog Timer
Timer_A3
WDTIFG
maskable
maskable
TACCR0 CCIFG (see Note 2)
TACCR1 and TACCR2
CCIFGs, TAIFG
Timer_A3
maskable
0FFF0h
8
(see Notes 1 and 2)
0FFEEh
0FFECh
0FFEAh
0FFE8h
7
6
5
4
P2IFG.0 to P2IFG.7
(see Notes 1 and 2)
I/O Port P2 (eight flags − see Note 3)
I/O Port P1 (eight flags)
maskable
maskable
0FFE6h
0FFE4h
3
2
P1IFG.0 to P1IFG.7
(see Notes 1 and 2)
0FFE2h
0FFE0h
1
0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module
3. There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0−5) are implemented on the ’11x devices.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇꢇꢆ
ꢀ ꢈꢉꢊ ꢋ ꢁꢈ ꢌ ꢍꢎꢏ ꢀ ꢈꢐꢑꢒ ꢐꢒ ꢍꢓ ꢑꢒ ꢏꢏ ꢊꢑ ꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.
interrupt enable 1
7
6
5
4
3
2
1
0
Address
0h
OFIE
WDTIE
NMIIE
rw-0
rw-0
rw-0
WDTIE:
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer
is configured in interval timer mode.
OFIE:
Oscillator fault enable
NMIIE:
(Non)maskable interrupt enable
interrupt flag register 1
7
6
5
4
3
2
1
0
Address
02h
NMIIFG
OFIFG
WDTIFG
rw-0
rw-1
rw-(0)
WDTIFG:
Set on Watchdog Timer overflow (in watchdog mode) or security key violation.
Reset on V power-up or a reset condition at RST/NMI pin in reset mode.
Flag set on oscillator fault
Set via RST/NMI-pin
CC
OFIFG:
NMIIFG:
Legend rw:
Bit can be read and written.
rw-0,1:
rw-(0,1):
Bit can be read and written. It is Reset or Set by PUC
Bit can be read and written. It is Reset or Set by POR
SFR bit is not present in device.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢆ
ꢀ ꢈ ꢉ ꢊꢋ ꢁꢈ ꢌꢍ ꢎ ꢏ ꢀꢈ ꢐ ꢑꢒꢐ ꢒꢍ ꢓꢑ ꢒꢏ ꢏꢊ ꢑꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
memory organization
MSP430P112
PMS430E112
MSP430C111
MSP430C112
Int. Vector
FFFFh
FFFFh
FFE0h
FFFFh
Int. Vector
2 KB ROM
Int. Vector
FFE0h
FFDFh
FFE0h
FFDFh
FFDFh
4 KB
EPROM
F800h
4 KB ROM
F000h
F000h
02FFh
0200h
02FFh
0200h
027Fh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
128B RAM
16b Per.
8b Per.
SFR
256B RAM
16b Per.
8b Per.
SFR
256B RAM
16b Per.
8b Per.
SFR
01FFh
0100h
00FFh
0010h
000Fh
0000h
01FFh
0100h
00FFh
0010h
000Fh
0000h
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x1xx Family User’s Guide, literature
number SLAU049.
oscillator and system clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock
module is designed to meet the requirements of both low system cost and low-power consumption. The internal
DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The basic clock module provides the
following clock signals:
D
D
D
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
digital I/O
There are two 8-bit I/O ports implemented—ports P1 and P2 (only six P2 I/O signals are available on external
pins):
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of port P1 and six bits of port P2.
Read/write access to port-control registers is supported by all instructions.
NOTE:
Six bits of Port P2, P2.0 to P2.5, are available on external pins − but all control and data bits for Port
P2 are implemented.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇꢇꢆ
ꢀ ꢈꢉꢊ ꢋ ꢁꢈ ꢌ ꢍꢎꢏ ꢀ ꢈꢐꢑꢒ ꢐꢒ ꢍꢓ ꢑꢒ ꢏꢏ ꢊꢑ ꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number Device Input Signal Module Input Name
Module Block
Module Output Signal
Output Pin Number
13 - P1.0
TACLK
ACLK
SMCLK
INCLK
TA0
TACLK
ACLK
Timer
NA
SMCLK
INCLK
CCI0A
CCI0B
GND
9 - P2.1
14 - P1.1
10 - P2.2
14 - P1.1
18 - P1.5
10 - P2.2
TA0
CCR0
CCR1
CCR2
TA0
TA1
TA2
DV
DV
SS
V
CC
CC
15 - P1.2
11 - P2.3
TA1
TA1
CCI1A
CCI1B
GND
15 - P1.2
19 - P1.6
11 - P2.3
DV
SS
DV
V
CC
CC
16 - P1.3
TA2
ACLK (internal)
CCI2A
CCI2B
GND
16 - P1.3
20 - P1.7
12 - P2.4
DV
DV
SS
V
CC
CC
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢆ
ꢀ ꢈ ꢉ ꢊꢋ ꢁꢈ ꢌꢍ ꢎ ꢏ ꢀꢈ ꢐ ꢑꢒꢐ ꢒꢍ ꢓꢑ ꢒꢏ ꢏꢊ ꢑꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog
Timer_A
Watchdog/Timer Control
WDTCTL
0120h
Timer_A Interrupt Vector
Timer_A Control
Cap/Com Control
Cap/Com Control
Cap/Com Control
Reserved
Reserved
Reserved
Reserved
Timer_A Register
Cap/Com Register
Cap/Com Register
Cap/Com Register
Reserved
Reserved
Reserved
Reserved
TAIV
TACTL
TACCTL0
TACCTL1
TACCTL2
012Eh
0160h
0162h
0164h
0166h
0168h
016Ah
016Ch
016Eh
0170h
0172h
0174h
0176h
0178h
017Ah
017Ch
017Eh
TAR
TACCR0
TACCR1
TACCR2
PERIPHERALS WITH BYTE ACCESS
Basic Clock
Basic Clock Sys. Control2
Basic Clock Sys. Control1
DCO Clock Freq. Control
BCSCTL2 058h
BCSCTL1 057h
DCOCTL
056h
EPROM
Port P2
EPROM Control
EPCTL
054h
Port P2 Selection
P2SEL
P2IE
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Port P2 Interrupt Enable
Port P2 Interrupt Edge Select
Port P2 Interrupt Flag
Port P2 Direction
Port P2 Output
Port P2 Input
P2IES
P2IFG
P2DIR
P2OUT
P2IN
Port P1
Port P1 Selection
P1SEL
P1IE
026h
025h
024h
023h
022h
021h
020h
Port P1 Interrupt Enable
Port P1 Interrupt Edge Select
Port P1 Interrupt Flag
Port P1 Direction
Port P1 Output
Port P1 Input
P1IES
P1IFG
P1DIR
P1OUT
P1IN
Special Function
SFR Interrupt Flag1
SFR Interrupt Enable1
IFG1
IE1
002h
000h
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇꢇꢆ
ꢀ ꢈꢉꢊ ꢋ ꢁꢈ ꢌ ꢍꢎꢏ ꢀ ꢈꢐꢑꢒ ꢐꢒ ꢍꢓ ꢑꢒ ꢏꢏ ꢊꢑ ꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
†
absolute maximum ratings
Voltage applied at V
to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
CC
SS
Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V +0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA
CC
Storage temperature, T (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
stg
Storage temperature, T (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to V . The JTAG fuse-blow voltage, V , is allowed to exceed the absolute maximum rating. The voltage is applied
SS
FB
to the TEST pin when blowing the JTAG fuse.
recommended operating conditions
MIN
2.5
2.7
2.7
4.5
4.5
NOM
MAX UNITS
MSP430C11x
MSP430P112
PMS430E112
MSP430P112
MSP430E112
MSP430C11x
MSP430P112
PMS430E112
5.5
V
5.5
Supply voltage, V
CC
5.5
5.5
5.5
V
V
V
5
5
Supply voltage during programming, V
CC
−40
85
Operating free-air temperature range, T
°C
A
25
XTAL frequency, f
(XTAL)
,(ACLK signal)
32768
Hz
V
CC
V
CC
V
CC
V
CC
= 3 V
= 5 V
= 3 V
= 5 V
dc
dc
dc
dc
2
5.35
2.73
5.35
Processor frequency f
(PMS430P/E112) (MCLK signal)
(MCLK signal) (MSP430C11x)
MHz
(system)
(system)
Processor frequency f
MHz
5
4
3
5.35 MHz
at 5 V
2.2 MHz
at 2.5 V
2
1
Minimum
0
0
1
2
3
4
5
6
7
V
CC
− Supply Voltage − V
NOTE: Minimum processor frequency is defined by system clock.
Figure 1. C Version Frequency vs Supply Voltage
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢆ
ꢀ ꢈ ꢉ ꢊꢋ ꢁꢈ ꢌꢍ ꢎ ꢏ ꢀꢈ ꢐ ꢑꢒꢐ ꢒꢍ ꢓꢑ ꢒꢏ ꢏꢊ ꢑꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
recommended operating conditions (continued)
5
4
3
5.35 MHz
at 5 V
2
1.1 MHz
at 2.7 V
1.1
Minimum
0
0
1
2
3
4
5
6
7
V
CC
− Supply Voltage − V
NOTE: Minimum processor frequency is defined by system clock.
Figure 2. P/E Version Frequency vs Supply Voltage
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇꢇꢆ
ꢀ ꢈꢉꢊ ꢋ ꢁꢈ ꢌ ꢍꢎꢏ ꢀ ꢈꢐꢑꢒ ꢐꢒ ꢍꢓ ꢑꢒ ꢏꢏ ꢊꢑ ꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
supply current (into V ) excluding external current
CC
PARAMETER
TEST CONDITIONS
= f = 1 MHz,
(MCLK) (SMCLK)
MIN NOM MAX
UNIT
V
V
V
V
= 3 V
= 5 V
= 3 V
= 5 V
330
630
3.4
7.8
400
700
4
T
= −40°C +85°C, f
CC
CC
CC
CC
A
µA
f
= 32,768 Hz
(ACLK)
C11x
P112
T
= −40°C +85°C,
A
µA
µA
µA
f
= f
= f
= 4096 Hz
10
(MCLK) (SMCLK) (ACLK)
I
Active mode
(AM)
T
= −40°C +85°C,
V
CC
V
CC
= 3 V
= 5 V
400
730
500
900
A
f
= f
= 1 MHz,
= 32,768 Hz
MCLK (SMCLK)
f(ACLK)
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
3.4
7.8
51
4
10
T
= −40°C +85°C,
A
f
= f
= f
= 4096 Hz
(MCLK) (SMCLK) (ACLK)
60
T
= −40°C +85°C, f = 0 MHz,
MCLK
A
C11x
P112
f
= 1 MHz, f
= 32,768 Hz
120
70
150
85
(SMCLK)
(ACLK)
Low power mode,
(LPM0)
I
I
µA
µA
(CPUOff)
T
= −40°C +85°C, f
= 0 MHz,
= 32,768 Hz
A
(MCLK)
(ACLK)
f
= 1 MHz, f
125
170
(SMCLK)
T
= −40°C +85°C,
V
= 3 V
= 5 V
8
22
35
A
CC
CC
Low power mode, (LPM2)
Low power mode, (LPM3)
f
= f
= 0 MHz,
= 32,768 Hz, SCG0 = 0, Rsel = 3
(LPM2)
(MCLK) (SMCLK)
V
16
f
(ACLK)
T
A
= −40°C
= 25°C
= 85°C
= −40°C
= 25°C
= 85°C
= −40°C
= 25°C
= 85°C
2
1.5
1.85
6.3
5.1
5.1
0.1
0.1
0.4
2.6
2.2
2.2
8
f
f
= f
= 0 MHz,
(MCLK) (SMCLK)
T
A
V
= 3 V
= 5 V
= 32,768 Hz,
(ACLK)
SCG0 = 1
CC
CC
T
A
I
µA
µA
(LPM3)
(LPM4)
T
A
f
f
= f
(MCLK) (SMCLK)
(ACLK)
= 0 MHz,
= 32,768 Hz, SCG0 = 1
T
A
V
7
T
A
7
T
A
0.8
0.8
1
f
f
= f
= 0 MHz,
(MCLK) (SMCLK)
V
= 3 V/
5 V
CC
I
Low power mode, (LPM4)
T
A
= 0 Hz,
(ACLK)
SCG0 = 1
T
A
NOTE: All inputs are tied to V
SS
or V . Outputs do not source or sink any current.
CC
current consumption of active mode versus system frequency
= I × f [MHz]
I
AM
AM[1 MHz]
system
current consumption of active mode versus supply voltage
= I + 175 µA/V × (V −3 V)
I
AM
AM[3 V]
CC
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢆ
ꢀ ꢈ ꢉ ꢊꢋ ꢁꢈ ꢌꢍ ꢎ ꢏ ꢀꢈ ꢐ ꢑꢒꢐ ꢒꢍ ꢓꢑ ꢒꢏ ꢏꢊ ꢑꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
Schmitt-trigger inputs Port 1 to Port P2; P1.0 to P1.7, P2.0 to P2.5
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
2.1
3.4
1.5
2.3
1
UNIT
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
1.2
2.3
0.7
1.4
0.3
0.6
V
IT+
V
IT−
V
hys
Positive-going input threshold voltage
V
Negative-going input threshold voltage
V
V
Input voltage hysteresis, (V
IT+
− V )
IT−
1.4
standard inputs RST/NMI, TCK, TMS, TDI
PARAMETER
TEST CONDITIONS
= 3 V/5 V
MIN
NOM
MAX
UNIT
V
V
Low-level input voltage
High-level input voltage
V
V
+0.8
CC
IL
SS
0.7xV
SS
V
CC
V
V
IH
CC
inputs Px.x, TAx
PARAMETER
TEST CONDITIONS
VCC
MIN NOM
MAX
UNIT
3 V/ 5 V
3 V
1.5
540
270
1.5
cycle
Port P1, P2: P1.x to P2.x,
External trigger signal for the interrupt flag, (see Note 1)
t
External Interrupt timing
(int)
ns
5 V
3 V/ 5 V
3 V
cycle
540
270
t
Timer_A, capture timing TA0, TA1, TA2. (see Note 2)
(cap)
ns
5 V
NOTES: 1. The external signal sets the interrupt flag every time the minimum t cycle and time parameters are met. It may be set even with
int
trigger signals shorter than t . Both the cycle and timing specifications must be met to ensure the flag is set.
int
2. The external capture signal triggers the capture event every time when the minimum t
cycles and time parameters are met. A
cap
capture may be triggered with capture signals even shorter than t
a correct capture of the 16-bit timer value and to ensure the flag is set.
. Both the cycle and timing specifications must be met to ensure
cap
internal signals TAx, SMCLK at Timer_A
PARAMETER
Input frequency
Timer_A clock frequency
TEST CONDITIONS
VCC
3 V
MIN NOM
MAX
10
UNIT
dc
dc
dc
f
f
Internal TA0, TA1, TA2, t = t
MHz
(IN)
H
L
5 V
15
Internally, SMCLK signal applied
3 V/5 V
f
System
(TAint)
leakage current (see Note 1)
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
Port P1: P1.x, 0 ≤ × ≤ 7
(see Note 2)
V
CC
= 3 V/5 V,
50
I
High-impendance leakage current
nA
lkg(Px.x)
Port P2: P2.x, 0 ≤ × ≤ 5
(see Note 2)
V
CC
= 3 V/5 V,
50
NOTES: 1. The leakage current is measured with V
SS
or V applied to the corresponding pin(s), unless otherwise noted.
CC
2. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional
pullup or pulldown resistor.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇꢇꢆ
ꢀ ꢈꢉꢊ ꢋ ꢁꢈ ꢌ ꢍꢎꢏ ꢀ ꢈꢐꢑꢒ ꢐꢒ ꢍꢓ ꢑꢒ ꢏꢏ ꢊꢑ ꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
outputs P2x, TAx
PARAMETER
TEST CONDITIONS
VCC
MIN NOM
MAX
UNIT
f
f
P2.0/ACLK,
C
C
= 20 pF
= 20 pF
3 V/5 V
3 V/5 V
1.1
(P20)
L
Output frequency
MHz
TA0, TA1, TA2,
dc
40%
35%
50%
f
(TAx)
L
System
60%
f
f
f
= 1.1 MHz
= f
P20
65%
t
P2.0/ACLK, C = 20 pF
L
3 V/ 5 V
3 V/ 5 V
P20 XTCLK
(Xdc)
Duty cycle of O/P frequency
= f
P20 XTCLK/n
TA0, TA1, TA2,
Duty cycle = 50%
C = 20 pF,
L
t
0
50
ns
(TAdc)
outputs Port 1 to P2; P1.0 to P1.7, P2.0 to P2.5
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
I
I
I
I
= − 1.5 mA,
= − 4.5 mA,
= 1.5 mA,
V
CC
V
CC
V
CC
V
CC
= 3 V/5 V, See Note 1
V
−0.4
V
V
(OH)
(OH)
(OL)
(OL)
CC
CC
V
V
High-level output voltage
V
OH
= 3 V/5 V, See Note 2
= 3 V/5 V, See Note 1
= 3 V/5 V, See Note 2
V
-0.6
CC
CC
V
SS
V
V
+0.4
+0.6
SS
Low-level output voltage
V
OL
= 4.5 mA,
V
SS
SS
NOTES: 1. The maximum total current, I
specified.
and I , or all outputs combined, should not exceed 12 mA to hold the maximum voltage drop
OL
OH
2. The maximum total current, I
specified.
and I , or all outputs combined, should not exceed 36 mA to hold the maximum voltage drop
OL
OH
optional resistors, individually programmable with ROM code (see Note 1)
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
6.2
9.3
18
UNIT
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
R
R
R
R
R
R
R
R
R
R
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V/5 V
= 3 V/5 V
= 3 V/5 V
= 3 V/5 V
= 3 V/5 V
= 3 V/5 V
= 3 V/5 V
= 3 V/5 V
= 3 V/5 V
= 3 V/5 V
2.1
3.1
6
4.1
6.2
12
(opt1)
(opt2)
(opt3)
(opt4)
(opt5)
(opt6)
(opt7)
(opt8)
(opt9)
(opt10)
10
19
29
19
37
56
Resistors, individually programmable with ROM code, all port pins,
values applicable for pulldown and pullup
38
75
113
168
281
392
506
56
112
187
261
337
94
131
167
NOTE 1: Optional resistors R
optx
for pulldown or pullup are not programmed in standard OTP or EPROM devices MSP430P112 or PMS430E112.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢆ
ꢀ ꢈ ꢉ ꢊꢋ ꢁꢈ ꢌꢍ ꢎ ꢏ ꢀꢈ ꢐ ꢑꢒꢐ ꢒꢍ ꢓꢑ ꢒꢏ ꢏꢊ ꢑꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
PUC/POR
PARAMETER
POR
TEST CONDITIONS
MIN NOM
MAX
250
2.4
UNIT
t
150
µs
(POR_Delay)
T
= −40°C
= 25°C
= 85°C
1.5
1.2
0.9
0
V
V
A
V
T
A
2.1
POR
V
CC
= 3 V/5 V
T
A
1.8
V
V
0.4
V
(min)
t
PUC/POR
Reset is accepted internally
2
µs
(reset)
V
VCC
V
POR
No POR
POR
POR
V
(min)
t
Figure 3. Power-On Reset (POR) vs Supply Voltage
3
2.4
2.5
2.1
1.8
0.9
2
1.5
1.5
1
1.2
0.5
25°C
0
−40
−20
0
20
40
60
80
Temperature [°C]
Figure 4. V
vs Temperature
POR
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇꢇꢆ
ꢀ ꢈꢉꢊ ꢋ ꢁꢈ ꢌ ꢍꢎꢏ ꢀ ꢈꢐꢑꢒ ꢐꢒ ꢍꢓ ꢑꢒ ꢏꢏ ꢊꢑ ꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
wake-up from lower power modes (LPMx)
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
t
t
(LPM0)/
(LPM2)
V
= 3 V/5 V
100
ns
CC
Delay time
t
R
R
= 4, DCO = 3, MOD = 0
V
V
= 3 V/5 V
= 3 V/5 V
2.6
2.8
6
6
µs
µs
(LPM3)
(LPM4)
Sel
Sel
CC
t
= 4, DCO = 3, MOD = 0
CC
RAM
PARAMETER
MIN NOM
1.8
MAX
UNIT
V
CPU halted (see Note 1)
V
(RAMh)
NOTE 1: This parameter defines the minimum supply voltage V
when the data in the program memory RAM remains unchanged. No program
CC
execution should happen during this supply voltage condition.
DCO (MSP430P112)
PARAMETER
TEST CONDITIONS
MIN
NOM
0.12
0.13
0.19
0.21
0.31
0.34
0.5
MAX
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
f
f
f
R
R
R
= 0, DCO = 3, MOD = 0, DCOR = 0,
= 1, DCO = 3, MOD = 0, DCOR = 0,
= 2, DCO = 3, MOD = 0, DCOR = 0,
T
A
= 25°C
= 25°C
= 25°C
MHz
(DCO03)
(DCO13)
(DCO23)
sel
sel
sel
T
A
MHz
MHz
T
A
f
f
f
f
f
f
R
R
R
R
R
R
= 3, DCO = 3, MOD = 0, DCOR = 0,
= 4, DCO = 3, MOD = 0, DCOR = 0,
= 5, DCO = 3, MOD = 0, DCOR = 0,
= 6, DCO = 3, MOD = 0, DCOR = 0,
= 7, DCO = 3, MOD = 0, DCOR = 0,
= 4, DCO = 7, MOD = 0, DCOR = 0,
T
A
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
MHz
MHz
MHz
MHz
MHz
MHz
ratio
(DCO33)
(DCO43)
(DCO53)
(DCO63)
(DCO73)
(DCO47)
sel
sel
sel
sel
sel
sel
0.55
0.8
0.5
0.6
0.9
1.1
1.7
2.1
2.8
3.8
1.1
1.2
1.55
1.7
2.3
2.7
3.5
4.5
T
A
0.9
1.2
T
A
1.4
2
T
A
2.4
3.1
T
A
4.2
F
F
F
DCO40
x1.8
DCO40
x2.2
DCO40
x2.6
T
A
V
CC
= 3 V/5 V
S
S
S
S
= f
/f
V
CC
V
CC
V
CC
V
CC
= 3 V/5 V
= 3 V/5 V
= 3 V
1.4
1.07
1.65
1.12
1.9
1.16
(Rsel)
R
Rsel+1 Rsel
= f /f
(DCO)
DCO DCO+1 DCO
−0.31
−0.33
−0.36
−0.38
−0.40
−0.43
Temperature drift, R
sel
MOD = 0 (see Note 1)
= 4, DCO = 3,
D
D
%/°C
t
= 5 V
Drift with V variation, R
MOD = 0 (see Note 1)
= 4, DCO = 3,
CC sel
V
CC
= 3 V to 5 V
0
5
10
%/V
V
NOTE 1: These parameters are not production tested.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢆ
ꢀ ꢈ ꢉ ꢊꢋ ꢁꢈ ꢌꢍ ꢎ ꢏ ꢀꢈ ꢐ ꢑꢒꢐ ꢒꢍ ꢓꢑ ꢒꢏ ꢏꢊ ꢑꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
DCO (MSP430C111, C112)
PARAMETER
TEST CONDITIONS
MIN
0.04
0.04
0.08
0.08
0.15
0.15
0.26
0.26
0.4
NOM
0.07
0.07
0.13
0.13
0.22
0.22
0.36
0.36
0.6
MAX
0.10
0.10
0.18
0.18
0.30
0.30
0.47
0.47
0.8
UNIT
V
V
V
V
V
V
V
V
V
V
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
f
f
f
R
R
R
= 0, DCO = 3, MOD = 0, DCOR = 0,
= 1, DCO = 3, MOD = 0, DCOR = 0,
= 2, DCO = 3, MOD = 0, DCOR = 0,
T
A
= 25°C
= 25°C
= 25°C
MHz
(DCO03)
(DCO13)
(DCO23)
sel
sel
sel
T
A
MHz
MHz
T
A
f
f
f
f
f
f
R
R
R
R
R
R
= 3, DCO = 3, MOD = 0, DCOR = 0,
= 4, DCO = 3, MOD = 0, DCOR = 0,
= 5, DCO = 3, MOD = 0, DCOR = 0,
= 6, DCO = 3, MOD = 0, DCOR = 0,
= 7, DCO = 3, MOD = 0, DCOR = 0,
= 4, DCO = 7, MOD = 0, DCOR = 0,
T
A
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
MHz
MHz
MHz
MHz
MHz
MHz
ratio
(DCO33)
(DCO43)
(DCO53)
(DCO63)
(DCO73)
(DCO47)
sel
sel
sel
sel
sel
sel
T
A
0.4
0.6
0.8
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
0.8
0.8
1.3
1.5
2.4
3.1
1.1
1.1
1.7
1.9
2.9
3.8
1.4
1.4
2.1
2.3
3.4
4.5
T
A
T
A
T
A
F
F
F
DCO40
x1.8
DCO40
x2.2
DCO40
x2.6
T
A
V
CC
= 3 V/5 V
S
S
S
S
= f
/f
V
CC
V
CC
V
CC
V
CC
= 3 V/5 V
= 3 V/5 V
= 3 V
1.4
1.07
1.65
1.12
1.9
1.16
(Rsel)
R
Rsel+1 Rsel
= f /f
(DCO)
DCO DCO+1 DCO
−0.31
−0.33
−0.36
−0.38
−0.40
−0.43
Temperature drift, R
sel
MOD = 0 (see Note 1)
= 4, DCO = 3,
D
D
%/°C
t
= 5 V
Drift with V variation, R
MOD = 0 (see Note 1)
= 4, DCO = 3,
CC sel
V
CC
= 3 V to 5 V
0
5
10
%/V
V
NOTE 1: These parameters are not production tested.
Max
f
f
(DCOx7)
(DCOx0)
Min
Max
Min
0
1
2
3
4
5
6
7
3
5
V
CC
DCO Steps
Figure 5. DCO Characteristics
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇꢇꢆ
ꢀ ꢈꢉꢊ ꢋ ꢁꢈ ꢌ ꢍꢎꢏ ꢀ ꢈꢐꢑꢒ ꢐꢒ ꢍꢓ ꢑꢒ ꢏꢏ ꢊꢑ ꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
main DCO characteristics
D
Individual devices have a minimum and maximum operation frequency. The specified parameters for
to f are valid for all devices.
f
DCOx0)
DCOx7)
(
(
D
D
D
All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps Rsel1, ... Rsel6 overlaps Rsel7.
DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter S
.
DCO
Modulation control bits MOD0 to MOD4 select how often f
is used within the period of 32 DCOCLK
DCO+1)
(
cycles. The frequency f
is used for the remaining cycles. The frequency is an average equal to:
(DCO)
32 f(DCO) f(DCO)1)
faverage
+
MOD f(DCO))(32*MOD) f(DCO)1)
crystal oscillator, XIN, XOUT
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
pF
C
C
Capacitance at input
Capacitance at output
V
V
= 3 V/5 V
= 3 V/5 V
12
12
XIN
CC
pF
XOUT
CC
V
V
V
0.2×V
IL
SS
CC
Input levels at XIN
V
CC
= 3 V/5 V (see Note 2)
V
0.8×V
V
CC
IH
CC
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢆ
ꢀ ꢈ ꢉ ꢊꢋ ꢁꢈ ꢌꢍ ꢎ ꢏ ꢀꢈ ꢐ ꢑꢒꢐ ꢒꢍ ꢓꢑ ꢒꢏ ꢏꢊ ꢑꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
EPROM Memory, P- and E- versions only (see Note 1)
TEST
CONDITIONS
PARAMETER
V
CC
MIN NOM
MAX
UNIT
V
Programming voltage, applied to TEST/VPP
Current from programming voltage source
Programming time, single pulse
Programming time, fast algorithm
Number of pulses for successful programming
Erase time:
12
5
12.5
13
70
V
(PP)
(PP)
(pps)
(ppf)
I
t
t
mA
ms
µs
100
P
(n)
4
100 Pulse
2
Wave length 2537 Å at 15 Ws/cm
30
min
2
(UV lamp of 12 mW/ cm )
t
(erase)
Write/erase cycles
1000
10
cycles
Year
Data retention Tj < 55°C
NOTES: 1. Refer to the Recommended Operating Conditions for the correct V
during programming.
CC
JTAG Interface
TEST
CONDITIONS
PARAMETER
V
CC
MIN NOM
MAX
UNIT
3 V
5 V
DC
DC
5
f
TCK input frequency
see Note 1
MHz
TCK
10
NOTES: 1. f
may be restricted to meet the timing requirements of the module selected.
TCK
JTAG Fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
V
CC
MIN NOM
MAX
UNIT
Fuse blow voltage, C versions (see Note 2)
Fuse blow voltage, E/P versions (see Note 2)
Supply current into TEST/VPP during fuse blow
Time to blow fuse
3 V/ 5 V
3 V/ 5 V
5.5
11
6
13
V
V
FB
I
t
100
1
mA
ms
FB
FB
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
2. The fuse blow voltage is applied to the TEST/VPP pin.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇꢇꢆ
ꢀ ꢈꢉꢊ ꢋ ꢁꢈ ꢌ ꢍꢎꢏ ꢀ ꢈꢐꢑꢒ ꢐꢒ ꢍꢓ ꢑꢒ ꢏꢏ ꢊꢑ ꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic
Port P1, P1.0 to P1.3, input/output with Schmitt-trigger
V
CC
P1SEL.x
0
(See Note 1)
(See Note 2)
P1DIR.x
1
0
Direction Control
From Module
Pad Logic
P1.0 − P1.3
P1OUT.x
1
Module X OUT
(See Note 2)
(See Note 1)
P1IN.x
GND
EN
D
Module X IN
P1IRQ.x
P1IE.x
Interrupt
Edge
Select
EN
Q
P1IFG.x
Set
Interrupt
Flag
P1IES.x
P1SEL.x
NOTE: x = Bit Identifier, 0 to 3 For Port P1
Dir. Control
Module X
OUT
Module X
PnSel.x
PnDIR.x
PnOUT.x
PnIN.x
PnIE.x
PnIFG.x
PnIES.x
from module
P1DIR.0
P1DIR.1
P1DIR.2
P1DIR.3
IN
†
P1Sel.0
P1Sel.1
P1Sel.2
P1Sel.3
P1DIR.0
P1DIR.1
P1DIR.2
P1DIR.3
P1OUT.0
P1OUT.1
P1OUT.2
P1OUT.3
V
SS
P1IN.0
P1IN.1
P1IN.2
P1IN.3
TACLK
P1IE.0
P1IE.1
P1IE.2
P1IE.3
P1IFG.0
P1IFG.1
P1IFG.2
P1IFG.3
P1IES.0
P1IES.1
P1IES.2
P1IES.3
†
†
†
†
†
†
Out0 signal
Out1 signal
Out2 signal
CCI0A
CCI1A
CCI2A
†
Signal from or to Timer_A
NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions.
2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory.
V
CC
(see Note 1)
(see Note 2)
(see Note 2)
(see Note 1)
GND
CMOS INPUT (RST/NMI)
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢆ
ꢀ ꢈ ꢉ ꢊꢋ ꢁꢈ ꢌꢍ ꢎ ꢏ ꢀꢈ ꢐ ꢑꢒꢐ ꢒꢍ ꢓꢑ ꢒꢏ ꢏꢊ ꢑꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features
V
CC
P1SEL.x
P1DIR.x
0
1
See Note 1
See Note 2
Direction Control
From Module
P1OUT.x
0
1
Pad Logic
P1.4−P1.7
Module X OUT
See Note 2
See Note 1
GND
Bus Keeper
TS
T
P1IN.x
EN
D
Module X IN
TEST/VPP
TST
Fuse
P1IRQ.x
P1IE.x
Interrupt
Edge
Select
60 kΩ
VPP_Internal
EN
Q
Typical
P1IFG.x
Set
GND
Fuse
Blow
T
Control
Interrupt
Flag
Control By JTAG
P1IES.x
P1SEL.x
P1.x
TDO
Controlled By JTAG
P1.7/TDI/TDO
P1.x
Controlled by JTAG
NOTES:The test pin should be protected from potential EMI and
ESD voltage spikes. This may require a smaller
external pulldown resistor in some applications.
TDI
TST
TST
P1.6/TDI
P1.x
x = Bit identifier, 4 to 7 for port P1
During programming activity and during blowing the
fuse, the pin TDO/TDI is used to apply the test input
for JTAG circuitry.
TMS
P1.5/TMS
P1.x
TST
TCK
P1.4/TCK
Dir. Control
from module
Module X
OUT
Module X
IN
PnSel.x
PnDIR.x
PnOUT.x
PnIN.x
PnIE.x
PnIFG.x
PnIES.x
P1Sel.4
P1Sel.5
P1Sel.6
P1Sel.7
P1DIR.4
P1DIR.5
P1DIR.6
P1DIR.7
P1DIR.4
P1DIR.5
P1DIR.6
P1DIR.7
P1OUT.4
P1OUT.5
P1OUT.6
P1OUT.7
SMCLK
P1IN.4
P1IN.5
P1IN.6
P1IN.7
unused
unused
unused
unused
P1IE.4
P1IE.5
P1IE.6
P1IE.7
P1IFG.4
P1IFG.5
P1IFG.6
P1IFG.7
P1IES.4
P1IES.5
P1IES.6
P1IES.7
†
†
†
Out0 signal
Out1 signal
Out2 signal
†
Signal from or to Timer_A
NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions.
2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory.
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇꢇꢆ
ꢀ ꢈꢉꢊ ꢋ ꢁꢈ ꢌ ꢍꢎꢏ ꢀ ꢈꢐꢑꢒ ꢐꢒ ꢍꢓ ꢑꢒ ꢏꢏ ꢊꢑ ꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
Port P2, P2.0 to P2.4, input/output with Schmitt-trigger
P2SEL.x
V
CC
0
P2DIR.x
0: Input
See Note 1
See Note 2
1
Direction Control
From Module
1: Output
Pad Logic
0
1
P2.0 − P2.4
P2OUT.x
Module X OUT
See Note 2
See Note 1
P2IN.x
EN
GND
D
Module X IN
P2IRQ.x
P2IE.x
Interrupt
Edge
Select
EN
Q
P2IFG.x
Set
Interrupt
Flag
P2IES.x
P2SEL.x
NOTE: x = Bit Identifier, 0 to 4 For Port P2
Dir. Control
Module X
OUT
Module X
PnSel.x
PnDIR.x
PnOUT.x
PnIN.x
PnIE.x
PnIFG.x
PnIES.x
from module
P2DIR.0
P2DIR.1
P2DIR.2
P2DIR.3
P2DIR.4
IN
P2Sel.0
P2Sel.1
P2Sel.2
P2Sel.3
P2Sel.4
P2DIR.0
P2DIR.1
P2DIR.2
P2DIR.3
P2DIR.4
P2OUT.0
P2OUT.1
P2OUT.2
P2OUT.3
P2OUT.4
ACLK
P2IN.0
P2IN.1
P2IN.2
P2IN.3
P2IN.4
unused
P2IE.0
P2IE.1
P2IE.2
P2IE.3
P2IE.4
P2IFG.0
P2IFG.1
P2IFG.2
P2IFG.3
P2IFG.4
P1IES.0
P1IES.1
P1IES.2
P1IES.3
P1IES.4
†
†
†
V
SS
INCLK
CCI0B
CCI1B
†
†
†
Out0 signal
Out1 signal
Out2 signal
unused
†
Signal from or to Timer_A
NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions.
2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory.
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢆ
ꢀ ꢈ ꢉ ꢊꢋ ꢁꢈ ꢌꢍ ꢎ ꢏ ꢀꢈ ꢐ ꢑꢒꢐ ꢒꢍ ꢓꢑ ꢒꢏ ꢏꢊ ꢑꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
Port P2, P2.5, input/output with Schmitt-trigger and R
function for the Basic Clock module
OSC
V
CC
P2SEL.5
0: Input
Pad Logic
0
1: Output
P2DIR.5
See Note 1
1
Direction Control
From Module
See Note 2
0
1
P2.5
P2OUT.5
Module X OUT
See Note 2
See Note 1
GND
Bus Keeper
P2IN.5
EN
D
Internal to
Basic Clock
Module X IN
Module
1
0
V
CC
P2IRQ.5
P2IE.5
Interrupt
Edge
Select
EN
Q
P2IFG.5
Set
DC
Generator
Interrupt
Flag
P2IES.5
DCOR
P2SEL.5
NOTE: DCOR: Control bit from basic clock module if it is set, P2.5 is disconnected from P2.5 pad
Director
Module X
OUT
Module X
IN
PnSel.x
PnDIR.x Control from
module
PnOUT.x
PnIN.x
PnIE.x
P2IE.5
PnIFG.x
P2IFG.5
PnIES.x
P2IES.5
P2Sel.5
P2DIR.5
P2DIR.5
P2OUT.5
V
SS
P2IN.5
unused
NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions.
2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory.
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇꢇꢆ
ꢀ ꢈꢉꢊ ꢋ ꢁꢈ ꢌ ꢍꢎꢏ ꢀ ꢈꢐꢑꢒ ꢐꢒ ꢍꢓ ꢑꢒ ꢏꢏ ꢊꢑ ꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
Port P2, un-bonded bits P2.6 and P2.7
P2SEL.x
P2DIR.x
0: Input
1: Output
0
1
Direction Control
From Module
0
1
P2OUT.x
Module X OUT
P2IN.x
Node Is Reset With PUC
Bus Keeper
EN
Module X IN
D
P2IRQ.x
P2IE.x
PUC
Interrupt
Edge
Select
EN
Set
Q
P2IFG.x
Interrupt
Flag
P2IES.x
P2SEL.x
NOTE: x = Bit identifier, 6 to 7 for Port P2 without external pins
Dir. Control
from module
Module X
OUT
Module X
IN
P2Sel.x
P2DIR.x
P2OUT.x
P2IN.x
P2IE.x
P2IFG.x
P2IES.x
P2Sel.6
P2Sel.7
P2DIR.6
P2DIR.7
P2DIR.6
P2DIR.7
P2OUT.6
P2OUT.7
V
V
P2IN.6
P2IN.7
unused
unused
P2IE.6
P2IE.7
P2IFG.6
P2IFG.7
P2IES.6
P2IES.7
SS
SS
NOTE: A good use of the unbonded bits 6 and 7 of port P2 is to use the interrupt flags. The interrupt flags can not be influenced from any signal
other than from software. They work then as soft interrupt.
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢆ
ꢀ ꢈ ꢉ ꢊꢋ ꢁꢈ ꢌꢍ ꢎ ꢏ ꢀꢈ ꢐ ꢑꢒꢐ ꢒꢍ ꢓꢑ ꢒꢏ ꢏꢊ ꢑꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
JTAG fuse check mode
MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of
the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, I , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care
TF
must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
When the TEST pin is taken back low after a test or programming session, the fuse check mode and sense
currents are terminated.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS
is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode.
After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse
check mode has the potential to be activated.
The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see
Figure 6). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
I
TF
I
TEST
Figure 6. Fuse Check Mode Current, MSP430x11x
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇꢇꢆ
ꢀ ꢈꢉꢊ ꢋ ꢁꢈ ꢌ ꢍꢎꢏ ꢀ ꢈꢐꢑꢒ ꢐꢒ ꢍꢓ ꢑꢒ ꢏꢏ ꢊꢑ ꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PIN SHOWN
0.050 (1,27)
16
0.020 (0,51)
0.010 (0,25)
M
0.014 (0,35)
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.293 (7,45)
Gage Plane
0.010 (0,25)
1
8
0°−ā8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
PINS **
16
20
24
0.610
DIM
0.410
0.510
A MAX
(10,41) (12,95) (15,49)
0.400
0.500
0.600
A MIN
(10,16) (12,70) (15,24)
4040000/D 02/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢆ
ꢀ ꢈ ꢉ ꢊꢋ ꢁꢈ ꢌꢍ ꢎ ꢏ ꢀꢈ ꢐ ꢑꢒꢐ ꢒꢍ ꢓꢑ ꢒꢏ ꢏꢊ ꢑꢁ
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
MSP430C111IDW, MSP430C112IDW, MSP430P112IDW pin out
DW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TEST/VPP
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI
P1.5/TA0/TMS
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
P2.4/TA2
P2.3/TA1
V
CC
P2.5/R
OSC
SS
V
XOUT/TCLK
XIN
RST/NMI
P2.0/ACLK
P2.1/INCLK
P2.2/TA0
PMS430E112 pin out
JL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TEST/VPP
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI
P1.5/TA0/PMS
P1.4/SMCLK/TCK
P1.3/TA2
V
CC
P2.5/R
OSC
V
SS
XOUT/TCLK
XIN
P1.2/TA1
RST/NMI
P2.0/ACLK
P2.1/INCLK
P2.2/TA0
P1.1/TA0
P1.0/TACLK
P2.4/TA2
P2.3/TA1
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-May-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
MSP-EVK430A110
MSP430C111IDW
MSP430P112AY
MSP430P112IDW
OBSOLETE
OBSOLETE
0
20
0
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
SOIC
DW
Y
OBSOLETE DIESALE
ACTIVE
SOIC
DW
20
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PMS430E112JL
OBSOLETE
CDIP
JL
20
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCER003A – JANUARY 1997
JL (R-GDIP-T20)
CERAMIC DUAL-IN-LINE PACKAGE
0.975 (24,76)
0.930 (23,62)
11
20
0.300 (7,62)
0.245 (6,22)
1
10
0.050 (1,27)
0.015 (0,38)
Window
0.050 (1,27)
0.015 (0,38)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040109/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only
E. Falls within MIL-STD-1835 GDIP1-T20
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
www.ti.com/industrial
www.ti.com/medical
www.ti.com/security
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
Medical
Security
Logic
Space, Avionics and Defense www.ti.com/space-avionics-defense
Power Mgmt
power.ti.com
Transportation and
Automotive
www.ti.com/automotive
Microcontrollers
RFID
microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
Wireless
www.ti.com/video
www.ti.com/wireless-apps
RF/IF and ZigBee® Solutions www.ti.com/lprf
TI E2E Community Home Page
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2011, Texas Instruments Incorporated
相关型号:
©2020 ICPDF网 联系我们和版权申明