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MSP432E401Y

ZHCSH09 –OCTOBER 2017

MSP432E401Y SimpleLink™ 以太网微控制器

1 器件概述

1.1 特性

1

• 内核

• 安全性

– 120MHz ARM^®Cortex^®- 具有浮点运算单元

(FPU) 的 M4F 处理器内核

– 高级加密标准 (AES)：基于 128、192 和 256 位

密钥的硬件加速数据加密和解密

• 连接

– 数据加密标准 (DES)：具有 168 位有效密钥长度

并且支持块密码实施的硬件加速数据加密和解密

– 以太网 MAC：具有集成以太网 PHY 的 10/100

以太网 MAC

– 安全哈希算法/消息摘要算法 (SHA/MD5)：支持

SHA-1、SHA-2 和 MD5 哈希计算的高级哈希引

擎

– 以太网 PHY：具有 IEEE 1588 PTP 硬件支持的

PHY

– 循环冗余校验 (CRC) 硬件

– 篡改：支持四个篡改输入和可配置篡改事件响应

• 模拟

– 通用串行总线 (USB)：具有 ULPI 接口选项和链

路层电源管理 (LPM) 的 USB 2.0 OTG、主机或

器件

– 8 个通用异步接收器/发射器 (UART)，每个具有

独立计时的发送器和接收器

– 2 个基于 12 位 SAR 的 ADC 模块，每个模块支

持高达 200 万次/秒的采样率 (2Msps)

– 4 个四通道同步串行接口 (QSSI)：提供双通道、

四通道和高级 SSI 支持

– 3 个独立的模拟比较器控制器

– 16 个数字比较器

• 系统管理

– 提供高速模式支持的 10 个内部集成电路 (I²C) 模

块

– JTAG 和串行线调试 (SWD)：一个具有集成

ARM SWD 的 JTAG 模块提供访问和控制测试设

计特性的途径，如 I/O 引脚监督和控制、扫描测

试和调试。

– 2 个 CAN 2.0 A 和 B 控制器：多播共享串行总线

标准

• 存储器

– 具有 4 个存储体的 1024KB 闪存存储器配置支持

对每个存储体提供独立代码保护

• 开发套件和软件（请参阅工具和软件）

– SimpleLink™MSP-EXP432E401Y LaunchPad™

开发套件

– 具有单周期访问的 256KB SRAM 以 120MHz 时

钟频率提供近 2GB/s 的内存带宽

– 6KB EEPROM：每 2 个页块写入 500k、矫正、

锁定保护

– SimpleLink MSP432E4 软件开发套件 (SDK)

• 封装信息

– 封装：128 引脚 TQFP (PDT)

– 扩展工作温度（环境）范围：–40°C 至 105°C

– 内部 ROM：搭载有 SimpleLink™SDK 软件

– 外设驱动程序库

– 引导加载程序

– 外部外设接口 (EPI)：8、16 或 32 位专用并行接

口访问外部器件和存储器（SDRAM、闪存或

SRAM）

1.2 应用

•

工业以太网网关

工业智能网关

适用于楼宇自动化的区域控制器

工厂自动化数据收集器和网关

面向电网基础设施的数据集中器

无线转以太网网关

1.3 说明

SimpleLink MSP432E401Y ARM^®Cortex^®-M4F 微控制器具有顶级性能和高级集成功能。该产品系列用于

需要强大的控制处理和连接功能且具有成本效益的应用。

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLASEN5

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

MSP432E401Y 微控制器集成了大量丰富的通信特性，以实现全新的高度互连设计，在性能和功耗之间实

现重要的实时控制。这些微控制器具有集成式通信外设以及其他高性能的模拟和数字功能，为开发从人机界

面 (HMI) 到联网系统管理控制器在内的许多不同目标应用奠定了坚实的基础。

此外，MSP432E401Y 微控制器为基于 ARM 的微控制器提供了诸多优势，如广泛可用的开发工具、片上系

统 (SoC) 基础架构，以及一个庞大的用户社区。另外，这些微控制器使用 ARM Thumb^®兼容的 Thumb-2^®

指令集来减少内存要求，并以此达到降低成本的目的。当使用 SimpleLink MSP432™SDK

时，MSP432E401Y 与 SimpleLink 系列的所有成员的代码兼容，因此使用灵活，可满足各类具体需求。

MSP432E401Y 器件是 SimpleLink 微控制器 (MCU) 平台的一部分，该平台包含 Wi-Fi^®、低功耗 Bluetooth

^®、低于 1GHz、以太网、Zigbee、线程和主机 MCU，它们均共用一个通用、简单易用的开发环境，其中包

含单核软件开发套件 (SDK) 和丰富的工具集。借助一次性集成的 SimpleLink 平台，可以将产品组合中的任

何器件组合添加至您的设计中，从而在设计要求变更时实现 100% 代码重用。更多详细信息，请访问

www.ti.com/simplelink。

Device Information⁽¹⁾

PART NUMBER

MSP432E401YTPDT

PACKAGE

封装尺寸

TQFP (128)

14mm x 14mm

(1) 更多信息，请参见节 9，机械、封装和可订购产品信息。

2

器件概述

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

1.4 功能框图

图 1-1 给出了功能框图。

JTAG, SWD

Arm

Cortex-M4F

Bootloader

ROM

DriverLib

(120 MHz)

AES and CRC

Ethernet Bootloater

System

Control and

Clocks

(with Precision

Oscillator)

Flash

ETM

FPU

DCode bus

ICode bus

(1024KB)

NVIC

MPU

System Bus

SRAM

(256KB)

Bus Matrix

SYSTEM PERIPHERALS

Watchdog

Timer

(2 Units)

DMA

Hibernation

Module

EEPROM

(6K)

Tamper

General-

Purpose

Timer (8 Units)

GPIOs

(90)

External

Peripheral

Interface

CRC

Module

DES

Module

AES

Module

SHA/MD5

Module

SERIAL PERIPHERALS

USB OTG

(FS PHY

or ULPI)

UART

(8 Units)

SSI

(4 Units)

I2C

(10 Units)

CAN

Controller

(2 Units)

Ethernet

MAC, PHY, MII

ANALOG PERIPHERALS

12-Bit ADC

(2 Units,

20 Channels)

Analog

Comparator

(3 Units)

MOTION CONTROL PERIPHERALS

PWM

(1 Unit,

8 Signals)

QEI

(1 Unit)

图 1-1. MSP432E401Y 功能方框图

器件概述

3

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

内容

1

器件概述.................................................... 1

1.1 特性 ................................................... 1

1.2 应用 ................................................... 1

1.3 说明 ................................................... 1

1.4 功能框图 .............................................. 3

Revision History ......................................... 5

Device Characteristics.................................. 6

3.1 Related Products ..................................... 7

Terminal Configuration and Functions.............. 8

4.1 Pin Diagram .......................................... 8

4.2 Pin Attributes ......................................... 9

4.3 Signal Descriptions.................................. 19

4.4 GPIO Pin Multiplexing............................... 30

4.5 Buffer Type.......................................... 33

4.6 Connections for Unused Pins ....................... 33

Specifications ........................................... 35

5.1 Absolute Maximum Ratings......................... 35

5.2 ESD Ratings ........................................ 35

5.3 Recommended Operating Conditions............... 35

5.11 Peripheral Current Consumption.................... 41

5.12 LDO Regulator Characteristics...................... 41

5.13 Power Dissipation ................................... 42

5.14 Thermal Resistance Characteristics, 128-Pin PDT

(TQFP) Package .................................... 42

5.15 Timing and Switching Characteristics ............... 43

Detailed Description ................................... 94

6.1 Overview ............................................ 94

6.2 Functional Block Diagram........................... 95

6.3 Arm Cortex-M4F Processor Core ................... 96

6.4 On-Chip Memory................................... 100

6.5 Peripherals ......................................... 102

6.6 Identification........................................ 144

6.7 Boot Modes ........................................ 144

Applications, Implementation, and Layout ...... 146

7.1 System Design Guidelines......................... 146

器件和文档支持......................................... 147

8.1 入门和后续步骤 .................................... 147

8.2 器件命名规则....................................... 147

8.3 工具和软件 ......................................... 148

8.4 文档支持 ........................................... 149

8.5 Community Resources............................. 150

8.6 商标 ................................................ 150

8.7 静电放电警告....................................... 150

8.8 出口管制提示....................................... 150

8.9 术语表.............................................. 150

机械、封装和可订购信息 .............................. 151

2

3

6

4

7

8

5

5.4

5.5

5.6

Recommended DC Operating Conditions .......... 35

Recommended GPIO Operating Characteristics ... 35

Recommended Fast GPIO Pad Operating

Conditions ........................................... 36

Recommended Slow GPIO Pad Operating

5.7

Conditions ........................................... 36

5.8 GPIO Current Restrictions .......................... 37

5.9 I/O Reliability ........................................ 37

5.10 Current Consumption ............................... 38

9

4

内容

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

2 Revision History

注：之前版本的页码可能与当前版本有所不同。

DATE

REVISION

NOTES

2017 年 10 月

*

初始发行版

Revision History

5

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

3 Device Characteristics

表 3-1 lists the characteristics of the MSP432E401Y MCU.

表 3-1. Device Characteristics

Feature

Description

Performance

Core

Arm Cortex-M4F processor core

Performance

120-MHz operation, 150-DMIPS performance

1024KB of flash memory

Flash

System SRAM

256KB of single-cycle system SRAM

6KB of EEPROM

EEPROM

Internal ROM

Internal ROM loaded with SimpleLink SDK software

8-, 16-, or 32-bit dedicated interface for peripherals and memory

External Peripheral Interface (EPI)

Security

Cyclical Redundancy Check (CRC)

16- or 32-bit hash function that supports four CRC forms

Hardware accelerated data encryption and decryption based on 128-, 192-, and 256-bit

keys

Advanced Encryption Standard (AES)

Data Encryption Standard (DES)

Hardware Accelerated Hash (SHA/MD5)

Tamper

Block cipher implementation with 168-bit effective key length

Advanced hash engine that supports SHA-1, SHA-2, or MD5 hash computation

Support for four tamper inputs and configurable tamper event response

Communication Interfaces

Universal Asynchronous Receiver/Transmitter

(UART)

Eight UARTs

Quad Synchronous Serial Interface (QSSI)

Inter-Integrated Circuit (I²C)

Controller Area Network (CAN)

Ethernet MAC

Four SSI modules with bi-, quad-, and advanced-SSI support

Ten I²C modules with four transmission speeds including high-speed mode

Two CAN 2.0 A/B controllers

10/100 Ethernet MAC

Ethernet PHY

PHY with IEEE 1588 PTP hardware support

USB 2.0 OTG, Host, and Device with ULPI interface option and Link Power

Management (LPM) support

Universal Serial Bus (USB)

System Integration

Micro Direct Memory Access (µDMA)

General-Purpose Timer (GPTM)

Watchdog Timer (WDT)

Arm PrimeCell^®32-channel configurable µDMA controller

Eight 16- or 32-bit GPTM blocks

Two watchdog timers

Hibernation Module (HIB)

Low-power battery-backed Hibernation module

15 physical GPIO blocks

General-Purpose Input/Output (GPIO)

Advanced Motion Control

One PWM module, with four PWM generator blocks and a control block, for a total of 8

PWM outputs

Pulse Width Modulator (PWM)

Quadrature Encoder Interface (QEI)

Analog Support

One QEI module

Analog-to-Digital Converter (ADC)

Analog Comparator Controller

Digital Comparator

Two 12-bit ADC modules, each with a maximum sample rate of 2 Msps

Three independent integrated analog comparators

16 digital comparators

System Management

JTAG and Serial Wire Debug (SWD)

Package Information

One JTAG module with integrated Arm SWD

Package

128-pin TQFP (PDT)

Operating Range (Ambient)

Extended temperature range (–40°C to 105°C)

6

Device Characteristics

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

Products for TI Microcontrollers Low-power and high-performance MCUs, with wired and wireless

connectivity options.

Products for SimpleLink MSP432 MCUs SimpleLink MSP432 MCUs with an ultra-low-power Arm

Cortex-M4 core are optimized for Internet-of-Things sensor node applications. With an

integrated ADC, the family enables acquisition and processing of high-precision signals

without sacrificing power and is an optimal host MCU for TI's SimpleLink wireless

connectivity solutions.

Companion Products for MSP432E401Y Review products that are frequently purchased or used with

this product.

Reference Designs The TI Designs Reference Design Library is a robust reference design library that

spans analog, embedded processor, and connectivity. Created by TI experts to help you

jump start your system design, all TI Designs include schematic or block diagrams, BOMs,

and design files to speed your time to market.

Device Characteristics

7

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

4 Terminal Configuration and Functions

4.1 Pin Diagram

图 4-1 shows the pinout of the 128-pin TQFP (PDT) package.

Each GPIO signal is identified by its GPIO port unless it defaults to an alternate function on reset. In this

case, the GPIO port name is followed by the default alternate function. For a complete list of functions for

each pin, see 表 4-2.

PD0

PD1

1

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

PB1

2

PB0

PD2

3

PL6

PD3

4

PL7

PQ0

PQ1

VDD

VDDA

VREFA+

GNDA

PQ2

PE3

5

PB3

6

PB2

7

VDD

OSC1

OSC0

VDDC

PL5

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

PL4

PE2

PL3

PE1

PL2

PE0

PL1

VDD

GND

PK0

PL0

GND

VDD

PM0

PM1

PM2

PM3

PM4

PM5

PM6

PM7

RST

VDD

VBAT

XOSC1

XOSC0

HIB

PK1

PK2

PK3

PC7

PC6

PC5

PC4

VDD

PQ3

VDD

PH0

PH1

PH2

PH3

图 4-1. 128-Pin PDT Package (Top View)

8

Terminal Configuration and Functions

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

4.2 Pin Attributes

表 4-1 lists GPIO pins with special considerations. Most GPIO pins are configured as GPIOs and are high-

impedance by default (GPIOAFSEL = 0, GPIODEN = 0, GPIOPDR = 0, GPIOPUR = 0, and GPIOPCTL =

0). Special consideration pins may be programed to a non-GPIO function or may have special commit

controls out of reset. In addition, a POR returns these GPIOs to their original special consideration state.

表 4-1. GPIO Pins With Special Considerations

DEFAULT

GPIO PINS

GPIOAFSEL

GPIODEN

GPIOPDR

GPIOPUR

GPIOPCTL

GPIOCR

RESET STATE

JTAG/SWD

GPIO⁽¹⁾

PC[3:0]

PD[7]

1

0

1

0

1

0

0x1

0x0

0

PE[7]

GPIO⁽¹⁾

(1) This pin is configured as a GPIO by default but is locked and can only be reprogrammed by unlocking the pin in the GPIOLOCK register

and uncommitting it by setting the GPIOCR register.

表 4-2 describes the pin attributes.

表 4-2. Pin Attributes

STATE AFTER

SIGNAL

TYPE⁽¹⁾

BUFFER

TYPE⁽²⁾

PIN MUX

ENCODING

POWER

PIN NUMBER

SIGNAL NAME

RESET

SOURCE⁽³⁾

RELEASE⁽⁴⁾

PD0

I/O

I

LVCMOS

Analog

–

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

AIN15

PD0

C0o

O

LVCMOS

Analog

PD0 (5)

PD0 (2)

PD0 (15)

PD0 (3)

–

1

VDD

I2C7SCL

SSI2XDAT1

T0CCP0

PD1

I/O

I

AIN14

PD1

C1o

O

LVCMOS

Analog

PD1 (5)

PD1 (2)

PD1 (15)

PD1 (3)

–

2

3

I2C7SDA

SSI2XDAT0

T0CCP1

PD2

I/O

I

AIN13

PD2

C2o

O

LVCMOS

Analog

PD2 (5)

PD2 (2)

PD2 (15)

PD2 (3)

–

I2C8SCL

SSI2Fss

T1CCP0

PD3

I/O

I

AIN12

PD3

4

5

I2C8SDA

SSI2Clk

T1CCP1

PQ0

I/O

LVCMOS

PD3 (2)

PD3 (15)

PD3 (3)

–

VDD

EPI0S20

SSI3Clk

PQ0 (15)

PQ0 (14)

(1) Signal Types: I = Input, O = Output, I/O = Input or Output.

(2) For details on buffer types, see 表 4-5.

(3) N/A = Not applicable

(4) State after reset release: PU = High impedance with an active pullup resistor, OFF = High impedance, N/A = not applicable

Terminal Configuration and Functions

9

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

表 4-2. Pin Attributes (continued)

STATE AFTER

RESET

SIGNAL

TYPE⁽¹⁾

BUFFER

TYPE⁽²⁾

PIN MUX

ENCODING

POWER

PIN NUMBER

SIGNAL NAME

SOURCE⁽³⁾

RELEASE⁽⁴⁾

PQ1

I/O

–

LVCMOS

Power

–

PQ1 (15)

PQ1 (14)

Fixed

–

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

6

EPI0S21

SSI3Fss

VDD

7

8

VDD

N/A

VDDA

VREFA+

GNDA

PQ2

–

Power

9

–

Analog

10

–

Power

I/O

I

LVCMOS

Analog

11

12

13

14

15

EPI0S22

SSI3XDAT0

PE3

PQ2 (15)

PQ2 (14)

–

VDD

AIN0

PE3

U1DTR

PE2

O

I/O

I

LVCMOS

Analog

PE3 (1)

–

AIN1

PE2

U1DCD

PE1

I

LVCMOS

Analog

PE2 (1)

–

I/O

I

AIN2

PE1

U1DSR

PE0

I

LVCMOS

Analog

PE1 (1)

–

I/O

I

AIN3

PE0

U1RTS

VDD

O

–

LVCMOS

Power

PE0 (1)

Fixed

–

16

17

N/A

GND

–

Power

PK0

I/O

I

LVCMOS

Analog

AIN16

EPI0S0

U4Rx

PK1

PK0

18

19

20

21

22

VDD

I/O

I

LVCMOS

Analog

PK0 (15)

PK0 (1)

–

I/O

I

AIN17

EPI0S1

U4Tx

PK1

I/O

O

I/O

I

LVCMOS

Analog

PK1 (15)

PK1 (1)

–

PK2

AIN18

EPI0S2

U4RTS

PK3

PK2

I/O

O

I/O

I

LVCMOS

Analog

PK2 (15)

PK2 (1)

–

AIN19

EPI0S3

U4CTS

PC7

PK3

I/O

I

LVCMOS

Analog

PK3 (15)

PK3 (1)

–

I/O

I

C0-

PC7

EPI0S4

U5Tx

I/O

O

LVCMOS

PC7 (15)

PC7 (1)

10

Terminal Configuration and Functions

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

表 4-2. Pin Attributes (continued)

STATE AFTER

SIGNAL

TYPE⁽¹⁾

BUFFER

TYPE⁽²⁾

PIN MUX

ENCODING

POWER

PIN NUMBER

SIGNAL NAME

RESET

SOURCE⁽³⁾

RELEASE⁽⁴⁾

PC6

C0+

I/O

I

LVCMOS

Analog

–

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

PC6

23

VDD

EPI0S5

U5Rx

I/O

I

LVCMOS

Analog

PC6 (15)

PC6 (1)

–

PC5

I/O

I

C1+

PC5

24

25

EPI0S6

RTCCLK

U7Tx

I/O

O

LVCMOS

Analog

PC5 (15)

PC5 (7)

PC5 (1)

–

VDD

O

PC4

I/O

I

C1-

PC4

EPI0S7

U7Rx

I/O

I

LVCMOS

Power

PC4 (15)

PC4 (1)

Fixed

26

27

28

29

VDD

–

N/A

VDD

N/A

PQ3

I/O

–

LVCMOS

Power

–

EPI0S23

SSI3XDAT1

VDD

PQ3 (15)

PQ3 (14)

Fixed

PH0

I/O

O

LVCMOS

–

EPI0S0

U0RTS

PH1

PH0 (15)

PH0 (1)

–

VDD

I/O

I

30

31

32

EPI0S1

U0CTS

PH2

PH1 (15)

PH1 (1)

–

VDD

I/O

I

EPI0S2

U0DCD

PH3

PH2 (15)

PH2 (1)

–

I/O

I

EPI0S3

U0DSR

PA0

PH3 (15)

PH3 (1)

–

I/O

I

CAN0Rx

I2C9SCL

T0CCP0

U0Rx

PA0 (7)

PA0 (2)

PA0 (3)

PA0 (1)

–

33

34

35

I/O

I

VDD

PA1

I/O

O

CAN0Tx

I2C9SDA

T0CCP1

U0Tx

PA1 (7)

PA1 (2)

PA1 (3)

PA1 (1)

–

I/O

O

PA2

I/O

I

I2C8SCL

SSI0Clk

T1CCP0

U4Rx

PA2 (2)

PA2 (15)

PA2 (3)

PA2 (1)

Terminal Configuration and Functions

11

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

表 4-2. Pin Attributes (continued)

STATE AFTER

RESET

SIGNAL

TYPE⁽¹⁾

BUFFER

TYPE⁽²⁾

PIN MUX

ENCODING

POWER

PIN NUMBER

SIGNAL NAME

SOURCE⁽³⁾

RELEASE⁽⁴⁾

PA3

I/O

O

LVCMOS

Power

–

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

I2C8SDA

SSI0Fss

PA3 (2)

PA3 (15)

PA3 (3)

PA3 (1)

–

36

37

VDD

T1CCP1

U4Tx

PA4

I/O

I

I2C7SCL

SSI0XDAT0

T2CCP0

U3Rx

PA4 (2)

PA4 (15)

PA4 (3)

PA4 (1)

–

PA5

I/O

O

I2C7SDA

SSI0XDAT1

T2CCP1

U3Tx

PA5 (2)

PA5 (15)

PA5 (3)

PA5 (1)

Fixed

38

39

VDD

N/A

VDD

–

PA6

I/O

I

LVCMOS

–

EPI0S8

I2C6SCL

SSI0XDAT2

T3CCP0

U2Rx

PA6 (15)

PA6 (2)

PA6 (13)

PA6 (3)

PA6 (1)

PA6 (5)

–

40

VDD

USB0EPEN

PA7

O

I/O

O

EPI0S9

I2C6SDA

SSI0XDAT3

T3CCP1

U2Tx

PA7 (15)

PA7 (2)

PA7 (13)

PA7 (3)

PA7 (1)

PA7 (11)

PA7 (5)

–

41

VDD

USB0EPEN

USB0PFLT

PF0

O

I

I/O

O

EN0LED0

M0PWM0

SSI3XDAT1

TRD2

PF0 (5)

PF0 (6)

PF0 (14)

PF0 (15)

–

42

O

VDD

I/O

O

PF1

I/O

O

EN0LED2

M0PWM1

SSI3XDAT0

TRD1

PF1 (5)

PF1 (6)

PF1 (14)

PF1 (15)

–

43

44

O

VDD

I/O

O

PF2

I/O

O

M0PWM2

SSI3Fss

TRD0

PF2 (6)

PF2 (14)

PF2 (15)

I/O

O

12

Terminal Configuration and Functions

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

表 4-2. Pin Attributes (continued)

STATE AFTER

SIGNAL

TYPE⁽¹⁾

BUFFER

TYPE⁽²⁾

PIN MUX

ENCODING

POWER

PIN NUMBER

SIGNAL NAME

RESET

SOURCE⁽³⁾

RELEASE⁽⁴⁾

PF3

I/O

O

LVCMOS

Power

–

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

M0PWM3

SSI3Clk

TRCLK

PF4

PF3 (6)

PF3 (14)

PF3 (15)

–

45

VDD

I/O

O

I/O

O

EN0LED1

M0FAULT0

SSI3XDAT2

TRD3

PF4 (5)

PF4 (6)

PF4 (14)

PF4 (15)

Fixed

46

I

VDD

I/O

O

47

48

VDD

–

N/A

GND

–

Power

Fixed

PG0

I/O

O

LVCMOS

Power

–

EN0PPS

EPI0S11

I2C1SCL

M0PWM4

PG1

PG0 (5)

PG0 (15)

PG0 (2)

PG0 (6)

–

49

I/O

O

VDD

I/O

O

EPI0S10

I2C1SDA

M0PWM5

VDD

PG1 (15)

PG1 (2)

PG1 (6)

Fixed

50

51

52

53

54

55

56

57

58

59

–

N/A

VDD

–

Power

Fixed

EN0RXIN

EN0RXIP

GND

I/O

–

LVCMOS

Power

Fixed

VDD

N/A

Fixed

EN0TXON

EN0TXOP

GND

I/O

–

LVCMOS

Power

Fixed

VDD

N/A

Fixed

RBIAS

O

Analog

Fixed

VDD

PK7

I/O

I

LVCMOS

–

EPI0S24

I2C4SDA

M0FAULT2

RTCCLK

U0RI

PK7 (15)

PK7 (2)

PK7 (6)

PK7 (5)

PK7 (1)

–

60

VDD

O

I

PK6

I/O

O

EN0LED1

EPI0S25

I2C4SCL

M0FAULT1

PK5

PK6 (5)

PK6 (15)

PK6 (2)

PK6 (6)

–

61

62

I/O

I

VDD

I/O

O

EN0LED2

EPI0S31

I2C3SDA

M0PWM7

PK5 (5)

PK5 (15)

PK5 (2)

PK5 (6)

I/O

O

Terminal Configuration and Functions

13

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

表 4-2. Pin Attributes (continued)

STATE AFTER

RESET

SIGNAL

TYPE⁽¹⁾

BUFFER

TYPE⁽²⁾

PIN MUX

ENCODING

POWER

PIN NUMBER

SIGNAL NAME

SOURCE⁽³⁾

RELEASE⁽⁴⁾

PK4

I/O

O

LVCMOS

Analog

–

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

EN0LED0

EPI0S32

PK4 (5)

PK4 (15)

PK4 (2)

PK4 (6)

Fixed

–

63

I/O

O

VDD

I2C3SCL

M0PWM6

WAKE

HIB

64

65

66

67

68

69

70

I

VBAT

N/A

O

XOSC0

XOSC1

VBAT

I

O

Analog

–

Power

VDD

–

Power

N/A

RST

I

LVCMOS

Power

VDD

PM7

I/O

I

T5CCP1

TMPR0

U0RI

PM7 (3)

PM7

71

72

73

74

VDD

PM7 (1)

–

PM6

I/O

I

T5CCP0

TMPR1

U0DSR

PM5

PM6 (3)

PM6

PM6 (1)

–

I/O

I

T4CCP1

TMPR2

U0DCD

PM4

PM5 (3)

PM5

PM5 (1)

–

I/O

I

T4CCP0

TMPR3

U0CTS

PM3

PM4 (3)

PM4

PM4 (1)

–

I/O

–

75

76

77

78

EPI0S12

T3CCP1

PM2

PM3 (15)

PM3 (3)

–

VDD

EPI0S13

T3CCP0

PM1

PM2 (15)

PM2 (3)

–

EPI0S14

T2CCP1

PM0

PM1 (15)

PM1 (3)

–

EPI0S15

T2CCP0

VDD

PM0 (15)

PM0 (3)

Fixed

79

80

N/A

GND

–

Power

14

Terminal Configuration and Functions

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

表 4-2. Pin Attributes (continued)

STATE AFTER

SIGNAL

TYPE⁽¹⁾

BUFFER

TYPE⁽²⁾

PIN MUX

ENCODING

POWER

PIN NUMBER

SIGNAL NAME

RESET

SOURCE⁽³⁾

RELEASE⁽⁴⁾

PL0

I/O

I

LVCMOS

Power

–

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

EPI0S16

I2C2SDA

M0FAULT3

USB0D0

PL1

PL0 (15)

PL0 (2)

PL0 (6)

PL0 (14)

–

81

VDD

I/O

I

EPI0S17

I2C2SCL

PhA0

PL1 (15)

PL1 (2)

PL1 (6)

PL1 (14)

–

82

83

84

VDD

USB0D1

PL2

I/O

O

C0o

PL2 (5)

PL2 (15)

PL2 (6)

PL2 (14)

–

EPI0S18

PhB0

I/O

I

USB0D2

PL3

I/O

O

C1o

PL3 (5)

PL3 (15)

PL3 (6)

PL3 (14)

–

EPI0S19

IDX0

I/O

I

USB0D3

PL4

I/O

–

EPI0S26

T0CCP0

USB0D4

PL5

PL4 (15)

PL4 (3)

PL4 (14)

–

85

86

VDD

EPI0S33

T0CCP1

USB0D5

VDDC

PL5 (15)

PL5 (3)

PL5 (14)

Fixed

87

88

89

90

N/A

VDD

N/A

OSC0

I

Analog

Fixed

OSC1

O

Analog

Fixed

VDD

–

Power

Fixed

PB2

I/O

O

LVCMOS

Analog

–

EPI0S27

I2C0SCL

T5CCP0

USB0STP

PB3

PB2 (15)

PB2 (2)

PB2 (3)

PB2 (14)

–

91

VDD

I/O

O

EPI0S28

I2C0SDA

T5CCP1

USB0CLK

PL7

PB3 (15)

PB3 (2)

PB3 (3)

PB3 (14)

–

92

93

VDD

I/O

T1CCP1

USB0DM

PL7 (3)

PL7

Terminal Configuration and Functions

15

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

表 4-2. Pin Attributes (continued)

STATE AFTER

RESET

SIGNAL

TYPE⁽¹⁾

BUFFER

TYPE⁽²⁾

PIN MUX

ENCODING

POWER

PIN NUMBER

SIGNAL NAME

SOURCE⁽³⁾

RELEASE⁽⁴⁾

PL6

I/O

I

LVCMOS

Analog

–

OFF

N/A

OFF

N/A

OFF

N/A

OFF

PU

94

95

T1CCP0

USB0DP

PL6 (3)

PL6

VDD

PB0

LVCMOS

Analog

–

CAN1Rx

I2C5SCL

T4CCP0

U1Rx

PB0 (7)

PB0 (2)

PB0 (3)

PB0 (1)

PB0

I/O

I

USB0ID

PB1

I

I/O

O

LVCMOS

Analog

–

CAN1Tx

I2C5SDA

T4CCP1

U1Tx

PB1 (7)

PB1 (2)

PB1 (3)

PB1 (1)

PB1

I/O

O

96

VDD

USB0VBUS

PC3

I/O

O

LVCMOS

Power

–

97

98

99

VDD

TDO/SWO

PC2

PC3 (1)

–

I/O

I

N/A

PU

TDI

PC2 (1)

–

PC1

I/O

I

OFF

PU

TMS/SWDIO

PC0

PC1 (1)

–

OFF

PU

100

101

VDD

N/A

TCK/SWCLK

VDD

PC0 (1)

Fixed

–

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

PQ4

I/O

O

LVCMOS

102

DIVSCLK

U1Rx

PQ4 (7)

PQ4 (1)

–

VDD

I

PP2

I/O

O

EPI0S29

U0DTR

USB0NXT

PP3

PP2 (15)

PP2 (1)

PP2 (14)

–

103

VDD

O

I/O

O

EPI0S30

RTCCLK

U0DCD

U1CTS

USB0DIR

PP4

PP3 (15)

PP3 (7)

PP3 (2)

PP3 (1)

PP3 (14)

–

104

VDD

I

O

I/O

I

U0DSR

U3RTS

USB0D7

PP5

PP4 (2)

PP4 (1)

PP4 (14)

–

105

106

VDD

O

I/O

I

I2C2SCL

U3CTS

USB0D6

PP5 (2)

PP5 (1)

PP5 (14)

I/O

16

Terminal Configuration and Functions

MSP432E401Y

www.ti.com.cn

PIN NUMBER

ZHCSH09 –OCTOBER 2017

表 4-2. Pin Attributes (continued)

STATE AFTER

SIGNAL

TYPE⁽¹⁾

BUFFER

TYPE⁽²⁾

PIN MUX

ENCODING

POWER

SIGNAL NAME

RESET

SOURCE⁽³⁾

RELEASE⁽⁴⁾

PN0

I/O

O

LVCMOS

Power

–

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

107

108

VDD

U1RTS

PN1

PN0 (1)

–

I/O

I

VDD

U1CTS

PN2

PN1 (1)

–

I/O

I

EPI0S29

U1DCD

U2RTS

PN3

PN2 (15)

PN2 (1)

PN2 (2)

–

109

110

O

I/O

I

EPI0S30

U1DSR

U2CTS

PN4

PN3 (15)

PN3 (1)

PN3 (2)

–

VDD

I

I/O

O

EPI0S34

I2C2SDA

U1DTR

U3RTS

PN5

PN4 (15)

PN4 (3)

PN4 (1)

PN4 (2)

–

111

112

O

I/O

I

EPI0S35

I2C2SCL

U1RI

PN5 (15)

PN5 (3)

PN5 (1)

PN5 (2)

Fixed

–

VDD

U3CTS

VDD

I

113

114

115

–

N/A

GND

–

Power

VDDC

PJ0

–

Power

I/O

O

LVCMOS

Analog

116

117

EN0PPS

U3Rx

PJ0 (5)

PJ0 (1)

–

VDD

I

PJ1

I/O

O

U3Tx

PJ1 (1)

–

PP0

I/O

I

C2+

PP0

118

119

VDD

SSI3XDAT2

U6Rx

I/O

I

LVCMOS

Analog

PP0 (15)

PP0 (1)

–

PP1

I/O

I

C2-

PP1

SSI3XDAT3

U6Tx

I/O

O

LVCMOS

Analog

PP1 (15)

PP1 (1)

–

PB5

I/O

I

AIN11

I2C5SDA

SSI1Clk

U0RTS

PB5

120

I/O

O

LVCMOS

PB5 (2)

PB5 (15)

PB5 (1)

VDD

Terminal Configuration and Functions

17

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

表 4-2. Pin Attributes (continued)

STATE AFTER

RESET

SIGNAL

TYPE⁽¹⁾

BUFFER

TYPE⁽²⁾

PIN MUX

ENCODING

POWER

PIN NUMBER

SIGNAL NAME

SOURCE⁽³⁾

RELEASE⁽⁴⁾

PB4

I/O

I

LVCMOS

Analog

–

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

OFF

N/A

AIN10

PB4

121

I2C5SCL

SSI1Fss

I/O

I

LVCMOS

Power

PB4 (2)

PB4 (15)

PB4 (1)

Fixed

VDD

U0CTS

VDD

122

123

–

N/A

PE4

I/O

I

LVCMOS

Analog

–

AIN9

PE4

VDD

SSI1XDAT0

U1RI

I/O

I

LVCMOS

Analog

PE4 (15)

PE4 (1)

–

PE5

I/O

I

124

125

AIN8

PE5

VDD

SSI1XDAT1

PD4

I/O

I

LVCMOS

Analog

PE5 (15)

–

AIN7

PD4

SSI1XDAT2

T3CCP0

U2Rx

I/O

I

LVCMOS

Analog

PD4 (15)

PD4 (3)

PD4 (1)

–

PD5

I/O

I

AIN6

PD5

126

127

SSI1XDAT3

T3CCP1

U2Tx

I/O

O

LVCMOS

Analog

PD5 (15)

PD5 (3)

PD5 (1)

–

VDD

PD6

I/O

I

AIN5

PD6

SSI2XDAT3

T4CCP0

U2RTS

USB0EPEN

PD7

I/O

O

LVCMOS

Analog

PD6 (15)

PD6 (3)

PD6 (1)

PD6 (5)

–

O

I/O

I

AIN4

PD7

NMI

I

LVCMOS

PD7 (8)

PD7 (15)

PD7 (3)

PD7 (1)

PD7 (5)

128

SSI2XDAT2

T4CCP1

U2CTS

USB0PFLT

I/O

I

VDD

I

18

Terminal Configuration and Functions

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

4.3 Signal Descriptions

表 4-3 describes the signals. The signals are sorted by function.

表 4-3. Signal Descriptions

FUNCTION

SIGNAL NAME

AIN0

PIN NO.

PIN TYPE

DESCRIPTION

12

I

Analog-to-digital converter input 0.

Analog-to-digital converter input 1

Analog-to-digital converter input 2

Analog-to-digital converter input 3

Analog-to-digital converter input 4

Analog-to-digital converter input 5

Analog-to-digital converter input 6

Analog-to-digital converter input 7

Analog-to-digital converter input 8

Analog-to-digital converter input 9

Analog-to-digital converter input 10

Analog-to-digital converter input 11

Analog-to-digital converter input 12

Analog-to-digital converter input 13

Analog-to-digital converter input 14

Analog-to-digital converter input 15

Analog-to-digital converter input 16

Analog-to-digital converter input 17

Analog-to-digital converter input 18

Analog-to-digital converter input 19

AIN1

13

14

I

AIN2

AIN3

15

AIN4

128

127

126

125

124

123

121

120

4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10

AIN11

AIN12

AIN13

AIN14

AIN15

AIN16

AIN17

AIN18

AIN19

ADC

3

2

1

18

19

20

21

A reference voltage used to specify the voltage at which the

ADC converts to a maximum value. This pin is used in

conjunction with GNDA. The voltage that is applied to

VREFA+ is the voltage with which an AINn signal is

converted to 4095. The VREFA+ voltage is limited to the

range specified in the ADC electrical specifications.

VREFA+

9

-

C0+

C0-

23

22

I

Analog comparator 0 positive input

Analog comparator 0 negative input

1

83

C0o

O

Analog comparator 0 output

C1+

C1-

24

25

I

Analog comparator 1 positive input

Analog comparator 1 negative input

Analog Comparators

2

84

C1o

O

Analog comparator 1 output

C2+

118

119

3

I

Analog comparator 2 positive input

Analog comparator 2 negative input

Analog comparator 2 output

CAN module 0 receive

C2-

C2o

O

I

CAN0Rx

CAN0Tx

CAN1Rx

CAN1Tx

33

34

95

96

O

I

CAN module 0 transmit

Controller Area

Network

CAN module 1 receive

O

CAN module 1 transmit

Terminal Configuration and Functions

19

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

表 4-3. Signal Descriptions (continued)

FUNCTION

SIGNAL NAME

TRCLK

PIN NO.

PIN TYPE

DESCRIPTION

45

O

Trace clock.

Trace data 0.

Trace data 1.

Trace data 2.

TRD0

TRD1

TRD2

TRD3

44

43

42

46

O

Core

Trace data 3.

42

63

EN0LED0

EN0LED1

EN0LED2

EN0PPS

O

Ethernet 0 LED 0

46

61

Ethernet 0 LED 1

Ethernet 0 LED 2

43

62

49

116

Ethernet

Ethernet 0 pulse-per-second (PPS) output

EN0RXIN

EN0RXIP

EN0TXON

EN0TXOP

RBIAS

53

54

56

57

59

I/O

O

Ethernet PHY negative receive differential input

Ethernet PHY positive receive differential input

Ethernet PHY negative transmit differential output

Ethernet PHY positive transmit differential output

4.87-kΩ resistor (1% precision) for Ethernet PHY

20

Terminal Configuration and Functions

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

表 4-3. Signal Descriptions (continued)

FUNCTION

SIGNAL NAME

EPI0S0

PIN NO.

PIN TYPE

DESCRIPTION

18

29

I/O

EPI module 0 signal 0

EPI module 0 signal 1

EPI module 0 signal 2

EPI module 0 signal 3

19

30

EPI0S1

EPI0S2

EPI0S3

I/O

20

31

21

32

EPI0S4

22

23

24

25

40

41

50

49

75

76

77

78

81

82

83

84

5

I/O

EPI module 0 signal 4

EPI module 0 signal 5

EPI module 0 signal 6

EPI module 0 signal 7

EPI module 0 signal 8

EPI module 0 signal 9

EPI module 0 signal 10

EPI module 0 signal 11

EPI module 0 signal 12

EPI module 0 signal 13

EPI module 0 signal 14

EPI module 0 signal 15

EPI module 0 signal 16

EPI module 0 signal 17

EPI module 0 signal 18

EPI module 0 signal 19

EPI module 0 signal 20

EPI module 0 signal 21

EPI module 0 signal 22

EPI module 0 signal 23

EPI module 0 signal 24

EPI module 0 signal 25

EPI module 0 signal 26

EPI module 0 signal 27

EPI module 0 signal 28

EPI0S5

EPI0S6

EPI0S7

EPI0S8

EPI0S9

EPI0S10

EPI0S11

EPI0S12

EPI0S13

EPI0S14

EPI0S15

EPI0S16

EPI0S17

EPI0S18

EPI0S19

EPI0S20

EPI0S21

EPI0S22

EPI0S23

EPI0S24

EPI0S25

EPI0S26

EPI0S27

EPI0S28

External Peripheral

Interface

6

11

27

60

61

85

91

92

103

109

EPI0S29

EPI0S30

I/O

EPI module 0 signal 29

EPI module 0 signal 30

104

110

EPI0S31

EPI0S32

EPI0S33

EPI0S34

EPI0S35

62

63

I/O

EPI module 0 signal 31

EPI module 0 signal 32

EPI module 0 signal 33

EPI module 0 signal 34

EPI module 0 signal 35

86

111

112

Terminal Configuration and Functions

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表 4-3. Signal Descriptions (continued)

FUNCTION

SIGNAL NAME

T0CCP0

PIN NO.

PIN TYPE

DESCRIPTION

1

33

85

I/O

16/32-Bit Timer 0 Capture/Compare/PWM 0

2

T0CCP1

T1CCP0

T1CCP1

34

86

I/O

16/32-Bit Timer 0 Capture/Compare/PWM 1

16/32-Bit Timer 1 Capture/Compare/PWM 0

16/32-Bit Timer 1 Capture/Compare/PWM 1

3

35

94

4

36

93

37

78

T2CCP0

T2CCP1

I/O

16/32-Bit Timer 2 Capture/Compare/PWM 0

16/32-Bit Timer 2 Capture/Compare/PWM 1

38

77

General-Purpose

Timers

40

76

125

T3CCP0

T3CCP1

T4CCP0

T4CCP1

I/O

16/32-Bit Timer 3 Capture/Compare/PWM 0

16/32-Bit Timer 3 Capture/Compare/PWM 1

16/32-Bit Timer 4 Capture/Compare/PWM 0

16/32-Bit Timer 4 Capture/Compare/PWM 1

41

75

126

74

95

127

73

96

128

72

91

T5CCP0

T5CCP1

I/O

16/32-Bit Timer 5 Capture/Compare/PWM 0

16/32-Bit Timer 5 Capture/Compare/PWM 1

71

92

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB3

PB4

PB5

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

33

34

35

36

37

38

40

41

95

96

91

92

121

120

100

99

98

97

25

24

23

22

I/O

GPIO port A bit 0

GPIO port A bit 1

GPIO port A bit 2

GPIO port A bit 3

GPIO port A bit 4

GPIO port A bit 5

GPIO port A bit 6

GPIO port A bit 7

GPIO port B bit 0

GPIO port B bit 1

GPIO port B bit 2

GPIO port B bit 3

GPIO port B bit 4

GPIO port B bit 5

GPIO port C bit 0

GPIO port C bit 1

GPIO port C bit 2

GPIO port C bit 3

GPIO port C bit 4

GPIO port C bit 5

GPIO port C bit 6

GPIO port C bit 7

GPIO, Port A

GPIO, Port B

GPIO, Port C

22

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表 4-3. Signal Descriptions (continued)

FUNCTION

SIGNAL NAME

PD0

PIN NO.

1

PIN TYPE

I/O

DESCRIPTION

GPIO port D bit 0

GPIO port D bit 1

GPIO port D bit 2

GPIO port D bit 3

GPIO port D bit 4

GPIO port D bit 5

GPIO port D bit 6

GPIO port D bit 7

GPIO port E bit 0

GPIO port E bit 1

GPIO port E bit 2

GPIO port E bit 3

GPIO port E bit 4

GPIO port E bit 5

GPIO port F bit 0

GPIO port F bit 1

GPIO port F bit 2

GPIO port F bit 3

GPIO port F bit 4

GPIO port G bit 0

GPIO port G bit 1

GPIO port H bit 0

GPIO port H bit 1

GPIO port H bit 2

GPIO port H bit 3

GPIO port J bit 0

GPIO port J bit 1

GPIO port K bit 0

GPIO port K bit 1

GPIO port K bit 2

GPIO port K bit 3

GPIO port K bit 4

GPIO port K bit 5

GPIO port K bit 6

GPIO port K bit 7

GPIO port L bit 0

GPIO port L bit 1

GPIO port L bit 2

GPIO port L bit 3

GPIO port L bit 4

GPIO port L bit 5

GPIO port L bit 6

GPIO port L bit 7

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PE0

PE1

PE2

PE3

PE4

PE5

PF0

PF1

PF2

PF3

PF4

PG0

PG1

PH0

PH1

PH2

PH3

PJ0

PJ1

PK0

PK1

PK2

PK3

PK4

PK5

PK6

PK7

PL0

PL1

PL2

PL3

PL4

PL5

PL6

PL7

2

3

4

GPIO, Port D

125

126

127

128

15

14

13

12

123

124

42

43

44

45

46

49

50

29

30

31

32

116

117

18

19

20

21

63

62

61

60

81

82

83

84

85

86

94

93

GPIO, Port E

GPIO, Port F

GPIO, Port G

GPIO, Port H

GPIO, Port J

GPIO, Port K

GPIO, Port L

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表 4-3. Signal Descriptions (continued)

FUNCTION

SIGNAL NAME

PM0

PIN NO.

78

PIN TYPE

I/O

O

DESCRIPTION

GPIO port M bit 0

GPIO port M bit 1

GPIO port M bit 2

GPIO port M bit 3

GPIO port M bit 4

GPIO port M bit 5

GPIO port M bit 6

GPIO port M bit 7

GPIO port N bit 0

GPIO port N bit 1

GPIO port N bit 2

GPIO port N bit 3

GPIO port N bit 4

GPIO port N bit 5

GPIO port P bit 0

GPIO port P bit 1

GPIO port P bit 2

GPIO port P bit 3

GPIO port P bit 4

GPIO port P bit 5

GPIO port Q bit 0

GPIO port Q bit 1

GPIO port Q bit 2

GPIO port Q bit 3

GPIO port Q bit 4

PM1

PM2

PM3

PM4

PM5

PM6

PM7

PN0

PN1

PN2

PN3

PN4

PN5

PP0

PP1

PP2

PP3

PP4

PP5

PQ0

PQ1

PQ2

PQ3

PQ4

HIB

77

76

75

GPIO, Port M

74

73

72

71

107

108

109

110

111

112

118

119

103

104

105

106

5

GPIO, Port N

GPIO, Port P

6

GPIO, Port Q

11

27

102

65

An output that indicates the processor is in Hibernate mode

24

60

104

Buffered version of the Hibernation module's 32.768-kHz

clock. This signal is not output when the part is in Hibernate

mode and before being configured after power-on reset.

RTCCLK

O

TMPR0

TMPR1

TMPR2

TMPR3

71

72

73

74

I/O

Tamper signal 0

Tamper signal 1

Tamper signal 2

Tamper signal 3

Power source for the Hibernation module. It is normally

connected to the positive terminal of a battery and serves as

the battery backup and Hibernation module power-source

supply.

Hibernate

VBAT

68

-

An external input that brings the processor out of Hibernate

mode when asserted

WAKE

64

66

67

I

Hibernation module oscillator crystal input or an external

clock reference input. This is either a crystal or a 32.768-

kHz oscillator for the Hibernation module RTC.

XOSC0

XOSC1

Hibernation module oscillator crystal output. Leave

unconnected when using a single-ended clock source.

O

24

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表 4-3. Signal Descriptions (continued)

FUNCTION

SIGNAL NAME

I2C0SCL

PIN NO.

PIN TYPE

DESCRIPTION

I²C module 0 clock. This signal has an active pullup. The

corresponding port pin should not be configured as open

drain.

91

I/O

I2C0SDA

I2C1SCL

I2C1SDA

I2C2SCL

92

I/O

I²C module 0 data

I²C module 1 clock. This signal has an active pullup. The

corresponding port pin should not be configured as open

drain.

I²C module 1 data

I²C module 2 clock. This signal has an active pullup. The

corresponding port pin should not be configured as open

drain.

49

I/O

50

I/O

82

106

112

I/O

81

111

I2C2SDA

I/O

I²C module 2 data

I²C module 3 clock. This signal has an active pullup. The

corresponding port pin should not be configured as open

drain.

I²C module 3 data

I²C module 4 clock. This signal has an active pullup. The

corresponding port pin should not be configured as open

drain.

I²C module 4 data

I2C3SCL

I2C3SDA

I2C4SCL

I2C4SDA

I2C5SCL

63

62

61

60

I/O

I²C module 5 clock. This signal has an active pullup. The

corresponding port pin should not be configured as open

drain.

I²C

95

121

96

120

I2C5SDA

I/O

I²C module 5 data

I²C module 6 clock. This signal has an active pullup. The

corresponding port pin should not be configured as open

drain.

I²C module 6 data

I²C module 7 clock. This signal has an active pullup. The

corresponding port pin should not be configured as open

drain.

I2C6SCL

I2C6SDA

I2C7SCL

40

41

I/O

1

37

2

38

I2C7SDA

I2C8SCL

I2C8SDA

I2C9SCL

I/O

I²C module 7 data

I²C module 8 clock. This signal has an active pullup. The

corresponding port pin should not be configured as open

drain.

3

35

4

36

I²C module 8 data

I²C module 9 clock. This signal has an active pullup. The

corresponding port pin should not be configured as open

drain

33

I2C9SDA

TCK/SWCLK

TDI

34

100

98

I/O

I²C module 9 data

JTAG/SWD clock

JTAG TDI

I

JTAG, SWD, SWO

TDO/SWO

TMS/SWDIO

97

O

I

JTAG TDO and SWO

JTAG TMS and SWDIO

99

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表 4-3. Signal Descriptions (continued)

FUNCTION

SIGNAL NAME

M0FAULT0

PIN NO.

46

PIN TYPE

DESCRIPTION

Motion Control module 0 PWM fault 0

Motion Control module 0 PWM fault 1

Motion Control module 0 PWM fault 2

Motion Control module 0 PWM fault 3

I

M0FAULT1

M0FAULT2

M0FAULT3

61

60

81

Motion Control module 0 PWM 0. This signal is controlled by

module 0 PWM generator 0.

M0PWM0

M0PWM1

M0PWM2

M0PWM3

M0PWM4

M0PWM5

M0PWM6

M0PWM7

42

43

44

45

49

50

63

62

O

Motion Control module 0 PWM 1. This signal is controlled by

module 0 PWM generator 0.

Motion Control module 0 PWM 2. This signal is controlled by

module 0 PWM generator 1.

PWM

Motion Control module 0 PWM 3. This signal is controlled by

module 0 PWM generator 1.

Motion Control module 0 PWM 4. This signal is controlled by

module 0 PWM generator 2.

Motion Control module 0 PWM 5. This signal is controlled by

module 0 PWM generator 2.

Motion Control module 0 PWM 6. This signal is controlled by

module 0 PWM generator 3.

Motion Control module 0 PWM 7. This signal is controlled by

module 0 PWM generator 3.

17

48

55

58

80

114

GND

-

Ground reference for logic and I/O pins

The ground reference for the analog circuits (ADC, Analog

Comparators, etc.). These are separated from GND to

minimize the electrical noise contained on VDD from

affecting the analog functions

GNDA

10

7

16

26

28

39

47

51

52

VDD

-

Positive supply for I/O and some logic

Power

69

79

90

101

113

122

The positive supply for the analog circuits (for example,

ADC and Analog Comparators). These are separated from

VDD to minimize the electrical noise contained on VDD from

affecting the analog functions. VDDA pins must be supplied

with a voltage that meets the specification in, regardless of

system implementation

VDDA

VDDC

8

-

Positive supply for most of the logic function, including the

processor core and most peripherals. The voltage on this

pin is 1.2 V and is supplied by the on-chip LDO. The VDDC

pins should only be connected to each other and an external

capacitor as specified in the LDO electrical specifications.

87

115

IDX0

PhA0

PhB0

84

82

83

I

QEI module 0 index

QEI module 0 phase A

QEI module 0 phase B

QEI

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ZHCSH09 –OCTOBER 2017

表 4-3. Signal Descriptions (continued)

FUNCTION

SIGNAL NAME

SSI0Clk

PIN NO.

35

PIN TYPE

I/O

DESCRIPTION

SSI module 0 clock

SSI module 0 frame signal

SSI0Fss

36

I/O

SSI module 0 bidirectional data pin 0 (SSI0TX in Legacy

SSI mode)

SSI0XDAT0

37

38

I/O

SSI module 0 bidirectional data pin 1 (SSI0RX in Legacy

SSI mode)

SSI0XDAT1

SSI0XDAT2

SSI0XDAT3

SSI1Clk

40

41

I/O

SSI module 0 bidirectional data pin 2

SSI module 0 bidirectional data pin 3

SSI module 1 clock

120

121

SSI1Fss

SSI module 1 frame signal

SSI module 1 bidirectional data pin 0 (SSI1TX in Legacy

SSI mode)

SSI1XDAT0

SSI1XDAT1

123

124

I/O

SSI module 1 bidirectional data pin 1 (SSI1RX in Legacy

SSI mode)

SSI1XDAT2

SSI1XDAT3

SSI2Clk

125

126

4

I/O

SSI module 1 bidirectional data pin 2

SSI module 1 bidirectional data pin 3

SSI module 2 clock

SSI

SSI2Fss

3

SSI module 2 frame signal

SSI module 2 bidirectional data pin 0 (SSI2TX in Legacy

SSI mode)

SSI2XDAT0

SSI2XDAT1

2

1

I/O

SSI module 2 bidirectional data pin 1 (SSI2RX in Legacy

SSI mode)

SSI2XDAT2

SSI2XDAT3

128

127

I/O

SSI module 2 bidirectional data pin 2

SSI module 2 bidirectional data pin 3

5

45

SSI3Clk

I/O

SSI module 3 clock

6

44

SSI3Fss

SSI module 3 frame signal

11

43

SSI module 3 bidirectional data pin 0 (SSI3TX in Legacy

SSI mode)

SSI3XDAT0

SSI3XDAT1

27

42

SSI module 3 bidirectional data pin 1 (SSI3RX in Legacy

SSI mode)

46

118

SSI3XDAT2

SSI3XDAT3

I/O

SSI module 3 bidirectional data pin 2

SSI module 3 bidirectional data pin 3

119

102

An optionally divided reference clock output based on a

selected clock source. This signal is not synchronized to the

system clock.

DIVSCLK

O

NMI

128

88

I

Nonmaskable interrupt

System Control and

Clocks

Main oscillator crystal input or an external clock reference

input

OSC0

Main oscillator crystal output. Leave unconnected when

using a single-ended clock source.

OSC1

RST

89

70

O

I

System reset input

Terminal Configuration and Functions

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表 4-3. Signal Descriptions (continued)

FUNCTION

SIGNAL NAME

U0CTS

PIN NO.

PIN TYPE

DESCRIPTION

30

74

121

UART module 0 Clear To Send modem flow control input

signal

I

31

73

104

UART module 0 Data Carrier Detect modem status input

signal

U0DCD

U0DSR

I

32

72

UART module 0 Data Set Ready modem output control line

105

UART Module 0

UART module 0 Data Terminal Ready modem status input

signal

U0DTR

U0RI

103

O

I

60

71

UART module 0 Ring Indicator modem status input signal

29

120

UART module 0 Request to Send modem flow control

output signal

U0RTS

O

U0Rx

U0Tx

33

34

I

UART module 0 receive

UART module 0 transmit

O

104

108

UART module 1 Clear To Send modem flow control input

signal

U1CTS

U1DCD

U1DSR

U1DTR

U1RI

I

13

109

UART module 1 Data Carrier Detect modem status input

signal

14

110

I

UART module 1 Data Set Ready modem output control line

12

111

UART module 1 Data Terminal Ready modem status input

signal

O

I

UART Module 1

112

123

UART module 1 Ring Indicator modem status input signal

15

107

UART module 1 Request to Send modem flow control

output line

U1RTS

O

95

102

U1Rx

U1Tx

I

O

I

UART module 1 receive.

UART module 1 transmit

96

110

128

UART module 2 Clear To Send modem flow control input

signal

U2CTS

109

127

UART module 2 Request to Send modem flow control

output line

U2RTS

U2Rx

O

I

UART Module 2

UART Module 3

UART Module 4

40

125

UART module 2 receive

UART module 2 transmit

41

126

U2Tx

O

I

106

112

UART module 3 Clear To Send modem flow control input

signal

U3CTS

U3RTS

U3Rx

105

111

UART module 3 Request to Send modem flow control

output line

O

I

37

116

UART module 3 receive

UART module 3 transmit

38

117

U3Tx

O

I

UART module 4 Clear To Send modem flow control input

signal

U4CTS

U4RTS

U4Rx

21

20

UART module 4 Request to Send modem flow control

output line

O

I

18

35

UART module 4 receive

UART module 4 transmit

19

36

U4Tx

O

28

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表 4-3. Signal Descriptions (continued)

FUNCTION

SIGNAL NAME

U5Rx

PIN NO.

23

PIN TYPE

DESCRIPTION

UART module 5 receive

I

UART Module 5

UART Module 6

UART Module 7

U5Tx

22

O

UART module 5 transmit

UART module 6 receive

UART module 6 transmit

UART module 7 receive

UART module 7 transmit

60-MHz clock to the external PHY

USB data 0

U6Rx

118

119

25

I

U6Tx

O

U7Rx

I

U7Tx

24

O

USB0CLK

USB0D0

USB0D1

USB0D2

USB0D3

USB0D4

USB0D5

USB0D6

USB0D7

92

O

81

I/O

82

USB data 1

83

USB data 2

84

USB data 3

85

USB data 4

86

USB data 5

106

105

USB data 6

USB data 7

Indicates that the external PHY is able to accept data from

the USB controller

USB0DIR

USB0DM

USB0DP

104

93

O

Bidirectional differential data pin (D– per USB specification)

for USB0

I/O

Bidirectional differential data pin (D+ per USB specification)

for USB0

94

USB

40

41

127

Optionally used in Host mode to control an external power

source to supply power to the USB bus

USB0EPEN

USB0ID

O

I

This signal senses the state of the USB ID signal. The USB

PHY enables an integrated pull-up, and an external element

(USB connector) indicates the initial state of the USB

controller (pulled down is the A side of the cable and pulled

up is the B side).

95

USB0NXT

USB0PFLT

103

O

I

Asserted by the external PHY to throttle all data types

41

128

Optionally used in Host mode by an external power source

to indicate an error state by that power source

Asserted by the USB controller to signal the end of a USB

transmit packet or register write operation

USB0STP

91

96

O

This signal is used during the session request protocol. This

signal allows the USB PHY to both sense the voltage level

of VBUS, and pull up VBUS momentarily during VBUS

pulsing.

USB0VBUS

I/O

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4.5 Buffer Type

表 4-5 describes the buffer types that are referenced in 节 4.2.

表 4-5. Buffer Type

NOMINAL

OUTPUT

DRIVE

STRENGTH

(mA)

BUFFER TYPE

(STANDARD)

NOMINAL

VOLTAGE

PU OR PD

STRENGTH

(µA)

OTHER

CHARACTERISTICS

HYSTERESIS

PU OR PD

See analog modules in 节 5

for details.

Analog⁽¹⁾

3.3 V

N

N/A

See

Input/Output

See Typical

Characteristics.

LVCMOS

Y⁽²⁾

Programmable

Characteristics

.

Power (VDD)⁽³⁾

Power (VDDA)⁽³⁾

3.3 V

N

N/A

Power (GND and

GNDA)⁽³⁾

0 V

N

N/A

(1) This is a switch, not a buffer.

(2) Only for input pins

(3) This is supply input, not a buffer.

4.6 Connections for Unused Pins

表 4-6 lists the recommended connections for unused pins.

表 4-6 lists two options: an acceptable practice and a preferred practice for reduced power consumption

and improved EMC characteristics. If a module is not used in a system, and its inputs are grounded, it is

important that the clock to the module is never enabled by setting the corresponding bit in the RCGCx

register.

表 4-6. Connections for Unused Pins

ACCEPTABLE

PRACTICE

PREFERRED

PRACTICE

FUNCTION

SIGNAL NAME

PIN NUMBER

ADC

VREFA+

9

VDDA

NC

VDDA

NC

EN0RXIN

EN0RXIP

EN0TXON

EN0TXOP

53

54

56

57

NC

Ethernet

NC

Connect to ground

through 4.87-kΩ

resistor.

Connect to ground

through 4.87-kΩ

resistor.

RBIAS

59

PA1 (U0Tx)

PA4 (SSI0XDAT0)

All unused GPIOs

HIB

34

37

NC

GND⁽¹⁾

GND⁽²⁾

GND

NC

GPIO

65

68

64

66

VBAT

VDD

WAKE

GND

Hibernate

XOSC0

XOSC1

NC

67

(1) PA1 (U0Tx) may be enabled as an output by the ROM bootloader if no code is present in the flash and PA0 (U0Rx) receives a valid

boot signature. Ensure that this condition will not occur if PA1 is to be connected directly to GND.

(2) PA4 (SSI0XDAT0) may be enabled as an output by the ROM bootloader if no code is present in the flash and the SSI0x (PA2, PA3,

PA5) receives a valid boot signature. Ensure that this condition will not occur if PA4 is to be connected directly to GND.

Terminal Configuration and Functions

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表 4-6. Connections for Unused Pins (continued)

ACCEPTABLE

PRACTICE

PREFERRED

PRACTICE

FUNCTION

SIGNAL NAME

PIN NUMBER

OSC0

OSC1

NC

GND

88

89

NC

System Control

Pull up to VDD with 0 to

RST

VDD

NC

100-kΩ resistor.⁽³⁾

70

93

94

Pull down to GND with

USB0DM / PL7

USB0DP / PL6

1-kΩ resistor.⁽⁴⁾

USB

Pull down to GND with

NC

1-kΩ resistor.⁽⁴⁾

(3) For details, see the System Control chapter of the SimpleLink™ MSP432E4 Microcontrollers Technical Reference Manual

(4) The ROM bootloader may configure these pins as USB pins if no code is present in the flash. Therefore, they should not be connected

directly to ground.

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ZHCSH09 –OCTOBER 2017

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1) (2)

MIN

0

MAX

4

UNIT

V

V_DD

V_DDsupply voltage

V_DDA

V_DDAsupply voltage

0

4

V

V_BAT

V_BATbattery supply voltage

V_BATbattery supply voltage ramp time

0

4

V

V_BATRMP

V_{IN_GPIO}

I_GPIOMAX

T_S

0

0.7

4

V/µs

V

(3)

Input voltage

–0.3

Maximum current per output pin

Unpowered storage temperature range

Maximum junction temperature

64

150

125

mA

°C

–65

T_JMAX

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Voltages are measured with respect to GND.

(3) Applies to static and dynamic signals including overshoot.

5.2 ESD Ratings

over operating free-air temperature range (unless otherwise noted)

VALUE

±2000

±500

UNIT

(1) (2)

Human-body model (HBM), per ANSI/ESDA/JEDEC JS‑001

Charged-device model (CDM), per JEDEC specification JESD22‑C101

V_(ESD)

Electrostatic discharge

V

(3)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as

±2000 V may actually have higher performance.

(2) All pins are HBM compliant to ±2000 V for all combinations as per JESD22-A114F, except for the following stress combinations:

•

The Ethernet EN0RXIN, EN0TXON, EN0RXIP, and EN0TXOP pins to each other.

The GPIO pins PM4, PM5, PM6, and PM7 to other pins.

These exceptions are compliant to 500 V and do not require any special handling beyond typical ESD control procedures during

assembly operations per JEDEC publication JEP155. These pins do meet the 500-V CDM specification.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V

may actually have higher performance.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

–40

MAX

105

UNIT

°C

T_AAmbient operating temperature range

T_JJunction operating temperature range

Extended temperature

125

°C

5.4 Recommended DC Operating Conditions

over operating free-air temperature (unless otherwise noted)

MIN

2.97

1.14

0.85

NOM

3.3

MAX

3.63

1.32

0.95

UNIT

V_DD

V_DDsupply voltage

V_DDAsupply voltage

V

(1)

V_DDA

V_DDC

V_DDCDS

3.3

V_DDCsupply voltage, run mode

1.2

V_DDCsupply voltage, deep-sleep mode

(1) To ensure proper operation, power on V_DDAbefore V_DDif sourced from different supplies, or connect V_DDAto the same supply as V_DD

.

No restriction exists for powering off.

5.5 Recommended GPIO Operating Characteristics

The following sections describe the recommended GPIO operating characteristics for the device.

Two types of pads are provided on the device:

Specifications

35

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

•

Fast GPIO pads: These pads provide variable, programmable drive strength and optimized voltage

output levels.

Slow GPIO pads: These pads provide 2-mA drive strength and are designed to be sensitive to voltage

inputs. The PJ1 GPIOs port pins are slow GPIO pads. All other GPIOs have a fast GPIO pad type.

注

Port pins PL6 and PL7 operate as fast GPIO pads, but have 4-mA drive capability only.

GPIO register controls for drive strength, slew rate and open drain have no effect on these

pins. The registers which have no effect are as follows: GPIODR2R, GPIODR4R,

GPIODR8R, GPIODR12R, GPIOSLR, and GPIOODR.

注

Port pins PM[7:4] operate as fast GPIO pads but support only 2-, 4-, 6-, and 8-mA drive

capability. 10- and 12-mA drive are not supported. All standard GPIO register controls,

except for the GPIODR12R register, apply to these port pins.

5.6 Recommended Fast GPIO Pad Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

4

UNIT

V

0.65 ×

V_DD

V_IH

I_IH

Fast GPIO high-level input voltage

Fast GPIO high-level input current

Fast GPIO low-level input voltage

300

nA

V

0.35 ×

V_DD

V_IL

0

(1)

I_IL

Fast GPIO low-level input current

Fast GPIO input hysteresis

–200

0.40

nA

V

V_HYS

V_OH

V_OL

0.49

2.4

Fast GPIO high-level output voltage

Fast GPIO low-level output voltage

V

2-mA drive

4-mA drive

8-mA drive

10-mA drive

12-mA drive

2-mA drive

4-mA drive

8-mA drive

10-mA drive

12-mA drive

2.0

4.0

(2)

I_OH

Fast GPIO high-level source current, V_OH= 2.4 V

8.0

mA

10.0

12.0

2.0

4.0

8.0

(2)

10.0

12.0

I_OL

Fast GPIO low-level sink current, V_OL= 0.4 V

mA

12-mA drive

overdriven to

18 mA

18.0

(1) Output, pullup, and pulldown are disabled; only input is enabled.

(2) I_Ospecifications reflect the maximum current where the corresponding output voltage meets the V_OHor V_OLthresholds. I_Ocurrent can

exceed these limits (subject to absolute maximum ratings).

5.7 Recommended Slow GPIO Pad Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

4

UNIT

V

0.65 ×

V_DD

V_IH

I_IH

Slow GPIO high-level input voltage

Slow GPIO high-level input current

4.1

nA

36

Specifications

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

Recommended Slow GPIO Pad Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

0.35 ×

V_DD

V_IL

Slow GPIO low-level input voltage

0

V

(1)

I_IL

Slow GPIO low-level input current

Slow GPIO input hysteresis

–1

nA

V

V_HYS

V_OH

V_OL

I_OH

I_OL

0.49

2.4

Slow GPIO high-level output voltage

V

Slow GPIO low-level output voltage

0.4

V

Slow GPIO high-level source current, V_OH= 2.4 V, 2-mA drive

Slow GPIO low-level sink current, V_OL= 0.4 V ⁽²⁾, 2-mA drive

2.0

mA

(1) Output, pullup, and pulldown are disabled; only input is enabled.

(2) I_Ospecifications reflect the maximum current where the corresponding output voltage meets the V_OHor V_OLthresholds. I_Ocurrent can

exceed these limits (subject to absolute maximum ratings).

5.8 GPIO Current Restrictions

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

NOM

MAX

112

97.6

112

80

UNIT

mA

I_MAXL

I_MAXB

I_MAXR

I_MAXT

Cumulative maximum GPIO current per side, left

Cumulative maximum GPIO current per side, bottom

(2)

mA

(2)

Cumulative maximum GPIO current per side, right

mA

(2)

Cumulative maximum GPIO current per side, top

mA

(1) Based on design simulations, not tested in production.

(2) Sum of sink and source current for GPIOs as listed in 表 5-1.

表 5-1. Maximum GPIO Package Side Assignments

SIDE

Left

GPIOs

PC[4-7], PD[0-3], PQ[0-3], PE[0-3], PK[0-3], PN[4-5], PH[0-3]

Bottom

Right

Top

PA[0-7], PF[0-4],PG[0-1], PK[4-7]

PM[0-7], PL[0-7], PB[0-3]

PC[0-3], PQ[4], PP[0-5], PN[0-5], PJ[0-1], PB[4-5], PE[4-5], PD[4-7]

5.9 I/O Reliability

For typical continuous drive applications, I/O pins configured in the range from 2 mA to 12 mA and

operating at –40°C to 85°C meet the standard 10-year lifetime reliability. If a continuous current sink of 18

mA is required, then operation is limited to 0 to 75°C to meet the standard 10-year reliability.

At 105°C, I/O pins configured for continuous drive meet the standard 2.5-year lifetime reliability.

In typical switching applications (40% switch rate) operating at –40°C to 85°C, all I/O configurations except

2 mA meet the standard 10-year lifetime reliability with 50-pF loading. By limiting the capacitive loading to

20 pF for an I/O configured to 2 mA, the 10-year lifetime reliability can be met at –40°C to 85°C.

In typical switching applications (40% switch rate) operating at 105°C, all I/O configurations except 2 mA

meet the standard 2.5-year lifetime reliability. By reducing the capacitive loading to 20 pF with a typical

switching rate at 105°C, a 2-mA I/O configuration meets a 2.5-year lifetime reliability.

Specifications

37

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

5.10 Current Consumption

over operating free-air temperature (unless otherwise noted)

(1)

SYSTEM CLOCK

TYP

MAX

PARAMETER

TEST CONDITIONS

UNIT

CLOCK

SOURCE

105°C

FREQ

120 MHz

60 MHz

–40°C

96.4

25°C

85°C

107.2

78.6

105°C

108.7

79.9

85°C

129.9

100.3

(2)

MOSC with

PLL

105.3

76.6

140.0

112.5

V_DD= 3.3 V,

V_DDA= 3.3 V,

Peripherals = All on

including MAC and PHY

MOSC with

PLL

67.4

16 MHz

1 MHz

PIOSC

11.9

5.75

24.4

10.9

25.5

12.1

26.7

13.3

45.0

31.3

56.4

42.6

MOSC with

PLL

120 MHz

60 MHz

69.9

40.9

77.8

49.2

79.6

50.9

80.8

52.1

98.8

69.2

108.4

80.8

V_DD= 3.3 V,

V_DDA= 3.3 V,

Peripherals = All on

including MAC but not

PHY

MOSC with

PLL

16 MHz

1 MHz

PIOSC

11.3

5.10

23.6

10.1

25.0

11.5

26.2

12.7

43.1

29.3

54.3

40.5

Run mode

(flash loop)

MOSC with

PLL

120 MHz

60 MHz

68.1

40.0

76.0

48.2

77.6

49.8

78.6

50.8

96.6

67.9

106.0

79.2

V_DD= 3.3 V,

V_DDA= 3.3 V,

Peripherals = All on

except MAC and PHY

MOSC with

PLL

16 MHz

1 MHz

PIOSC

11.1

5.07

23.3

10.1

24.6

11.3

25.6

12.3

42.5

29.0

53.3

39.8

MOSC with

PLL

120 MHz

60 MHz

35.2

23.2

39.1

29.4

40.4

30.7

41.5

31.7

55.8

45.8

65.3

55.5

V_DD= 3.3 V,

V_DDA= 3.3 V,

MOSC with

PLL

Peripherals = All off

16 MHz

1 MHz

PIOSC

7.38

4.12

17.9

9.13

19.0

10.3

20.0

11.4

34.5

25.7

44.1

35.5

I_{DD_RUN}

mA

MOSC with

PLL

120 MHz

60 MHz

93.8

66.9

103.6

76.7

111.6

78.7

113.2

80.0

133.4

100.0

144.6

111.9

V_DD= 3.3 V,

V_DDA= 3.3 V,

Peripherals = All on

including MAC and PHY

MOSC with

PLL

16 MHz

1 MHz

PIOSC

12.6

5.73

19.0

10.6

20.1

11.7

21.3

12.8

39.1

30.9

50.3

42.2

MOSC with

PLL

120 MHz

60 MHz

67.2

40.3

76.1

49.2

84.0

50.9

85.4

52.2

102.3

68.9

113.0

80.2

V_DD= 3.3 V,

V_DDA= 3.3 V,

Peripherals = All on

including MAC but not

PHY

MOSC with

PLL

16 MHz

1 MHz

PIOSC

11.9

5.08

18.2

9.79

19.6

11.2

20.8

12.3

37.2

28.9

48.2

40.1

Run mode

(SRAM loop)

MOSC with

PLL

120 MHz

60 MHz

65.4

39.4

74.3

48.2

82.0

49.8

83.2

50.9

100.1

67.6

110.6

78.6

V_DD= 3.3 V,

V_DDA= 3.3 V,

Peripherals =All on

except MAC and PHY

MOSC with

PLL

16 MHz

1 MHz

PIOSC

11.7

5.05

17.9

9.75

19.2

11.0

20.2

11.9

36.6

28.6

47.2

39.4

MOSC with

PLL

120 MHz

60 MHz

35.4

23.4

43.3

29.4

44.7

30.7

45.8

31.7

59.8

45.5

69.0

54.9

V_DD= 3.3 V,

V_DDA= 3.3 V,

MOSC with

PLL

Peripherals = All off

16 MHz

1 MHz

PIOSC

7.08

4.60

12.4

8.78

13.6

10.0

14.6

11.0

28.7

25.3

38.0

34.9

(1) Section 5.11 lists the current consumption that specific peripherals contribute to the run mode current consumption in Section 5.10. If

these peripherals are not powered, then the peripheral current consumption can be subtracted from the run mode consumption in

Section 5.10.

(2) Applicable to extended temperature devices only.

38

Specifications

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

Current Consumption (continued)

(1)

over operating free-air temperature (unless otherwise noted)

SYSTEM CLOCK

TYP

MAX

PARAMETER

TEST CONDITIONS

UNIT

CLOCK

SOURCE

105°C

FREQ

120 MHz

60 MHz

–40°C

82.8

25°C

94.8

69.2

85°C

96.8

71.2

105°C

98.1

85°C

(2)

MOSC with

PLL

117.9

91.8

129.1

102.9

V_DD= 3.3 V,

V_DDA= 3.3 V,

Peripherals = All on

including MAC and PHY,

LDO = 1.2 V

MOSC with

PLL

60.8

72.3

16 MHz

1 MHz

PIOSC

11.2

5.10

16.8

10.3

18.1

11.5

19.1

12.6

35.4

28.9

45.9

39.6

(3)

PIOSC

MOSC with

PLL

120 MHz

60 MHz

56.2

34.4

67.4

41.9

69.1

43.4

70.3

44.5

87.1

60.7

97.8

71.6

V_DD= 3.3 V,

V_DDA= 3.3 V,

Peripherals = All on

including MAC but not

PHY,

MOSC with

PLL

(3)

16 MHz

1 MHz

PIOSC

10.6

4.47

16.2

9.60

17.5

10.9

18.5

12.0

34.5

28.0

45.1

38.7

LDO = 1.2 V

(3)

Sleep mode

PIOSC

(FLASHPM =

0x0)

MOSC with

PLL

120 MHz

60 MHz

54.4

33.5

65.6

40.9

67.1

42.3

68.1

43.2

84.9

59.4

95.4

70.0

V_DD= 3.3 V,

V_DDA= 3.3 V,

Peripherals = All on

except MAC and PHY,

LDO = 1.2 V

MOSC with

PLL

(3)

16 MHz

1 MHz

PIOSC

10.4

4.44

15.9

9.56

17.1

10.7

17.9

11.6

33.9

27.7

44.1

38.0

(3)

PIOSC

MOSC with

PLL

120 MHz

60 MHz

22.0

16.3

28.6

22.0

29.8

23.2

30.7

24.1

44.1

37.5

53.1

46.6

V_DD= 3.3 V,

MOSC with

PLL

V_DDA= 3.3 V,

Peripherals = All off,

LDO = 1.2 V

(3)

16 MHz

1 MHz

PIOSC

5.37

4.37

10.4

8.60

11.5

9.71

12.4

10.6

26.1

24.6

35.1

33.9

(3)

PIOSC

I_{DD_SLEEP}

mA

MOSC with

PLL

120 MHz

60 MHz

86.5

61.6

89.0

63.4

91.2

65.6

92.5

66.7

112.1

86.0

123.5

97.2

V_DD= 3.3 V,

V_DDA= 3.3 V,

Peripherals = All on

including MAC and PHY,

LDO = 1.2 V

MOSC with

PLL

(3)

16 MHz

1 MHz

PIOSC

10.4

4.45

11.1

4.49

12.4

5.83

13.5

6.98

29.8

23.4

40.4

34.2

(3)

PIOSC

MOSC with

PLL

120 MHz

60 MHz

59.9

35.1

61.7

36.1

63.4

37.8

64.7

38.9

81.3

54.9

92.1

66.0

V_DD= 3.3 V,

V_DDA= 3.3 V,

Peripherals = All on

including MAC but not

PHY,

MOSC with

PLL

(3)

16 MHz

1 MHz

PIOSC

9.75

3.82

10.4

3.82

11.8

5.25

12.9

6.38

28.9

22.5

39.6

33.4

LDO = 1.2 V

(3)

Sleep mode

(FLASHPM =

0x2)

PIOSC

MOSC with

PLL

120 MHz

60 MHz

58.1

34.2

59.9

35.1

61.4

36.7

62.5

37.6

79.1

53.6

89.7

64.4

V_DD= 3.3 V,

V_DDA= 3.3 V,

Peripherals = All on

except MAC and PHY,

LDO = 1.2 V

MOSC with

PLL

(3)

16 MHz

1 MHz

PIOSC

9.50

3.79

10.1

3.78

11.4

5.06

12.3

5.96

28.3

22.2

38.6

32.7

(3)

PIOSC

MOSC with

PLL

120 MHz

60 MHz

22.0

15.7

22.8

16.2

24.1

17.5

25.1

18.5

38.2

31.7

47.4

40.9

V_DD= 3.3 V,

MOSC with

PLL

V_DDA= 3.3 V,

Peripherals = All off,

LDO = 1.2 V

(3)

16 MHz

1 MHz

PIOSC

4.50

3.00

4.60

2.80

5.80

4.10

6.80

5.20

20.5

19.1

29.8

28.7

(3)

PIOSC

(3) If the MOSC is the source of the run-mode system clock and is powered down in sleep mode, wake time is increased by t_{MOSC_SETTLE}

.

Specifications

39

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

Current Consumption (continued)

(1)

over operating free-air temperature (unless otherwise noted)

SYSTEM CLOCK

TYP

MAX

PARAMETER

TEST CONDITIONS

UNIT

CLOCK

SOURCE

105°C

FREQ

–40°C

25°C

85°C

105°C

85°C

(2)

V_DD= 3.3 V,

16 MHz

PIOSC

9.74

9.78

10.8

11.6

24.1

32.1

25.3

22.7

20.7

20.1

14.9

13.4

10.8

V_DDA= 3.3 V,

Peripherals = All on,

LDO = 1.2 V

30 kHz

16 MHz

30 kHz

16 MHz

30 kHz

16 MHz

30 kHz

LFIOSC

PIOSC

LFIOSC

PIOSC

LFIOSC

PIOSC

LFIOSC

2.60

4.53

2.83

4.05

3.83

4.88

1.69

7.97

2.79

3.61

0.954

4.60

5.53

2.46

8.48

3.29

4.01

1.36

17.1

15.9

13.3

15.3

10.0

9.50

6.86

V_DD= 3.3 V,

V_DDA= 3.3 V,

Peripherals = All off,

LDO = 1.2 V

Deep-sleep

0.614

5.21

0.762

7.33

mode

(FLASHPM =

0x2)

I_{DD_DEEPSLEEP}

mA

V_DD= 3.3 V,

V_DDA= 3.3 V,

Peripherals = All on,

LDO = 0.9 V

2.02

2.16

V_DD= 3.3 V,

V_DDA= 3.3 V,

Peripherals = All off,

LDO = 0.9 V

1.08

3.10

0.367

0.454

(4)

MOSC with

PLL

120 MHz

60 MHz

2.61

2.66

2.68

2.66

3.03

3.04

3.35

3.10

V_DD= 3.3 V,

MOSC with

PLL

All run modes

V_DDA= 3.3 V,

Peripherals = All on

16 MHz

1 MHz

PIOSC

2.45

2.49

2.48

2.50

2.48

2.85

2.84

2.95

2.90

I_{DDA_RUN}, I_{DDA_SLEEP}

mA

MOSC with

PLL

120 MHz

60 MHz

0.227

0.229

0.232

0.270

0.267

0.250

0.559

0.579

0.650

0.600

V_DD= 3.3 V,

V_DDA= 3.3 V,

Peripherals = All off

MOSC with

PLL

All sleep

modes

16 MHz

1 MHz

PIOSC

0.228

0.227

2.45

0.229

0.227

2.48

0.265

0.267

2.50

0.251

0.247

2.48

0.545

0.549

2.84

0.575

0.555

2.90

V_DD= 3.3 V,

16 MHz

V_DDA= 3.3 V,

Peripherals = All on,

LDO = 1.2 V

30 kHz

16 MHz

30 kHz

16 MHz

30 kHz

16 MHz

30 kHz

LFIOSC

PIOSC

LFIOSC

PIOSC

LFIOSC

PIOSC

LFIOSC

2.45

0.226

0.228

2.14

2.48

0.227

2.42

2.50

0.265

0.272

2.44

2.48

0.249

0.247

2.42

2.85

0.558

2.78

2.90

0.635

0.600

2.88

V_DD= 3.3 V,

V_DDA= 3.3 V,

Peripherals = All off,

LDO = 1.2 V

Deep-sleep

mode

(FLASHPM =

0x2)

I_{DDA_DEEPSLEEP}

mA

V_DD= 3.3 V,

V_DDA= 3.3 V,

Peripherals = All on,

2.44

2.42

2.44

2.42

2.86

2.88

(4)

LDO = 0.9 V

V_DD= 3.3 V,

V_DDA= 3.3 V,

0.216

0.223

0.166

0.167

0.209

0.193

0.189

0.563

0.508

0.580

Peripherals = All off,

(4)

LDO = 0.9 V

V_BAT= 3.0 V V_DD= 0 V,

V_DDA= 0 V,

System clock = OFF,

Hibernate module =

32.768 kHz

Hibernate

mode (external

wake, RTC

disabled)

I_{HIB_NORTC}

1.04

1.12

1.20

1.29

1.44

1.54

1.69

1.82

1.62

1.75

2.14

2.33

µA

V_BAT= 3.0 V,

V_DD= 0 V,

V_DDA= 0 V,

System clock = OFF,

Hibernate module =

32.768 kHz

Hibernate

mode (RTC

enabled)

I_{HIB_RTC}

(4) See the System Control chapter of the MSP432E4 SimpleLink™ Microcontrollers Technical Reference Manual for information on

lowering the LDO voltage to 0.9 V.

40

Specifications

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

Current Consumption (continued)

(1)

over operating free-air temperature (unless otherwise noted)

SYSTEM CLOCK

TYP

MAX

PARAMETER

TEST CONDITIONS

UNIT

CLOCK

SOURCE

105°C

FREQ

–40°C

25°C

85°C

105°C

85°C

(2)

V_BAT= 3.0 V,

V_DD= 3.3 V,

V_DDA= 3.3 V,

System clock = OFF,

Hibernate module =

32.768 kHz

Hibernate

mode

(VDD3ON

mode, tamper

enabled)

6.78

7.99

17.0

22.1

31.0

28.9

46.2

32.0

I_{HIB_VDD3ON}

µA

V_BAT= 3.0 V,

V_DD= 3.3 V,

V_DDA= 3.3 V,

System clock = OFF,

Hibernate module =

32.768 kHz

Hibernate

mode

(VDD3ON

mode, tamper

disabled)

5.42

6.39

15.4

17.8

5.11 Peripheral Current Consumption

over operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SYSTEM CLOCK

TYP

UNIT

USB (including USB PHY) run mode

current

V_DD= 3.3 V,

V_DDA= 3.3 V

I_DDUSB

120 MHz (MOSC with PLL)

4.0

1.9

30

mA

V_DD= 3.3 V,

V_DDA= 3.3 V

I_DDEMAC

I_DDEMACPHY

Ethernet MAC run mode current

mA

V_DD= 3.3 V,

V_DDA= 3.3 V

Ethernet MAC and PHY run mode current

5.12 LDO Regulator Characteristics

over operating free-air temperature (unless otherwise noted)

PARAMETER

MIN

2.5

0

TYP

MAX

4.0

UNIT

µF

C_LDO

ESR

External filter capacitor size for internal power supply⁽¹⁾

Filter capacitor equivalent series resistance

Filter capacitor equivalent series inductance

LDO output voltage, run mode

100

0.5

mΩ

nH

ESL

V_LDO

I_INRUSH

1.13

50

1.2

1.27

250

V

Inrush current

mA

(1) Connect the capacitor as close as possible to pin 115.

Specifications

41

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

5.13 Power Dissipation

over operating free-air temperature (unless otherwise noted)

(1) (2)

PARAMETER

T_A

T_J

MIN

MAX

452

UNIT

Extended temperature device power

dissipation

105°C (extended

temperature part)

125°C (extended

temperature part)

P_DE

mW

(1) If the device exceeds the power dissipation value shown, then modifications such as heat sinks or fans must be used to conform to the

limits shown.

(2) A larger power dissipation allowance can be achieved by lowering T_Aas long as T_JMAXshown in Section 5.1 is not exceeded.

5.14 Thermal Resistance Characteristics, 128-Pin PDT (TQFP) Package

over operating free-air temperature range (unless otherwise noted)

THERMAL METRIC

VALUE

44.2

UNIT

°C/W

(1)

θ_JA

θ_JB

θ_JC

Ψ_JT

Ψ_JB

Thermal resistance (junction to ambient)

(1)

Thermal resistance (junction to board)

22.4

(1)

Thermal resistance (junction to case)

6.8

Thermal metric (junction to top of package)

Thermal metric (junction to board)

0.2

22.1

(2)

T_C+ (P × Ψ_JT

T_PCB+ (P × Ψ_JB

)

(3)

)

T_J

Junction temperature formula

°C

(4)

T_A+ (P × θ_JA

)

(5) (6)

T_B+ (P × θ_JB

)

(1) Junction to ambient thermal resistance (θ_JA), junction to board thermal resistance (θ_JB), and junction to case thermal resistance (θ_JC

)

numbers are determined by a package simulator.

(2) T_Cis the case temperature and P is the device power consumption.

(3) T_PCBis the temperature of the board acquired by following the steps listed in the EAI/JESD 51-8 standard summarized in Semiconductor

and IC Package Thermal Metrics. P is the device power consumption.

(4) Because θ_JAis highly variable and based on factors such as board design, chip size, pad size, altitude, and external ambient

temperature, TI recommends using the equations that contain Ψ_JTand Ψ_JBfor best results.

(5) T_Bis temperature of the board.

(6) θ_JBis not a pure reflection of the internal resistance of the package because it includes the resistance of the testing board and

environment. TI recommends using equations that contain Ψ_JTand Ψ_JBfor best results.

42

Specifications

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

5.15 Timing and Switching Characteristics

5.15.1 Load Conditions

表 5-2 shows the load conditions used for timing measurements, and 表 5-2 lists the load values for the

specified signals.

C_L

图 5-1. Load Conditions

表 5-2. Load Conditions

SIGNALS

EPI0S[35:0] SDRAM interface

EPI0S[35:0] general-purpose interface

EPI0S[35:0] host-bus interface

EPI0S[35:0] PSRAM interface

All other digital I/O signals

LOAD VALUE (C_L)

30 pF

40 pF

50 pF

5.15.2 Power Supply Sequencing

To ensure proper operation, power on V_DDAbefore V_DDif sourced from different supplies, or connect V_DDA

to the same supply as V_DD. No restriction exists for powering off.

5.15.2.1 Power and Brownout

表 5-3. Power and Brownout Levels

over operating free-air temperature (unless otherwise noted)

NO.

P1

PARAMETER

MIN

TYP

MAX

∞

UNIT

µs

t_{VDDA_RISE}

t_{VDD_RISE}

t_{VDDC_RISE}

Analog supply voltage (V_DDA) rise time

I/O supply voltage (V_DD) rise time

Core supply voltage (V_DDC) rise time

Power-on reset threshold (rising edge)

Power-on reset threshold (falling edge)

Power-on reset hysteresis

P2

∞

µs

P3

10

1.98

1.84

0.06

2.67

2.71

2.65

2.67

2.77

0.85

0.71

150

2.72

2.56

0.24

2.97

2.89

2.90

2.85

2.95

1.10

0.85

µs

2.35

2.20

0.15

2.82

2.80

2.76

2.86

0.95

0.80

P4

V_POR

V

P5

P6

V_{DDA_POK}

V_DDApower-OK threshold (rising edge)

V_DDAbrownout reset threshold

V

V_{DDA_BOR0}

V_DDpower-OK threshold (rising edge)

V_DDpower-OK threshold (falling edge)

V_DDbrownout reset threshold

P7

P8

P9

V_{DD_POK}

V_{DD_BOR0}

V_{DDC_POK}

V

V_DDCpower-OK threshold (rising edge)

V_DDCpower-OK threshold (falling edge)

Specifications

43

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

5.15.2.1.1 V_DDALevels

The V_DDAsupply has three monitors:

•

Power-on reset (POR)

Power-OK (POK)

Brownout reset (BOR)

The POR monitor is used to keep the analog circuitry in reset until the V_DDAsupply reaches the correct

range for the analog circuitry to begin operating. The POK monitor is used to keep the digital circuitry in

reset until the V_DDApower supply is at an acceptable operational level. The digital reset is only released

when the Power-On Reset has deasserted and the Power-OK monitor for each supply indicates that

power levels are in operational ranges. The BOR monitor is used to generate a reset to the device or

assert an interrupt if the V_DDAsupply drops below its operational range.

注

V_DDABOR and V_DDBOR events are a combined BOR to the system logic, such that if either

BOR event occurs, the following bits are affected:

•

The BORRIS bit in the Raw Interrupt Status (RIS) register, System Control offset 0x050

The BORMIS bit in the Masked Interrupt Status and Clear (MISC) register, System

Control offset 0x058. This bit is set only if the BORIM bit in the Interrupt Mask Control

(IMC) register has been set.

•

The BOR bit in the Reset Cause (RESC) register, System Control offset 0x05C. This bit

is set only if either of the BOR events have been configured to initiate a reset.

In addition, the following bits control both BOR events:

•

The BORIM bit in the Interrupt Mask Control (IMC) register, System Control offset 0x054

The VDDA_UBOR0 and VDD_UBOR0 bits in the Power-Temperature Cause (PWRTC)

register

See the System Control chapter of the MSP432E4 SimpleLink™ Microcontrollers Technical

Reference Manual for more information on how to configure these registers.

图 5-2 shows the relationship between V_DDA, POK, POR, and a BOR event.

P1

VDDA_MIN

P6

P5_RISE

P4

1

0

1

0

1

0

图 5-2. Power and Brownout Assertions vs V_DDALevels

44

Specifications

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

5.15.2.1.2 V_DDLevels

The V_DDsupply has two monitors:

Power-OK (POK)

Brownout reset (BOR)

•

The POK monitor is used to keep the digital circuitry in reset until the V_DDpower supply reaches an

acceptable operational level. The digital reset is only released when the POR has deasserted and the

POK monitor for each supply indicates that power levels are in operational ranges. The BOR monitor is

used to generate a reset to the device or assert an interrupt if the V_DDsupply drops below its operational

range.

注

V_DDABOR and V_DDBOR events are a combined BOR to the system logic, such that if either

BOR event occurs, the following bits are affected:

•

The BORRIS bit in the Raw Interrupt Status (RIS) register, System Control offset 0x050

The BORMIS bit in the Masked Interrupt Status and Clear (MISC) register, System

Control offset 0x058. This bit is set only if the BORIM bit in the Interrupt Mask Control

(IMC) register has been set.

•

The BOR bit in the Reset Cause (RESC) register, System Control offset 0x05C. This bit

is set only if either of the BOR events have been configured to initiate a reset.

In addition, the following bits control both BOR events:

•

The BORIM bit in the Interrupt Mask Control (IMC) register, System Control offset 0x054

The VDDA_UBOR0 and VDD_UBOR0 bits in the Power-Temperature Cause (PWRTC)

register

See the System Control chapter of the MSP432E4 SimpleLink™ Microcontrollers Technical

Reference Manual for more information on how to configure these registers.

图 5-3 shows the relationship between V_DD, POK, POR, and a BOR event.

P2

VDD_MIN

P8

P7_RISE

P7_FALL

1

0

1

0

图 5-3. Power and Brownout Assertions vs V_DDLevels

Specifications

45

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

5.15.2.1.3 V_DDCLevels

The V_DDCsupply has one monitor, the Power-OK (POK). The POK monitor is used to keep the digital

circuitry in reset until the V_DDCpower supply reaches an acceptable operational level. The digital reset is

only released when the power-on reset has deasserted and the POK monitor for each supply indicates

that power levels are in operational ranges. 图 5-4 shows the relationship between POK and V_DDC

.

P3

1.2V

P9_RISE

P9_FALL

1

0

图 5-4. POK Assertion vs V_DDC

5.15.2.1.4 V_DDGlitch Response

图 5-5 shows the response of the BOR and the POR circuit to glitches on the VDD supply.

图 5-5. POR-BOR V_DDGlitch Response

5.15.2.1.5 V_DDDroop Response

图 5-6 shows the response of the BOR and the POR monitors to a drop on the VDD supply.

图 5-6. POR-BOR V_DDDroop Response

5.15.3 Reset Timing

表 5-4 lists the reset characteristics.

46

Specifications

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

表 5-4. Reset Characteristics

over operating free-air temperature (unless otherwise noted)

NO.

PARAMETER

MIN

TYP

MAX

126

UNIT

R1

t_DPORDLY

Digital POR to internal reset assertion delay (see 图 5-7)

Standard internal reset time

Internal reset time with recovery code repair (program or erase)⁽³⁾

BOR0 to internal reset assertion delay ⁽⁵⁾(see 图 5-8)

0.44

µs

14

16

6400⁽⁴⁾

(1) (2)

R2

t_IRTOUT

ms

24.4

0.44

(1)

R3

R4

R5

R6

t_BOR0DLY

t_RSTMIN

125

µs

0.25⁽⁶⁾or

100⁽⁷⁾

Minimum RST pulse duration

t_IRHWDLY

RST to internal reset assertion delay (see 图 5-9)

0.85

Internal reset time-out after software-initiated system reset (see 图

(1)

t_IRSWR

2.44

5-10)

(1)

R7

R8

t_IRWDR

t_IRMFR

Internal reset time-out after watchdog reset (see 图 5-11)

Internal reset time-out after MOSC failure reset (see 图 5-12)

2.44

µs

(1) These values are based on simulation.

(2) This is the delay from the time POR is released until the reset vector is fetched.

(3) This parameter applies only in situations where a power-loss or brownout event occurs during an EEPROM program or erase operation,

and EEPROM must be repaired (which is a rare case). For all other sequences, there is no change to normal POR timing. This delay is

in addition to other POR delays.

(4) This value represents the maximum internal reset time when the EEPROM reaches its endurance limit.

(5) Timing values depend on the V_DDpower-down ramp rate.

(6) Standard operation

(7) Deep-sleep operation with PIOSC powered down

Digital POR

R₁

R2

Reset

(Internal)

图 5-7. Digital Power-On Reset Timing

The digital power-on reset is released only when the analog power-on reset has deasserted and the

Power-OK monitor for each supply indicates that power levels are in operational ranges.

BOR

R3

R2

Reset

(Internal)

图 5-8. Brownout Reset Timing

Specifications

47

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

R₄

RST

(Package Pin)

R₅

R₂

Reset

(Internal)

图 5-9. External Reset Timing (RST)

Software Reset

R₆

Reset

(Internal)

图 5-10. Software Reset Timing

Watchdog Reset

R₇

Reset

(Internal)

图 5-11. Watchdog Reset Timing

MOSC Fail Reset

R₈

Reset

(Internal)

图 5-12. MOSC Failure Reset Timing

48

Specifications

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

5.15.4 Clock Specifications

The following sections provide specifications on the various clock sources and mode.

5.15.4.1 PLL Specifications

表 5-5 lists the PLL characteristics.

注

If the integrated Ethernet PHY is used, f_{REF_XTAL}and f_{REF_EXT}must be 25 MHz.

表 5-5. Phase Locked Loop (PLL) Characteristics

over operating free-air temperature (unless otherwise noted)

PARAMETER

MIN

5

MAX

25

UNIT

MHz

f_{REF_XTAL}

f_{REF_EXT}

f_PLLR

Crystal reference

External clock reference

5

25

PLL VCO frequency at 1.2 V⁽¹⁾

PLL VCO frequency at 0.9 V⁽²⁾

100

480

f_PLLS

512 ×

(reference

clock period)

Enabling the PLL, when PLL is transitioning from power down to

power up

128 ×

(reference

clock period)

When the PLL VCO frequency is changed (PLL is already

enabled)

t_READY

PLL lock time

µs

128 ×

(reference

Changing the OSCSRC between MOSC and PIOSC

clock period)

(1) PLL frequency is manually calculated using the values in the PLLFREQ0 and PLLFREQ1 registers.

(2) If the LDO is dropped to 0.9 V, the system must be run 1/4 of the maximum frequency at most. The Q value in the PLLFREQ1 register

must be set to 0x3 rather than using the PSYSDIV field in the RSCLKCFG register for the divisor.

5.15.4.1.1 PLL Configuration

The PLL is disabled by default during power-on reset and is enabled later by software if required. Software

specifies the output divisor to set the system clock frequency and enables the PLL to drive the output. The

PLL is controlled using the PLLFREQ0, PLLFREQ1, and PLLSTAT registers. Changes made to these

registers do not become active until after the NEWFREQ bit in the RSCLKCFG register is enabled. The

clock source for the main PLL is selected by configuring the PLLSRC field in the Run and Sleep Clock

Configuration (RSCLKCFG) register. The PLL allows for the generation of system clock frequencies in

excess of the reference clock provided. The reference clocks for the PLL are the PIOSC and the MOSC.

The PLL is controlled by two registers, PLLFREQ0 and PLLFREQ1. The PLL VCO frequency (f_VCO) is

determined through 公式 1.

f_VCO= f_IN× MDIV

where

•

f_IN= f_XTAL/ (Q+1)(N+1) or f_PIOSC/ (Q+1)(N+1)

MDIV = MINT + (MFRAC / 1024)

(1)

The Q and N values are programmed in the PLLFREQ1 register. To reduce jitter, program MFRAC to 0x0.

When the PLL is active, the system clock frequency (SysClk) is calculated using 公式 2.

SysClk = f_VCO/ (1 + 1)

(2)

The PLL system divisor factor (PSYSDIV) must be set as 1. 表 5-6 lists examples of the system clock

frequency.

Specifications

49

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

表 5-6. Examples of System Clock Frequencies

System Clock

f_VCO(MHz)

Q

PSYSDIV + 1

(SYSCLK) Frequency

(MHz)

480

320

2

3

4

5

2

3

4

2

120

80

60

48

80

53

40

If the main oscillator provides the clock reference to the PLL, the translation provided by hardware and

used to program the PLL is available for software in the PLL Frequency n (PLLFREQn) registers. The

internal translation provides a translation within ±1% of the targeted PLL VCO frequency. 表 5-7 shows the

actual PLL frequency and error for a given crystal choice.

表 5-7 provides examples of the programming expected for the PLLFREQ0 and PLLFREQ1 registers. The

CRYSTAL FREQUENCY column specifies the input crystal frequency and the PLL FREQUENCY column

displays the PLL frequency given the values of MINT and N, when Q = 0.

表 5-7. Actual PLL Frequency⁽¹⁾

MINT

REFERENCE

FREQUENCY

(MHz)⁽²⁾

CRYSTAL

FREQUENCY (MHz)

PLL FREQUENCY

(MHz)

N

HEXADECIMAL

VALUE

DECIMAL VALUE

5

64

160

40

32

80

20

160

16

40

64

96

80

60

48

40

30

80

24

20

96

0x40

0x35

0x28

0x20

0x50

0x14

0xA0

0x10

0x28

0x40

0x60

0x50

0x3C

0x30

0x28

0x1E

0x50

0x18

0x14

0x60

0x0

0x2

0x0

0x2

0x0

0x8

0x0

0x2

0x4

0x0

0x2

0x0

0x4

5

2

320

480

6

8

10

12

16

18

20

24

25

5

10

4

16

2

20

8

5

6

8

10

12

16

18

20

24

25

10

12

16

6

20

24

5

(1) For all examples listed, Q = 0.

(2) For a given crystal frequency, N should be chosen such that the reference frequency is 4 to 30 MHz.

50

Specifications

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

5.15.4.2 PIOSC Specifications

表 5-8 lists the PIOSC characteristics.

表 5-8. PIOSC Clock Characteristics

PARAMETER

Factory calibration, 0°C to 105°C:

Internal 16-MHz precision oscillator frequency variance across voltage and

temperature range when factory calibration is used

MIN

NOM

MAX

±6%

±10%

±1%

1

UNIT

f_PIOSC

Factory calibration, –40°C to <0°C

Recalibration:

Internal 16-MHz precision oscillator frequency variance when recalibration is used

at a specific temperature

PIOSC start-up time⁽¹⁾

t_START

µs

(1) PIOSC start-up time is part of reset and is included in the internal reset time-out value (T_IRTOUT) in 表 5-4. The T_STARTvalue is based on

simulation.

5.15.4.3 Low-Frequency Oscillator Specifications

表 5-9 lists the characteristics of the low-frequency oscillator.

表 5-9. Low-Frequency Oscillator Characteristics

PARAMETER

MIN

NOM

MAX

UNIT

f_LFIOSC

Internal low-frequency oscillator frequency

10

33

75

kHz

5.15.4.4 Hibernation Low-Frequency Oscillator Specifications

表 5-10. Hibernation External Oscillator (XOSC) Input Characteristics

PARAMETER

Parallel resonance frequency

MIN

NOM

MAX

UNIT

kHz

pF

(1)

f_HIBXOSC

C₁, C₂

C_PKG

32.768

(2)

External load capacitance on XOSC0, XOSC1 pins

12

24

(2)

Device package stray shunt capacitance

0.5

pF

(2)

C_PCB

PCB stray shunt capacitance

pF

(2)

C_SHUNT

Total shunt capacitance

4

50

75

pF

(3)

Crystal effective series resistance, OSCDRV = 0

ESR

kΩ

(3)

Crystal effective series resistance, OSCDRV = 1

DL

Oscillator output drive level

0.25

µW

ms

(4)

(5)

t_START

Oscillator start-up time, when using a crystal

600

1500

CMOS input high level, when using an external oscillator with V_Supply

3.3 V

>

2.64

V_IH

V

CMOS input high level, when using an external oscillator with 1.8 V ≤

0.8 ×

V

_Supply≤ 3.3 V

CMOS input low level, when using an external oscillator with 1.8 V ≤

_Supply≤ 3.63 V

V_Supply

0.2 ×

V_Supply

(6)

V_IL

V

CMOS input buffer hysteresis, when using an external oscillator with 1.8 V

≤ V_Supply≤ 3.63 V

(6)

V_HYS

360

960

1390

70%

mV

DC_{HIBOSC_EXT}

External single-ended (bypass) reference duty cycle

30%

(1) The Hibernation XOSC pins are not fail-safe and must follow the limits in 节 5.15.9.1.2.

(2) See the additional information about the load capacitors following this table.

(3) Crystal ESR specified by crystal manufacturer.

(4) Oscillator start-up time is specified from the time the oscillator is enabled to when it reaches a stable point of oscillation such that the

internal clock is valid.

(5) Only valid for recommended supply conditions. Measured with OSCDRV bit set (high drive strength enabled, 24 pF).

(6) Specification is relative to the larger of V_DDor V_BAT

.

Specifications

51

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

Choose the load capacitors added on the board, C₁and C₂, such that 公式 3 is satisfied (see 表 5-10 for

typical values).

C_L= (C₁× C₂) / (C₁+ C₂) + C_SHUNT

where

•

C_L= load capacitance specified by crystal manufacturer

C_SHUNT= C_PKG+ C_PCB+ C₀(total shunt capacitance seen across XOSC0 and XOSC1)

C_PKG, C_PCBas measured across the XOSC0 and XOSC1 pins excluding the crystal

Clear the OSCDRV bit in the Hibernation Control (HIBCTL) register for C_1,2≤ 18 pF

Set the OSCDRV bit for C_1,2> 18 pF

C₀= Shunt capacitance of crystal specified by the crystal manufacturer

(3)

表 5-11 lists the characteristics of the Hibernation module low-frequency oscillator.

表 5-11. Hibernation Internal Low-Frequency Oscillator Clock Characteristics

PARAMETER

MIN

NOM

MAX

UNIT

f_HIBLFIOSC

Internal low-frequency hibernation oscillator frequency

10

33

90

kHz

5.15.4.5 Main Oscillator Specifications

表 5-12 lists the required characteristics of the main oscillator input.

表 5-12. Main Oscillator Input Characteristics

over operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

MIN

NOM

MAX

25

UNIT

MHz

pF

(2)

f_MOSC

Parallel resonance frequency

4

f_{REF_XTAL_BYPASS}

C₁, C₂

External clock reference (PLL in BYPASS mode)

0

120

24

(3)

External load capacitance on OSC0, OSC1 pins

12

(3)

C_PKG

Device package stray shunt capacitance

0.5

pF

(3)

C_PCB

PCB stray shunt capacitance

pF

(3)

C_SHUNT

Total shunt capacitance

4

300

200

130

120

100

50

pF

(4) (5)

4 MHz

6 MHz

8 MHz

ESR

Crystal effective series resistance

Ω

(4) (5)

12 MHz

16 MHz

25 MHz

DL

Oscillator output drive level⁽⁶⁾

OSC_PWR

mW

ms

(7)

T_START

Oscillator start-up time, when using a crystal

18

0.65 ×

V_DD

V_IH

V_IL

CMOS input high level, when using an external oscillator

CMOS input low level, when using an external oscillator

V_DD

V

0.35 ×

V_DD

GND

V

V_HYS

CMOS input buffer hysteresis, when using an external oscillator

External clock reference duty cycle

150

mV

DC_{OSC_EXT}

45%

55%

(1) See 表 5-39 and 表 5-40 for additional Ethernet crystal requirements.

(2) 5 MHz is the minimum when using the PLL.

(3) See the additional information about the load capacitors following this table.

(4) Crystal ESR specified by crystal manufacturer.

(5) Crystal vendors can be contacted to confirm these specifications are met for a specific crystal part number if the vendors generic crystal

datasheet show limits outside of these specifications.

(6) OSC_PWR= (2 × π × F_P× C_L× 2.5)²× ESR / 2. An estimation of the typical power delivered to the crystal is based on the C_L, F_Pand

ESR parameters of the crystal in the circuit as calculated by the OSC_PWRequation. Ensure that the value calculated for OSC_PWRdoes

not exceed the crystal's drive-level maximum.

(7) Oscillator start-up time is specified from the time the oscillator is enabled to when it reaches a stable point of oscillation such that the

internal clock is valid.

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The load capacitors added on the board, C₁and C₂, should be chosen such that 公式 4 is satisfied (see

表 5-12 for typical values and 表 5-13 for detailed crystal parameter information).

C_L= (C₁× C₂) / (C₁+ C₂) + C_SHUNT

where

•

C_L= load capacitance specified by crystal manufacturer

C_SHUNT= C₀+ C_PKG+ C_PCB(total shunt capacitance seen across OSC0 and OSC1 crystal inputs)

C_PKG, C_PCB= Mutual capacitance as measured across the OSC0 and OSC1 pins excluding the crystal

C₀= Shunt capacitance of crystal specified by the crystal manufacturer

(4)

表 5-13 lists part numbers of crystals that have been simulated and confirmed to operate within the

specifications in 表 5-12. Other crystals that have nearly identical crystal parameters can be expected to

work as well.

In 表 5-13, the crystal parameters labeled C0, C1, and L1 are values that are obtained from the crystal

manufacturer. These numbers are usually a result of testing a relevant batch of crystals on a network

analyzer. The parameters labeled ESR, DL, and C_Lare maximum numbers usually available in the data

sheet for a crystal.

表 5-13 also includes three columns of Recommended Component Values. These values apply to system

board components. C₁and C₂are the values in picofarads of the load capacitors that should be put on

each leg of the crystal pins to ensure oscillation at the correct frequency. R_sis the value in kΩ of a resistor

that is placed in series with the crystal between the OSC1 pin and the crystal pin. R_sdissipates some of

the power so the Max Dl crystal parameter is not exceeded. Only use the recommended C₁, C₂, and R_s

values with the associated crystal part. The values in the table were used in the simulation to ensure

crystal start-up and to determine the worst-case drive level (WC DL). The value in the WC DL column

should not be greater than the Max DL crystal parameter. The WC DL value can be used to determine if a

crystal with similar parameter values but a lower Max DL value is acceptable.

Specifications

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5.15.4.6 Main Oscillator Specification WIth ADC

表 5-14 lists the system clock characteristics with ADC operation.

表 5-14. System Clock Characteristics With ADC Operation

PARAMETER

MIN

NOM

MAX

UNIT

System clock frequency when the ADC module is operating (when PLL is

bypassed)

f_sysadc

16

MHz

5.15.4.7 System Clock Characteristics With USB Operation

表 5-15 lists the system clock characteristics with USB operation.

表 5-15. System Clock Characteristics With USB Operation

PARAMETER

MIN

NOM

MAX

UNIT

System clock frequency when the USB module is operating (MOSC must be the

clock source, either with or without using the PLL)

f_sysusb

30

MHz

5.15.5 Sleep Modes

The following tables can be used to calculate the maximum wake time from sleep or deep sleep mode,

depending on the specific application. Depending on the application configuration, each parameter, except

for t_FLASH, adds sequential latency to the wake time. Flash restoration happens in parallel to the other

wake processes, and its wake time is normally absorbed by the other latencies. As an example, the wake

time for a device in deep sleep mode with the PIOSC and PLL turned off and the flash and SRAM in low-

power mode is calculated by 公式 5.

Wake Time = t_PIOSCDS+ t_PLLDS+ t_SRAMLPDS

(5)

t_FLASHdoes not contribute to this equation because the values of the other parameters are greater.

In sleep mode, the wake time due to a clock source is zero because the device uses the same clock

configuration in run mode; thus, there is no latency involved with respect to the clocks.

表 5-16 lists the wake-up times from sleep mode.

表 5-16. Wake From Sleep Characteristics

over operating free-air temperature (unless otherwise noted)

NO.

D1

D2

D3

D4

D5

D6

D7

PARAMETER

MIN

TYP

MAX UNIT

t_PIOSC

t_MOSC

t_PLL

Time to restore PIOSC as system clock in sleep mode

Time to restore MOSC as system clock in sleep mode

Time to restore PLL as system clock in sleep mode

N/A

39

µs

t_LDO

Time to restore LDO to 1.2 V in sleep mode

t_FLASH

t_SRAMLP

t_SRAMSTBY

Time to restore flash to active state from low-power state in sleep mode

Time to restore SRAM to active state from low-power state in sleep mode

Time to restore SRAM to active state from standby state in sleep mode

96

15

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表 5-16 lists the wake-up times from deep sleep mode.

表 5-17. Wake From Deep Sleep Characteristics

over operating free-air temperature (unless otherwise noted)

NO.

PARAMETER

MIN

TYP

MAX

14

UNIT

deep-

sleep

clock

D8

t_PIOSCDS

Time to restore PIOSC as system clock in deep sleep mode

Time to restore MOSC as system clock in deep sleep mode

cycles

D9

t_MOSCDS

18

ms

1 cycle of

deep sleep

clock + 512

clock

D10

t_PLLDS

Time to restore PLL as system clock in deep sleep mode

cycles of PLL cycles

reference

(1)

clock

D11

D12

D13

D14

t_LDODS

Time to restore LDO to 1.2 V in deep sleep mode

39

96

15

µs

t_FLASHLPDS

t_SRAMLPDS

t_SRAMSTBYDS

Time to restore flash to active state from low-power state

Time to restore SRAM to active state from low-power state

Time to restore SRAM to active state from standby state

(1) Deep sleep clock can vary. See the System Control chapter of the MSP432E4 SimpleLink™ Microcontrollers Technical Reference

Manual for the deep sleep clock options.

5.15.6 Hibernation Module

The Hibernation module requires special system implementation considerations because it is intended to

power down all other sections of its host device. See the Hibernation Module chapter of the MSP432E4

SimpleLink™ Microcontrollers Technical Reference Manual.

表 5-18 lists the required characteristics of the Hibernation module battery.

表 5-18. Hibernation Module Battery Characteristics

over operating free-air temperature (unless otherwise noted)

PARAMETER

MIN

1.8

0

NOM

MAX

3.6

0.7

2.0

2.2

2.4

2.6

UNIT

V

V_BAT

Battery supply voltage

3.0

V_BATRMP

V_BATbattery supply voltage ramp time

V/µs

VBATSEL = 0x0

VBATSEL = 0x1

VBATSEL = 0x2

VBATSEL = 0x3

1.8

2.0

2.2

2.4

1.9

2.1

2.3

2.5

V_LOWBAT

Low-battery detect voltage

V

Specifications

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表 5-19 lists the timing characteristics of the HIB module.

表 5-19. Hibernation Module Characteristics

over operating free-air temperature (unless otherwise noted) (see 图 5-13)

NO.

PARAMETER

WAKE assertion time

MIN

TYP

MAX

UNIT

H1

t_WAKE

100

ns

HIB module

clock period

H2

t_{WAKE_TO_HIB}

WAKE assert to HIB desassert (wake-up time)

1

(1)

H3

H4

t_{VDD_RAMP}

t_{VDD_CODE}

V_DDramp to 3.0 V

See

µs

V_DDat 3 V to internal POR deassert; first instruction executes

500

Duty cycle for RTCCLK output signal, when using a

32.768‑kHz crystal

40%

30%

60%

H5

DC_RTCCLK

Duty cycle for RTCCLK output signal, when using a

32.768‑kHz external single-ended (bypass) clock source

70%

(1) Depends on characteristics of power supply.

H1

WAKE

HIB

H2

H3

V_DD

H4

POR

图 5-13. Hibernation Module Timing

表 5-20 lists the characteristics of the HIB module tamper detection.

表 5-20. Hibernation Module Tamper I/O Characteristics

over operating free-air temperature (unless otherwise noted)

PARAMETER

MIN

3.5

62

TYP

4.4

MAX

5.2

UNIT

MΩ

µs

R_TPU

t_SP

TMPRn pullup resistor

TMPRn pulse duration with short glitch filter

TMPRn pulse duration with long glitch filter

TMPRn assertion to NMI (short glitch filter)

TMPRn assertion to NMI (long glitch filter)

t_LP

94

ms

µs

t_NMIS

t_NMIL

95

94

ms

V_BAT

× 0.8

V_IH

TMPRn high-level input voltage when operating from V_BAT

V

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Specifications

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5.15.7 Flash Memory

表 5-21 lists the characteristics of the flash memory.

表 5-21. Flash Memory Characteristics

over operating free-air temperature (unless otherwise noted)

PARAMETER

MIN

100000

20

TYP

MAX

UNIT

cycles

years

PE_CYC

t_RET

Number of program and erase cycles

Data retention with 100% power-on hours at T_J= 85°C

Data retention with 10% power-on hours at T_J= 125°C and 90% power-on

hours at T_J= 100°C

t_{RET_EXTEMP}

t_PROG64

11

30

years

µs

Program time for double-word-aligned (64 bits) data

<1k cycles

100

8

300

15

t_ERASE

Page erase time

10k cycles

100k cycles

<1k cycles

10k cycles

100k cycles

15

75

10

20

300

40

ms

500

25

t_ME

Mass erase time

70

2500

5.15.8 EEPROM

表 5-22 lists the characteristics of the EEPROM.

表 5-22. EEPROM Characteristics

over operating free-air temperature (unless otherwise noted)

PARAMETER

MIN

500000

20

TYP

MAX

UNIT

cycles

years

EPE_CYC

ET_RET

Number of mass program and erase cycles of a single word

Data retention with 100% power-on hours at T_J= 85°C

Data retention with 10% power-on hours at T_J= 125°C and 90% power-on

hours at T_J= 100°C

ET_{RET_EXTEMP}

11

years

µs

Program time for 32 bits of data with memory space available

110

30

600

900

Program time for 32 bits of data in which a copy to the copy buffer is

required, the copy buffer has space, and less than 10% of EEPROM

endurance used

Program time for 32 bits of data in which a copy to the copy buffer is

required, the copy buffer has space, and more than 90% of EEPROM

endurance used

ET_PROG

ms

Program time for 32 bits of data in which a copy of the copy buffer is

required, the copy buffer requires an erase, and less than 10% of

EEPROM endurance used

60

Program time for 32 bits of data a copy to the copy buffer is required, the

copy buffer requires an erase, and more than 90% of EEPROM endurance

used

1800

system

clock

cycles

7 +

2EWS

9 +

4EWS

ET_READ

Read access time

<1k cycles

8

15

75

15

40

ET_ME

Mass erase time

10k cycles

ms

100k cycles

500

Specifications

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5.15.9 Input/Output Pin Characteristics

注

All GPIO signals are 3.3-V tolerant, except for PB1 (USB0VBUS) which is 5-V tolerant. See

the General-Purpose Input/Outputs (GPIOs) chapter of the MSP432E4 SimpleLink™

Microcontrollers Technical Reference Manual for more information on GPIO configuration.

Two types of pads are provided on the device:

•

Fast GPIO pads: These pads provide variable, programmable drive strength and optimized voltage

output levels.

•

Slow GPIO pads: These pads provide 2-mA drive strength and are designed to be sensitive to voltage

inputs. The following GPIOs port pins are designed with slow GPIO pads:

–

PJ1

注

Port pins PL6 and PL7 operate as fast GPIO pads, but have 4-mA drive capability only.

GPIO register controls for drive strength, slew rate, and open drain have no effect on these

pins. The following registers have no effect: GPIODR2R, GPIODR4R, GPIODR8R,

GPIODR12R, GPIOSLR, and GPIOODR.

注

Port pins PM[7:4] operate as fast GPIO pads but support only 2-, 4-, 6-, and 8-mA drive

capability. All standard GPIO register controls, except for the GPIODR12R register, apply to

these port pins.

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表 5-23 lists the characteristics of the fast GPIOs.

表 5-23. Fast GPIO Module Characteristics

(1) (2) (3) (4)

over operating free-air temperature (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

50

UNIT

pF

(5)

C_LGPIO

Capacitive loading for measurements given in this table

(6)

R_GPIOPU

Fast GPIO internal pullup resistor

12.1

25

16.0

20.2

40

kΩ

R_GPIOPU4MA

R_GPIOPD

Fast GPIO PL6 and PL7 (4 mA only) pullup resistor

kΩ

(6)

Fast GPIO internal pulldown resistor

13.0

10

20.5

14.3

35.5

17

kΩ

R_GPIOPD4MA

Fast GPIO PL6 and PL7 (4 mA only) pulldown resistor

kΩ

Fast GPIO input leakage current, 0 V ≤ V_IN≤ V_DDGPIO pins⁽⁷⁾

400

I_LKG+

nA

Fast GPIO input leakage current, 0 V < V_IN≤ V_DD, fast GPIO pins configured

as ADC or analog comparator inputs

400

I_INJ-

DC injection current, V_IN≤ 0 V

60

–0.5

µA

(8)

I_MAXINJ-

Maximum negative injection if not voltage protected

mA

2-mA drive

4-mA drive

8-mA drive

7.85

4.15

2.33

11.73

6.35

3.73

t_GPIOR

Fast GPIO rise time⁽⁹⁾

ns

8-mA drive with slew rate

control

3.77

5.76

10-mA drive

12-mA drive

2-mA drive

4-mA drive

1.98

1.75

10.3

5.15

2.58

3.22

2.9

16.5

8.29

4.16

8-mA drive

(10)

t_GPIOF

Fast GPIO fall time

ns

8-mA drive with slew rate

control

3.54

5.55

10-mA drive

12-mA drive

2.07

1.73

3.34

2.78

(1) V_DDmust be within the range specified in Section 5.4.

(2) Leakage and Injection current characteristics specified in this table also apply to XOSC0 and XOSC1 inputs.

(3) For the external reference inputs of the ADC, avoid a current-limiting resistor (see the I_VREFspecification in 表 5-33).

(4) I/O pads should be protected if the I/O voltage may go outside the limits shown in the table. If the part is unpowered, the I/O pad voltage

or current must be limited (as shown in this table) to avoid powering the part through the I/O pad, which can potentially cause

irreversible damage.

(5) See the individual peripheral sections for specific loading information.

(6) This value includes all GPIO except for port pins PL6 and PL7.

(7) The leakage current is measured with V_INapplied to the corresponding pins. The leakage of digital port pins is measured individually.

The port pin is configured as an input and the pullup/pulldown resistor is disabled.

(8) If the I/O pad is not voltage limited, it should be current limited (to I_INJ+ and I_INJ-) if there is any possibility of the pad voltage exceeding

the V_IOlimits (including transient behavior during supply ramp up, or at any time when the part is unpowered).

(9) Time measured from 20% to 80% of V_DD

(10) Time measured from 80% to 20% of V_DD

.

Specifications

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表 5-24 lists the characteristics of the slow GPIOs.

表 5-24. Slow GPIO Module Characteristics

over operating free-air temperature (unless otherwise noted)^(1)(2)(3)

PARAMETER

MIN

TYP

MAX

UNIT

pF

C_LGPIO

Capacitive loading for measurements given in this table⁽⁴⁾

50

31.4

35.5

3.25

R_GPIOPU

R_GPIOPD

Slow GPIO internal pullup resistor

13.8

13.0

20.0

20.5

kΩ

Slow GPIO internal pulldown resistor

Slow GPIO input leakage current, 0 V ≤ V_IN≤ V_DD, GPIO pins⁽⁵⁾

kΩ

I_LKG+

nA

Slow GPIO input leakage current, 0 V < V_IN≤ V_DD, GPIO pins configured as ADC

or analog comparator inputs

3.25

I_INJ-

DC injection current, V_IN≤ 0 V

Slow GPIO rise time, 2-mA drive⁽⁶⁾

Slow GPIO fall time, 2-mA drive⁽⁷⁾

3.42

29.8

21.1

µA

ns

t_GPIOR

t_GPIOF

19.3

12.8

(1) V_DDmust be within the range specified in Section 5.4.

(2) V_INmust be within the range specified in Section 5.1. Leakage current outside of this maximum voltage is not ensured and can result in

permanent damage of the device.

(3) To avoid potential damage to the part, externally limit either the voltage or current on the I/Os other than power and WAKE as listed in

this table.

(4) See the individual peripheral sections for specific loading information.

(5) The leakage current is measured with V_INapplied to the corresponding pins. The leakage of digital port pins is measured individually.

The port pin is configured as an input and the pullup/pulldown resistor is disabled.

(6) Time measured from 20% to 80% of V_DD

(7) Time measured from 80% to 20% of V_DD

.

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5.15.9.1 Types of I/O Pins and ESD Protection

CAUTION

All device I/Os pins, except for PB1, are NOT 5-V tolerant; voltages in excess

of the limits in Section 5.4 can permanently damage the device. PB1 is used for

the USB0VBUS signal, which requires a 5-V input.

5.15.9.1.1 Hibernate WAKE pin

The Hibernate WAKE pin uses ESD protection, similar to the one shown in 图 5-14. This ESD protection

prevents a direct path between this pad and any power supply rails in the device. The WAKE pad input

voltage should be kept inside the maximum ratings specified in Section 5.1 to ensure current leakage and

current injections are within acceptable range. 表 5-25 lists current leakages and current injection for these

pins.

V_DD

I/O Pad

ESD

Clamp

GND

图 5-14. ESD Protection

表 5-25. Pad Voltage and Current Characteristics for Hibernate WAKE Pin

over operating free-air temperature (unless otherwise noted)⁽¹⁾⁽²⁾

PARAMETER

MIN

TYP

MAX

300

43.3

2

UNIT

nA

I_LKG+

I_LKG-

I_INJ+

I_INJ-

Positive I/O leakage for V_DD≤ V_IN≤ V_BAT+ 0.3 V

Negative I/O leakage for –0.3 V ≤ V_IN≤ 0 V⁽³⁾

Maximum positive injection if not voltage protected

Maximum negative injection if not voltage protected

µA

mA

(4)

–0.5

(1) V_INmust be within the range specified in Section 5.1. Leakage current outside of this maximum voltage is not ensured and can result in

permanent damage of the device.

(2) VDD must be within the range specified in Section 5.4.

(3) Leakage outside the minimum range (–0.3 V) is unbounded and must be limited to I_INJ-using an external resistor.

(4) If the I/O pad is not voltage limited, it should be current limited (to I_INJ+ and I_INJ-) if there is any possibility of the pad voltage exceeding

the V_IOlimits (including transient behavior during supply ramp up, or at any time when the part is unpowered).

Specifications

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5.15.9.1.2 Nonpower I/O Pins

Most nonpower I/Os (with the exception of the I/O pad for Hibernate WAKE input) have ESD protection as

shown in 图 5-15.

These I/Os have an ESD clamp to ground and a diode connection to the corresponding power supply rail.

To prevent potential damage to the device, follow the specifications in 表 5-26 for the voltage and current

of these I/Os. In addition, comply with that the ADC external reference specifications in 表 5-33 to prevent

gain error.

V_DD

I/O Pad

ESD

Clamp

GND

图 5-15. ESD Protection for Nonpower Pins (Except WAKE Signal)

表 5-26. Nonpower I/O Pad Voltage and Current Characteristics

(1) (2) (3)

over operating free-air temperature (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

V

V_IO

I/O pad voltage limits if voltage protected

–0.3

V_DDV_DD+ 0.3

(4)

I_LKG+

I_LKG-

I_INJ+

I_INJ-

Positive I/O leakage for V_DD≤ V_IN≤V_IO

400

60

nA

(4)

Negative I/O leakage for V_IOMIN ≤ V_IN≤ 0V

µA

Maximum positive injection if not voltage protected⁽⁵⁾

Maximum negative injection if not voltage protected⁽⁵⁾

2

mA

–0.5

(1) To avoid potential damage to the part, externally limit either the voltage or current on I/Os other than power and WAKE as listed in this

table.

(2) For the external reference inputs of the ADC, avoid a current-limiting resistor (see the I_VREFspecification in 表 5-33).

(3) I/O pads should be protected if at any point the I/O voltage has a possibility of going outside the limits shown in the table. If the part is

unpowered, the I/O pad voltage and current must be limited (as shown in this table) to avoid powering the part through the I/O pad,

which can potentially cause irreversible damage.

(4) MIN and MAX leakage current for the case when the I/O is voltage protected to V_IOMIN or V_IOMAX.

(5) If the I/O pad is not voltage limited, it should be current limited (to I_INJ+and I_INJ-) if there is any possibility of the pad voltage exceeding

the V_IOlimits (including transient behavior during supply ramp up, or at any time when the part is unpowered).

64

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5.15.10 External Peripheral Interface (EPI)

表 5-27 lists the load conditions used to characterize the EPI interface.

表 5-27. EPI Interface Load Conditions

SIGNALS

EPI0S[35:0] SDRAM interface

LOAD VALUE (C_L)

EPI0S[35:0] General-Purpose interface

EPI0S[35:0] Host-Bus interface

30 pF

40 pF

EPI0S[35:0] PSRAM interface

When the EPI module is in SDRAM mode, EPI CLK (EPI0S31) must be configured to 12 mA. The EPI

data bus can be configured to 8 mA. 表 5-28 lists the rise and fall times in SDRAM mode.

表 5-28. EPI SDRAM Characteristics

over operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

12-mA drive, C_L= 30 pF

MIN

TYP

2

MAX

UNIT

ns

t_SDRAMR

t_SDRAMF

EPI rise time (from 20% to 80% of V_DD

)

3

EPI fall time (from 80% to 20% of V_DD

)

2

ns

表 5-29 lists the switching characteristics of the SDRAM interface.

表 5-29. EPI SDRAM Interface Characteristics

over operating free-air temperature (unless otherwise noted) ⁽¹⁾(see 图 5-16, 图 5-17, and 图 5-18)

NO.

E1

PARAMETER

MIN

16.67

8.33

TYP

MAX

UNIT

ns

t_CK

t_CH

t_CL

SDRAM clock period

E2

SDRAM clock high time

SDRAM clock low time

CLK to output valid

CLK to output invalid

CLK to output tristate

Input set up to CLK

CLK to input hold

ns

E3

8.33

ns

E4

t_COV

t_COI

t_COT

t_S

4

ns

E5

ns

E6

ns

E7

8.5

0

ns

E8

t_H

ns

E9

t_PU

t_RP

t_RFC

t_MRD

Power-up time

100

20

66

2

µs

E10

E11

E12

Precharge all banks

Auto refresh

ns

Program mode register

EPI CLK

(1) The EPI SDRAM interface must use 12-mA drive.

Specifications

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CLK

(EPI0S31)

E1

E2

E3

CKE

(EPI0S30)

NOP

Command

NOP

PRE

AREF

PRE

AREF

LOAD

NOP

AREF

Active

(EPI0S[29:28,19:18])

DQMH, DQML

(EPI0S[17:16])

AD11, AD[9:0]

(EPI0S[11,9:0]

Code

Row

Bank

All Banks

AD10

(EPI0S[10])

Single Bank

BAD[1:0]

(EPI0S[14:13])

AD [15,12]

(EPI0S [15,12])

E9

E10

E11

E12

(1) If CS is high at clock high time, all applied commands are NOP.

(2) The Mode register can be loaded before the autorefresh cycles.

(3) JEDEC and PC100 specify 3 clock cycles.

(4) Outputs are Hi-Z after the command is issued.

图 5-16. SDRAM Initialization and Load Mode Register Timing

CLK

(EPI0S31)

CKE

(EPI0S30)

E4

E5

E6

CSn (EPI0S29)

WEn (EPI0S28)

RASn

(EPI0S19)

CASn

(EPI0S18)

E7

DQMH, DQML

(EPI0S [17:16])

E8

AD [15:0] (EPI0S

[15:0])

Row

Column

Data 0

Data 1

...

Data n

Burst Term

Activate

NOP

Read

NOP

AD [15:0] driven in

AD [15:0] driven out

图 5-17. SDRAM Read Timing

66

Specifications

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

CLK

(EPI0S31)

CKE

(EPI0S30)

E4

E5

E6

CSn (EPI0S29)

WEn (EPI0S28)

RASn

(EPI0S19)

CASn

(EPI0S18)

DQMH, DQML

(EPI0S [17:16])

AD [15:0] (EPI0S

[15:0])

Row

Column-1

Write

Data 0

Data 1

...

Data n

Activate

NOP

Burst Term

AD [15:0] driven out

图 5-18. SDRAM Write Timing

Specifications

67

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ZHCSH09 –OCTOBER 2017

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表 5-30 lists the characteristics of the Host-Bus 8 and Host-Bus 16 interface.

表 5-30. EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics

over operating free-air temperature (unless otherwise noted) (see 图 5-19, 图 5-20, 图 5-21, and 图 5-22)

NO.

E14

E15

E16

PARAMETER

Read data set up time

MIN

10

0

TYP

MAX

UNIT

ns

t_ISU

t_IH

Read data hold time

ns

t_DV

WRn to write data valid

3.6

ns

EPI clock

cycles

E17

t_DI

Data hold from WRn invalid

1

E18

E19

t_OV

ALE/CSn to output valid

CSn to output invalid

4

ns

t_OINV

EPI clock

cycles

E20

E21

E22

E23

E24

t_STLOW

t_ALEHIGH

t_CSLOW

t_ALEST

WRn / RDn strobe duration low

ALE duration high

EPI clock

cycles

1

EPI clock

cycles

CSn duration low

2

1

EPI clock

cycles

ALE rising to WRn / RDn strobe falling

ALE falling to Address high impedance

EPI clock

cycles

t_ALEADD

E21

ALE (EPI0S30)

CSn (EPI0S30)

WRn (EPI0S29)

E18

E22

E19

E23

E20

RDn/OEn

(EPI0S28)

BSEL0n/

BSEL1n^a

Address

E15

E14

Data

^aBSEL0n and BSEL1n are available in Host-Bus 16 mode only.

图 5-19. Host-Bus 8/16 Asynchronous Mode Read Timing

68

Specifications

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

E21

ALE

(EPI0S30)

E18

E22

CSn

(EPI0S30)

E18

E19

E20

WRn

(EPI0S29)

E23

RDn/Oen

(EPI0S28)

BSEL0n

BSEL1n^a

Address

E16

E17

Data

^aBSEL0n and BSEL1n are available in Host-Bus 16 mode only.

图 5-20. Host-Bus 8/16 Asynchronous Mode Write Timing

E21

ALE (EPI0S30)

CSn (EPI0S30)

WRn (EPI0S29)

E18

E22

E19

E18

E23

E20

RDn/OEn

(EPI0S28)

E24

BSEL0n/

BSEL1n^a

E14

E15

Muxed Address/

Data

Address

Data

^aBSEL0n and BSEL1n are available in Host-Bus 16 mode only.

图 5-21. Host-Bus 8/16 Mode Asynchronous Muxed Read Timing

Specifications

69

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

E21

ALE

(EPI0S30)

E18

E22

CSn

(EPI0S30)

E18

E19

E20

WRn

(EPI0S29)

E23

RDn/Oen

(EPI0S28)

BSEL0n

BSEL1n^a

E16

Muxed Address/

Data

Address

Data

^aBSEL0n and BSEL1n are available in Host-Bus 16 mode only.

图 5-22. Host-Bus 8/16 Mode Asynchronous Muxed Write Timing

70

Specifications

MSP432E401Y

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ZHCSH09 –OCTOBER 2017

表 5-31 lists the switching characteristics of the general-purpose interface.

表 5-31. EPI General-Purpose Interface Characteristics

over operating free-air temperature (unless otherwise noted) (see 图 5-23)

NO.

E25

E26

E27

E28

E29

E30

E31

PARAMETER

General-purpose clock period

MIN

16.67

8.33

8.50

0

TYP

MAX

UNIT

ns

t_CK

t_CH

t_CL

t_ISU

t_IH

General-purpose clock high time

ns

General-purpose clock low time

ns

Input signal set up time to rising clock edge

Input signal hold time from rising clock edge

Falling clock edge to output valid

ns

t_DV

t_DI

4

ns

Falling clock edge to output invalid

ns

E25

E26

E27

Clock

(EPI0S31)

E30

Frame

(EPI0S30)

RD

(EPI0S29)

WR

(EPI0S28)

Address

E30

Data

E31

E28

Data

E29

Read

Write

NOTE: This figure shows accesses when the FRM50 bit is clear, the FRMCNT field is 0x0, and the WR2CYC bit is clear.

图 5-23. General-Purpose Mode Read and Write Timing

Specifications

71

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ZHCSH09 –OCTOBER 2017

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表 5-32 lists the switching characteristics of the PSRAM interface.

表 5-32. EPI PSRAM Interface Characteristics

over operating free-air temperature (unless otherwise noted) (see 图 5-24 and 图 5-25)

NO.

E33

E34

E35

E36

E37

E38

E39

E40

PARAMETER

MIN

TYP

MAX

UNIT

ns

t_EPICLK

t_RTFT

t_OV

EPI_CLK period

20

EPI_CLK rise or fall time

1.8

20

ns

(1)

Falling EPI_CLK to address/write data or control output valid

4.5

2

ns

(1)

t_HT

Falling EPI_CLK to address/write data or control hold time

Read data setup time from EPI_CLK rising

Read data output hold from EPI_CLK rising

iRDY setup time

ns

t_SUP

t_DH

9

ns

0

ns

t_IRV

9

ns

t_IRH

iRDY hold time

ns

(1) Control output includes WRn, RDn, OEn, BSELn, ALE, and CSn.

E33

E34

EPICLK

EPI0S31

E35

E36

EPI0S [19:0]

ADDRESS

ALE

E36

CSn

E36

WRn

EPI0S29

BSELn

E40

E39

iRDY

EPI0S32

EPI0S[15:0]

DATA

E37

E38

图 5-24. PSRAM Single Burst Read

72

Specifications

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

E34

E33

EPICLK

EPI0S31

E35

E36

EPI0S[19:0]

ADDRESS

ALE

E35

BSELn

E36

CSn

WRn

EPI0S29

E39

E40

iRDY

EPI0S32

E35

E36

EPI0S[15:0]

DATA

图 5-25. PSRAM Single Burst Write

Specifications

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ZHCSH09 –OCTOBER 2017

www.ti.com.cn

5.15.11 Analog-to-Digital Converter (ADC)

表 5-33 lists the electrical characteristics for the ADC at 1 Msps.

表 5-33. Electrical Characteristics for ADC at 1 Msps

V_REF+= 3.3 V, f_ADC= 16 MHz (unless otherwise noted)⁽¹⁾

PARAMETER

MIN

TYP

MAX

UNIT

Power supply requirements

V_DDA

ADC supply voltage

ADC ground voltage

2.97

3.3

0

3.63

V

GNDA

VDDA and GNDA voltage reference

(2)

C_REF

Voltage reference decoupling capacitance

1.0 // 0.01

µF

External voltage reference input

Positive external voltage reference for ADC, when VREF field in the

V_REFA+

V_REFA-

2.4

V_DDA

0.3

V

ADCCTL register is 0x1⁽³⁾

Negative external voltage reference for ADC, when VREF field in the

ADCCTL register is 0x1⁽³⁾

GNDA

330.5

I_VREF

I_LVREF

C_REF

Current on VREF+ input, using external V_REF+= 3.3 V

440

2.0

µA

µF

DC leakage current on VREF+ input when external VREF disabled

(3)

(2)

External reference decoupling capacitance

1.0 // 0.01

Analog input

Single-ended, full-scale analog input voltage, internal reference

(4) (5)

(3)

0

V_DDA

(4)(6)

Differential, full-scale analog input voltage, internal reference

–V_DDA

V_VDDA

Single-ended, full-scale analog input voltage, external reference

V_REFA-

V_REFA+

(5)

V_ADCIN

V

–(V_REFA+

– V_REFA-

)

Differential, full-scale analog input voltage, external reference⁽³⁾⁽⁷⁾

V_REFA+– V_REFA-

[(V_REFA+

+

VIN_CM

Input common-mode voltage, differential mode⁽⁸⁾

ADC input leakage current⁽⁹⁾

V_REFA-) / 2]

±0.025

I_L

2.0

2.5

10

µA

kΩ

pF

Ω

(9)

R_ADC

C_ADC

R_S

ADC equivalent input resistance

(9)

ADC equivalent input capacitance

(9)

Analog source resistance

500

Sampling dynamics

f_ADC

f_CONV

t_S

ADC conversion clock frequency⁽¹⁰⁾

16

1

MHz

Msps

ns

ADC conversion rate

ADC sample time

250

1

(11)

t_C

ADC conversion time

µs

(1) Best design practices suggest placing static or quiet digital I/O signals adjacent to sensitive analog inputs to reduce capacitive coupling

and crosstalk. Unexpected results can occur if a switching digital I/O is placed adjacent to an ADC input channel or voltage reference

input. In addition, analog signals that are adjacent to ADC input channels or reference inputs must meet the R_ADCequivalent input

resistance given in this table and must be band-limited to 100 kHz or lower.

(2) Two capacitors in parallel. These capacitors should be as close to the die as possible.

(3) Assumes external filtering network between VREFA+ and VREFA- as shown in 图 5-26. External reference noise level must be under

12-bit (–74 dB) full-scale input, over input bandwidth, measured at VREFA+ – VREFA-.

(4) Internal reference is connected directly between V_DDAand GNDA (VREFi = V_DDA– GNDA). In this mode, E_O, E_G, E_T, and dynamic

specifications are adversely affected due to internal voltage drop and noise on V_DDAand GNDA. Internal reference voltage is selected

when VREF field in the ADCCTL register is 0x0.

(5) V_ADCIN= V_INP– V_INN

(6) With signal common-mode voltage as V_DDA/ 2.

(7) With signal common-mode voltage as V_REF++ GNDA.

(8) This parameter is defined as the average of the differential inputs.

(9) As shown in 图 5-27, R_ADCis the total equivalent resistance in the input line all the way up to the sampling node at the input of the ADC.

(10) See 表 5-14 for full ADC clock frequency specification.

(11) ADC conversion time (t_C) includes the ADC sample time (t_S).

74

Specifications

MSP432E401Y

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ZHCSH09 –OCTOBER 2017

表 5-33. Electrical Characteristics for ADC at 1 Msps (continued)

V_REF+= 3.3 V, f_ADC= 16 MHz (unless otherwise noted)⁽¹⁾

PARAMETER

MIN

TYP

MAX

UNIT

ADC

clock

cycles

t_LT

Latency from trigger to start of conversion

2

(12) (13)

System performance when using external reference

N

Resolution

12

±1.5

±0.8

±1.0

±2.0

±2.5

bits

LSB

INL

DNL

E_O

E_G

E_T

Integral nonlinearity error, over full input range

Differential nonlinearity error, over full input range

Offset error

±3.0

(14)

+2.0/–1.0

±3.0

±4.0

(15)

Gain error

(16)

Total unadjusted error, over full input range

System performance when using internal reference

N

Resolution

12

±1.5

bits

LSB

INL

DNL

E_O

E_G

E_T

Integral nonlinearity error, over full input range

Differential nonlinearity error, over full input range

Offset error

±3.0

(14)

±0.8

+2.0/–1.0

±5.0

±15.0

±30.0

(15)

Gain error

±10.0

(16)

Total unadjusted error, over full input range

(12) (17)

Dynamic characteristics

(18)

SNR_D

Signal-to-noise-ratio, Differential input, V_ADCIN: –20 dB FS, 1 kHz

70

72

75

dB

Signal-to-distortion ratio, Differential input, V_ADCIN: –3 dB FS, 1 kHz

SDR_D

(18) (19) (20)

Signal-to-Noise+Distortion ratio, Differential input, V_ADCIN: –3 dB FS,

1 kHz

SNDR_D

SNR_S

68

60

70

60

70

65

72

63

dB

(18) (21) (22)

Signal-to-noise-ratio, Single-ended input, V_ADCIN: –20 dB FS, 1 kHz

(23)

Signal-to-distortion ratio, Single-ended input, V_ADCIN: –3 dB FS, 1

SDR_S

(19) (20)

kHz

Signal-to-Noise+Distortion ratio, Single-ended input, V_ADCIN: –3 dB

SNDR_S

(23) (21) (22)

FS, 1 kHz

Temperature sensor

V_TSENSTemperature sensor voltage, junction temperature 25°C

1.633

–13.3

V

Temperature sensor slope at:

S_TSENS

mV/°C

–40°C to 105°C ambient (extended temperature part)

(12) A low-noise environment is assumed to obtain values close to specifications. The board must have good ground isolation between

analog and digital grounds and a clean reference voltage. The input signal must be band-limited to Nyquist bandwidth. No antialiasing

filter is provided internally.

(13) ADC static measurements taken by averaging over several samples. At least 20-sample averaging is assumed to obtain expected

typical or maximum specification values.

(14) 12-bit DNL

(15) Gain error is measured at maximum code after compensating for offset. Gain error is equivalent to the full-scale error. It can be given

in % of slope error, or in LSB, as done here.

(16) Total unadjusted error is the maximum error at any one code versus the ideal ADC curve. It includes all other errors (offset error, gain

error and INL) at any given ADC code.

(17) ADC dynamic characteristics are measured using low-noise board design, with low-noise reference voltage (< –74-dB noise level in

signal bandwidth) and low-noise analog supply voltage. Board noise and ground bouncing couple into the ADC and affect dynamic

characteristics. A clean external reference must be used to achieve the listed specifications.

(18) Differential signal with correct common-mode voltage, applied between two ADC inputs.

(19) SDR = –THD in dB.

(20) For higher-frequency inputs, expect degradation in SDR.

(21) SNDR = S/(N+D) = SINAD (in dB)

(22) Effective number of bits (ENOB) can be calculated from SNDR: ENOB = (SNDR – 1.76) / 6.02.

(23) Single-ended inputs are more sensitive to board and trace noise than differential inputs; SNR and SNDR measurements on single-

ended inputs are highly dependent on how clean the test setup is. If the input signal is not well isolated on the board, higher noise than

specified could be seen at the ADC output.

Specifications

75

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ZHCSH09 –OCTOBER 2017

www.ti.com.cn

表 5-33. Electrical Characteristics for ADC at 1 Msps (continued)

V_REF+= 3.3 V, f_ADC= 16 MHz (unless otherwise noted)⁽¹⁾

PARAMETER

Temperature sensor accuracy ⁽²⁴⁾at:

–40°C to 105°C ambient (extended temperature part)

MIN

TYP

MAX

±5

UNIT

E_TSENS

°C

(24) This parameter does not include ADC error.

76

Specifications

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

表 5-34 lists the electrical characteristics for the ADC at 2 Msps.

表 5-34. Electrical Characteristics for ADC at 2 Msps

V_REF+= 3.3 V, f_ADC= 32 MHz, over operating free-air temperature (unless otherwise noted) (see 图 5-26 and 图 5-27)⁽¹⁾

PARAMETER

MIN

TYP

MAX

UNIT

Power supply requirements

V_DDA

ADC supply voltage

ADC ground voltage

2.97

3.3

0

3.63

V

GNDA

VDDA and GNDA voltage reference

(2)

C_REF

Voltage reference decoupling capacitance

1.0 // 0.01

µF

External voltage reference input

Positive external voltage reference for ADC, when VREF field in the

V_REFA+

V_REFA-

2.4

V_DDA

0.3

V

ADCCTL register is 0x1⁽³⁾

Negative external voltage reference for ADC, when VREF field in the

GNDA

330.5

(3)

ADCCTL register is 0x1

I_VREF

I_LVREF

C_REF

Current on VREF+ input, using external V_REF+= 3.3 V

440

2.0

µA

µF

DC leakage current on VREF+ input when external VREF disabled

(3)

(2)

External reference decoupling capacitance

1.0 // 0.01

Analog input

Single-ended, full-scale analog input voltage, internal reference⁽⁴⁾⁽⁵⁾

0

V_DDA

(4)(6)

Differential, full-scale analog input voltage, internal reference

Single-ended, full-scale analog input voltage, external reference

–V_DDA

V_VDDA

(3)

V_REFA-

V_REFA+

(5)

V_ADCIN

V

–(V_REFA+

– V_REFA-

)

(3)(7)

Differential, full-scale analog input voltage, external reference

V_REFA+– V_REFA-

[(V_REFA+

+

(8)

VIN_CM

Input common-mode voltage, differential mode

V_REFA-) / 2]

±0.025

I_L

ADC input leakage current⁽⁹⁾

2.0

2.5

10

µA

kΩ

pF

Ω

(9)

R_ADC

C_ADC

R_S

ADC equivalent input resistance

(9)

ADC equivalent input capacitance

(9)

Analog source resistance

250

Sampling dynamics

f_ADC

f_CONV

t_S

ADC conversion clock frequency⁽¹⁰⁾

32

MHz

Msps

ns

ADC conversion rate

ADC sample time

2

125

0.5

(11)

t_C

ADC conversion time

µs

ADC

clock

cycles

t_LT

Latency from trigger to start of conversion

2

(1) Best design practices suggest placing static or quiet digital I/O signals adjacent to sensitive analog inputs to reduce capacitive coupling

and crosstalk. Unexpected results can occur if a switching digital I/O is placed adjacent to an ADC input channel or voltage reference

input. In addition, analog signals configured adjacent to ADC input channels or reference inputs must meet the R_ADCequivalent input

resistance given in this table and must be band-limited to 100 kHz or lower.

(2) Two capacitors in parallel. These capacitors should be as close to the die as possible.

(3) Assumes external filtering network between VREFA+ and VREFA- as shown in 图 5-26. External reference noise level must be under

12-bit (–74-dB) full scale input, over input bandwidth, measured at VREFA+ – VREFA-.

(4) Internal reference is connected directly between V_DDAand V_GNDA(V_REFi= V_DDA– V_GNDA). In this mode, E_O, E_G, E_T, and dynamic

specifications are adversely affected due to internal voltage drop and noise on V_DDAand GNDA. Internal reference voltage is selected

when VREF field in the ADCCTL register is 0x0.

(5) V_ADCIN= V_INP– V_INN

(6) With signal common-mode voltage as V_DDA/ 2.

(7) With signal common-mode voltage as (V_REF++ V_REF-)/ 2.

(8) This parameter is defined as the average of the differential inputs.

(9) As shown in 图 5-27, R_ADCis the total equivalent resistance in the input line all the way up to the sampling node at the input of the ADC.

(10) See 表 5-14 for full ADC clock frequency specification.

(11) ADC conversion time (t_C) includes the ADC sample time (t_S).

Specifications

77

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ZHCSH09 –OCTOBER 2017

www.ti.com.cn

表 5-34. Electrical Characteristics for ADC at 2 Msps (continued)

V_REF+= 3.3 V, f_ADC= 32 MHz, over operating free-air temperature (unless otherwise noted) (see 图 5-26 and 图 5-27)⁽¹⁾

PARAMETER

MIN

TYP

MAX

UNIT

(12) (13)

System performance when using external reference

N

Resolution

12

±1.5

±0.8

±1.0

±2.0

±2.5

bits

LSB

INL

DNL

E_O

E_G

E_T

Integral nonlinearity error, over full input range

Differential nonlinearity error, over full input range

Offset error

±3.0

(14)

+2.0/–1.0

±3.0

±4.0

(15)

Gain error

(16)

Total unadjusted error, over full input range

System performance when using internal reference

N

Resolution

12

±1.5

bits

LSB

INL

DNL

E_O

E_G

E_T

Integral nonlinearity error, over full input range

Differential nonlinearity error, over full input range

Offset error

±3.0

(14)

±0.8

+2.0/–1.0

±5.0

±15.0

±30.0

(15)

Gain error

±10.0

(16)

Total unadjusted error, over full input range

(17) (18)

Dynamic characteristics

(19)

SNR_D

Signal-to-noise-ratio, differential input, V_ADCIN: –20 dB FS, 1 kHz

68

70

72

75

dB

Signal-to-distortion ratio, differential input, V_ADCIN: –3 dB FS, 1 kHz

SDR_D

(19) (20) (21)

Signal-to-noise+distortion ratio, differential input, V_ADCIN: –3 dB FS, 1

kHz

SNDR_D

SNR_S

65

58

68

58

70

65

72

63

dB

(19) (22) (23)

Signal-to-noise-ratio, single-ended input, V_ADCIN: –20 dB FS, 1 kHz

(24)

Signal-to-distortion ratio, single-ended input, V_ADCIN: –3 dB FS, 1

SDR_S

(20) (21)

kHz

Signal-to-noise+distortion ratio, single-ended input, V_ADCIN: –3 dB

SNDR_S

(24) (22) (23)

FS, 1 kHz

(12) A low-noise environment is assumed to obtain values close to specifications. The board must have good ground isolation between

analog and digital grounds, a clean reference voltage is assumed, and input signal must be bandlimited to Nyquist bandwidth. No

antialiasing filter is provided internally.

(13) ADC static measurements taken by averaging over several samples. At least 20-sample averaging is assumed to obtain expected

typical or maximum specification values.

(14) 12-bit DNL

(15) Gain error is measured at maximum code after compensating for offset. Gain error is equivalent to"Full Scale Error." It can be given

in % of slope error, or in LSB, as done here.

(16) Total Unadjusted Error is the maximum error at any one code versus the ideal ADC curve. It includes all other errors (offset error, gain

error and INL) at any given ADC code.

(17) A low noise environment is assumed to obtain values close to spec. The board must have good ground isolation between analog and

digital grounds and a clean reference voltage. The input signal must be band-limited to Nyquist bandwidth. No antialiasing filter is

provided internally.

(18) ADC dynamic characteristics are measured using low-noise board design, with low-noise reference voltage (< –74 dB noise level in

signal BW) and low-noise analog supply voltage. Board noise and ground bouncing couple into the ADC and affect dynamic

characteristics. Clean external reference must be used to achieve the listed specifications.

(19) Differential signal with correct common-mode voltage, applied between two ADC inputs.

(20) SDR = –THD in dB.

(21) For higher-frequency inputs, expect degradation in SDR.

(22) SNDR = S/(N+D) = SINAD (in dB)

(23) Effective number of bits (ENOB) can be calculated from SNDR: ENOB = (SNDR – 1.76) / 6.02.

(24) Single-ended inputs are more sensitive to board and trace noise than differential inputs; SNR and SNDR measurements on single-

ended inputs are highly dependent on how clean the test setup is. If the input signal is not well isolated on the board, higher noise than

specified could be seen at the ADC output.

78

Specifications

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

MSP432E4 Microcontroller

I_VREF

V_REFA+

V_REFA-

V_REFP

+

V_REF

_

ADC

C_REF

V_REFA-

V_REFA+

V_REFN

图 5-26. ADC External Reference Filtering

MSP432E4 Microcontroller

Input pad

equivalent

circuit

V_DD

Z_ADC

Zs

Rs

+

R_ADC

12-bit

SAR ADC

ESD

Clamp

12-bit

Word

I_L

V_S

V_ADCIN

C_S

R_ADC

Input pad equivalent

circuit

R_ADC

Input pad equivalent

circuit

C_ADC

图 5-27. ADC Input Equivalency

Specifications

79

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

5.15.12 Synchronous Serial Interface (SSI)

表 5-35. SSI Characteristics

over operating free-air temperature (unless otherwise noted) (see 图 5-28, 图 5-29, and 图 5-30)

NO.

PARAMETER

MIN

16.67

100

TYP

MAX

UNIT

As master⁽¹⁾

As slave⁽²⁾

As master

As slave

S1

t_{CLK_PER}

t_{CLK_HIGH}

t_{CLK_LOW}

SSIClk cycle time

SSIClk high time

SSIClk low time

ns

8.33

50

S2

S3

ns

As master

As slave

8.33

50

S4

S5

t_CLKR

t_CLKF

SSIClk rise time⁽³⁾

1.25

ns

(3)

SSIClk fall time

Master mode: master Tx data output (to slave) valid time from

edge of SSIClk

S6

S7

t_TXDMOV

t_TXDMOH

4.00

ns

Master mode: master Tx data output (to slave) hold time after

next SSIClk

0.60

S8

S9

t_RXDMS

t_RXDMH

Master mode: master Rx data In (from slave) setup time

Master mode: master Rx data In (from slave) hold time

7.89

0

ns

Slave mode: master Tx data output (to master) valid time from

edge of SSIClk

S10

S11

t_TXDSOV

t_TXDSOH

47.60⁽⁴⁾

ns

Slave mode: slave Tx data output (to master) hold time from next

SSIClk

37.4⁽⁵⁾

S13

S14

t_RXDSSU

t_RXDSH

Slave mode: Rx data in (from master) setup time

Slave mode: Rx data in (from master) hold time

0

ns

37.03⁽⁶⁾

(1) In master mode, the system clock must be at least twice as fast as the SSIClk.

(2) In slave mode, the system clock must be at least 12 times faster than the SSIClk.

(3) The delays shown are using 12-mA drive strength.

(4) This MAX value is for the minimum slave mode t_SYSCLKperiod (8.33 ns). To find the MAX t_TXDSOVvalue for a larger t_SYSCLK, use the

equation: 4 × t_SYSCLK+ 14.25.

(5) This MIN value is for the minimum slave mode t_SYSCLK(8.33 ns). To find the MIN t_TXDSOHvalue for a larger t_SYSCLK, use the equation: 4

× t_SYSCLK+ 4.08.

(6) This MIN value is for the minimum slave mode t_SYSCLK(8.33 ns). To find the MIN t_TXDSHvalue for a larger t_SYSCLK, use the equation: 4 ×

t_SYSCLK+ 3.70.

S1

S2

S5

S4

SSIClk

SSIFss

S3

SSITx

SSIRx

MSB

LSB

4 to 16 bits

图 5-28. SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement

80

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S1

S5

S2

S4

SSIClk

(SPO=1)

S3

SSIClk

(SPO=0)

S7

S6

SSITx

(to slave)

MSB

S9

LSB

S8

SSIRx

(from slave)

MSB

LSB

SSIFss

图 5-29. Master Mode SSI Timing for SPI Frame Format (FRF = 00), With SPH = 1

S1

S5

S2

S4

SSIClk

(SPO=1)

S3

SSIClk

(SPO=0)

S10

S11

SSITx

(to master)

MSB

LSB

S12

S13

MSB

SSIRx

( from master)

LSB

SSIFss

图 5-30. Slave Mode SSI Timing for SPI Frame Format (FRF = 00), With SPH = 1

Specifications

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表 5-36 lists the characteristics for Bi-SSI and Quad-SSI.

表 5-36. Bi- and Quad-SSI Characteristics⁽¹⁾

over operating free-air temperature (unless otherwise noted)

NO.

S15

S16

S17

S18

S19

PARAMETER

MIN

16.67

8.33

1.25

TYP

MAX

UNIT

ns

(2)

t_{CLK_PER}

t_{CLK_HIGH}

t_{CLK_LOW}

t_CLKR

SSIClk cycle time, as master

SSIClk high time, as master

SSIClk low time, as master

ns

(3)

SSIClk rise time

ns

(3)

t_CLKF

SSIClk fall time

ns

Master mode: master SSInXDATn data output (to slave) valid time

from edge of SSIClk

S20

S21

t_TXDMOV

t_TXDMOH

4.04

ns

Master mode: master SSInXDATn data output (to slave) hold time

after next SSIClk

0.60

S22

S23

t_RXDMS

t_RXDMH

Master mode: master SSInXDATn data in (from slave) setup time

Master mode: master SSInXDATn data in (from slave) hold time

5.78

0

ns

(1) Parameters S15 to S23 correspond to parameters S1 to S9 in 图 5-28 and 图 5-29.

(2) In master mode, the system clock must be at least twice as fast as the SSIClk.

(3) The delays shown are using 12-mA drive strength.

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5.15.13 Inter-Integrated Circuit (I²C) Interface

表 5-37 lists the characteristics for the I²C interface.

表 5-37. I²C Characteristics

over operating free-air temperature (unless otherwise noted) (see 图 5-31)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

system

clock

I1⁽¹⁾

t_SCH

Start condition hold time

36

cycles

system

clock

(1)

I2

t_LP

Clock low period

36

cycles

(2)

I3

t_SRT

t_DH

t_SFT

t_HT

I2CSCL and I2CSDA rise time (V_IL= 0.5 V to V _IH= 2.4 V)

Slave

See

ns

2

7

9

system

clock

cycles

I4

Data hold time

Master

(3)

I5

I2CSCL and I2CSDA fall time (V_IH= 2.4 V to V _IL= 0.5 V)

Clock high time

10

ns

system

clock

cycles

(1)

I6

24

18

36

24

system

clock

cycles

I7

t_DS

Data setup time

system

clock

cycles

(1)

I8

t_SCSR

Start condition setup time (for repeated start condition only)

Stop condition setup time

system

clock

(1)

I9

t_SCS

cycles

system

clock

Slave

2

cycles

I10

t_DV

Data valid

(6 × (1 +

TPR)) +

1

system

clock

cycles

Master

(1) Values depend on the value programmed into the TPR bit in the I²C Master Timer Period (I2CMTPR) register; a TPR programmed for

the maximum I2CSCL frequency (TPR = 0x2) results in a minimum output timing listed in this table. The I²C interface is designed to

scale the actual data transition time to move it to the middle of the I2CSCL low period. The actual position is affected by the value

programmed into the TPR; however, the values in this table are minimum values.

(2) Because I2CSCL and I2CSDA operate as open-drain-type signals, which the controller can only actively drive low, the time I2CSCL or

I2CSDA takes to reach a high level depends on external signal capacitance and pullup resistor values.

(3) Specified at a nominal 50-pF load

I2

I10

I6

I5

I2CSCL

I2CSDA

I1

I7

I8

I3

I9

I4

图 5-31. I²C Timing

Specifications

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5.15.14 Ethernet Controller

5.15.14.1 DC Characteristics

The parameters listed in 表 5-38, with the exception of R_BIAS, apply to transmit pins of the Ethernet PHY,

which are generally the EN0TXOP and EN0TXON signals during standard operation but can also be the

EN0RXIN and EN0RXIP signals if Auto-MDIX is enabled.

表 5-38. Ethernet PHY DC Characteristics

over operating free-air temperature (unless otherwise noted)

PARAMETER

Value of the pulldown resistor on the RBIAS pin

100M transmit voltage

MIN

4.82

0.95

–2%

TYP

4.87

1

MAX

4.92

1.05

2%

UNIT

kΩ

R_BIAS

V_{TPTD_100}

V_TPTDSYM

V_OVRSHT

V_{TPTD_10}

V_TH1

V

100M transmit voltage symmetry

Output overshoot

5%

10M transmit voltage

2.2

2.5

2.8

V

10Base-T Receive threshold

200

mV

5.15.14.2 Clock Characteristics for Ethernet

表 5-39 lists the specifications of the MOSC 25-MHz crystal.

表 5-39. MOSC 25-MHz Crystal Specification⁽¹⁾

over operating free-air temperature (unless otherwise noted) (see 图 5-32)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

MHz

ppm

N1

f_MOSC25

f_TOL

Frequency

25

Frequency tolerance at operational temperature

Frequency stability at 1-year aging

0

±50

±5

f_STA

(1) See 表 5-12 for additional MOSC requirements.

N1

OSC0

图 5-32. MOSC Crystal Characteristics for Ethernet

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表 5-40 lists the specifications of the single-ended 25-MHz oscillator.

表 5-40. MOSC Single-Ended 25-MHz Oscillator Specification

(1)

over operating free-air temperature (unless otherwise noted) (see 图 5-33)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

MHz

ppm

ns

N4

f_OSC

f_TOL

t_STA

t_RF

Frequency

25

Frequency tolerance at operational temperature

Frequency stability at 1-year aging

Frequency rise and fall time

0

±50

1

N5

Cycle to cycle

Over 10 ms

50

ps

t_J

Jitter

1

ns

DC

Duty cycle

40%

60%

(1) See 表 5-12 for additional MOSC requirements.

N4

N5

OSC0

图 5-33. Single-Ended MOSC Characteristics for Ethernet

Specifications

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5.15.14.3 AC Characteristics

表 5-41 lists the timing characterists of the enable and reset.

表 5-41. Ethernet Controller Enable and Software Reset Timing

over operating free-air temperature (unless otherwise noted) (see 图 5-34)

NO.

N16

N17

PARAMETER

MIN

45

TYP

MAX

UNIT

µs

Time from the System Control enable of the PHY to energy on the

t_EN

(1) (2)

PMD output pin

t_SWRST

Time from software reset of the PHY to energy on the PMD output pin

110

ns

(1) The PHY is enabled through System Control by setting the P0 bit in the PCEPHY register and the R0 bit in the RCGCPHY register.

(2) This minimum timing assumes the PHYHOLD bit in the EMACPC register is not set.

CLK

PHY Enable

N16

PHY SW Reset

N17

PMD Output Pair

图 5-34. Reset Timing

86

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表 5-42 lists the 100Base-TX transmit timing.

表 5-42. 100Base-TX Transmit Timing

over operating free-air temperature (unless otherwise noted) (see 图 5-35)

NO.

N38

N39

PARAMETER

MIN

TYP

MAX

5

UNIT

ns

(1)

t_RF

100-Mbps PMD output pair t_Rand t_F

3

4

(2) (3)

t_{RF_MM}

t_{RF_JTTR}

100-Mbps t_Rand t_Fsymmetry

500

1.4

ps

100-Mbps PMD output pair transmit jitter

ns

(1) Rise and fall times taken at 10% and 90% of the +1 or –1 amplitude.

(2) Normal mismatch is the difference between the maximum and minimum of all rise and fall times

(3) Choice of Ethernet transformer magnetics can affect this parameter.

90%

10%

PMD Output Pair

90%

+1

rise

+1 fall

N38

10%

-1

rise

-1 fall

N38

N39

PMD Output Pair

Eye Pattern

N39

图 5-35. 100 Base-TX Transmit Timing

表 5-43 lists the 10Base-T normal link pulse timing.

表 5-43. 10Base-T Normal Link Pulse Timing

over operating free-air temperature (unless otherwise noted) (see 图 5-36)

NO.

N69

N70

PARAMETER

MIN

TYP

76

MAX

UNIT

ms

t_{LP_PER}

t_{LP_WID}

Link pulse period

Link pulse width

100

µs

N69

N70

Normal Link

Pulse(s)

图 5-36. 10Base-TX Normal Link Pulse Timing

Specifications

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表 5-44 lists the Auto-Negotiation FLP timing.

表 5-44. Auto-Negotiation Fast Link Pulse (FLP) Timing

over operating free-air temperature (unless otherwise noted) (see 图 5-37)

NO.

N72

N73

N74

N75

N76

PARAMETER

Clock pulse to clock pulse period

Clock pulse to data pulse period

Clock, data pulse width

MIN

TYP

125

62

MAX

UNIT

µs

t_CLKP

t_CLKDP

t_PUL

t_BRSTP

t_BRSTW

µs

110

16

ns

FLP burst to flp burst period

Burst width

ms

2

N76

N72

N73

N74

Fast Link Pulse(s)

Clock

Pulse

Data

Pulse

Clock

Pulse

N75

N76

FLP Burst

图 5-37. Auto-Negotiation Fast Link Pulse Timing

表 5-45 lists the 100Base-TX signal detect timing.

表 5-45. 100Base-TX Signal Detect Timing

over operating free-air temperature (unless otherwise noted) (see 图 5-38)

NO.

N79

N80

PARAMETER

SD internal turnon time

Internal turnoff time

MIN

TYP

MAX

100

UNIT

µs

t_ON

t_OFF

200

µs

PMD Input Pair

N79

N80

Signal Detect

(Internal)

图 5-38. 100Base-TX Signal Detect Timing

88

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5.15.15 Universal Serial Bus (USB) Controller

The USB controller electrical specifications are compliant with the Universal Serial Bus Specification

Rev 2.0 (full-speed and low-speed support) and the On-The-Go Supplement to the USB 2.0 Specification

Rev 1.0. Some components of the USB system are integrated within the microcontroller and specific to the

microcontroller design.

注

GPIO pin PB1, which can be configured as the USB0VBUS signal, is the only pin that is 5-V

tolerant on the device.

表 5-46 lists the timing characteristics of the ULPI interface.

表 5-46. ULPI Interface Timing

over operating free-air temperature (unless otherwise noted) (see 图 5-39)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

Timings with respect to external clock source input to USB0CLK

U1

U2

U3

U4

U5

U6

t_SUC

t_SUD

t_HTC

t_HTD

t_ODC

t_ODD

Setup time (control in) USB0DIR, USB0NXT

Setup time (data in) USB0Dn

4.8

3.5

0

ns

Hold time (control in) USB0DIR, USB0NXT

Hold time (data in) USB0Dn

0

Output delay (control out) USB0STP

Output delay (data out) USB0Dn

3.7

9.5

Timings with USB0CLK as clock output

U1

U2

U3

U4

U5

U6

t_SUC

t_SUD

t_HTC

t_HTD

t_ODC

t_ODD

Setup time (control in) USB0DIR, USB0NXT

Setup time (data in) USB0Dn

6.0

4.6

0

ns

Hold time (control in) USB0DIR, USB0NXT

Hold time (data in) USB0Dn

0

Output delay (control out) USB0STP

Output delay (data out) USB0Dn

4.0

10.6

USB0CLK

U5

U6

USB0STP

USB0Dn

Write

U1

U2

U3

USB0DIR/

USB0NXT

U4

USB0Dn

Read

图 5-39. ULPI Interface Timing Diagram

Specifications

89

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5.15.16 Analog Comparator

表 5-47 lists the characteristics of the comparator.

表 5-47. Analog Comparator Characteristics

(1) (2)

over operating free-air temperature (unless otherwise noted)

PARAMETER

MIN

GNDA

TYP

MAX

UNIT

V_INP

,

Input voltage range

V_DDA

V

(3)

V_INN

V_CM

V_OS

Input common-mode voltage range

Input offset voltage

V_DDA

V

mV

µA

dB

µs

(4)

±10

50

±50

I_INP, I_INNInput leakage current over full voltage range

2.0

C_MRR

t_RT

Common-mode rejection ratio

Response time

(5)

1.0

t_MC

Comparator mode change to output valid

10

µs

(1) Best design practices suggest placing static or quiet digital I/O signals adjacent to sensitive analog inputs to reduce capacitive coupling

and crosstalk.

(2) To achieve best analog results, keep the source resistance driving the analog inputs, V_INPand V_INN, low.

(3) The external voltage inputs to the analog comparator are designed to be highly sensitive and can be affected by external noise on the

board. For this reason, V_INPand V_INNmust be set to different voltage levels during idle states to ensure the analog comparator triggers

are not enabled. If an internal voltage reference is used, it should be set to a mid-supply level. When operating in sleep or deep-sleep

modes, disable the analog comparator module or set the external voltage inputs to different levels (greater than the input offset voltage)

to achieve minimum current draw.

(4) Measured at V_REF= 100 mV

(5) Measured at external V_REF= 100 mV, input signal switching from 75 mV to 125 mV

表 5-48 lists the characteristics for the comparator.

表 5-48. Analog Comparator Characteristics

over operating free-air temperature (unless otherwise noted)

PARAMETER

Resolution in high range

MIN

TYP

V_DDA/ 29.4

V_DDA/ 22.12

MAX

UNIT

R_HR

R_LR

A_HR

A_LR

V

Resolution in low range

Absolute accuracy high range

Absolute accuracy low range

±R_HR/ 2

±R_LR/ 2

90

Specifications

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

表 5-49 and 表 5-50 list the reference voltages for the comparator under different conditions.

表 5-49. Analog Comparator Voltage Reference Characteristics

V_DDA= 3.3 V, EN = 1, RNG = 0, over operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VREF = 0x0

MIN

0.731

0.843

0.955

1.067

1.180

1.292

1.404

1.516

1.629

1.741

1.853

1.965

2.078

2.190

2.302

2.414

TYP

0.786

0.898

1.010

1.122

1.235

1.347

1.459

1.571

1.684

1.796

1.908

2.020

2.133

2.245

2.357

2.469

MAX

0.841

0.953

1.065

1.178

1.290

1.402

1.514

1.627

1.739

1.851

1.963

2.076

2.188

2.300

2.412

2.525

UNIT

VREF = 0x1

VREF = 0x2

VREF = 0x3

VREF = 0x4

VREF = 0x5

VREF = 0x6

VREF = 0x7

VREF = 0x8

VREF = 0x9

VREF = 0xA

VREF = 0xB

VREF = 0xC

VREF = 0xD

VREF = 0xE

VREF = 0xF

V_IREF

Reference voltage

V

表 5-50. Analog Comparator Voltage Reference Characteristics

V_DDA= 3.3 V, EN = 1, RNG = 1, over operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VREF = 0x0

MIN

0.000

0.076

0.225

0.374

0.523

0.672

0.822

0.971

1.120

1.269

1.418

1.567

1.717

1.866

2.015

2.164

TYP

0.000

0.149

0.298

0.448

0.597

0.746

0.895

1.044

1.193

1.343

1.492

1.641

1.790

1.939

2.089

2.238

MAX

0.074

0.223

0.372

0.521

0.670

0.820

0.969

1.118

1.267

1.416

1.565

1.715

1.864

2.013

2.162

2.311

UNIT

VREF = 0x1

VREF = 0x2

VREF = 0x3

VREF = 0x4

VREF = 0x5

VREF = 0x6

VREF = 0x7

VREF = 0x8

VREF = 0x9

VREF = 0xA

VREF = 0xB

VREF = 0xC

VREF = 0xD

VREF = 0xE

VREF = 0xF

V_IREF

Reference voltage

V

Specifications

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5.15.17 Pulse-Width Modulator (PWM)

表 5-51 lists the PWM timing characteristics.

表 5-51. PWM Timing Characteristics

over operating free-air temperature (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

PWM

clock

t_FLTW

Minimum fault pulse width

2

periods

24 + (1

PWM

clock)

(1)

t_FLTMAX

t_FLTMIN

MnFAULTn assertion to PWM inactive

MnFAULTn deassertion to PWM active

ns

(2)

5

(1) This parameter value can vary depending on the PWM clock frequency which is controlled by the System Clock and a programmable

divider field in the PWMCC register.

(2) The latch and minimum fault period functions that can be enabled in the PWMnCTL register can change the timing of this parameter.

5.15.18 Emulation and Debug

表 5-52 lists the JTAG characteristics.

表 5-52. JTAG Characteristics

over operating free-air temperature (unless otherwise noted) (see 图 5-40 and 图 5-41)

NO.

J1

PARAMETER

TCK operational clock frequency

TCK operational clock period

TCK clock low time

MIN

0

TYP

MAX

UNIT

MHz

ns

f_TCK

10

J2

t_TCK

100

J3

t_{TCK_LOW}

t_{TCK_HIGH}

t_{TCK_R}

t_TCK/ 2

ns

J4

TCK clock high time

ns

J5

TCK rise time

0

10

ns

J6

t_{TCK_F}

TCK fall time

ns

J7

t_{TMS_SU}

t_{TMS_HLD}

t_{TDI_SU}

t_{TDI_HLD}

TMS setup time to TCK rise

TMS hold time from TCK rise

TDI setup time to TCK rise

TDI hold time from TCK rise

8

ns

J8

4

ns

J9

18

4

ns

J10

ns

2-mA drive

13

9

35

26

29

13

14

20

26

21

26

14

15

16

19

22

25

4-mA drive

8-mA drive

8

J11

J12

J13

t_{TDO_ZDV}

TCK fall to data valid from Hi-Z

ns

8-mA drive with slew rate control

10-mA drive

10

11

14

10

8

12-mA drive

2-mA drive

4-mA drive

8-mA drive

TCK fall to data valid from

data valid

t_{TDO_DV}

8-mA drive with slew rate control

10-mA drive

10

12

7

12-mA drive

2-mA drive

4-mA drive

7

8-mA drive

7

t_{TDO_DVZ}

TCK fall to Hi-Z from data valid

8-mA drive with slew rate control

10-mA drive

8

20

12-mA drive

92

Specifications

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ZHCSH09 –OCTOBER 2017

J2

J3

J4

TCK

J6

J5

图 5-40. JTAG Test Clock Input Timing

TCK

TMS

TDI

J7

J8

J7

J8

TMS Input Valid

J9

J10

J9

J10

TDI Input Valid

J11

J12

J13

TDO

TDO Output Valid

图 5-41. JTAG Test Access Port (TAP) Timing

Specifications

93

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6 Detailed Description

6.1 Overview

The SimpleLink MSP432E401Y Arm Cortex-M4 microcontroller (MCU) provides top performance and

advanced integration. The MSP432E4 product family is positioned for cost-effective applications requiring

significant control processing and connectivity capabilities such as the following:

•

Industrial communication equipment

Network appliances, gateways, and adapters

Residential and commercial site monitoring and control

Remote connectivity and monitoring

Security and access systems

HMI control panels

Factory automation control

Test and measurement equipment

Fire and security systems

Motion control and power inversion

Medical instrumentation

Gaming equipment

Electronic point-of-sale (POS) displays

Smart energy and smart grid solutions

Intelligent lighting control

Vehicle tracking

The MSP432E401Y MCU integrates a large variety of rich communication features to enable a new class

of highly connected designs that can support critical, real-time control with a balance between

performance and power. The MCU features integrated communication peripherals and other high-

performance analog and digital functions to offer a strong foundation for many different target uses, from

human-machine interface to networked system management controllers.

In addition, the MSP432E401Y MCU offers the advantages of widely available development tools from

Arm, System-on-Chip (SoC) infrastructure, and a large user community. Additionally, this MCU uses the

Thumb-compatible Thumb-2 instruction set from Arm to reduce memory requirements and, thereby, cost.

Finally, when using the SimpleLink SDK, the MSP432E401Y MCU is code-compatible with all members of

the SimpleLink series, providing flexibility to fit precise needs.

TI offers a complete solution to get to market quickly, with evaluation and development boards; white

papers and application notes; an easy-to-use peripheral driver library; and a strong support, sales, and

distributor network.

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6.2 Functional Block Diagram

图 6-1 shows the features on the MSP432E401Y MCU. Two on-chip buses connect the core to the

peripherals. The Advanced Peripheral Bus (APB) bus is the legacy bus. The Advanced High-Performance

Bus (AHB) bus provides better back-to-back access performance than the APB bus.

JTAG, SWD

Arm

Cortex-M4F

Bootloader

ROM

DriverLib

(120 MHz)

AES and CRC

Ethernet Bootloater

System

Control and

Clocks

(with Precision

Oscillator)

Flash

ETM

NVIC

FPU

DCode bus

ICode bus

(1024KB)

MPU

System Bus

SRAM

(256KB)

Bus Matrix

SYSTEM PERIPHERALS

Watchdog

Timer

(2 Units)

DMA

Hibernation

Module

EEPROM

(6K)

Tamper

General-

Purpose

Timer (8 Units)

GPIOs

(90)

External

Peripheral

Interface

CRC

Module

DES

Module

AES

Module

SHA/MD5

Module

SERIAL PERIPHERALS

USB OTG

(FS PHY

or ULPI)

UART

(8 Units)

SSI

(4 Units)

I2C

(10 Units)

CAN

Controller

(2 Units)

Ethernet

MAC, PHY, MII

ANALOG PERIPHERALS

12-Bit ADC

(2 Units,

20 Channels)

Analog

Comparator

(3 Units)

MOTION CONTROL PERIPHERALS

PWM

(1 Unit,

8 Signals)

QEI

(1 Unit)

图 6-1. MSP432E401Y High-Level Block Diagram

Detailed Description

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6.3 Arm Cortex-M4F Processor Core

All members of the MSP432E4 family are designed around an Arm Cortex-M processor core. The Arm

Cortex-M processor provides the core for a high-performance low-cost platform that meets the needs of

minimal memory implementation, reduced pin count, and low power consumption, while delivering

outstanding computational performance and exceptional system response to interrupts.

6.3.1 Processor Core

Features of the processor core include:

•

32-bit Arm Cortex-M4F architecture optimized for small-footprint embedded applications

120-MHz operation; 150 DMIPS performance

Outstanding processing performance combined with fast interrupt handling

Thumb-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit Arm

core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of

a few kilobytes of memory for MCU-class applications.

–

Single-cycle multiply instruction and hardware divide

Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral

control

–

Unaligned data access, enabling data to be efficiently packed into memory

•

IEEE 754-compliant single-precision floating-point unit (FPU)

16-bit SIMD vector processing unit

Fast code execution permits slower processor clock or increases sleep mode time

Harvard architecture characterized by separate buses for instruction and data

Efficient processor core, system, and memories

Hardware division and fast digital-signal-processing orientated multiply accumulate

Saturating arithmetic for signal processing

Deterministic high-performance interrupt handling for time-critical applications

Memory protection unit (MPU) to provide a privileged mode for protected operating system functionality

Enhanced system debug with extensive breakpoint and trace capabilities

Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and tracing

Migration from the Arm7^®processor family for better performance and power efficiency

Optimized for single-cycle flash memory use up to specific frequencies; see the Internal Memory

chapter of the MSP432E4 SimpleLink™ Microcontrollers Technical Reference Manual for more

information.

•

Ultra-low-power consumption with integrated sleep modes

6.3.2 System Timer (SysTick)

SysTick provides a simple, 24-bit, clear-on-write, decrementing, wrap-on-zero counter with a flexible

control mechanism. The counter can be used in several different ways, for example:

•

An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick

routine

•

A high-speed alarm timer using the system clock

A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and

the dynamic range of the counter

•

A simple counter used to measure time to completion and time used

An internal clock-source control based on missing or meeting durations

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6.3.3 Nested Vectored Interrupt Controller (NVIC)

The NVIC and Cortex-M4F core prioritize and handle all exceptions in handler mode. The processor state

is automatically stored to the stack on an exception and automatically restored from the stack at the end

of the interrupt service routine (ISR). The interrupt vector is fetched in parallel to the state saving, enabling

efficient interrupt entry. The processor supports tail-chaining, meaning that back-to-back interrupts can be

performed without the overhead of state saving and restoration. Software can set 8 priority levels on 7

exceptions (system handlers) and 109 interrupts.

•

Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining (these

values reflect no FPU stacking)

•

External nonmaskable interrupt signal (NMI) available for immediate execution of NMI handler for

safety critical applications

•

Dynamically reprioritizable interrupts

Exceptional interrupt handling through hardware implementation of required register manipulations

表 6-1 lists the interrupts.

表 6-1. Interrupts

INTERRUPT NUMBER

(BIT IN INTERRUPT

REGISTERS)

VECTOR ADDRESS OR

OFFSET

VECTOR NUMBER

DESCRIPTION

0x0000.0000 to

0x0000.003C

0 to 15

–

Processor exceptions

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

0

0x0000.0040

0x0000.0044

0x0000.0048

0x0000.004C

0x0000.0050

0x0000.0054

0x0000.0058

0x0000.005C

0x0000.0060

0x0000.0064

0x0000.0068

0x0000.006C

0x0000.0070

0x0000.0074

0x0000.0078

0x0000.007C

0x0000.0080

0x0000.0084

0x0000.0088

0x0000.008C

0x0000.0090

0x0000.0094

0x0000.0098

0x0000.009C

0x0000.00A0

0x0000.00A4

0x0000.00A8

0x0000.00AC

0x0000.00B0

GPIO Port A

1

GPIO Port B

2

GPIO Port C

3

GPIO Port D

4

GPIO Port E

5

UART0

6

UART1

7

SSI0

8

I2C0

9

PWM fault

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

PWM generator 0

PWM generator 1

PWM generator 2

QEI0

ADC0 sequence 0

ADC0 sequence 1

ADC0 sequence 2

ADC0 sequence 3

Watchdog timers 0 and 1

16-/32-Bit Timer 0A

16-/32-Bit Timer 0B

16-/32-Bit Timer 1A

16-/32-Bit Timer 1B

16-/32-Bit Timer 2A

16-/32-Bit Timer 2B

Analog comparator 0

Analog comparator 1

Analog comparator 2

System control

Detailed Description

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表 6-1. Interrupts (continued)

INTERRUPT NUMBER

(BIT IN INTERRUPT

REGISTERS)

VECTOR ADDRESS OR

OFFSET

VECTOR NUMBER

DESCRIPTION

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

0x0000.00B4

0x0000.00B8

0x0000.00BC

0x0000.00C0

0x0000.00C4

0x0000.00C8

0x0000.00CC

0x0000.00D0

0x0000.00D4

0x0000.00D8

0x0000.00DC

0x0000.00E0

0x0000.00E4

0x0000.00E8

0x0000.00EC

0x0000.00F0

0x0000.00F4

0x0000.00F8

0x0000.00FC

0x0000.0100

0x0000.0104

0x0000.0108

0x0000.010C

0x0000.0110

0x0000.0114

0x0000.0118

0x0000.011C

0x0000.0120

0x0000.0124

0x0000.0128

0x0000.012C

0x0000.0130

0x0000.0134

0x0000.0138

0x0000.013C

0x0000.0140

0x0000.0144

0x0000.0148

0x0000.014C

–

Flash memory control

GPIO port F

GPIO port G

GPIO port H

UART2

SSI1

16-/32-Bit Timer 3A

16-/32-Bit Timer 3B

I2C1

CAN0

CAN1

Ethernet MAC

HIB

USB MAC

PWM generator 3

µDMA 0 Software

µDMA 0 Error

ADC1 sequence 0

ADC1 sequence 1

ADC1 sequence 2

ADC1 sequence 3

EPI0

GPIO port J

GPIO port K

GPIO port L

SSI2

SSI3

UART3

UART4

UART5

UART6

UART7

I2C2

I2C3

Timer 4A

Timer 4B

Timer 5A

Timer 5B

Floating-Point Exception (imprecise)

Reserved

–

Reserved

0x0000.0158

0x0000.015C

0x0000.0160

0x0000.0164

–

I2C4

I2C5

GPIO port M

GPIO port N

Reserved

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表 6-1. Interrupts (continued)

INTERRUPT NUMBER

(BIT IN INTERRUPT

REGISTERS)

VECTOR ADDRESS OR

OFFSET

VECTOR NUMBER

DESCRIPTION

91

75

76

0x0000.016C

0x0000.017

0x0000.0174

0x0000.0178

0x0000.017C

0x0000.0180

0x0000.0184

0x0000.0188

0x0000.018C

0x0000.0190

0x0000.0194

0x0000.0198

0x0000.019C

0x0000.01A0

0x0000.01A4

0x0000.01A8

0x0000.01AC

–

Tamper

92

GPIO port P (Summary or P0)

GPIO port P1

GPIO port P2

GPIO port P3

GPIO port P4

GPIO port P5

GPIO port P6

GPIO port P7

GPIO port Q (summary or Q0)

GPIO port Q1

GPIO port Q2

GPIO port Q3

GPIO port Q4

GPIO port Q5

GPIO port Q6

GPIO port Q7

Reserved

93

77

94

78

95

79

96

80

97

81

98

82

99

83

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

84

85

86

87

88

89

90

91

92

93

–

Reserved

94

0x0000.01B8

0x0000.01BC

0x0000.01C0

–

SHA/MD5

95

AES

96

DES

97

Reserved

98

0x0000.01C8

0x0000.01CC

0x0000.01D0

0x0000.01D4

0x0000.01D8

0x0000.01DC

–

16-/32-Bit Timer 6A

16-/32-Bit Timer 6B

16-/32-Bit Timer 7A

16-/32-Bit Timer 7B

I2C6

99

100

101

102

103

104

105

106

107

108

109

110

111

I2C7

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

0x0000.01F4

0x0000.01F8

–

I2C8

I2C9

Reserved

6.3.4 System Control Block (SCB)

The SCB provides system implementation information and system control, including configuration, control,

and reporting of system exceptions.

6.3.5 Memory Protection Unit (MPU)

The MPU supports the standard Arm7 Protected Memory System Architecture (PMSA) model. The MPU

provides full support for protection regions, overlapping protection regions, access permissions, and

exporting memory attributes to the system.

Detailed Description

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6.3.6 Floating-Point Unit (FPU)

The FPU fully supports single-precision add, subtract, multiply, divide, multiply-and-accumulate, and

square root operations. It also provides conversions between fixed-point and floating-point data formats,

and floating-point constant instructions.

•

32-bit instructions for single-precision (C float) data-processing operations

Combined multiply and accumulate instructions for increased precision (fused MAC)

Hardware support for conversion, addition, subtraction, multiplication with optional accumulate,

division, and square-root

•

Hardware support for denormals and all IEEE rounding modes

32 dedicated 32-bit single-precision registers, also addressable as 16 double-word registers

Decoupled 3-stage pipeline

6.4 On-Chip Memory

The following on-chip memories are supported:

•

256KB of single-cycle SRAM

1024KB of flash memory

6KB of EEPROM

Internal ROM loaded with SimpleLink SDK software:

–

Peripheral driver library

Bootloader

6.4.1 SRAM

The MSP432E401Y MCU provides 256KB of single-cycle on-chip SRAM. The internal SRAM of the device

is at offset 0x2000.0000 of the device memory map.

The SRAM is implemented using four 32-bit-wide interleaving SRAM banks (separate SRAM arrays),

which allow for increased speed between memory accesses. The SRAM memory provides nearly 2 GBps

of memory bandwidth at a 120-MHz clock frequency.

Because read-modify-write (RMW) operations are time consuming, Arm has introduced bit-banding

technology in the Cortex-M4F processor. With a bit-band-enabled processor, certain regions in the

memory map (SRAM and peripheral space) can use address aliases to access individual bits in an atomic

operation.

Data can be transferred to and from SRAM by the following masters:

•

µDMA

USB

Ethernet controller

6.4.2 Flash Memory

The MSP432E401Y MCU provides 1024KB of on-chip flash memory. The flash memory is configured as

four banks of 16K × 128 bits (4 × 256KB total) that are 2-way interleaved. Memory blocks can be marked

as read only or execute only, providing different levels of code protection. Read-only blocks cannot be

erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks

cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism,

protecting the contents of those blocks from being read by either the controller or a debugger.

Two sets of instruction prefetch buffers provide enhanced performance and power savings. Each prefetch

buffer is 2 × 256 bits and can be combined as a 4 × 256-bit prefetch buffer.

The flash can also be accessed by the µDMA in run mode.

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6.4.3 ROM

The ROM is preprogrammed with the following software and programs:

•

Peripheral driver library

Bootloader

The SimpleLink MSP432E4 SDK driver library is a royalty-free software library for controlling on-chip

peripherals with a bootloader capability. The library performs both peripheral initialization and control

functions, with a choice of polled or interrupt-driven peripheral support. In addition, the library is designed

to take full advantage of the stellar interrupt performance of the Arm Cortex-M4F core. No special

pragmas or custom assembly code prologue or epilogue functions are required. For applications that

require in-field programmability, the royalty-free bootloader can act as an application loader and support

in-field firmware updates.

6.4.4 EEPROM

The EEPROM includes the following features:

•

6KB of memory accessible as 1536 32-bit words

96 blocks of 16 words (64 bytes) each

Built-in wear leveling

Access protection per block

Lock protection option for the whole peripheral as well as per block using 32-bit to 96-bit unlock codes

(application selectable)

•

Interrupt support for write completion to avoid polling

Endurance of 500k writes (when writing at fixed offset in every alternate page in circular fashion) to

15M operations (when cycling through two pages) per each 2-page block.

Detailed Description

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6.4.5 Memory Map

The device supports a 4GB address space that is divided into eight 512MB zones (see 图 6-2).

0xFFFF.FFFF

Private Peripheral Bus

0xE000.0000

0xDFFF.FFFF

External Device

External RAM

Peripherals

0xC000.0000

0xBFFF.FFFF

0xA000.0000

0x9FFF.FFFF

0x8000.0000

0x9FFF.FFFF

0x6000.0000

0x5FFF.FFFF

0x4000.0000

0x3FFF.FFFF

SRAM

Code

0x2000.0000

0x1FFF.FFFF

0x0000.0000

图 6-2. Device Memory Zones

6.5 Peripherals

6.5.1 External Peripheral Interface (EPI)

The EPI provides access to external devices using a parallel path. Unlike communications peripherals

such as SSI, UART, and I²C, the EPI acts as a bus to external peripherals and memory.

The EPI has the following features:

•

8-, 16-, or 32-bit dedicated parallel bus for external peripherals and memory

Memory interface supports contiguous memory access independent of data bus width, thus enabling

code execution directly from SDRAM, SRAM, and flash memory

•

Blocking and nonblocking reads

Separates processor from timing details through use of an internal write FIFO

Efficient transfers using µDMA

–

Separate channels for read and write

Read channel request asserted by programmable levels on the internal Nonblocking Read FIFO

(NBRFIFO)

–

Write channel request asserted by empty on the internal Write FIFO (WFIFO)

The EPI supports three primary functional modes: SDRAM mode, traditional host-bus mode, and general-

purpose mode. The EPI module also provides custom GPIOs; however, unlike regular GPIOs, the EPI

module uses a FIFO in the same way as a communication mechanism and is speed-controlled using

clocking.

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•

SDRAM mode

–

Supports ×16 (single data rate) SDRAM at up to 60 MHz

Supports low-cost SDRAMs up to 64MB (512 Mb)

Includes automatic refresh and access to all banks and rows

Includes a sleep (standby) mode to keep contents active with minimal power draw

Multiplexed address and data interface for reduced pin count

•

Host-bus mode

–

Traditional ×8 and ×16 MCU bus interface capabilities

Similar device compatibility options as PIC, ATmega, 8051, and others

Access to SRAM, NOR flash memory, and other devices, with up to 1MB of addressing in

nonmultiplexed mode and 256MB in multiplexed mode (512MB in host bus 16 mode with no byte

selects)

–

Support for up to 512Mb PSRAM in quad chip select mode, with dedicated configuration register

read and write enable

–

Support of both muxed and demuxed address and data

Access to a range of devices supporting the nonaddress FIFO ×8 and ×16 interface variant, with

support for external FIFO (XFIFO) EMPTY and FULL signals

–

Speed controlled, with read and write data wait-state counters

Support for read or write burst mode to Host Bus

Multiple chip-select modes including single, dual, and quad chip selects, with and without ALE

External iRDY signal provided for stall capability of reads and writes

Manual chip-enable (or use extra address pins)

•

General-purpose mode

–

Wide parallel interfaces for fast communications with CPLDs and FPGAs

Data widths up to 32 bits

Data rates up to 150 MB/second

Optional "address" sizes from 4 bits to 20 bits

Optional clock output, read and write strobes, framing (with counter-based size), and clock-enable

input

General parallel GPIO

–

1 to 32 bits, FIFO with speed control

Useful for custom peripherals or for digital data acquisition and actuator controls

6.5.2 Cyclical Redundancy Check (CRC)

The CRC computation module is for uses such as message transfer and safety system checks. This

module can be used with the AES and DES modules. The CRC has the following features:

•

Support four major CRC forms:

–

CRC16-CCITT as used by CCITT/ITU X.25

CRC16-IBM as used by USB and ANSI

CRC32-IEEE as used by IEEE 802.3 and MPEG-2

CRC32C as used by G.Hn

•

Allows word and byte feed

Supports automatic initialization and manual initialization

Supports MSb and LSb

Supports CCITT post-processing

Can be fed by µDMA, flash memory, and code

Detailed Description

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6.5.3 Advanced Encryption Standard (AES) Accelerator

The AES accelerator module provides hardware-accelerated data encryption and decryption operations

based on a binary key. The AES module is a symmetric cipher module that supports a 128-, 192-, or 256-

bit key in hardware for both encryption and decryption.

The AES has following features:

•

Support for basic AES encryption and decryption operations:

–

Galois/counter mode (GCM) with basic GHASH operation

Counter mode with CBC-MAC (CCM)

XTS mode

•

Availability of the following feedback operating modes:

–

Electronic code book mode (ECB)

Cipher block chaining mode (CBC)

Counter mode (CTR)

Cipher feedback mode (CFB), 128-bit

F8 mode

•

Key sizes 128-, 192-, and 256-bits

Support for CBC_MAC and Fedora 9 (F9) authentication modes

Basic GHASH operation (when selecting no encryption)

Key scheduling in hardware

Support for µDMA transfers

Fully synchronous design

6.5.4 Data Encryption Standard (DES) Accelerator

The DES module provides hardware accelerated data encryption and decryption functions. The module

runs either the single DES or the triple DES (3DES) algorithm and supports electronic codebook (ECB),

cipher block chaining (CBC), and cipher feedback (CFB) modes of operation.

The DES accelerator includes the following main features:

•

DES/3DES encryption and decryption algorithm compliant with the FIPS 180-3 standard

Feedback modes: ECB, CBC, CFB

Host interrupt or µDMA driven modes of operation. µDMA support for data and context in and result

out

•

Fully synchronous design

Internal wide-bus interface

6.5.5 Secure Hash Algorithm/Message Digest Algorithm (SHA/MD5) Accelerator

The SHA/MD5 module provides hardware-accelerated hash functions and can run:

•

MD5 message digest algorithm developed by Ron Rivest in 1991

SHA-1 algorithm compliant with the FIPS 180-3 standard

SHA-2 (SHA-224 and SHA-256) algorithm compliant with the FIPS 180-3 standard

Hash message authentication code (HMAC) operation

The algorithms produce a condensed representation of a message or a data file, which can then be used

to verify the message integrity.

The SHA/MD5 accelerator module includes the following main features:

•

Hashing of 0 to (2³³– 2) bytes of data [of which (2³²– 1) bytes are in one pass] using the MD5, SHA-

1, SHA-224, or SHA-256 hash algorithm (byte granularity only, no support for bit granularity)

•

Automatic HMAC key preprocessing for HMAC keys up to 64 bytes

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•

Host-assisted HMAC key preprocessing for HMAC keys larger than 64 bytes

HMAC from precomputes (inner and outer digest) for improved performance on small blocks

Supports µDMA operation for data and context in and result out transfers

Supports interrupt to read the digest (signature)

6.5.6 Serial Communications Peripherals

Both asynchronous and synchronous serial communications are supported with:

•

10/100 Ethernet MAC with advanced IEEE 1588 PTP hardware; integrated PHY provided

Two CAN 2.0 A and B controllers

USB 2.0 controller OTG, host, or device with optional high speed using external PHY through ULPI

interface

•

Eight UARTs with IrDA, 9-bit, and ISO 7816 support

Ten I2C modules with four transmission speeds including high-speed mode

Four Quad Synchronous Serial Interface (QSSI) modules with bi- and quad-SSI support

The following sections provide more detail on each of these communications functions.

6.5.6.1 Ethernet MAC and PHY

The Ethernet controller consists of a fully integrated media access controller (MAC) and network physical

(PHY) interface with the following features:

•

Conforms to the IEEE 802.3 specification

–

10BASE-T and 100BASE-TX IEEE-802.3 compliant

Supports 10- and 100-Mbps data transmission rates

Supports full-duplex and half-duplex (CSMA/CD) operation

Supports flow control and back pressure

Full-featured and enhanced auto-negotiation

Supports IEEE 802.1Q VLAN tag detection

•

Conforms to IEEE 1588-2002 timestamp PTP protocol and the IEEE 1588-2008 advanced timestamp

specification

–

Transmit and receive frame timestamping

Precision time protocol

Flexible pulse per second output

Supports coarse and fine correction methods

•

Multiple addressing modes

–

Four MAC address filters

Programmable 64-bit hash filter for multicast address filtering

Promiscuous mode support

Processor offloading

–

Programmable insertion (TX) or deletion (RX) of preamble and start-of-frame data

Programmable generation (TX) or deletion (RX) of CRC and pad data

IP header and hardware checksum checking (IPv4, IPv6, TCP, UDP, ICMP)

Highly configurable

–

LED activity selection

Supports network statistics with RMON and MIB counters

Supports magic packet and wake-up frames

Detailed Description

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•

Efficient transfers using integrated µDMA

–

Dual-buffer (ring) or linked-list (chained) descriptors

Round-robin or fixed priority arbitration between TX and RX

Descriptors support transfer blocks size up to 8KB

Programmable interrupts for flexible system implementation

•

Physical media manipulation

–

MDI/MDI-X cross-over support

Register-programmable transmit amplitude

Automatic polarity correction and 10BASE-T signal reception

6.5.6.2 Controller Area Network (CAN)

CAN is a multicast shared serial-bus standard for connecting electronic control units (ECUs). CAN was

specifically designed to be robust in electromagnetically noisy environments and can use a differential

balanced line like RS-485 or twisted-pair wire. Originally created for automotive purposes, it is now used in

many embedded control applications (for example, industrial or medical). Bit rates up to 1 Mbps are

possible at network lengths below 40 meters. Decreased bit rates allow longer network distances (for

example, 125 kbps at 500 m).

A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis of the

identifier received whether it should process the message. The identifier also determines the priority that

the message enjoys in competition for bus access. Each CAN message can transmit from 0 to 8 bytes of

user information.

Each of the two CAN units includes the following features:

•

CAN protocol version 2.0 part A/B

Bit rates up to 1 Mbps

32 message objects with individual identifier masks

Maskable interrupt

Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications

Programmable loopback mode for self-test operation

Programmable FIFO mode enables storage of multiple message objects

Gluelessly attaches to an external CAN transceiver through the CANnTX and CANnRX signals

6.5.6.3 Universal Serial Bus (USB)

USB is a serial bus standard designed to allow connection and disconnection of peripherals using a

standardized interface without rebooting the system.

One USB controller supports high-speed and full-speed multiple-point communications and complies with

the USB 2.0 standard for high-speed function. The USB controller can have three configurations: USB

device, USB host, and USB OTG (negotiated on-the-go as host or device when connected to other USB-

enabled systems). Support for full-speed communication is provided by using the integrated USB PHY or

optionally, a high-speed ULPI can communicate to an external PHY.

The USB module has the following features:

•

Complies with USB-IF (Implementer's Forum) certification standards

USB 2.0 high-speed (480 Mbps) operation with the integrated ULPI communicating with an external

PHY

•

Link power-management support that uses link-state awareness to reduce power usage

Four transfer types: control, interrupt, bulk, and isochronous

16 endpoints

–

1 dedicated control IN endpoint and 1 dedicated control OUT endpoint

7 configurable IN endpoints and 7 configurable OUT endpoints

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•

4KB of dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte

isochronous packet size

•

VBUS droop detection and interrupt

Integrated USB DMA with bus master capability

–

Up to eight RX endpoint channels and up to eight TX endpoint channels are available.

Each channel can be separately programmed to operate in different modes.

Incremental burst transfers of 4, 8, 16, or unspecified length supported

6.5.6.4 Universal Asynchronous Receiver/Transmitter (UART)

A UART is an integrated circuit used for RS-232C serial communications, containing a transmitter

(parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately.

Eight fully programmable 16C550-type UARTs are integrated. Although the functionality is similar to a

16C550 UART, this UART design is not register compatible. The UART can generate individually masked

interrupts from the RX, TX, modem flow control, modem status, and error conditions. The module

generates one combined interrupt when any of the interrupts are asserted and are unmasked.

The UARTs have the following features:

•

Programmable baud-rate generator allowing speeds up to 7.5 Mbps for regular speed (divide by 16)

and 15 Mbps for high speed (divide by 8)

•

Separate 16×8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading

Programmable FIFO length, including a 1-byte-deep operation providing conventional double-buffered

interface

•

FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8

Standard asynchronous communication bits for start, stop, and parity

Line-break generation and detection

Fully programmable serial interface characteristics

–

5, 6, 7, or 8 data bits

Even, odd, stick, or no-parity bit generation/detection

1 or 2 stop bit generation

•

IrDA serial-IR (SIR) encoder and decoder providing

–

Programmable use of IrDA Serial Infrared (SIR) or UART I/O

Support of IrDA SIR encoder and decoder functions for data rates up to 115.2 kbps half-duplex

Support of normal 3/16 and low-power (1.41 to 2.23 µs) bit durations

Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-

power mode bit duration

•

Support for communication with ISO 7816 smart cards

Modem functionality available on the following UARTs:

–

UART0 (modem flow control and modem status)

UART1 (modem flow control and modem status)

UART2 (modem flow control)

UART3 (modem flow control)

UART4 (modem flow control)

•

EIA-485 9-bit support

Standard FIFO-level and end-of-transmission interrupts

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•

Efficient transfers using µDMA

–

Separate channels for transmit and receive

Receive single request asserted when data is in the FIFO; burst request asserted at programmed

FIFO level

–

Transmit single request asserted when there is space in the FIFO; burst request asserted at

programmed FIFO level

•

The Global Alternate Clock (ALTCLK) resource or System Clock (SYSCLK) can be used to generate

the baud clock

6.5.6.5 Inter-Integrated Circuit (I²C)

The I²C bus provides bidirectional data transfer through a 2-wire design (a serial data line SDA and a

serial clock line SCL). The I²C bus interfaces to external I²C devices such as serial memory (RAMs and

ROMs), networking devices, LCDs, tone generators, and so on. The I²C bus can also be used for system

testing and diagnostic purposes in product development and manufacture.

Each device on the I²C bus can be designated as either a master or a slave. The I2C module supports

both sending and receiving data as either a master or a slave and can operate simultaneously as both a

master and a slave. Both the I²C master and slave can generate interrupts.

The I2C modules include the following features:

•

Devices on the I²C bus can be designated as either a master or a slave

–

Supports both transmitting and receiving data as either a master or a slave

Supports simultaneous master and slave operation

•

Four I²C modes

–

Master transmit

Master receive

Slave transmit

Slave receive

•

Two 8-entry FIFOs for receive and transmit data

FIFOs can be independently assigned to master or slave

Four transmission speeds:

–

Standard (100 kbps)

Fast-mode (400 kbps)

Fast-mode plus (1 Mbps)

High-speed mode (3.33 Mbps)

•

Glitch suppression

SMBus support through software

–

Clock low time-out interrupt

Dual slave address capability

Quick command capability

•

Master and slave interrupt generation

–

Master generates interrupts when a transmit or receive operation completes (or aborts due to an

error)

–

Slave generates interrupts when data has been transferred or requested by a master or when a

START or STOP condition is detected

•

Master with arbitration and clock synchronization, multiple-master support, and 7-bit addressing mode

Efficient transfers using µDMA

–

Separate channels for transmit and receive

Ability to execute single data transfers or burst data transfers using the RX and TX FIFOs in the I²C

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6.5.6.6 Quad Synchronous Serial Interface (QSSI)

QSSI is a bidirectional communications interface that converts data between parallel and serial. The QSSI

module performs serial-to-parallel conversion on data received from a peripheral device and performs

parallel-to-serial conversion on data transmitted to a peripheral device. The QSSI module can be

configured as either a master or slave device. As a slave device, the QSSI module can also be configured

to disable its output, which allows a master device to be coupled with multiple slave devices. The TX and

RX paths are buffered with separate internal FIFOs.

The QSSI module also includes a programmable bit rate clock divider and prescaler to generate the

output serial clock derived from the input clock of the QSSI module. Bit rates are generated based on the

input clock, and the maximum bit rate is determined by the connected peripheral.

The four QSSI modules each support the following features:

•

Four QSSI channels with advanced, bi-SSI, and quad-SSI functionality

Programmable interface operation for Freescale SPI or TI synchronous serial interfaces in legacy

mode. Support for Freescale interface in Bi- and Quad-SSI mode.

•

Master or slave operation

Programmable clock bit rate and prescaler

Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep

Programmable data frame size from 4 to 16 bits

Internal loopback test mode for diagnostic/debug testing

Standard FIFO-based interrupts and end-of-transmission interrupt

Efficient transfers using µDMA

–

Separate channels for transmit and receive

Receive single request asserted when data is in the FIFO; burst request asserted when FIFO

contains four entries

–

Transmit single request asserted when there is space in the FIFO; burst request asserted when

four or more entries are available to be written in the FIFO

Maskable µDMA interrupts for receive and transmit complete

•

Global alternate clock (ALTCLK) resource or system clock (SYSCLK) can be used to generate baud

clock.

6.5.7 System Integration

A variety of standard system functions are integrated into the device, including:

•

Direct memory access (DMA) controller (see 节 6.5.7.1)

System control and clocks including on-chip precision 16-MHz oscillator (see 节 6.5.7.2)

Eight 32-bit timers (each timer can be configured as two 16-bit timers) (see 节 6.5.7.3)

Lower-power battery-backed Hibernation module (see 节 6.5.7.5)

RTC in Hibernation module

Two watchdog timers (see 节 6.5.7.6)

–

One timer runs off the main oscillator.

One timer runs off the precision internal oscillator.

•

90 GPIOs, depending on configuration (see 节 6.5.7.7)

–

Highly flexible pin multiplexing allows use as GPIO or one of several peripheral functions.

GPIOs are independently configurable to 2-, 4-, 8-, 10-, or 12-mA drive capability.

Up to 4 GPIOs can have 18-mA drive capability.

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6.5.7.1 Direct Memory Access (DMA)

The DMA controller is known as micro-DMA (µDMA). The µDMA controller provides a way to offload data

transfer tasks from the Cortex-M4F processor, allowing for more efficient use of the processor and the

available bus bandwidth. The µDMA controller can perform transfers between memory and peripherals. It

has dedicated channels for each supported on-chip module and can be programmed to automatically

perform transfers between peripherals and memory as the peripheral is ready to transfer more data. The

µDMA controller provides the following features:

•

Arm PrimeCell 32-channel configurable µDMA controller

Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer

modes

–

Basic for simple transfer scenarios

Ping-pong for continuous data flow

Scatter-gather for a programmable list of up to 256 arbitrary transfers initiated from one request

•

Highly flexible and configurable channel operation

–

Independently configured and operated channels

Dedicated channels for supported on-chip modules

Flexible channel assignments

One channel each for receive and transmit path for bidirectional modules

Dedicated channel for software-initiated transfers

Per-channel configurable priority scheme

Optional software-initiated requests for any channel

•

Two levels of priority

Design optimizations for improved bus access performance between µDMA controller and the

processor core

–

µDMA controller access is subordinate to core access

RAM striping

Peripheral bus segmentation

•

Data sizes of 8, 16, and 32 bits

Transfer size is programmable in binary steps from 1 to 1024

Source and destination address increment size of byte, halfword, word, or no increment

Maskable peripheral requests

Interrupt on transfer completion, with a separate interrupt per channel

Each DMA channel has up to nine possible assignments that are selected using the DMA Channel Map

Select n (DMACHMAPn) registers with 4-bit assignment fields for each µDMA channel.

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6.5.7.2 System Control and Clocks

System control determines the overall operation of the device. It provides information about the device,

controls power-saving features, controls the clocking of the device and individual peripherals, and handles

reset detection and reporting.

•

Device identification information: version, part number, SRAM size, flash memory size, and so on

Power control

–

On-chip fixed low dropout (LDO) voltage regulator

Hibernation module manages the power-up and power-down 3.3-V sequencing and control for the

core digital logic and analog circuits

–

Low-power options for MCU: sleep and deep-sleep modes with clock gating

Low-power options for on-chip modules: software controls shutdown of individual peripherals and

memory

–

3.3-V supply brownout detection and reporting through interrupt or reset

•

Multiple clock sources for the system clock. The MCU is clocked by the system clock (SYSCLK) that is

distributed to the processor and integrated peripherals after clock gating. The SYSCLK frequency is

based on the frequency of the clock source and a divisor factor. A PLL is provided for the generation of

system clock frequencies in excess of the reference clock provided. The reference clocks for the PLL

are the PIOSC and the main crystal oscillator. The following clock sources are provided to the MCU:

–

16-MHz precision oscillator (PIOSC)

Main oscillator (MOSC): A frequency-accurate clock source by one of two means: an external

single-ended clock source is connected to the OSC0 input pin, or an external crystal is connected

across the OSC0 input and OSC1 output pins.

–

Low-frequency internal oscillator (LFIOSC): On-chip resource used during power-saving modes.

Hibernate RTC oscillator (RTCOSC): A clock that can be configured to be the 32.768-kHz external

oscillator source from the HIB module or the HIB low-frequency clock source (HIB LFIOSC), which

is in the HIB module.

•

Flexible reset sources

–

Power-on reset (POR)

Reset pin assertion

Brownout reset (BOR) detector alerts to system power drops

Software reset

Watchdog timer reset

Hibernation module event

MOSC failure

•

128-bit unique identifier for individual device identification

6.5.7.3 Programmable Timers

Programmable timers can be used to count or time external events that drive the Timer input pins. Each

16- or 32-bit General-Purpose Timer Module (GPTM) block provides two 16-bit timers/counters that can

be configured to operate independently as timers or event counters. These two timers/counters can also

be configured to operate as one 32-bit timer or one 32-bit RTC. Timers can also be used to trigger analog-

to-digital conversions and DMA transfers.

The GPTM contains eight 16- or 32-bit GPTM blocks with the following functional options:

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•

Operating modes

–

16- or 32-bit programmable one-shot timer

16- or 32-bit programmable periodic timer

16-bit general-purpose timer with an 8-bit prescaler

32-bit RTC when using an external 32.768-kHz clock as the input

16-bit input-edge count- or time-capture modes with an 8-bit prescaler

16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the PWM

signal

•

Count up or down

Sixteen 16- or 32-bit capture/compare PWM (CCP) pins

Daisy-chaining of timer modules lets one timer initiate multiple timing events

Timer synchronization lets selected timers start counting on the same clock cycle

ADC event trigger

User-enabled stalling when the MCU asserts the CPU halt flag during debug (excluding RTC mode)

Can determine the elapsed time between the assertion of the timer interrupt and entry into the ISR

Efficient transfers using µDMA

–

Dedicated channel for each timer

Burst request generated on timer interrupt

6.5.7.4 Capture Compare PWM (CCP) Pins

CCP pins can be used by the General-Purpose Timer module to time or count external events using the

CCP pin as an input. Alternatively, the GPTM can generate a simple PWM output on the CCP pin.

The 16/32-bit CCP pins can be programmed to operate in the following modes:

•

Capture: The GP timer is incremented or decremented by programmed events on the CCP input. The

GP timer captures and stores the current timer value when a programmed event occurs.

•

Compare: The GP timer is incremented or decremented by programmed events on the CCP input. The

GP timer compares the current value with a stored value and generates an interrupt when a match

occurs.

•

PWM: The GP timer is incremented or decremented by the system clock. A PWM signal is generated

based on a match between the counter value and a value stored in a match register and is output on

the CCP pin.

6.5.7.5 Hibernation (HIB) Module

The HIB module provides logic to switch power off to the main processor and peripherals and to wake on

external or time-based events. The HIB module includes power-sequencing logic and has the following

features:

•

32-bit RTC with 1/32768-second resolution and a 15-bit subseconds counter

–

32-bit RTC seconds match register and a 15-bit subseconds match for timed wakeup and interrupt

generation with 1/32768-second resolution

–

RTC predivider trim for making fine adjustments to the clock rate

•

Hardware calendar function

–

Year, month, day, day of week, hours, minutes, and seconds

Four-year leap compensation

24-hour or AM and PM configuration

•

Two mechanisms for power control

–

System power control using a discrete external regulator

On-chip power control using internal switches under register control

V_DDsupplies power when valid, even if V_BAT> V_DD

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•

Dedicated pin for wake using an external signal

Can configure the external reset (RST) pin or up to four GPIO port pins as wake sources, with

programmable wake level

•

Tamper functionality

–

Support for four tamper inputs

Configurable level, weak pullup, and glitch filter

Configurable tamper event response

Logging of up to four tamper events

Optional BBRAM erase on tamper detection

Tamper detection and wake-from-hibernate capability

Hibernation clock input failure detect with a switch to the internal oscillator on detection

•

RTC operational and hibernation memory valid as long as V_DDor V_BATis valid

Low-battery detection, signaling, and interrupt generation, with optional wake on low battery

GPIO pin state can be retained during hibernation

Clock source from an internal low-frequency oscillator (HIB LFIOSC) or a 32.768-kHz external crystal

or oscillator

•

Sixteen 32-bit words of battery-backed memory to save state during hibernation

Programmable interrupts for:

–

RTC match

External wake

Low battery

6.5.7.6 Watchdog Timers

A watchdog timer is used to regain control when a system has failed due to a software error or to the

failure of an external device to respond in the expected way. The watchdog timer can generate an

interrupt, a nonmaskable interrupt, or a reset when a time-out value is reached. In addition, the watchdog

timer is Arm FiRM-compliant and can be configured to generate an interrupt to the MCU on its first time-

out, and to generate a reset signal on its second time-out. After the watchdog timer has been configured,

the lock register can be written to prevent inadvertently altering the timer configuration.

Two watchdog timer modules are supported: Watchdog Timer 0 uses the system clock for its timer clock;

Watchdog Timer 1 uses the PIOSC as its timer clock. The watchdog timer module has the following

features:

•

32-bit down counter with a programmable load register

Separate watchdog clock with an enable

Programmable interrupt generation logic with interrupt masking and optional NMI function

Lock register protection from runaway software

Reset generation logic with an enable/disable

User-enabled stalling when the MCU asserts the CPU Halt flag during debug

6.5.7.7 Programmable GPIOs

General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The GPIO module is

composed of 15 physical GPIO blocks, each corresponding to an individual GPIO port. The GPIO module

is FiRM-compliant (compliant to the Arm Foundation IP for Real-Time MCUs specification) and supports 0

to 90 programmable I/O pins. The number of GPIOs available depends on the peripherals being used.

•

Up to 90 GPIOs, depending on configuration

Highly flexible pin multiplexing allows use as GPIO or one of several peripheral functions

3.3-V tolerant in input configuration

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•

Advanced high-performance bus (AHB) accesses all ports:

Ports A to H, K to N, P, and Q

–

•

Fast toggle capable of a change every clock cycle for ports on AHB

Programmable control for GPIO interrupts

–

Interrupt generation masking

Edge-triggered on rising, falling, or both

Level-sensitive on high or low values

Per-pin interrupts available on port P and port Q

•

Bit masking in both read and write operations through address lines

Can be used to initiate an ADC sample sequence or a µDMA transfer

Pin state can be retained during hibernation mode; pins on port P can be programmed to wake on

level in hibernation mode

•

Pins configured as digital inputs are Schmitt triggered

Programmable control for GPIO pad configuration

–

Weak pullup or pulldown resistors

2-, 4-, 6-, 8-, 10-, or 12-mA pad drive for digital communication; up to four pads can sink 18-mA for

high-current applications

–

Slew rate control for 8-, 10-, and 12-mA pad drive

Open-drain enables

Digital-input enables

6.5.8 Advanced Motion Control

The motion control functions that are integrated into the device support the following features:

•

Eight advanced PWM outputs for motion and energy applications

Four fault inputs to promote low-latency shutdown

One quadrature encoder input (QEI)

The following sections provides more detail on these motion control functions.

6.5.8.1 Pulse Width Modulation (PWM)

PWM is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used

to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog

signal. Typical applications include switching power supplies and motor control.

One PWM module is included, with four PWM generator blocks and a control block, for a total of eight

PWM outputs. Each PWM generator block contains one timer (16-bit down or up/down counter), two

comparators, a PWM signal generator, a dead-band generator, and an interrupt or ADC-trigger selector.

Each PWM generator block produces two PWM signals that can be either independent signals or a pair of

complementary signals with dead-band delays inserted.

Each PWM generator has the following features:

•

Four fault-condition handling inputs to quickly provide low-latency shutdown and prevent damage to

the motor being controlled

•

One 16-bit counter

–

Runs in down or up/down mode

Output frequency controlled by a 16-bit load value

Synchronized load value updates

Produces output signals at zero and load value

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•

Two PWM comparators

–

Synchronized comparator value updates

Produces output signals on match

PWM signal generator

–

Output PWM signal is constructed based on actions taken as a result of the counter and PWM

comparator output signals.

–

Produces two independent PWM signals

•

Dead-band generator

–

Produces two PWM signals with programmable dead-band delays suitable for driving a half-H

bridge

–

Can be bypassed, leaving input PWM signals unmodified

•

Can initiate an ADC sample sequence

The control block determines the polarity of the PWM signals and which signals are passed through to the

pins. The output of the PWM generation blocks are managed by the output control block before being

passed to the device pins. The PWM control block has the following options:

•

PWM output enable of each PWM signal

Optional output inversion of each PWM signal (polarity control)

Optional fault handling for each PWM signal

Synchronization of timers in the PWM generator blocks

Synchronization of timer/comparator updates across the PWM generator blocks

Extended PWM synchronization of timer/comparator updates across the PWM generator blocks

Interrupt status summary of the PWM generator blocks

Extended PWM fault handling, with multiple fault signals, programmable polarities, and filtering

PWM generators can be operated independently or synchronized with other generators

6.5.8.2 Quadrature Encoder With Index (QEI) Module

A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement into

a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals, the

position, direction of rotation, and speed can be tracked. In addition, a third channel, or index signal, can

be used to reset the position counter. The QEI module interprets the code produced by a quadrature

encoder wheel to integrate position over time and determine direction of rotation. In addition, it can

capture a running estimate of the velocity of the encoder wheel. The input frequency of the QEI inputs

may be as high as 1/4 of the system frequency (for example, 30 MHz for a 120-MHz system).

One QEI module provides control of one motor with the following features:

•

Position integrator that tracks the encoder position

Programmable noise filter on the inputs

Velocity capture using built-in timer

The input frequency of the QEI inputs may be as high as 1/4 of the system frequency (for example,

12.5 MHz for a 50-MHz system)

•

Interrupt generation on:

–

Index pulse

Velocity-timer expiration

Direction change

Quadrature error detection

6.5.9 Analog

Integrated analog functions include:

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•

Two 12-bit ADCs with a total of 20 analog input channels and each with a sample rate of 2 Msps (see

节 6.5.9.1)

•

Three analog comparators (see 节 6.5.9.2)

On-chip voltage regulator

6.5.9.1 ADC

An ADC is a peripheral that converts a continuous analog voltage to a discrete digital number. The ADC

module features 12-bit conversion resolution and supports 20 input channels plus an internal temperature

sensor. Four buffered sample sequencers allow rapid sampling of up to 20 analog input sources without

controller intervention. Each sample sequencer provides flexible programming with fully configurable input

source, trigger events, interrupt generation, and sequencer priority. Each ADC module has a digital

comparator function that lets the conversion value be sent to a comparison unit that provides eight digital

comparators.

Both ADC modules support the following features:

•

20 shared analog input channels

12-bit precision ADC

Single-ended and differential-input configurations

On-chip internal temperature sensor

Maximum sample rate of two million samples/second

Optional, programmable phase delay

Sample and hold window programmability

Four programmable sample conversion sequencers from one to eight entries long, with corresponding

conversion result FIFOs

•

Flexible trigger control

–

Controller (software)

Timers

Analog comparators

PWM

GPIO

•

Hardware averaging of up to 64 samples

Eight digital comparators

Converter uses two external reference signals (VREFA+ and VREFA–) or VDDA and GNDA as the

voltage reference

•

Power and ground for the analog circuitry is separate from the digital power and ground

Efficient transfers using µDMA

–

Dedicated channel for each sample sequencer

ADC module uses burst requests for DMA

•

Global Alternate Clock (ALTCLK) resource or System Clock (SYSCLK) can be used to generate ADC

clock.

6.5.9.2 Analog Comparators

An analog comparator is a peripheral that compares two analog voltages and provides a logical output

that signals the comparison result. The independent integrated analog comparators can be configured to

drive an output or generate an interrupt or ADC event.

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The comparator can provide its output to a device pin, acting as a replacement for an analog comparator

on the board, or it can be used to signal the application via interrupts or triggers to the ADC to cause it to

start capturing a sample sequence. The interrupt generation and ADC triggering logic is separate. This

means, for example, that an interrupt can be generated on a rising edge and the ADC triggered on a

falling edge.

Each analog comparator supports the following functions:

•

Compare external pin input to external pin input or to internal programmable voltage reference

Compare a test voltage against any one of the following voltages:

–

An individual external reference voltage

A shared single external reference voltage

A shared internal reference voltage

6.5.10 JTAG and Arm Serial Wire Debug

The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port (TAP) and

Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for

controlling the associated test logic. The TAP, Instruction Register (IR), and Data Register (DR) can be

used to test the interconnections of assembled printed circuit boards and obtain manufacturing information

on the components. The JTAG port also provides a means of accessing and controlling design-for-test

features such as I/O pin observation and control, scan testing, and debugging. TI replaces the Arm SW-

DP and JTAG-DP with the Arm Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface

combines the SWD and JTAG debug ports into one module. This module provides the standard JTAG

debug and test functionality plus real-time access to system memory without halting the core or requiring

any target resident code. The SWJ-DP interface has the following features:

•

IEEE 1149.1-1990 compatible TAP controller

Four-bit IR chain for storing JTAG instructions

IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, and EXTEST

Arm additional instructions: APACC, DPACC, and ABORT

Integrated Arm Serial Wire Debug (SWD)

–

Serial Wire JTAG Debug Port (SWJ-DP)

Flash Patch and Breakpoint (FPB) unit for implementing breakpoints

Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and

system profiling

–

Instrumentation Trace Macrocell (ITM) for support of printf-style debugging

Embedded Trace Macrocell (ETM) for instruction trace capture

Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer

6.5.11 Peripheral Memory Map

表 6-3 lists the address for each peripheral.

注

Within the memory map, attempts to read or write addresses in reserved spaces result in a

bus fault. In addition, attempts to write addresses in the flash range also result in a bus fault.

表 6-3. Memory Map

START

END

DESCRIPTION

REGISTERS

0x4000.0000

0x4000.1000

0x4000.2000

0x4000.0FFF

0x4000.1FFF

0x4000.3FFF

Watchdog Timer 0

Watchdog Timer 1

Reserved

表 6-32

Detailed Description

119

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表 6-3. Memory Map (continued)

START

END

DESCRIPTION

REGISTERS

0x4000.4000

0x4000.5000

0x4000.6000

0x4000.7000

0x4000.8000

0x4000.9000

0x4000.A000

0x4000.B000

0x4000.C000

0x4000.D000

0x4000.E000

0x4000.F000

0x4001.0000

0x4001.1000

0x4001.2000

0x4001.3000

0x4001.4000

0x4002.0000

0x4002.1000

0x4002.2000

0x4002.3000

0x4002.4000

0x4002.5000

0x4002.6000

0x4002.7000

0x4002.8000

0x4002.9000

0x4002.C000

0x4002.D000

0x4003.0000

0x4003.1000

0x4003.2000

0x4003.3000

0x4003.4000

0x4003.5000

0x4003.6000

0x4003.8000

0x4003.9000

0x4003.A000

0x4003.C000

0x4003.D000

0x4003.E000

0x4004.0000

0x4004.1000

0x4004.2000

0x4005.0000

0x4005.1000

0x4000.4FFF

0x4000.5FFF

0x4000.6FFF

0x4000.7FFF

0x4000.8FFF

0x4000.9FFF

0x4000.AFFF

0x4000.BFFF

0x4000.CFFF

0x4000.DFFF

0x4000.EFFF

0x4000.FFFF

0x4001.0FFF

0x4001.1FFF

0x4001.2FFF

0x4001.3FFF

0x4001.FFFF

0x4002.0FFF

0x4002.1FFF

0x4002.2FFF

0x4002.3FFF

0x4002.4FFF

0x4002.5FFF

0x4002.6FFF

0x4002.7FFF

0x4002.8FFF

0x4002.BFFF

0x4002.CFFF

0x4002.FFFF

0x4003.0FFF

0x4003.1FFF

0x4003.2FFF

0x4003.3FFF

0x4003.4FFF

0x4003.5FFF

0x4003.7FFF

0x4003.8FFF

0x4003.9FFF

0x4003.BFFF

0x4003.CFFF

0x4003.DFFF

0x4003.FFFF

0x4004.0FFF

0x4004.1FFF

0x4004.FFFF

0x4005.0FFF

0x4005.7FFF

GPIO Port A

表 6-17

表 6-25

表 6-30

GPIO Port B

GPIO Port C

GPIO Port D

SSI0

SSI1

SSI2

SSI3

UART0

UART1

UART2

UART3

UART4

UART5

UART6

UART7

Reserved

I2C 0

表 6-20

表 6-17

表 6-23

I2C 1

I2C 2

I2C 3

GPIO Port E

GPIO Port F

GPIO Port G

GPIO Port H

PWM 0

Reserved

QEI0

表 6-24

Reserved

16/32-bit Timer 0

16/32-bit Timer 1

16/32-bit Timer 2

16/32-bit Timer 3

16/32-bit Timer 4

16/32-bit Timer 5

Reserved

ADC0

表 6-18

表 6-6

ADC1

Reserved

Analog Comparator

GPIO Port J

Reserved

CAN0 Controller

CAN1 Controller

Reserved

USB

表 6-8

表 6-17

表 6-7

表 6-31

Reserved

120

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ZHCSH09 –OCTOBER 2017

表 6-3. Memory Map (continued)

START

END

DESCRIPTION

GPIO Port A (AHB aperture)

GPIO Port B (AHB aperture)

GPIO Port C (AHB aperture)

GPIO Port D (AHB aperture)

GPIO Port E (AHB aperture)

GPIO Port F (AHB aperture)

GPIO Port G (AHB aperture)

GPIO Port H (AHB aperture)

GPIO Port J (AHB aperture)

GPIO Port K (AHB aperture)

GPIO Port L (AHB aperture)

GPIO Port M (AHB aperture)

GPIO Port N (AHB aperture)

GPIO Port P (AHB aperture)

GPIO Port Q (AHB aperture)

Reserved

REGISTERS

0x4005.8000

0x4005.9000

0x4005.A000

0x4005.B000

0x4005.C000

0x4005.D000

0x4005.E000

0x4005.F000

0x4006.0000

0x4006.1000

0x4006.2000

0x4006.3000

0x4006.4000

0x4006.5000

0x4006.6000

0x4006.7000

0x400A.F000

0x400B.0000

0x400B.6000

0x400B.7000

0x400B.8000

0x400B.9000

0x400B.A000

0x400C.0000

0x400C.1000

0x400C.2000

0x400C.3000

0x400C.4000

0x400D.0000

0x400D.1000

0x400E.0000

0x400E.1000

0x400E.2000

0x400E.C000

0x400E.D000

0x400F.9000

0x400F.A000

0x400F.C000

0x400F.D000

0x400F.E000

0x400F.F000

0x4010.0000

0x4200.0000

0x4400.0000

0x4403.0000

0x4403.1000

0x4403.2000

0x4005.8FFF

0x4005.9FFF

0x4005.AFFF

0x4005.BFFF

0x4005.CFFF

0x4005.DFFF

0x4005.EFFF

0x4005.FFFF

0x4006.0FFF

0x4006.1FFF

0x4006.2FFF

0x4006.3FFF

0x4006.4FFF

0x4006.5FFF

0x4006.6FFF

0x400A.EFFF

0x400A.FFFF

0x400B.5FFF

0x400B.6FFF

0x400B.7FFF

0x400B.8FFF

0x400B.9FFF

0x400B.FFFF

0x400C.0FFF

0x400C.1FFF

0x400C.2FFF

0x400C.3FFF

0x400C.FFFF

0x400D.0FFF

0x400D.FFFF

0x400E.0FFF

0x400E.1FFF

0x400E.BFFF

0x400E.CFFF

0x400F.8FFF

0x400F.9FFF

0x400F.BFFF

0x400F.CFFF

0x400F.DFFF

0x400F.EFFF

0x400F.FFFF

0x41FF.FFFF

0x43FF.FFFF

0x4402.FFFF

0x4403.0FFF

0x4403.1FFF

0x4403.3FFF

表 6-17

EEPROM and Key Locker

Reserved

表 6-12

Reserved

I2C 8

表 6-20

I2C 9

Reserved

I2C 4

表 6-20

I2C 5

I2C 6

I2C 7

Reserved

EPI0

表 6-13

Reserved

16/32-bit Timer 6

16/32-bit Timer 7

Reserved

表 6-18

Ethernet Controller

Reserved

表 6-14

表 6-29

System Exception

Reserved

Hibernation

表 6-19

表 6-16

表 6-28

表 6-21

Flash Memory Control

System Control

µDMA

Reserved

Bit-banded alias of 0x4000.0000 through 0x400F.FFFF

Reserved

CRC and Cryptographic Control

Reserved (4KB)

表 6-9

Reserved (8KB)

Detailed Description

121

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表 6-3. Memory Map (continued)

START

END

DESCRIPTION

REGISTERS

0x4403.4000

0x4403.6000

0x4403.8000

0x4403.A000

0x4403.F000

0x4404.0000

0x4405.0000

0x4405.1000

0x4405.4000

0x4405.5000

0x6000.0000

0x4403.5FFF

0x4403.7FFF

0x4403.9FFF

0x4403.EFFF

0x4403.FFFF

0x4404.FFFF

0x4405.0FFF

0x4405.3FFF

0x4405.4FFF

0x5FFF.FFFF

0xDFFF.FFFF

SHA/MD5

表 6-26

AES

表 6-4, 表 6-5

DES

表 6-10, 表 6-11

Reserved

Reserved (4KB)

Reserved (64KB)

Reserved

EPHY 0

表 6-15

表 6-13

Reserved

EPI0 Mapped Peripheral and RAM

表 6-4. AES Registers

OFFSET

0x00C

0x010

ACRONYM

REGISTER NAME

AES Key 2_5

AES Key 2_2

AES Key 2_3

AES Key 2_0

AES Key 2_1

AES Key 1_6

AES Key 1_7

AES Key 1_4

AES Key 1_5

AES Key 1_2

AES Key 1_3

AES Key 1_0

AES Key 1_1

AES_KEY2_5

AES_KEY2_2

AES_KEY2_3

AES_KEY2_0

AES_KEY2_1

AES_KEY1_6

AES_KEY1_7

AES_KEY1_4

AES_KEY1_5

AES_KEY1_2

AES_KEY1_3

AES_KEY1_0

AES_KEY1_1

0x014

0x018

0x01C

0x020

0x024

0x028

0x02C

0x030

0x034

0x038

0x03C

0x40 to 0x4C

0x50

AES_IV_IN_0 to AES_IV_IN_3

AES_CTRL

AES Initialization Vector Input 0 to AES Initialization Vector Input 3

AES Control

AES_C_LENGTH_0 to

AES_C_LENGTH_1

0x54 to 0x58

0x5C

AES Crypto Data Length 0 to AES Crypto Data Length 1

AES Authentication Data Length

AES_AUTH_LENGTH

AES_DATA_IN_0 to

AES_DATA_IN_3

AES Data R/W Plaintext/Ciphertext 0 to AES Data R/W Plaintext/Ciphertext

3

0x60 to 0x6C

AES_TAG_OUT_0 to

AES_TAG_OUT_3

0x70 to 0x7C

AES Hash Tag Out 0 to AES Hash Tag Out 3

0x80

0x84

0x88

0x8C

0x90

0x94

AES_REVISION

AES IP Revision Identifier

AES System Configuration

AES System Status

AES Interrupt Status

AES Interrupt Enable

AES Dirty Bits

AES_SYSCONFIG

AES_SYSSTATUS

AES_IRQSTATUS

AES_IRQENABLE

AES_DIRTYBITS

表 6-5. AES µDMA Registers

OFFSET

0x20

ACRONYM

REGISTER NAME

AES_DMAIM

AES_DMARIS

AES_DMAMIS

AES DMA Interrupt Mask

AES DMA Raw Interrupt Status

AES DMA Masked Interrupt Status

0x24

0x28

122

Detailed Description

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ZHCSH09 –OCTOBER 2017

表 6-5. AES µDMA Registers (continued)

OFFSET

ACRONYM

REGISTER NAME

0x2C

AES_DMAIC

AES DMA Interrupt Clear

表 6-6. ADC Registers

OFFSET

0x0

ACRONYM

ADCACTSS

ADCRIS

REGISTER NAME

ADC Active Sample Sequencer

ADC Raw Interrupt Status

0x4

0x8

ADCIM

ADC Interrupt Mask

0xC

ADCISC

ADC Interrupt Status and Clear

ADC Overflow Status

0x10

0x14

0x18

0x1C

0x20

0x24

0x28

0x30

0x34

0x38

0x40

0x44

0x48

0x4C

0x50

0x54

0x58

0x5C

0x60

0x64

0x068

0x06C

0x70

0x74

0x78

0x7C

0x080

0x084

0x088

0x08C

0x090

0x094

0x098

0x09C

0xA0

0xA4

0x0A8

0x0AC

0xB0

ADCOSTAT

ADCEMUX

ADC Event Multiplexer Select

ADC Underflow Status

ADCUSTAT

ADCTSSEL

ADCSSPRI

ADC Trigger Source Select

ADC Sample Sequencer Priority

ADC Sample Phase Control

ADCSPC

ADCPSSI

ADC Processor Sample Sequence Initiate

ADC Sample Averaging Control

ADC Digital Comparator Interrupt Status and Clear

ADC Control

ADCSAC

ADCDCISC

ADCCTL

ADCSSMUX0

ADCSSCTL0

ADCSSFIFO0

ADCSSFSTAT0

ADCSSOP0

ADCSSDC0

ADCSSEMUX0

ADCSSTSH0

ADCSSMUX1

ADCSSCTL1

ADCSSFIFO1

ADCSSFSTAT1

ADCSSOP1

ADCSSDC1

ADCSSEMUX1

ADCSSTSH1

ADCSSMUX2

ADCSSCTL2

ADCSSFIFO2

ADCSSFSTAT2

ADCSSOP2

ADCSSDC2

ADCSSEMUX2

ADCSSTSH2

ADCSSMUX3

ADCSSCTL3

ADCSSFIFO3

ADCSSFSTAT3

ADCSSOP3

ADC Sample Sequence Input Multiplexer Select 0

ADC Sample Sequence Control 0

ADC Sample Sequence Result FIFO 0

ADC Sample Sequence FIFO 0 Status

ADC Sample Sequence 0 Operation

ADC Sample Sequence 0 Digital Comparator Select

ADC Sample Sequence Extended Input Multiplexer Select 0

ADC Sample Sequence 0 Sample and Hold Time

ADC Sample Sequence Input Multiplexer Select 1

ADC Sample Sequence Control 1

ADC Sample Sequence Result FIFO 1

ADC Sample Sequence FIFO 1 Status

ADC Sample Sequence 1 Operation

ADC Sample Sequence 1 Digital Comparator Select

ADC Sample Sequence Extended Input Multiplexer Select 1

ADC Sample Sequence 1 Sample and Hold Time

ADC Sample Sequence Input Multiplexer Select 2

ADC Sample Sequence Control 2

ADC Sample Sequence Result FIFO 2

ADC Sample Sequence FIFO 2 Status

ADC Sample Sequence 2 Operation

ADC Sample Sequence 2 Digital Comparator Select

ADC Sample Sequence Extended Input Multiplexer Select 2

ADC Sample Sequence 2 Sample and Hold Time

ADC Sample Sequence Input Multiplexer Select 3

ADC Sample Sequence Control 3

ADC Sample Sequence Result FIFO 3

ADC Sample Sequence FIFO 3 Status

ADC Sample Sequence 3 Operation

Detailed Description

123

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表 6-6. ADC Registers (continued)

OFFSET

0xB4

ACRONYM

REGISTER NAME

ADCSSDC3

ADC Sample Sequence 3 Digital Comparator Select

0xB8

ADCSSEMUX3

ADCSSTSH3

ADC Sample Sequence Extended Input Multiplexer Select 3

ADC Sample Sequence 3 Sample and Hold Time

ADC Digital Comparator Reset Initial Conditions

0xBC

0xD00

ADCDCRIC

0xE00 to 0xE1C

0xE40 to 0xE5C

0xFC0

ADCDCCTL0 to ADCDCCTL7

ADCDCCMP0 to ADCDCCMP7

ADCPP

ADC Digital Comparator Control 0 to ADC Digital Comparator Control 7

ADC Digital Comparator Range 0 to ADC Digital Comparator Range 7

ADC Peripheral Properties

0xFC4

ADCPC

ADC Peripheral Configuration

0xFC8

ADCCC

ADC Clock Configuration

表 6-7. CAN Registers

OFFSET

0x0

ACRONYM

CANCTL

REGISTER NAME

CAN Control

0x4

CANSTS

CAN Status

0x8

CANERR

CAN Error Counter

CAN Bit Timing

0xC

CANBIT

0x10

0x14

0x18

0x20

0x24

0x28

0x2C

0x30

0x34

0x38

0x3C

0x40

0x44

0x48

0x80

0x84

0x88

0x8C

0x90

0x94

0x98

0x9C

0xA0

0xA4

0xA8

0x100

0x104

0x120

0x124

0x140

0x144

CANINT

CAN Interrupt

CANTST

CAN Test

CANBRPE

CAN Baud Rate Prescaler Extension

CAN IF1 Command Request

CAN IF1 Command Mask

CAN IF1 Mask 1

CANIF1CRQ

CANIF1CMSK

CANIF1MSK1

CANIF1MSK2

CANIF1ARB1

CANIF1ARB2

CANIF1MCTL

CANIF1DA1

CANIF1DA2

CANIF1DB1

CANIF1DB2

CANIF2CRQ

CANIF2CMSK

CANIF2MSK1

CANIF2MSK2

CANIF2ARB1

CANIF2ARB2

CANIF2MCTL

CANIF2DA1

CANIF2DA2

CANIF2DB1

CANIF2DB2

CANTXRQ1

CANTXRQ2

CANNWDA1

CANNWDA2

CANMSG1INT

CANMSG2INT

CAN IF1 Mask 2

CAN IF1 Arbitration 1

CAN IF1 Arbitration 2

CAN IF1 Message Control

CAN IF1 Data A1

CAN IF1 Data A2

CAN IF1 Data B1

CAN IF1 Data B2

CAN IF2 Command Request

CAN IF2 Command Mask

CAN IF2 Mask 1

CAN IF2 Mask 2

CAN IF2 Arbitration 1

CAN IF2 Arbitration 2

CAN IF2 Message Control

CAN IF2 Data A1

CAN IF2 Data A2

CAN IF2 Data B1

CAN IF2 Data B2

CAN Transmission Request 1

CAN Transmission Request 2

CAN New Data 1

CAN New Data 2

CAN Message 1 Interrupt Pending

CAN Message 2 Interrupt Pending

124

Detailed Description

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ZHCSH09 –OCTOBER 2017

表 6-7. CAN Registers (continued)

OFFSET

0x160

ACRONYM

REGISTER NAME

CANMSG1VAL

CANMSG2VAL

CAN Message 1 Valid

CAN Message 2 Valid

0x164

表 6-8. Comparator Registers

OFFSET

0x0

ACRONYM

ACMIS

REGISTER NAME

Analog Comparator Masked Interrupt Status

0x4

ACRIS

Analog Comparator Raw Interrupt Status

Analog Comparator Interrupt Enable

Analog Comparator Reference Voltage Control

Analog Comparator Status 0

0x8

ACINTEN

ACREFCTL

ACSTAT0

ACCTL0

ACSTAT1

ACCTL1

ACSTAT2

ACCTL2

ACMPPP

0x10

0x20

0x24

0x40

0x44

0x60

0x64

0xFC0

Analog Comparator Control 0

Analog Comparator Status 1

Analog Comparator Control 1

Analog Comparator Status 2

Analog Comparator Control 2

Analog Comparator Peripheral Properties

表 6-9. CRC Registers

OFFSET

400h

ACRONYM

CRCCTRL

CRCSEED

CRCDIN

REGISTER NAME

CRC Control

410h

CRC SEED/Context

CRC Data Input

414h

418h

CRCRSLTPP

CRC Post Processing Result

表 6-10. DES Registers

OFFSET

0x00

0x04

0x08

0x0C

0x10

0x14

0x18

0x1C

0x20

0x24

0x28

0x2C

0x30

0x34

0x38

0x3C

0x40

0x44

ACRONYM

REGISTER NAME

DES_KEY3_L

DES_KEY3_H

DES_KEY2_L

DES_KEY2_H

DES_KEY1_L

DES_KEY1_H

DES_IV_L

DES Key 3 LSW for 192-Bit Key

DES Key 3 MSW for 192-Bit Key

DES Key 2 LSW for 128-Bit Key

DES Key 2 MSW for 128-Bit Key

DES Key 1 LSW for 64-Bit Key

DES Key 1 MSW for 64-Bit Key

DES Initialization Vector

DES Control

DES_IV_H

DES_CTRL

DES_LENGTH

DES_DATA_L

DES_DATA_H

DES_REVISION

DES_SYSCONFIG

DES_SYSSTATUS

DES_IRQSTATUS

DES_IRQENABLE

DES_DIRTYBITS

DES Cryptographic Data Length

DES LSW Data RW

DES MSW Data RW

DES Revision Number

DES System Configuration

DES System Status

DES Interrupt Status

DES Interrupt Enable

DES Dirty Bits

Detailed Description

125

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ZHCSH09 –OCTOBER 2017

www.ti.com.cn

表 6-11. DES µDMA Registers

OFFSET

0x30

ACRONYM

REGISTER NAME

DES_DMAIM

DES_DMARIS

DES_DMAMIS

DES_DMAIC

DES DMA Interrupt Mask

DES DMA Raw Interrupt Status

DES DMA Masked Interrupt Status

DES DMA Interrupt Clear

0x34

0x38

0x3C

表 6-12. EEPROM Registers

OFFSET

0x0

ACRONYM

EESIZE

REGISTER NAME

EEPROM Size Information

EEPROM Current Block

EEPROM Current Offset

EEPROM Read-Write

0x4

EEBLOCK

EEOFFSET

EERDWR

0x8

0x10

0x14

EERDWRINC

EEDONE

EEPROM Read-Write with Increment

EEPROM Done Status

0x18

0x1C

0x20

EESUPP

EEPROM Support Control and Status

EEPROM Unlock

EEUNLOCK

EEPROT

0x30

EEPROM Protection

0x34 to 0x3C

0x40

EEPASS0 to EEPASS2

EEINT

EEPROM Password 0 to EEPROM Password 2

EEPROM Interrupt

0x50

EEHIDE0

EEPROM Block Hide 0

0x54

EEHIDE1

EEPROM Block Hide 1

0x58

EEHIDE2

EEPROM Block Hide 2

0x80

EEDBGME

EEPROMPP

EEPROM Debug Mass Erase

EEPROM Peripheral Properties

0xFC0

表 6-13. EPI Registers

OFFSET

0x000

0x004

0x008

0x010

0x014

0x01C

0x020

0x024

0x028

0x030

0x034

0x038

0x060

0x06C

0x70 to 0x8C

0x200

0x24

ACRONYM

EPICFG

REGISTER NAME

EPI Configuration

EPIBAUD

EPI Main Baud Rate

EPIBAUD2

EPI Main Baud Rate

EPISDRAMCFG

EPIHB8CFG

EPIHB16CFG

EPIGPCFG

EPIHB8CFG2

EPIHB16CFG2

EPIADDRMAP

EPIRSIZE0

EPIRADDR0

EPIRPSTD0

EPIRSIZE1

EPIRADDR1

EPIRPSTD1

EPISTAT

EPI SDRAM Configuration

EPI Host-Bus 8 Configuration

EPI Host-Bus 16 Configuration

EPI General-Purpose Configuration

EPI Host-Bus 8 Configuration 2

EPI Host-Bus 16 Configuration 2

EPI Address Map

EPI Read Size 0

EPI Read Address 0

EPI Non-Blocking Read Data 0

EPI Read Size 1

EPI Read Address 1

EPI Non-Blocking Read Data 1

EPI Status

EPIRFIFOCNT

EPI Read FIFO Count

EPIREADFIFO0 to EPIREADFIFO7

EPIFIFOLVL

EPI Read FIFO 0 to EPI Read FIFO 7

EPI FIFO Level Selects

EPIWFIFOCNT

EPI Write FIFO Count

126

Detailed Description

MSP432E401Y

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ZHCSH09 –OCTOBER 2017

表 6-13. EPI Registers (continued)

OFFSET

0x28

ACRONYM

REGISTER NAME

EPIDMATXCNT

EPIIM

EPI DMA Transmit Count

EPI Interrupt Mask

0x210

0x214

0x218

0x21C

0x308

0x30C

0x310

0x314

0x318

0x31C

0x360

EPIRIS

EPI Raw Interrupt Status

EPI Masked Interrupt Status

EPIMIS

EPIEISC

EPI Error and Interrupt Status and Clear

EPIHB8CFG3

EPIHB16CFG3

EPIHB8CFG4

EPIHB16CFG4

EPIHB8TIME

EPIHB16TIME

EPIHB8TIME2

EPIHB16TIME2

EPIHB8TIME3

EPIHB16TIME3

EPIHB8TIME4

EPIHB16TIME4

EPIHBPSRAM

EPI Host-Bus 8 Configuration 3

EPI Host-Bus 16 Configuration 3

EPI Host-Bus 8 Configuration 4

EPI Host-Bus 16 Configuration 4

EPI Host-Bus 8 Timing Extension

EPI Host-Bus 16 Timing Extension

EPI Host-Bus 8 Timing Extension

EPI Host-Bus 16 Timing Extension

EPI Host-Bus 8 Timing Extension

EPI Host-Bus 16 Timing Extension

EPI Host-Bus 8 Timing Extension

EPI Host-Bus 16 Timing Extension

EPI Host-Bus PSRAM

表 6-14. Ethernet MAC (EMAC) Registers

OFFSET

0x0

ACRONYM

REGISTER NAME

EMACCFG

Ethernet MAC Configuration

Ethernet MAC Frame Filter

Ethernet MAC Hash Table High

Ethernet MAC Hash Table Low

Ethernet MAC MII Address

Ethernet MAC MII Data Register

Ethernet MAC Flow Control

Ethernet MAC VLAN Tag

0x4

EMACFRAMEFLTR

EMACHASHTBLH

EMACHASHTBLL

EMACMIIADDR

EMACMIIDATA

EMACFLOWCTL

EMACVLANTG

EMACSTATUS

EMACRWUFF

0x8

0xC

0x10

0x14

0x18

0x1C

0x24

0x28

0x2C

0x30

0x34

0x38

0x3C

0x40

0x44

0x48

0x4C

0x50

0x54

0x58

0x5C

0xDC

0x100

0x104

Ethernet MAC Status

Ethernet MAC Remote Wake-Up Frame Filter

EMACPMTCTLSTAT

EMACLPICTLSTAT

EMACLPITIMERCTRL

EMACRIS

Ethernet MAC PMT Control and Status

LPI Control and Status

LPI Timers Control

Ethernet MAC Raw Interrupt Status

Ethernet MAC Interrupt Mask

Ethernet MAC Address 0 High

Ethernet MAC Address 0 Low Register

Ethernet MAC Address 1 High

Ethernet MAC Address 1 Low

Ethernet MAC Address 2 High

Ethernet MAC Address 2 Low

Ethernet MAC Address 3 High

Ethernet MAC Address 3 Low

Ethernet MAC Watchdog Time-out

Ethernet MAC MMC Control

EMACIM

EMACADDR0H

EMACADDR0L

EMACADDR1H

EMACADDR1L

EMACADDR2H

EMACADDR2L

EMACADDR3H

EMACADDR3L

EMACWDOGTO

EMACMMCCTRL

EMACMMCRXRIS

Ethernet MAC MMC Receive Raw Interrupt Status

Detailed Description

127

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ZHCSH09 –OCTOBER 2017

www.ti.com.cn

表 6-14. Ethernet MAC (EMAC) Registers (continued)

OFFSET

0x108

ACRONYM

EMACMMCTXRIS

REGISTER NAME

Ethernet MAC MMC Transmit Raw Interrupt Status

Ethernet MAC MMC Receive Interrupt Mask

Ethernet MAC MMC Transmit Interrupt Mask

0x10C

0x110

EMACMMCRXIM

EMACMMCTXIM

EMACTXCNTGB

0x118

Ethernet MAC Transmit Frame Count for Good and Bad Frames

Ethernet MAC Transmit Frame Count for Frames Transmitted After Single

Collision

0x14C

0x150

EMACTXCNTSCOL

EMACTXCNTMCOL

Ethernet MAC Transmit Frame Count for Frames Transmitted After Multiple

Collisions

0x164

0x180

0x194

0x198

0x1C4

0x584

0x588

0x700

0x704

0x708

0x70C

0x710

0x714

0x718

0x71C

0x720

0x724

0x728

0x72C

0x760

0x764

0xC00

0xC04

0xC08

0xC0C

0xC10

0xC14

0xC18

0xC1C

0xC20

0xC24

0xC48

0xC4C

0xC50

0xC54

0xFC0

0xFC4

0xFC8

0xFD0

0xFD4

EMACTXOCTCNTG

EMACRXCNTGB

EMACRXCNTCRCERR

EMACRXCNTALGNERR

EMACRXCNTGUNI

EMACVLNINCREP

EMACVLANHASH

EMACTIMSTCTRL

EMACSUBSECINC

EMACTIMSEC

Ethernet MAC Transmit Octet Count Good

Ethernet MAC Receive Frame Count for Good and Bad Frames

Ethernet MAC Receive Frame Count for CRC Error Frames

Ethernet MAC Receive Frame Count for Alignment Error Frames

Ethernet MAC Receive Frame Count for Good Unicast Frames

Ethernet MAC VLAN Tag Inclusion or Replacement

Ethernet MAC VLAN Hash Table

Ethernet MAC Timestamp Control

Ethernet MAC Sub-Second Increment

Ethernet MAC System Time - Seconds

EMACTIMNANO

EMACTIMSECU

EMACTIMNANOU

EMACTIMADD

Ethernet MAC System Time - Nanoseconds

Ethernet MAC System Time - Seconds Update

Ethernet MAC System Time - Nanoseconds Update

Ethernet MAC Timestamp Addend

EMACTARGSEC

EMACTARGNANO

EMACHWORDSEC

EMACTIMSTAT

EMACPPSCTRL

EMACPPS0INTVL

EMACPPS0WIDTH

EMACDMABUSMOD

EMACTXPOLLD

EMACRXPOLLD

EMACRXDLADDR

EMACTXDLADDR

EMACDMARIS

Ethernet MAC Target Time Seconds

Ethernet MAC Target Time Nanoseconds

Ethernet MAC System Time-Higher Word Seconds

Ethernet MAC Timestamp Status

Ethernet MAC PPS Control

Ethernet MAC PPS0 Interval

Ethernet MAC PPS0 Width

Ethernet MAC DMA Bus Mode

Ethernet MAC Transmit Poll Demand

Ethernet MAC Receive Poll Demand

Ethernet MAC Receive Descriptor List Address

Ethernet MAC Transmit Descriptor List Address

Ethernet MAC DMA Interrupt Status

EMACDMAOPMODE

EMACDMAIM

Ethernet MAC DMA Operation Mode

Ethernet MAC DMA Interrupt Mask Register

Ethernet MAC Missed Frame and Buffer Overflow Counter

Ethernet MAC Receive Interrupt Watchdog Timer

Ethernet MAC Current Host Transmit Descriptor

Ethernet MAC Current Host Receive Descriptor

Ethernet MAC Current Host Transmit Buffer Address

Ethernet MAC Current Host Receive Buffer Address

Ethernet MAC Peripheral Property Register

Ethernet MAC Peripheral Configuration

Ethernet MAC Clock Configuration

EMACMFBOC

EMACRXINTWDT

EMACHOSTXDESC

EMACHOSRXDESC

EMACHOSTXBA

EMACHOSRXBA

EMACPP

EMACPC

EMACCC

EPHYRIS

Ethernet PHY Raw Interrupt Status

EPHYIM

Ethernet PHY Interrupt Mask

128

Detailed Description

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

表 6-14. Ethernet MAC (EMAC) Registers (continued)

OFFSET

ACRONYM

EPHYMISC

REGISTER NAME

0xFD8

Ethernet PHY Masked Interrupt Status and Clear

表 6-15. Ethernet MII Management (EPHY) Registers (Accessed Through the EMACMIIADDR Register)

ADDRESS

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0D

0x0E

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x18

0x19

0x1A

0x1B

0x1C

0x1E

0x1F

0x25

ACRONYM

REGISTER NAME

EPHYBMCR

EPHYBMSR

EPHYID1

Ethernet PHY Basic Mode Control - MR0

Ethernet PHY Basic Mode Status - MR1

Ethernet PHY Identifier Register 1 - MR2

Ethernet PHY Identifier Register 2 - MR3

Ethernet PHY Auto-Negotiation Advertisement - MR4

Ethernet PHY Auto-Negotiation Link Partner Ability -MR5

Ethernet PHY Auto-Negotiation Expansion - MR6

Ethernet PHY Auto-Negotiation Next Page TX - MR7

Ethernet PHY Auto-Negotiation Link Partner Ability Next Page - MR8

Ethernet PHY Configuration 1 - MR9

EPHYID2

EPHYANA

EPHYANLPA

EPHYANER

EPHYANNPTR

EPHYANLNPTR

EPHYCFG1

EPHYCFG2

EPHYCFG3

EPHYREGCTL

EPHYADDAR

EPHYSTS

Ethernet PHY Configuration 2 - MR10

Ethernet PHY Configuration 3 - MR11

Ethernet PHY Register Control - MR13

Ethernet PHY Address or Data - MR14

Ethernet PHY Status - MR16

EPHYSCR

Ethernet PHY Specific Control - MR17

EPHYMISR1

EPHYMISR2

EPHYFCSCR

EPHYRXERCNT

EPHYBISTCR

EPHYLEDCR

EPHYCTL

Ethernet PHY MII Interrupt Status 1 - MR18

Ethernet PHY MII Interrupt Status 2 - MR19

Ethernet PHY False Carrier Sense Counter - MR20

Ethernet PHY Receive Error Count - MR21

Ethernet PHY BIST Control - MR22

Ethernet PHY LED Control - MR24

Ethernet PHY Control - MR25

EPHY10BTSC

EPHYBICSR1

EPHYBICSR2

EPHYCDCR

EPHYRCR

Ethernet PHY 10Base-T Status/Control - MR26

Ethernet PHY BIST Control and Status 1 - MR27

Ethernet PHY BIST Control and Status 2 - MR28

Ethernet PHY Cable Diagnostic Control - MR30

Ethernet PHY Reset Control - MR31

EPHYLEDCFG

Ethernet PHY LED Configuration - MR37

表 6-16. Flash Registers

OFFSET

0x0

ACRONYM

FMA

REGISTER NAME

Flash Memory Address

0x4

FMD

Flash Memory Data

0x8

FMC

Flash Memory Control

0xC

FCRIS

Flash Controller Raw Interrupt Status

Flash Controller Interrupt Mask

Flash Controller Masked Interrupt Status and Clear

Flash Memory Control 2

0x10

FCIM

0x14

FCMISC

FMC2

0x20

0x30

FWBVAL

FLPEKEY

FWB0 to FWB31

FLASHPP

Flash Write Buffer Valid

0x3C

Flash Program/Erase Key

0x100 to 0x17C

0xFC0

Flash Write Buffer 0 to Flash Write Buffer 32

Flash Peripheral Properties

Detailed Description

129

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ZHCSH09 –OCTOBER 2017

www.ti.com.cn

表 6-16. Flash Registers (continued)

OFFSET

0xFC4

0xFC8

0xFCC

0xFD0

0xFD4

ACRONYM

REGISTER NAME

SSIZE

SRAM Size

FLASHCONF

ROMSWMAP

FLASHDMASZ

FLASHDMAST

Flash Configuration Register

ROM Third-Party Software

Flash DMA Address Size

Flash DMA Starting Address

表 6-17. GPIO Registers

OFFSET

0x0

ACRONYM

GPIODATA

GPIODIR

REGISTER NAME

GPIO Data

0x400

0x404

0x408

0x40C

0x410

0x414

0x418

0x41C

0x420

0x500

0x504

0x508

0x50C

0x510

0x514

0x518

0x51C

0x520

0x524

0x528

0x52C

0x530

0x534

0x538

0x53C

0x540

0x544

0x548

0xFC0

0xFC4

0xFD0

0xFD4

0xFD8

0xFDC

0xFE0

0xFE4

0xFE8

0xFEC

GPIO Direction

GPIOIS

GPIO Interrupt Sense

GPIOIBE

GPIO Interrupt Both Edges

GPIO Interrupt Event

GPIOIEV

GPIOIM

GPIO Interrupt Mask

GPIORIS

GPIO Raw Interrupt Status

GPIO Masked Interrupt Status

GPIO Interrupt Clear

GPIOMIS

GPIOICR

GPIOAFSEL

GPIODR2R

GPIODR4R

GPIODR8R

GPIOODR

GPIO Alternate Function Select

GPIO 2-mA Drive Select

GPIO 4-mA Drive Select

GPIO 8-mA Drive Select

GPIO Open Drain Select

GPIO Pullup Select

GPIOPUR

GPIOPDR

GPIO Pulldown Select

GPIO Slew Rate Control Select

GPIO Digital Enable

GPIOSLR

GPIODEN

GPIOLOCK

GPIOCR

GPIO Lock

GPIO Commit

GPIOAMSEL

GPIOPCTL

GPIOADCCTL

GPIODMACTL

GPIOSI

GPIO Analog Mode Select

GPIO Port Control

GPIO ADC Control

GPIO DMA Control

GPIO Select Interrupt

GPIODR12R

GPIOWAKEPEN

GPIOWAKELVL

GPIOWAKESTAT

GPIOPP

GPIO 12-mA Drive Select

GPIO Wake Pin Enable

GPIO Wake Level

GPIO Wake Status

GPIO Peripheral Property

GPIO Peripheral Configuration

GPIO Peripheral Identification 4

GPIO Peripheral Identification 5

GPIO Peripheral Identification 6

GPIO Peripheral Identification 7

GPIO Peripheral Identification 0

GPIO Peripheral Identification 1

GPIO Peripheral Identification 2

GPIO Peripheral Identification 3

GPIOPC

GPIOPeriphID4

GPIOPeriphID5

GPIOPeriphID6

GPIOPeriphID7

GPIOPeriphID0

GPIOPeriphID1

GPIOPeriphID2

GPIOPeriphID3

130

Detailed Description

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

表 6-17. GPIO Registers (continued)

OFFSET

0xFF0

0xFF4

0xFF8

0xFFC

ACRONYM

REGISTER NAME

GPIOPCellID0

GPIOPCellID1

GPIOPCellID2

GPIOPCellID3

GPIO PrimeCell Identification 0

GPIO PrimeCell Identification 1

GPIO PrimeCell Identification 2

GPIO PrimeCell Identification 3

表 6-18. GPTM Registers

OFFSET

0x0

ACRONYM

GPTMCFG

REGISTER NAME

GPTM Configuration

0x4

GPTMTAMR

GPTMTBMR

GPTMCTL

GPTM Timer A Mode

0x8

GPTM Timer B Mode

0xC

GPTM Control

0x10

0x18

0x1C

0x20

0x24

0x28

0x2C

0x30

0x34

0x38

0x3C

0x40

0x44

0x48

0x4C

0x50

0x54

0x58

0x5C

0x60

0x6C

0x70

0xFC0

0xFC8

GPTMSYNC

GPTMIMR

GPTM Synchronize

GPTM Interrupt Mask

GPTM Raw Interrupt Status

GPTM Masked Interrupt Status

GPTM Interrupt Clear

GPTM Timer A Interval Load

GPTM Timer B Interval Load

GPTM Timer A Match

GPTM Timer B Match

GPTM Timer A Prescale

GPTM Timer B Prescale

GPTM TimerA Prescale Match

GPTM TimerB Prescale Match

GPTM Timer A

GPTMRIS

GPTMMIS

GPTMICR

GPTMTAILR

GPTMTBILR

GPTMTAMATCHR

GPTMTBMATCHR

GPTMTAPR

GPTMTBPR

GPTMTAPMR

GPTMTBPMR

GPTMTAR

GPTMTBR

GPTM Timer B

GPTMTAV

GPTM Timer A Value

GPTMTBV

GPTM Timer B Value

GPTMRTCPD

GPTMTAPS

GPTMTBPS

GPTMDMAEV

GPTMADCEV

GPTMPP

GPTM RTC Predivide

GPTM Timer A Prescale Snapshot

GPTM Timer B Prescale Snapshot

GPTM DMA Event

GPTM ADC Event

GPTM Peripheral Properties

GPTM Clock Configuration

GPTMCC

表 6-19. HIB Registers

OFFSET

0x0

ACRONYM

HIBRTCC

HIBRTCM0

HIBRTCLD

HIBCTL

REGISTER NAME

Hibernation RTC Counter

Hibernation RTC Match 0

Hibernation RTC Load

0x4

0xC

0x10

0x14

0x18

0x1C

0x20

0x24

Hibernation Control

HIBIM

Hibernation Interrupt Mask

Hibernation Raw Interrupt Status

Hibernation Masked Interrupt Status

Hibernation Interrupt Clear

Hibernation RTC Trim

HIBRIS

HIBMIS

HIBIC

HIBRTCT

Detailed Description

131

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ZHCSH09 –OCTOBER 2017

www.ti.com.cn

表 6-19. HIB Registers (continued)

OFFSET

0x28

ACRONYM

REGISTER NAME

HIBRTCSS

HIBIO

Hibernation RTC Sub Seconds

Hibernation IO Configuration

Hibernation Data

0x2C

0x30 to 0x6F

0x300

0x310

0x314

0x320

0x324

0x330

0x334

0x360

0x400

0x404

0x410

0x4E0

0x4E4

0x4E8

0x4EC

0x4F0

0x4F4

0x4F8

0x4FC

0xFC0

0xFC8

HIBDATA

HIBCALCTL

HIBCAL0

Hibernation Calendar Control

Hibernation Calendar 0

Hibernation Calendar 1

Hibernation Calendar Load 0

Hibernation Calendar Load 1

Hibernation Calendar Match 0

Hibernation Calendar Match 1

Hibernation Lock

HIBCAL1

HIBCALLD0

HIBCALLD1

HIBCALM0

HIBCALM1

HIBLOCK

HIBTPCTL

HIBTPSTAT

HIBTPIO

HIB Tamper Control

HIB Tamper Status

HIB Tamper I/O Control

HIB Tamper Log 0

HIBTPLOG0

HIBTPLOG1

HIBTPLOG2

HIBTPLOG3

HIBTPLOG4

HIBTPLOG5

HIBTPLOG6

HIBTPLOG7

HIBPP

HIB Tamper Log 1

HIB Tamper Log 2

HIB Tamper Log 3

HIB Tamper Log 4

HIB Tamper Log 5

HIB Tamper Log 6

HIB Tamper Log 7

Hibernation Peripheral Properties

Hibernation Clock Control

HIBCC

表 6-20. I2C Registers

OFFSET

0x0

ACRONYM

I2CMSA

REGISTER NAME

I2C Master Slave Address

I2C Master Control/Status

I2C Master Data

0x4

I2CMCS

0x8

I2CMDR

0xC

I2CMTPR

I2CMIMR

I2CMRIS

I2CMMIS

I2CMICR

I2CMCR

I2C Master Timer Period

I2C Master Interrupt Mask

I2C Master Raw Interrupt Status

I2C Master Masked Interrupt Status

I2C Master Interrupt Clear

I2C Master Configuration

I2C Master Clock Low Time-out Count

I2C Master Bus Monitor

I2C Master Burst Length

I2C Master Burst Count

0x10

0x14

0x18

0x1C

0x20

0x24

0x2C

0x30

0x34

0x800

0x804

0x808

0x80C

0x810

0x814

0x818

I2CMCLKOCNT

I2CMBMON

I2CMBLEN

I2CMBCNT

I2CSOAR

I2CSCSR

I2CSDR

I2C Slave Own Address

I2C Slave Control/Status

I2C Slave Data

I2CSIMR

I2CSRIS

I2C Slave Interrupt Mask

I2C Slave Raw Interrupt Status

I2C Slave Masked Interrupt Status

I2C Slave Interrupt Clear

I2CSMIS

I2CSICR

132

Detailed Description

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

表 6-20. I2C Registers (continued)

OFFSET

0x81C

0x820

0xF00

0xF04

0xF08

0xFC0

0xFC4

ACRONYM

I2CSOAR2

I2CSACKCTL

I2CFIFODATA

I2CFIFOCTL

I2CFIFOSTATUS

I2CPP

REGISTER NAME

I2C Slave Own Address 2

I2C Slave ACK Control

I2C FIFO Data

I2C FIFO Control

I2C FIFO Status

I2C Peripheral Properties

I2C Peripheral Configuration

I2CPC

表 6-21. µDMA Registers

OFFSET

0x0

ACRONYM

REGISTER NAME

DMASTAT

DMA Status

0x4

DMACFG

DMA Configuration

0x8

DMACTLBASE

DMAALTBASE

DMAWAITSTAT

DMASWREQ

DMA Channel Control Base Pointer

DMA Alternate Channel Control Base Pointer

DMA Channel Wait-on-Request Status

DMA Channel Software Request

DMA Channel Useburst Set

DMA Channel Useburst Clear

DMA Channel Request Mask Set

DMA Channel Request Mask Clear

DMA Channel Enable Set

0xC

0x10

0x14

0x18

DMAUSEBURSTSET

DMAUSEBURSTCLR

DMAREQMASKSET

DMAREQMASKCLR

DMAENASET

DMAENACLR

DMAALTSET

0x1C

0x20

0x24

0x28

0x2C

0x30

DMA Channel Enable Clear

DMA Channel Primary Alternate Set

DMA Channel Primary Alternate Clear

DMA Channel Priority Set

0x34

DMAALTCLR

DMAPRIOSET

DMAPRIOCLR

DMAERRCLR

DMACHMAP0

DMACHMAP1

DMACHMAP2

DMACHMAP3

DMAPeriphID4

DMAPeriphID0

DMAPeriphID1

DMAPeriphID2

DMAPeriphID3

DMAPCellID0

DMAPCellID1

DMAPCellID2

DMAPCellID3

0x38

0x3C

0x4C

0x510

0x514

0x518

0x51C

0xFD0

0xFE0

0xFE4

0xFE8

0xFEC

0xFF0

0xFF4

0xFF8

0xFFC

DMA Channel Priority Clear

DMA Bus Error Clear

DMA Channel Map Select 0

DMA Channel Map Select 1

DMA Channel Map Select 2

DMA Channel Map Select 3

DMA Peripheral Identification 4

DMA Peripheral Identification 0

DMA Peripheral Identification 1

DMA Peripheral Identification 2

DMA Peripheral Identification 3

DMA PrimeCell Identification 0

DMA PrimeCell Identification 1

DMA PrimeCell Identification 2

DMA PrimeCell Identification 3

表 6-22. µDMA Channel Control Structure Registers

OFFSET

0x0

ACRONYM

REGISTER NAME

DMASRCENDP

DMADSTENDP

DMACHCTL

DMA Channel Source Address End Pointer

DMA Channel Destination Address End Pointer

DMA Channel Control Word

0x4

0x8

Detailed Description

133

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

表 6-23. PWM Registers

OFFSET

0x0

ACRONYM

REGISTER NAME

PWMCTL

PWM Master Control

0x4

PWMSYNC

PWM Time Base Sync

0x8

PWMENABLE

PWMINVERT

PWMFAULT

PWMINTEN

PWMRIS

PWM Output Enable

0xC

PWM Output Inversion

PWM Output Fault

0x10

0x14

PWM Interrupt Enable

0x18

PWM Raw Interrupt Status

PWM Interrupt Status and Clear

PWM Status

0x1C

0x20

PWMISC

PWMSTATUS

PWMFAULTVAL

PWMENUPD

PWM0CTL

0x24

PWM Fault Condition Value

PWM Enable Update

0x28

0x40

PWM0 Control

0x44

PWM0INTEN

PWM0RIS

PWM0 Interrupt and Trigger Enable

PWM0 Raw Interrupt Status

PWM0 Interrupt Status and Clear

PWM0 Load

0x48

0x4C

0x50

PWM0ISC

PWM0LOAD

PWM0COUNT

PWM0CMPA

PWM0CMPB

PWM0GENA

PWM0GENB

PWM0DBCTL

PWM0DBRISE

PWM0DBFALL

PWM0FLTSRC0

PWM0FLTSRC1

PWM0MINFLTPER

PWM1CTL

0x54

PWM0 Counter

0x58

PWM0 Compare A

0x5C

0x60

PWM0 Compare B

PWM0 Generator A Control

PWM0 Generator B Control

PWM0 Dead-Band Control

PWM0 Dead-Band Rising-Edge Delay

PWM0 Dead-Band Falling-Edge-Delay

PWM0 Fault Source 0

0x64

0x68

0x6C

0x70

0x74

0x78

PWM0 Fault Source 1

0x7C

0x080

0x084

0x088

0x08C

0x090

0x094

0x098

0x09C

0x0A0

0x0A4

0x0A8

0x0AC

0x0B0

0x0B4

0x0B8

0x0BC

0x0C0

0x0C4

0x0C8

0x0CC

PWM0 Minimum Fault Period

PWM1 Control

PWM1INTEN

PWM1RIS

PWM1 Interrupt and Trigger Enable

PWM1 Raw Interrupt Status

PWM1 Interrupt Status and Clear

PWM1 Load

PWM1ISC

PWM1LOAD

PWM1COUNT

PWM1CMPA

PWM1CMPB

PWM1GENA

PWM1GENB

PWM1DBCTL

PWM1DBRISE

PWM1DBFALL

PWM1FLTSRC0

PWM1FLTSRC1

PWM1MINFLTPER

PWM2CTL

PWM1 Counter

PWM1 Compare A

PWM1 Compare B

PWM1 Generator A Control

PWM1 Generator B Control

PWM1 Dead-Band Control

PWM1 Dead-Band Rising-Edge Delay

PWM1 Dead-Band Falling-Edge-Delay

PWM1 Fault Source 0

PWM1 Fault Source 1

PWM1 Minimum Fault Period

PWM2 Control

PWM2INTEN

PWM2RIS

PWM2 Interrupt and Trigger Enable

PWM2 Raw Interrupt Status

PWM2 Interrupt Status and Clear

PWM2ISC

134

Detailed Description

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

表 6-23. PWM Registers (continued)

OFFSET

0x0D0

0x0D4

0x0D8

0x0DC

0x0E0

0x0E4

0x0E8

0x0EC

0x0F0

0x0F4

0x0F8

0x0FC

0x100

0x104

0x108

0x10C

0x110

0x114

0x118

0x11C

0x120

0x124

0x128

0x12C

0x130

0x134

0x138

0x13C

0x800

0x804

0x808

0x880

0x884

0x888

0x900

0x904

0x908

0x980

0x984

0x988

0xFC0

0xFC8

ACRONYM

REGISTER NAME

PWM2LOAD

PWM2 Load

PWM2COUNT

PWM2CMPA

PWM2 Counter

PWM2 Compare A

PWM2CMPB

PWM2 Compare B

PWM2GENA

PWM2 Generator A Control

PWM2 Generator B Control

PWM2 Dead-Band Control

PWM2 Dead-Band Rising-Edge Delay

PWM2 Dead-Band Falling-Edge-Delay

PWM2 Fault Source 0

PWM2GENB

PWM2DBCTL

PWM2DBRISE

PWM2DBFALL

PWM2FLTSRC0

PWM2FLTSRC1

PWM2MINFLTPER

PWM3CTL

PWM2 Fault Source 1

PWM2 Minimum Fault Period

PWM3 Control

PWM3INTEN

PWM3RIS

PWM3 Interrupt and Trigger Enable

PWM3 Raw Interrupt Status

PWM3 Interrupt Status and Clear

PWM3 Load

PWM3ISC

PWM3LOAD

PWM3COUNT

PWM3CMPA

PWM3 Counter

PWM3 Compare A

PWM3CMPB

PWM3 Compare B

PWM3GENA

PWM3 Generator A Control

PWM3 Generator B Control

PWM3 Dead-Band Control

PWM3 Dead-Band Rising-Edge Delay

PWM3 Dead-Band Falling-Edge-Delay

PWM3 Fault Source 0

PWM3GENB

PWM3DBCTL

PWM3DBRISE

PWM3DBFALL

PWM3FLTSRC0

PWM3FLTSRC1

PWM3MINFLTPER

PWM0FLTSEN

PWM0FLTSTAT0

PWM0FLTSTAT1

PWM1FLTSEN

PWM1FLTSTAT0

PWM1FLTSTAT1

PWM2FLTSEN

PWM2FLTSTAT0

PWM2FLTSTAT1

PWM3FLTSEN

PWM3FLTSTAT0

PWM3FLTSTAT1

PWMPP

PWM3 Fault Source 1

PWM3 Minimum Fault Period

PWM0 Fault Pin Logic Sense

PWM0 Fault Status 0

PWM0 Fault Status 1

PWM1 Fault Pin Logic Sense

PWM1 Fault Status 0

PWM1 Fault Status 1

PWM2 Fault Pin Logic Sense

PWM2 Fault Status 0

PWM2 Fault Status 1

PWM3 Fault Pin Logic Sense

PWM3 Fault Status 0

PWM3 Fault Status 1

PWM Peripheral Properties

PWM Clock Configuration

PWMCC

表 6-24. QEI Registers

OFFSET

0x0

ACRONYM

QEICTL

REGISTER NAME

QEI Control

0x4

QEISTAT

QEI Status

Detailed Description

135

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

表 6-24. QEI Registers (continued)

OFFSET

0x8

ACRONYM

REGISTER NAME

QEI Position

QEIPOS

0xC

QEIMAXPOS

QEILOAD

QEITIME

QEICOUNT

QEISPEED

QEIINTEN

QEIRIS

QEI Maximum Position

QEI Timer Load

0x10

0x14

0x18

0x1C

0x20

0x24

0x28

QEI Timer

QEI Velocity Counter

QEI Velocity

QEI Interrupt Enable

QEI Raw Interrupt Status

QEI Interrupt Status and Clear

QEIISC

表 6-25. QSSI Registers

OFFSET

0x0

ACRONYM

SSICR0

REGISTER NAME

QSSI Control 0

0x4

SSICR1

QSSI Control 1

0x8

SSIDR

QSSI Data

0xC

SSISR

QSSI Status

0x10

SSICPSR

SSIIM

QSSI Clock Prescale

0x14

QSSI Interrupt Mask

0x18

SSIRIS

QSSI Raw Interrupt Status

QSSI Masked Interrupt Status

QSSI Interrupt Clear

0x1C

SSIMIS

0x20

SSIICR

0x24

SSIDMACTL

SSIPP

QSSI DMA Control

0xFC0

0xFC8

0xFD0

0xFD4

0xFD8

0xFDC

0xFE0

0xFE4

0xFE8

0xFEC

0xFF0

0xFF4

0xFF8

0xFFC

QSSI Peripheral Properties

QSSI Clock Configuration

QSSI Peripheral Identification 4

QSSI Peripheral Identification 5

QSSI Peripheral Identification 6

QSSI Peripheral Identification 7

QSSI Peripheral Identification 0

QSSI Peripheral Identification 1

QSSI Peripheral Identification 2

QSSI Peripheral Identification 3

QSSI PrimeCell Identification 0

QSSI PrimeCell Identification 1

QSSI PrimeCell Identification 2

QSSI PrimeCell Identification 3

SSICC

SSIPeriphID4

SSIPeriphID5

SSIPeriphID6

SSIPeriphID7

SSIPeriphID0

SSIPeriphID1

SSIPeriphID2

SSIPeriphID3

SSIPCellID0

SSIPCellID1

SSIPCellID2

SSIPCellID3

表 6-26. SHA/MD5 Registers

OFFSET

0x000

0x004

0x008

0x00C

0x010

0x014

0x018

0x01C

ACRONYM

REGISTER NAME

SHA Outer Digest A

SHA Outer Digest B

SHA Outer Digest C

SHA Outer Digest D

SHA Outer Digest E

SHA Outer Digest F

SHA Outer Digest G

SHA Outer Digest H

SHA_ODIGEST_A

SHA_ODIGEST_B

SHA_ODIGEST_C

SHA_ODIGEST_D

SHA_ODIGEST_E

SHA_ODIGEST_F

SHA_ODIGEST_G

SHA_ODIGEST_H

136

Detailed Description

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

表 6-26. SHA/MD5 Registers (continued)

OFFSET

0x020

0x024

0x028

0x02C

0x030

0x034

0x038

0x03C

0x40

ACRONYM

REGISTER NAME

SHA Inner Digest A

SHA Inner Digest B

SHA Inner Digest C

SHA Inner Digest D

SHA Inner Digest E

SHA Inner Digest F

SHA Inner Digest G

SHA Inner Digest H

SHA_IDIGEST_A

SHA_IDIGEST_B

SHA_IDIGEST_C

SHA_IDIGEST_D

SHA_IDIGEST_E

SHA_IDIGEST_F

SHA_IDIGEST_G

SHA_IDIGEST_H

SHA_DIGEST_COUNT

SHA_MODE

SHA Digest Count

SHA Mode

0x44

0x48

SHA_LENGTH

SHA Length

0x080

0x084

0x088

0x08C

0x090

0x094

0x098

0x09C

0x0A0

0x0A4

0x0A8

0x0AC

0x0B0

0x0B4

0x0B8

0x0BC

0x100

0x110

0x114

0x118

0x11C

SHA_DATA_0_IN

SHA_DATA_1_IN

SHA_DATA_2_IN

SHA_DATA_3_IN

SHA_DATA_4_IN

SHA_DATA_5_IN

SHA_DATA_6_IN

SHA_DATA_7_IN

SHA_DATA_8_IN

SHA_DATA_9_IN

SHA_DATA_10_IN

SHA_DATA_11_IN

SHA_DATA_12_IN

SHA_DATA_13_IN

SHA_DATA_14_IN

SHA_DATA_15_IN

SHA_REVISION

SHA_SYSCONFIG

SHA_SYSSTATUS

SHA_IRQSTATUS

SHA_IRQENABLE

SHA Data 0 Input

SHA Data 1 Input

SHA Data 2 Input

SHA Data 3 Input

SHA Data 4 Input

SHA Data 5 Input

SHA Data 6 Input

SHA Data 7 Input

SHA Data 8 Input

SHA Data 9 Input

SHA Data 10 Input

SHA Data 11 Input

SHA Data 12 Input

SHA Data 13 Input

SHA Data 14 Input

SHA Data 15 Input

SHA Revision

SHA System Configuration

SHA System Status

SHA Interrupt Status

SHA Interrupt Enable

表 6-27. SHA/MD5 µDMA Registers

OFFSET

0x10

ACRONYM

REGISTER NAME

SHA_DMAIM

SHA_DMARIS

SHA_DMAMIS

SHA_DMAIC

SHA DMA Interrupt Mask

SHA DMA Raw Interrupt Status

SHA DMA Masked Interrupt Status

SHA DMA Interrupt Clear

0x14

0x18

0x1C

表 6-28. System Control Memory Registers

OFFSET

0xD4

ACRONYM

RVP

REGISTER NAME

Reset Vector Pointer

Boot Configuration

0x1D0

BOOTCFG

0x1E0 to 0x1EC

USER_REG_0 to USER_REG_3

User Register 0 to User Register 3

Flash Memory Protection Read Enable 0 to Flash Memory Protection Read

Enable 15

0x200 to 0x23C

FMPRE_0 to FMPRE_15

Detailed Description

137

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

表 6-28. System Control Memory Registers (continued)

OFFSET

ACRONYM

REGISTER NAME

Flash Memory Protection Program Enable 0 to Flash Memory Protection

Program Enable 15

0x400 to 0x43C

FMPPE_0 to FMPPE_15

表 6-29. System Exception Registers

OFFSET

0x0

ACRONYM

SYSEXCRIS

SYSEXCIM

SYSEXCMIS

SYSEXCIC

REGISTER NAME

System Exception Raw Interrupt Status

System Exception Interrupt Mask

System Exception Masked Interrupt Status

System Exception Interrupt Clear

0x4

0x8

0xC

表 6-30. UART Registers

OFFSET

0x0

ACRONYM

REGISTER NAME

UARTDR

UART Data

0x4

UARTRSR/UARTECR

UARTFR

UART Receive Status/Error Clear

UART Flag

0x18

0x20

UARTILPR

UART IrDA Low-Power Register

UART Integer Baud-Rate Divisor

UART Fractional Baud-Rate Divisor

UART Line Control

0x24

UARTIBRD

0x28

UARTFBRD

0x2C

0x30

UARTLCRH

UARTCTL

UART Control

0x34

UARTIFLS

UART Interrupt FIFO Level Select

UART Interrupt Mask

0x38

UARTIM

0x3C

0x40

UARTRIS

UART Raw Interrupt Status

UART Masked Interrupt Status

UART Interrupt Clear

UARTMIS

0x44

UARTICR

0x48

UARTDMACTL

UART9BITADDR

UART9BITAMASK

UARTPP

UART DMA Control

0xA4

UART 9-Bit Self Address

0xA8

UART 9-Bit Self Address Mask

UART Peripheral Properties

UART Clock Configuration

UART Peripheral Identification 4

UART Peripheral Identification 5

UART Peripheral Identification 6

UART Peripheral Identification 7

UART Peripheral Identification 0

UART Peripheral Identification 1

UART Peripheral Identification 2

UART Peripheral Identification 3

UART PrimeCell Identification 0

UART PrimeCell Identification 1

UART PrimeCell Identification 2

UART PrimeCell Identification 3

0xFC0

0xFC8

0xFD0

0xFD4

0xFD8

0xFDC

0xFE0

0xFE4

0xFE8

0xFEC

0xFF0

0xFF4

0xFF8

0xFFC

UARTCC

UARTPeriphID4

UARTPeriphID5

UARTPeriphID6

UARTPeriphID7

UARTPeriphID0

UARTPeriphID1

UARTPeriphID2

UARTPeriphID3

UARTPCellID0

UARTPCellID1

UARTPCellID2

UARTPCellID3

表 6-31. USB Registers

OFFSET

0x0

ACRONYM

USBFADDR

USBPOWER

REGISTER NAME

USB Device Functional Address

USB Power

0x1

138

Detailed Description

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

表 6-31. USB Registers (continued)

OFFSET

0x2

ACRONYM

REGISTER NAME

USBTXIS

USB Transmit Interrupt Status

USB Receive Interrupt Status

USB Transmit Interrupt Enable

USB Receive Interrupt Enable

USB General Interrupt Status

USB Interrupt Enable

0x4

USBRXIS

0x6

USBTXIE

0x8

USBRXIE

0xA

USBIS

0xB

USBIE

0xC

USBFRAME

USB Frame Value

0xE

USBEPIDX

USB Endpoint Index

0xF

USBTEST

USB Test Mode

0x20

0x24

0x28

0x2C

0x30

0x34

0x38

0x3C

0x60

0x61

0x62

0x63

0x64

0x66

0x70

0x74

0x75

0x76

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x80

0x82

0x83

0x88

0x8A

0x8B

0x8C

0x8E

0x8F

0x90

0x92

0x93

0x94

USBFIFO0

USB FIFO Endpoint 0

USBFIFO1

USB FIFO Endpoint 1

USBFIFO2

USB FIFO Endpoint 2

USBFIFO3

USB FIFO Endpoint 3

USBFIFO4

USB FIFO Endpoint 4

USBFIFO5

USB FIFO Endpoint 5

USBFIFO6

USB FIFO Endpoint 6

USBFIFO7

USB FIFO Endpoint 7

USBDEVCTL

USBCCONF

USB Device Control

USB Common Configuration

USB Transmit Dynamic FIFO Sizing

USB Receive Dynamic FIFO Sizing

USB Transmit FIFO Start Address

USB Receive FIFO Start Address

USB ULPI VBUS Control

USB ULPI Register Data

USB ULPI Register Address

USB ULPI Register Control

USB Endpoint Information

USB RAM Information

USBTXFIFOSZ

USBRXFIFOSZ

USBTXFIFOADD

USBRXFIFOADD

ULPIVBUSCTL

ULPIREGDATA

ULPIREGADDR

ULPIREGCTL

USBEPINFO

USBRAMINFO

USBCONTIM

USBVPLEN

USB Connect Timing

USB OTG VBUS Pulse Timing

USBHSEOF

USB High-Speed Last Transaction to End of Frame Timing

USBFSEOF

USB Full-Speed Last Transaction to End of Frame Timing

USB Low-Speed Last Transaction to End of Frame Timing

USB Transmit Functional Address Endpoint 0

USB Transmit Hub Address Endpoint 0

USB Transmit Hub Port Endpoint 0

USBLSEOF

USBTXFUNCADDR0

USBTXHUBADDR0

USBTXHUBPORT0

USBTXFUNCADDR1

USBTXHUBADDR1

USBTXHUBPORT1

USBRXFUNCADDR1

USBRXHUBADDR1

USBRXHUBPORT1

USBTXFUNCADDR2

USBTXHUBADDR2

USBTXHUBPORT2

USBRXFUNCADDR2

USB Transmit Functional Address Endpoint 1

USB Transmit Hub Address Endpoint 1

USB Transmit Hub Port Endpoint 1

USB Receive Functional Address Endpoint 1

USB Receive Hub Address Endpoint 1

USB Receive Hub Port Endpoint 1

USB Transmit Functional Address Endpoint 2

USB Transmit Hub Address Endpoint 2

USB Transmit Hub Port Endpoint 2

USB Receive Functional Address Endpoint 2

Detailed Description

139

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ZHCSH09 –OCTOBER 2017

www.ti.com.cn

表 6-31. USB Registers (continued)

OFFSET

0x96

ACRONYM

REGISTER NAME

USBRXHUBADDR2

USBRXHUBPORT2

USBTXFUNCADDR3

USBTXHUBADDR3

USBTXHUBPORT3

USBRXFUNCADDR3

USBRXHUBADDR3

USBRXHUBPORT3

USBTXFUNCADDR4

USBTXHUBADDR4

USBTXHUBPORT4

USBRXFUNCADDR4

USBRXHUBADDR4

USBRXHUBPORT4

USBTXFUNCADDR5

USBTXHUBADDR5

USBTXHUBPORT5

USBRXFUNCADDR5

USBRXHUBADDR5

USBRXHUBPORT5

USBTXFUNCADDR6

USBTXHUBADDR6

USBTXHUBPORT6

USBRXFUNCADDR6

USBRXHUBADDR6

USBRXHUBPORT6

USBTXFUNCADDR7

USBTXHUBADDR7

USBTXHUBPORT7

USBRXFUNCADDR7

USBRXHUBADDR7

USBRXHUBPORT7

USBCSRL0

USB Receive Hub Address Endpoint 2

USB Receive Hub Port Endpoint 2

0x97

0x98

USB Transmit Functional Address Endpoint 3

USB Transmit Hub Address Endpoint 3

USB Transmit Hub Port Endpoint 3

0x9A

0x9B

0x9C

0x9E

0x9F

USB Receive Functional Address Endpoint 3

USB Receive Hub Address Endpoint 3

USB Receive Hub Port Endpoint 3

0xA0

0xA2

0xA3

0xA4

0xA6

0xA7

0xA8

0xAA

0xAB

0xAC

0xAE

0xAF

0xB0

0xB2

0xB3

0xB4

0xB6

0xB7

0xB8

0xBA

0xBB

0xBC

0xBE

0xBF

0x102

0x103

0x108

0x10A

0x10B

0x110

0x112

0x113

0x114

0x116

0x117

0x118

0x11A

0x11B

0x11C

USB Transmit Functional Address Endpoint 4

USB Transmit Hub Address Endpoint 4

USB Transmit Hub Port Endpoint 4

USB Receive Functional Address Endpoint 4

USB Receive Hub Address Endpoint 4

USB Receive Hub Port Endpoint 4

USB Transmit Functional Address Endpoint 5

USB Transmit Hub Address Endpoint 5

USB Transmit Hub Port Endpoint 5

USB Receive Functional Address Endpoint 5

USB Receive Hub Address Endpoint 5

USB Receive Hub Port Endpoint 5

USB Transmit Functional Address Endpoint 6

USB Transmit Hub Address Endpoint 6

USB Transmit Hub Port Endpoint 6

USB Receive Functional Address Endpoint 6

USB Receive Hub Address Endpoint 6

USB Receive Hub Port Endpoint 6

USB Transmit Functional Address Endpoint 7

USB Transmit Hub Address Endpoint 7

USB Transmit Hub Port Endpoint 7

USB Receive Functional Address Endpoint 7

USB Receive Hub Address Endpoint 7

USB Receive Hub Port Endpoint 7

USB Control and Status Endpoint 0 Low

USB Control and Status Endpoint 0 High

USB Receive Byte Count Endpoint 0

USB Type Endpoint 0

USBCSRH0

USBCOUNT0

USBTYPE0

USBNAKLMT

USB NAK Limit

USBTXMAXP1

USB Maximum Transmit Data Endpoint 1

USB Transmit Control and Status Endpoint 1 Low

USB Transmit Control and Status Endpoint 1 High

USB Maximum Receive Data Endpoint 1

USB Receive Control and Status Endpoint 1 Low

USB Receive Control and Status Endpoint 1 High

USB Receive Byte Count Endpoint 1

USB Host Transmit Configure Type Endpoint 1

USB Host Transmit Interval Endpoint 1

USB Host Configure Receive Type Endpoint 1

USBTXCSRL1

USBTXCSRH1

USBRXMAXP1

USBRXCSRL1

USBRXCSRH1

USBRXCOUNT1

USBTXTYPE1

USBTXINTERVAL1

USBRXTYPE1

140

Detailed Description

MSP432E401Y

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ZHCSH09 –OCTOBER 2017

表 6-31. USB Registers (continued)

OFFSET

0x11D

0x120

0x122

0x123

0x124

0x126

0x127

0x128

0x12A

0x12B

0x12C

0x12D

0x130

0x132

0x133

0x134

0x136

0x137

0x138

0x13A

0x13B

0x13C

0x13D

0x140

0x142

0x143

0x144

0x146

0x147

0x148

0x14A

0x14B

0x14C

0x14D

0x150

0x152

0x153

0x154

0x156

0x157

0x158

0x15A

0x15B

0x15C

0x15D

0x160

0x162

ACRONYM

REGISTER NAME

USBRXINTERVAL1

USBTXMAXP2

USBTXCSRL2

USBTXCSRH2

USBRXMAXP2

USBRXCSRL2

USBRXCSRH2

USBRXCOUNT2

USBTXTYPE2

USBTXINTERVAL2

USBRXTYPE2

USBRXINTERVAL2

USBTXMAXP3

USBTXCSRL3

USBTXCSRH3

USBRXMAXP3

USBRXCSRL3

USBRXCSRH3

USBRXCOUNT3

USBTXTYPE3

USBTXINTERVAL3

USBRXTYPE3

USBRXINTERVAL3

USBTXMAXP4

USBTXCSRL4

USBTXCSRH4

USBRXMAXP4

USBRXCSRL4

USBRXCSRH4

USBRXCOUNT4

USBTXTYPE4

USBTXINTERVAL4

USBRXTYPE4

USBRXINTERVAL4

USBTXMAXP5

USBTXCSRL5

USBTXCSRH5

USBRXMAXP5

USBRXCSRL5

USBRXCSRH5

USBRXCOUNT5

USBTXTYPE5

USBTXINTERVAL5

USBRXTYPE5

USBRXINTERVAL5

USBTXMAXP6

USBTXCSRL6

USB Host Receive Polling Interval Endpoint 1

USB Maximum Transmit Data Endpoint 2

USB Transmit Control and Status Endpoint 2 Low

USB Transmit Control and Status Endpoint 2 High

USB Maximum Receive Data Endpoint 2

USB Receive Control and Status Endpoint 2 Low

USB Receive Control and Status Endpoint 2 High

USB Receive Byte Count Endpoint 2

USB Host Transmit Configure Type Endpoint 2

USB Host Transmit Interval Endpoint 2

USB Host Configure Receive Type Endpoint 2

USB Host Receive Polling Interval Endpoint 2

USB Maximum Transmit Data Endpoint 3

USB Transmit Control and Status Endpoint 3 Low

USB Transmit Control and Status Endpoint 3 High

USB Maximum Receive Data Endpoint 3

USB Receive Control and Status Endpoint 3 Low

USB Receive Control and Status Endpoint 3 High

USB Receive Byte Count Endpoint 3

USB Host Transmit Configure Type Endpoint 3

USB Host Transmit Interval Endpoint 3

USB Host Configure Receive Type Endpoint 3

USB Host Receive Polling Interval Endpoint 3

USB Maximum Transmit Data Endpoint 4

USB Transmit Control and Status Endpoint 4 Low

USB Transmit Control and Status Endpoint 4 High

USB Maximum Receive Data Endpoint 4

USB Receive Control and Status Endpoint 4 Low

USB Receive Control and Status Endpoint 4 High

USB Receive Byte Count Endpoint 4

USB Host Transmit Configure Type Endpoint 4

USB Host Transmit Interval Endpoint 4

USB Host Configure Receive Type Endpoint 4

USB Host Receive Polling Interval Endpoint 4

USB Maximum Transmit Data Endpoint 5

USB Transmit Control and Status Endpoint 5 Low

USB Transmit Control and Status Endpoint 5 High

USB Maximum Receive Data Endpoint 5

USB Receive Control and Status Endpoint 5 Low

USB Receive Control and Status Endpoint 5 High

USB Receive Byte Count Endpoint 5

USB Host Transmit Configure Type Endpoint 5

USB Host Transmit Interval Endpoint 5

USB Host Configure Receive Type Endpoint 5

USB Host Receive Polling Interval Endpoint 5

USB Maximum Transmit Data Endpoint 6

USB Transmit Control and Status Endpoint 6 Low

Detailed Description

141

MSP432E401Y

ZHCSH09 –OCTOBER 2017

www.ti.com.cn

表 6-31. USB Registers (continued)

OFFSET

0x163

0x164

0x166

0x167

0x168

0x16A

0x16B

0x16C

0x16D

0x170

0x172

0x173

0x174

0x176

0x177

0x178

0x17A

0x17B

0x17C

0x17D

0x200

0x204

0x208

0x20C

0x214

0x218

0x21C

0x224

0x228

0x22C

0x234

0x238

0x23C

0x244

0x248

0x24C

0x254

0x258

0x25C

0x264

0x268

0x26C

0x274

0x278

0x27C

0x304

0x308

ACRONYM

REGISTER NAME

USBTXCSRH6

USB Transmit Control and Status Endpoint 6 High

USBRXMAXP6

USBRXCSRL6

USB Maximum Receive Data Endpoint 6

USB Receive Control and Status Endpoint 6 Low

USB Receive Control and Status Endpoint 6 High

USB Receive Byte Count Endpoint 6

USB Host Transmit Configure Type Endpoint 6

USB Host Transmit Interval Endpoint 6

USB Host Configure Receive Type Endpoint 6

USB Host Receive Polling Interval Endpoint 6

USB Maximum Transmit Data Endpoint 7

USB Transmit Control and Status Endpoint 7 Low

USB Transmit Control and Status Endpoint 7 High

USB Maximum Receive Data Endpoint 7

USB Receive Control and Status Endpoint 7 Low

USB Receive Control and Status Endpoint 7 High

USB Receive Byte Count Endpoint 7

USB Host Transmit Configure Type Endpoint 7

USB Host Transmit Interval Endpoint 7

USB Host Configure Receive Type Endpoint 7

USB Host Receive Polling Interval Endpoint 7

USB DMA Interrupt

USBRXCSRH6

USBRXCOUNT6

USBTXTYPE6

USBTXINTERVAL6

USBRXTYPE6

USBRXINTERVAL6

USBTXMAXP7

USBTXCSRL7

USBTXCSRH7

USBRXMAXP7

USBRXCSRL7

USBRXCSRH7

USBRXCOUNT7

USBTXTYPE7

USBTXINTERVAL7

USBRXTYPE7

USBRXINTERVAL7

USBDMAINTR

USBDMACTL0

USB DMA Control 0

USBDMAADDR0

USBDMACOUNT0

USBDMACTL1

USB DMA Address 0

USB DMA Count 0

USB DMA Control 1

USBDMAADDR1

USBDMACOUNT1

USBDMACTL2

USB DMA Address 1

USB DMA Count 1

USB DMA Control 2

USBDMAADDR2

USBDMACOUNT2

USBDMACTL3

USB DMA Address 2

USB DMA Count 2

USB DMA Control 3

USBDMAADDR3

USBDMACOUNT3

USBDMACTL4

USB DMA Address 3

USB DMA Count 3

USB DMA Control 4

USBDMAADDR4

USBDMACOUNT4

USBDMACTL5

USB DMA Address 4

USB DMA Count 4

USB DMA Control 5

USBDMAADDR5

USBDMACOUNT5

USBDMACTL6

USB DMA Address 5

USB DMA Count 5

USB DMA Control 6

USBDMAADDR6

USBDMACOUNT6

USBDMACTL7

USB DMA Address 6

USB DMA Count 6

USB DMA Control 7

USBDMAADDR7

USBDMACOUNT7

USBRQPKTCOUNT1

USBRQPKTCOUNT2

USB DMA Address 7

USB DMA Count 7

USB Request Packet Count in Block Transfer Endpoint 1

USB Request Packet Count in Block Transfer Endpoint 2

142

Detailed Description

MSP432E401Y

www.ti.com.cn

ZHCSH09 –OCTOBER 2017

表 6-31. USB Registers (continued)

OFFSET

0x30C

0x310

0x314

0x318

0x31C

0x340

0x342

0x344

0x346

0x348

0x360

0x362

0x363

0x364

0x365

0x400

0x404

0x408

0x40C

0x410

0x414

0x418

0x41C

0x430

0x434

0x438

0x43C

0xFC0

0xFC4

0xFC8

ACRONYM

REGISTER NAME

USBRQPKTCOUNT3

USBRQPKTCOUNT4

USBRQPKTCOUNT5

USBRQPKTCOUNT6

USBRQPKTCOUNT7

USBRXDPKTBUFDIS

USBTXDPKTBUFDIS

USBCTO

USB Request Packet Count in Block Transfer Endpoint 3

USB Request Packet Count in Block Transfer Endpoint 4

USB Request Packet Count in Block Transfer Endpoint 5

USB Request Packet Count in Block Transfer Endpoint 6

USB Request Packet Count in Block Transfer Endpoint 7

USB Receive Double Packet Buffer Disable

USB Transmit Double Packet Buffer Disable

USB Chirp Time-out

USBHHSRTN

USBHSBT

USB High Speed to UTM Operating Delay

USB High Speed Time-out Adder

USBLPMATTR

USBLPMCNTRL

USBLPMIM

USB LPM Attributes

USB LPM Control

USB LPM Interrupt Mask

USBLPMRIS

USBLPMFADDR

USBEPC

USB LPM Raw Interrupt Status

USB LPM Function Address

USB External Power Control

USBEPCRIS

USBEPCIM

USB External Power Control Raw Interrupt Status

USB External Power Control Interrupt Mask

USB External Power Control Interrupt Status and Clear

USB Device RESUME Raw Interrupt Status

USB Device RESUME Interrupt Mask

USB Device RESUME Interrupt Status and Clear

USB General-Purpose Control and Status

USB VBUS Droop Control

USBEPCISC

USBDRRIS

USBDRIM

USBDRISC

USBGPCS

USBVDC

USBVDCRIS

USBVDCIM

USB VBUS Droop Control Raw Interrupt Status

USB VBUS Droop Control Interrupt Mask

USB VBUS Droop Control Interrupt Status and Clear

USB Peripheral Properties

USBVDCISC

USBPP

USBPC

USB Peripheral Configuration

USBCC

USB Clock Configuration

表 6-32. WDT Registers

OFFSET

0x0

ACRONYM

WDTLOAD

WDTVALUE

WDTCTL

REGISTER NAME

Watchdog Load

0x4

Watchdog Value

0x8

Watchdog Control

0xC

WDTICR

Watchdog Interrupt Clear

Watchdog Raw Interrupt Status

Watchdog Masked Interrupt Status

Watchdog Test

0x10

WDTRIS

0x14

WDTMIS

0x418

0xC00

0xFD0

0xFD4

0xFD8

0xFDC

0xFE0

0xFE4

WDTTEST

WDTLOCK

WDTPeriphID4

WDTPeriphID5

WDTPeriphID6

WDTPeriphID7

WDTPeriphID0

WDTPeriphID1

Watchdog Lock

Watchdog Peripheral Identification 4

Watchdog Peripheral Identification 5

Watchdog Peripheral Identification 6

Watchdog Peripheral Identification 7

Watchdog Peripheral Identification 0

Watchdog Peripheral Identification 1

Detailed Description

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表 6-32. WDT Registers (continued)

OFFSET

0xFE8

0xFEC

0xFF0

0xFF4

0xFF8

0xFFC

ACRONYM

REGISTER NAME

WDTPeriphID2

WDTPeriphID3

WDTPCellID0

WDTPCellID1

WDTPCellID2

WDTPCellID3

Watchdog Peripheral Identification 2

Watchdog Peripheral Identification 3

Watchdog PrimeCell Identification 0

Watchdog PrimeCell Identification 1

Watchdog PrimeCell Identification 2

Watchdog PrimeCell Identification 3

6.6 Identification

Device Identification

Read-only registers in the system control module provide information about the MCU, such as version,

part number, pin count, operating temperature range, and available peripherals on the device. The Device

Identification 0 (DID0) and Device Identification 1 (DID1) registers provide details about the version,

package, and temperature range of the device. The peripheral present registers starting at system control

offset 0x300, such as the Watchdog Timer Peripheral Present (PPWD) register, provide information on

how many of each type of module are included on the device. Finally, information about the capabilities of

the on-chip peripherals are provided at offset 0xFC0 in the register space of each peripheral in the

peripheral properties registers, such as the GPTM Peripheral Properties (GPTMPP). In addition, four

unique identifier registers, Unique Identifier n (UNIQUEIDn), provide a 128-bit unique identifier that cannot

be modified for each device.

JTAG Identification

图 6-3 shows the format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1. The

major uses of the JTAG port are for manufacturer testing of component assembly and program

development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE instruction

outputs a value of 0x4BA0.0477. This value lets the debuggers automatically configure themselves to

work correctly with the Cortex-M4F during debug.

31

28 27

12 11

1 0

TDI

TDO

Version

Part Number

Manufacturer ID

1

图 6-3. IDCODE Register Format

ROM Version

The internal ROM is at address 0x0100.0000 of the device memory map.

6.7 Boot Modes

After POR and device initialization occurs, the hardware loads the stack pointer from either flash or ROM,

based on the presence of an application in flash and the state of the EN bit in the BOOTCFG register.

If the flash address 0x0000.0004 contains an erased word (value 0xFFFF.FFFF) or the EN bit is of the

BOOTCFG register is clear, the stack pointer and reset vector pointer are loaded from ROM at address

0x0100.0000 and 0x0100.0004, respectively. The bootloader executes and configures the available boot

slave interfaces and waits for a programmer, host PC, or boot server to load its software. The bootloader

uses a simple packet interface to provide synchronous communication with the device for I²C, SSI, and

UART. The speed of the bootloader is determined by the frequency of the internal oscillator (PIOSC) or

external crystal (if connected).

The ROM invokes the USB and Ethernet bootloader only when an external crystal is detected. Also, the

Ethernet bootloader works only when a 25-MHz crystal is detected.

The following serial interfaces can be used:

144

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•

UART0

SSI0

I2C0

USB

Ethernet MAC and Integrated PHY

If the check of the flash at address 0x0000.0004 contains a valid reset vector value and the EN bit in the

BOOTCFG register is set, the stack pointer and reset vector values are fetched from the beginning of

flash. This application stack pointer and reset vector are loaded and the processor executes the

application directly. Otherwise, the stack pointer and reset vector values are fetched from the beginning of

ROM.

Detailed Description

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7 Applications, Implementation, and Layout

注

Information in the following Applications section is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI's customers are responsible for

determining suitability of components for their purposes. Customers should validate and test

their design implementation to confirm system functionality.

7.1 System Design Guidelines

The SimpleLink MSP432E4 microcontrollers are highly-integrated system-on-chip (SoC) devices with

extensive interface and processing capabilities. Consequently, there are many factors to consider when

creating a schematic and designing a circuit board. By following the recommendations in this design

guide, your confidence will increase that the board will work successfully upon initial power up.

System Design Guidelines for MSP432E4 SimpleLink™ Microcontrollers

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8 器件和文档支持

8.1 入门和后续步骤

TI 提供大量的开发工具。下面是用于评估器件性能、生成代码和开发解决方案的工具和软件。

8.2 器件命名规则

为了指出产品开发周期所处的阶段，TI 为所有微处理器 (MPU) 和支持工具的产品型号分配了前缀。每个器

件都具有以下三个前缀中的其中一个：XMS、PMS 或 MSP。这些前缀代表了产品开发的发展阶段，即从工

程原型直到完全合格的生产器件和工具。

器件开发进化流程：

XMS

PMS

MSP

试验器件不一定代表最终器件的电气规范标准，并且可能不使用生产组装流程。

原型器件不一定是最终器件模型，并且不一定符合最终电气标准规范。

完全合格的器件模型的生产版本。

试验器件和工具在供货时附带如下免责声明：

“开发中的产品用于内部评估用途。”

生产器件和开发支持工具已进行完全特性描述，并且器件的质量和可靠性已经完全论证。TI 的标准保修证书

适用。

预测显示原型器件的故障率大于标准生产器件。由于这些器件的预计最终使用故障率仍未定义，德州仪器

(TI) 建议不要将它们用于任何生产系统。只有合格的产品器件将被使用。

TI 器件的命名规则也包括一个带有器件系列名称的后缀。这个后缀表示封装类型（例如，ZAD）和温度范围

（例如，“空白”是默认的商业级温度范围）。图 8-1 显示了完整器件名称的解读图例。

有关器件的订购部件号，请参阅本文档的封装选项附录、ti.com.cn 或者与您的 TI 销售代表联系。

有关裸片器件命名规则标记的其他说明，请参阅具体器件的《器件勘误表》。

MSP 432

E

411Y

T

ZAD R

Processor Family

Platform

Series

Feature Set

Optional: Distribution Format

Packaging

Optional: Temperature Range

Processor Family

Platform

MSP = Mixed-Signal Processor

XMS = Experimental Silicon

432 = TI’s 32-Bit Low-Power Microcontroller Platform

E = Ethernet and Wired Connectivity Series

Series

First Digit

4 = Flash-based devices

up to 120 MHz

Second Digit

1 = LCD

0 = No LCD

Third Digit

1 = ADC

0 = No ADC

Fourth Digit

Y = 1MB Flash

Feature Set

T = –40°C to 105°C

Optional:

Temperature Range

Packaging

http://www.ti.com/packaging

Optional:

Distribution

Format

T = Small reel

R = Large reel

No markings = Tube or tray

图 8-1. 器件命名规则

器件和文档支持

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8.3 工具和软件

设计套件与评估模块

MSP432E401Y SimpleLink 微控制器 LaunchPad 开发套件 SimpleLink 以太网 MSP432E401Y 微控制器

LaunchPad 开发套件是一款适用于基于 SimpleLink Arm Cortex-M4F 以太网微控制器的低成

本评估平台。以太网 LaunchPad 开发套件设计的重点突出了 MSP432E401Y 微控制器及其片

上 10/100 以太网 MAC 和 PHY、USB 2.0、休眠模块、运动控制脉宽调制以及大量同步串行

连接。

软件

SimpleLink MSP432E4 软件开发套件 (SDK) MSP432E4 SDK 是一套综合性的软件包，可帮助工程师在德

州仪器 (TI) MSP432E4 MCU 上快速开发功能强大的应用。MSP432E4 SDK 由多个兼容软

件组件构成，其中包括 RTOS、驱动程序和中间件以及一些如何一起使用这些组件的示例。此

外，还提供了各种示例来展示如何使用各功能区和各个受支持的器件，同时这些示例还可用作

您自己的项目的起点。

开发工具

适用于 MSP 微控制器的 Code Composer Studio™ 集成开发环境 Code Composer Studio 是一种集成开

发环境 (IDE)，支持所有 MSP430 和 SimpleLink MSP432 微控制器器件。Code Composer

Studio 包含一整套开发和调试嵌入式应用的嵌入式软件实用程序。它包含了优化的 C/C++ 编

译器、源代码编辑器、项目构建环境、调试器、描述器以及其他多种功能。借助集成式 TI 资

源浏览器，您可以访问适用于您的器件和开发板的更多示例、库、可执行代码和文档。有关更

多信息，请参阅《适用于 SimpleLink™ MSP432™ 微控制器的 Code Composer Studio™ IDE

用户指南》。

IAR 嵌入式工作平台 Kickstart 适用于 MSP 的 IAR 嵌入式工作平台 Kickstart 是一套完整的调试器和

C/C++ 编译器工具链，可用于构建和调试基于 MSP430 和 SimpleLink MSP432 微控制器的

嵌入式应用。MSP430 器件和 MSP432 器件的 C/C++ 编译器代码尺寸限制分别为 8KB 和

32KB。有关更多信息，请参阅《适用于 SimpleLink™ MSP432™ 微控制器的 IAR Embedded

Workbench® for ARM® 用户指南》。

Arm® Keil® MDK – 免费 32KB IDE Arm Keil MDK 是一套完整的调试器和 C/C++ 编译器工具链，可用于

构建和调试嵌入式应用。Keil MDK 支持低功耗和高性能 SimpleLink MSP432 MCU 系列，并

且它还包括一个全集成调试器，适用于源代码级调试和反汇编级调试，支持复杂代码和数据断

点。对于此 IDE，SimpleLink MSP432 软件开发套件 (SDK) 中仅支持非 RTOS 示例。有关更

多信息，请参阅《适用于 SimpleLink™ MSP432™ 微控制器的 Arm® Keil® MDK 用户指

南》。

MSP432E CMSIS 器件系列软件包 TI 为 MSP432E 器件提供了符合 CMSIS 标准的器件系列软件包。该软

件包将 MSP432E 器件支持添加到 IAR EWArm 8.x、Keil MDK 5.x 和 Atollic True Studio

7.x。在 IAR EWArm 中，该软件包是可选的，因为 IDE 本身便支持这些器件。

适用于 MSP432 的调试器根据设计，SimpleLink MSP432E MCU 可与 TI 及第三方供应商的各种调试器结

合使用。MSP-FET 不支持 MSP432E 器件系列。

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8.4 文档支持

如需接收文档更新通知，请访问 ti.com 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收

产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

以下文档描述了 MCU、相关外设和其他技术材料。

勘误表

《MSP432E4 SimpleLink™ 微控制器器件勘误表》介绍与已发布的规格不同的器件行为

应用报告

《SimpleLink™ MSP432E4 微控制器的系统设计指南》 SimpleLink MSP432E4 微控制器是高度集成的片

上系统 (SOC) 器件，具有扩展接口和处理功能。因此，在创建原理图和设计电路板时要考虑

很多因素。通过采用本设计指南中的建议，您会更有信心，设计的电路板在首次加电时就可以

有效工作。

《在 SimpleLink MSP432E4 微控制器上使用 I²C 主机的功能集》内部集成电路（I²C) 是一个多主多从单

端总线，通常用于将速度较低的外设 IC 连接到处理器和微控制器。从器件涵盖从非易失性存

储器到数据采集器件在内的各类型器件，如模数转换器 (ADC)、传感器等。本应用报告展示了

如何在 SimpleLink MSP432E4 微控制器上使用功能丰富的 I²C 主机与系统中的多个从器件通

信。

《通过 JTAG 接口使用 SimpleLink MSP432E4 微控制器》 IEEE 标准 1149.1 - 1990、IEEE 标准测试访

问端口和边界扫描架构 (JTAG) 是一种用于验证设计和测试组装后的印刷电路板的方法。它是

将数据传输到嵌入式系统的非易失性存储器和调试嵌入式软件的主要手段。本应用报告介绍了

JTAG 的物理连接和设计自定义电路板时需要考虑的注意事项。它还说明了如何使用

SimpleLink MSP432E4 LaunchPad 开发套件上的 JTAG 接口，以通过外部调试器调试板载微

控制器，或使用板载调试器调试非板载微控制器。

用户指南

《MSP432E4 SimpleLink™ 微控制器技术参考手册》介绍 MSP432E4 系列微控制器，包括围绕 Arm

Cortex-M4F 内核设计的片上系统 (SoC) 器件的功能块。

《MSP432E4 SimpleLink™ 微控制器引导加载程序用户指南》引导加载程序是一小段代码，可以编程到

闪存的开始位置，以便用作应用加载程序。也可以用作在 SimpleLink MSP432E4 基于 Arm

Cortex-M4 的微控制器上运行的应用的更新机制。引导加载程序可以搭建为使用 UART、

SSI、I²C、CAN、以太网或 USB 端口来更新微控制器上的代码。通过源代码修改，或者简单

地在编译时决定要包括的例程，可以定制引导加载程序。由于提供了完整源代码，因此引导加

载程序可完全自定义

器件和文档支持

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8.5 Community Resources

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术

规范，并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区为了促进工程师之间的合作，我们创建了 TI 工程师对工程师 (E2E) 社区。在 e2e.ti.com

中，您可以提问、分享知识、拓展思路并与同行工程师一道帮助解决问题。

TI Embedded Processors Wiki Established to help developers get started with Embedded Processors

from Texas Instruments and to foster innovation and growth of general knowledge about the

hardware and software surrounding these devices.

8.6 商标

SimpleLink, LaunchPad, MSP432, E2E are trademarks of Texas Instruments.

ARM, Cortex, Thumb, Thumb-2, PrimeCell, Arm7 are registered trademarks of Arm Limited.

Bluetooth is a registered trademark of Bluetooth SIG.

Wi-Fi is a registered trademark of Wi-Fi Alliance.

All other trademarks are the property of their respective owners.

8.7 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

8.8 出口管制提示

接收方同意：如果美国或其他适用法律限制或禁止将通过非披露义务的披露方获得的任何产品或技术数据

（其中包括软件）（见美国、欧盟和其他出口管理条例之定义）、或者其他适用国家条例限制的任何受管制

产品或此项技术的任何直接产品出口或再出口至任何目的地，那么在没有事先获得美国商务部和其他相关政

府机构授权的情况下，接收方不得在知情的情况下，以直接或间接的方式将其出口。

8.9 术语表

TI 术语表

这份术语表列出并解释术语、缩写和定义。

150

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提交文档反馈意见

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9 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通

知和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

机械、封装和可订购信息

151

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产品主页链接: MSP432E401Y

MECHANICAL DATA

MPQF013 – NOVEMBER 1995

PDT (S-PQFP-G128)

PLASTIC QUAD FLATPACK

0,23

0,13

M

0,40

96

0,05

65

64

97

33

128

0,13 NOM

1

32

12,40 TYP

Gage Plane

14,05

SQ

13,95

0,25

16,10

SQ

0,05 MIN

15,90

0°–5°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4087726/A 11/95

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	MSP432E401Y
厂家：	TEXAS INSTRUMENTS
描述：	具有以太网、CAN、1MB 闪存和 256kB RAM 的 SimpleLink™ 32 位 Arm Cortex-M4F MCU 以太网闪存
文件：	总156页 (文件大小：1377K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MSP432E401Y [TI]

相关型号：

MSP432E401YTPDT

MSP432E401YTPDTR

MSP432E411Y

MSP432E411YTZAD

MSP432E411YTZADR

MSP4408G

MSP4408G-C4PP

MSP4408G-C4QA

MSP4408G-C4QI

MSP4408GFH

MSP4408GPP

MSP4408GQA