NE555PWG4 [TI]
PRECISION TIMERS; 精密定时器
| 型号： | NE555PWG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PRECISION TIMERS |
| 文件： | 总27页 (文件大小：560K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NA555, NE555, SA555, SE555
PRECISION TIMERS
www.ti.com
SLFS022F–SEPTEMBER 1973–REVISED JUNE 2006
FEATURES
•
•
Timing From Microseconds to Hours
Astable or Monostable Operation
•
•
Adjustable Duty Cycle
TTL-Compatible Output Can Sink or Source
up to 200 mA
DESCRIPTION/ORDERING INFORMATION
These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the
time-delay or monostable mode of operation, the timed interval is controlled by a single external resistor and
capacitor network. In the astable mode of operation, the frequency and duty cycle can be controlled
independently with two external resistors and a single external capacitor.
The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be
altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is
set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the
threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs
and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes
low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground.
The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of
5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.
NA555...D OR P PACKAGE
SE555...FK PACKAGE
NE555...D, P, PS, OR PW PACKAGE
(TOP VIEW)
SA555...D OR P PACKAGE
SE555...D, JG, OR P PACKAGE
(TOP VIEW)
3
2
1 20 19
18
1
2
3
4
GND
TRIG
OUT
VCC
8
7
6
5
NC
NC
TRIG
NC
OUT
NC
4
5
6
7
8
DISCH
THRES
CONT
DISCH
NC
THRES
NC
17
16
15
14
RESET
9 10 11 12 13
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1973–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
On products compliant to MIL-PRF-38535, all parameters are
Instruments standard warranty. Production processing does not
tested unless otherwise noted. On all other products, production
necessarily include testing of all parameters.
processing does not necessarily include testing of all parameters.
NA555, NE555, SA555, SE555
PRECISION TIMERS
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SLFS022F–SEPTEMBER 1973–REVISED JUNE 2006
ORDERING INFORMATION
VTHRES
MAX
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
VCC = 15 V
PDIP – P
SOIC – D
SOP – PS
TSSOP – PW
PDIP – P
SOIC – D
PDIP – P
SOIC – D
PDIP – P
SOIC – D
Tube of 50
NE555P
NE555P
Tube of 75
Reel of 2500
Reel of 2000
Tube of 150
Reel of 2000
Tube of 50
Tube of 75
Reel of 2000
Tube of 50
Tube of 75
Reel of 2000
Tube of 50
Tube of 75
Reel of 2500
Tube of 50
Tube of 55
NE555D
NE555
N555
NE555DR
NE555PSR
NE555PW
NE555PWR
SA555P
0°C to 70°C
11.2 V
N555
SA555P
SA555
NA555P
NA555
SE555P
SE555D
–40°C to 85°C
–40°C to 105°C
11.2 V
11.2 V
SA555D
SA555DR
NA555P
NA555D
NA555DR
SE555P
SE555D
–55°C to 125°C
10.6
SE555DR
SE555JG
SE555FK
CDIP – JG
LCCC – FK
SE555JG
SE555FK
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
TRIGGER
THRESHOLD
VOLTAGE(1)
DISCHARGE
SWITCH
RESET
OUTPUT
VOLTAGE(1)
Low
High
High
High
Irrelevant
<1/3 VDD
>1/3 VDD
>1/3 VDD
Irrelevant
Irrelevant
>2/3 VDD
<2/3 VDD
Low
High
Low
On
Off
On
As previously established
(1) Voltage levels shown are nominal.
2
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SLFS022F–SEPTEMBER 1973–REVISED JUNE 2006
FUNCTIONAL BLOCK DIAGRAM
V
CC
RESET
8
4
CONT
5
R1
6
THRES
3
R
1
OUT
S
2
1
TRIG
7
DISCH
GND
Pin numbers shown are for the D, JG, P, PS, and PW packages.
NOTE A: RESET can override TRIG, which can override THRES.
3
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SLFS022F–SEPTEMBER 1973–REVISED JUNE 2006
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
18
UNIT
VCC
VI
Supply voltage(2)
Input voltage
V
CONT, RESET, THRES, TRIG
VCC
±225
97
V
IO
Output current
mA
D package
P package
85
θJA
Package thermal impedance(3)(4)
°C/W
PS package
PW package
FK package
JG package
95
149
5.61
14.5
150
260
300
150
θJC
Package thermal impedance(5)(6)
°C/W
TJ
Operating virtual junction temperature
Case temperature for 60 s
°C
°C
°C
°C
FK package
JG package
Lead temperature 1, 6 mm (1/16 in) from case for 60 s
Storage temperature range
Tstg
–65
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND.
(3) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) - TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) Maximum power dissipation is a function of TJ(max), θJC, and TC. The maximum allowable power dissipation at any allowable case
temperature is PD = (TJ(max) - TC)/θJC. Operating at the absolute maximum TJ of 150°C can affect reliability.
(6) The package thermal impedance is calculated in accordance with MIL-STD-883.
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
MAX
16
UNIT
NA555, NE555, SA555
SE555
VCC
Supply voltage
V
4.5
18
VI
IO
Input voltage
CONT, RESET, THRES, and TRIG
VCC
±200
105
70
V
Output current
mA
NA555
NE555
SA555
SE555
–40
0
TA
Operating free-air temperature
°C
–40
–55
85
125
4
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SLFS022F–SEPTEMBER 1973–REVISED JUNE 2006
Electrical Characteristics
VCC = 5 V to 15 V, TA = 25°C (unless otherwise noted)
NA555
SE555
NE555
SA555
PARAMETER
TEST CONDITIONS
UNIT
MIN
9.4
TYP
10
3.3
30
5
MAX
10.6
4
MIN
8.8
TYP
10
3.3
30
5
MAX
11.2
4.2
VCC = 15 V
VCC = 5 V
THRES voltage level
THRES current(1)
V
2.7
2.4
250
5.2
6
250
5.6
nA
4.8
3
4.5
1.1
VCC = 15 V
TA = –55°C to 125°C
TRIG voltage level
V
1.45
1.67
1.9
1.9
0.9
1
1.67
2.2
VCC = 5 V
TA = –55°C to 125°C
TRIG current
TRIG at 0 V
0.5
0.7
0.5
0.7
2
1
µA
0.3
0.3
RESET voltage level
V
TA = –55°C to 125°C
RESET at VCC
1.1
0.4
–1
0.1
0.1
0.4
RESET current
mA
nA
RESET at 0 V
–0.4
–0.4
–1.5
DISCH switch off-state
current
20
10
100
20
10
100
11
9.6
9.6
2.9
2.9
10.4
10.4
3.8
3.8
0.15
0.2
0.5
1
9
VCC = 15 V
TA = –55°C to 125°C
TA = –55°C to 125°C
TA = –55°C to 125°C
TA = –55°C to 125°C
TA = –55°C to 125°C
TA = –55°C to 125°C
TA = –55°C to 125°C
CONT voltage
(open circuit)
V
3.3
0.1
0.4
2
2.6
3.3
0.1
0.4
2
4
0.25
0.75
2.5
VCC = 5 V
VCC = 15 V, IOL = 10 mA
VCC = 15 V, IOL = 50 mA
VCC = 15 V, IOL = 100 mA
2.2
2.7
Low-level output voltage
V
VCC = 15 V, IOL = 200 mA
VCC = 5 V, IOL = 3.5 mA
2.5
0.1
2.5
0.1
0.35
0.2
0.35
0.4
VCC = 5 V, IOL = 5 mA
VCC = 5 V, IOL = 8 mA
VCC = 15 V, IOL = –100 mA
0.8
0.15
13.3
0.25
0.15
13.3
13
12
12.75
2.75
TA = –55°C to 125°C
High-level output voltage VCC = 15 V, IOH = –200 mA
VCC = 15 V, IOL = –100 mA
12.5
3.3
12.5
3.3
V
3
2
TA = –55°C to 125°C
VCC = 15 V
10
3
12
5
10
3
15
6
Output low, No load
Supply current
VCC = 5 V
mA
VCC = 15 V
9
10
4
9
13
5
Output high, No load
VCC = 5 V
2
2
(1) This parameter influences the maximum value of the timing resistors RA and RB in the circuit of Figure 12. For example,
when VCC = 5 V, the maximum value is R = RA + RB ≈ 3.4 MΩ, and for VCC = 15 V, the maximum value is 10 MΩ.
5
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SLFS022F–SEPTEMBER 1973–REVISED JUNE 2006
Operating Characteristics
VCC = 5 V to 15 V, TA = 25°C (unless otherwise noted)
NA555
NE555
SA555
SE555
TYP
TEST
PARAMETER
UNIT
CONDITIONS(1)
MIN
MAX
MIN
TYP
1
MAX
Each timer, monostable(3)
Initial error of timing
TA = 25°C
0.5 1.5(4)
3
%
interval(2)
Each timer, astable(5)
Each timer, monostable(3)
Each timer, astable(5)
Each timer, monostable(3)
Each timer, astable(5)
1.5
2.25
50
TA = MIN to MAX
TA = 25°C
30 100(4)
90
0.05 0.2(4)
Temperature coefficient of
timing interval
ppm/
°C
150
0.1
0.3
0.5
Supply-voltage sensitivity of
timing interval
%/V
0.15
CL = 15 pF,
TA = 25°C
Output-pulse rise time
Output-pulse fall time
100 200(4)
100 200(4)
100
100
300
300
ns
ns
CL = 15 pF,
TA = 25°C
(1) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
(2) Timing interval error is defined as the difference between the measured value and the average value of a random sample from each
process run.
(3) Values specified are for a device in a monostable circuit similar to Figure 9, with the following component values: RA = 2 kΩ to 100 kΩ,
C = 0.1 µF.
(4) On products compliant to MIL-PRF-38535, this parameter is not production tested.
(5) Values specified are for a device in an astable circuit similar to Figure 12, with the following component values: RA = 1 kΩ to 100 kΩ,
C = 0.1 µF.
6
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SLFS022F–SEPTEMBER 1973–REVISED JUNE 2006
TYPICAL CHARACTERISTICS
Data for temperatures below 0°C and above 70°C are applicable for SE555 circuits only.
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
10
7
10
7
V
CC
= 10 V
V
CC
= 5 V
4
2
4
2
T
A
= −55°C
T
A
= 25°C
1
0.7
1
0.7
T = −55°C
A
T
A
= 25°C
0.4
0.2
T = 125°C
A
0.4
0.2
T
A
= 125°C
0.1
0.1
0.07
0.07
0.04
0.02
0.04
0.02
0.01
0.01
1
2
4
7
10
20
40
70 100
1
2
4
7
10
20
40
70 100
I
− Low-Level Output Current − mA
I
− Low-Level Output Current − mA
OL
OL
Figure 1.
Figure 2.
LOW-LEVEL OUTPUT VOLTAGE
vs
DROP BETWEEN SUPPLY VOLTAGE AND OUTPUT
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
10
7
2.0
V
CC
= 15 V
T
= −55°C
= 25°C
A
1.8
1.6
4
2
T
A
= −55°C
T
A
1
0.7
1.4
1.2
1
T
A
= 125°C
0.4
0.2
T
A
= 25°C
T
A
= 125°C
0.8
0.6
0.4
0.1
0.07
0.04
0.02
0.2
0
V
= 5 V to 15 V
4
CC
0.01
1
2
4
7
10
20
40
70 100
1
2
7
10
20
40
70 100
I
− Low-Level Output Current − mA
OL
I
− High-Level Output Current − mA
OH
Figure 3.
Figure 4.
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SLFS022F–SEPTEMBER 1973–REVISED JUNE 2006
TYPICAL CHARACTERISTICS (continued)
Data for temperatures below 0°C and above 70°C are applicable for SE555 circuits only.
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
NORMALIZED OUTPUT PULSE DURATION
(MONOSTABLE OPERATION)
vs
SUPPLY VOLTAGE
10
9
1.015
1.010
1.005
1
Output Low,
No Load
8
T
= 25°C
A
7
6
5
T
= −55°C
A
4
T
A
= 125°C
3
0.995
0.990
0.985
2
1
0
5
6
7
8
9
10 11 12 13 14 15
0
5
10
15
20
V
CC
− Supply Voltage − V
V
CC
− Supply Voltage − V
Figure 5.
Figure 6.
NORMALIZED OUTPUT PULSE DURATION
(MONOSTABLE OPERATION)
vs
PROPAGATION DELAY TIME
vs
LOWEST VOLTAGE LEVEL
OF TRIGGER PULSE
FREE-AIR TEMPERATURE
1.015
1.010
1.005
1
300
250
200
150
100
50
V
CC
= 10 V
T
= −55°C
A
T
A
= 0°C
0.995
0.990
0.985
T
= 25°C
A
T
A
= 70°C
T
A
= 125°C
0
0
−75 −50 −25
0
25
50
75
100 125
0.1 x V
0.2 x V
0.3 x V
0.4 x V
CC
CC
CC
CC
T
A
− Free-Air Temperature − °C
Lowest Voltage Level of Trigger Pulse
Figure 7.
Figure 8.
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SLFS022F–SEPTEMBER 1973–REVISED JUNE 2006
APPLICATION INFORMATION
Monostable Operation
For monostable operation, any of these timers can be connected as shown in Figure 9. If the output is low,
application of a negative-going pulse to the trigger (TRIG) sets the flip-flop (Q goes low), drives the output high,
and turns off Q1. Capacitor C then is charged through RA until the voltage across the capacitor reaches the
threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the output of the
threshold comparator resets the flip-flop (Q goes high), drives the output low, and discharges C through Q1.
V
CC
(5 V to 15 V)
5
8
R
A
CONT
V
R
L
CC
4
7
RESET
DISCH
3
OUT
Output
6
2
THRES
TRIG
Input
GND
1
Pin numbers shown are for the D, JG, P, PS, and PW packages.
Figure 9. Circuit for Monostable Operation
Monostable operation is initiated when TRIG voltage falls below the trigger threshold. Once initiated, the
sequence ends only if TRIG is high at the end of the timing interval. Because of the threshold level and
saturation voltage of Q1, the output pulse duration is approximately tw = 1.1RAC. Figure 11 is a plot of the time
constant for various values of RA and C. The threshold levels and charge rates both are directly proportional to
the supply voltage, VCC. The timing interval is, therefore, independent of the supply voltage, so long as the
supply voltage is constant during the time interval.
Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges
C and reinitiates the cycle, commencing on the positive edge of the reset pulse. The output is held low as long
as the reset pulse is low. To prevent false triggering, when RESET is not used, it should be connected to VCC
.
9
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SLFS022F–SEPTEMBER 1973–REVISED JUNE 2006
APPLICATION INFORMATION (continued)
10
R
A
= 9.1 kΩ
R
A
= 10 MΩ
C = 0.01 µF
L
R
= 1 kΩ
L
1
See Figure 9
R
A
= 1 MΩ
−1
10
Input Voltage
−2
10
−3
−4
−5
10
10
10
R
= 100 kΩ
A
Output Voltage
R
= 10 kΩ
A
R
A
= 1 kΩ
Capacitor Voltage
Time − 0.1 ms/div
0.001
0.01
0.1
1
10
100
C − Capacitance − µF
Figure 10. Typical Monostable Waveforms
Figure 11. Output Pulse Duration vs Capacitance
Astable Operation
As shown in Figure 12, adding a second resistor, RB, to the circuit of Figure 9 and connecting the trigger input to
the threshold input causes the timer to self-trigger and run as a multivibrator. The capacitor C charges through
RA and RB and then discharges through RB only. Therefore, the duty cycle is controlled by the values of RA and
RB.
This astable connection results in capacitor C charging and discharging between the threshold-voltage level
(≈0.67 × VCC) and the trigger-voltage level (≈0.33 × VCC). As in the monostable circuit, charge and discharge
times (and, therefore, the frequency and duty cycle) are independent of the supply voltage.
V
CC
R
R
= 5 kW
= 3 kW
R = 1 kW
See Figure 12
A
L
(5 V to 15 V)
B
C = 0.15 µF
0.01 µF
Open
(see Note A)
5
8
R
R
A
CONT
V
CC
R
L
4
7
RESET
DISCH
3
OUT
Output
6
2
B
t
THRES
TRIG
H
Output Voltage
t
L
GND
C
1
Pin numbers shown are for the D, JG, P, PS, and PW packages.
NOTE A: Decoupling CONT voltage to ground with a capacitor can
improve operation. This should be evaluated for individual
applications.
Capacitor Voltage
Time − 0.5 ms/div
Figure 12. Circuit for Astable Operation
Figure 13. Typical Astable Waveforms
10
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APPLICATION INFORMATION (continued)
Figure 13 shows typical waveforms generated during astable operation. The output high-level duration tH and
low-level duration tL can be calculated as follows:
100 k
t
t
+ 0.693 (R ) R
C
H
L
A
B)
R
A
+ 2 R = 1 kΩ
B
+ 0.693 (R
C
R
A
+ 2 R = 10 kΩ
B
B)
10 k
1 k
Other useful relationships are shown below.
R
A
+ 2 R = 100 kΩ
B
period + t ) t + 0.693 (R ) 2R ) C
H
L
A
B
1.44
frequency [
(R ) 2R ) C
A
B
100
10
t
R
L
B
Output driver duty cycle +
+
t
) t
R
) 2R
H
L
A
B
Output waveform duty cycle
t
R
1
H
B
+
+ 1–
R
A
+ 2 R = 1 MΩ
B
t
) t
R
) 2R
H
L
A
B
R
R
A
+ 2 R = 10 MΩ
B
t
0.1
0.001
L
B
+
+
Low-to-high ratio
0.01
0.1
1
10
100
t
R
) R
H
A
B
C − Capacitance − µF
Figure 14. Free-Running Frequency
Missing-Pulse Detector
The circuit shown in Figure 15 can be used to detect a missing pulse or abnormally long spacing between
consecutive pulses in a train of pulses. The timing interval of the monostable circuit is retriggered continuously
by the input pulse train as long as the pulse spacing is less than the timing interval. A longer pulse spacing,
missing pulse, or terminated pulse train permits the timing interval to be completed, thereby generating an
output pulse as shown in Figure 16.
V
CC
(5 V to 15 V)
V
CC
= 5 V
R
A
= 1 kΩ
C = 0.1 µF
See Figure 15
R
L
R
A
4
8
RESET
V
CC
Input
3
Output
OUT
2
5
TRIG
Input Voltage
7
6
DISCH
CONT
THRES
0.01 µF
Output Voltage
GND
1
C
A5T3644
Capacitor Voltage
Time − 0.1 ms/div
Pin numbers shown are shown for the D, JG, P, PS, and PW packages.
Figure 15. Circuit for Missing-Pulse Detector
Figure 16. Completed Timing Waveforms for
Missing-Pulse Detector
11
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SLFS022F–SEPTEMBER 1973–REVISED JUNE 2006
APPLICATION INFORMATION (continued)
Frequency Divider
By adjusting the length of the timing cycle, the basic circuit of Figure 9 can be made to operate as a frequency
divider. Figure 17 shows a divide-by-three circuit that makes use of the fact that retriggering cannot occur during
the timing cycle.
V
CC
= 5 V
R
A
= 1250 Ω
C = 0.02 µF
See Figure 9
Input Voltage
Output Voltage
Capacitor Voltage
Time − 0.1 ms/div
Figure 17. Divide-by-Three Circuit Waveforms
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SLFS022F–SEPTEMBER 1973–REVISED JUNE 2006
APPLICATION INFORMATION (continued)
Pulse-Width Modulation
The operation of the timer can be modified by modulating the internal threshold and trigger voltages, which is
accomplished by applying an external voltage (or current) to CONT. Figure 18 shows a circuit for pulse-width
modulation. A continuous input pulse train triggers the monostable circuit, and a control signal modulates the
threshold voltage. Figure 19 shows the resulting output pulse-width modulation. While a sine-wave modulation
signal is shown, any wave shape could be used.
V
CC
(5 V to 15 V)
R
A
= 3 kΩ
C = 0.02 µF
= 1 kΩ
R
L
See Figure 18
R
L
R
A
4
8
RESET
V
Modulation Input Voltage
Clock Input Voltage
CC
3
2
5
OUT
Clock
Input
Output
TRIG
7
6
DISCH
THRES
Modulation
Input
(see Note A)
CONT
GND
1
C
Output Voltage
Pin numbers shown are for the D, JG, P, PS, and PW packages.
NOTE A: The modulating signal can be direct or capacitively coupled
to CONT. For direct coupling, the effects of modulation source
voltage and impedance on the bias of the timer should be
considered.
Capacitor Voltage
Time − 0.5 ms/div
Figure 18. Circuit for Pulse-Width Modulation
Figure 19. Pulse-Width-Modulation Waveforms
13
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NA555, NE555, SA555, SE555
PRECISION TIMERS
www.ti.com
SLFS022F–SEPTEMBER 1973–REVISED JUNE 2006
APPLICATION INFORMATION (continued)
Pulse-Position Modulation
As shown in Figure 20, any of these timers can be used as a pulse-position modulator. This application
modulates the threshold voltage and, thereby, the time delay, of a free-running oscillator. Figure 21 shows a
triangular-wave modulation signal for such a circuit; however, any wave shape could be used.
R
A
R
B
= 3 kΩ
= 500 Ω
V
CC
(5 V to 15 V)
R = 1 kΩ
L
See Figure 20
R
L
R
A
4
8
RESET
TRIG
V
CC
3
OUT
Output
2
5
Modulation Input Voltage
7
6
DISCH
THRES
Modulation
Input
R
B
CONT
(see Note A)
GND
Output Voltage
C
Pin numbers shown are for the D, JG, P, PS, and PW packages.
NOTE A: The modulating signal can be direct or capacitively coupled
to CONT. For direct coupling, the effects of modulation
source voltage and impedance on the bias of the timer
should be considered.
Capacitor Voltage
Time − 0.1 ms/div
Figure 20. Circuit for Pulse-Position Modulation
Figure 21. Pulse-Position-Modulation Waveforms
14
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NA555, NE555, SA555, SE555
PRECISION TIMERS
www.ti.com
SLFS022F–SEPTEMBER 1973–REVISED JUNE 2006
APPLICATION INFORMATION (continued)
Sequential Timer
Many applications, such as computers, require signals for initializing conditions during start-up. Other
applications, such as test equipment, require activation of test signals in sequence. These timing circuits can be
connected to provide such sequential control. The timers can be used in various combinations of astable or
monostable circuit connections, with or without modulation, for extremely flexible waveform control. Figure 22
shows a sequencer circuit with possible applications in many systems, and Figure 23 shows the output
waveforms.
V
CC
4
8
4
8
V
CC
OUT
4
8
V
CC
33 kΩ
33 kΩ
RA
R
B
R
C
RESET
V
RESET
RESET
CC
OUT
3
7
6
3
7
6
3
7
2
5
2
5
2
OUT
TRIG
TRIG
TRIG
0.001
µF
0.001
µF
S
DISCH
DISCH
DISCH
THRES
5
CONT
CONT
CONT
6
THRES
THRES
GND
GND
GND
1
1
1
0.01
µF
0.01
µF
0.01
µF
C
C
C
B
C
A
C
C
R
C
= 14.7 µF
= 100 kΩ
C
= 10 µF
A
Output A
Output B
Output C
R
A
= 100 kΩ
C
B
= 4.7 µF
R
B
= 100 kΩ
Pin numbers shown are for the D, JG, P, PS, and PW packages.
NOTE A: S closes momentarily at t = 0.
Figure 22. Sequential Timer Circuit
See Figure 22
t A
w
t A = 1.1 R C
A A
w
Output A
Output B
Output C
t B
w
t B = 1.1 R C
w B B
t C = 1.1 R C
C C
w
t C
w
t = 0
t − Time − 1 s/div
Figure 23. Sequential Timer Waveforms
15
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
SOIC
Drawing
JM38510/10901BPA
NA555D
ACTIVE
ACTIVE
JG
D
8
8
1
TBD
A42 SNPB
N / A for Pkg Type
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
NA555DG4
NA555DR
NA555DRG4
NA555P
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
D
D
D
P
P
D
D
D
D
D
D
P
P
8
8
8
8
8
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
NA555PE4
NE555D
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
NE555DE4
NE555DG4
NE555DR
NE555DRE4
NE555DRG4
NE555P
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
NE555PE4
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
NE555PSLE
NE555PSR
OBSOLETE
ACTIVE
SO
SO
PS
PS
8
8
TBD
Call TI
Call TI
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
NE555PSRE4
NE555PSRG4
NE555PW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
SO
PS
PS
8
8
8
8
8
8
8
8
0
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
NE555PWE4
NE555PWG4
NE555PWR
NE555PWRE4
NE555PWRG4
NE555Y
150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TBD
Call TI
Call TI
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
Orderable Device
SA555D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SA555DE4
SA555DG4
SA555DR
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
D
D
D
D
D
P
P
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SA555DRE4
SA555DRG4
SA555P
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
50
75
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU Level-1-220C-UNLIM
SA555PE4
Pb-Free
(RoHS)
SE555D
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
TBD
SE555DG4
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SE555DR
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
2500
TBD
CU NIPDAU Level-1-220C-UNLIM
SE555DRG4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SE555FKB
SE555JG
SE555JGB
SE555N
ACTIVE
ACTIVE
LCCC
CDIP
CDIP
PDIP
PDIP
FK
JG
JG
N
20
8
1
1
1
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
Call TI
N / A for Pkg Type
N / A for Pkg Type
Call TI
ACTIVE
8
OBSOLETE
ACTIVE
8
SE555P
P
8
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
330
330
330
(mm)
12
NA555DR
NA555DR
NE555DR
NE555DR
NE555PSR
NE555PWR
SA555DR
D
D
8
8
8
8
8
8
8
SITE 27
SITE 41
SITE 27
SITE 41
SITE 41
SITE 41
SITE 27
6.4
6.4
6.4
6.4
8.2
7.0
6.4
5.2
5.2
5.2
5.2
6.6
3.6
5.2
2.1
2.1
2.1
2.1
2.5
1.6
2.1
8
8
12
12
12
12
16
12
12
Q1
Q1
Q1
Q1
Q1
Q1
Q1
12
D
12
8
D
12
8
PS
PW
D
16
12
8
12
12
8
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
NA555DR
NA555DR
NE555DR
NE555DR
NE555PSR
NE555PWR
SA555DR
D
D
8
8
8
8
8
8
8
SITE 27
SITE 41
SITE 27
SITE 41
SITE 41
SITE 41
SITE 27
342.9
346.0
342.9
346.0
346.0
346.0
342.9
336.6
346.0
336.6
346.0
346.0
346.0
336.6
20.64
29.0
D
20.64
29.0
D
PS
PW
D
33.0
29.0
20.64
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.063 (1,60)
0.015 (0,38)
0.020 (0,51) MIN
0.200 (5,08) MAX
0.130 (3,30) MIN
Seating Plane
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.430 (10,92)
MAX
0.010 (0,25)
M
0.015 (0,38)
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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