NN325-Q1_技术文档

NN325-Q1

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Multisensing Touch Manager

1

FEATURES

2

•

Qualified for Automotive Applications

•

Brownout Detector

Serial Onboard Programming, No External

Programming Voltage Needed, Programmable

Code Protection by Security Fuse

Low Supply Voltage Range: 1.8 V to 3.6 V

Ultra-Low-Power Consumption

–

Active Mode: 270 µA at 1 MHz, 2.2 V

Standby Mode: 0.7 µA

•

Bootstrap Loader (BSL)

On-Chip Emulation Module

Family Members Include:

Off Mode (RAM Retention): 0.1 µA

•

Ultra-Fast Wakeup From Standby Mode in

Less Than 1 µs

–

NN325

–

32KB + 256B Flash Memory

1KB RAM

16-Bit RISC Architecture, 62.5-ns Instruction

Cycle Time

Basic Clock Module Configurations

•

Available in a 40-Pin QFN Package (RHA)

–

Internal Frequencies up to 16 MHz With

Four Calibrated Frequencies to ±1%

For Complete Module Descriptions, See the

MSP430x2xx Family User's Guide (SLAU144)

–

Internal Very-Low-Power Low-Frequency

Oscillator

APPLICATIONS

•

Optical Touch Screen

–

32-kHz Crystal

High-Frequency (HF) Crystal up to 16 MHz

Resonator

DESCRIPTION

The NN325 device is an ultra-low-power multisensing

touch manager that includes optimized peripherals

dedicated for high-performance touch-sensing

applications. The device is optimized for ultra-low

power operation using five low-power modes. The

embedded powerful 16-bit RISC core based on a

MSP430™ architecture offers 16-bit registers and

constant generators to achieve maximum code

efficiency. The digitally controlled oscillator (DCO)

allows wakeup from low-power modes to active mode

in less than 1 µs. The ultra-low-power core comes

together with two built-in 16-bit timers, a universal

serial communication interface (USCI), a 10-bit ADC

with integrated reference and data transfer controller

(DTC), and 32 I/O pins.

External Digital Clock Source

External Resistor

•

16-Bit Timer_A With Three Capture/Compare

Registers

16-Bit Timer_B With Three Capture/Compare

Registers

Universal Serial Communication Interface

(USCI)

–

Enhanced UART With Auto-Baudrate

Detection (LIN)

–

IrDA Encoder and Decoder

Synchronous SPI

I²C

•

10-Bit 200-ksps Analog-to-Digital Converter

(ADC) With Internal Reference, Sample-and-

Hold, Autoscan, and Data Transfer Controller

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

MSP430 is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

NN325-Q1

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Functional Block Diagram

VCC

VSS

P1.x/P2.x

2x8

P3.x/P4.x

2x8

XIN

XOUT

ADC10

10-Bit

Ports P1/P2

ACLK

Ports P3/P4

Basic Clock

System+

2x8 I/O

Interrupt

capability,

pullup/down

resistors

Flash

32kB

RAM

1kB

SMCLK

12

2x8 I/O

pullup/down

resistors

Channels,

Autoscan,

DTC

MCLK

MAB

16MHz

CPU

incl. 16

Registers

MDB

Emulation

(2BP)

Timer_B3

USCI_A0:

UART/LIN,

IrDA, SPI

Watchdog

WDT+

Timer_A3

JTAG

Interface

Brownout

Protection

3 CC

Registers,

Shadow

Reg

3 CC

Registers

USCI_B0:

SPI, I2C

15/16−Bit

Spy−Bi Wire

RST/NMI

2

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

Device Pinout

RHA PACKAGE

(TOP VIEW)

39 38 37 36 35 34 33 32

DVSS

XOUT/P2.7

1

2

3

4

5

6

7

8

9

10

30 P1.1/TA0

29 P1.0/TACLK/ADC10CLK

28 P2.4/TA2/A4/VREF+/VeREF+

27 P2.3/TA1/A3/VREF−/VeREF−

26 P3.7/A7

XIN/P2.6

DVSS

RST/NMI/SBWTDIO

P2.0/ACLK/A0

25 P3.6/A6

P2.1/TAINCLK/SMCLK/A1

P2.2/TA0/A2

24 P3.5/UCA0RXD/UCA0SOMI

23 P3.4/UCA0TXD/UCA0SIMO

22 P4.7/TBCLK

P3.0/UCB0STE/UCA0CLK/A5

P3.1/UCB0SIMO/UCB0SDA

21 P4.6/TBOUTH/A15

12 13 14 15 16 17 18 19

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Table 1. Terminal Functions

TERMINAL

NAME

NO.

I/O

DESCRIPTION

RHA

General-purpose digital I/O pin

Timer_A, clock signal TACLK input

ADC10, conversion clock

P1.0/TACLK/ADC10CLK

P1.1/TA0

29

30

General-purpose digital I/O pin

Timer_A, capture: CCI0A input, compare: OUT0 output

BSL transmit

General-purpose digital I/O pin

P1.2/TA1

P1.3/TA2

31

32

I/O

Timer_A, capture: CCI1A input, compare: OUT1 output

General-purpose digital I/O pin

Timer_A, capture: CCI2A input, compare: OUT2 output

General-purpose digital I/O pin

P1.4/SMCLK/TCK

P1.5/TA0/TMS

33

34

35

36

I/O

SMCLK signal output

Test Clock input for device programming and test

General-purpose digital I/O pin

Timer_A, compare: OUT0 output

Test Mode Select input for device programming and test

General-purpose digital I/O pin

P1.6/TA1/TDI/TCLK

P1.7/TA2/TDO/TDI⁽¹⁾

Timer_A, compare: OUT1 output

Test Data Input or Test Clock Input for programming and test

General-purpose digital I/O pin

Timer_A, compare: OUT2 output

Test Data Output or Test Data Input for programming and test

General-purpose digital I/O pin

ACLK output

P2.0/ACLK/A0

6

7

I/O

ADC10, analog input A0

General-purpose digital I/O pin

Timer_A, clock signal at INCLK

SMCLK signal output

P2.1/TAINCLK/SMCLK/A1

ADC10, analog input A1

General-purpose digital I/O pin

Timer_A, capture: CCI0B input, compare: OUT0 output

BSL receive

P2.2/TA0/A2

8

I/O

ADC10, analog input A2

General-purpose digital I/O pin

Timer_A, capture CCI1B input, compare: OUT1 output

ADC10, analog input A3

P2.3/TA1/A3/ V_REF-/V_eREF-

27

28

Negative reference voltage output/input

General-purpose digital I/O pin

Timer_A, compare: OUT2 output

ADC10, analog input A4

P2.4/TA2/A4/ V_REF+/V_eREF+

Positive reference voltage output/input

(1) TDO or TDI is selected via JTAG instruction.

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Table 1. Terminal Functions (continued)

TERMINAL

NAME

NO.

I/O

DESCRIPTION

RHA

General-purpose digital I/O pin

P2.5/R_OSC

XIN/P2.6

40

3

I/O

Input for external DCO resistor to define DCO frequency

Input terminal of crystal oscillator

General-purpose digital I/O pin

Output terminal of crystal oscillator

General-purpose digital I/O pin⁽²⁾

General-purpose digital I/O pin

XOUT/P2.7

2

USCI_B0 slave transmit enable

USCI_A0 clock input/output

P3.0/UCB0STE/UCA0CLK/A5

9

I/O

ADC10, analog input A5

General-purpose digital I/O pin

P3.1/UCB0SIMO/UCB0SDA

P3.2/UCB0SOMI/UCB0SCL

P3.3/UCB0CLK/UCA0STE

P3.4/UCA0TXD/UCA0SIMO

P3.5/UCA0RXD/UCA0SOMI

10

11

12

23

24

I/O

USCI_B0 slave in, master out (SPI mode)

USCI_B0 SDA I2C data (I2C mode)

General-purpose digital I/O pin

USCI_B0 slave out, master in (SPI mode)

USCI_B0 SCL I2C clock (I2C mode)

General-purpose digital I/O pin

USCI_B0 clock input/output

USCI_A0 slave transmit enable

General-purpose digital I/O pin

USCI_A0 transmit data output (UART mode)

USCI_A0 slave in, master out (SPI mode)

General-purpose digital I/O pin

USCI_A0 receive data input in UART mode

USCI_A0 slave out/master in SPI mode

General-purpose digital I/O pin

P3.6/A6

P3.7/A7

25

26

I/O

ADC10 analog input A6

General-purpose digital I/O pin

ADC10 analog input A7

General-purpose digital I/O pin

P4.0/TB0

P4.1/TB1

P4.2/TB2

15

16

17

I/O

Timer_B, capture: CCI0A input, compare: OUT0 output

General-purpose digital I/O pin

Timer_B, capture: CCI1A input, compare: OUT1 output

General-purpose digital I/O pin

Timer_B, capture: CCI2A input, compare: OUT2 output

General-purpose digital I/O pin

Timer_B, capture: CCI0B input, compare: OUT0 output

ADC10 analog input A12

P4.3/TB0/A12

P4.4/TB1/A13

18

19

I/O

General-purpose digital I/O pin

Timer_B, capture: CCI1B input, compare: OUT1 output

ADC10 analog input A13

(2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to

this pad after reset.

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Table 1. Terminal Functions (continued)

TERMINAL

NAME

NO.

I/O

DESCRIPTION

RHA

General-purpose digital I/O pin

Timer_B, compare: OUT2 output

ADC10 analog input A14

P4.5/TB2/A14

20

21

I/O

General-purpose digital I/O pin

Timer_B, switch all TB0 to TB3 outputs to high impedance

ADC10 analog input A15

P4.6/TBOUTH/A15

I/O

General-purpose digital I/O pin

P4.7/TBCLK

22

5

I/O

I

Timer_B, clock signal TBCLK input

Reset or nonmaskable interrupt input

RST/NMI/SBWTDIO

Spy-Bi-Wire test data input/output during programming and test

Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to

TEST.

TEST/SBWTCK

37

I

Spy-Bi-Wire test clock input during programming and test

Digital supply voltage

DV_CC

38, 39

14

AV_CC

Analog supply voltage

DV_SS

1, 4

13

Digital ground reference

AV_SS

Analog ground reference

QFN Pad

Pad

NA

QFN package pad; connection to DV_SSrecommended.

6

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Short-Form Description

Program Counter

Stack Pointer

PC/R0

CPU

The MSP430™ CPU has a 16-bit RISC architecture

that is highly transparent to the application. All

operations, other than program-flow instructions, are

performed as register operations in conjunction with

seven addressing modes for source operand and four

addressing modes for destination operand.

SP/R1

Status Register

SR/CG1/R2

Constant Generator

CG2/R3

R4

General-Purpose Register

The CPU is integrated with 16 registers that provide

reduced instruction execution time. The register-to-

register operation execution time is one cycle of the

CPU clock.

R5

R6

R7

Four of the registers, R0 to R3, are dedicated as

program counter, stack pointer, status register, and

constant generator respectively. The remaining

registers are general-purpose registers.

R8

R9

Peripherals are connected to the CPU using data,

address, and control buses and can be handled with

all instructions.

R10

R11

Instruction Set

The instruction set consists of 51 instructions with

three formats and seven address modes. Each

instruction can operate on word and byte data.

Table 2 shows examples of the three types of

instruction formats; Table 3 shows the address

modes.

R12

R13

R14

R15

Table 2. Instruction Word Formats

INSTRUCTION FORMAT

Dual operands, source-destination

EXAMPLE

ADD R4,R5

CALL R8

JNE

OPERATION

R4 + R5 → R5

Single operands, destination only

PC → (TOS), R8 → PC

Relative jump, unconditional/conditional

Jump-on-equal bit = 0

Table 3. Address Mode Descriptions

(1)

(2)

ADDRESS MODE

Register

S

D

SYNTAX

MOV Rs,Rd

EXAMPLE

OPERATION

R10 → R11

✓

MOV R10,R11

Indexed

✓

MOV X(Rn),Y(Rm)

MOV EDE,TONI

MOV &MEM,&TCDAT

MOV @Rn,Y(Rm)

MOV 2(R5),6(R6)

M(2+R5) → M(6+R6)

M(EDE) → M(TONI)

M(MEM) → M(TCDAT)

M(R10) → M(Tab+R6)

Symbolic (PC relative)

Absolute

Indirect

MOV @R10,Tab(R6)

MOV @R10+,R11

MOV #45,TONI

M(R10) → R11

R10 + 2 → R10

Indirect autoincrement

Immediate

✓

MOV @Rn+,Rm

MOV #X,TONI

#45 → M(TONI)

(1) S = source

(2) D = destination

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Operating Modes

The NN325-Q1 has one active mode and five software-selectable low-power modes of operation. An interrupt

event can wake up the device from any of the five low-power modes, service the request, and restore back to the

low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

•

Active mode (AM)

All clocks are active.

Low-power mode 0 (LPM0)

–

•

–

CPU is disabled.

ACLK and SMCLK remain active. MCLK is disabled.

•

Low-power mode 1 (LPM1)

–

CPU is disabled ACLK and SMCLK remain active. MCLK is disabled.

DCO dc-generator is disabled if DCO not used in active mode.

Low-power mode 2 (LPM2)

–

CPU is disabled.

MCLK and SMCLK are disabled.

DCO dc-generator remains enabled.

ACLK remains active.

•

Low-power mode 3 (LPM3)

–

CPU is disabled.

MCLK and SMCLK are disabled.

DCO dc-generator is disabled.

ACLK remains active.

Low-power mode 4 (LPM4)

–

CPU is disabled.

ACLK is disabled.

MCLK and SMCLK are disabled.

DCO dc-generator is disabled.

Crystal oscillator is stopped.

8

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Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h.

The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed), the

CPU goes into LPM4 immediately after power up.

Table 4. Interrupt Vector Addresses

SYSTEM

INTERRUPT

INTERRUPT SOURCE

INTERRUPT FLAG

WORD ADDRESS

PRIORITY

Power-up

External reset

Watchdog

PORIFG

RSTIFG

WDTIFG

KEYV⁽²⁾

Reset

0FFFEh

31, highest

Flash key violation

PC out-of-range⁽¹⁾

NMI

Oscillator fault

Flash memory access violation

NMIIFG

OFIFG

(non)-maskable,

(non)-maskable

0FFFCh

30

ACCVIFG⁽²⁾⁽³⁾

Timer_B3

TBCCR0 CCIFG⁽⁴⁾

maskable

0FFFAh

0FFF8h

29

28

TBCCR1 and TBCCR2 CCIFGs,

TBIFG⁽²⁾⁽⁴⁾

Timer_B3

maskable

0FFF6h

0FFF4h

0FFF2h

27

26

25

Watchdog Timer

Timer_A3

WDTIFG

maskable

TACCR0 CCIFG (see Note 3)

TACCR1 CCIFG

TACCR2 CCIFG

TAIFG⁽²⁾⁽⁴⁾

Timer_A3

maskable

0FFF0h

24

USCI_A0/USCI_B0 Receive

USCI_A0/USCI_B0 Transmit

ADC10

UCA0RXIFG, UCB0RXIFG⁽²⁾

UCA0TXIFG, UCB0TXIFG⁽²⁾

ADC10IFG⁽⁴⁾

maskable

0FFEEh

0FFECh

0FFEAh

0FFE8h

23

22

21

20

I/O Port P2

(eight flags)

P2IFG.0 to P2IFG.7⁽²⁾⁽⁴⁾

P1IFG.0 to P1IFG.7⁽²⁾⁽⁴⁾

maskable

0FFE6h

0FFE4h

19

18

I/O Port P1

(eight flags)

0FFE2h

0FFE0h

17

16

15

(5)

(6)

0FFDEh

0FFDCh to 0FFC0h

14 to 0, lowest

(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from

within unused address range.

(2) Multiple source flags

(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.

Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.

(4) Interrupt flags are located in the module.

(5) This location is used as bootstrap loader security key (BSLSKEY).

A 0AA55h at this location disables the BSL completely.

A zero (0h) disables the erasure of the flash if an invalid password is supplied.

(6) The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if

necessary.

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Special Function Registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits

not allocated to a functional purpose are not physically present in the device. Simple software access is provided

with this arrangement.

Legend

rw

Bit can be read and written.

rw-0, 1

rw-(0), (1)

Bit can be read and written. It is Reset or Set by PUC.

Bit can be read and written. It is Reset or Set by POR.

SFR bit is not present in device.

Table 5. Interrupt Enable 1

Address

00h

7

6

5

4

3

2

1

0

ACCVIE

rw-0

NMIIE

rw-0

OFIE

rw-0

WDTIE

rw-0

WDTIE

Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval

timer mode.

OFIE

Oscillator fault interrupt enable

(Non)maskable interrupt enable

Flash access violation interrupt enable

NMIIE

ACCVIE

Table 6. Interrupt Enable 2

Address

7

6

5

4

3

2

1

0

01h

UCB0TXIE

rw-0

UCB0RXIE

rw-0

UCA0TXIE

rw-0

UCA0RXIE

rw-0

UCA0RXIE

UCA0TXIE

UCB0RXIE

UCB0TXIE

USCI_A0 receive-interrupt enable

USCI_A0 transmit-interrupt enable

USCI_B0 receive-interrupt enable

USCI_B0 transmit-interrupt enable

Table 7. Interrupt Flag Register 1

Address

02h

7

6

5

4

3

2

1

0

NMIIFG

rw-0

RSTIFG

rw-(0)

PORIFG

rw-(1)

OFIFG

rw-1

WDTIFG

rw-(0)

WDTIFG

Set on watchdog timer overflow (in watchdog mode) or security key violation.

Reset on V_CCpower-up or a reset condition at RST/NMI pin in reset mode.

OFIFG

Flag set on oscillator fault

RSTIFG

PORIFG

NMIIFG

External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on V_CCpower up.

Power-on reset interrupt flag. Set on V_CCpower up.

Set via RST/NMI pin

Table 8. Interrupt Flag Register 2

Address

03h

7

6

5

4

3

2

1

0

UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG

rw-1 rw-0 rw-1 rw-0

UCA0RXIFG

UCA0TXIFG

UCB0RXIFG

UCB0TXIFG

USCI_A0 receive-interrupt flag

USCI_A0 transmit-interrupt flag

USCI_B0 receive-interrupt flag

USCI_B0 transmit-interrupt flag

10

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Memory Organization

Table 9. Memory Organization

NN325

Memory

Main: interrupt vector

Main: code memory

Size

Flash

32KB Flash

0FFFFh-0FFC0h

0FFFFh-08000h

Size

Flash

256 Byte

010FFh-01000h

Information memory

Boot memory

RAM

Size

ROM

1KB

0FFFh-0C00h

1KB

05FFh-0200h

Size

16-bit

8-bit

8-bit SFR

01FFh-0100h

0FFh-010h

0Fh-00h

Peripherals

Bootstrap Loader (BSL)

The bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface.

Access to the NN325-Q1 memory via the BSL is protected by user-defined password. For complete description

of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader

User’s Guide (SLAU319).

Table 10. BSL Function Pins

BSL FUNCTION

Data transmit

Data receive

RHA PACKAGE PINS

30 - P1.1

8 - P2.2

Flash Memory

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The

CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

•

Flash memory has n segments of main memory and four segments of information memory (A to D) of

64 bytes each. Each segment in main memory is 512 bytes in size.

•

Segments 0 to n may be erased in one step, or each segment may be individually erased.

Segments A to D can be erased individually, or as a group with segments 0 to n.

Segments A to D are also called information memory.

•

Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It

can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is

required.

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Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all

instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).

Oscillator and System Clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal

oscillator, an internal very-low-power low-frequency oscillator, an internal digitally-controlled oscillator (DCO), and

a high-frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low

system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in

less than 1 µs. The basic clock module provides the following clock signals:

•

Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, or the internal very-

low-power LF oscillator.

•

Main clock (MCLK), the system clock used by the CPU.

Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.

Table 11. DCO Calibration Data

(Provided From Factory in Flash Information Memory Segment A)

DCO FREQUENCY

CALIBRATION REGISTER

CALBC1_1MHZ

SIZE

byte

ADDRESS

010FFh

010FEh

010FDh

010FCh

010FBh

010FAh

010F9h

010F8h

1 MHz

CALDCO_1MHZ

CALBC1_8MHZ

8 MHz

12 MHz

16 MHz

CALDCO_8MHZ

CALBC1_12MHZ

CALDCO_12MHZ

CALBC1_16MHZ

CALDCO_16MHZ

Brownout

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and

power off.

Digital I/O

There are four 8-bit I/O ports implemented—ports P1, P2, P3, and P4:

•

All individual I/O bits are independently programmable.

Any combination of input, output, and interrupt condition is possible.

Edge-selectable interrupt input capability for all eight bits of port P1 and P2.

Read/write access to port-control registers is supported by all instructions.

Each I/O has an individually programmable pullup/pulldown resistor.

Because there are only three I/O pins implemented from port P2, bits [5:1] of all port P2 registers read as 0, and

write data is ignored.

Watchdog Timer (WDT+)

The primary function of the WDT+ module is to perform a controlled system restart after a software problem

occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed

in an application, the module can be disabled or configured as an interval timer and can generate interrupts at

selected time intervals.

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Timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple

capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare

registers.

Table 12. Timer_A3 Signal Connections

OUTPUT PIN

NUMBER

INPUT PIN NUMBER

DEVICE INPUT

SIGNAL

MODULE INPUT

NAME

MODULE OUTPUT

SIGNAL

MODULE BLOCK

RHA

29 - P1.0

TACLK

ACLK

SMCLK

TAINCLK

TA0

TACLK

ACLK

SMCLK

INCLK

CCI0A

CCI0B

GND

Timer

NA

7 - P2.1

30 - P1.1

8 - P2.2

CCR0

CCR1

CCR2

TA0

TA1

TA2

30 - P1.1

8 - P2.2

TA0

V_SS

34 - P1.5

V_CC

31 - P1.2

27 - P2.3

TA1

CCI1A

CCI1B

GND

31 - P1.2

27 - P2.3

35 - P1.6

TA1

V_SS

V_CC

32 - P1.3

TA2

CCI2A

CCI2B

GND

32 - P1.3

28 - P2.4

36 - P1.7

ACLK (internal)

V_SS

V_CC

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Timer_B3

Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple

capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare

registers.

Table 13. Timer_B3 Signal Connections

OUTPUT PIN

NUMBER

INPUT PIN NUMBER

DEVICE INPUT

SIGNAL

MODULE INPUT

NAME

MODULE OUTPUT

SIGNAL

MODULE BLOCK

RHA

22 - P4.7

TBCLK

ACLK

SMCLK

TBCLK

TB0

TBCLK

ACLK

SMCLK

INCLK

CCI0A

CCI0B

GND

Timer

NA

22 - P4.7

15 - P4.0

18 - P4.3

CCR0

CCR1

CCR2

TB0

TB1

TB2

15 - P4.0

18 - P4.3

TB0

V_SS

V_CC

16 - P4.1

19 - P4.4

TB1

CCI1A

CCI1B

GND

16 - P4.1

19 - P4.4

TB1

V_SS

V_CC

17 - P4.2

TB2

CCI2A

CCI2B

GND

17 - P4.2

20 - P4.5

ACLK (internal)

V_SS

V_CC

Universal Serial Communications Interface (USCI)

The USCI module is used for serial data communication. The USCI module supports synchronous

communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols such as UART,

enhanced UART with automatic baudrate detection (LIN), and IrDA.

USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.

USCI_B0 provides support for SPI (3 or 4 pin) and I2C.

ADC10

The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR

core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion

result handling allowing ADC samples to be converted and stored without any CPU intervention.

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Peripheral File Map

Table 14. Peripherals With Word Access

MODULE

ADC10

REGISTER NAME

SHORT NAME

ADDRESS

OFFSET

ADC data transfer start address

ADC memory

ADC10SA

ADC10MEM

ADC10CTL1

ADC10CTL0

ADC10AE0

ADC10AE1

ADC10DTC1

ADC10DTC0

TBCCR2

TBCCR1

TBCCR0

TBR

1BCh

1B4h

ADC control register 1

ADC control register 0

ADC analog enable 0

ADC analog enable 1

ADC data transfer control register 1

ADC data transfer control register 0

Capture/compare register

Timer_B register

1B2h

1B0h

04Ah

04Bh

049h

048h

Timer_B

0196h

0194h

0192h

0190h

0186h

0184h

0182h

0180h

011Eh

0176h

0174h

0172h

0170h

0166h

0164h

0162h

0160h

012Eh

012Ch

012Ah

0128h

0120h

Capture/compare control

Timer_B control

TBCCTL2

TBCCTL1

TBCCTL0

TBCTL

Timer_B interrupt vector

Capture/compare register

Timer_A register

TBIV

Timer_A

TACCR2

TACCR1

TACCR0

TAR

Capture/compare control

Timer_A control

TACCTL2

TACCTL1

TACCTL0

TACTL

Timer_A interrupt vector

Flash control 3

TAIV

Flash Memory

FCTL3

Flash control 2

FCTL2

Flash control 1

FCTL1

Watchdog Timer+

Watchdog/timer control

WDTCTL

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Table 15. Peripherals With Byte Access

MODULE

USCI_B0

REGISTER NAME

SHORT NAME

ADDRESS

OFFSET

06Fh

06Eh

06Dh

06Bh

06Ah

069h

068h

011Ah

0118h

067h

066h

065h

064h

063h

062h

061h

060h

05Fh

05Eh

05Dh

053h

058h

057h

056h

011h

01Fh

01Eh

01Dh

01Ch

010h

01Bh

01Ah

019h

018h

02Fh

02Eh

02Dh

02Ch

02Bh

02Ah

029h

028h

USCI_B0 transmit buffer

USCI_B0 receive buffer

USCI_B0 status

UCB0TXBUF

UCB0RXBUF

UCB0STAT

UCB0BR1

UCB0BR0

UCB0CTL1

UCB0CTL0

UCB0SA

UCB0OA

UCA0TXBUF

UCA0RXBUF

UCA0STAT

UCA0MCTL

UCA0BR1

UCA0BR0

UCA0CTL1

UCA0CTL0

UCA0IRRCTL

UCA0IRTCTL

UCA0ABCTL

BCSCTL3

BCSCTL2

BCSCTL1

DCOCTL

P4REN

USCI_B0 bit rate control 1

USCI_B0 bit rate control 0

USCI_B0 control 1

USCI_B0 control 0

USCI_B0 I2C slave address

USCI_B0 I2C own address

USCI_A0 transmit buffer

USCI_A0 receive buffer

USCI_A0 status

USCI_A0

USCI_A0 modulation control

USCI_A0 baud rate control 1

USCI_A0 baud rate control 0

USCI_A0 control 1

USCI_A0 control 0

USCI_A0 IrDA receive control

USCI_A0 IrDA transmit control

USCI_A0 auto baud rate control

Basic clock system control 3

Basic clock system control 2

Basic clock system control 1

DCO clock frequency control

Port P4 resistor enable

Port P4 selection

Basic Clock System+

Port P4

P4SEL

Port P4 direction

P4DIR

Port P4 output

P4OUT

Port P4 input

P4IN

Port P3

Port P2

Port P3 resistor enable

Port P3 selection

P3REN

P3SEL

Port P3 direction

P3DIR

Port P3 output

P3OUT

Port P3 input

P3IN

Port P2 resistor enable

Port P2 selection

P2REN

P2SEL

Port P2 interrupt enable

Port P2 interrupt edge select

Port P2 interrupt flag

Port P2 direction

P2IE

P2IES

P2IFG

P2DIR

Port P2 output

P2OUT

Port P2 input

P2IN

16

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Table 15. Peripherals With Byte Access (continued)

MODULE

REGISTER NAME

SHORT NAME

ADDRESS

OFFSET

Port P1

Port P1 resistor enable

Port P1 selection

P1REN

P1SEL

P1IE

027h

026h

025h

024h

023h

022h

021h

020h

003h

002h

001h

000h

Port P1 interrupt enable

Port P1 interrupt edge select

Port P1 interrupt flag

Port P1 direction

P1IES

P1IFG

P1DIR

P1OUT

P1IN

Port P1 output

Port P1 input

Special Function

SFR interrupt flag 2

SFR interrupt flag 1

SFR interrupt enable 2

SFR interrupt enable 1

IFG2

IFG1

IE2

IE1

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Absolute Maximum Ratings⁽¹⁾

Voltage applied at V_CCto V_SS

-0.3 V to 4.1 V

-0.3 V to V_CC+ 0.3 V

±2 mA

(2)

Voltage applied to any pin

Diode current at any device terminal

Unprogrammed device

Programmed device

-55°C to 150°C

(3)

Storage temperature, T_stg

(1) Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditionsis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V_SS. The JTAG fuse-blow voltage, V_FB, is allowed to exceed the absolute maximum rating. The voltage is

applied to the TEST pin when blowing the JTAG fuse.

(3) Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak

reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

Recommended Operating Conditions⁽¹⁾⁽²⁾

MIN NOM

MAX UNIT

During program

execution

1.8

3.6

V

V_CC

Supply voltage

AV_CC= DV_CC= V_CC

AV_SS= DV_SS= V_SS

During program/erase

flash memory

2.2

V_SS

T_A

Supply voltage

0

V

Operating free-air temperature

T version

-40

dc

105

°C

V_CC= 1.8 V, Duty cycle = 50% ±10%

(maximum MCLK frequency)⁽¹⁾⁽²⁾V_CC= 2.7 V, Duty cycle = 50% ±10%

4.15

Processor frequency

f_SYSTEM

12 MHz

16

(see Figure 1)

V_CC≥ 3.3 V, Duty cycle = 50% ±10%

(1) The CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified

maximum frequency.

(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.

Legend:

16 MHz

Supply voltage range,

during flash memory

programming

12 MHz

Supply voltage range,

during program execution

7.5 MHz

4.15 MHz

1.8 V

2.2 V

2.7 V

3.3 V 3.6 V

Supply Voltage −V

NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V_CC

of 2.2 V.

Figure 1. Operating Area

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(1)(2)

Active Mode Supply Current (into DV_CC+ AV_CC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

TYP

MAX UNIT

f_DCO= f_MCLK= f_SMCLK= 1 MHz,

f_ACLK= 32768 Hz,

2.2 V

270

390

Program executes in flash,

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

CPUOFF = 0, SCG0 = 0, SCG1 = 0,

OSCOFF = 0

Active mode (AM)

current (1 MHz)

I_AM,1MHz

µA

3 V

390

240

340

550

f_DCO= f_MCLK= f_SMCLK= 1 MHz,

f_ACLK= 32768 Hz,

2.2 V

3.3 V

Program executes in RAM,

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

CPUOFF = 0, SCG0 = 0, SCG1 = 0,

OSCOFF = 0

Active mode (AM)

current (1 MHz)

I_AM,1MHz

µA

f_MCLK= f_SMCLK= f_ACLK= 32768 Hz/8 =

4096 Hz,

f_DCO= 0 Hz,

Program executes in flash,

SELMx = 11, SELS = 1,

DIVMx = DIVSx = DIVAx = 11,

CPUOFF = 0, SCG0 = 1, SCG1 = 0,

OSCOFF = 0

-40°C to

85°C

5

6

9

2.2 V

3 V

105°C

18

µA

10

Active mode (AM)

current (4 kHz)

I_AM,4kHz

-40°C to

85°C

105°C

20

85

-40°C to

85°C

60

72

f_MCLK= f_SMCLK= f_{DCO(0, 0)}≈ 100 kHz,

f_ACLK= 0 Hz,

Program executes in flash,

RSELx = 0, DCOx = 0, CPUOFF = 0,

SCG0 = 0, SCG1 = 0, OSCOFF = 1

2.2 V

3 V

105°C

95

Active mode (AM)

current (100 kHz)

I_AM,100kHz

µA

-40°C to

85°C

95

105°C

105

(1) All inputs are tied to 0 V or V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external

load capacitance is chosen to closely match the required 9 pF.

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Typical Characteristics - Active-Mode Supply Current (Into DV_CC+ AV_CC)

ACTIVE-MODE CURRENT

vs

ACTIVE-MODE CURRENT

SUPPLY VOLTAGE

T_A= 25°C

vs

DCO FREQUENCY

8.0

7.0

6.0

5.0

4.0

3.0

2.0

1.0

0.0

5.0

4.0

3.0

2.0

1.0

0.0

f

= 16 MHz

= 12 MHz

DCO

T

= 85 °C

A

T

A

= 25 °C

V

CC

= 3 V

f

= 8 MHz

DCO

T

= 85 °C

= 25 °C

A

T

A

V

CC

= 2.2 V

f

= 1 MHz

DCO

1.5

2.0

2.5

3.0

3.5

4.0

0.0

4.0

8.0

12.0

16.0

V

CC

− Supply Voltage − V

f

DCO

− DCO Frequency − MHz

Figure 2.

Figure 3.

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(1)(2)

Low-Power-Mode Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

TYP

MAX UNIT

f_MCLK= 0 MHz,

2.2 V

75

90

f_SMCLK= f_DCO= 1 MHz,

f_ACLK= 32768 Hz,

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

CPUOFF = 1, SCG0 = 0,

SCG1 = 0, OSCOFF = 0

Low-power mode 0

I_LPM0,1MHz

µA

(LPM0) current⁽³⁾

3 V

90

120

f_MCLK= 0 MHz,

f_SMCLK= f_{DCO(0, 0)}≈ 100 kHz,

f_ACLK= 0 Hz,

RSELx = 0, DCOx = 0,

CPUOFF = 1, SCG0 = 0,

SCG1 = 0, OSCOFF = 1

2.2 V

3 V

37

41

48

Low-power mode 0

(LPM0) current⁽³⁾

I_LPM0,100kHz

µA

65

-40°C to

85°C

f_MCLK= f_SMCLK= 0 MHz,

f_DCO= 1 MHz,

f_ACLK= 32768 Hz,

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

CPUOFF = 1, SCG0 = 0,

SCG1 = 1, OSCOFF = 0

22

25

29

2.2 V

3 V

105°C

31

Low-power mode 2

(LPM2) current⁽⁴⁾

I_LPM2

µA

-40°C to

85°C

32

105°C

-40°C

25°C

34

1.4

3.3

0.7

2.4

5

2.2 V

3 V

85°C

f_DCO= f_MCLK= f_SMCLK= 0 MHz,

f_ACLK= 32768 Hz,

CPUOFF = 1, SCG0 = 1,

SCG1 = 1, OSCOFF = 0

105°C

-40°C

25°C

10

µA

1.5

Low-power mode 3

(LPM3) current⁽⁴⁾

I_LPM3,LFXT1

0.9

2.6

6

1.5

3.8

12

1

85°C

105°C

-40°C

25°C

0.4

0.5

1.8

4.5

0.5

0.6

2.1

5.5

0.1

1.5

4.5

1

2.2 V

3 V

85°C

2.9

f_DCO= f_MCLK= f_SMCLK= 0 MHz,

f_ACLKfrom internal LF oscillator

(VLO),

CPUOFF = 1, SCG0 = 1,

SCG1 = 1, OSCOFF = 0

105°C

-40°C

25°C

9

µA

1.2

Low-power mode 3

current, (LPM3)⁽⁴⁾

I_LPM3,VLO

1.2

3.3

11

85°C

105°C

-40°C

25°C

0.5

f_DCO= f_MCLK= f_SMCLK= 0 MHz,

f_ACLK= 0 Hz,

CPUOFF = 1, SCG0 = 1,

SCG1 = 1, OSCOFF = 1

0.5

µA

3

Low-power mode 4

(LPM4) current⁽⁵⁾

2.2 V,

3 V

I_LPM4

85°C

105°C

9

(1) All inputs are tied to 0 V or V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external

load capacitance is chosen to closely match the required 9 pF.

(3) Current for brownout and WDT clocked by SMCLK included.

(4) Current for brownout and WDT clocked by ACLK included.

(5) Current for brownout included.

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MAX UNIT

Schmitt-Trigger Inputs (Ports P1, P2, P3, P4, and RST/NMI)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

0.45 V_CC

1

TYP

0.75 V_CC

1.65

V_IT+

Positive-going input threshold voltage

2.2 V

3 V

V

1.35

2.25

0.25 V_CC

0.55

0.55 V_CC

V_IT-

Negative-going input threshold voltage

2.2 V

3 V

1.20

1.65

1

V

0.75

2.2 V

3 V

0.1

V_hys

Input voltage hysteresis (V_IT+- V_IT-)

0.3

1

For pullup: V_IN= V_SS

For pulldown: V_IN= V_CC

,

R_Pull

C_I

Pullup/pulldown resistor

Input capacitance

3 V

20

35

5

50

kΩ

V_IN= V_SSor V_CC

pF

Inputs (Ports P1, P2)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Port P1, P2: P1.x to P2.x, External trigger

pulse width to set interrupt flag⁽¹⁾

t_(int)

External interrupt timing

2.2 V, 3 V

20

ns

(1) An external signal sets the interrupt flag every time the minimum interrupt pulse width t_(int)is met. It may be set even with trigger signals

shorter than t_(int)

.

Leakage Current (Ports P1, P2, P3, and P4)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

±50 nA

(1) (2)

I_lkg(Px.y)

High-impedance leakage current

2.2 V, 3 V

(1) The leakage current is measured with V_SSor V_CCapplied to the corresponding pin(s), unless otherwise noted.

(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is

disabled.

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Outputs (Ports P1, P2, P3, and P4)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

V_CC- 0.25

V_CC- 0.6

V_CC- 0.25

V_CC- 0.6

V_SS

MAX

V_CC

UNIT

(1)

I_OH(max)= -1.5 mA

2.2 V

(2)

I_OH(max)= -6 mA

V_CC

V_OH

High-level output voltage

V

I_OH(max)= -1.5 mA⁽¹⁾

I_OH(max)= -6 mA⁽²⁾

I_OL(max)= 1.5 mA⁽¹⁾

I_OL(max)= 6 mA⁽²⁾

I_OL(max)= 1.5 mA⁽¹⁾

I_OL(max)= 6 mA⁽²⁾

V_CC

3 V

2.2 V

3 V

V_CC

V_SS+ 0.25

V_SS+ 0.6

V_SS+ 0.25

V_SS+ 0.6

V_SS

V_OL

Low-level output voltage

V

V_SS

(1) The maximum total current, I_OH(max)and I_OL(max), for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop

specified.

(2) The maximum total current, I_OH(max)and I_OL(max), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop

specified.

Output Frequency (Ports P1, P2, P3, and P4)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

2.2 V

3 V

MIN

TYP

MAX UNIT

10

P1.4/SMCLK, C_L= 20 pF,

f_Px.y

Port output frequency (with load)

MHz

12

R_L= 1 kΩ against V_CC/2⁽¹⁾⁽²⁾

2.2 V

3 V

12

f_{Port_CLK}

Clock output frequency

P2.0/ACLK, P1.4/SMCLK, C_L= 20 pF⁽²⁾

MHz

16

(1) Alternatively, a resistive divider with two 2-kΩ resistors between V_CCand V_SSis used as load. The output is connected to the center tap

of the divider.

(2) The output voltage reaches at least 10% and 90% V_CCat the specified toggle frequency.

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Typical Characteristics - Outputs

One output loaded at a time.

TYPICAL LOW-LEVEL OUTPUT CURRENT

vs

LOW-LEVEL OUTPUT VOLTAGE

25.0

20.0

15.0

10.0

5.0

50.0

40.0

30.0

20.0

10.0

0.0

V

= 2.2 V

T

= 25°C

V = 3 V

CC

A

P4.5

T

= 25°C

= 85°C

A

T

= 85°C

A

T

A

0.0

0.5

1.0

1.5

2.0

2.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

V

OL

− Low-Level Output V oltage − V

V

OL

− Low-Level Output V oltage − V

Figure 4.

Figure 5.

TYPICAL HIGH-LEVEL OUTPUT CURRENT

vs

HIGH-LEVEL OUTPUT VOLTAGE

0.0

−5.0

0.0

−10.0

−20.0

−30.0

−40.0

−50.0

V

= 2.2 V

V

= 3 V

CC

P4.5

−10.0

−15.0

−20.0

−25.0

T

= 85°C

A

T

A

= 85°C

T = 25°C

A

T

A

= 25°C

1.5

0.0

0.5

1.0

2.0

2.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

V

OH

− High-Level Output V oltage − V

V

OH

− High-Level Output V oltage − V

Figure 6.

Figure 7.

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(1) (2)

POR/Brownout Reset (BOR)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

0.7 ×

V_{(B_IT-)}

V_CC(start)

See Figure 8

dV_CC/dt ≤ 3 V/s

V

V_{(B_IT-)}

See Figure 8 through Figure 10

See Figure 8

dV_CC/dt ≤ 3 V/s

1.71

210

V

V_{hys(B_IT-)}

t_d(BOR)

70

2

130

mV

µs

See Figure 8

2000

Pulse length needed at RST/NMI pin

to accepted reset internally

t_(reset)

3 V

µs

+

(1) The current consumption of the brownout module is already included in the I_CCcurrent consumption data. The voltage level V_{(B_IT-)}

V_{hys(B_IT-)}is ≤ 1.8 V.

(2) During power up, the CPU begins code execution following a period of t_d(BOR)after V_CC= V_{(B_IT-)}+ V_{hys(B_IT-)}. The default DCO settings

must not be changed until V_CC≥ V_CC(min), where V_CC(min)is the minimum supply voltage for the desired operating frequency.

V

CC

V

hys(B_IT−)

V

(B_IT−)

V

CC(start)

1

0

t

d(BOR)

Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage

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Typical Characteristics - POR/Brownout Reset (BOR)

V

t

CC

pw

2

3 V

V

= 3 V

Typical Conditions

CC

1.5

1

V

CC(drop)

0.5

0

0.001

1

1000

1 ns

− Pulse Width − µs

t

− Pulse Width − µs

t

pw

Figure 9. V_CC(drop)Level With a Square Voltage Drop to Generate a POR/Brownout Signal

V

t

CC

pw

2

1.5

1

3 V

V

= 3 V

CC

Typical Conditions

V

CC(drop)

0.5

0

t = t

f

r

0.001

1

1000

t

r

f

t

− Pulse Width − µs

t

− Pulse Width − µs

pw

Figure 10. V_CC(drop)Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal

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Main DCO Characteristics

•

All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14

overlaps RSELx = 15.

•

DCO control bits DCOx have a step size as defined by parameter S_DCO.

Modulation control bits MODx select how often f_{DCO(RSEL,DCO+1)}is used within the period of 32 DCOCLK

cycles. The frequency f_{DCO(RSEL,DCO)}is used for the remaining cycles. The frequency is an average equal to:

32 × f

× f

DCO(RSEL,DCO)

DCO(RSEL,DCO+1)

f

=

average

MOD × f

+ (32 – MOD) × f

DCO(RSEL,DCO+1)

DCO(RSEL,DCO)

DCO Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

RSELx < 14

V_CC

MIN

1.8

TYP

MAX UNIT

3.6

V_CC

Supply voltage range

RSELx = 14

2.2

3.6

V

RSELx = 15

3.0

f_DCO(0,0)

f_DCO(0,3)

f_DCO(1,3)

f_DCO(2,3)

f_DCO(3,3)

f_DCO(4,3)

f_DCO(5,3)

f_DCO(6,3)

f_DCO(7,3)

f_DCO(8,3)

f_DCO(9,3)

f_DCO(10,3)

f_DCO(11,3)

f_DCO(12,3)

f_DCO(13,3)

f_DCO(14,3)

f_DCO(15,3)

f_DCO(15,7)

DCO frequency (0, 0)

DCO frequency (0, 3)

DCO frequency (1, 3)

DCO frequency (2, 3)

DCO frequency (3, 3)

DCO frequency (4, 3)

DCO frequency (5, 3)

DCO frequency (6, 3)

DCO frequency (7, 3)

DCO frequency (8, 3)

DCO frequency (9, 3)

DCO frequency (10, 3)

DCO frequency (11, 3)

DCO frequency (12, 3)

DCO frequency (13, 3)

DCO frequency (14, 3)

DCO frequency (15, 3)

DCO frequency (15, 7)

RSELx = 0, DCOx = 0, MODx = 0

RSELx = 0, DCOx = 3, MODx = 0

RSELx = 1, DCOx = 3, MODx = 0

RSELx = 2, DCOx = 3, MODx = 0

RSELx = 3, DCOx = 3, MODx = 0

RSELx = 4, DCOx = 3, MODx = 0

RSELx = 5, DCOx = 3, MODx = 0

RSELx = 6, DCOx = 3, MODx = 0

RSELx = 7, DCOx = 3, MODx = 0

RSELx = 8, DCOx = 3, MODx = 0

RSELx = 9, DCOx = 3, MODx = 0

RSELx = 10, DCOx = 3, MODx = 0

RSELx = 11, DCOx = 3, MODx = 0

RSELx = 12, DCOx = 3, MODx = 0

RSELx = 13, DCOx = 3, MODx = 0

RSELx = 14, DCOx = 3, MODx = 0

RSELx = 15, DCOx = 3, MODx = 0

RSELx = 15, DCOx = 7, MODx = 0

2.2 V, 3 V

3 V

0.06

0.07

0.10

0.14

0.20

0.28

0.39

0.54

0.80

1.10

1.60

2.50

3.00

4.30

6.00

8.60

12.0

16.0

0.14 MHz

0.17 MHz

0.20 MHz

0.28 MHz

0.40 MHz

0.54 MHz

0.77 MHz

1.06 MHz

1.50 MHz

2.10 MHz

3.00 MHz

4.30 MHz

5.50 MHz

7.30 MHz

9.60 MHz

13.9 MHz

18.5 MHz

26.0 MHz

3 V

Frequency step between

range RSEL and RSEL+1

S_RSEL

S_DCO

S_RSEL= f_{DCO(RSEL+1,DCO)}/f_{DCO(RSEL,DCO)}

2.2 V, 3 V

1.55 ratio

1.12 ratio

Frequency step between tap

DCO and DCO+1

S_DCO= f_{DCO(RSEL,DCO+1)}/f_{DCO(RSEL,DCO)}

Measured at P1.4/SMCLK

2.2 V, 3 V

1.05

40

1.08

50

Duty cycle

60

%

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MAX UNIT

Calibrated DCO Frequencies - Tolerance at Calibration

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

TYP

Frequency tolerance at calibration

25°C

3 V

-1

±0.2

+1

%

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

Gating time: 5 ms

f_CAL(1MHz)

f_CAL(8MHz)

f_CAL(12MHz)

f_CAL(16MHz)

1-MHz calibration value

8-MHz calibration value

12-MHz calibration value

16-MHz calibration value

25°C

3 V

0.990

7.920

11.88

15.84

1

8

1.010 MHz

8.080 MHz

BCSCTL1 = CALBC1_8MHZ,

DCOCTL = CALDCO_8MHZ,

Gating time: 5 ms

BCSCTL1 = CALBC1_12MHZ,

DCOCTL = CALDCO_12MHZ,

Gating time: 5 ms

12 12.12 MHz

16 16.16 MHz

BCSCTL1 = CALBC1_16MHZ,

DCOCTL = CALDCO_16MHZ,

Gating time: 2 ms

Calibrated DCO Frequencies - Tolerance Over Temperature 0°C to 85°C

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

TYP

MAX

UNIT

1-MHz tolerance over

temperature

0°C to 85°C

3 V

-2.5

±0.5

+2.5

%

8-MHz tolerance over

temperature

0°C to 85°C

3 V

-2.5

-3

±1.0

±2.0

+2.5

%

12-MHz tolerance over

temperature

16-MHz tolerance over

temperature

+3

2.2 V

3 V

0.97

0.975

0.97

7.76

7.8

1

1.03

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

Gating time: 5 ms

f_CAL(1MHz)

1-MHz calibration value

8-MHz calibration value

0°C to 85°C

1.025 MHz

1.03

3.6 V

2.2 V

3 V

1

8

8.4

BCSCTL1 = CALBC1_8MHZ,

DCOCTL = CALDCO_8MHZ,

Gating time: 5 ms

f_CAL(8MHz)

8

8.2 MHz

8.24

3.6 V

2.2 V

3 V

7.6

8

11.7

15.52

12

12.3

BCSCTL1 = CALBC1_12MHZ,

f_CAL(12MHz)12-MHz calibration value DCOCTL = CALDCO_12MHZ,

Gating time: 5 ms

0°C to 85°C

12.3 MHz

12.3

3.6 V

3 V

BCSCTL1 = CALBC1_16MHZ,

f_CAL(16MHz)16-MHz calibration value DCOCTL = CALDCO_16MHZ,

Gating time: 2 ms

16 16.48

MHz

3.6 V

15

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Calibrated DCO Frequencies - Tolerance Over Supply Voltage V_CC

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

-3

TYP

±2

MAX UNIT

1-MHz tolerance over V_CC

8-MHz tolerance over V_CC

12-MHz tolerance over V_CC

16-MHz tolerance over V_CC

25°C

1.8 V to 3.6 V

2.2 V to 3.6 V

3 V to 3.6 V

+3

%

-3

±2

-3

±2

-6

±2

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

Gating time: 5 ms

f_CAL(1MHz)

1-MHz calibration value

8-MHz calibration value

25°C

1.8 V to 3.6 V

2.2 V to 3.6 V

3 V to 3.6 V

0.97

7.76

11.64

15

1

8

1.03 MHz

8.24 MHz

BCSCTL1 = CALBC1_8MHZ,

DCOCTL = CALDCO_8MHZ,

Gating time: 5 ms

f_CAL(8MHz)

BCSCTL1 = CALBC1_12MHZ,

DCOCTL = CALDCO_12MHZ,

Gating time: 5 ms

f_CAL(12MHz)12-MHz calibration value

f_CAL(16MHz)16-MHz calibration value

12 12.36 MHz

16 16.48 MHz

BCSCTL1 = CALBC1_16MHZ,

DCOCTL = CALDCO_16MHZ,

Gating time: 2 ms

Calibrated DCO Frequencies - Overall Tolerance

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

TYP

MAX UNIT

1-MHz tolerance

overall

-40°C to 105°C

1.8 V to 3.6 V

-5

±2

±3

+5

+6

%

8-MHz tolerance

overall

-40°C to 105°C

1.8 V to 3.6 V

2.2 V to 3.6 V

3 V to 3.6 V

-5

-6

12-MHz

tolerance overall

16-MHz

tolerance overall

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

Gating time: 5 ms

1-MHz

calibration value

f_CAL(1MHz)

f_CAL(8MHz)

f_CAL(12MHz)

f_CAL(16MHz)

-40°C to 105°C

1.8 V to 3.6 V

2.2 V to 3.6 V

3 V to 3.6 V

0.95

7.6

1

8

1.05 MHz

8.4 MHz

12.6 MHz

17 MHz

BCSCTL1 = CALBC1_8MHZ,

DCOCTL = CALDCO_8MHZ,

Gating time: 5 ms

8-MHz

calibration value

BCSCTL1 = CALBC1_12MHZ,

DCOCTL = CALDCO_12MHZ,

Gating time: 5 ms

12-MHz

calibration value

11.4

15

12

16

BCSCTL1 = CALBC1_16MHZ,

DCOCTL = CALDCO_16MHZ,

Gating time: 2 ms

16-MHz

calibration value

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Typical Characteristics - Calibrated 1-MHz DCO Frequency

CALIBRATED 1-MHz FREQUENCY

vs

TEMPERATURE

SUPPLY VOLTAGE

1.03

1.02

1.01

1.00

0.99

0.98

0.97

1.03

1.02

1.01

1.00

0.99

0.98

0.97

V

= 1.8 V

= 2.2 V

CC

T

= 105 °C

A

T

= 85 °C

= 25 °C

A

CC

V

CC

= 3.0 V

T

A

T

A

= −40°C

V

CC

= 3.6 V

−50.0 −25.0

0.0

25.0

50.0

75.0 100.0

1.5

2.0

2.5

3.0

3.5

4.0

T

A

− Temperature − °C

V

CC

− Supply Voltage − V

Figure 11.

Figure 12.

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Wake-Up From Lower-Power Modes (LPM3/4)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ

2

BCSCTL1 = CALBC1_8MHZ,

DCOCTL = CALDCO_8MHZ

2.2 V, 3 V

1.5

µs

1

DCO clock wake-up time

from LPM3/4

t_DCO,LPM3/4

(1)

BCSCTL1 = CALBC1_12MHZ,

DCOCTL = CALDCO_12MHZ

BCSCTL1 = CALBC1_16MHZ,

DCOCTL = CALDCO_16MHZ

3 V

1

CPU wake-up time from

LPM3/4

1 / f_MCLK

t_Clock,LPM3/4

+

t_CPU,LPM3/4

(2)

(1) The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock

edge observable externally on a clock pin (MCLK or SMCLK).

(2) Parameter applicable only if DCOCLK is used for MCLK.

Typical Characteristics - DCO Clock Wake-Up Time From LPM3/4

CLOCK WAKE-UP TIME FROM LPM3

vs

DCO FREQUENCY

10.00

RSELx = 0...11

RSELx = 12...15

1.00

0.10

1.00

10.00

DCO Frequency − MHz

Figure 13.

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(1)

DCO With External Resistor R_OSC

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

DCOR = 1,

2.2 V

1.8

f_DCO,ROSC

DCO output frequency with R_OSC

RSELx = 4, DCOx = 3, MODx = 0,

T_A= 25°C

MHz

3 V

1.95

±0.1

DCOR = 1,

RSELx = 4, DCOx = 3, MODx = 0

D_T

D_V

Temperature drift

Drift with V_CC

2.2 V, 3 V

%/°C

%/V

DCOR = 1,

RSELx = 4, DCOx = 3, MODx = 0

2.2 V, 3 V

10

(1) R_OSC= 100 kΩ. Metal film resistor, type 0257, 0.6 W with 1% tolerance and T_K= ±50 ppm/°C.

Typical Characteristics - DCO With External Resistor R_OSC

DCO FREQUENCY

vs

R_OSC

vs

R_OSC

V_CC= 2.2 V, T_A= 25°C

V_CC= 3 V, T_A= 25°C

10.00

1.00

0.10

0.01

10.00

1.00

0.10

0.01

RSELx = 4

10.00

100.00

1000.00

10000.00

10.00

100.00

1000.00

10000.00

R

OSC

− External Resistor − kW

R

OSC

− External Resistor − kW

Figure 14.

Figure 15.

DCO FREQUENCY

vs

TEMPERATURE

V_CC= 3 V

DCO FREQUENCY

vs

SUPPLY VOLTAGE

T_A= 25°C

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0.00

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0.00

R

= 100k

OSC

R

= 100k

OSC

R

= 270k

= 1M

R

= 270k

= 1M

OSC

R

OSC

−50.0 −25.0

0.0

25.0

50.0

75.0 100.0

2.0

2.5

3.0

3.5

4.0

T

A

− Temperature −

C

V

CC

− Supply Voltage − V

Figure 16.

Figure 17.

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Crystal Oscillator LFXT1, Low-Frequency Mode⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

LFXT1 oscillator crystal

frequency, LF mode 0, 1

f_LFXT1,LF

XTS = 0, LFXT1Sx = 0 or 1

1.8 V to 3.6 V

32768

Hz

LFXT1 oscillator logic level

f_{LFXT1,LF,logic}

square wave input frequency, XTS = 0, LFXT1Sx = 3

LF mode

1.8 V to 3.6 V 10000

32768 50000

Hz

XTS = 0, LFXT1Sx = 0,

f_LFXT1,LF= 32768 Hz, C_L,eff= 6 pF

500

200

Oscillation allowance for

LF crystals

OA_LF

kΩ

XTS = 0, LFXT1Sx = 0,

f_LFXT1,LF= 32768 Hz, C_L,eff= 12 pF

XTS = 0, XCAPx = 0

XTS = 0, XCAPx = 1

XTS = 0, XCAPx = 2

XTS = 0, XCAPx = 3

1

5.5

8.5

11

Integrated effective load

capacitance, LF mode⁽²⁾

C_L,eff

pF

XTS = 0, Measured at P2.0/ACLK,

f_LFXT1,LF= 32768 Hz

Duty cycle, LF mode

2.2 V, 3 V

30

10

50

70

%

Oscillator fault frequency,

LF mode⁽³⁾

f_Fault,LF

XTS = 0, LFXT1Sx = 3⁽⁴⁾

10000

Hz

(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.

(a) Keep the trace between the device and the crystal as short as possible.

(b) Design a good ground plane around the oscillator pins.

(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.

(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This

signal is no longer required for the serial programming adapter.

(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a

correct setup, the effective load capacitance should always match the specification of the crystal that is used.

(3) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(4) Measured with logic-level input frequency but also applies to operation with crystals.

Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

T_A

V_CC

MIN

TYP

MAX UNIT

-40°C to 85°C

105°C

4

12

20

f_VLO

VLO frequency

2.2 V, 3 V

kHz

22

(1)

df_VLO/dT

VLO frequency temperature drift

VLO frequency supply voltage drift

-40°C to 105°C

25°C

2.2 V, 3 V

0.5

4

%/°C

%/V

(2)

df_VLO/dV_CC

1.8 V to 3.6 V

(1) Calculated using the box method:

I version: [MAX(-40...85°C) - MIN(-40...85°C)]/MIN(-40...85°C)/[85°C - (-40°C)]

T version: [MAX(-40...105°C) - MIN(-40...105°C)]/MIN(-40...105°C)/[105°C - (-40°C)]

(2) Calculated using the box method: [MAX(1.8...3.6 V) - MIN(1.8...3.6 V)]/MIN(1.8...3.6 V)/(3.6 V - 1.8 V)

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MAX UNIT

Crystal Oscillator LFXT1, High-Frequency Mode⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

LFXT1 oscillator crystal

frequency, HF mode 0

f_LFXT1,HF0

f_LFXT1,HF1

XTS = 1, LFXT1Sx = 0

XTS = 1, LFXT1Sx = 1

1.8 V to 3.6 V

0.4

1

MHz

LFXT1 oscillator crystal

frequency, HF mode 1

1.8 V to 3.6 V

1

4

1.8 V to 3.6 V

2.2 V to 3.6 V

3 V to 3.6 V

2

10

LFXT1 oscillator crystal

frequency, HF mode 2

f_LFXT1,HF2

XTS = 1, LFXT1Sx = 2

12 MHz

2

16

1.8 V to 3.6 V

2.2 V to 3.6 V

3 V to 3.6 V

0.4

10

LFXT1 oscillator logic-level

square-wave input frequency, HF XTS = 1, LFXT1Sx = 3

mode

f_{LFXT1,HF,logic}

12 MHz

16

XTS = 1, LFXT1Sx = 0,

f_LFXT1,HF= 1 MHz,

C_L,eff= 15 pF

2700

800

Oscillation allowance for HF

crystals (see Figure 18 and

Figure 19)

XTS = 1, LFXT1Sx = 1,

f_LFXT1,HF= 4 MHz,

C_L,eff= 15 pF

OA_HF

Ω

XTS = 1, LFXT1Sx = 2,

f_LFXT1,HF= 16 MHz,

C_L,eff= 15 pF

300

1

Integrated effective load

capacitance, HF mode⁽²⁾

C_L,eff

XTS = 1⁽³⁾

pF

XTS = 1,

Measured at P2.0/ACLK,

f_LFXT1,HF= 10 MHz

40

50

60

Duty cycle, HF mode

2.2 V, 3 V

%

XTS = 1,

Measured at P2.0/ACLK,

f_LFXT1,HF= 16 MHz

XTS = 1, LFXT1Sx = 3⁽⁵⁾

40

30

50

60

f_Fault,HF

Oscillator fault frequency⁽⁴⁾

300 kHz

(1) To improve EMI on the XT1 oscillator the following guidelines should be observed:

(a) Keep the trace between the device and the crystal as short as possible.

(b) Design a good ground plane around the oscillator pins.

(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.

(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This

signal is no longer required for the serial programming adapter.

(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is

recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should

always match the specification of the used crystal.

(3) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

(4) Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and

frequencies in between might set the flag.

(5) Measured with logic-level input frequency, but also applies to operation with crystals.

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Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1)

OSCILLATION ALLOWANCE

vs

CRYSTAL FREQUENCY

C_L,eff= 15 pF, T_A= 25°C

OSCILLATOR SUPPLY CURRENT

vs

CRYSTAL FREQUENCY

C_L,eff= 15 pF, T_A= 25°C

800.0

700.0

600.0

500.0

400.0

300.0

200.0

100.0

0.0

100000.00

LFXT1Sx = 3

10000.00

1000.00

100.00

10.00

LFXT1Sx = 3

LFXT1Sx = 2

LFXT1Sx = 1

8.0

0.10

1.00

10.00

100.00

0.0

4.0

12.0

16.0

20.0

Crystal Frequency − MHz

Figure 18.

Figure 19.

Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK

2.2 V

10

f_TA

Timer_A clock frequency

Timer_A capture timing

External: TACLK, INCLK

Duty cycle = 50% ± 10%

MHz

3 V

16

t_TA,cap

TA0, TA1, TA2

2.2 V, 3 V

20

ns

Timer_B

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK

2.2 V

10

f_TB

Timer_B clock frequency

Timer_B capture timing

External: TACLK, INCLK

Duty cycle = 50% ± 10%

MHz

3 V

16

t_TB,cap

TB0, TB1, TB2

2.2 V, 3 V

20

ns

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USCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK

External: UCLK

f_USCI

USCI input clock frequency

f_SYSTEMMHz

Duty cycle = 50% ± 10%

BITCLK clock frequency

(equals baud rate in MBaud)

f_BITCLK

t_τ

2.2 V, 3 V

1

MHz

ns

2.2 V

3 V

50

150

100

600

UART receive deglitch time⁽¹⁾

(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are

correctly recognized their width should exceed the maximum specification of the deglitch time.

USCI (SPI Master Mode)⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(see Figure 20 and Figure 21)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

SMCLK, ACLK

Duty cycle = 50% ± 10%

f_USCI

USCI input clock frequency

f_SYSTEMMHz

2.2 V

3 V

110

75

0

t_SU,MI

SOMI input data setup time

SOMI input data hold time

SIMO output data valid time

ns

2.2 V

3 V

t_HD,MI

0

2.2 V

3 V

30

ns

20

UCLK edge to SIMO valid,

C_L= 20 pF

t_VALID,MO

(1) f_UCxCLK= 1/2t_LO/HIwith t_LO/HI≥ max(t_{VALID,MO(USCI)}+ t_SU,SI(Slave), t_SU,MI(USCI)+ t_{VALID,SO(Slave)}).

For the slave's parameters t_SU,SI(Slave)and t_{VALID,SO(Slave)}, see the SPI parameters of the attached slave.

USCI (SPI Slave Mode)⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(see Figure 22 and Figure 23)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

t_STE,LEAD

t_STE,LAG

t_STE,ACC

STE lead time, STE low to clock

STE lag time, Last clock to STE high

STE access time, STE low to SOMI data out

2.2 V, 3 V

50

ns

10

50

STE disable time, STE high to SOMI high

impedance

t_STE,DIS

t_SU,SI

2.2 V, 3 V

ns

2.2 V

3 V

20

15

10

SIMO input data setup time

SIMO input data hold time

SOMI output data valid time

2.2 V

3 V

t_HD,SI

ns

2.2 V

3 V

75

50

110

ns

UCLK edge to SOMI valid,

C_L= 20 pF

t_VALID,SO

75

(1) f_UCxCLK= 1/2t_LO/HIwith t_LO/HI≥ max(t_{VALID,MO(Master)}+ t_SU,SI(USCI), t_{SU,MI(Master)}+ t_{VALID,SO(USCI)}).

For the master's parameters t_{SU,MI(Master)}and t_{VALID,MO(Master)}, see the SPI parameters of the attached slave.

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1/f

UCxCLK

CKPL=0

CKPL=1

UCLK

t

LO/HI

SU,MI

t

HD,MI

SOMI

SIMO

t

VALID,MO

Figure 20. SPI Master Mode, CKPH = 0

1/f

UCxCLK

CKPL=0

CKPL=1

UCLK

t

LO/HI

t

HD,MI

t

SU,MI

SOMI

SIMO

t

VALID,MO

Figure 21. SPI Master Mode, CKPH = 1

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t

STE,LEAD

STE,LAG

STE

1/f

UCxCLK

CKPL=0

CKPL=1

UCLK

t

LO/HI

SU,SI

t

HD,SI

SIMO

SOMI

t

STE,ACC

VALID,SO

STE,DIS

Figure 22. SPI Slave Mode, CKPH = 0

t

STE,LEAD

STE,LAG

STE

1/f

UCxCLK

CKPL=0

CKPL=1

UCLK

t

LO/HI

t

HD,SI

t

SU,SI

SIMO

SOMI

t

STE,ACC

VALID,SO

STE,DIS

Figure 23. SPI Slave Mode, CKPH = 1

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USCI (I2C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 24)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK

External: UCLK

f_USCI

USCI input clock frequency

f_SYSTEMMHz

Duty cycle = 50% ± 10%

f_SCL

SCL clock frequency

2.2 V, 3 V

0

4

400 kHz

µs

f

_SCL≤ 100 kHz

f_SCL> 100 kHz

_SCL≤ 100 kHz

f_SCL> 100 kHz

t_HD,STA

Hold time (repeated) START

0.6

4.7

0.6

0

f

t_SU,STA

Setup time for a repeated START

2.2 V, 3 V

µs

t_HD,DAT

t_SU,DAT

t_SU,STO

Data hold time

2.2 V, 3 V

2.2 V

ns

µs

Data setup time

Setup time for STOP

250

4

50

150

100

600

ns

t_SP

Pulse width of spikes suppressed by input filter

3 V

600

t

t t

SU,STA HD,STA

HD,STA

SDA

SCL

1/f

SCL

t

SP

t

SU,STO

SU,DAT

t

HD,DAT

Figure 24. I2C Mode Timing

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MAX UNIT

10-Bit ADC, Power Supply and Input Range Conditions⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

TYP

Analog supply voltage

range

V_CC

V_SS= 0 V

2.2

3.6

V

All Ax terminals,

Analog inputs selected in

ADC10AE register

Analog input voltage

range⁽²⁾

V_Ax

0

V_CC

f_ADC10CLK= 5 MHz,

ADC10ON = 1, REFON = 0,

2.2 V

3 V

0.52

0.6

1.05

I_ADC10ADC10 supply current⁽³⁾ADC10SHT0 = 1,

ADC10SHT1 = 0,

-40°C to 105°C

mA

1.2

ADC10DIV = 0

f_ADC10CLK= 5 MHz,

ADC10ON = 0, REF2_5V = 0,

REFON = 1, REFOUT = 0

2.2 V, 3 V

3 V

0.25

0.4

Reference supply

current, reference buffer

disabled⁽⁴⁾

I_REF+

f_ADC10CLK= 5 MHz,

ADC10ON = 0, REF2_5V = 1,

REFON = 1, REFOUT = 0

0.25

1.1

f_ADC10CLK= 5 MHz

-40°C to 85°C

105°C

2.2 V, 3 V

1.4

1.8

0.7

0.8

Reference buffer supply

ADC10ON = 0, REFON = 1,

REF2_5V = 0, REFOUT = 1,

ADC10SR = 0

I_REFB,0current with

mA

ADC10SR = 0⁽⁴⁾

f_ADC10CLK= 5 MHz,

-40°C to 85°C

105°C

0.5

Reference buffer supply

ADC10ON = 0, REFON = 1,

REF2_5V = 0, REFOUT = 1,

ADC10SR = 1

I_REFB,1current with

ADC10SR = 1⁽⁴⁾

Only one terminal Ax selected at

a time

C_I

R_I

Input capacitance

-40°C to 105°C

27

pF

Input MUX ON

resistance

0 V ≤ V_Ax≤ V_CC

2.2 V, 3 V

2000

Ω

(1) The leakage current is defined in the leakage current table with Px.x/Ax parameter.

(2) The analog input voltage range must be within the selected reference voltage range V_R+to V_R-for valid conversion results.

(3) The internal reference supply current is not included in current consumption parameter I_ADC10

.

(4) The internal reference current is supplied via terminal V_CC. Consumption is independent of the ADC10ON control bit, unless a

conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.

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10-Bit ADC, Built-In Voltage Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_VREF+≤ 1 mA, REF2_5V = 0

V_CC

MIN

2.2

TYP

MAX

UNIT

Positive built-in

V_CC,REF+

reference analog

supply voltage range

I_VREF+≤ 0.5 mA, REF2_5V = 1

I_VREF+≤ 1 mA, REF2_5V = 1

2.8

2.9

V

I_VREF+≤ I_VREF+max, REF2_5V = 0

I_VREF+≤ I_VREF+max, REF2_5V = 1

2.2 V, 3 V

3 V

1.41

2.35

1.5

2.5

1.59

2.65

±0.5

±1

Positive built-in

reference voltage

V_REF+

V

2.2 V

3 V

Maximum V_REF+

load current

I_LD,VREF+

mA

I_VREF+= 500 µA ± 100 µA,

Analog input voltage V_Ax≈ 0.75 V,

REF2_5V = 0

2.2 V, 3 V

3 V

±2

V_REF+load

regulation

LSB

ns

I_VREF+= 500 µA ± 100 µA,

Analog input voltage V_Ax≈ 1.25 V,

REF2_5V = 1

I_VREF+= 100 µA to 900 µA,

V_Ax≈ 0.5 x V_REF+

ADC10SR = 0

400

V_REF+load

regulation response

time

,

3 V

Error of conversion result

≤1 LSB

ADC10SR = 1

2000

Maximum

I_VREF+≤ ±1 mA,

REFON = 1, REFOUT = 1

C_VREF+

T_CREF+

t_REFON

capacitance at pin

2.2 V, 3 V

3.6 V

100

±100

30

pF

ppm/°C

µs

(1)

V_REF+

Temperature

coefficient

I_VREF+= constant with

0 mA ≤ I_VREF+≤ 1 mA

Settling time of

internal reference

voltage⁽²⁾

I_VREF+= 0.5 mA, REF2_5V = 0,

REFON = 0 to 1

I_VREF+= 0.5 mA,

REF2_5V = 0,

REFON = 1,

ADC10SR = 0

ADC10SR = 1

ADC10SR = 0

ADC10SR = 1

1

2.5

2

2.2 V

3 V

REFBURST = 1

Settling time of

t_REFBURST

µs

reference buffer⁽²⁾

I_VREF+= 0.5 mA,

REF2_5V = 1,

REFON = 1,

4.5

REFBURST = 1

(1) The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA 2/A4/V_REF+/ V_eREF+(REFOUT = 1),

must be limited; the reference buffer may become unstable otherwise.

(2) The condition is that the error in a conversion started after t_REFONor t_RefBufis less than ±0.5 LSB.

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MAX UNIT

10-Bit ADC, External Reference⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

V_eREF+> V_eREF-

SREF1 = 1, SREF0 = 0

,

1.4

V_CC

Positive external reference input

voltage range⁽²⁾

V_eREF+

V

_eREF-≤ V_eREF+≤ V_CC- 0.15 V,

1.4

0

3

SREF1 = 1, SREF0 = 1⁽³⁾

Negative external reference input

voltage range⁽⁴⁾

V_eREF-

V_eREF+> V_eREF-

1.2

V_CC

±1

V

Differential external reference

input voltage range

ΔV_eREF= V_eREF+- V_eREF-

(5)

ΔV_eREF

V_eREF+> V_eREF-

1.4

0 V ≤ V_eREF+≤ V_CC

SREF1 = 1, SREF0 = 0

,

I_VeREF+

Static input current into V_eREF+

Static input current into V_eREF-

2.2 V, 3 V

µA

0 V ≤ V_eREF+≤ V_CC- 0.15 V ≤ 3 V,

0

SREF1 = 1, SREF0 = 1⁽³⁾

I_VeREF-

0 V ≤ V_eREF-≤ V_CC

±1

(1) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the

dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the

recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.

(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced

accuracy requirements.

(3) Under this condition, the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply

current I_REFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.

(4) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced

accuracy requirements.

(5) The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with

reduced accuracy requirements.

10-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

0.45

TYP

MAX UNIT

ADC10SR = 0

ADC10SR = 1

6.3

ADC10 input clock

frequency

For specified performance of

ADC10 linearity parameters

f_ADC10CLK

f_ADC10OSC

2.2 V, 3 V

MHz

1.5

ADC10 built-in oscillator ADC10DIVx = 0, ADC10SSELx = 0,

2.2 V, 3 V

3.7

6.3 MHz

frequency

f_ADC10CLK= f_ADC10OSC

ADC10 built-in oscillator, ADC10SSELx = 0,

f_ADC10CLK= f_ADC10OSC

2.06

3.51

µs

t_CONVERT

Conversion time

f_ADC10CLKfrom ACLK, MCLK or SMCLK,

13 × ADC10DIVx ×

1 / f_ADC10CLK

ADC10SSELx ≠ 0

Turn on settling time of

the ADC⁽¹⁾

t_ADC10ON

100

ns

(1) The condition is that the error in a conversion started after t_ADC10ONis less than ±0.5 LSB. The reference and input signal are already

settled.

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10-Bit ADC, Linearity Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Integral linearity error

Differential linearity error

Offset error

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

±1 LSB

E_I

2.2 V, 3 V

E_D

E_O

Source impedance R_S< 100 Ω

SREFx = 010, unbuffered external reference,

V_eREF+= 1.5 V

2.2 V

3 V

±1.1

±2

SREFx = 010, unbuffered external reference,

V_eREF+= 2.5 V

±2

E_G

Gain error

LSB

±4

SREFx = 011, buffered external reference⁽¹⁾

V_eREF+= 1.5 V

,

2.2 V

3 V

SREFx = 011, buffered external reference⁽¹⁾

V_eREF+= 2.5 V

,

±3

±5

SREFx = 010, unbuffered external reference,

V_eREF+= 1.5 V

2.2 V

3 V

SREFx = 010, unbuffered external reference,

V_eREF+= 2.5 V

±2

±5

E_T

Total unadjusted error

LSB

±7

SREFx = 011, buffered external reference⁽¹⁾

V_eREF+= 1.5 V

,

2.2 V

3 V

±2

SREFx = 011, buffered external reference⁽¹⁾

V_eREF+= 2.5 V

,

±2

±6

(1) The reference buffer offset adds to the gain and total unadjusted error.

(1)

10-Bit ADC, Temperature Sensor and Built-In V_MID

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

2.2 V

MIN

TYP

40

MAX UNIT

120

µA

Temperature sensor supply

current⁽¹⁾

REFON = 0, INCHx = 0Ah,

T_A= 25°C

I_SENSOR

3 V

60

160

TC_SENSOR

ADC10ON = 1, INCHx = 0Ah⁽²⁾

2.2 V, 3 V

3.44

-100

3.55

3.66 mV/°C

V_{Offset,Sensor}

Sensor offset voltage

100

mV

Temperature sensor voltage at

T_A= 105°C (T version only)

1265

1365

1465

Temperature sensor voltage at T_A= 85°C

Temperature sensor voltage at T_A= 25°C

Temperature sensor voltage at T_A= 0°C

1195

985

1295

1085

995

1395

1185

1095

V_SENSOR

Sensor output voltage⁽³⁾

2.2 V, 3 V

mV

895

Sample time required if

channel 10 is selected⁽⁴⁾

ADC10ON = 1, INCHx = 0Ah,

Error of conversion result ≤ 1 LSB

t_{SENSOR(sample)}

I_VMID

30

µs

2.2 V

3 V

N/A

Current into divider at

channel 11⁽⁴⁾

ADC10ON = 1, INCHx = 0Bh

µA

2.2 V

3 V

1.06

1.46

1.1

1.5

1.14

1.54

ADC10ON = 1, INCHx = 0Bh,

V_MID

V_CCdivider at channel 11

V

V_MID≈ 0.5 × V_CC

2.2 V

3 V

1400

1220

Sample time required if

channel 11 is selected⁽⁵⁾

ADC10ON = 1, INCHx = 0Bh,

Error of conversion result ≤ 1 LSB

t_VMID(sample)

ns

(1) The sensor current I_SENSORis consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON = 1 and INCH = 0Ah and sample signal is

high).When REFON = 1, I_SENSORis included in I_REF+.When REFON = 0, I_SENSORapplies during conversion of the temperature sensor

input (INCH = 0Ah).

(2) The following formula can be used to calculate the temperature sensor output voltage:

V_Sensor,typ= TC_Sensor( 273 + T [°C] ) + V_{Offset,sensor}[mV] or

V_Sensor,typ= TC_SensorT [°C] + V_Sensor(T_A= 0°C) [mV]

(3) Results based on characterization and/or production test, not TC_Sensoror V_{Offset,sensor}

.

(4) No additional current is needed. The V_MIDis used during sampling.

(5) The on time, t_VMID(on), is included in the sampling time, t_VMID(sample); no additional on time is needed.

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Flash Memory

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

2.2

TYP

MAX

3.6

476

5

UNIT

V

V_{CC (PGM/ERASE)}Program and erase supply voltage

f_FTG

Flash timing generator frequency

Supply current from V_CCduring program

Supply current from V_CCduring erase

Cumulative program time⁽¹⁾

257

kHz

mA

I_PGM

2.2 V, 3.6 V

1

I_ERASE

t_CPT

7

mA

10

ms

t_CMErase

Cumulative mass erase time

20

10⁴

15

ms

Program/Erase endurance

10⁵

cycles

years

t_FTG

t_Retention

t_Word

Data retention duration

T_J= 25°C

(2)

Word or byte program time

30

25

(2)

t_{Block, 0}

Block program time for first byte or word

Block program time for each additional

byte or word

t_{Block, 1-63}

18

t_FTG

(2)

t_{Block, End}

t_{Mass Erase}

t_{Seg Erase}

Block program end-sequence wait time

Mass erase time

6

10593

4819

t_FTG

Segment erase time

(1) The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming

methods: individual word/byte write and block write modes.

(2) These values are hardwired into the flash controller's state machine (t_FTG= 1/f_FTG).

RAM

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

CPU halted

MIN

MAX UNIT

(1)

V_(RAMh)

RAM retention supply voltage

1.6

V

(1) This parameter defines the minimum supply voltage V_CCwhen the data in RAM remains unchanged. No program execution should

happen during this supply voltage condition.

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JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

0

TYP

MAX UNIT

f_SBW

Spy-Bi-Wire input frequency

Spy-Bi-Wire low clock pulse length

2.2 V, 3 V

20 MHz

t_SBW,Low

0.025

15

µs

Spy-Bi-Wire enable time

t_SBW,En

t_SBW,Ret

2.2 V, 3 V

1

µs

(TEST high to acceptance of first clock edge⁽¹⁾

)

Spy-Bi-Wire return to normal operation time

TCK input frequency⁽²⁾

2.2 V, 3 V

2.2 V

15

0

100

5

µs

MHz

f_TCK

3 V

0

10 MHz

90 kΩ

R_Internal

Internal pulldown resistance on TEST

2.2 V, 3 V

25

60

(1) Tools accessing the Spy-Bi-Wire interface need to wait for the maximum t_SBW,Entime after pulling the TEST/SBWCLK pin high before

applying the first SBWCLK clock edge.

(2) f_TCKmay be restricted to meet the timing requirements of the module selected.

JTAG Fuse⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Supply voltage during fuse-blow condition

Voltage level on TEST for fuse blow

Supply current into TEST during fuse blow

Time to blow fuse

TEST CONDITIONS

T_A= 25°C

MIN

2.5

6

MAX UNIT

V_CC(FB)

V_FB

V

7

100

1

V

I_FB

mA

ms

t_FB

(1) Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to

bypass mode.

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Application Information

Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger

Pad Logic

P1REN.x

DVSS

DVCC

0

1

P1DIR.x

0

1

Direction

0: Input

1: Output

0

1

P1OUT.x

Module X OUT

P1.0/TACLK/ADC10CLK

P1.1/TA0

P1.2/TA1

P1.3/TA2

P1SEL.x

P1IN.x

EN

D

Module X IN

P1IRQ.x

P1IE.x

EN

Q

Set

P1IFG.x

Interrupt

Edge

Select

P1SEL.x

P1IES.x

Table 16. Port P1 (P1.0 to P1.3) Pin Functions

CONTROL BITS/SIGNALS

PIN NAME (P1.x)

x

FUNCTION

P1DIR.x

P1SEL.x

P1.0⁽¹⁾

I: 0; O: 1

0

1

0

1

0

1

0

1

P1.0/TACLK/ADC10CLK

0

Timer_A3.TACLK

ADC10CLK

P1.1⁽¹⁾(I/O)

0

1

I: 0; O: 1

P1.1/TA0

P1.2/TA1

P1.3/TA2

1

2

3

Timer_A3.CCI0A

Timer_A3.TA0

P1.2⁽¹⁾(I/O)

0

1

I: 0; O: 1

Timer_A3.CCI1A

Timer_A3.TA1

P1.3⁽¹⁾(I/O)

0

1

I: 0; O: 1

Timer_A3.CCI2A

Timer_A3.TA2

0

1

(1) Default after reset (PUC/POR)

46

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Port P1 Pin Schematic: P1.4 to P1.6, Input/Output With Schmitt Trigger and In-System Access

Features

Pad Logic

P1REN.x

DVSS

DVCC

0

1

P1DIR.x

0

1

Direction

0: Input

1: Output

0

1

P1OUT.x

Module X OUT

P1.4/SMCLK/TCK

P1.5/TA0/TMS

P1.6/TA1/TDI

Bus

Keeper

P1SEL.x

P1IN.x

EN

D

Module X IN

P1IRQ.x

P1IE.x

EN

Q

Set

P1IFG.x

Interrupt

Edge

Select

P1SEL.x

P1IES.x

To JTAG

From JTAG

Table 17. Port P1 (P1.4 to P1.6) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P1.x)

x

FUNCTION

P1DIR.x

P1SEL.x

4-Wire JTAG

P1.4⁽²⁾(I/O)

SMCLK

I: 0; O: 1

0

1

X

0

1

X

0

1

X

0

1

0

1

0

1

P1.4/SMCLK/TCK

P1.5/TA0/TMS

4

1

TCK

X

P1.5⁽²⁾(I/O)

Timer_A3.TA0

TMS

P1.6⁽²⁾(I/O)

Timer_A3.TA1

TDI/TCLK⁽³⁾

I: 0; O: 1

5

6

1

X

I: 0; O: 1

P1.6/TA1/TDI/TCLK

(1) X = Don't care

1

X

(2) Default after reset (PUC/POR)

(3) Function controlled by JTAG

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Port P1 Pin Schematic: P1.7, Input/Output With Schmitt Trigger and In-System Access Features

Pad Logic

P1REN.7

DVSS

DVCC

0

1

P1DIR.7

0

1

Direction

0: Input

1: Output

0

1

P1OUT.7

Module X OUT

P1.7/TA2/TDO/TDI

Bus

Keeper

P1SEL.7

P1IN.7

EN

D

Module X IN

P1IRQ.7

P1IE.7

EN

Q

Set

P1IFG.7

Interrupt

Edge

Select

P1SEL.7

P1IES.7

To JTAG

From JTAG

From JTAG (TDO)

Table 18. Port P1 (P1.7) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P1.x)

x

FUNCTION

P1DIR.x

I: 0; O: 1

P1SEL.x

4-Wire JTAG

P1.7⁽²⁾(I/O)

0

1

0

1

P1.7/TA2/TDO/TDI

(1) X = Don't care

7

Timer_A3.TA2

TDO/TDI⁽³⁾

1

X

(2) Default after reset (PUC/POR)

(3) Function controlled by JTAG

48

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Port P2 Pin Schematic: P2.0, P2.2, Input/Output With Schmitt Trigger

Pad Logic

To ADC10

INCHx = y

ADC10AE0.y

P2REN.x

P2DIR.x

DVSS

DVCC

0

1

0

1

Direction

0: Input

1: Output

0

1

P2OUT.x

Module X OUT

P2.0/ACLK/A0

P2.2/TA0/A2

Bus

Keeper

P2SEL.x

P2IN.x

EN

D

Module X IN

P2IRQ.x

P2IE.x

EN

Q

Set

P2IFG.x

Interrupt

Edge

Select

P2SEL.x

P2IES.x

Table 19. Port P2 (P2.0, P2.2) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

Pin Name (P2.x)

x

y

FUNCTION

P2DIR.x

P2SEL.x

ADC10AE0.y

P2.0⁽²⁾(I/O)

ACLK

A0⁽³⁾

P2.2⁽²⁾(I/O)

Timer_A3.CCI0B

Timer_A3.TA0

A2⁽³⁾

I: 0; O: 1

0

1

X

0

1

X

0

1

0

1

P2.0/ACLK/A0

0

2

1

X

I: 0; O: 1

0

1

X

P2.2/TA0/A2

2

(1) X = Don't care

(2) Default after reset (PUC/POR)

(3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

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Port P2 Pin Schematic: P2.1, Input/Output With Schmitt Trigger

Pad Logic

To ADC10

INCHx = 1

ADC10AE0.1

P2REN.1

P2DIR.1

DVSS

DVCC

0

1

0

1

Direction

0: Input

1: Output

P2OUT.1

0

1

Module X OUT

P2.1/TAINCLK/SMCLK/A1

Bus

Keeper

P2SEL.1

P2IN.1

EN

D

Module X IN

P2IRQ.1

P2IE.1

EN

Q

Set

P2IFG.1

Interrupt

Edge

Select

P2SEL.1

P2IES.1

Table 20. Port P2 (P2.1) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P2.x)

x

y

FUNCTION

P2DIR.x

P2SEL.x

ADC10AE0.y

P2.1⁽²⁾(I/O)

Timer_A3.INCLK

SMCLK

I: 0; O: 1

0

1

X

0

1

0

1

X

P2.1/TAINCLK/SMCLK/

A1

1

A1⁽³⁾

(1) X = Don't care

(2) Default after reset (PUC/POR)

(3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

50

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Port P2 Pin Schematic: P2.3, Input/Output With Schmitt Trigger

SREF2

VSS

Pad Logic

0

1

To ADC10 V

R−

To ADC10

INCHx = 3

ADC10AE0.3

P2REN.3

P2DIR.3

DVSS

DVCC

0

1

0

1

Direction

0: Input

1: Output

0

1

P2OUT.3

Module X OUT

P2.3/TA1/

A3/VREF−/VeREF−

Bus

Keeper

P2SEL.3

P2IN.3

EN

D

Module X IN

P2IRQ.3

P2IE.3

EN

Q

Set

P2IFG.3

Interrupt

Edge

Select

P2SEL.3

P2IES.3

Table 21. Port P2 (P2.3) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P2.x)

x

y

FUNCTION

P2DIR.x

P2SEL.x

ADC10AE0.y

P2.3⁽²⁾(I/O)

I: 0; O: 1

0

1

X

0

1

Timer_A3.CCI1B

Timer_A3.TA1

0

1

X

P2.3/TA1/A3/V_REF-

/V_eREF-

3

(3)

A3/V_REF-/V_eREF-

(1) X = Don't care

(2) Default after reset (PUC/POR)

(3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

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Port P2 Pin Schematic: P2.4, Input/Output With Schmitt Trigger

Pad Logic

To/fromADC10

positive reference

To ADC10

INCHx = 4

ADC10AE0.4

P2REN.4

DVSS

DVCC

0

1

P2DIR.4

0

1

Direction

0: Input

1: Output

0

1

P2OUT.4

Module X OUT

P2.4/TA2/

A4/VREF+/VeREF+

Bus

Keeper

P2SEL.4

P2IN.4

EN

D

Module X IN

P2IRQ.4

P2IE.4

EN

Q

Set

P2IFG.4

Interrupt

Edge

Select

P2SEL.4

P2IES.4

Table 22. Port P2 (P2.4) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P2.x)

x

y

FUNCTION

P2DIR.x

P2SEL.x

ADC10AE0.y

P2.4⁽²⁾(I/O)

I: 0; O: 1

0

1

X

0

1

P2.4/TA2/A4/V_REF+

V_eREF+

/

4

Timer_A3.TA2

1

(3)

A4/V_REF+/V_eREF+

X

(1) X = Don't care

(2) Default after reset (PUC/POR)

(3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

52

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Port P2 Pin Schematic: P2.5, Input/Output With Schmitt Trigger and External R_OSCfor DCO

Pad Logic

To DCO

DCOR

P2REN.x

DVSS

DVCC

0

1

P2DIR.x

0

1

Direction

0: Input

1: Output

0

1

P2OUT.x

Module X OUT

P2.5/ROSC

Bus

Keeper

P2SEL.x

P2IN.x

EN

D

Module X IN

P2IRQ.x

P2IE.x

EN

Q

Set

P2IFG.x

Interrupt

Edge

Select

P2SEL.x

P2IES.x

Table 23. Port P2 (P2.5) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P2.x)

x

FUNCTION

P2DIR.x

I: 0; O: 1

P2SEL.x

DCOR

P2.5⁽²⁾(I/O)

N/A⁽³⁾

0

1

X

0

1

0

1

P2.5/R_OSC

5

DV_SS

R_OSC

X

(1) X = Don't care

(2) Default after reset (PUC/POR)

(3) N/A = Not available or not applicable

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Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger and Crystal Oscillator Input

BCSCTL3.LFXT1Sx = 11

LFXT1 Oscillator

P2.7/XOUT

LFXT1 off

0

1

LFXT1CLK

Pad Logic

P2SEL.7

P2REN.6

DVSS

0

1

DVCC

P2DIR.6

0

1

Direction

0: Input

1: Output

0

1

P2OUT.6

Module X OUT

P2.6/XIN

Bus

Keeper

P2SEL.6

P2IN.6

EN

D

Module X IN

P2IRQ.6

P2IE.6

EN

Set

Q

P2IFG.6

P2SEL.6

Interrupt

Edge

Select

P2IES.6

Table 24. Port P2 (P2.6) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P2.x)

x

FUNCTION

P2DIR.x

I: 0; O: 1

X

P2SEL.x

P2.6 (I/O)

XIN⁽²⁾

0

1

P2.6/XIN

6

(1) X = Don't care

(2) Default after reset (PUC/POR)

54

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Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger and Crystal Oscillator Output

BCSCTL3.LFXT1Sx = 11

LFXT1 Oscillator

LFXT1 off

0

1

LFXT1CLK

From P2.6/XIN

P2.6/XIN

Pad Logic

P2SEL.6

P2REN.7

DVSS

0

1

DVCC

P2DIR.7

0

1

Direction

0: Input

1: Output

0

1

P2OUT.7

Module X OUT

P2.7/XOUT

Bus

Keeper

P2SEL.7

P2IN.7

EN

D

Module X IN

P2IRQ.7

P2IE.7

EN

Set

Q

P2IFG.7

P2SEL.7

Interrupt

Edge

Select

P2IES.7

Table 25. Port P2 (P2.7) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P2.x)

x

FUNCTION

P2DIR.x

I: 0; O: 1

X

P2SEL.x

P2.7 (I/O)

XOUT^{(2) (3)}

0

1

XOUT/P2.7

7

(1) X = Don't care

(2) Default after reset (PUC/POR)

(3) If the pin XOUT/P2.7 is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection to this

pin after reset.

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Port P3 Pin Schematic: P3.0, Input/Output With Schmitt Trigger

Pad Logic

To ADC10

INCHx = 5

ADC10AE0.5

P3REN.0

DVSS

DVCC

0

1

P3DIR.0

0

1

Direction

0: Input

1: Output

USCI Direction

Control

0

1

P3OUT.0

Module X OUT

P3.0/UCB0STE/UCA0CLK/A5

Bus

Keeper

P3SEL.0

P3IN.0

EN

D

Module X IN

Table 26. Port P3 (P3.0) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P1.x)

x

y

FUNCTION

P3DIR.x

I: 0; O: 1

P3SEL.x

ADC10AE0.y

P3.0⁽²⁾(I/O)

0

1

X

0

1

P3.0/UCB0STE/

UCA0CLK/A5

0

5

UCB0STE/UCA0CLK^{(3) (4)}

A5⁽⁵⁾

X

(1) X = Don't care

(2) Default after reset (PUC/POR)

(3) The pin direction is controlled by the USCI module.

(4) UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI_B0 is forced to

3-wire SPI mode if 4-wire SPI mode is selected.

(5) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

56

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Port P3 Pin Schematic: P3.1 to P3.5, Input/Output With Schmitt Trigger

Pad Logic

DVSS

P3REN.x

DVSS

DVCC

0

1

P3DIR.x

0

1

Direction

0: Input

1: Output

USCI Direction

Control

0

1

P3OUT.x

Module X OUT

P3.1/UCB0SIMO/UCB0SDA

P3.2/UCB0SOMI/UCB0SCL

P3.3/UCB0CLK/UCA0STE

P3.4/UCA0TXD/UCA0SIMO

P3.5/UCA0RXD/UCA0SOMI

Bus

Keeper

P3SEL.x

P3IN.x

EN

D

Module X IN

Table 27. Port P3 (P3.1 to P3.5) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P3.x)

P3.1/UCB0SIMO/UCB0SDA

P3.2/UCB0SOMI/UCB0SCL

P3.3/UCB0CLK/UCA0STE

P3.4/UCA0TXD/UCA0SIMO

x

1

2

3

4

5

FUNCTION

P3DIR.x

P3SEL.x

P3.1⁽²⁾(I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

UCB0SIMO/UCB0SDA⁽³⁾

P3.2⁽²⁾(I/O)

X

I: 0; O: 1

UCB0SOMI/UCB0SCL⁽³⁾

P3.3⁽²⁾(I/O)

X

I: 0; O: 1

UCB0CLK/UCA0STE^{(3) (4)}

P3.4⁽²⁾(I/O)

X

I: 0; O: 1

X

UCA0TXD/UCA0SIMO⁽³⁾

P3.5⁽²⁾(I/O)

I: 0; O: 1

X

P3.5/UCA0RXD/UCA0SOMI

(1) X = Don't care

UCA0RXD/UCA0SOMI⁽³⁾

(2) Default after reset (PUC/POR)

(3) The pin direction is controlled by the USCI module.

(4) UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI_A0 is forced to

3-wire SPI mode even if 4-wire SPI mode is selected.

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Port P3 Pin Schematic: P3.6 to P3.7, Input/Output With Schmitt Trigger

Pad Logic

To ADC10

INCHx = y

ADC10AE0.y

P3REN.x

DVSS

DVCC

0

1

P3DIR.x

0

1

Direction

0: Input

1: Output

DVSS

0

1

P3OUT.x

Module X OUT

P3.6/A6

P3.7/A7

Bus

Keeper

P3SEL.x

P3IN.x

EN

D

Module X IN

Table 28. Port P3 (P3.6, P3.7) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P3.x)

x

y

6

7

FUNCTION

P3DIR.x

P3SEL.x

ADC10AE0.y

P3.6⁽²⁾(I/O)

A6⁽³⁾

P3.7⁽²⁾(I/O)

A7⁽³⁾

I: 0; O: 1

0

X

0

1

0

1

P3.6/A6

6

7

X

I: 0; O: 1

X

P3.7/A7

X

(1) X = Don't care

(2) Default after reset (PUC/POR)

(3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

58

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Port P4 Pin Schematic: P4.0 to P4.2, Input/Output With Schmitt Trigger

Timer_B OutputTristate Logic

P4.6/TBOUTH/A15

P4SEL.6

Pad Logic

P4DIR.6

ADC10AE1.7

P4REN.x

DVSS

DVCC

0

1

P4DIR.x

0

1

Direction

0: Input

1: Output

0

1

P4OUT.x

Module X OUT

P4.0/TB0

P4.1/TB1

P4.2/TB2

Bus

Keeper

P4SEL.x

P4IN.x

EN

D

Module X IN

Table 29. Port P4 (P4.0 to P4.2) Pin Functions

CONTROL BITS/SIGNALS

PIN NAME (P4.x)

x

FUNCTION

P4DIR.x

P4SEL.x

P4.0⁽¹⁾(I/O)

I: 0; O: 1

0

1

0

1

0

1

P4.0/TB0

0

Timer_B3.CCI0A

Timer_B3.TB0

P4.1⁽¹⁾(I/O)

0

1

I: 0; O: 1

P4.1/TB1

P4.2/TB2

1

2

Timer_B3.CCI1A

Timer_B3.TB1

P4.2⁽¹⁾(I/O)

0

1

I: 0; O: 1

Timer_B3.CCI2A

Timer_B3.TB2

0

1

(1) Default after reset (PUC/POR)

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Port P4 Pin Schematic: P4.3 to P4.4, Input/Output With Schmitt Trigger

Timer_B OutputTristate Logic

P4.6/TBOUTH/A15

P4SEL.6

P4DIR.6

ADC10AE1.7

Pad Logic

To ADC10

†

INCHx = 8+y

ADC10AE1.y

P4REN.x

DVSS

DVCC

0

1

P4DIR.x

0

1

Direction

0: Input

1: Output

P4OUT.x

0

1

Module X OUT

P4.3/TB0/A12

P4.4/TB1/A13

Bus

Keeper

P4SEL.x

P4IN.x

EN

D

Module X IN

60

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SLAS824 –DECEMBER 2013

Table 30. Port P4 (P4.3 to P4.4) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P4.x)

x

y

FUNCTION

P4DIR.x

P4SEL.x

ADC10AE1.y

P4.3⁽²⁾(I/O)

Timer_B3.CCI0B

Timer_B3.TB0

A12⁽³⁾

P4.4⁽²⁾(I/O)

Timer_B3.CCI1B

Timer_B3.TB1

A13⁽³⁾

I: 0; O: 1

0

1

X

0

1

X

0

1

0

1

0

P4.3/TB0/A12

3

4

1

X

I: 0; O: 1

0

1

X

P4.4/TB1/A13

4

5

(1) X = Don't care

(2) Default after reset (PUC/POR)

(3) Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

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SLAS824 –DECEMBER 2013

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Port P4 Pin Schematic: P4.5, Input/Output With Schmitt Trigger

Timer_B OutputTristate Logic

P4.6/TBOUTH/A15

P4SEL.6

P4DIR.6

ADC10AE1.7

Pad Logic

To ADC10

INCHx = 14

ADC10AE1.6

P4REN.5

DVSS

DVCC

0

1

P4DIR.5

0

1

Direction

0: Input

1: Output

P4OUT.5

0

1

Module X OUT

P4.5/TB3/A14

Bus

Keeper

P4SEL.5

P4IN.5

EN

D

Module X IN

Table 31. Port P4 (P4.5) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P4.x)

x

y

FUNCTION

P4DIR.x

P4SEL.x

ADC10AE1.y

P4.5⁽²⁾(I/O)

Timer_B3.TB2

A14⁽³⁾

I: 0; O: 1

0

1

X

0

1

P4.5/TB3/A14

5

6

1

X

(1) X = Don't care

(2) Default after reset (PUC/POR)

(3) Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

62

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SLAS824 –DECEMBER 2013

Port P4 Pin Schematic: P4.6, Input/Output With Schmitt Trigger

Pad Logic

To ADC10

INCHx = 15

ADC10AE1.7

P4REN.6

DVSS

DVCC

0

1

P4DIR.6

0

1

Direction

0: Input

1: Output

0

1

P4OUT.6

Module X OUT

P4.6/TBOUTH/A15

Bus

Keeper

P4SEL.6

P4IN.6

EN

D

Module X IN

Table 32. Port P4 (P4.6) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P4.x)

x

y

FUNCTION

P4DIR.x

P4SEL.x

ADC10AE1.y

P4.6⁽²⁾(I/O)

TBOUTH

DV_SS

I: 0; O: 1

0

1

X

0

1

0

1

P4.6/TBOUTH/A15

6

7

A15⁽³⁾

X

(1) X = Don't care

(2) Default after reset (PUC/POR)

(3) Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

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Port P4 Pin Schematic: P4.7, Input/Output With Schmitt Trigger

Pad Logic

DVSS

P4REN.x

DVSS

DVCC

0

1

P4DIR.x

0

1

Direction

0: Input

1: Output

0

1

P4OUT.x

Module X OUT

P4.7/TBCLK

Bus

Keeper

P4SEL.x

P4IN.x

EN

D

Module X IN

Table 33. Port P4 (Pr.7) Pin Functions

CONTROL BITS/SIGNALS

PIN NAME (P4.x)

x

FUNCTION

P4DIR.x

P4SEL.x

P4.7⁽¹⁾(I/O)

I: 0; O: 1

0

1

P4.7/TBCLK

7

Timer_B3.TBCLK

DV_SS

0

1

(1) Default after reset (PUC/POR)

64

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SLAS824 –DECEMBER 2013

JTAG Fuse Check Mode

NN325-Q1 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of

the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check

current, I_TF, of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care

must be taken to avoid accidentally activating the fuse check mode and increasing overall system power

consumption.

When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense

currents are terminated.

Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is

being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode.

After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse

check mode has the potential to be activated.

The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state (see

Figure 25). Therefore, the additional current flow can be prevented by holding the TMS pin high (default

condition).

Time TMS Goes Low After POR

TMS

I

TF

I

TEST

Figure 25. Fuse Check Mode Current

NOTE

The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit

bootloader access key is used. Also, see the Bootstrap Loader section for more

information.

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GENERIC PACKAGE VIEW

RHA 40

6 x 6, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225870/A

www.ti.com

PACKAGE OUTLINE

RHA0040B

VQFN - 1 mm max height

S

C

A

L

E

2

.

2

0

PLASTIC QUAD FLATPACK - NO LEAD

6.1

5.9

B

A

PIN 1 INDEX AREA

6.1

5.9

1 MAX

C

SEATING PLANE

0.08

0.05

0.00

2X 4.5

4.15 0.1

(0.2) TYP

11

20

36X 0.5

10

21

EXPOSED

THERMAL PAD

2X

4.5

SYMM

41

30

0.27

40X

1

0.17

PIN 1 ID

(OPTIONAL)

0.1

C A B

40

31

SYMM

0.05

0.5

0.3

40X

4219052/A 06/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RHA0040B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

4.15)

SYMM

40X (0.6)

40X (0.22)

40

31

1

30

(0.25) TYP

36X (0.5)

SYMM

41

(5.8)

(0.685)

TYP

(1.14)

TYP

(

0.2) TYP

VIA

10

21

(R0.05) TYP

20

11

(0.685)

TYP

(1.14)

TYP

(5.8)

LAND PATTERN EXAMPLE

SCALE:12X

0.07 MIN

ALL SIDES

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219052/A 06/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RHA0040B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

9X ( 1.17)

(1.37) TYP

40X (0.6)

40X (0.22)

31

40

1

30

41

(1.37)

TYP

(0.25) TYP

SYMM

(5.8)

36X (0.5)

(R0.05) TYP

10

21

11

20

METAL

TYP

SYMM

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 41:

72% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:12X

4219052/A 06/2016

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	NN325-Q1
厂家：	TEXAS INSTRUMENTS
描述：	多感应触摸管理器
文件：	总73页 (文件大小：1870K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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