O917A186TRGZRQ1 [TI]
具有 5 个降压转换器和 5 个 LDO 的汽车类 3.15V 至 5.25V 电源管理 IC (PMIC) | RGZ | 48 | -40 to 105;型号: | O917A186TRGZRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 5 个降压转换器和 5 个 LDO 的汽车类 3.15V 至 5.25V 电源管理 IC (PMIC) | RGZ | 48 | -40 to 105 集成电源管理电路 转换器 |
文件: | 总94页 (文件大小:2474K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TPS65917-Q1
ZHCSGJ3D –JULY 2015–REVISED FEBRUARY 2019
TPS65917-Q1 适用于处理器的电源管理单元 (PMU)
1 器件概述
1.1 特性
1
部时钟保持同步
• 五个低压降 (LDO) 线性稳压器:
• 符合汽车应用 应用
• 具有符合 AEC-Q100 标准的下列结果:
– 输出电压范围为 0.9V 至 3.3V(步长为 50mV)
– 其中两个稳压器具备 300mA 电流性能以及旁路
模式
– 器件温度 2 级:-40℃ 至 +105℃ 的环境运行温
度范围
– 器件人体放电模型 (HBM) 分类等级 2
– 器件充电器件模型 (CDM) 分类等级 C4B
• 系统电压范围为 3.135V 至 5.25V
• 低功耗
– 一个稳压器具备 100mA 电流性能以及最高可达
50mA 的低噪声性能
– 其他两个 LDO 具有 200mA 电流性能
– 短路保护功能
– 断电模式下为 20μA
– 休眠模式下(两个 SMPS 处于激活状态)为
90μA
• 具有 8 条输入通道(2 条为外部通道)的 12 位 ∑-Δ
通用模数转换器 (ADC) (GPADC)
• 具有高温报警和热关断功能的温度监控
• 电源序列控制:
– 可配置加电和断电序列 (OTP)
– 休眠和激活状态转换之间的可配置序列 (OTP)
– 三个数字输出信号可添加至启动序列
• 可选控制接口:
• 五个降压开关模式电源 (SMPS) 稳压器:
– 输出电压范围为 0.7V 至 3.3V(步长为 10mV 或
20mV)
– 其中两个 SMPS 稳压器具备 3.5A 电流性能、在
双相配置中结合 7A 输出的能力以及差分远程感
测(输出和接地)
– 其他三个 SMPS 稳压器分别具有 3A、2A 和
1.5A 电流性能
– 3.5A 和 3A SMPS 稳压器具备动态电压调节
(DVS) 控制和输出电流测量功能
– 硬件和软件受控的 Eco-mode™最高可提供 5mA
电流
– 一个用于资源配置和 DVS 控制的串行外设接口
(SPI)
– 两个 I2C 接口。
– 其中一个专用于 DVS 控制
– 另一个用作资源配置和 DVS 控制的通用 I2C
接口
– 短路保护功能
• 带有运行或保持加电序列以及 RESET_OUT 释放选
项的 OTP 位完整性错误检测
• 封装选项:
– 电源正常指示(电压和过流指示)
– 用于限制浪涌电流的内部软启动
– 能够与频率介于 1.7MHz 至 2.7MHz 范围内的外
– 7mm × 7mm 48 引脚 VQFN,间距为 0.5mm
1.2 应用
•
•
汽车数字集群
•
汽车导航系统
汽车高级驾驶员辅助系统 (ADAS)
1.3 说明
该TPS65917-Q1 PMIC 将五个可配置降压转换器与高达 3.5A 的输出电流相集成,从而为 LDO 的处理器内
核、存储器、I/O 以及预稳压电路供电该器件符合 AEC-Q100 标准。 降压转换器与 2.2MHz 内部时钟同
步,可提升器件的 EMC 性能。GPIO_3 引脚允许降压转换器与外部时钟同步,支持多个器件与同一时钟同
步,从而提升系统级 EMC 性能。该器件还包含五个 LDO,用于为低电流或低噪声域供电。
电源序列控制器采用一次性可编程 (OTP) 存储器控制电源序列,同时采用默认配置,例如输出电压和通用输
入/输出 (GPIO) 配置。OTP 经过出厂编程,无需使用软件即可启动。多数默认静态设置可通过 SPI 或 I2C
进行更改,从而根据多种不同系统需求配置器件。例如,电压调节寄存器用于支持处理器的动态电压调节要
求。对于另一项安全功能,OTP 还具备比特完整性错误检测功能,可在检测到错误时停止上电序列,防止系
统在未知状态下启动。
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLVSCO4
TPS65917-Q1
ZHCSGJ3D –JULY 2015–REVISED FEBRUARY 2019
www.ti.com.cn
TPS65917-Q1 器件还具有一个监控系统状态的模数转换器 (ADC)。GPADC 包括两条监控所有外部电压的
外部通道,以及多条测量电源电压、输出电流和芯片温度的内部通道,允许处理器监控系统健康状况。该器
件提供看门狗监控软件锁定情况并提供保护和诊断机制,例如短路保护、热监控、关断和自动 ADC 转换,
以便检测电压是否低于预定义阈值。PMIC 可通过中断处理程序向处理器报告这些事件,以便处理器采取相
关措施进行响应。
器件信息(1)
封装
器件型号
封装尺寸(标称值)
7.00mm × 7.00mm
TPS65917-Q1
VQFN (48)
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附录。
2
器件概述
版权 © 2015–2019, Texas Instruments Incorporated
TPS65917-Q1
www.ti.com.cn
ZHCSGJ3D –JULY 2015–REVISED FEBRUARY 2019
1.4 功能图
VCCA
VCCA
I2C and SPI
VSYS Monitor
VCC_SENSE
PWRON
INT
First Supply Detection
32-kHz RC Oscillator
SYNCCLKOUT
Interrupt Handler
Bandgap
REFSYS
VBG
1.23-V
Vref
RC15M
÷6
PWRDOWN
POWERHOLD
RESET_IN
Event Handler
OSC
SYNCDCDC
PLL
REFGND
BBS
NSLEEP
OFF2ACT
ACT2OFF
ACT2SLP
SLP2ACT
Watchdog Timer
NRESWARM
OSC + PLL
Independent Bandgap
LDOVRTC
I2C/SPI
NRESWARM
OTP
LDOVRTC_OUT
SMPS1_IN
SMPS1
Power
Sequencer
VIN Monitor,
Thermal SD,
Short Circuit Monitor
SMPS1_FDBK
CRC
Registers
LDO1, Bypass
LDO1_OUT
LDO12_IN
LDO2_OUT
Short Circuit Monitor
Dual Phase or
Single Phase
VCCA
LDO2, Bypass
Thermal
Monitor
SMPS2_IN
Short Circuit Monitor
SMPS2
Resource Controller
VIN Monitor,
Thermal SD,
Short Circuit Monitor
SMPS/LDO
POWERGOOD/SHORT/
VINLOW
SMPS2_FDBK
LDO3
LDO3_IN
Short Circuit Monitor
LDO3_OUT
I2C and SPI
SMPS3_IN
SMPS3
GPADC Controller
LDO4
LDO4_IN
CNTRL
Registers
VIN Monitor,
Thermal SD,
Short Circuit Monitor
Short Circuit Monitor
SMPS3_FDBK
LDO4_OUT
LDO5, LN
LDO5_IN
SMPS4_IN
Short Circuit Monitor
SMPS4
LDO5_OUT
VIN Monitor,
Short Circuit Monitor
SMPS4_FDBK
I2C and SPI
I/O
12-Bit GPADC
LDOVANA
LDOVANA_OUT
VCC_SENSE
SMPS5_IN
SMPS5
7x GPIO
VIN Monitor,
Thermal SD,
SMPS5_FDBK
Short Circuit Monitor
POWERGOOD
POWERGOOD Monitor
VIO
VIO_IN
图 1-1. 功能图
版权 © 2015–2019, Texas Instruments Incorporated
器件概述
3
TPS65917-Q1
ZHCSGJ3D –JULY 2015–REVISED FEBRUARY 2019
www.ti.com.cn
内容
4.23 Switching Characteristics — Reference Generator
1
器件概述.................................................... 1
1.1 特性 ................................................... 1
1.2 应用 ................................................... 1
1.3 说明 ................................................... 1
1.4 功能图 ................................................ 3
修订历史记录............................................... 5
Pin Configuration and Functions..................... 6
3.1 Pin Attributes ......................................... 6
3.2 Signal Descriptions ................................... 9
Specifications ........................................... 12
4.1 Absolute Maximum Ratings......................... 12
4.2 ESD Ratings ........................................ 12
4.3 Recommended Operating Conditions............... 12
4.4 Thermal Information................................. 13
(Bandgap) ........................................... 23
4.24 Switching Characteristics — PLL for SMPS Clock
Generation .......................................... 23
4.25 Switching Characteristics — 32-kHz RC Oscillators
and SYNCCLKOUT Output Buffers................. 23
4.26 Switching Characteristics — 12-Bit Sigma-Delta
ADC ................................................. 24
2
3
4.27 Typical Characteristics .............................. 26
Detailed Description ................................... 29
5.1 Overview ............................................ 29
5.2 Functional Block Diagram........................... 30
5.3 Device State Machine ............................... 31
5
4
5.4
Power Resources (Step-Down and Step-Up SMPS
Regulators, LDOs) .................................. 41
SMPS and LDO Input Supply Connections ........ 50
5.5
4.5
Electrical Characteristics — LDO Regulators....... 13
5.6 First Supply Detection .............................. 50
5.7 Long-Press Key Detection .......................... 51
4.6
Electrical Characteristics — SMPS1&2 in Dual-
Phase Configuration ................................ 15
Electrical Characteristics — SMPS1, SMPS2,
SMPS3, SMPS4, and SMPS5 Stand-Alone
5.8
12-Bit Sigma-Delta General-Purpose ADC
4.7
(GPADC) ............................................ 51
Regulators........................................... 16
5.9 General-Purpose I/Os (GPIO Pins) ................. 55
5.10 Thermal Monitoring.................................. 56
5.11 Interrupts ........................................... 57
5.12 Control Interfaces ................................... 60
5.13 OTP Configuration Memory ........................ 65
5.14 Watchdog Timer (WDT) ............................ 65
5.15 System Voltage Monitoring ......................... 66
5.16 Register Map ........................................ 69
5.17 Device Identification................................. 69
Applications, Implementation, and Layout........ 70
6.1 Application Information.............................. 70
6.2 Typical Application .................................. 71
6.3 Layout ............................................... 79
4.8
4.9
Electrical Characteristics — Reference Generator
(Bandgap) ........................................... 17
Electrical Characteristics — 32-kHz RC Oscillators
and SYNCCLKOUT Output Buffers................. 17
4.10 Electrical Characteristics — 12-Bit Sigma-Delta
ADC ................................................. 18
4.11 Electrical Characteristics — Thermal Monitoring and
Shutdown............................................ 18
4.12 Electrical Characteristics — System Control
Thresholds .......................................... 19
4.13 Electrical Characteristics — Current Consumption . 19
4.14 Electrical Characteristics — Digital Input Signal
Parameters .......................................... 19
4.15 Electrical Characteristics — Digital Output Signal
Parameters .......................................... 20
6
7
6.4
Power Supply Coupling and Bulk Capacitors....... 82
4.16 I/O Pullup and Pulldown Characteristics............ 20
4.17 Electrical Characteristics — I2C Interface........... 20
4.18 Timing Requirements — I2C Interface .............. 21
4.19 Timing Requirements — SPI ....................... 22
4.20 Switching Characteristics — LDO Regulators ...... 22
器件和文档支持 .......................................... 83
7.1 器件支持............................................. 83
7.2 文档支持............................................. 83
7.3 接收文档更新通知 ................................... 84
7.4 社区资源............................................. 84
7.5 商标.................................................. 84
7.6 静电放电警告 ........................................ 84
7.7 Glossary ............................................. 84
机械、封装和可订购信息................................ 84
4.21 Switching Characteristics — SMPS1&2 in Dual-
Phase Configuration ................................ 22
4.22 Switching Characteristics — SMPS1, SMPS2,
SMPS3, SMPS4, and SMPS5 Stand-Alone
8
Regulators........................................... 23
4
内容
版权 © 2015–2019, Texas Instruments Incorporated
TPS65917-Q1
www.ti.com.cn
ZHCSGJ3D –JULY 2015–REVISED FEBRUARY 2019
2 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Revision C (March 2017) to Revision D
Page
•
•
Added footnote recommending not to pull open-drain GPIOs up to an always-on voltage domain ....................... 9
Clarified that LDO1 and LDO2 input pins are not included in this minimum recommended operating voltage. See
Electrical Characteristics: LDO Regulators for more information. ............................................................ 12
Added LDO and SMPS output capacitance footnote........................................................................... 13
Added SMPS Output voltage slew rate description ............................................................................ 15
已更改 the comparison condition from VCCA to VCC_SENSE in the Embedded Power Controller section ........... 32
Added typical debounce time from POWERHOLD to the enable of the first rail in the power sequence. .............. 33
Changed discharge resistance to match electrical characteristics table..................................................... 42
Changed description of clock dithering from internal to external only........................................................ 44
Added information about shutdown timing during short circuit detection .................................................... 45
Updated POWERGOOD block diagram and description to clarify dual phase operation. ................................ 46
已添加 notes to the SMPS Controls for DVS image............................................................................ 48
已添加 the equation to convert GPADC code to internal die temperature in the 12-Bit Sigma-Delta General-
Purpose ADC (GPADC) section................................................................................................... 52
Additional description of VSYS_LO functionality ............................................................................... 66
Added details on identifying device version. .................................................................................... 69
SMPS and LDO output capacitance specification further explained ......................................................... 74
Added design considerations for VCCA capacitance to support loss of power............................................. 74
Corrected 9-Vpp with 7V absolute maximum specification in the Layout Guidelines section............................. 79
Updated requirements relating to measurement of high-side and low-side FETs in the Layout Guidelines section... 80
Updated images and description on differential measurements across high-side and low-side FETs .................. 81
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Changes from Revision B (November 2015) to Revision C
Page
•
•
•
•
首次公开发布的完整数据表.......................................................................................................... 1
Added recommendation for external pulldown resistor on the LDOVRTC_OUT pin in the Pin Attributes table ......... 7
Added OTP to the PU/PD selection for GPIO_1 as NRESWARM in the Signal Descriptions table ...................... 9
已更改 the caption of the SMPS Efficiency For SMPS1 and SMPS 2 in Dual-Phase PWM Mode graph to SMPS
Load Regulation for SMPS1 and SMPS2 Single-Phase PWM Mode in the Typical Characteristics section ........... 26
已添加 the SMPS Load regulation for SMPS3, PWM Mode graph to the Typical Characteristics section.............. 26
已更改 single-phase to dual-phase and increased the output current to 7 A in the SMPS Load Regulation for
SMPS12 graph in the Typical Characteristics section.......................................................................... 26
已更改 the debounce for PWRON to N/A in the ON Requests table......................................................... 33
已添加 description of VIO power-up timing in the Device Power Up Timing section....................................... 37
已更改 the description of the LDOVRTC when in the BACKUP and OFF states and added a note in the
•
•
•
•
•
LDOVRTC section .................................................................................................................. 50
已添加 the note and pulldown equations to the System Voltage Monitoring section....................................... 67
已更改 the SMPS1 voltage, SMPS2 voltage, and LDO2 voltage in the Design Parameters table ...................... 72
已更改 静电放电注意事项声明..................................................................................................... 84
•
•
•
Changes from Revision A (November 2015) to Revision B
已添加 statement to the Current Monitoring and Short Circuit Detection section that the
Page
•
SMPS_SHORT_REGISTER bit will keep a resource off until it is cleared ................................................. 45
Changes from Original (July 2015) to Revision A
Page
•
Deleted the PPU type and changed the connection from floating to VRTC for the GPIO_1 pin when used only as
an input with the secondary function as NRESWARM .......................................................................... 7
Updated Max value of Device Off Mode Current Consumption from 45 µA to 55 µA ..................................... 19
已更改 the units for the x axis from mA to A in graphs D002 to D008 in the Typical Characteristics section .......... 26
Added register names for the GPADC channel 3 D1 & D2 trim when HIGH_VCC_SENSE = 1 ......................... 55
•
•
•
Copyright © 2015–2019, Texas Instruments Incorporated
修订历史记录
5
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Product Folder Links: TPS65917-Q1
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www.ti.com.cn
3 Pin Configuration and Functions
Figure 3-1 shows the 48-pin RGZ plastic quad-flatpack no-lead (VQFN) pin assignments and thermal pad.
GPIO_4
GPIO_2
1
2
36
35
34
33
32
31
30
29
28
27
26
25
I2C1_SDA_SDI
I2C1_SCL_SCK
VIO_IN
LDO5_IN
3
LDO5_OUT
LDO3_IN
4
SMPS1_FDBK
SMPS1_IN
SMPS1_SW
SMPS2_SW
SMPS2_IN
SMPS2_FDBK
GPIO6
5
LDO3_OUT
LDO4_OUT
LDO4_IN
6
Thermal Pad
(PGND)
7
8
SMPS3_FDBK
SMPS3_IN
SMPS3_SW
GPIO_0
9
10
11
12
INT
RESET_OUT
Figure 3-1. 48-Pin RGZ (VQFN) Package, 0.5-mm Pitch,
With Thermal Pad (Top View)
3.1 Pin Attributes
Pin Attributes
PIN
CONNECTION
IF NOT USED
I/O
DESCRIPTION
PU/PD(1)
NAME
NO.
REFERENCE
REFGND
VBG
41
40
—
O
System reference ground
Ground
—
—
—
Bandgap reference voltage
STEP-DOWN CONVERTERS (SMPSs)
SMPS1_IN
32
I
Power input for SMPS1
System supply
Ground
—
—
Output voltage-sense (feedback) input for SMPS1 or
differential voltage-sense (feedback) positive input for SMPS12
in dual-phase configuration
SMPS1_FDBK
33
I
SMPS1_SW
SMPS2_IN
31
29
O
I
Switch node of SMPS1; connect output inductor
Power input for SMPS2
Floating
—
—
System supply
Output voltage-sense (feedback) input for SMPS2 or
differential voltage-sense (feedback) negative input for
SMPS12 in dual-phase configuration
SMPS2_FDBK
28
I
Ground
—
SMPS2_SW
SMPS3_IN
30
10
9
O
I
Switch node of SMPS2; connect output inductor
Power input for SMPS3
Floating
System supply
Floating
—
—
—
—
—
SMPS3_FDBK
SMPS3_SW
SMPS4_IN
I
Output voltage-sense (feedback) input for SMPS3
Switch node of SMPS3; connect output inductor
Power input for SMPS4
11
18
O
I
Floating
System supply
(1) The PU/PD column shows the pullup and pulldown resistors on the digital input lines. Pullup and pulldown resistors: PU = Pullup, PD =
Pulldown, PPU = Software-programmable pullup, PPD = Software-programmable pulldown.
6
Pin Configuration and Functions
Copyright © 2015–2019, Texas Instruments Incorporated
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ZHCSGJ3D –JULY 2015–REVISED FEBRUARY 2019
Pin Attributes (continued)
PIN
CONNECTION
PU/PD(1)
I/O
DESCRIPTION
IF NOT USED
NAME
NO.
17
19
46
45
47
SMPS4_FDBK
SMPS4_SW
SMPS5_IN
I
O
I
Output voltage-sense (feedback) input for SMPS4
Switch node of SMPS4; connect output inductor
Power input for SMPS5
Ground
Floating
—
—
—
—
—
System supply
Ground
SMPS5_FDBK
SMPS5_SW
I
Output voltage-sense (feedback) input for SMPS5
Switch node of SMPS5; connect output inductor
O
Floating
LOW-DROPOUT REGULATORS
LDO12_IN
LDO1_OUT
LDO2_OUT
LDO3_IN
22
23
21
5
I
Power input voltage for LDO1 and LDO2 regulators
LDO1 output voltage
System supply
Floating
—
—
—
—
—
—
—
—
—
O
O
I
LDO2 output voltage
Floating
Power input voltage for LDO3 regulator
LDO3 output voltage
System supply
Floating
LDO3_OUT
LDO4_IN
6
O
I
8
Power input voltage for LDO4 regulator
LDO4 output voltage
System supply
Floating
LDO4_OUT
LDO5_IN
7
O
I
3
Power input voltage for LDO5 regulator
LDO5 output voltage
System supply
Floating
LDO5_OUT
4
O
LOW-DROPOUT REGULATORS (INTERNAL)
LDOVRTC output voltage. To support rapid power off and on,
LDOVRTC_OUT
44
43
O
O
connect a pulldown resistor on the LDOVRTC_OUT pin. See
节 5.15 for more details.
—
—
—
—
LDOVANA_OUT
GPADC
LDOVANA output voltage
ADCIN1
38
39
I
I
GPADC input 1
GPADC input 2
Ground
Ground
—
—
ADCIN2
CLOCKING
Primary function: 2.2-MHz fallback switching frequency for
SMPS
SYNCCLKOUT
48
16
O
Floating
—
Secondary function: 32-kHz digital-gated output clock when
VIO_IN input supply is present
SYSTEM CONTROL
Ground or
VRTC
BOOT
I
Boot ball for power-up sequence selection
—
Ground or
VRTC
I/O
Primary function: General-purpose input(2) and output
PPD
Secondary function: ENABLE2 which is the peripheral power
request input 2
Floating
Ground or VIO
Floating
PPD(2)
PPD
—
GPIO_0
GPIO_1
12
I
Secondary function: PWRDOWN input
Secondary function: REGEN1 which is the external regulator
enable output 1
Primary function: General-purpose input(2) and output
Secondary function: RESET_IN which is the reset input
Secondary function: VBUS_SENSE input
O
I/O
Floating
Floating
PPD
PPD
—
13
Ground or VIO
I
Secondary function: NRESWARM which is the warm reset
input
VRTC
Floating
Floating
PPD
PPU
PPD
I/O
I
Primary function: General-purpose input(2) and output
Secondary function: ENABLE1 which is the peripheral power
request input 1
PPU
GPIO_2
2
PPD(2)
Secondary function: I2C2_SDA_SDO which is the DVS I2C
serial bidirectional data (external pullup) and the SPI output
data signal
I/O
Floating
—
(2) Default option.
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Pin Attributes (continued)
PIN
CONNECTION
IF NOT USED
I/O
DESCRIPTION
PU/PD(1)
NAME
NO.
I/O
O
Primary function: General-purpose input(2) and output
Floating
Floating
PPD
—
Secondary function: REGEN1 which is the external regulator
enable output 1
GPIO_3
14
Secondary function: ENABLE2 which is the peripheral power
request input 2
I
I
PPD(2)
PPD(2)
Secondary function: SYNCDCDC which is the synchronization
signal for SMPS switching
Floating
Floating
Floating
Floating
PPU
PPD
I/O
O
I
Primary function: General-purpose input(2) and output
Secondary function: REGEN2 which is the external regulator
enable output 2
Secondary function: I2C2_SCL_SCE which is the DVS I2C
serial clock (external pullup) and the SPI chip enable signal
GPIO_4
GPIO_5
1
—
—
I/O
I
Primary function: General-purpose input(2) and output
Ground
PPD
PPD
Secondary function: POWERHOLD input
Ground or VIO
15
Secondary function: REGEN3 which is the external regulator
enable output 3
Primary function: General-purpose input(2) and output
O
I/O
I
Floating
Ground
Floating
—
PPD
PPU(2)
PPD
Secondary function: NSLEEP request signal
GPIO_6
27
Secondary function: POWERGOOD which is the indication
signal for valid regulator output voltages
O
Floating
—
Secondary function: REGEN3 which is the external regulator
enable output 3
Control I2C serial clock (external pullup) and SPI clock signal
Control I2C serial bidirectional data (external pullup) and SPI
input data signal
O
I
Floating
—
—
—
I2C1_SCL_SCK
I2C1_SDA_SDI
35
36
—
—
I/O
INT
26
24
O
I
Maskable interrupt output request to the host processor
External power-on event (on-button switch-on event)
—
—
PWRON
Floating
PU
System reset or power on output (low = reset, high = active or
sleep)
RESET_OUT
25
O
Floating
—
PROGRAMMING, TESTING
Ground or
floating
I
Primary function: OTP programming voltage
Secondary function: TESTV
—
—
VPROG
20
O
Floating
POWER SUPPLIES
VCCA
42
37
34
I
I
I
Analog input voltage for internal LDOs
System supply sense line
System supply
System supply
N/A
—
—
—
VCC_SENSE
VIO_IN
Digital supply input for GPIOs and I/O supply voltage
8
Pin Configuration and Functions
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3.2 Signal Descriptions
Table 3-1. Signal Descriptions
OUTPUT TYPE
SELECTION
OTP POLARITY
ACTIVITY
SIGNAL NAME
LEVEL
I/O(1)
INPUT PU/PD(2)
PU/PD SELECTION
SELECTION
PWRON
BOOT
VSYS (VCCA)
VRTC
Input
PU fixed
N/A (fixed)
N/A (input)
N/A (input)
N/A (input)
Low
No
No
Tri-level input
N/A (input)
Boot conf.
GPIO_0
(primary function)
Input(1)/output
Input
PPD
OTP/SW
Open-drain
Low or high
High
Yes
GPIO_0
secondary
function:
PPD (Opt. Ext. PU)
OTP/SW
N/A (input)
Yes
PWRDOWN
VRTC, fail-safe
(5.25-V tolerance)
GPIO_0
secondary
function:
ENABLE2
No, but software
possible
Input
PPD(1)
SW
N/A (input)
High
GPIO_0
secondary
function:
Output
Input(1)/output
Input
N/A (output)
PPD
N/A (output)
OTP/SW
Open-drain
Open-drain
N/A (input)
High
Low or high
Low
No
Yes
Yes
REGEN1(3)
GPIO_1
(primary function)
GPIO_1
secondary
function:
PPD
OTP/SW
RESET_IN
VRTC, fail-safe
(5.25-V tolerance)
GPIO_1
secondary
function:
Input
Input
PPD
No
OTP/SW
No
N/A (input)
N/A (input)
Low or high
High
Yes
No
NRESWARM
GPIO_1
secondary
function:
VBUS_SENSE
(1) Default option.
(2) Pullup and pulldown resistors: PU = Pullup, PD = Pulldown, PPU = Software-programmable pullup, PPD = Software-programmable pulldown.
(3) This pin should not be pulled up to an always-on voltage domain. Before OTP is loaded, this will be configured as an input, and an active pull-up domain will pull this pin to a high level.
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Table 3-1. Signal Descriptions (continued)
OUTPUT TYPE
SELECTION
OTP POLARITY
SELECTION
SIGNAL NAME
LEVEL
I/O(1)
INPUT PU/PD(2)
PU/PD SELECTION
ACTIVITY
GPIO_2
(primary function)
Input(1)/output
PPU/PPD
OTP/SW
Push-pull(1) or open-drain
Low or high
Yes
GPIO_2
secondary
function:
ENABLE1
No, but software
possible
Input
PPU/PPD(1)
SW
N/A (input)
High
VIO (VIO_IN)
GPIO_2
secondary
function:
I2C2_SDA_SDO
Input/output
Input(1)/output
Input
No
No
OTP/SW
SW
Open-drain
Open-drain
N/A (input)
High
Low or high
High
No
GPIO_3
(primary function)
PPD
Yes
GPIO_3
secondary
function:
ENABLE2
No, but software
possible
PPD(1)
VRTC, fail-safe
(5.25-V tolerance)
GPIO_3
secondary
function:
Output
Input
N/A (output)
PPD(1)
N/A (output)
SW
Open-drain
N/A (input)
High
No
No
REGEN1(3)
GPIO_3
secondary
function:
Toggling
SYNCDCDC
GPIO_4
(primary function)
Input(1)/output
Output
PPU/PPD
OTP/SW
Push-pull(1) or open-drain
Push-pull(1) or open-drain
Low or high
High
Yes
No
GPIO_4
secondary
N/A (output)
N/A (output)
function: REGEN2
VIO (VIO_IN)
GPIO_4
secondary
function:
Input
No
No
N/A (input)
High
No
I2C2_SCL_SCE
10
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SIGNAL NAME
ZHCSGJ3D –JULY 2015–REVISED FEBRUARY 2019
Table 3-1. Signal Descriptions (continued)
OUTPUT TYPE
SELECTION
OTP POLARITY
ACTIVITY
LEVEL
I/O(1)
INPUT PU/PD(2)
PU/PD SELECTION
SELECTION
GPIO_5
(primary function)
Input(1)/output
PPD
OTP/SW
Open-drain
Low or high
High
Yes
GPIO_5
secondary
function:
Input
PPD(1)
SW
N/A (input)
Yes
VRTC, fail-safe
POWERHOLD
(5.25-V tolerance)
GPIO_5
secondary
function:
Output
N/A (output)
N/A (output)
Open-drain
High
No
REGEN3(3)
GPIO_6
(primary function)
Input(1)/output
Input
PPD
OTP/SW
SW
Open-drain
N/A (input)
Low or high
Low
Yes
Yes
GPIO_6
secondary
PPU(1)/PPD
function: NSLEEP
GPIO_6
VRTC
secondary
function:
Output
Output
N/A (output)
N/A (output)
N/A (output)
N/A (output)
Open-drain
Low or high
High
Yes
POWERGOOD(3)
GPIO_6
secondary
function:
Open-drain
No
No
REGEN3(3)
RESET_OUT
VIO (VIO_IN)
VIO (VIO_IN)
Output
Output
N/A (output)
N/A (output)
N/A (output)
N/A (output)
Push-pull(1) or open-drain
Push-pull(1) or open-drain
Low
Low
No, but software
possible
INT
SYNCCLKOUT
I2C1_SDA_SDI
I2C1_SCL_CLK
VCC_SENSE
VRTC
Output
Input/output
Input
N/A (output)
N/A (output)
Push-pull
Open-drain
N/A (input)
N/A (analog)
Toggling
High
No
No
No
No
VIO (VIO_IN)
VIO (VIO_IN)
VSYS (VCCA)
No
No
No
No
No
No
High
Input
Analog
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4 Specifications
4.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–2
MAX
UNIT
VCCA
6
VCC_SENSE
7
All LDOs and SMPS supply voltage input pins
SMPSx_SW pins, 10-ns transient
All SMPS-related input pins _FDBK
6
7
–0.3
3.6
I/O digital supply voltage (VIO_IN with respect to VIO_GND) –0.3 VIOmax + 0.3
VIOmax + 0.3
Voltage
VBUS
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–5
6
V
GPADC pins: ADCIN1 and ADCIN2
OTP supply voltage VPROG
2.4
7
VRTC digital input pins, without fail-safe
VRTC digital input pins, with fail-Safe
VIO digital input pins (VIO_IN pin reference)
VSYS digital input pins (VCCA pin reference)
Peak output current on all pins other than power resources
2.15
5.25
VIOmax + 0.3
6
5
mA
A
Buck SMPS, SMPSx_IN, SMPSx_SW, and SMPSx_OUT
total per phase
Current
4
LDOs
1
Junction temperature, TJ
Storage temperature, Tstg
–45
–65
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
4.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
All pins
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC
Q100-011
Corner pins (1, 12, 13,
24, 25, 36, 37, and 48)
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
4.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted).
MIN
NOM
MAX
UNIT
ELECTRICAL
System voltage input pin VCCA (named VSYS in the specification)
VCC_SENSE, HIGH_VCC_SENSE = 0 (if measured with GPADC, see also 表 5-9)
VCC_SENSE, HIGH_VCC_SENSE = 1 (if measured with GPADC, see also 表 5-9)
3.135
3.135
3.135
1.75
3.8
5.25
VCCA
V
V
V
V
V
VCCA – 1
5.25
(1)
All LDO-related input pins _IN
3.8
3.8
All SMPS-related input pins _IN
3.135
5.25
VOUTmax
+
All SMPS-related input pins _FDBK
All SMPS-related input pins _FDBK_GND
0
V
V
0.3
–0.3
1.71
0.3
VIO = 1.8 V
1.8
3.3
1.89
3.465
I/O digital supply voltage VIO_IN
VIO = 3.3 V
V
3.135
(1) Does not include LDO1 and LDO2 minimum input voltages.
12
Specifications
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Recommended Operating Conditions (continued)
Over operating free-air temperature range (unless otherwise noted).
MIN
0
NOM
MAX
UNIT
V
Voltage on the GPADC pins ADCIN1 (channel 0) and ADCIN2 (channel 1)
OTP supply voltage VPROG
1.25
0
6
LDOVRTC
LDOVRTC
VIO
V
without fail-safe
0
1.85
5.25
Voltage on VRTC digital input pins
V
with fail-safe
0
Voltage on VIO digital input pin (VIO_IN pin reference)
Voltage on VSYS digital input pins (VCCA pin reference)
TEMPERATURE
0
VIOmax
5.25
V
V
0
3.8
Operating free-air temperature range(2)
–40
–40
–40
–65
27
27
105
150
125
150
°C
°C
Operational
Junction temperature, TJ
Parametric compliance
27
Storage temperature, Tstg
27
°C
°C
Lead temperature (soldering, 10 s)
260
(2) Additional cooling strategies may be necessary to maintain junction temperature at recommended limits.
4.4 Thermal Information
TPS65917-Q1
THERMAL METRIC(1)
RGZ (VQFN)
UNIT
48 PINS
24.8
5.6
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
3.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.1
ψJB
3.9
RθJC(bot)
0.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4.5 Electrical Characteristics — LDO Regulators
Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Connected from LDOx_IN to GND
Input filtering capacitance (C18, C19)
0.6
2.2
µF
Shared input tank capacitance (depending on platform requirements)
Connected from LDOx_OUT to GND
Output filtering capacitance (C20, C21, C22,
C23, C24)(1)
0.6
2.2
2.7
µF
< 100 kHz
20
1
100
10
600
20
CESR
Filtering capacitor ESR
Input voltage
mΩ
1 to 10 MHz
0.9 V ≤ VOUT < 2.2 V
1.2
1.2
1.2
1.75
1.75
0.9
VCCA
5.25
3.6
LDO1, LDO2 from LDO12_IN, Normal Mode
LDO1, LDO2 from LDO12_IN, Bypass Mode
2.2 V ≤ VOUT ≤ 3.3 V
VOUT = VIN
VIN(LDOx)
V
0.9 V ≤ VOUT < 2.2 V
2.2 V ≤ VOUT ≤ 3.3 V
VCCA
5.25
3.3
LDO3, LDO4, LDO5 from LDO3_IN, LDO4_IN and
LDO5_IN
LDO output voltage programmable(2) (except
LDOVRTC and LDOVANA)
Range
V
VOUT(LDOx)
Step size
50
mV
0.99 ×
1.006 ×
VOUT(LDOx)
+ 0.014
All LDOs except LDOVANA and LDOVRTC
VOUT(LDOx)
–
VIN(LDOx) ≥ 2.5 V
Total DC output voltage accuracy, including
0.014
TDCOV(LDOx) voltage references, DC load and line
regulations, process and temperature
V
0.99 ×
1.006 ×
VOUT(LDOx)
+ 0.014
All LDOs except LDOVANA and LDOVRTC
VIN(LDOx) < 2.5 V and VOUT(LDOx) < 1.5 V
VOUT(LDOx)
–
0.014
(1) Additional information about how this parameter is specified is located in 节 6.2.2.
(2) LDO output voltages are programmed separately.
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Electrical Characteristics — LDO Regulators (continued)
Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Total DC output voltage accuracy, including
TDCOV(LDOx) voltage references, DC load and line
regulations, process and temperature
–40°C ≤ TA ≤ 85°C
85°C <TA ≤ 105°C
–40°C ≤ TA ≤ 85°C
85°C <TA ≤ 105°C
1.726
1.8
1.85
LDOVRTC_OUT
LDOVANA_OUT
V
1.726
2.002
2.002
1.8
2.093
2.093
1.85
2.14
2.14
Total DC output voltage accuracy, including
TDCOV(LDOx) voltage references, DC load and line
regulations, process and temperature
V
LDO1, LDO2: IOUT = IOUTmax
LDO3, LDO4: IOUT = IOUTmax
LDO5: IOUT = 50 mA
150
290
150
290
300
200
100
10
Dropout voltage
DV(LDOx)= VIN – VOUT
where
VOUT = VOUTnom – 2%
DV(LDOx)
mV
LDO5: IOUT = IOUTmax (not low-noise performance)
LDO1, LDO2
IOUT(LDOx)
Output current
LDO3, LDO4
mA
LDO5
IOUT(LDOx)
IOUT(LDOx)
Output current, internal LDOs
Output current, internal LDOs
LDOVANA in Active Mode
LDOVRTC in Active Mode
LDO1, LDO2
mA
mA
25
380
340
135
600
650
325
1800
1300
740
500
16
ISHORT(LDOx) LDO current limitation
LDO inrush current
LDO3, LDO4
mA
mA
LDO5
LDO1, LDO2
–40°C ≤ TA ≤ 85°C
85°C <TA ≤ 105°C
–40°C ≤ TA ≤ 85°C
85°C <TA ≤ 105°C
–40°C ≤ TA ≤ 85°C
85°C <TA ≤ 105°C
–40°C ≤ TA ≤ 85°C
85°C <TA ≤ 105°C
4
4
IOUT = 0 to IOUTmax at pin, LDO1, LDO2
IOUT = 0 to IOUTmax at pin, all other LDOs
VIN = VINmin to VINmax, IOUT = IOUTmax
16
DCLDR
DC load regulation, ΔVOUT
mV
4
14
4
14
0.1%
0.1%
0.3%
0.3%
0.2%
0.2%
0.75%
0.75%
DCLNR
DC line regulation, ΔVOUT / VOUT
VSYS = VSYSmin to VSYSmax, IOUT = IOUTmax. VINconstant
(LDO preregulated), VOUT ≤ 2.2 V
Pulldown discharge resistance at LDO
output, except LDOVRTC
RDIS
Off mode, pulldown enabled and LDO disabled. Applies to bypass mode also.
30
125
Ω
f = 217 Hz, IOUT = IOUTmax
f = 50 kHz, IOUT = IOUTmax
f = 1 MHz, IOUT = IOUTmax
f = 217 Hz, IOUT = IOUTmax
f = 50 kHz, IOUT = IOUTmax
f = 1 MHz, IOUT = IOUTmax
f = 217 Hz, IOUT = IOUTmax
55
35
25
55
25
20
55
25
25
90
45
Power supply ripple rejection (PSRR),
LDO1, LDO2
35
90
Power supply ripple rejection (PSRR),
LDO3, LDO4
45
dB
35
90
Power supply ripple rejection (PSRR), LDO5 f = 50 kHz, IOUT = IOUTmax
f = 1 MHz, IOUT = IOUTmax
45
35
For all LDOs, VCCA = VIN(LDOx) = 3.8 V, TA = 27°C
0.1
0.2
0.2
46
0.4
1.3
1.3
70
IQoff
Quiescent current – off mode
For all LDOs, VCCA = VIN(LDOx) = 3.8 V, TA = 85°C
For all LDOs, VCCA = VIN(LDOx) = 3.8 V, TA = 105°C
µA
–40°C ≤ TA ≤ 85°C
85°C <TA ≤ 105°C
–40°C ≤ TA ≤ 85°C
85°C <TA ≤ 105°C
–40°C ≤ TA ≤ 85°C
85°C <TA ≤ 105°C
–40°C ≤ TA ≤ 85°C
85°C <TA ≤ 105°C
ILOAD = 0 mA (LDO1, LDO2),
VIN(LDOx) > VOUT(LDOx) + DV(LDOx)
46
70
36
47
ILOAD = 0 mA (LDO3, LDO4),
VIN(LDOx) > VOUT(LDOx) + DV(LDOx)
36
47
IQon(LDO)
Quiescent current – LDO on mode
µA
140
140
180
180
4%
2%
1%
190
190
210
210
ILOAD = 0 mA (LDO5) ,
VOUT ≤ 1.8 V, VIN(LDOx) > VOUT(LDOx) + DV(LDOx)
ILOAD = 0 mA (LDO5) ,
VOUT > 1.8 V, VIN(LDOx) > VOUT(LDOx) + DV(LDOx)
IOUT < 100 µA
Quiescent current coefficient
LDO on mode, IQout = IQon + αQ × IOUT
αQ
100 µA ≤ IOUT < 1 mA
IOUT ≥ 1 mA
On mode, IOUT = 10 mA to IOUTmax / 2, TR = TF = 1 µs. All LDOs except LDO5
On mode, IOUT = 1 mA to IOUTmax / 2, TR = TF = 1 µs. LDO5
On mode, IOUT = 100 µA to IOUTmax / 2, TR = TF = 1 µs
–25
–25
–50
25
25
33
TLDR
Transient load regulation, ΔVOUT
mV
14
Specifications
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Electrical Characteristics — LDO Regulators (continued)
Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN step = 600 mVpp, TR = TF = 10 µs
0.25%
0.5%
Transient line regulation,
ΔVOUT / VOUT
TLNR
VSYS step = 600 mVpp, TR = TF = 10 µs. VINconstant (LDO preregulated), VOUT
2.2 V
≤
0.8%
1.6%
100 Hz < f ≤ 10 kHz
5000
1250
150
250
400
62
8000
2500
300
10 kHz < f ≤ 100 kHz
Noise (except LDO5)
nV/√Hz
100 kHz < f ≤ 1 MHz
f > 1 MHz
500
100 Hz < f ≤ 5 kHz, IOUT = 50 mA , VOUT ≤ 1.8 V
5 kHz < f ≤ 400 kHz, IOUT = 50 mA , VOUT ≤ 1.8 V
400 kHz < f ≤ 10 MHz, IOUT = 50 mA , VOUT ≤ 1.8 V
500
Noise (LDO5)
Ripple
125 nV/√Hz
25
50
LDO1, LDO2, ripple at 32 kHz (from the internal charge pump of 300 mA LDO)
5
mVPP
LDO BYPASS MODE LDO1, LDO2
Bypass resistance of 300 mA LDO
2.9 V ≤ VIN ≤ 3.3 V, VSYS ≥ 3.4 V, IOUT = 250 mA, programmed to BYPASS
1.75 V ≤ VIN ≤ 1.9 V, IOUT = 75 mA , programmed to BYPASS
1.75 V ≤ VIN ≤ 1.9 V, IOUT = 200 mA , programmed to BYPASS
Maximum 50 µF load connected to LDOx_OUT
0.22
0.24
0.24
1100
60
Ω
Ω
Bypass resistance of 300 mA LDO
Bypass resistance of 300 mA LDO
Bypass mode inrush current
Quiescent current – bypass mode
Slew-rate
Ω
mA
µA
IQon(bypass)
60 mV/µs
4.6 Electrical Characteristics — SMPS1&2 in Dual-Phase Configuration
Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted).(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
4.7
47
2
MAX
UNIT
µF
Input capacitance (C8, C9)
Output capacitance (C13, C14)(2)
Filtering capacitor ESR
SMPS1&2 input dual phase operation, per phase
33
57
10
µF
CESR
1 to 10 MHz
SMPSx_SW
mΩ
µH
Output filter inductance (L1, L2)
Filter inductor DC resistance
0.7
1
1.3
100
DCRL
50
mΩ
VIN
(SMPSx)
Input voltage range, SMPSx_IN
VSYS (VCCA)
3.135
0.7
5.25
1.65
V
RANGE = 0 (value for RANGE must not be changed when SMPS is active). In
ECO mode the output voltage values are fixed (defined before ECO mode is
enabled). RANGE = 1 is not supported in Multi-phase configuration.
V
VOUT
(SMPSx)
Output voltage, programmable, SMPSx
Step size, 0.7 V ≤ VOUT ≤ 1.65 V (RANGE = 0)
10
mV
DC output voltage accuracy, includes
voltage references, DC load and line
regulation, process and temperature
ECO mode
–3%
–1%
4%
2%
PWM mode
Max load, VIN = 3.8 V, VOUT = 1.2 V, ESRCOUT = 2 mΩ, measure with 20-MHz
LPF
Ripple, dual phase
4
0.1
0.1
mVPP
%/V
DC line regulation,
ΔVOUT / VOUT
DCLNR
DCLDR
VIN = VINmin to VINmax
IOUT = 0 to IOUTmax
DC load regulation,
ΔVOUT / VOUT
%/A
IOUT = 0.8 to 2 A, TR = TF = 400 ns, COUT = 47 µF , L = 1 µH
IOUT = 0.5 to 500 mA, TR = TF = 100 ns, COUT = 47 µF , L = 1 µH
Advance thermal design is required to avoide thermal shut down
3%
3%
TLDSR
Transient load step response, dual phase
Rated output current, SMPS1&2
7
5
A
mA
A
IOUTmax
Maximum output current, ECO mode
High-side MOSFET forward current limit
Low-side MOSFET forward current limit
ILIM
SMPS1&2, each phase
SMPS1&2, each phase
4.2
4.5
4.2
HS FET
ILIM
A
LS FET
RDS(ON) HS
N-channel MOSFET on-resistance, high-
side FET
SMPS1&2, each phase
50
mΩ
FET
RDS(ON) LS
N-channel MOSFET on-resistance, low-side
FET
SMPS1&2, each phase
RANGE = 1
39
mΩ
FET
(3)
Output voltage slew rate
2.5
mV/μs
(1) SMPS1 and SMPS2 can be used in parallel in dual-phase mode to be able to multiply the output current by 2, and the converter is
named SMPS1&2. The naming SMPS1 and SMPS2 is used when the bucks are configured as a separate buck converters.
(2) Additional information about how this parameter is specified is located in节 6.2.2.
(3) This slew rate refers to the rate at which the output voltage changes from one voltage level to another voltage after startup is complete.
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Electrical Characteristics — SMPS1&2 in Dual-Phase Configuration (continued)
Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted).(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
375
9
MAX
UNIT
SMPSx_FDBK, SMPS turned off
RDIS
Pulldown discharge resistance output
Ω
SMPSx_SW, SMPS turned off. Pulldown is at master phase output.
Between SMPS1_FDBK and SMPS2_FDBK
22
Input resistance for remote sense (sense
line)
RSENSE
IQoff
260
2200
kΩ
μA
Quiescent current – Off mode
ILOAD = 0 mA
0.1
15
18
2.5
25
ECO mode, device not switching, –40°C ≤TA ≤ 85°C
ECO mode, device not switching, 85°C < TA ≤105°C
µA
25.5
IQon(ON)
Quiescent current – On mode, dual phase
PWM mode,
11
mA
ILOAD = 0 mA, VIN = 3.8 V, VOUT = 1 V, device switching, 1-phase operation
SMPS output voltage rising, referenced to programmed output voltage
SMPS output voltage falling, referenced to programmed output voltage
IL_AVG_COMP_rising
–4%
–16%
6
VSMPSPG
Powergood threshold SMPS1, SMPS2
IL_AVG_COMP Powergood: GPADC monitoring SMPS1&2
A
IL_AVG_COM
P_rising-5%
IL_AVG_COMP_falling
4.7 Electrical Characteristics — SMPS1, SMPS2, SMPS3, SMPS4, and SMPS5 Stand-
Alone Regulators
Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input capacitance (C8, C9, C10, C11, C12)
4.7
µF
Output capacitance (C13, C14, C15, C16,
C17)(1)
33
47
57
µF
CESR
Filtering capacitor DC ESR
1 to 10 MHz
SMPSx_SW
2
1
10
1.3
mΩ
µH
mΩ
V
Output filter inductance (L1, L2, L3, L4, L5)
Filter inductor DC resistance
0.7
DCRL
50
100
5.25
VIN (SMPSx)
Input voltage range, SMPSx_IN
VSYS (VCCA)
3.135
0.7
RANGE = 0 (value for RANGE must not be changed when SMPS is
active). In ECO mode the output voltage value is fixed (defined before
ECO mode is enabled).
1.65
3.3
V
RANGE = 1 (value for RANGE must not be changed when SMPS is
active). In ECO mode the output voltage value is fixed (defined before
ECO mode is enabled).
VOUT (SMPSx) Output voltage, programmable, SMPSx
1.0
Step size, 0.7 V ≤ VOUT ≤ 1.65 V
Step size, 1 V ≤ VOUT ≤ 3.3 V
10
20
mV
DC output voltage accuracy, includes voltage ECO mode
–3%
–1%
4%
2%
references, DC load and line regulation,
process and temperature
PWM mode
Max load, VIN = 3.8 V, VOUT = 1.2 V, ESRCOUT = 2 mΩ, measured with 20-
MHz LPF
Ripple
8
mVPP
DCLNR
DCLDR
DC line regulation, ΔVOUT / VOUT
DC load regulation, ΔVOUT / VOUT
VIN = VINmin to VINmax
IOUT = 0 to IOUTmax
0.1
0.1
%/V
%/A
SMPS1, SMPS2, SMPS3, SMPS5, IOUT = 0.5 to 500 mA, TR = TF = 100
ns, COUT = 47 µF , L = 1µH
TLDSR
TLDSR
Transient load step response
Transient load step response
3%
3%
SMPS4, IOUT = 0.5 to 500 mA, TR = TF = 1 µs, COUT = 47 µF , L = 1µH
IOUTmax(SMPS1,2) Rated output current, SMPS1, SMPS2
Advance thermal design is required to avoid thermal shut down
3.5
3
A
A
IOUTmax(SMPS3)
IOUTmax(SMPS4)
IOUTmax(SMPS5)
IOUTmax(ECO)
Rated output current, SMPS3
Rated output current, SMPS4
Rated output current, SMPS5
Maximum output current, ECO mode
Advance thermal design is required to avoid thermal shut down
Advance thermal design is required to avoid thermal shut down
1.5
2
A
Advance thermal design is required to avoid thermal shut down
A
Advance thermal design is required to avoid thermal shut down
5
mA
SMPS1, SMPS2, SMPS3
4.2
2.2
2.7
4.5
2.5
3
ILIM
High-side MOSFET forward current limit
Low-side MOSFET forward current limit
SMPS4
A
A
HS FET
SMPS5
SMPS1, SMPS2, SMPS3
4.2
2.2
2.7
50
ILIM
SMPS4
LS FET
SMPS5
SMPS1, SMPS2, SMPS3, SMPS5
SMPS4
mΩ
mΩ
N-channel MOSFET on-resistance (high-side
FET)
RDS(ON)
HS FET
110
(1) Additional information about how this parameter is specified is located in 节 6.2.2.
16 Specifications
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Electrical Characteristics — SMPS1, SMPS2, SMPS3, SMPS4, and SMPS5 Stand-Alone
Regulators (continued)
Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
39
MAX
UNIT
SMPS1, SMPS2, SMPS3, SMPS5
N-channel MOSFET on-resistance (low-side
FET)
RDS(ON)
mΩ
LS FET
SMPS4
79
Overshoot during turn-on
5%
(2)
Output voltage slew rate
2.5
375
9
mV/μs
Ω
SMPSx_FDBK, SMPS turned off
Pulldown discharge resistance at SMPSx
output
RDIS
IQoff
SMPSx_SW, SMPS turned off
22
2.5
Quiescent current – Off mode
ILOAD = 0 mA
0.1
15
μA
ECO mode, device not switching, VOUT < 1.8 V –40°C ≤TA ≤ 85°C
ECO mode, device not switching, VOUT < 1.8 V 85°C < TA ≤ 105°C
ECO mode, device not switching, VOUT ≥ 1.8 V, –40°C ≤TA ≤ 85°C
ECO mode, device not switching, VOUT ≥ 1.8 V, 85°C < TA ≤ 105°C
25
18
25.5
25
µA
mA
µA
Quiescent current – On mode - SMPS1,
SMPS2, SMPS3, SMPS5
16.5
19.5
IQon(SMPS1,2,3,5)
25.5
FORCED_PWM mode, ILOAD = 0 mA, VIN = 3.8 V, VOUT = 1 V, device
switching
11
ECO mode, device not switching, VOUT < 1.8 V –40°C ≤TA ≤ 85°C
ECO mode, device not switching, VOUT < 1.8 V 85°C < TA ≤ 105°C
ECO mode, device not switching, VOUT ≥ 1.8 V, –40°C ≤TA ≤ 85°C
ECO mode, device not switching, VOUT ≥ 1.8 V, 85°C < TA ≤ 105°C
15
18
24
25
24
25
16.5
19.5
IQon(SMPS4)
Quiescent current – On mode - SMPS4
FORCED_ PWM mode, ILOAD = 0 mA, VIN = 3.8 V, VOUT = 1 V, device
switching
7
mA
SMPS output voltage rising, referenced to programmed output voltage
SMPS output voltage falling, referenced to programmed output voltage
IL_AVG_COMP_rising - SIMPS1, SMPS2
–4%
VSMPSPG
Powergood threshold
–16%
3
3
2
A
A
A
IL_AVG_COMP_rising - SMPS3
IL_AVG_COMP_rising - SMPS5
IL_AVG_COMP Powergood: GPADC monitoring
IL_AVG_COM
P_rising-5%
IL_AVG_COMP_falling - SMPS1, SMPS2, SMPS3
IL_AVG_COMP_falling- SMPS5
A
A
IL_AVG_COM
P_rising-8%
(2) This slew rate refers to the rate at which the output voltage changes from one voltage level to another voltage after startup is complete.
4.8 Electrical Characteristics — Reference Generator (Bandgap)
Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
Connected from VBG to REFGND
MIN
TYP
100
0.85
20
MAX
UNIT
nF
Filtering capacitor
Output voltage
Ground current
30
150
V
40
µA
4.9 Electrical Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers
Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted).
PARAMETER
32-kHz RC OSCILLATOR
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Active current consumption
Power down current
4
8
μA
30
nA
SYNCCLKOUT OUTPUT BUFFER
Logic output external load
5
35
50
pF
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4.10 Electrical Characteristics — 12-Bit Sigma-Delta ADC
Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted).
PARAMETER
Current consumption
Off mode current
TEST CONDITIONS
MIN
TYP
MAX
1600
1
UNIT
μA
IQON
During conversion
1500
IQOFF
GPADC is not enabled (no conversion)
Without calibration (inputs without scaler)
Without calibration (inputs with scaler)
With calibration, TA = 27°C, VCCA = 5.25V
Without calibration
μA
–3.5%
–4.5%
–0.95%
–65
3.5%
4.5%
0.95%
65
Gain error
Offset
LSB
With calibration, TA = 27°C, VCCA = 5.25V
–17
17
Gain error drift (after trimming, including
reference voltage)
Temperature and supply
–0.6%
0.6%
Offset drift after trimming
Integral nonlinearity
Differential nonlinearity
Input capacitance
Temperature and supply
Best fitting
–2
–3.5
–1
2
3.5
3.5
LSB
LSB
LSB
pF
INL
DNL
ADCIN1, ADCIN2
0.5
Source resistance without capacitance
Source capacitance with > 20-kΩ source resistance
Typical range
20
kΩ
Source input impedance
100
0
nF
1.25
Input range (sigma-delta ADC)
V
Assured range without saturation
0.01
1.215
SMPS CURRENT MONITORING (GPADC CHANNEL 4)(1)
Channel 4 SMPS output current
measurement gain factor, IFS0
3.958
0.652
A
A
Channel 4 SMPS output current
measurement current offset, IOS0
Channel 4 SMPS output current
measurement temperature coefficient,
TC_R0
–1090
ppm/°C
SMPS output current measurement
accuracy, Ierr (%), GPADC trimmed
ILOAD_error (%) = ILOAD_meas / ILOAD × 100.
ILOAD = 3 A for SMPS1/SMPS2/SMPS3. 25°C
–8%
8%
SMPS output current measurement
accuracy, Ierr (%), GPADC trimmed
ILOAD_error (%) = ILOAD_meas / ILOAD × 100.
ILOAD = 2 A for SMPS5. 25°C
–10%
10%
(1) Basic equation for result: ILOAD = IFS × GPADC code / (212 – 1) – IOS, where K is the number of SMPS active phases, IFS= IFS0 × K
and IOS = IOS0 × K
Temperature compensated result: ILOAD = IFS × GPADC code / ( (212 – 1) × (1 + TC_R0 × (TEMP-25) ) ) – IOS
4.11 Electrical Characteristics — Thermal Monitoring and Shutdown
Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
104
95
TYP
117
108
121
112
125
116
130
120
148
123
MAX
127
119
132
123
136
128
143
132
163
135
0.1
UNIT
Rising threshold
Falling threshold
Rising threshold
Falling threshold
Rising threshold
Falling threshold
Rising threshold
Falling threshold
HDSEL[1:0] = 00
HDSEL[1:0] = 01
HDSEL[1:0] = 10
HDSEL[1:0] = 11
109
99
Hot-die temperature threshold
°C
113
104
117
108
133
111
Rising threshold
Falling threshold
Thermal shutdown threshold
°C
μA
μA
Device in OFF state, VCCA = 3.8 V, T = 25°C
Device in OFF state
Off ground current (two sensors on the die,
specification for one sensor)
IQOFF
0.5
Device in ACTIVE state, VCCA = 3.8 V, T = 25°C
Device in ACTIVE state, GPADC measurement
7
15
On ground current (two sensors on the die,
specification for one sensor)
IQON
25
40
18
Specifications
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4.12 Electrical Characteristics — System Control Thresholds
Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted).
PARAMETER
POR (power-on reset) rising-edge threshold
POR falling-edge threshold
TEST CONDITIONS
MIN
2.0
TYP
2.15
2
MAX
UNIT
V
Measured on VCCA pin
Measured on VCCA pin
2.5
1.7
2.46
300
3.1
V
POR hysteresis
Rising edge to falling edge
Voltage range, 50-mV steps
Voltage accuracy
40
mV
V
2.75
–50
75
VSYS_LO, falling threshold, measured on VCCA pin
VSYS_LO hysteresis
95
mV
mV
V
Falling edge to rising edge
Voltage range, 50-mV steps
Voltage accuracy
460
3.85
140
4.6
2.9
VSYS_HI, measured on VCC_SENSE pin
–70
2.75
–70
2.9
mV
V
Voltage range, 50-mV steps
Voltage accuracy
VSYS_MON, measured on VCC_SENSE pin
140
3.6
mV
V
Rising threshold
VBUS detection (VBUS wake-up comparator threshold [plug
detect])
Falling threshold
2.8
3.3
V
4.13 Electrical Characteristics — Current Consumption
Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFF MODE
IOFF
Device Off Mode Current Consumption
VCCA = 3.8 V, Device in OFF mode.
20
90
55
µA
SLEEP MODE
VCCA = 3.8 V, PLL disabled, Device in Sleep mode. SMPS4 and
SMPS5 enabled in ECO mode, no load, all other external supply
rails are disabled
ISLEEP Device Sleep Mode Current Consumption
150
µA
4.14 Electrical Characteristics — Digital Input Signal Parameters
Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted). (VIO to refers to VIO_IN
pin, VSYS to refers to VCCA pin)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PWRON
Low-level input voltage related to VSYS (VCCA pin
reference)
0.35 ×
VSYS
VIL(VSYS)
–0.3
0
V
V
V
High-level input voltage related to VSYS (VCCA pin
reference)
0.65 ×
VSYS
VSYS + 0.3
VIH(VSYS)
VSYS
≤ 5.25
0.025 ×
VSYS
Hysteresis related to VSYS
GPIO_2, GPIO_4, ENABLE1, I2C2_SCL_SCE, I2C2_SDA_SDO, I2C1_SCL_SCK, I2C1_SDA_SDI
Low-level input voltage related to VIO (VIO_IN pin
reference)
VIL(VIO)
–0.3
0
0.3 × VIO
VIO + 0.3
V
High-level input voltage related to VIO (VIO_IN pin
reference)
VIH(VIO)
0.7 × VIO
VIO
V
V
Hysteresis related to VIO
0.045 × VIO
BOOT, SYNCDCDC, ENABLE2, GPIO_0, GPIO_1, GPIO_3, GPIO_5, GPIO_6, NRESWARM, POWERHOLD, PWRDOWN, RESET_IN, NSLEEP
VIL(VRTC)
VIH(VRTC)
Low-level input voltage related to VRTC
High-level input voltage related to VRTC
–0.3
0
0.3 × VRTC
V
V
0.7 × VRTC
VRTC VRTC + 0.3
0.05 ×
VRTC
Hysteresis related to VRTC
V
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4.15 Electrical Characteristics — Digital Output Signal Parameters
TA = –40°C to +85°C, typical values are at TA = 27°C (unless otherwise noted). (VIO to refers to VIO_IN pin, VSYS to refers
to VCCA pin)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GPIO_2, GPIO_4, REGEN2, INT, RESET_OUT
IOL = 2 mA
0.45
0.2
Low-level output voltage, push-pull and open-drain
V
IOL = 100 µA
VIO –
0.45
IOH = 2 mA
VIO
High-level output voltage, push-pull (VIO_IN pin
reference)
V
V
IOH = 100 µA
VIO – 0.2
VIO
VIO
Supply for external pullup resistor, open drain
SYNCCLKOUT
IOL = 1 mA
0.45
0.2
VOL(SYNCCLKO
Low-level output voltage, push-pull
High-level output voltage , push-pull
V
V
UT)
IOL = 100 µA
VRTC –
0.45
IOH = 1 mA
VRTC
VRTC
VOH(SYNCCLK
OUT)
VRTC –
0.2
IOH = 100 µA
GPIO_0, GPIO_1, GPIO_3, GPIO_5, REGEN1
External pullup to VRTC, IOL = 2 mA
External pullup to VRTC, IOL = 100 µA
0.45
0.2
Low-level output voltage, open-drain
V
V
Supply for external pullup resistor, open-drain
5.25
GPIO_6, POWERGOOD, REGEN3
External pullup to VRTC, IOL = 2 mA
External pullup to VRTC, IOL = 100 µA
0.45
0.2
Low-level output voltage, open-drain
V
V
Supply for external pullup resistor, open-drain
VRTC
I2C1_SDA_SDI, I2C2_SDA_SDO
Low-level output voltage related to VIO (VIO_IN pin
reference)
VOL(VIO)
3-mA sink current
0.1 × VIO
0.2 × VIO
20
V
CB
Capacitive load for I2C2_SDA _SDO
SPI Interface mode is selected
pF
4.16 I/O Pullup and Pulldown Characteristics
Over operating free-air temperature range (unless otherwise noted). (VIO to refers to VIO_IN pin, VSYS to refers to VCCA
pin)
PARAMETER
PWRON signal, fixed pullup
TEST CONDITIONS
PULL UP
MIN
55
TYP
120
400
400
400
400
400
MAX
370
UNIT
kΩ
VSYS pullup supply
VRTC pullup supply
GPIO_0, GPIO_1, GPIO3, and GPIO5 signals
PULL DOWN
PULL UP
180
170
170
170
180
900
kΩ
1200
950
GPIO_2 and GPIO_4 signals
VIO pullup supply
kΩ
kΩ
PULL DOWN
PULL UP
1200
900
GPIO_6 signal
VRTC pullup supply
PULL DOWN
4.17 Electrical Characteristics — I2C Interface
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CB
Capacitive load for SDA and SCL
400
pF
20
Specifications
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4.18 Timing Requirements — I2C Interface
Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted).
(1)(2)(3)(4)
MIN
MAX
100
UNIT
kHz
Standard mode
Fast mode
400
kHz
High-speed mode (write operation), CB
100 pF max
–
–
–
–
3.4
3.4
1.7
1.7
MHz
MHz
MHz
MHz
High-speed mode (read operation), CB
100 pF max
f(SCL)
SCL clock frequency
High-speed mode (write operation), CB
400 pF max
High-speed mode (read operation), CB
400 pF max
Standard mode
4.7
μs
μs
μs
ns
ns
μs
μs
ns
ns
μs
ns
ns
ns
μs
ns
ns
ns
ns
ns
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Bus free time between a stop (P)
and start (S) condition
tBUF
Fast mode
1.3
Standard mode
4
tHD(ST Hold time (Repeated) start
Fast mode
600
condition
A)
High-speed mode
160
Standard mode
4.7
Fast mode
1.3
tLOW
Low period of the SCL clock
High period of the SCL clock
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
160
320
4
Fast mode
600
tHIGH
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
60
120
4.7
tSU(STA Setup time for a repeated start
Fast mode
600
(Sr) condition
)
High-speed mode
160
Standard mode
250
tSU(DA
T)
Data setup time
Fast mode
100
High-speed mode
10
Standard mode
0
3.45
0.9
Fast mode
0
tHD(DA
T)
Data hold time
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
0
70
0
20 + 0.1 CB
20 + 0.1 CB
10
150
1000
300
40
Fast mode
tRCL
Rise time of the SCL signal
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
20
80
20 + 0.1 CB
20 + 0.1 CB
10
1000
300
80
Rise time of the SCL signal after
a Repeated Start condition and
after an acknowledge bit
Fast mode
tRCL1
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
20
160
(1) Specified by design. Not tested in production.
(2) All values referred to VIHmin and VIHmax levels.
(3) For bus line loads CB between 100 and 400 pF, the timing parameters must be linearly interpolated.
(4) A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH
signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
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Timing Requirements — I2C Interface (continued)
Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted). (1)(2)(3)(4)
MIN
MAX
300
300
40
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
Standard mode
20 + 0.1 CB
Fast mode
20 + 0.1 CB
tFCL
tRDA
tFDA
Fall time of the SCL signal
Rise time of the SDA signal
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
10
20
80
20 + 0.1 CB
1000
300
80
Fast mode
20 + 0.1 CB
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
10
20
160
300
300
80
20 + 0.1 CB
Fast mode
20 + 0.1 CB
Fall time of the SDA signal
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
10
20
160
4
tSU(ST
O)
Setup time for a stop condition
Fast mode
600
160
ns
ns
High-speed mode
4.19 Timing Requirements — SPI
See 图 4-3 for the SPI timing diagram.
MIN
30
30
67
20
20
5
MAX
UNIT
ns
tcesu
tcehld
tckper
tckhigh
tcklow
tsisu
Chip-select set up time
Chip-select hold time
ns
Clock cycle time
100
ns
Clock high typical pulse duration
Clock low typical pulse duration
Input data set up time, before clock active edge
Input data hold time, after clock active edge
ns
ns
ns
tsihld
tdr
5
ns
15
30
ns
tCE
Time from CE going low to CE going high
Capacitive load on pin SDO
67
ns
pF
4.20 Switching Characteristics — LDO Regulators
Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted).
PARAMETER
Turn-on time
Turn-off time (except VRTC)
TEST CONDITIONS
MIN
TYP
100
250
MAX
500
UNIT
μs
Ton
Toff
IOUT = 0, VOUT = 0.1 V up to VOUTmin
IOUT = 0, VOUT down to 10% × VOUT
500
μs
4.21 Switching Characteristics — SMPS1&2 in Dual-Phase Configuration
Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
PWM mode
MIN
TYP
MAX
UNIT
fSW
Switching frequency
1.7
2.2
2.7
MHz
Time from enable to the start of the
ramp
Tstart
Tramp
240
400
µs
µs
Time from enable to 80% of VOUT
COUT < 57 µF per phase, no load
1000
22
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4.22 Switching Characteristics — SMPS1, SMPS2, SMPS3, SMPS4, and SMPS5 Stand-
Alone Regulators
Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
In PWM mode
MIN
TYP
MAX
UNIT
fSW
Switching frequency
1.7
2.2
2.7
MHz
Time from enable to the start of the
ramp
Tstart
Tramp
150
400
µs
µs
Time from enable to 80% of VOUT
COUT < 57 µF per phase, no load
1000
4.23 Switching Characteristics — Reference Generator (Bandgap)
Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted).
PARAMETER
Start-up time
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1
3
ms
4.24 Switching Characteristics — PLL for SMPS Clock Generation
Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Synchronization range of
SYNCDCDC clock
fSYNC
1.7
2.2
2.7
MHz
Dither amplitude of SYNCDCDC
clock
ADITHER
MDITHER
128
kHz
Dither slope of SYNCDCDC clock
1.35
2.42
2.42
2.42
kHz/µs
VCCA = 5.25 V
1.98
1.9
2.2
2.2
2.2
fFALLBACK
Fallback frequency
VCCA = 3.8 V
MHz
VCCA = 3.135 V
1.9
The low saturation frequency of
the PLL
fSAT,LO
fSAT,HI
1.35
2.8
1.68
3.8
MHz
MHz
The high saturation frequency of
the PLL
Time from initial application or
removal of sync clock until PLL
output has settled to 1% of the final
value
tSETTLE
Settling time
100
1%
µs
The steady-state percent of
difference between fSYNC and the
switching frequency
fERROR
Frequency error
–1%
4.25 Switching Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers
Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted).
PARAMETER
32-kHz RC OSCILLATOR
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output frequency low-level output voltage
Output frequency accuracy
Cycle jitter (RMS)
32768
0%
Hz
After trimming at 27°C
–10%
40%
10%
10%
60%
150
Output duty cycle
50%
Settling time
μs
SYNCCLKOUT OUTPUT BUFFER
Rise and fall time
CL = 35 pF, 10% to 90%
Logic output signal
5
20
100
ns
Duty cycle
40%
50%
60%
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4.26 Switching Characteristics — 12-Bit Sigma-Delta ADC
Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Active or
sleep with VANA ON and
RC15MHZ_ON_IN_SLEEP = 1 or
sleep with GPADC_FORCE = 1
0
Turn-on time
μs
Sleep or OFF
794
282
113
563
223
Sleep with VANA enabled
1 channel, EXTEND_DELAY = 0
1 channel, EXTEND_DELAY = 1
2 channels
Conversion time
μs
SDA
SCL
tBUF
tf
tLOW
tf
tsu;DAT
tr
thd;STA
tr
thd;STA
tsu;STA
tsu;STO
thd;DAT
HIGH
Sr
S
P
S
Note: S = Start; Sr = Repeated start; P = Stop
图 4-1. Serial Interface Timing Diagram For F/S Mode
Sr
Sr
P
tfDA
trDA
SDA (HS)
thd;DAT
tsu;STO
tsu;STA
tsu;DAT
thd;STA
SCL (HS)
tfCL1
trCL1
trCL1
trCL
tLOW
tHIGH
tHIGH
tLOW
See Note A
See Note B
= MCS Current Source Pullup
= R(P) Resistor Pullup
A. First rising edge of the SCL (HS) signal after Sr and after each acknowledge bit.
B. Sr = Repeated start; P = Stop
图 4-2. Serial Interface Timing Diagram For HS Mode
24
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SPI chip select
tckper
tckhigh
tcehld
tcklow
tcesu
SPI clock enable
tsisu
tsihld
R/W
Address
Unused
tdr
Data
SPI data input
SPI data output
Don‘t care
图 4-3. SPI Timings
See Section 4.19 for the Timing Parameters
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4.27 Typical Characteristics
100%
80%
60%
40%
20%
0%
80%
60%
40%
20%
VO = 0.7 V
VO = 1.05 V
VO = 1.2 V
VO = 1.65 V
VO = 1.8 V
VO = 2.5 V
VO = 0.7 V
VO = 1.05 V
VO = 1.2 V
VO = 1.65 V
VO = 1.8 V
VO = 3.3 V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
Load Current (mA)
D001
Load Current (A)
D002
VI = 3.8 V
ƒS = 2.2 MHz
TA = 25°C
VI = 3.8 V
ƒS = 2.2 MHz
TA = 25°C
图 4-4. SMPS Efficiency for all SMPS in Eco-mode
图 4-5. SMPS Efficiency for SMPS1 and SMPS2
in Single-Phase PWM Mode
100%
100%
80%
60%
40%
20%
0%
80%
60%
40%
20%
0%
TA = -40èC
TA = 25èC
TA = 105èC
Ö
Ö
Ö
S = 1.7 MHz
S = 2.2 MHz
S = 2.7 MHz
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
Load Current (A)
Load Current (A)
D003
D004
VI = 3.8 V
ƒS = 2.2 MHz
VO = 1.8 V
VI = 3.8 V
VO = 1.8 V
TA = 25°C
图 4-6. SMPS Efficiency for SMPS1 and SMPS2
in Single-Phase PWM Mode With Temperature Variation
图 4-7. SMPS Efficiency for SMPS1 and SMPS2
in Single-Phase PWM Mode With Frequency Variation
100%
80%
60%
100%
80%
60%
40%
40%
VO = 0.7 V
VO = 0.7 V
VO = 1.05 V
VO = 1.2 V
VO = 1.65 V
VO = 1.05 V
VO = 1.2 V
VO = 1.65 V
20%
20%
VO = 1.8 V
VO = 1.8 V
VO = 3.3 V
VO = 3.3 V
0%
0%
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Load Current (A)
3
0
0.2
0.4
0.6
0.8
1
1.2
1.4 1.6
Load Current (A)
D005
D006
VI = 3.8 V
ƒS = 2.2 MHz
TA = 25°C
VI = 3.8 V
ƒS = 2.2 MHz
TA = 25°C
图 4-8. SMPS Efficiency for SMPS3
图 4-9. SMPS Efficiency for SMPS4
in PWM Mode
in PWM Mode
26
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Typical Characteristics (continued)
100%
100%
80%
60%
40%
20%
0%
80%
60%
40%
20%
0%
VO = 0.7 V
VO = 1.05 V
VO = 1.2 V
VO = 1.65 V
VO = 1.8 V
VO = 3.3 V
VO = 0.7 V
VO = 1.05 V
VO = 1.2 V
VO = 1.65 V
VO = 1.8 V
VO = 3.3 V
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
Load Current (A)
Load Current (A)
D007
D008
VI = 3.8 V
ƒS = 2.2 MHz
TA = 25°C
VI = 3.8 V
ƒS = 2.2 MHz
TA = 25°C
图 4-10. SMPS Efficiency for SMPS5
in PWM Mode
图 4-11. SMPS Efficiency for SMPS12
in Dual-Phase PWM Mode
0.2%
0.16%
0.12%
0.08%
0.04%
0%
0.32%
0.28%
0.24%
0.2%
0.16%
0.12%
0.08%
0.04%
0
-0.04%
-0.08%
-0.12%
-0.16%
-0.2%
VO = 0.7 V
VO = 0.7 V
VO = 1.2 V
VO = 1.8 V
VO = 3.3 V
VO = 1.05 V
VO = 1.2 V
VO = 1.65 V
-0.04%
-0.08%
-0.12%
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
Output Current (A)
Output Current (A)
D009
D013
VI = 3.8 V
ƒS = 2.2 MHz
TA = 25°C
VI = 3.8 V
ƒS = 2.2 MHz
TA = 25°C
图 4-12. SMPS Load Regulation for SMPS1 and SMPS2 Single-
图 4-13. SMPS Load Regulation for SMPS3, PWM Mode
Phase PWM Mode
0.2%
0.16%
0.12%
0.08%
0.04%
0%
0.32%
0.28%
0.24%
0.2%
0.16%
0.12%
0.08%
0.04%
-0.04%
-0.08%
0
VO = 0.7 V
VO = 1.05 V
VO = 1.2 V
VO = 1.65 V
VO = 0.7 V
-0.12%
-0.04%
-0.08%
-0.12%
VO = 1.05 V
VO = 1.2 V
VO = 1.65 V
-0.16%
-0.2%
0
0.5
Output Current (A)
1
1.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
Output Current (A)
D010
D011
VI = 3.8 V
ƒS = 2.2 MHz
TA = 25°C
VI = 3.8 V
ƒS = 2.2 MHz
TA = 25°C
图 4-14. SMPS Load Regulation for SMPS4
图 4-15. SMPS Load Regulation for SMPS12
in Dual-Phase PWM Mode
in PWM Mode
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Typical Characteristics (continued)
0.2%
0.16%
0.12%
0.08%
0.04%
0%
-0.04%
-0.08%
-0.12%
-0.16%
VO = 0.7 V
VO = 1.05 V
VO = 1.2 V
VO = 1.65 V
-0.2%
0
0.5
1
1.5
2
Output Current (A)
D012
VI = 3.8 V
ƒS = 2.2 MHz
TA = 25°C
图 4-16. SMPS Load Regulation for SMPS5
in PWM Mode
28
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5 Detailed Description
5.1 Overview
The TPS65917-Q1 device is an integrated power-management integrated circuit (PMIC), available in a 48-
pin, 0.5-mm pitch, 7-mm × 7-mm QFN package. It is designed specifically for automotive applications. It
provides five configurable step-down converter rails, with two of the rails having the ability to combine
power rails and supply up to 7A of output current in multi-phase mode. The TPS65917-Q1 device also
provides five external LDO rails. It also comes with a 12-bit GPADC with two external channels, seven
configurable GPIOs, two I2C interface channels or one SPI interface channel, PLL for external clock sync
and phase delay capability, and programmable power sequencer and control for supporting different
processors and applications.
The five step-down converter rails are consisting of five high frequency switch mode converters with
integrated FETs. They are capable of synchronizing to an external clock input and supports switching
frequency between 1.7 MHz and 2.7 MHz. The SMPS1 and SMPS2 can combine in dual phase
configuration to supply up to 7 A. In addition, SMPS1, SMPS2, and SMPS3 support dynamic voltage
scaling by a dedicated I2C interface for optimum power savings.
The five LDOs support 0.9 V to 3.3 V output with 50-mV step. The LDOs can be supplied from either a
system supply or a pre-regulated supply. All LDOs and step-down converters can be controlled by the SPI
or I2C interface, or by power request signals. In addition, voltage scaling registers allow transitioning the
SMPS to different voltages by SPI, I2C, or roof and floor control.
The power-up and power-down controller is configurable and programmable through OTP. The
TPS65917-Q1 device includes a 32-kHz RC oscillator to sequence all resources during power up and
power down. An internal LDOVRTC generates the supply for the entire digital circuitry of the device as
soon as the VSYS supply is available through the VCCA input.
Configurable GPIOs with multiplexed feature are available on the TPS65917-Q1 device. The GPIOs can
be configured and used as enable signals for external resources, which can be included into the power-up
and power-down sequence. The general-purpose (GP) sigma-delta analog-to-digital converter (ADC) with
two external input channels included in this device can be used as thermal or voltage and current
monitors.
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5.2 Functional Block Diagram
VSYS
VIO
VSYS
C1
C3
C5
C4
C2
BOOT
Boot mode
selection
PWRON
POWERHOLD
Control
inputs
SMPS1_IN
VSYS
RESET_IN
NRESWARM
NSLEEP
Grounds
L1
SMPS1_SW
SMPS1
3.5 A
(DVS/AVS)
[Master]
Test and
program
LDOVANA
LDOVRTC
C8
<SMPS1_GND>
C13
VCC
I2C1_SCL_CLK
internal
supply
I2C CNTL,
I2C DVS,
or SPI
SMPS2_IN
SMPS2_SW
SMPS1_FDBK
SMPS2_FDBK
<SMPS2_GND>
I2C1_SDA_SDI
VSYS
Dual or
Single phase
L2
EN
VSEL
RAMP
CLK1
I2C2_SCL_SCE
I2C2_SDA_SDO
TPS65917-Q1
Application
Processor
SMPS2
3.5 A
(DVS/AVS)
[Multi/Stand-
alone]
RESET_OUT
INT
C14
C9
PLL
(Phase
synchronization
and dither)
Internal
Interrupt
events
SYNCDCDC
SMPS3_IN
SMPS3_SW
VSYS
VSYS
ENABLE2
PWRDOWN
REGEN1
GPIO_0
GPIO_1
GPIO_2
JTAG
DFT
L3
SMPS3
3 A
(DVS/
AVS)
CLK2
EN
VSEL
RAMP
SMPS3_FDBK
OTP controller
OTP memory
C10
C15
RESET_IN
<SMPS3_GND>
RESWARM
VBUS_SENSE
Registers
CLK3
EN
VSEL
SMPS4_IN
VCCA
POR
Programmable
power sequencer
controller
L4
SMPS4_SW
ENABLE1
I2C2_SDA_SDO
SMPS4
1.5 A
(AVS)
VCCA
SMPS4_FDBK
VSYS_LO
VCC_SENSE
VSYS_MON
C11
ECO
PWM
DVS
C16
GPIO
signals
and
<SMPS4_GND>
ENABLE2
REGEN1
GPIO_3
VBUS_SENSE
Switch ON and
OFF
controls
SYNCDCDC
SMPS5_IN
VSYS
VBUS_WKUP_UP
CLK4
EN
VSEL
L5
SMPS5_SW
GPIO_4
GPIO_5
GPIO_6
WDT
REGEN2
I2C2_SCL_SCE
SMPS5
2 A
(AVS)
Thermal
monitoring
SMPS5_FDBK
C12
C17
<SMPS5_GND>
Thermal
shutdown
REGEN3
POWERHOLD
Hot die detection
NSLEEP
REGEN3
VCC_SENSE
SYNCCLKOUT
Internal
32-KHz
RC
Control
outputs
12-bit
ADC
POWERGOOD
ADCIN1
ADCIN2
Osc.
VCC internal
supply
Low noise
LDO5
100 mA
VBG
Bypass
LDO1
300 mA
Bypass
LDO2
300 mA
LDO3
200 mA
LDO4
200 mA
C7
REFGND
Reference
and bias
VSYS
C18
C19
C20
C21
C22
C23
C24
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5.3 Device State Machine
The TPS65917-Q1 device integrates an embedded power controller (EPC) that fully manages the state of
the device during power transitions. According to the four defined types of requests (ON, OFF, WAKE,
and SLEEP), the EPC executes one of the five predefined power sequences (OFF2ACT, ACT2OFF,
SLP2OFF, ACT2SLP, and SLP2ACT) to control the state of the device resources. Any resource can be
included in any power sequence. When a resource is not controlled or configured through a power
sequence, the resource is left in the default state as pre-programmed by the OTP.
Each resource is only configured through register bits. Therefore, the user can statically control the
resource through the control interfaces (I2C or SPI), or the EPC can automatically control the resource
during power transitions which are predefined sequences of registers accesses.
The EPC is powered by an internal LDO which is automatically enabled when VSYS is available to the
device. Ensuring that the VSYS pin (which is connected to VCCA, VCC_SENSE, SMPSx_In and LDOx_IN
as suggested in the device block diagram) is the first supply available to the device is important to ensure
proper operation of all the power resources provided by the device. Ensuring that the VSYS pin is stable
prior to the VIO supply becoming available is important to ensure proper operation of the control interface
and device IOs.
5.3.1 Embedded Power Controller
The EPC is composed of the following three main modules:
•
•
An event arbitration module that is used to prioritize ON, OFF, WAKE, and SLEEP requests.
A power state-machine that is used to determine which power sequence to execute based on the
system state (supplies, temperature, and so forth) and requested transition (from the event arbitration
module).
•
A power sequencer that fetches the selected power sequence from OTP and executes the sequence.
The power sequencer sets up and controls all resources accordingly, based on the definition of each
sequence.
图 5-1 shows the EPC block diagram.
Power
sequence
pointer
ON requests
Resources
Resources
Resources
OFF requests
SLEEP requests
WAKE requests
Events
arbitration
Event
Power
state-machine
Power
sequence
System state
(supplies,
temperature, ...)
Power
sequences
OFF2ACT
ACT2OFF
SLP2OFF
ACT2SLP
SLP2ACT
图 5-1. EPC Block Diagram
The power state-machine is defined through the following states:
NO SUPPLY The device is not powered by a valid energy source on the system power rail (VCCA <
POR).
BACKUP
OFF
The device is powered by a valid supply on the system power rail which is above power-on
reset (POR) threshold but below the system low threshold (POR < VCCA < VSYS_LO).
The device is powered by a valid supply on the system power rail (VCCA > VSYS_LO) and
is waiting for a start-up event or condition. All device resources, except VRTC, are in the
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OFF state.
ACTIVE
SLEEP
The device is powered by a valid supply on the system power rail (VCC_SENSE >
VSYS_HI) and has received a start-up event. The device has switched to the ACTIVE state
and has full capacity to supply the processor and other platform modules.
The device is powered by a valid supply on the system power rail (VCCA > VSYS_LO) and
is in low-power mode. All configured resources are set to the low-power mode, which can be
ON, SLEEP, or OFF depending on the specific resource setting. If a given resource is
maintained active (ON) during low-power mode, then all linked subsystems are automatically
maintained active.
图 5-2 shows the state diagram for the power control state-machine.
NO SUPPLY
VCCA > POR_threshold
VCCA < POR
BACKUP
VCCA < POR
VCCA > VSYS_LO
VCCA < VSYS_LO
VCCA < POR
VCCA < VSYS_LO
OFF
VCCA < VSYS_LO
ON request and
VCC_SENSE > VSYS_HI
OFF request
ACTIVE
OFF request
WAKE request
SLEEP request
SLEEP
图 5-2. State Diagram for the Power Control State-Machine
Power sequences define how a resource state switches between the OFF, ACTIVE, and SLEEP states,
but these sequences have no effect during the NO SUPPLY or BACKUP states. When the device is
brought into the OFF state from a NO SUPPLY or BACKUP state, internal hardware manages the state
transition automatically before the EPC takes control of the device power sequencing as the device arrives
the OFF state.
The allowed power transitions include the following:
•
•
OFF to ACTIVE (OFF2ACT)
ACTIVE to OFF (ACT2OFF)
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•
•
•
ACTIVE to SLEEP (ACT2SLP)
SLEEP to ACTIVE (SLP2ACT)
SLEEP to OFF (SLP2OFF)
Each power transition consists of a sequence of one or several register accesses that controls the
resources according to the EPC supervision. Because these sequences are stored in nonvolatile memory
(OTP), these sequences cannot be altered.
As an additional safety feature, an error detection routine of the OTP bit integrity is available with this
device. If enabled, this routine is executed to compare the current OTP values with the preprogrammed
values at the beginning of every OFF2ACT power sequence. When an OTP bit integrity error is detected,
the OTP register, CRC_CONTROL, can be preprogramed to select the following options:
•
•
•
Skip Error Detection and execute all power sequence
Execute Error Detection and execute all power-up sequence, even if an error is detected
Execute Error Detection. If an error is detected, execute power-up sequence until the VIO supply rail is
up
•
Execute Error Detection. If an error is detected, stop power-up sequence altogether
When an error is detected, an interrupt (INT2.OTP_ERROR) is sent to the host processor regardless of
the CRC_CONTROL setting.
5.3.2 State Transition Requests
5.3.2.1 ON Requests
ON requests are used to switch on the device, which transitions the device from the OFF to the ACTIVE
state. 表 5-1 lists the ON requests.
表 5-1. ON Requests
EVENT
MASKABLE
POLARITY
COMMENT
DEBOUNCE
PWRON (pin)
No
Low
Level sensitive
N/A
Yes (INTx_MASK register.
Default: Masked)
Part of interrupts (event)
POWERHOLD (pin)
Event
High
Edge sensitive
Level sensitive
N/A
No
3 - 5 ms typical
If one of the events listed in 表 5-1 occurs, the event powers on the device unless one of the gating
conditions listed in 表 5-2 is present. 表 5-12 lists interrupt sources that can be configured as ON
requests.
表 5-2. ON Requests Gating Conditions
EVENT
MASKABLE
POLARITY
Low
COMMENT
VSYS_HI (event)
HOTDIE (event)
PWRDOWN (pin)
RESET_IN (pin)
No
No
No
No
VCC_SENSE < VSYS_HI
High
Device temperature exceeds the HOTDIE level
OTP configurable
OTP configurable
—
—
5.3.2.2 OFF Requests
OFF requests are used to switch off the device, meaning a transition from SLEEP or ACTIVE to OFF
state. 表 5-3 lists the OFF requests. OFF requests have the highest priority, which means these requests
have no gating conditions. Any OFF request is executed even though a valid SLEEP or ON request is
present. The device goes to the OFF state and then, when the OFF request is cleared, the device reacts
to an ON request, if one occurs.
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表 5-3. OFF Requests
MASKAB
SWITCH OFF
RESET
EVENT
POLARITY
DEBOUNCE
RESET LEVEL(2)
OTP configurable
OTP configurable
OTP configurable
OTP configurable
LE
DELAY(1)
SEQUENCE(3)
PWRON (pin)
(long press key)
No
Low
OTP configurable
N/A
LPK_TIME (OTP)
SWOFF_DLY
OTP configurable
OTP configurable
OTP configurable
OTP configurable
PWRDOWN
(pin)
WATCHDOG TIMEOUT(4)
(internal event)
No
N/A
No
SWOFF_DLY
SWOFF_DLY
0
N/A
N/A
THERMAL SHUTDOWN
(internal event)
N/A
1 ms for ACT2OFF
26 ms for
RESET_IN
(pin)
No
OTP configurable
SWOFF_DLY
OTP configurable
OTP configurable
OFF2ACT
SW_RST
(register bit)
DEV_ON(5)
(register bit)
No
No
No
N/A
N/A
N/A
N/A
N/A
0
0
0
OTP configurable
SWORST
OTP configurable
SD
VSYS_LO
(internal event)
OTP configurable
OTP configurable
POWERHOLD(6)
(pin)
No
Low
N/A
0
SWORST
SD
GPADC_SHUTDOWN
Yes
N/A
SWOFF_DLY
OTP configurable
OTP configurable
(1) SWOFF_DLY is the same for all requests. When configured (in the PMU_CONFIG register) to a specific value (0, 1, 2, or 4 s), the value
is applied to all OFF requests.
(2) The reset level is selectable as HWRST (a wide set of registers is reset to default values) or SWORTS (a more limited set of registers is
reset). See 节 5.3.7.
(3) The OFF requests in the reset sequence are configured to force the EPC to execute either a shutdown (SD) or a cold restart (CR).
Configuration occurs in the SWOFF_COLDRST register.
•
When configured to generate a shutdown, the EPC executes a transition to the OFF state (SLP2OFF or ACT2OFF power sequence)
and remains in the OFF state.
•
When configured to generate a cold restart, the EPC executes a transition to the OFF state (SLP2OFF or ACT2OFF power
sequence) and restarts, transitioning to the ACTIVE state (OFF2ACT power sequence) if none of the ON request gating conditions
are present.
(4) The watchdog is disabled by default. Software can enable watchdog and lock (write protect) watchdog register (WATCHDOG).
(5) The DEV_ON event has a lower priority than other ON events, meaning that DEV_ON forces the device to go to the OFF state only if no
other ON conditions keep the device active (POWERHOLD).
(6) The POWERHOLD event has a lower priority than other ON events, meaning that POWERHOLD forces the device to go to the OFF
state only if no other ON conditions keep the device active (DEV_ON).
5.3.2.3 SLEEP and WAKE Requests
The device transitions from the ACTIVE to the SLEEP state after receiving a SLEEP request. Upon this
request, internal resources as well as user-defined resources will enter the low-power mode as predefined
by the user. The states of the resources during ACTIVE and SLEEP states are defined in the LDO*_CTRL
and SMPSx_CTRL registers.
表 5-4 lists the SLEEP requests. Any of theses events trigger the ACT2SLP sequence unless pending
interrupts (unmasked) are present. Once the device enters the SLEEP state, only an interrupt or an
NSLEEP signal can generate a WAKE request to wake up the device (exit from the SLEEP state). A
WAKE request (only during the SLEEP state) wakes up the device and triggers a SLP2ACT or a
SLP2OFF power sequence.
表 5-4. SLEEP Requests
EVENT
MASKABLE
POLARITY
COMMENT
NSLEEP (pin)
Yes (Default: Masked)
Low
Level sensitive
For each resource, a transition from the ACTIVE state to the SLEEP state or from the SLEEP state to the
ACTIVE state is controlled in two different ways which are described as follows:
•
Through EPC sequencing (ACT2SLP or SLP2ACT power sequence) when the resource is associated
to the NSLEEP signal.
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•
Through direct control of the resource power mode (ACTIVE or SLEEP) in which case the user can
bypass SLEEP and WAKE sequencing by having resources assigned to two external control signals
(ENABLE1 and ENABLE2). These signals have a direct control on the power modes (ACTIVE or
SLEEP) of any resources associated to them and they trigger an immediate switch from one mode to
the other, regardless of the EPC sequencing.
Therefore, all resources can be associated to three external pins (NSLEEP, ENABLE1, and ENABLE2)
and can switch between the SLEEP and ACTIVE states. 表 5-5 outlines the type of state transition each
resource undergoes according to the logic combination of the NSLEEP, ENABLE1 and ENABLE2
assignments.
表 5-5. Resources SLEEP and ACTIVE Assignments(1)
ENABLE1
ASSIGNMENT
ENABLE2
ASSIGNMENT
NSLEEP
ENABLE1
ENABLE2
NSLEEP
STATE
TRANSITION
None
ASSIGNMENT PIN STATE PIN STATE PIN STATE
0
0
0
1
Don't care
Don't care
Don't care
Don't care
Don't care
ACTIVE
SLEEP ↔
ACTIVE
0
0
0 ↔ 1
Sequenced
SLEEP ↔
ACTIVE
0
0
1
1
1
1
0
0
0
1
0
1
Don't care
Don't care
0 ↔ 1
0 ↔ 1
Don't care
Immediate
SLEEP ↔
ACTIVE
0
1
0 ↔ 1
Sequenced
None
0 ↔ 1
ACTIVE
SLEEP ↔
ACTIVE
0 ↔ 1
0 ↔ 1
Don't care
0
1
Immediate
None
ACTIVE
SLEEP ↔
ACTIVE
Don't care
Immediate
SLEEP ↔
ACTIVE
0
1
0 ↔ 1
Sequenced
None
0 ↔ 1
ACTIVE
Don't care
SLEEP ↔
ACTIVE
0 ↔ 1
0 ↔ 1
0
0
1
Immediate
None
ACTIVE
SLEEP ↔
ACTIVE
0 ↔ 1
Immediate
None
1
0 ↔ 1
ACTIVE
1
1
0
Don't care
SLEEP ↔
ACTIVE
0 ↔ 1
0 ↔ 1
0
0
1
0
Immediate
None
ACTIVE
SLEEP ↔
ACTIVE
0 ↔ 1
Sequenced
0
1
1
1
0
1
0 ↔ 1
0 ↔ 1
0 ↔ 1
ACTIVE
ACTIVE
ACTIVE
None
None
None
SLEEP ↔
ACTIVE
0
0 ↔ 1
0
Immediate
0
1
1
0 ↔ 1
0 ↔ 1
0 ↔ 1
1
0
1
ACTIVE
ACTIVE
ACTIVE
None
None
None
1
1
1
SLEEP ↔
ACTIVE
0 ↔ 1
0
0
Immediate
0 ↔ 1
0 ↔ 1
0 ↔ 1
0
1
1
1
0
1
ACTIVE
ACTIVE
ACTIVE
None
None
None
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(1) Notes:
–
The polarity of the NSLEEP, ENABLE1, and ENABLE2 signals is configurable through the POLARITY_CTRL register. By default:
–
ENABLE1 and ENABLE2 are active high, meaning a transition from 0 to 1 requests a transition from SLEEP state to ACTIVE
state.
–
NSLEEP is active low, meaning a transition from 1 to 0 requests a transition from ACTIVE state to SLEEP state.
–
–
–
–
Resource assignments to the NSLEEP, ENABLE1, and ENABLE2 signals are configured in the ENABLEx_YYY_ASSIGN and
NSLEEP_YYY_ASSIGN registers (where x = 1 or 2 and YYY = RES, SMPS, or LDO).
Several resources can be assigned to the same ENABLE signal (ENABLE1 or ENABLE2) and therefore, when triggered, they all
switch their power mode at the same time.
When resources are assigned only to the NSLEEP signal, the respective switching order is controlled and defined in the power
sequence.
When a resource is not assigned to any signal (NSLEEP, ENABLE1, or ENABLE2), it never switches from the ACTIVE state to the
SLEEP state. The resource always remains in ACTIVE mode.
5.3.3 Power Sequences
A power sequence is an automatic preprogrammed sequence the TPS65917-Q1 device configures its
resources, which include the states of the SMPSs, LDOs, 32-kHz clock, and part of the GPIOs (REGEN
signals). For a detailed description of the GPIOs signals, please refer to 节 5.9.
图 5-3 shows an example of an OFF2ACT transition followed by an ACT2OFF transition. The sequence is
triggered through PWRON pin and the resources controlled (for this example) are: SMPS3 (VIO), LDO1,
SMPS2, LDO2, REGEN1, LDO5, and LDO3. The time between each resource enable and disable (TinstX)
is also part of the preprogrammed sequence definition.
When a resource is not assigned to any power sequence, it remains in off mode. The user (through
software) can enable and configure this resource independently when the power sequence completes.
OFF2ACT power sequence
ACT2OFF power sequence
X
X
X
X
PWRON
SMPS3
LDO1
Tinst16
Tinst15
Tinst1
Tinst2
Tinst3
Tinst4
Tinst5
Tinst6
SMPS2
Tinst14
LDO2
REGEN1
LDO5
Tinst13
Tinst12
Tinst11
LDO3
Tinst7
Tinst8
Tinst10
Tinst9
SYNCCLKOUT
RESET_OUT
INT
PWRON_IT = 1
Interrupt Acknowledge
Interrupt Acknowledge
PWRON_IT = 1
图 5-3. Power Sequence Example
As the power sequences of the TPS65917-Q1 device are defined according to the processor
requirements, the total time for the completion of the power sequence will vary across various system
definitions.
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5.3.4 Device Power Up Timing
图 5-4 shows the timing diagram of the TPS65917-Q1 after the first supply detection.
VCC_SENSE
VRTC
RC 32kHz
t
1
VIO
RESET_OUT
t
2
图 5-4. TPS65917-Q1 Power-Up Sequence After FSD
The time t1 is the delay from VCC crossing the POR threshold to VIO rising up. The time t1 must be at
least 6 ms. If the time from VCC to VIO is less than 6 ms, the VIO buffers will be supplied while the OTP
is still being initialized, which could cause glitches on any VIO output buffer. Supplying VIO at least 6 ms
after supplying VCC ensures that the OTP is initialized and output buffers are held low when VIO is
supplied.
The time t2 is the delay between the start of the power-up sequence and the RESET_OUT release. The
RESET_OUT resource is released when the power-up sequence is complete. The duration of the power-
up sequence depends on OTP programming.
5.3.5 Power-On Acknowledge
The PMIC is designed to support the following power-on acknowledge modes: POWERHOLD mode and
AUTODEVON mode.
5.3.5.1 POWERHOLD Mode
In POWERHOLD mode, the power-on acknowledge is received through a dedicated pin, POWERHOLD.
When an ON request is received, the device initiates the power-up sequence and asserts the
RESET_OUT pin high while the device is in the ACTIVE state (reset released). The device remains in
ACTIVE state for a fixed delay of 8 seconds and then automatically shuts down. During this timeframe, to
keep the device active, the host processor must assert and keep the POWERHOLD pin high. The device
interprets a the high to low transition of the POWERHOLD pin as an OFF request.
图 5-5 shows the POWERHOLD mode timing diagram.
Switch-on
event
Device maintained
ACTIVE for 8 seconds
Device switch off starts
with no delay
Power-up sequence
RESET_OUT
POWERHOLD
图 5-5. POWERHOLD Mode Timing Diagram
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5.3.5.2 AUTODEVON Mode
In AUTODEVON mode, at the end of the power-up sequence, the DEV_CTRL.DEV_ON register bit is
automatically set to 1 and the device remains in the ACTIVE state until the host processor clears this bit.
No dedicated signal from processor is required to maintain the PMIC in the ACTIVE state.
图 5-6 and 图 5-7 show the AUTODEVON mode timing diagrams.
Switch-on
event
Device maintained
ACTIVE for 8 seconds
Device switch off starts
with no delay
Power-up sequence
RESET_OUT
DEV_ON
I2C-SPI access
图 5-6. AUTODEVON Mode Timing Diagram
The DEV_ON bit can also be configured so that it is not auto-updated (set to 1) at the end of the power-up
sequence. In this case, the device functions similarly to when it is in the POWERHOLD mode, except that
the host has control over the device using the DEV_CTRL.DEV_ON register bit instead of the
POWERHOLD pin. Therefore, to maintain the device in the ACTIVE state, the host must set and keep this
bit at 1.
Switch-on
event
Device maintained
ACTIVE for 8 seconds
Device switch off starts
with no delay
Power-up sequence
RESET_OUT
DEV_ON
I2C-SPI access
I2C-SPI access
图 5-7. DEV_ON Mode Timing Diagram
5.3.6 BOOT Configuration
All TPS65917-Q1 resource settings are stored in registers. Therefore, any platform-related settings are
linked to an action which alters these registers. This action is either a static update (register initialization
value) or a dynamic update of the register (from the user or a power sequence).
Resources and platform settings are stored in nonvolatile memory (OTP). These settings are defined as
follows:
Static platform settings These settings define, for example, the SMPS and LDO default voltages, GPIO
functionality, and TPS65917-Q1 switch-on events.
Sequence platform settings These settings define TPS65917-Q1 power sequences between state
transitions An example includes the OFF2ACT sequence when transitioning from OFF state
to ACTIVE state. Each power sequence is composed of several register accesses that
define the resources (and the corresponding registers) that must be updated during the
respective state transition. Small modifications from the main sequence can be defined with
the BOOT pin as long as the OTP memory size constraint is respected. The user can
overwrite these settings when the power sequence completes.
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Static
platform
settings
Platform settings
are modifiable by
microcontroller
during OFF,
ACTIVE, and
SLEEP transition
(Default config for
all boot; I/O mux,
default voltage)
Reload during
OFF state transition
(According to respective reset
domain SWORST / HWRST)
Selectable
platform
settings
Switch ON event,
supply threshold
Power IC
Initialization done at reset
Resource
configuration and
control registers
RD
BOOT
RD
Microcontroller
Voltage modification,
resource
enable and disable
Registers updates during
OFF, ACTIVE, and SLEEP
transition
Sequence
Platform
Settings
(State transition
microprogram)
图 5-8. Boot Pins Control
5.3.6.1 Boot Pin Usage and Connection
表 5-6 lists the associated configurations of the boot pins.
表 5-6. Boot Pins Associated Configurations
BOOT
OTP CONFIGURATION
OTP5 (0x00~0x2F)
OTP5 (0x30~0x5F)
POWER SEQUENCE SELECTOR
0
1
Sel_0
Sel_1
The BOOT pin must be grounded or pulled up.
The status of the BOOT pin is latched at the end of the transition from OFF to ACTIVE mode and stored in
the BOOT_STATUS register.
The BOOT pin can also be used as static selectors during execution of the power sequence. This static
selection provides from within a static power sequence, to branch to different instructions. This static
selection allows the selection of power sequences (or subpart of power sequences) without altering the
power sequences themselves in OTP.
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5.3.7 Reset Levels
The TPS65917-Q1 resource control registers are defined by the following three categories:
•
•
•
Power-on request (POR) registers
Hardware (HW) registers
Switchoff (SWO) registers
These registers are associated to three levels of reset which are described as follows
Power-on reset (POR) A POR occurs when the device receives supplies and transition from the NO
SUPPLY state to the BACKUP state. The POR is the global device reset which resets all
registers.
The values of the registers in this domain will retain their value under HWRST and SWORST
event. This ensures the information which contains the cause of the switch off event is
retained when the device is reset to its default operating state.
The following registers are reset only during POR event:
•
•
•
•
•
SMPS_THERMAL_STATUS
SMPS_SHORT_STATUS
SMPS_POWERGOOD_MASK
LDO_SHORT_STATUS
SWOFF_STATUS
This list is indicative only; a full list and bit details can be found in the TPS65917-Q1 Register
Map (SLVUAH1).
Hardware reset (HWRST) A HWRST occurs when any OFF request is configured to generate a
hardware reset. Configuration of the reset level is programmed in the SWOFF_HWRST
register. This reset triggers a transition to the OFF state from either the ACTIVE or SLEEP
state, and therefore executes the ACT2OFF or SLP2OFF sequence.
A HWRST will reset all registers in the HWRST and the SWORST domain, but leave the
registers in the POR domain unchanged.
The following registers are in the HWRST domain:
•
•
•
•
•
•
•
•
•
SMPS control registers expect MODE_ACTIVE and MODE_SLEEP bits
LDO control registers expect MODE_ACTIVE and MODE_SLEEP bits
VSYS_LO Threshold
PMU_CONFIG & PMU_CTRL
NSLEEP, ENABLE1, and ENABLE2 resource assignment registers
Input and Output, including the GPIO pins, Configuration and Control registers
Interrupt Control, Status and Mask Registers
OTP CRC results register
GPADC Configuration and Results registers
This list is indicative only; a full list and bit details can be found in the TPS65917-Q1 Register
Map (SLVUAH1).
Switch-off reset (SWORST) A SWORST occurs when any OFF request is configured to not generate a
hardware reset. Configuration is done in the SWOFF_HWRST register. This reset acts like
the HWRST, except only the SWO registers are reset. The TPS65917-Q1 goes into the OFF
state, from either ACTIVE or SLEEP, and therefore executes the ACT2OFF or SLP2OFF
sequence.
A SWORST only resets registers in the SWORST domain, but leave the registers in the
HWRST and POR domains unchanged.
The following registers are in the SWORST domain:
•
•
•
•
•
•
SMPS control registers for voltage levels and operating mode control
LDO control registers for voltage levels and operating mode control
DEV_CTRL & POWER_CTRL registers
VSYS_MON enable and result register
WATCHDOG configuration register
PLL and REGEN Control registers
This list is indicative only; a full list and bit details can be found in the TPS65917-Q1 Register
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Map (SLVUAH1).
表 5-7 lists the reset levels, and 图 5-9 shows the reset levels versus registers.
表 5-7. Reset Levels
LEVEL
RESET TAG
REGISTERS AFFECTED
COMMENT
0
POR
POR, HW, SWO
This reset level is the lowest level, for which all registers are reset.
During hardware reset (HWRST), all registers are reset except the POR
registers.
1
2
HWRST
HW, SWO
SWO
SWORST
Only the SWO registers are reset.
POR reset
HWRST reset
SWORST reset
POR registers
HW registers
SWO registers
图 5-9. Reset Levels versus Registers
5.3.8 INT
The INT output is the interrupt request to the processor. By default, the INT pin is push-pull output and
active low (when interrupt is pending, output is driven low). By default, the line is masked when the PMIC
is in sleep state (configurable by setting the INT_MASK_IN_SLEEP bit). Individual interrupt sources can
be masked according to 表 5-12 .
5.3.9 Warm Reset
The TPS65917-Q1 device can execute a warm reset. The main purpose of this reset is to recover the
device from a locked or unknown state by reloading default configuration. The warm reset is triggered by
the NRESWARM pin. During a warm reset, the OFF2ACT sequence is executed regardless of the state
(ACTIVE or SLEEP) and the device returns to or remains in the ACTIVE state. Resources that are not part
of the OFF2ACT sequence are not impacted by a warm reset and retain the previous state. Resources
that are part of power-up sequence go to active mode, and output voltage level is reloaded from OTP or
kept in the previous value depending on the WR_S bit in the SMPSx_CTRL or LDOx_CTRL register.
5.3.10 RESET_IN
The RESET_IN function causes a switch-off event (either a cold reset or shutdown). 表 5-3 shows that the
RESET_IN behavior is programmable. The RESET_IN input has a 1-ms debounce that is independent of
the selected polarity. In addition, after the device goes into the OFF state, a 25-ms masking period occurs
before a new RESET_IN event is accepted, which is equivalent to a 26-ms debounce for an OFF2ACT
request.
5.4 Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
The power resources provided by the TPS65917-Q1 device include inductor-based SMPSs and linear
LDOs. These supply resources provide the required power to the external processor cores, external
components, and to modules embedded in the TPS65917-Q1 device. 表 5-8 lists the power resources
provided by the TPS65917-Q1 device.
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表 5-8. Power Resources
RESOURCE
TYPE
VOLTAGE
CURRENT
COMMENTS
0.7 to 1.65 V, 10-mV steps
1 to 3.3 V, 20-mV steps
Can be used as 1 dual-phase (7 A) or 2
single-phase (3.5 A) regulators
SMPS1, SMPS2
SMPS
7 A
0.7 to 1.65 V, 10-mV steps
1 to 3.3 V, 20-mV steps
SMPS3
SMPS4
SMPS5
SMPS
SMPS
SMPS
3 A
1.5 A
2 A
0.7 to 1.65 V, 10-mV steps
1 to 3.3 V, 20-mV steps
0.7 to 1.65 V, 10-mV steps
1 to 3.3 V, 20-mV steps
LDO1, LDO2
LDO3
LDO
LDO
LDO
LDO
0.9 to 3.3 V, 50-mV steps
0.9 to 3.3 V, 50-mV steps
0.9 to 3.3 V, 50-mV steps
0.9 to 3.3 V, 50-mV steps
300 mA
200 mA
200 mA
100 mA
LDO4
LDO5
Low-noise LDO
5.4.1 Step-Down Regulators
The synchronous step-down converter used in the power-management core has high efficiency while
enabling operation with cost-competitive and small external components. The SMPSx_IN supply pins of all
the converters should be individually connected to the VSYS supply (VCCA pin). Two of these
configurable step-down converters can be multiphased to create up to a 7-A rail. All of the step-down
converters can synchronize to an external clock source between 1.7 MHz and 2.7 MHz, or an internal
fallback clock at 2.2 MHz.
The step-down converter supports two operating modes, which can be selected independently. These two
operating modes are defined as follows:
Forced PWM mode: In forced PWM mode, the device avoids pulse skipping and allows easy filtering of
the switch noise by external filter components. The drawback is the higher IDDQ at low-
output current levels.
Eco-mode (lowest quiescent-current mode): Each step-down converter can be individually controlled
to enter a low quiescent-current mode. In ECO-mode, the quiescent current is reduced and
the output voltage is supervised by a comparator while most of the control circuitry disabled
to save power. The regulators should not be enabled under ECO-mode to ensure the
stability of the output. ECO-mode should only be enabled when a converter has less than 5
mA of load current and VO can remain constant. In addition, ECO-mode should be disabled
before a load-transient step to allow the converter to respond in a timely manner to the
excess current draw.
To ensure proper operation of the converter while it is in ECO-mode, the output voltage level must be less
then 70% of the input supply voltage level. If the VO of the converter is greater than 2.8 V, a safety feature
of the device monitors the supply voltage of the converter and automatically switch off the converter if the
input voltage falls below 4 V. The purpose of this safety mechanism is to prevent damage to the converter
because of design limitation while the converter is in ECO mode.
In addition to the operating modes, the following parameters can be selected for the regulators:
•
•
Powergood: See 节 5.4.1.3.
Output discharge: Each switching regulator is equipped with an output discharge enable bit. When this
bit is set to 1, the output of the regulator is discharged to ground with the equivalent of a 9-Ω resistor
when the regulator is disabled. If the regulator enable bit is set, the discharge bit of the regulator is
ignored.
•
Output-current monitoring: The GPADC can monitor the SMPS output current. One SMPS at a time
can be selected for measurement from the following: SMPS1, SMPS2, SMPS1&2, SMPS3, and
SMPS5. Selection is controlled through the GPADC_SMPS_ILMONITOR_EN register.
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•
Enable control of the Step-down converters: The step-down converter enable and disable is part of the
flexible power-up and power-down state-machine. Each converter can be programmed such that it is
powered up automatically to a preselected voltage in one of the time slots after a power-on condition
occurs. Alternatively, each SMPS can be controlled by a dedicated pin. The NSLEEP, ENABLE1, and
ENABLE2 pins can be mapped to any resource (LDOs, SMPS converter, 32-kHz clock output, or
GPIO) to enable or disable the pin. Each SMPS can also be enabled and disabled through access to
the I2C registers.
5.4.1.1 Output Voltage and Mode Selection
One-time programmable (OTP) bits define the default output voltage and enabling of the regulator during
the start-up sequence.
After start up, while the SMPS is in forced PWM mode, software can change the output voltage by setting
the RANGE and VSEL bits in the SMPSx_VOLTAGE register. When the SMPS enters ECO mode, the
output voltage cannot be changed. Setting the SMPSx_VOLTAGE.VSEL register to 0x0 disables the
SMPS (turns off). The value for the RANGE bit cannot be changed when the SMPS is active. To change
the operating voltage range, the SMPS must be disabled.
The operating mode (ECO, forced PWM, or off) of an SMPS when the TPS65917-Q1 device is in ACTIVE
state can be selected in the SMPSx_CTRL register by setting the MODE_ACTIVE[1:0] bit field.
The operating mode of an SMPSx when the TPS65917-Q1 device is in the SLEEP state is controlled by
the MODE_SLEEP[1:0] bit field, depending on the SMPS assignment to the NSLEEP, ENABLE1, and
ENABLE2 pins (see 表 5-5).
The soft-start slew rate (t(ramp)) is fixed.
The pulldown discharge resistance for off mode is enabled and disabled in the SMPS_PD_CTRL register.
By default, discharge is enabled. Two pulldown resistors, one at SMPSx_SW and one at SMPS_FDBK
node, are enabled or disabled together. For multiphase SMPS, pulldown is in the master phase.
SMPS behavior for warm reset (reload default values or keep current values) is defined by the
SMPSx_CTRL.WR_S bit.
5.4.1.2 Clock Generation for SMPS
In PWM mode, the SMPSs are synchronized on an external input clock, SYNCDCDC (muxed with
GPIO_3), whereas in ECO mode, the switching frequency is based on an internal RC oscillator.
For PWM mode, a PLL is present to buffer the external clock input from SYNCDCDC pin, and to create 5
clock signals for the 5 SMPSs with different phases.
图 5-10 shows the frequency of SYNCDCDC input clock (fSYNC) and the frequency of PLL output signal
(fSW).
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tSETTLE
fSAT,HI
fA
fSW
fFALLBACK
fSAT,LO
fSAT,HI
fA
tSETTLE
fSYNC
fSAT,LO
No Clock
图 5-10. Synchronized Clock Frequency
When no clock is present on the SYNCDCDC pin, the PLL generates a clock with a frequency equal to the
fallback frequency (fFALLBACK).
When a clock is present on the SYNCDCDC pin with a frequency between the low and high PLL
saturation frequencies (fSAT,LO and fSAT,HI), then the PLL is synchronized on the SYNCDCDC clock and
generates a clock with frequency equal to fSYNC
If fSYNC is higher than fSAT,HI, then the PLL generates a clock with a frequency equal to fSAT,HI
If fSYNC is smaller than fSAT,LO, then the PLL generates a clock with a frequency equal to fSAT,LO
.
.
.
Dithering can be achieved by changing the frequency of the clock provided on the SYNCDCDC pin. The
sync clock dither specification parameters are based on a triangular dither pattern, but other patterns that
comply with the minimum and maximum sync frequency range and the maximum dither slope can also be
used, as seen in 图 5-11.
MDITHER
tDITHER
fSYNC
ADITHER
fSYNC,MAX
fSYNC,MIN
t
图 5-11. Synchronized Clock Frequency Range and Dither
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5.4.1.3 Current Monitoring and Short Circuit Detection
SMPS1, SMPS2, SMPS1&2, and SMPS3 include several other features.
The SMPS sink current limitation is controlled with the SMPS_NEGATIVE_CURRENT_LIMIT_EN register.
The limitation is enabled by default.
Channel 4 of the GPADC can be used to monitor the output current of SMPS1, SMPS2, SMPS1&2,
SMPS3, or SMPS5. Load current monitoring is enabled for a given SMPS in the SMPS_ILMONITOR_EN
register. SMPS output-power monitoring is intended to be used during the steady state of the output
voltage, and is supported in PWM mode only.
Use 公式 1 to calculate the SMPS output-current result.
ILOAD = IFS × GPADC code / (212 – 1) – IOS
(1)
where
•
•
•
IFS= IFS0 × K
IOS = IOS0 × K
K is the number of SMPS active phases
Use 公式 2 to calculate the temperature compensated result.
ILOAD = IFS × GPADC code / ([212 – 1] × [1 + TC_R0 × (TEMP-25)]) – IOS
(2)
For the values of IFS0 and IOS0, see Section 4.10.
The SMPS thermal monitoring is enabled (default) and disabled with the SMPS_THERMAL_EN register.
When enabled, the SMPS thermal status is available in the SMPS_THERMAL_STATUS register.
SMPS12, SMPS3, and SMPS5 have thermal protection. A unique thermal sensor is shared and protecting
both SMPS1 and SMPS2. SMPS4 has no dedicated thermal protection.
Each SMPS has a detection for load current above ILIM, indicating overcurrent or a shorted SMPS output.
The SMPS_SHORT_STATUS register indicates any SMPS short condition. Depending on the setting of
the INT2_MASK.SHORT register, an interrupt is generated upon any shorted SMPS. If a short occurs on
any enabled SMPSs, the corresponding short status bit is set in the SMPS_SHORT_STATUS register. A
switch-off signal is then sent to the corresponding SMPS, and it remains off until the corresponding bit in
the SMPS_SHORT_STATUS register is cleared. This register is cleared on read, or by issuing a POR.
The same behavior applies to LDO shorts using the LDO_SHORT_STATUS registers.
A short must occur on any enabled SMPS or LDO for at least 155 us to 185 us for the short detection to
shut off the rail. During startup of the device, there is a 2 ms counter that masks any short-circuit
shutdown. This counter starts when the device is enabled and the counter is reset when any SMPSx or
LDOx rail becomes ACTIVE. When no rail has been enabled for 2 ms, the counter reaches its threshold
and the short-circuit shutdown is no longer masked for the enabled SMPSs and LDOs.
5.4.1.4 POWERGOOD
The TPS65917-Q1 device includes an external POWERGOOD pin which indicates if the outputs of the
SMPS are within the acceptable range of the programmed output voltage, and if the current loading for the
SMPS is within the range of the current limit. Users can select whether POWERGOOD reports the result
of both voltage and current monitoring or only current monitoring. This selection applies to all SMPSs in
the SMPS_POWERGOOD_MASK2 register.POWERGOOD_TYPE_SELECT register. When both the
voltage and current are monitored, the POWERGOOD signal indicates whether or not all SMPS outputs
are within a certain percentage, as specified by the VSMPSPG parameter, of the programmed value while
the load current is below ILIM
.
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All POWERGOOD sources can be masked in the SMPS_POWERGOOD_MASK1 and
SMPS_POWERGOOD_MASK2 registers. By default, only the SMPS1 rail (or SMPS12 rail if in dual
phase) is monitored. When an SMPS is disabled, it should be masked in the
SMPS_POWERGOOD_MASKx registers to prevent the SMPS from forcing the POWERGOOD pin to go
inactive. When the SMPS voltage is transitioning from one target voltage to another because of a DVS
command, voltage monitoring is internally masked and POWERGOOD is not impacted.
The GPADC result for SMPS output current monitoring can be included in POWERGOOD by setting the
SMPS_COMPMODE bit to 1. The GPADC can monitor only one SMPS.
图 5-12 is the block diagram of the circuitry which constructs the logic output of the POWERGOOD pin.
CAUTION
When operating in dual phase, the SMPS12 current monitor may cause
POWERGOOD to change to a low level (with default polarity) when
transitioning from dual phase operation to single phase operation. TI
recommends masking SMPS12 as
a
POWERGOOD source, using
SMPS_POWERGOOD_MASK1, or debouncing the POWERGOOD signal if this
POWERGOOD toggle is not desired in the application design.
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POWERGOOD_TYPE_SELECT
1
0
SMPS1 ILIM1
SMPS1 POWERGOOD1
SMPS_POWERGOOD_MASK[0]*
SMPS_POWERGOOD_MASK[1]
SMPS_POWERGOOD_MASK[3]
1
0
SMPS2 ILIM2
POWERGOOD
SMPS2 POWERGOOD2
1
0
SMPS3 ILIM3
SMPS3 POWERGOOD3
1
0
SMPS4 ILIM4
SMPS4 POWERGOOD4
SMPS_POWERGOOD_MASK[4]
SMPS_POWERGOOD_MASK[6]
1
0
SMPS5 ILIM5
SMPS5 POWERGOOD5
SMPS_ILMON_SEL
SMPS_COMPMODE
*When operating in dual phase, SMPS_POWERGOOD_MASK[0] controls the monitoring of SMPS12.
SMPS_POWERGOOD_MASK[1] is masked internally with dual phase operation.
图 5-12. POWERGOOD Block Diagram
5.4.1.5 DVS-Capable Regulators
The Step-down converters, SMPS1, SMPS2, or SMPS1&2 and SMPS3, are DVS-capable and have some
additional parameters for control. The slew rate of the output voltage during a voltage level change is fixed
at 2.5 mV/μs. The control for two different voltage levels (roof and floor) with the NSLEEP, ENABLE1, and
ENABLE2 signals is available. When the roof-floor control is not used (ROOF_FLOOR_EN = 0), the CMD
bit in the SMPSx_FORCE register can select two different voltage levels.
Below are the steps for programming two difference output voltage levels (roof and floor) for the DVS-
capable step-down converters:
•
The NSLEEP, ENABLE1, or ENABLE2 pins can be used for roof-floor control of SMPS. For roof-floor
operation, set the SMPSx_CTRL.ROOF_FLOOR_EN register, and assign SMPS to NSLEEP,
ENABLE1, and ENABLE2 in the NSLEEP_SMPS_ASSIGN, ENABLE1_SMPS_ASSIGN, and
ENABLE2_SMPS_ASSIGN registers, respectively. When the controlling pin is active, the value for the
SMPS output is defined by the SMPSx_VOLTAGE register. When the controlling pin is not active, the
value for the SMPS output is defined by the SMPSx_FORCE register.
•
Set the second value for the output voltage with the SMPSx_FORCE.VSEL register. Setting this
register to 0x0 turns off the SMPS.
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•
Select which register, SMPSx_VOLTAGE or SMPSx_FORCE, to use with the SMPSx_FORCE.CMD
bit. The default is the voltage setting of SMPSx_VOLTAGE. For the CMD bit to work, ensure that the
SMPSx_CTRL.ROOF_FLOOR_EN bit is set to 0.
图 5-13 shows the SMPS controls for DVS.
Voltage Control Through I2C
SMPSx_CTRL.ROOF_FLOOR_EN = 0
SMPSx_FORCE.VSEL, when SMPSx_FORCE.CMD = 0
SMPSx_VOLTAGE.VSEL(1), when SMPSx_FORCE.CMD = 1
SMPSx_VOLTAGE.VSEL
SMPSx_OUT
Discharge control (pulldown)
SMPS_PD_CTRL.SMPSx (disable/
enabled)
t
(ramp)
Tstart
I2C(2)
Voltage Control Through External Pin
SMPSx_CTRL.ROOF_FLOOR_EN = 1
SMPSx_VOLTAGE.VSEL (ACTIVE mode)
SMPSx_FORCE.VSEL (SLEEP mode)
SMPSx_VOLTAGE.VSEL
SMPSx_OUT
Discharge control (pulldown)
SMPS_PD_CTRL.SMPSx (disable/
enabled)
t
(ramp)
Tstart
EN(3)
(1) VSEL[6:0] (voltage selection):
SMPSx_VOLTAGE.RANGE = 0: OFF, 0.5 V to 1.65 V in 10-mV steps
SMPSx_VOLTAGE.RANGE = 1: 1 to 3.3 V in 20-mV steps
(2) I2C: Control through access to SMPSx_VOLTAGE, SMPSx_FORCE registers
(3) EN: Control through NSLEEP, ENABLE1, and ENABLE2 pins (see 表 5-5)
图 5-13. SMPS Controls for DVS
5.4.1.5.1 Non DVS-Capable Regulators
SMPS4 and SMPS5 are non-DVS-capable regulators. The slew rate of the output voltage is not controlled
internally, and the converter achieves the new output voltage in JUMP mode. When changes to the output
voltage are required, programming the changes to the output voltages of SMPS4 and SMPS5 at a rate
slower than 2.5 mV/μs is recommended to avoid voltage overshoot or undershoot.
5.4.1.6 Step-Down Converters SMPS1, SMPS2 or SMPS1&2
The step-down converters, SMPS1 and SMPS2, can be used in two different configurations which are
described as follows:
•
•
SMPS1 and SMPS2 in single-phase configuration with each SMPS supporting a 3.5-A load current
SMPS1&2 in dual-phase configuration supporting 7-A load current
SMPS1 and SMPS2 can be used as separate converters. In dual-phase configuration the two interleaved
synchronous buck-regulator phases with built-in current sharing operate in opposite phases. For light
loads, the converter automatically changes to single-phase operation.
图 5-14 shows the connections for dual-phase configurations.
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CIN1
VSYS
SMPS1_IN
L1
SMPS1_SW
SMPS1
[Master]
SMPS1_GND
Vapps1
CIN2
VSYS
COUT
SMPS2_IN
L2
SMPS2_SW
SMPS2
[Slave]
SMPS2_GND
SMPS1_FDBK
SMPS2_FDBK
图 5-14. SMPS1&2 Dual-Phase Configuration
Below are the steps to program the SMPS1 and SMPS2 for single-phase or dual-phase operation:
•
The OTP bit defines single-phase (SMPS1 and SMPS2) or dual-phase (SMPS1&2) operation. If dual-
phase mode is selected, the SMPS12 registers control SMPS1&2.
•
By default, SMPS1&2 operates in dual-phase mode for higher load currents and switches automatically
to single-phase mode for low load currents. Forcing multiphase operation or single-phase operation is
possible by setting the SMPS_CTRL.SMPS12_PHASE_CTRL[1:0] bits when the SMPS1&2 are
loaded. Under no-load condition, do not force the multiphase operation because it causes SMPS12 to
exhibit instability.
5.4.1.7 Step-Down Converters SMPS3, SMPS4, and SMPS5
SMPS3 is a buck converter supporting up to 3-A load current. SMPS4 and SMPS5 are also buck
converters, with SMPS4 supporting up to 1.5-A load current, and SMPS5 supporting up to 2-A load
current. SMPS3 is DVS-capable.
5.4.2 Low Dropout Regulators (LDOs)
All LDOs are integrated. They can be connected to the system supply, to an external buck boost SMPS,
or to another preregulated voltage source. The output voltages of all LDOs can be selected, regardless of
the LDO input voltage level, VIN. No hardware protection is available to prevent software from selecting an
improper output voltage if the VIN minimum level is lower than the total DC-output voltage (TDCOV(LDOx)
)
plus the dropout voltage ( DV(LDOx)). In such conditions, the output voltage is lower and nearly equal to the
input supply. The output voltage of the regulator cannot be modified while the LDO is enabled from one
voltage range (0.9 to 2.1 V) to the other voltage range (2.2 to 3.3 V). The regulator must be restarted in
these cases. If an LDO is not needed, the external components do not need to be mounted. The
TPS65917-Q1 device is not damaged by such configuration. The other functions do not depend on the
unused LDOs and work properly.
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5.4.2.1 LDOVANA
The LDOVANA voltage regulator is dedicated to supply the analog functions of the TPS65917-Q1 device,
such as the GPADC and other analog circuitry. The LDOVANA regulator is automatically enabled and
disabled as needed. The automatic control optimizes the overall current consumption if the SLEEP state.
5.4.2.2 LDOVRTC
The LDOVRTC regulator supplies always-on functions, such as wake-up functions. This power resource is
active as soon as a valid energy source is present.
This resource has two modes which are Normal mode and backup mode. The LDOVRTC regulator
functions in normal mode when supplied from the main system power rail and is able to supply all digital
components of the TPS65917-Q1 device. The LDOVRTC regulator functions backup mode when supplied
from system power rail that is above the power-on reset threshold but below the system low threshold and
is only able to supply always-on components.
The LDOVRTC regulator supplies the digital components of the TPS65917-Q1 device. In the BACKUP
state, the digital activity is reduced to maintaining the wake up functions only. In the OFF state, the turn-on
events and detection mechanism are added to the previous current load in the BACKUP state. In the
BACKUP and OFF states, the external load on the LDOVRTC pin should not exceed 0.5 mA.
In the ACTIVE state, the LDOVRTC switches automatically into active mode. The reset is released and
the clocks are available. In SLEEP state, the LDOVRTC is kept active. The reset is released and only the
32-kHz clock is available. To reduce power consumption, the user is still able to select low-power mode
through the software.
注
If VCC is discharged rapidly and then resupplied, a POR may not be reliably generated. In
this case a pulldown resistor can be added on the LDOVRTC output. See 节 5.15 for details.
5.4.2.3 LDO1 and LDO2
The LDO1 and LDO2 regulators have bypass capability to connect the input voltage to the output. This
ability is useful, for example, as an input-output (I/O) supply of an SD card and preregulated with a 2.7 to
3.3 V supply. This ability allows switching between 1.8 V (normal LDO mode) and the preregulated supply
(bypass mode).
5.4.2.4 Low-Noise LDO (LDO5)
LDO5 is specifically designed to supply noise sensitive circuits. This supply can be used to power circuits
such as PLLs, oscillators, or other analog modules that require low noise on the supply.
5.4.2.5 Other LDOs
All other LDOs have the same output voltage capability which is from 0.9 to 3.3 V in 50-mV steps.
5.5 SMPS and LDO Input Supply Connections
To avoid leakage, all SMPSx_IN supply pins and the VCCA pin must be externally connected together.
The LDO preregulation from a boosted supply (voltage at LDOx_IN > voltage at VCCA) is supported if the
output voltage of the LDO is 2.2 V (minimum).
5.6 First Supply Detection
The TPS65917-Q1 device can be configured to detect and wake up from a first supply-detection (FSD)
event.
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When an automatic start from an FSD event is enabled, the PMIC powers up automatically when a supply
is inserted, without waiting for a PWRON button press or other start-up event. An FSD event is detected
when the VCCA pin voltage increases above the VSYS_LO threshold. Transition to ACTIVE state requires
that the VCC_SENSE voltage increases above the VSYS_HI voltage.
The FSD feature is enabled through unmasking the corresponding interrupt. This event triggers the
interrupt, FSD, to the interrupt (INT) line. When an FSD interrupt occurs, the source can be determined
using the FSD_STATUS bit in the PMU_SECONDARY_INT register. An interrupt from an FSD event, if
not masked, is a wake-up event. Interrupt masking is pre-programmed in the one time programmable
memory (OTP) of the device. Any HWRST event sets the interrupt mask bits to the default (OTP) value.
The FSD event can also be masked through the PMU_SECONDARY_INT register by setting the
FSD_MASK bit.
5.7 Long-Press Key Detection
The TPS65917-Q1 device can detect a long press on a key (or pin), PWRON. Upon detection, the device
generates a LONG_PRESS_KEY interrupt and then switches the system off. The key-press duration is
configured through the LONG_PRESS_KEY.LPK_TIME bits.
5.8 12-Bit Sigma-Delta General-Purpose ADC (GPADC)
The features of the GPADC include the following:
The GPADC consists of a 12-bit sigma-delta ADC combined with a 8-input analog multiplexer. The
running frequency of the GPADC is 2.5MHz. The GPADC lets the host processor monitor analog signals
using analog-to-digital conversion on the input source. After the conversion is complete, an interrupt is
generated to signal the host processor that the result of the conversion is ready to be accessed through
the I2C interface.
The GPADC supports 8 analog inputs. Two of these inputs are available on external pins and the
remaining inputs are dedicated to VSYS supply voltage monitoring and internal resource monitoring.
图 5-15 shows the block diagram of the GPADC.
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ADC voltage reference
ADCIN1
ch0
ch1
ch2
ch3
ADCIN2
Reserved
VCC_SENSE
Software
conversion result
12-bit sigma-
delta ADC
DC-DC current probe
ch4
ch5
PMIC internal die temperature 1
PMIC internal die temperature 2
Test network
ch6
ch7
AUTO conversion result
AUTO conversion request
Software conversion request
Interrupt
ADC control
图 5-15. Block Diagram of the GPADC
The conversion requests are initiated by the host processor either by software through the I2C or by
periodical measurements.
Two kinds of conversion requests occur with the following priority:
1. Asynchronous conversion request (SW), see 节 5.8.1
2. Periodic conversion (AUTO), see 节 5.8.2
表 5-9 lists the GPADC channel assignments.
Use 公式 3 to convert from the GPADC code to the internal die temperature using GPADC channels 5 and
6.
≈
’
GPADC Code
212
»
…
ÿ
ì 1.25 - 0.753 V
∆
÷
Ÿ
⁄
«
◊
Die Temperature (èC) =
2.64 mV
(3)
表 5-9. GPADC Channel Assignments
INPUT VOLTAGE
FULL RANGE
INPUT VOLTAGE
CHANNEL
TYPE
SCALER
OPERATION
(1)
PERFORMANCE RANGE(2)
0 (ADCIN1)
1 (ADCIN2)
2
External(3)
External(3)
Reserved
0 to 1.25 V
0 to 1.25 V
0.01 to 1.215 V
0.01 to 1.215 V
No
No
General purpose
General purpose
(1) The minimum and maximum voltage full range corresponds to typical minimum and maximum output codes (0 and 4095).
(2) The performance voltage is a range where gain error drift, offset drift, INL and DNL parameters are ensured.
(3) If VANALDO is off, maximum current to draw from GPADC_INx is 1 mA for reliability. For current higher than 1 mA, LDOVANA must be
in the SLEEP or ACTIVE state.
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表 5-9. GPADC Channel Assignments (continued)
INPUT VOLTAGE
FULL RANGE
INPUT VOLTAGE
TYPE
SCALER
OPERATION
PERFORMANCE RANGE(2)
(1)
2.5 to 5 V when
2.5 to 4.86 V when
HIGH_VCC_SENSE = 0
2.3 V to (VCCA – 1 V) when
HIGH_VCC_SENSE = 1
3
HIGH_VCC_SENSE = 0
2.3 V to (VCCA – 1 V) when
HIGH_VCC_SENSE = 1
System supply voltage
(VCC_SENSE)
Internal
4
(VCC_SENSE)
4
5
Internal
Internal
0 to 1.25 V
No
No
DC-DC current probe
PMIC internal die
temperature 1
0 to 1.25 V
0 to 1.215 V
PMIC internal die
temperature 2
6
7
Internal
Internal
0 to 1.25 V
0 to 1.215 V
No
5
0 to VCCA V
0.055 to VCCA V
Test network
5.8.1 Asynchronous Conversion Request (SW)
The user can request an asynchronous conversion. This conversion is not critical for start-of-conversion
positioning.
The user must select the channel to be converted through the software and then request the conversion
through the GPADC_SW_SELECT register. An GPADC_EOC_SW interrupt is generated when the
conversion result is ready, and the result is stored in the GPADC_SW_CONV0_LSB and
GPADC_SW_CONV0_MSB registers.
CAUTION
A defect in the digital controller of TPS65917-Q1 device may cause an
unreliable result from the first asynchronous conversion request after the device
exit from a warm reset. Texas Instruments recommends that user rely on
subsequent requests to obtain accurate result from the asynchronous
conversion after a device warm reset.
For detailed information regarding this issue, see Guide to Using the GPADC in
TPS65903x and TPS6591x Devices SLIA087.
5.8.2 Periodic Conversion (AUTO)
The user can enable periodic conversions to compare one or two channels with a predefined threshold
level. One or two channels can be selected by programming the GPADC_AUTO_SELECT register. The
thresholds and polarity of the conversion can be programmable through the
GPADC_THRES_CONV0_LSB, GPADC_THRES_CONV0_MSB, GPADC_THRES_CONV1_LSB, and
GPADC_THRES_CONV1_MSB registers. In addition, software must select the conversion interval with
the GPADC_AUTO_CTRL register and enable the periodic conversion with the AUTO_CONV0_EN and
AUTO_CONV1_EN bits.
The GPADC does not need to be enabled separately. The control logic enables and disables the GPADC
automatically to save power. The latest conversion result is always stored in the
GPADC_AUTO_CONV0_LSB,
GPADC_AUTO_CONV0_MSB,
GPADC_AUTO_CONV1_LSB,
and
GPADC_AUTO_CONV1_MSB registers. All selected channels are queued and converted from channel 0
to 7. The first (lower) converted channel result is placed in the GPADC_AUTO_CONV0 register and the
second result is placed in the GPADC_AUTO_CONV1 register. Therefore, it is recommended to place the
lower channel for conversion in the AUTO_CONV0_SEL bit field of the GPADC_AUTO_SELECT register,
and the higher channel for conversion in the AUTO_CONV1_SEL bit field.
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If the conversion result triggers the threshold level, an INT interrupt is generated and the conversion result
is stored. If the interrupt is not cleared or the results are not read before another auto-conversion is
complete, then the registers store only the latest results, discarding the previous ones. The auto-
conversion is never stopped by an uncleared interrupt or unread registers.
Programming the triggering of the threshold level can also generate shutdown. This programming is
available independently for the CONV0 and CONV1 channels and is enabled by setting the SHUTDOWN
bits in the GPADC_AUTO_CTRL register. During sleep and off modes, only channels 0 to 4 can be
converted. For channels 5 and 6, conversion is possible in sleep state if the thermal sensor is not
disabled.
5.8.3 Calibration
The GPADC channels are calibrated in the production line using a 2-point calibration method. The
channels are measured with two known values (X1 and X2) and the difference (D1 and D2) to the ideal
values (Y1 and Y2) are stored in the OTP memory. 图 5-16 shows the principle of the calibration.
Measured
code
Calibration points
Measured points
Y2
D2 = Y2 œ X2
Ideal
curve
Measured
curve
Y1
D1 = Y1 œ X1
Offset
Ideal
code
X1
X2
图 5-16. ADC Calibration Scheme
Some of the GPADC channels can use the same calibration data. Use 公式 4 and 公式 5 to calculate the
corrected result.
D2 -D1
(
)
k = 1+
X2 - X1
Gain:
(4)
(5)
b = D1- k -1 ì X1
Offset:
If the measured code is a, the corrected code a' is calculated using 公式 6.
a - b
(
)
a' =
k
(6)
表 5-10 lists the parameters, X1 and X2, and the register for D1 and D2 required in the calculation for all
the channels.
表 5-10. GPADC Calibration Parameters
CHANNEL
X1
X2
D1
D2
COMMENTS
0, 1
2064 (0.63 V)
3112 (0.95 V)
GPADC_TRIM1
GPADC_TRIM2
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表 5-10. GPADC Calibration Parameters (continued)
CHANNEL
X1
X2
D1
D2
COMMENTS
When
3
2064 (2.52 V)
3112 (3.8 V)
GPADC_TRIM3
GPADC_TRIM4
HIGH_VCC_SENSE = 0
When
3
2064 (2.52 V)
3112 (3.8 V)
GPADC_TRIM5
GPADC_TRIM6
HIGH_VCC_SENSE = 1
5.9 General-Purpose I/Os (GPIO Pins)
The TPS65917-Q1 device integrates seven configurable general-purpose I/Os that are multiplexed with
alternative features as listed in 表 5-11
表 5-11. General Purpose I/Os Multiplexed Functions
PIN
PRIMARY FUNCTION
SECONDARY FUNCTION
Input: PWRDOWN (Power down signal)
GPIO_0
General-purpose I/O Port 0
Input: ENABLE2 (Peripheral power request input 2)
Output: REGEN1 (External regulator enable output 4)
Input: RESET_IN (Reset input)
GPIO_1
GPIO_2
GPIO_3
General-purpose I/O Port 1
General-purpose I/O Port 2
General-purpose I/O Port 3
Input: NRESWARM (Warm reset input)
Input: VBUS_SENSE (VBUS input)
Input: ENABLE1 (Peripheral power request input 1)
Input/Output: I2C2_SDA_SDO (DVS control I2C serial bidirectional data) or SPI
output data signal
Input: ENABLE2 (Peripheral power request input 2)
Output: REGEN1 (External regulator enable output 1)
Input: SYNCDCDC (SMPS clock synchronization input)
Output: REGEN2 (External regulator enable output 2)
Input/Output: I2C2_SCL_SCE (DVS control I2C serial clock) or SPI chip-select signal
Input: POWERHOLD (Power hold input)
GPIO_4
GPIO_5
General-purpose I/O Port 4
General-purpose I/O Port 5
Output: REGEN3 (External regulator enable output 3)
Input: NSLEEP (Sleep mode request signal)
GPIO_6
General-purpose I/O Port 6
Output: POWERGOOD (Indicator signal for valid regulator output voltages)
Output: REGEN3 (External regulator enable output 3)
For GPIOs characteristics, refer to:
•
•
•
Pin description,
Electrical characteristics, Section 4.14 and Section 4.15
Pullup and pulldown characteristics, Section 4.16
Each GPIO event can generate an interrupt on a rising edge, falling edge, or both; each line is individually
maskable (as described in 节 5.11). A GPIO-interrupt applies only when the primary function (general-
purpose I/O) has been selected.
All GPIOs can be used as wake-up events.
注
GPIO_2 and GPIO_4 are in the VIO domain (only the I/O supply is required to be available)
and therefore these GPIOs cannot be used as ON requests from the OFF mode.
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The REGEN1 output is muxed in GPIO_0 and GPIO_3, the REGEN2 output is muxed in GPIO_4, and the
REGEN3 output is muxed in GPIO_5 and GPIO_6. When the GPO_0, GPIO_3, GPIO_4, GPIO_5, and
GPIO_6 pins are configured as REGEN1, REGEN2, or REGEN3, these pins can be programmed as part
of the power-up sequence to enable external devices such as external SMPSs. The REGEN1 and
REGEN3 signals are at the VRTC voltage level and the REGEN2 signal is at the VIO voltage level.
The PRIMARY_SECONDARY_PAD1 and PRIMARY_SECONDARY_PAD2 registers control selection
between primary and secondary functions.
When configured as primary functions, all GPIOs are controlled through the following set of registers:
•
•
•
•
•
•
•
•
GPIO_DAT_DIR: Configures individually each GPIO direction (read and write)
GPIO_DATA_IN: Data line-in when configured as an input (read only)
GPIO_DATA_OUT: Data line-out when configured as an output (read and write)
GPIO_DEBOUNCE_EN: Enables individually each GPIO debouncing (read and write)
GPIO_CTRL: Global GPIO control to enable and disable all GPIOs (read and write)
GPIO_CLEAR_DATA_OUT: Clears individually each GPIO data out (write only)
GPIO_SET_DATA_OUT: Sets individually each GPIO data out (write only)
PU_PD_GPIO_CTRL1, PU_PD_GPIO_CTRL2: Configures each line pullup and pulldown (read and
write)
•
OD_OUTPUT_GPIO_CTRL: Enables individual output open drain (read and write)
When configured as secondary functions, none of the GPIO control registers (see 表 5-11) affect GPIO
lines. The line configurations (pullup, pulldown, or open drain) for secondary functions are held in a
separate register set as well as specific function settings.
5.10 Thermal Monitoring
The TPS65917-Q1 device includes several thermal monitoring functions for internal thermal protection of
the PMIC.
The TPS65917-Q1 device integrates two thermal detection modules to monitor the temperature of the die.
These modules are placed on opposite sides of the device and close to the LDO and SMPS modules. An
over-temperature condition at either module first generates a warning to the system and then, if the
temperature continues to rise, a switch-off of the PMIC device can occur before damage to the die.
Two thermal protection levels are available. One of these protections is a hot-die (HD) function which
sends an interrupt to software. Software is expected to close any noncritical running tasks to reduce
power. The second protection is a thermal shutdown (TS) function which immediately begins device
switch-off.
By default, thermal protection is always enabled except in the BACKUP or OFF state. Disabling thermal
protection in sleep state is possible for minimum power consumption.
To use thermal monitoring in the system do the following:
•
Set the value for the hot-die temperature threshold with the
OSC_THERM_CTRL.THERM_HD_SEL[1:0] bits.
•
Disable thermal shutdown in sleep state by setting the THERM_OFF_IN_SLEEP bit to 1 in the
OSC_THERM_CTRL register.
During operation, if the die temperature increases beyond HD_THR_SEL, an interrupt (INT1.HOTDIE) is
sent to the host processor. Immediate action to reduce the PMIC power dissipation by shutting down
some functions must occur.
If the die temperature of the PMIC device rises further (above 148°C), an immediate shutdown occurs.
Indication of a thermal shutdown event indication is written to the status register,
INT1_STATUS_HOTDIE. The system cannot restart until the temperature falls below the HD_THR_SEL
threshold.
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5.10.1 Hot-Die Function (HD)
The HD detector monitors the temperature of the die and provides a warning to the host processor
through the interrupt system when the temperature reaches a critical value. The threshold value must be
set to less than the thermal shutdown threshold. Hysteresis is added to the HD detection to avoid
generating multiple interrupts.
The integrated HD function provides the host PM software with an early warning overtemperature
condition. This monitoring system is connected to the interrupt controller (INTC) and can send an interrupt
when the temperature is higher than the programmed threshold. The TPS65917-Q1 device allows the
programming of four junction-temperature thresholds to increase the flexibility of the system: in nominal
conditions, the threshold triggering of the interrupt can be set from 117°C to 130°C. The HD hysteresis is
10°C in typical conditions.
When the power-management software triggers an interrupt, immediate action must be taken to reduce
the amount of power drawn from the PMIC device (for example, noncritical applications must be closed).
5.10.2 Thermal Shutdown
The thermal shutdown detector monitors the temperature on the die. If the junction reaches a temperature
at which damage can occur, a switch-off transition is initiated and a thermal shutdown event is written into
a status register.
The system cannot restart until the die temperature falls below the HD threshold.
5.11 Interrupts
表 5-12 lists the TPS65917-Q1 interrupts.
These interrupts are split into four register groups (INT1, INT2, INT3, and INT4) and each group has three
associated control registers which are defined as follows:
INTx_STATUS Reflects which interrupt source has triggered an interrupt event
INTx_MASK Used to mask any source of interrupt, to avoid generating an interrupt on a specified source
INTx_LINE_STATE Reflects the real-time state of each line associated to each source of interrupt
The INT4 register group has two additional registers, INT4_EDGE_DETECT1 and
INT4_EDGE_DETECT2, to independently configure rising and falling edge detection (respectively).
All interrupts are logically combined on a single output line, INT (default is active low). The INT line is used
as an external interrupt line to warn the host processor of any interrupt event that has occurred within the
device. The host processor must read the interrupt status registers (INTx_STATUS) through the control
interface (I2C) to identify the interrupt source. Any interrupt source can be masked by programming the
corresponding mask register, INTx_MASK. When an interrupt is masked, the associated event-detection
mechanism is disabled. Therefore the corresponding STATUS bit is not updated and the INT line is not
triggered if the masked event occurs. If an event occurs while the corresponding interrupt is masked, that
event is not recorded. If an interrupt is masked after it has been triggered (the event has occurred and has
not been cleared), the STATUS bit would reflect the event until the bit is cleared. While the event is
masked, the STATUS bit will not be over-written when a new event occurs.
Because some interrupts are sources of ON requests (see 表 5-12), source masking can mask a specific
device switch-on event. Because an active interrupt line, INT, is treated as an ON request, any interrupt
that is not masked must be cleared to allow the execution of a sleep sequence of the device, when
requested.
The polarity of the INT line and clearing method of interrupts can be configured using the INT_CTRL
register.
An INT line can be triggered in either SLEEP or ACTIVE state, depending on the setting of the
OSC_THERM_CTRL.INT_MASK_IN_SLEEP bit.
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When a new interrupt occurs while the INT line is still active (not all interrupts are cleared), then the
following occurs:
•
If the new interrupt source is the same as the one that has already triggered the INT line, the interrupt
can be discarded or stored as a pending interrupt depending on the setting of the
INT_CTRL.INT_PENDING bit.
–
When the INT_CTRL.INT_PENDING bit is active, then any new interrupt event occurring on the
same source (while the INT line is still active) is stored as a pending interrupt. Because only one
level of pending interrupts can be stored for a given source, when more than two events occur on
the same source, only the last event is stored. While an interrupt is pending, two accesses are
required (either read or write) to clear the STATUS bit: one access for the actual interrupt and the
other for the pending interrupt. Two consecutive read-write (R/W) operations to the same register
clear only one interrupt. Another register must be accessed between the two R/W clear operations.
For example of a clear-on-read operation, when the INT signal is active, read all four
INTx_STATUS registers in sequence to collect the status of all potential interrupt sources. The read
access clears the full register for the active or actual interrupt. If the INT line is still active, repeat
the read sequence to check and clear pending interrupts.
–
When the INT_CTRL.INT_PENDING bit is inactive (default), then any new interrupt event occurring
on the same source (while the INT line is still active) is discarded. Two consecutive R/W operations
to the same register only clear one interrupt. Another register must be accessed between the two
R/W-to-clear operations.
•
If the new interrupt source is different from the one that already triggered the INT line, then the
interrupt is stored immediately in the corresponding STATUS bit.
To clear the interrupt line, all status registers must be cleared. The clearing of all status registers occurs
by using a clear-on-read or a clear-on-write method. The clearing method is selectable though the
INT_CTRL.INT_CLEAR bit. When this bit is set, the clearing method applies to all bits for all interrupts.
The two different clear operations are defined as follows:
Clear-on-read Read operation on a single status register clears all bits for only this specific register (8
bits). Therefore, a read operation of all the four status registers is required to clear all the
interrupts requests. When the four read operations are complete, if the INT line is still active
then another interrupt event has occurred during the read process. Therefore, the read
sequence must be repeated.
Clear-on-write This method is bit-based; setting a specific bit to 1 clears only the written bit. Therefore,
to clear a complete status register, write 0xFF. Writing 0xFF to all four status registers is
required to clear all the interrupt requests. When the four write operations are complete, if
the INT line is still active then another interrupt event has occurred during the write process.
Therefore the write sequence must be repeated.
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表 5-12. Interrupt Sources
INTERRUPT
ASSOCIATED EVENT
EDGES DETECTION
ON REQUEST
REG. GROUP REG. BIT
DESCRIPTION
System voltage monitoring interrupt
Triggered when the system voltage crosses the configured threshold in the VSYS_MON register.
VSYS_MON
HOTDIE
Internal event
Rising and falling
Never
Never
6
Hot-die temperature interrupt
The embedded thermal monitoring module has detected a die temperature above the hot-die detection
threshold. An interrupt is generated in ACTIVE and SLEEP states, not in OFF state.
Internal event
Rising and Falling
5
Power-down interrupt
Triggered when event is detected on the PWRDOWN pin.
PWRDOWN
PWRDOWN (pin)
PWRON (pin)
Rising and falling
Falling
Never
Never
INT1
4
2
Power-on long key-press interrupt
Triggered when PWRON is low during more than the long-press delay, LONG_PRESS_KEY.LPK_TIME.
LONG_PRESS_KEY
Power-on interrupt
Always (INT mask, don't
care)
PWRON
SHORT
FSD
PWRON (pin)
Internal event
Internal event
Falling
Rising
Rising
1
6
5
Triggered when the PWRON button is pressed (low) while the device is on. An interrupt is generated in ACTIVE
and SLEEP states, not in OFF state.
Short interrupt
Yes (if INT not masked)
Yes (if INT not masked)
Triggered when at least one of the power resources (SMPS or LDO) outputs is shorted.
First supply detection interrupt
Triggered when a first supply detection is detected. This functions is selected by
PMU_SECONDARY_INT.FSD_MASK.
INT2
RESET_IN interrupt
Triggered when event is detected on the RESET_IN pin.
RESET_IN
WDT
RESET_IN (pin)
Internal event
Internal event
VBUS (pin)
Rising
Rising
Never
Never
4
2
1
7
2
Watchdog time-out interrupt
Triggered when watchdog time-out expires.
OTP bit error detection interrupt
Triggered when an OTP bit error is detected.
OTP_ERROR
VBUS
Rising
Never
VBUS wake-up comparator interrupt
Active in OFF state. Triggered when VBUS present.
Rising and falling
N/A
Yes (if INT not masked)
Yes (if INT not masked)
GPADC software end-of-conversion interrupt
Triggered when the conversion result is available.
GPADC_EOC_SW
Internal event
GPADC automatic periodic conversion 1
INT3
GPADC_AUTO_1
GPADC_AUTO_0
Internal event
Internal event
N/A
N/A
Yes (if INT not masked)
Yes (if INT not masked)
1
0
Triggered when the result of a conversion is either above or below (depending on configuration) reference
threshold GPADC_AUTO_CONV1_LSB and GPADC_AUTO_CONV1_MSB.
GPADC automatic periodic conversion 0
Triggered when the result of a conversion is either above or below (depending on configuration) reference
threshold GPADC_AUTO_CONV0_LSB and GPADC_AUTO_CONV0_MSB.
GPIO_6
GPIO_5
GPIO_4
GPIO_3
GPIO_2
GPIO_1
GPIO_0
GPIO_6 (pin)
GPIO_5 (pin)
GPIO_4 (pin)
GPIO_3 (pin)
GPIO_2 (pin)
GPIO_1 (pin)
GPIO_0 (pin)
Rising, falling, or both Yes (if INT not masked)
Rising, falling, or both Yes (if INT not masked)
Rising, falling, or both Yes (if INT not masked)
Rising, falling, or both Yes (if INT not masked)
Rising, falling, or both Yes (if INT not masked)
Rising, falling, or both Yes (if INT not masked)
Rising, falling, or both Yes (if INT not masked)
6
5
4
3
2
1
0
GPIO_6 rising-edge detection interrupt, falling-edge detection interrupt, or detection interrupt for both edges
GPIO_5 rising-edge detection interrupt, falling-edge detection interrupt, or detection interrupt for both edges
GPIO_4 rising-edge detection interrupt, falling-edge detection interrupt, or detection interrupt for both edges
GPIO_3 rising-edge detection interrupt, falling-edge detection interrupt, or detection interrupt for both edges
GPIO_2 rising-edge detection interrupt, falling-edge detection interrupt, or detection interrupt for both edges
GPIO_1 rising-edge detection interrupt, falling-edge detection interrupt, or detection interrupt for both edges
GPIO_0 rising-edge detection interrupt, falling-edge detection interrupt, or detection interrupt for both edges
INT4
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5.12 Control Interfaces
The TPS65917-Q1 device has two, exclusive selectable (from factory settings) interfaces; 2 high-speed
I2C interfaces (I2C1_SCL_SCK or I2C1_SDA_SDI and I2C2_SCL_SCE or I2C2_SDA_SDO) or 1 SPI
(I2C1_SCL_SCK, I2C1_SDA_SDI, I2C2_SDA_SDO, or I2C2_SCL_SCE). Both are used to fully control
and configure the device and have access to all the registers. When the I2C configuration is selected
(either I2C1_SCL_SCK or I2C1_SDA_SDI) a general purpose control (GPC) interface is dedicated to
configure the device and the I2C2_SCL_SCE or I2C2_SDA_SDO interface, dynamic voltage scaling
(DVS) is dedicated to dynamically change the output voltage of the SMPS converters. The DVS I2C
interface has access only to the voltage scaling registers of the SMPS converters (R/W mode).
5.12.1 I2C Interfaces
The GPC I2C interface (I2C1_SCL_SCK and I2C1_SDA_SDI) is dedicated to access the configuration
registers of all the resources of the system.
The DVS I2C interface (I2C2_SCL_SCE and I2C_SDA_SDO) is dedicated to access the DVS registers
independently from the GPC I2C.
The control interfaces comply with the HS-I2C specification and support the following features:
•
•
Mode: Slave only (receiver and transmitter)
Speed:
–
–
–
Standard mode (100 kbps)
Fast mode (400 kbps)
High-speed mode (3.4 Mbps)
•
Addressing: 7-bit mode addressing device
The following features are not supported:
•
•
•
10-bit addressing
General call
Master mode (bus arbitration and clock generation)
I2C is a 2-wire serial interface developed by NXP (formerly Philips Semiconductor) (see I2C-Bus
Specification and user manual, Rev 03, June 2007). The bus consists of a data line (SDA) and a clock line
(SCL) with pullup structures. When the bus is idle, the SDA and SCL lines are pulled high. All the I2C-
compatible devices connect to the I2C bus through open-drain I/O pins, SDA and SCL. A master device,
usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for
generating the SCL signal and device addresses. The master also generates specific conditions that
indicate the start and stop of data transfers. A slave device receives data, transmits data, or both on the
bus under control of the master device. The data transfer protocol for standard and fast modes is exactly
the same. In this data sheet, these modes are referred to as F/S mode. The protocol for high-speed (HS)
mode is different from F/S mode.
5.12.1.1 I2C Implementation
The TPS65917-Q1 standard I2C 7-bit slave device address is set to 010010xx (binary) where the two
least-significant bits are used for page selection.
The device is organized in five internal pages of 256 bytes (registers) as follows:
•
•
•
•
•
Slave device address 0x48: Power registers
Slave device address 0x49: Interfaces and auxiliaries
Slave device address 0x4A: Trimming and test
Slave device address 0x4B: OTP
Slave device address 0x12: DVS
The device address for the DVS I2C interface is set to 0x12.
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If one of the addresses conflicts with another device I2C address, remapping each address to a fixed
alternative address is possible as listed in 表 5-13. The I2C for DVS is fixed because it is a dedicated
interface.
表 5-13. I2C Address Configuration
REGISTER
BIT
PAGE
ADDRESSES
ID_I2C1[0] = 0: 0x48
ID_I2C1[0] = 1: 0x58
ID_I2C1[1] = 0: 0x49
ID_I2C1[1] = 1: 0x59
ID_I2C1[2] = 0: 0x4A
ID_I2C1[2] = 1: 0x5A
ID_I2C1[3] = 0: 0x4B
ID_I2C1[3] = 1: 0x5B
ID_I2C2 = 0: 0x12
ID_I2C1[0]
Power registers
ID_I2C1[1]
ID_I2C1[2]
Interfaces and auxiliaries
Trimming and test
I2C_SPI
ID_I2C1[3]
ID_IDC2
OTP
DVS
5.12.1.2 F/S Mode Protocol
The master initiates a data transfer by generating a START condition. The START condition is when a
high-to-low transition occurs on the SDA line while SCL is high (see 图 5-17). All I2C-compatible devices
should recognize a START condition.
The master then generates SCL pulses and transmits the 7-bit address and the read or write direction bit
(R/W) on the SDA line. During all transmissions, the master ensures that data is valid. A valid data
condition requires the SDA line to be stable during the entire high period of the clock pulse (see 图 5-18).
All devices recognize the address sent by the master and compare it to the internal fixed addresses of the
respective device. Only the slave device with a matching address generates an acknowledge signal (see
图 5-19) by pulling the SDA line low during the entire high period of the ninth SCL cycle. When this
acknowledge signal is detected, the communication link between the master and the slave device has
been established.
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data
from the slave (R/W bit 0). In either case, the receiver must acknowledge the data sent by the transmitter.
An acknowledge signal can be generated by the master or the slave, depending on which device is the
receiver. Nine-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue for as
long as required.
To signal the end of the data transfer, the master generates a STOP condition by pulling the SDA line
from low to high while the SCL line is high (see 图 5-17). Pulling the line from low to high while SCL is
high releases the bus and stops the communication link with the addressed slave. All I2C-compatible
devices must recognize the STOP condition. Upon the receipt of a STOP condition, the slave device must
wait for a START condition followed by a matching address.
Attempting to read data from the register addresses not listed in this section results in a read out of 0xFF.
5.12.1.3 HS Mode Protocol
When the bus is idle, the SDA and SCL lines are pulled high by the pullup devices.
The master generates a START condition followed by a valid serial byte containing the HS master code,
00001XXX. This transmission is made in F/S mode at no more than 400 kbps. No device is allowed to
acknowledge the HS master code, but all devices must recognize it and switch the internal setting to
support 3.4-Mbps operation.
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The master then generates a REPEATED START condition (a REPEATED START condition has the
same timing as the START condition). After the REPEATED START condition, the protocol is the same as
F/S mode, except that transmission speeds up to 3.4 Mbps are allowed. A STOP condition ends the HS
mode and switches all the internal settings of the slave devices to support F/S mode. Instead of using a
STOP condition, REPEATED START conditions are used to secure the bus in HS mode.
Attempting to read data from register addresses not listed in this section results in a read out of 0xFF.
DATA
CLK
S
P
START
STOP
condition
condition
图 5-17. START and STOP Conditions
DATA
CLK
Data line stable;
Change of data allowed
data valid
图 5-18. Bit Transfer on the Serial Interface
Data output
by transmitter
Not Acknowledge
Data output
by receiver
Acknowledge
SCL from
master
1
2
8
9
S
Clock pulse for
acknowledgement
START
condition
图 5-19. Acknowledge on the I2C Bus
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Recognize START or
REPEATED START
condition
Recognize SOP or
REPEATED START
condition
Generate
ACKNOWLEDGE signal
P
SDA
MSB
Acknowledgement
signal from slave
Sr
Address
R/W
1
2
7
8
9
1
2
3 to 8
9
SCL
ACK
S or
Sr
ACK
Sr or
P
Clock line held low while
interrupts are serviced
START or REPEATED
START condition
STOP or REPEATED
START condition
图 5-20. Bus Protocol
5.12.2 Serial Peripheral Interface (SPI)
The SPI is a 4-wire slave interface used to access and configure the device. The SPI allows read-and-
write access to the configuration registers of all resources of the system.
The SPI uses the following signals:
•
•
•
•
SCE (I2C2_SCL_SCE): Chip enable which is the input driven by host master. This signal is used to
initiate and terminate a transaction
SCK (I2C1_SCL_SCK): Clock which is the input driven by host master. This signal is as master clock
for data transaction
SDI (I2C1_SDA_SDI): Data input which is the input driven by host master. This signal is as data line
from master to slave
SDO (I2C2_SDA_SDO): Data output which is the output driven by TPS65917-Q1. This signal is as
data line from slave to master and defaults to high impedance
5.12.2.1 SPI Modes
This SPI supports two access modes which are single access and burst access. All shifts occur with the
most significant bit (MSB) first (data, address, page). These two access modes have the following
features:
•
Single access (read or write)
–
–
–
This mode consists of fetching and storing one single data location. The protocol is shown in 图 5-
21.
The R/W bit is always provided first, followed by page address and register address fields. When
the R/W bit = 0, a read access is performed. When the R/W bit = 1, a write access is performed.
One burst bit indicates if the following transfer is a single access (BURST = 0) or a burst access
(BURST = 1).
–
–
–
Four unused bits follow the burst bit and the 8-bit data is finally either shifted in (write) or out (read).
For a write access, the data output line SDO is invalid (useless) during the whole transaction.
For a read access, the data output line SDO is invalid during the unused bits (time slot used for
data fetch) and then becomes active or valid after the unused bits.
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•
Burst access (read or write)
–
–
–
–
This mode consists of fetching and storing several data at contiguous locations. The protocol is
shown in 图 5-22.
The R/W bit is always provided first, followed by page address and register address fields. When
the R/W bit 0, a read access is performed. When the R/W bit 1, a write access is performed.
One burst bit indicates if the following transfer is a single access (BURST = 0) or a burst access
(BURST = 1).
Four unused bits follow the burst bit and packets of 8-bit data are finally either shifted in (write) or
out (read).
–
–
–
The transaction remains active as long as the SCE signal is maintained high by the host.
The address is automatically incremented internally for each new 8-bit packet received.
The host must pull the SCE signal low after a complete 8-bit data is transferred, otherwise the last
transaction is discarded.
–
–
For a write access, the data output line SDO is invalid (useless) during the whole transaction.
For a read access, the data output line SDO is invalid during the unused bits (time slot used for
data fetch) and then becomes active or valid after the unused bits.
5.12.2.2 SPI Protocol
图 5-21 shows the SPI protocol for a single read and write access. 图 5-22 shows the SPI protocol for a
burst read and write access.
SPI write
SCE
SCK
SDI
RW Page
Burst
Register address (8)
Unused bits (5)
Data (8)
(SDI)
Palmas samples SDI on SCK rising edge
: Master to assert data on falling edge
SPI read
SCE
SCK
SDI
RW Page
Burst
Register address (8)
Unused bits (5)
Don‘t Care
(SDI)
SDO
Data (8)
(SDO)
Palmas samples SDI on SCK rising edge
PMIC asserts SDO so that it is available on SCK rising edge
: Master to assert data on falling edge
: Master must sample data on rising edge
图 5-21. SPI Single Read and Write Access
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SPI write
SCE
SCK
SDI
Data (8)
Data (8)
RW Page
Burst
Data (8)
Register address (8)
Unused bits (5)
(SDI)
Palmas samples SDI on SCK rising edge
: Master to assert data on falling edge
SPI read
SCE
SCK
SDI
Data (8)
Data (8)
Data (8)
Data (8)
RW Page
Burst
Data (8)
Data (8)
Register address (8)
Unused bits (5)
(SDI)
SDO
(SDO)
Palmas samples SDI on SCK rising edge
PMIC asserts SDO so that it is available on SCK rising edge
: Master to assert data on falling edge
: Master must sample data on rising edge
图 5-22. SPI Burst Read and Write Access
5.13 OTP Configuration Memory
The register mapping for the device describes the OTP configuration bits. These bits are highlighted as
the value X during reset in the register mapping (the value of the bit is the copy of the OTP configuration
memory).
5.14 Watchdog Timer (WDT)
The watchdog timer has two modes of operation: periodic mode and interrupt mode.
In periodic mode, an interrupt is generated with a regular period N, defined by the setting of
WATCHDOG.TIMER. This interrupt is generated at the beginning of the period (when the watchdog
internal counter equals 1). The IC initiates a shutdown at the end of the period (when the internal counter
reaches N) only if the interrupt is not cleared within the defined time frame (0 to N). In this mode, when the
interrupt is cleared, the internal counter is not reset. The counter continues counting until it reaches the
maximum value (defined by the TIMER setting) and automatically rolls over to 0 to start a new counting
period. Regardless of when the interrupt is cleared within a given period (N), the next interrupt is
generated only when the ongoing period completes (reaches N). The internal watchdog counter is
initialized and kept at 0 as long as the RESET_OUT pin is low. The watchdog counter begins counting
when the RESET_OUT pin is released.
In interrupt mode, any interrupt source resets the watchdog counter and starts the counting. If the sources
of the interrupts are not cleared (meaning the INT line is released) before the end of the predefined
period, N (set by WATCHDOG.TIMER setting), then the device initiates a shutdown. If the sources of the
interrupts are cleared within the predefined period, then the watchdog counter is discarded (dc) and no
shutdown sequence is initiated.
By default, the watchdog is disabled. The watchdog can be enabled by setting the ENABLE bit of the
WATCHDOG register to 1, and this selection is write protected by setting the LOCK bit to 1. Reset of the
device returns these bits to default values.
图 5-23 and 图 5-24 show the watchdog timings.
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Watchdog internal
0
1
...
i
...
N
0
1
...
...
N
0
counter
IT not cleared
in allowed
timeframe
New
watchdog IT
Watchdog IT
cleared
New
watchdog IT
INT pin (active high)
Device Switch off
RESET_OUT pin
图 5-23. Watchdog Timings—Periodic Mode
Watchdog internal
counter
X
0
1
...
i
dc
dc
0
1
...
N
0
IT not cleared
in allowed
timeframe
New IT (reset
WDT counter)
New IT (reset
WDT counter)
INT pin (active high)
RESET_OUT pin
IT
cleared
Device switch off
图 5-24. Watchdog Timings—Interrupt Mode
5.15 System Voltage Monitoring
Comparators that monitor the voltage on the VCC_SENSE, and VCCA pins control the power state
machine of the TPS65917-Q1 device. For electrical parameters, see Section 4.12.
POR
When the supply at the VCCA pin is below the POR threshold, the TPS65917-Q1 device is
in the NO SUPPLY state. All functionality is off. The device moves from the NO SUPPLY
state to the BACKUP state when the voltage in VCCA rises above the POR threshold.
VSYS_LO When the voltage on the VCCA pin rises above VSYS_LO, the device enters from the
BACKUP state to the OFF state. When the device is in an ACTIVE, SLEEP, or OFF state
and the voltage on VCCA decreases below the VSYS_LO level, the device enters backup
mode. When the device transitions from the ACTIVE state to the BACKUP state, all active
SMPS and LDO regulators, except LDOVRTC, are disabled simultaneously. There is a 180-
µs deglitch time after VCCA becomes less than VSYS_LO and before the regulators are
disabled. The level of VSYS_LO is OTP programmable.
VSYS_MON During power up, the value of VSYS_HI OTP is used as a threshold for the VSYS_MON
comparator which is gating PMIC start-up (that is, as a threshold for transition from the OFF
state to the ACTIVE state). The VSYS_MON comparator monitors the VCC_SENSE pin.
After power up, software can configure the comparator threshold in the VSYS_MON register.
VBUS_DET The VBUS_DET comparator is monitoring the VBUS_SENSE (secondary function of GPIO1)
pin. This comparator is active when VCCA is greater than the POR threshold. Triggering the
threshold level generates an interrupt. It can wake up the device from the SLEEP state, but
can also switch on the device from the OFF state.
图 5-25 shows a block diagram of the system comparators and 图 5-26 shows the state transitions.
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OTP bits
Register bits
VCCA
POR
Power-On Reset Threshold
VCCA
VSYS_LO
VSYS_LO
VCC_SENSE
VSYS_MON
VSYS_MON
Default VSYS_HI
VBUS_SENSE
VBUS_DET
VBUS_WKUP_UP
图 5-25. System Comparators
VSYS_HI
VSYS_MON
VSYS_LO
Start-Up Event
POR
INT
STATE
NO SUPPLY
BACKUP
OFF
ACTIVE / SLEEP
BACKUP
NO SUPPLY
图 5-26. State Transitions
注
To generate a POR from a falling VCC, VCC is sampled every 1 ms and compared to the POR
threshold. In case VCC is discharged and resupplied quickly, a POR may not be reliably
generated if VCC crosses the POR threshold between samples. Another way to generate
POR is to discharge the LDOVRTC regulator to 0 V after VCC is removed. With no external
load, this could take seconds for the LDOVRTC output to discharge to 0 V. The PMIC should
not be restarted after VCC is removed but before LDOVRTC is discharged to 0 V. If
necessary, TI recommends adding a pulldown resistor from the LDOVRTC output to GND
with a minimum of 3.9 kΩ to speed up the LDOVRTC discharge time.
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The value of the pulldown resistor should be chosen based on the desired discharge time and acceptable
current draw in the OFF state, but no greater than 0.5 mA. Use 公式 7 to calculate the pulldown resistor
based on the desired discharge time.
tdischarge (ms)
RPD (kW) =
CO (mF) ì 3
where
•
•
•
tdischarge = discharge time of the VRTC output
RPD = pulldown resistance from the VRTC output to GND
CO = output capacitance on the VRTC line (typically 2.2 µF)
(7)
Because LDOVRTC is always on when VCC is supplied, additional current is drawn through the pulldown
resistor. The output current of LDOVRTC while the PMIC is in OFF state should not exceed 0.5 mA. Use
公式 8 to calculate the pulldown current.
1.8 V
IPD
=
RPD
where
•
•
IPD = current through the pulldown resistor
RPD = pulldown resistance from the VRTC regulator
(8)
To use comparators in the system:
•
•
The VSYS_HI and VSYS_LO thresholds are defined in the OTP. Software cannot change these levels.
After startup, the VSYS_MON comparator is automatically disabled. Software can select new threshold
levels using the VSYS_MON register and then enable the comparators.
•
To have the same coding for rising and falling edge, the VSYS_MON comparator does not include
hysteresis and thus can generate multiple interrupts when the voltage level is at threshold level. New
interrupt generation has a 125-µs debounce time. This time lets software mask the interrupt and
update the threshold level or disable the comparator before receiving a new interrupt.
图 5-27 shows more details on VSYS_MON comparator. When the VSYS_MON comparator is enabled,
and the internal buffer is bypassed, the input impedance at VCC_SENSE pin is 500 kΩ (typical). When the
comparator is disabled, the VCC_SENSE pin is in the high-impedance state. If GPADC is enabled to
measure channel 2 or channel 3, 40 kΩ is added in parallel to the corresponding comparator. See 表 5-9
for GPADC input range.
To enable system voltage sensing above 5.25 V, an external resistive divider can be used. Internal buffers
can be enabled by setting the OTP bit HIGH_VCC_SENSE to 1 to provide high impedance for the external
resistive dividers. The maximum input level for the internal buffer is VCCA – 1 V.
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VCCA
VCC_SENSE
1
0
VSYS_MON
VSYS_MON
HIGH_VCC_SENSE(1)
Default VSYS_HI
500 kꢀ
30 kꢀ
10 kꢀ
Scale down,
divide by 4
GPADC_IN3
GPADC
(1) HIGH_VCC_SENSE = 0: buffer bypassed (not enabled). HIGH_VCC_SENSE = 1: buffer enabled, bypass disabled (Hi-Z at SENSE
input)
图 5-27. VSYS_MON Comparator Details
5.16 Register Map
5.16.1 Functional Register Mapping
For the register descriptions, refer to the TPS65917-Q1 Register Map.
5.17 Device Identification
The following registers can differentiate the TPS65917-Q1 device being used.
表 5-14. TPS65917-Q1 Device ID
REGISTER NAME
REGISTER DESCRIPTION
VALUE
For all TPS65917-Q1 devices, this register will have the
same value.
PRODUCT_ID_MSB
0x09
For all TPS65917-Q1 devices, this register will have the
same value.
PRODUCT_ID_LSB
DESIGNREV
0x17
Revision 1.0
Revision 1.1
0x0
0x1
This register distinguishes which silicon
version is used.
This register will be representative of the OTP version
programmed on the device.
SW_REVISION
OTP dependent - See User's Guide
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6 Applications, Implementation, and Layout
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1 Application Information
The TPS65917-Q1 device is an integrated power management integrated circuits (PMIC), available in a
48-pin, 0.5-mm pitch, 7-mm × 7-mm QFN package. It is designed specifically for automotive applications.
It has five configurable step-down converter rails, with two of these SMPSs capable of combining power
rails and supply up to 7 A of output current in multi-phase mode. These step-down converters can be
synchronized to an external clock between 1.7 MHz to 2.7 MHz, or an internal fallback clock at 2.2 MHz.
The TPS65917-Q1 device also has five external LDOs which can be supplied from the system supply or a
pre-regulated supply. Two of these LDOs can be configured in bypass mode. One of the five LDOs also
provides low noise output.
The TPS65917-Q1 device also come with a 12-bit GPADC with two external channels, seven configurable
GPIOs, two I2C interface channels or one SPI interface channel, a PLL for external clock sync and phase
delay capability, and a programmable power sequencer and control for supporting different processors
and applications.
As TPS65917-Q1 device is a highly integrated PMIC device, it is very important that customers should
take necessary actions to ensure the PMIC is operating under the recommended operating conditions to
ensure desired performance from the device. Additional cooling strategies may be necessary to maintain
the junction temperature below maximum limit allowed for the device. To minimize the interferences when
turning on a power rail while the device is in operation, optimal PCB layout and grounding strategy are
essential and are recommended in 节 6.3. In addition, customer may take steps such as turning on
additional rails only when the systems is operating in light load condition.
Details on how to use this device as a power management device for a application processor are
described throughout this device specification. The following sections provides the typical application use
case with the recommended external components and layout guidelines. A design checklist for the
TPS65917-Q1 device is also available on which provides application design guidance and cross checks.
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6.2 Typical Application
Typical Application
Processor
TPS65917-Q1
12-V Power
Source
SMPS1
DVS/AVS 3.5 A
CPU and Vision Processor
GPADC
Voltage Monitor
Voltage Monitor
Voltage Monitor
ADCIN2
ADCIN1
SMPS2
DVS/AVS 3.5 A
Core
GPADC
Preregulator
3.3 V
SMPS3
DVS/AVS 3 A
GPU and SRAM
I2C2 and DVS
Dedicated DVFS
Interface Controller
and Registers
I2C2 Data
I2C2 CLK
GPIO2
GPIO4
Dedicated DVFS
Interface
SMPS4
1.5 A
1.8-V IO
SMPS5
2 A
DDR & DDR Interface
LDO1, Bypass mode, 300 mA
LDO2, Bypass mode, 300 mA
LDO3, 200 mA
Peripheral Supplies
(SD card, camera,
radar, and others)
3.3-V IO
LDO4, 200 mA
LDO5, Low Noise 100 mA
PLL, Oscillator, DAC, ADC
SYNCCLKOUT
OSC + PLL CLKSYS
Interrupt Handler
INT
GPADC
External
Power
Supply
œ
Voltage Monitor
VBG
PWRDOWN,
POWERHOLD,
RESET_IN,
ENABLE1&2,
NSLEEP,
BBS and Bandgap REFSYS
+
I2C2 and
SPI
Interface
Controller
NRESWARM
I2C CLK
I2C Data
POWERGOOD
Power Switch
Safety MCU
Optional
Clock
Monitor
EN
Optional
External
Regulator
External Peripherals
CLK_SYNC_IN
Copyright © 2017, Texas Instruments Incorporated
图 6-1. Application Diagram in a Typical ADAS System
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6.2.1 Design Requirements
For a typical ADAS application shown in 图 6-1, 表 6-1 lists the key design parameters of the power
resources.
表 6-1. Design Parameters
DESIGN PARAMETER
Supply voltage
Switching frequency
SMPS1 voltage
SMPS1 current
SMPS2 voltage
SMPS2 current
SMPS3 voltage
SMPS3 current
SMPS4 voltage
SMPS4 current
SMPS5 voltage
SMPS5 current
LDO1 voltage
VALUE
3.3 V to 5 V
2.2 MHz
1.15 V
Up to 3.5 A
1.15 V
Up to 3.5 A
1.06 V
Up to 3 A
1.8 V
Up to 1.5 A
1.35 V or 1.5 V
Up to 2 A
1.8 V or 3.3 V
Up to 300 mA
1.8 V
LDO1 current
LDO2 voltage
LDO2 current
Up to 300 mA
1.8 V
LDO3 voltage
LDO3 current
Up to 200 mA
3.3 V
LDO4 voltage
LDO4 current
Up to 200 mA
1.8 V
LDO5 voltage
LDO5 current
Up to 100 mA
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6.2.2 Detailed Design Procedure
表 6-2 lists the recommended external components.
表 6-2. Recommended External Components
REFERENCE
COMPONENTS
EIA size
code(2)
MASS
COMPONENT(1)
MANUFACTURER
PART NUMBER
VALUE
SIZE (mm)
PRODUCTION(3)
INPUT POWER SUPPLIES EXTERNAL COMPONENTS
C1, C2
C3
VSYS and VCCA tank capacitor(4)
Murata
Murata
GCM21BR70J106KE22
GCM155R71C104KA55
10 µF, 6V3
0805
2 × 1.25 × 1.25
1 × 0.5 × 0.5
Available(5)
Available(5)
Decoupling capacitor
100 nF, 16 V
0402
BANDGAP EXTERNAL COMPONENTS
C7 Capacitor
SMPS EXTERNAL COMPONENTS
(5)
Murata
GCM155R71C104KA55
100 nF, 16 V
0402
1 × 0.5 × 0.5
Available
(5)
C8, C9, C10, C11, C12
C13, C14, C15, C16, C17
L1, L2, L3, L4, L5
Input capacitor
Murata
Murata
VISHAY
GCM21BC71A475MA735 4.7 µF 10 V
0805
1210
2 × 1.25 × 1.25
3.2 × 2.5 × 2.5
4.45 × 4.1 × 1.2
Available
Output capacitor
Inductor
GCM32ER70J476KE19
IHLP1616ABER1R0M11
47 uF 10 V
1 µH
Available(5)
Available(5)
LDO EXTERNAL COMPONENTS
C18, C19
Input capacitor
Output capacitor
Murata
Murata
GCM188R70J225KE22
GCM188R70J225KE22
2.2 µF 6V3
2.2 µF 6V3
0603
0603
1.6 × 0.8 × 0.8
1.6 × 0.8 × 0.8
Available(5)
Available(5)
C4, C5, C20, C21, C22,
C23, C24
(1) Component minimum and maximum tolerance values are specified in the electrical parameters section of each IP.
(2) The PACK column describes the external component package type.
(3) This column refers to the criteria.
(4) The tank capacitors filter the VSYS and VCCA input voltage of the LDO and SMPS core architectures.
(5) Component used on the validation boards.
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6.2.2.1 SMPS Input Capacitors
All SMPS inputs require an input decoupling capacitor to minimize input ripple voltage. Using a 10-V, 4.7-
µF capacitor for each SMPS is recommended. Depending on the input voltage of the SMPS, a 6.3-V or
10-V capacitor can be used. See 表 6-2 for the specific part number of the recommended input capacitor.
For optimal performance, the input capacitors should be placed as close to the SMPS input pins as
possible. See the 节 6.3.1 section for more information about component placement.
6.2.2.2 SMPS Output Capacitors
All SMPS outputs require an output capacitor to hold up the output voltage during a load step or changes
to the input voltage. To ensure stability across the entire switching frequency range, the TPS65917-Q1
device requires an output capacitance value between 33 µF and 57 µF. To meet this requirement across
temperature and DC bias voltage, using a 47-µF capacitor for each SMPS is recommended. Remember
that each SMPS requires an output capacitor, not just each output rail. For example, SMPS12 is a dual-
phase regulator and an output capacitor is required for the SMPS1 output and the SMPS2 output. Note,
this requirement excludes any capacitance seen at the load and only refers to the capacitance seen close
to the device. Additional capacitance placed near the load can be supported, but the end application or
system should be evaluated for stability. See 表 6-2 for the specific part number of the recommended
output capacitor.
6.2.2.3 SMPS Inductors
Again, to ensure stability across the entire switching frequency range, using a 1-µH inductor on each
SMPS is recommended. Remember that each SMPS requires an inductor, not just each output rail. For
example, SMPS12 is a dual-phase regulator and an inductor is required for the SMPS1_SW pins and the
SMPS2_SW pins. See 表 6-2 for the specific part number of the recommended inductor.
6.2.2.4 LDO Input Capacitors
All LDO inputs require an input decoupling capacitor to minimize input ripple voltage. Using a 2.2-µF
capacitor for each LDO is recommended. Depending on the input voltage of the LDO, a 6.3-V or 10-V
capacitor can be used. See 表 6-2 for the specific part number of the recommended input capacitors.
For optimal performance, the input capacitors should be placed as close to the LDO input pins as
possible. See the 节 6.3.1 section for more information about component placement.
6.2.2.5 LDO Output Capacitors
All LDO outputs require an output capacitor to hold up the output voltage during a load step or changes to
the input voltage. Using a 2.2-µF capacitor for each LDO output is recommended. Note, this requirement
excludes any capacitance seen at the load and only refers to the capacitance seen close to the device.
Additional capacitance placed near the load can be supported, but the end application or system should
be evaluated for stability. See 表 6-2 for the specific part number of the recommended output capacitors.
6.2.2.6 VCCA
VCCA is the supply for the analog input voltage of the device. This pin requires a 10-µF decoupling
capacitor.
Texas Instruments recommends to always power down the TPS65917-Q1 before removing power from
VCCA. If the input voltage to the device is removed while the device is ACTIVE, the device will shut off
when VCCA reaches the VSYS_LO threshold. As mentioned in the 节 5.15 section, once VCCA reaches
VSYS_LO, there is about 180 us delay before all the output rails are disabled simultaneously.
There are two scenarios to consider in the system-level design in the event of unexpected loss of power.
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6.2.2.6.1 Meeting the Power-Down Sequence
To prevent a sequencing violation, it is important to block reverse current and implement a disable signal
to the PMIC. A Schottky diode can block reverse current when the input is removed. Additionally,
capacitors can help maintain the input voltage level while the power-down sequence occurs. Depending
on the system design, there are a couple ways to implement a disable signal.
For a system where the TPS65917-Q1 is powered by the system input voltage, a supervisor can be used
to create a logic signal, indicating if the power is at a good level. An example of this solution is shown in
图 6-2.
VIN
(5 V)
VCC
PMIC
GND
Supervisor
ENABLE
图 6-2. Supporting Uncontrolled Power Down When the PMIC is Supplied by the System Input Voltage
An alternative solution is possible when a pre-regulator is present. In the case of the pre-regulator, the
pre-regulator output capacitance can also act as the energy storage to maintain VCCA for the necessary
time. The total supply capacitance should be calculated to support the worst-case leakage current during
power down so that the voltage is maintained until the power-down sequence completes. 图 6-3 shows an
example of this configuration.
VIN
(12 V)
5 V
Buck
VCC
PGOOD
PMIC
GND
ENABLE
图 6-3. Supporting Uncontrolled Power Down when the PMIC is Supplied by a Preregulator
To determine the capacitance needed at the output of the pre-regulator, use 公式 9. This equation is used
to ensure that the power down sequence is complete before the device is disabled.
C = I × ΔT / (VCCA – VSYS_LO)
where
•
•
•
•
•
C is total capacitance on VCCA, including preregulator output capacitance and PMIC input capacitance
I is the total current on the PMIC input supply
ΔT is the time it takes the power-down sequence to complete
VCCA is the voltage at the VCCA pin
VSYS_LO is the threshold where the device is disabled
(9)
6.2.2.6.2 Maintaining Sufficient Input Voltage
In the event of high loading during loss of input voltage, there is a risk to go below the voltage level
necessary for the internal logic of the device to work properly before the device is disabled. This means
that when the VCCA voltage supply level becomes lower than the VSYS_LO threshold, the input voltage
may continue dropping to very low voltages during the 180 us ±10% delay before the device is disabled.
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If a large input voltage drop occurs before the device is disabled, the internal logic can no longer properly
drive the FETs of the SMPS, and it is possible that the high-side FET and low-side FET of the SMPS are
on at the same time. In the event that the high-side and low-side FETs for an SMPS are on at the same
time, there is a direct path from SMPSx_IN to GND, allowing cross-conduction and possible damage of
the device.
In order to prevent damage or irregular switching behavior, it is important that the voltage at the
SMPSx_IN pin stays above 1.8 V, including negative transients, before the device is disabled. The
minimum voltage seen at the SMPSx_IN pin is dependent on VCCA and the PCB inductance between the
SMPSx_IN pin and the input capacitor. Use 公式 10 to determine the minimum capacitance needed on
VCCA to ensure that the device continues switching properly before it is disabled.
C = I × ΔT / (VSYS_LO – VCCAMIN
)
where
•
•
•
•
•
C is total capacitance on VCCA, including preregulator output capacitance and PMIC input capacitance
I is the total current on the PMIC input supply
ΔT is the maximum debounce time after VCCA = VSYS_LO before the device switches off (198us)
VSYS_LO is the threshold where the device is disabled
VCCAMIN is the minimum VCCA voltage to keep the SMPSx_IN transients above 1.8 V
(10)
When measuring the SMPSx_IN and VCCA during power down, use active differential probes and a high
resolution oscilloscope (4GS/sec or more). VCCA can be measured over the 10uF input capacitor.
However, SMPSx_IN must be measured at the pin in order to measure the transients on this rail
accurately. To measure SMPSx_IN, place the negative lead of the differential probe at a nearby GND,
such as the GND of the SMPSx_IN input capacitor. Place the positive lead of the differential probe directly
on the exposed metal of the SMPSx_IN pin. With this set up, verify that SMPSx_IN, including the ripple on
this signal, does not drop below 1.8V before the SMPS stops switching. See 图 6-4 for an example of how
to take this measurement. For ways to decrease the amplitude of the transient spikes, see 表 6-3 for
recommended parasitic inductance requirements.
SMPSx_IN
VCCA
1.8 V minimum
SMPSx_SW
图 6-4. Waveform of SMPSx_IN Transients
6.2.2.7 VIO_IN
VIO_IN is the supply for the interface IO circuits inside the device. This pin requires a 0.1-µF decoupling
capacitor.
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6.2.2.8 GPADC
To perform a software conversion with the GPADC, use the following steps:
1. Enable software conversion mode – GPADC_SW_SELECT.SW_CONV_EN
2. Select the channel to convert – GPADC_SW_SELECT.SW_CONV0_SEL
–
For channel 0, set up the current source in the GPADC_CTRL1 register if needed.
3. For minimum latency, the GPADC can be set to always on (instead of default enabled from conversion
request) by GPADC_CTRL1.GPADC_FORCE.
4. Unmask software conversion interrupt – INT3_MASK.GPADC_EOC_SW
5. Start conversion – GPADC_SW_SELECT.SW_START_CONV0.
6. An interrupt is generated at the end of the conversion INT3_STATUS.GPADC_EOC_SW.
7. Read conversion result – GPADC_SW_CONV0_MSB and GPADC_SW_CONV0_LSB
8. Expected result = dec(GPADC_SW_CONV0_MSB[3:0].GPADC_SW_CONV0_LSB[7:0])/ 4096 × 1.25
× scaler
To perform an auto conversion with the GPADC, use the following steps:
1. Select the channel to convert – GPADC_AUTO_SELECT.AUTO_CONV0_SEL
2. Configure auto conversion frequency – GPADC_AUTO_CTRL.COUNTER_CONV
3. Set the threshold level for comparison – GPADC_THRESH_CONV0_MSB.THRESH_CONV0_MSB,
GPADC_THRESH_CONV0_LSB.THRESH_CONV0_LSB
–
Level = expected voltage threshold / (1.25 × scaler) × 4096 (in hexadecimal)
4. Set if the interrupt is triggered when conversion is above or below threshold –
GPADC_THRESH_CONV0_MSB.THRESH_CONV0_POL
5. Triggering the threshold level can also be programmed to generate shutdown –
GPADC_AUTO_CTRL.SHUTDOWN_CONV0
6. Unmask AUTO_CONV_0 interrupt – INT3_MASK.GPADC_AUTO_0
7. Enable AUTO CONV0 – GPADC_AUTO_CTRL.AUTO_CONV0_EN
8. When selected channel crosses programmed threshold, interrupt is generated –
INT3_STATUS.GPADC_AUTO_0
9. Conversion results are available – GPADC_AUTO_CONV0_MSB, GPADC_AUTO_CONV0_LSB
10. If shutdown was enabled, chip switches off after SWOFF_DLY, unless interrupt is cleared
Both examples above are for CONV0; a similar procedure applies to CONV1.
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6.2.3 Application Curves
V
(20 mV/div)
O
V
O
(20 mV/div)
0.8-mA to 2-A load step,
t = t = 400 ns
0.5-mA to 500- mA load step,
t = t = 100 ns
I
(2 A/div)
O
r
f
I
O
(2 A/div)
r
f
VI = 3.15 V
ƒS = 2.2 MHz
VO = 1.05 V
VI = 3.15 V
ƒS = 2.2 MHz
VO = 1.05 V
图 6-6. Typical SMPS Load Transient Response for SMPS12
图 6-5. Typical SMPS Load Transient Response for SMPS12
in Dual Phase Mode
in Dual Phase Mode
V
(20 mV/div)
V
(20 mV/div)
O
O
0.5-mA to 500-mA load step,
I
(500 mA/div)
I
(500 mA/div)
O
O
t = t = 100 ns
r
f
0.5-mA to 500-mA load step,
t = t = 1 µs
r
f
VI = 5.25 V
ƒS = 2.2 MHz
VO = 0.7 V
VI = 3.15 V
ƒS = 2.2 MHz
VO = 0.7 V
图 6-8. Typical SMPS Load Transient Response for SMPS4
图 6-7. Typical SMPS Load Transient Response for
SMPS1, SMPS2, SMPS3, and SMPS5
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6.3 Layout
6.3.1 Layout Guidelines
As in every switch-mode-supply design, general layout rules apply:
•
•
•
Use a solid ground-plane for the power ground (PGND)
Connect those grounds at a star-point that is located ideally underneath the device.
Place input capacitors as close as possible to the input pins of the device. This placement is
paramount and more important than the output-loop.
•
•
•
Place the inductor and output capacitor as close as possible to the phase node (or switch-node) of the
device.
Keep the loop-area formed by the phase-node, inductor, output-capacitor, and PGND as small as
possible.
For traces and vias on power-lines, keep inductance and resistance as small as possible by using wide
traces. Avoid switching layers but, if needed, use plenty of vias.
The goal of these guidelines is a layout that minimizes emissions, maximizes EMI immunity, and
maintains a safe operating area (SOA) for the device.
To minimize the spiking at the phase-node for both the high-side (VIN to SWx) and low-side (SWx to
PGND), the decoupling of VIN is the most important guideline. Appropriate decoupling and thorough
layout should ensure that the spikes never exceed 7V across the high-side and low-side FETs.
图 6-9 shows a set of guidelines regarding parasitic inductance and resistance that are recommended.
Parasitic Inductance: < 0.5 nH
Parasitic resistance: < 2 mΩ
Parasitic resistance:
As small as possible for
the best efficiency
SMPSx_SW
SMPSx_IN
SMPSx_SW
SMPSx_GND
Connection to power plane
Parasitic resistance:
As small as possible for the
best efficiency
For multiple 22-µF
capacitors, keep the
parasitic resistance
< 1 mꢀ among
Parasitic inductance: < 0.1 nH
Parasitic resistance: < 1 mΩ
capacitors
图 6-9. Parasitic Inductance and Resistance
表 6-3 lists the maximum allowable parasitic (inductance measured at 100 MHz) and the achievable
values in an optimized layout.
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表 6-3. Maximum Allowable Parasitic
MAXIMUM ALLOWABLE
MAXIMUM ALLOWABLE
RESISTANCE
OPTIMIZED LAYOUT
(EVM) INDUCTANCE
OPTIMIZED LAYOUT (EVM)
RESISTANCE
CONNECTION
INDUCTANCE
N/A for SOA
N/A for SOA
PowerPlane to CIN
N/A
Maintain a low resistance value for N/A
efficiency
Maintain a low resistance
value for efficiency
SMPS1
0.2 nH
0.2 nH
0.2 nH
0.2 nH
0.2 nH
0.3 nH
0.3 nH
0.4 nH
0.3 nH
0.4 nH
SMPS1
SMPS2
SMPS3
SMPS4
SMPS5
SMPS1
SMPS2
SMPS3
SMPS4
SMPS5
SMPS1
SMPS2
SMPS3
SMPS4
SMPS5
N/A for SOA
1.1 mΩ
1.6 mΩ
1.5 mΩ
1.8 mΩ
1.5 mΩ
0.4 mΩ
0.4 mΩ
0.5 mΩ
0.6 mΩ
0.5 mΩ
1 mΩ
SMPS2
SMPS3
SMPS4
SMPS5
SMPS1
SMPS2
SMPS3
SMPS4
SMPS5
CIN to SMPSx_IN
0.5 nH
2 mΩ
CIN to PGND
0.5 nH
2 mΩ
0.7 mΩ
1 mΩ
N/A for SOA
SMPSx_SW to inductor
Inductor to COUT
N/A
N/A
Maintain a low resistance value for N/A
efficiency
0.7 mΩ
1.4 mΩ
N/A for SOA
Maintain a low resistance value for N/A
efficiency
Maintain a low resistance
value for efficiency
SMPS1
0.8 nH
0.6 nH
0.5 nH
0.4 nH
0.5 nH
SMPS1
SMPS2
SMPS3
SMPS4
SMPS5
0.7 mΩ
0.8 mΩ
0.6 mΩ
0.6 mΩ
0.5 mΩ
SMPS2
SMPS3
SMPS4
SMPS5
Use dedicated GND plane to
keep inductance low
COUT to GND
1 mΩ
GND (CIN) to GND
Use dedicated GND plane to
keep inductance low
Use dedicated GND plane to
keep inductance low
1 mΩ
mΩ
(COUT
)
Texas Instruments recommends measuring the voltages across the high-side FET (voltage at SMPSx_IN
versus SMPSx_SW) and the low-side FET (SMPSx_SW versus PGND) with a high bandwidth, high
sampling-rate scope with a low-capacitance probe (ideally a differential probe). Measure the voltages as
close as possible to the device pins and verify the amplitude of the spikes. A small-loop ground connection
to PGND is essential.
When measuring the voltage difference between the SMPSx_IN and SMPSx_SW pins, there should be a
maximum of 7 V when measuring at the pins. Similarly, when measuring the voltage difference between
the SMPSx_SW and PGND pins, there should be a maximum of 7 V when measuring at the pins.
For more information on cursor-positioning, see 图 6-10 and 图 6-11.
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7 V maximum
SMPSx_IN - SMPSx_SW
Measure across the high-side FET (SMPSx_IN – SMPSx_SW) as close to the IC as possible. The preferred
measurement is with a differential probe. The negative side of the probe should be at SMPSx_SW and the positive
side of the probe should measure SMPSx_IN. As shown in this image, the voltage across the high-side FET should
not exceed 7 V. Repeat the measurement for all SMPSs in use.
图 6-10. Measuring the High-Side FET (Differentially)
7 V maximum
SMPSx_SW - SMPSx_GND
Measure across the low-side FET (SMPSx_SW – GND) as close to the IC as possible. The preferred measurement is
with a differential probe. The negative side of the probe should be at GND and the positive side of the probe should
measure SMPSx_SW. As shown in this image, the voltage across the low-side FET should not exceed 7 V.Repeat
the measurement for all SMPSs in use.
图 6-11. Measuring the Low-Side FET (Differentially)
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6.3.2 Layout Example
See 图 6-12 and 图 6-13 for the actual placement and routing on the EVM.
Input
Capacitors
Output
Capacitors
Inductors
图 6-12. Top Layer Overview of Inductor and Capacitor Placement and Routing of SMPSs
图 6-13. Bottom Layer Overview of Capacitor Placement and Routing of LDOs
6.4 Power Supply Coupling and Bulk Capacitors
The TPS65917-Q1 device is designed to work with an analog supply-voltage range of 3.135 V to 5.25 V.
The input supply should be well regulated and connected to the VCCA pin, as well as SMPS and LDO
input pins with appropriate bypass capacitors as recommended in 表 6-2. If the input supply is located
more than a few inches from the TPS65917-Q1 device, additional capacitance may be required in addition
to the recommended input capacitors at the VCCA pin and the SMPS and LDO input pins.
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产品主页链接: TPS65917-Q1
TPS65917-Q1
www.ti.com.cn
ZHCSGJ3D –JULY 2015–REVISED FEBRUARY 2019
7 器件和文档支持
7.1 器件支持
7.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构
成此类产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
7.1.2 器件命名规则
本数据表使用下列缩略词和术语。有关术语、缩写和定义的详细列表,请参阅《TI 术语表》。
ADC
APE
DVS
GPIO
LDO
PM
模数转换器
应用处理器引擎
数字电压调节
通用输入/输出
低压降线性稳压器
电源管理
PMIC
PSRR
RTC
SMPS
NA
电源管理集成电路
电源抑制比
实时时钟
开关模式电源
不适用
OTP
ESR
PMU
PFM
PWM
SPI
一次性可编程
等效串联电阻
电源管理单元
脉频调制
脉宽调制
串行外设接口
嵌入式电源控制器
首次电源检测
EPC
FSD
7.2 文档支持
7.2.1 相关文档
请参阅如下相关文档:
•
•
•
•
•
•
•
德州仪器 (TI),《电池供电的汽车类 ADAS 和信息娱乐系统处理器电源参考设计》
德州仪器 (TI),《TPS65903x 和 TPS6591x 器件中的 GPADC 使用指南》
德州仪器 (TI),《适用于处理器的 TPS65917-Q1 电源管理单元 (PMU) 安全手册》
德州仪器 (TI),《TPS65917-Q1 EVM 用户指南》
德州仪器 (TI),《TPS65917-Q1 寄存器映射》
德州仪器 (TI),《为 DRA7xx 和 TDA2x/TDA2Ex 供电的 TPS65917-Q1 用户指南》
德州仪器 (TI),《为 DRA71x、DRA79x 和 TDA2E-17 供电的 TPS65919-Q1 和 TPS65917-Q1 用户指
南》
•
德州仪器 (TI),《为 TDA3x 供电的 TPS65919-Q1 和 TPS65917-Q1 用户指南》
7.3 接收文档更新通知
版权 © 2015–2019, Texas Instruments Incorporated
器件和文档支持
83
提交文档反馈意见
产品主页链接: TPS65917-Q1
TPS65917-Q1
ZHCSGJ3D –JULY 2015–REVISED FEBRUARY 2019
www.ti.com.cn
要接收文档更新通知,请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册,即可每周
接收产品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
7.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信
息。
7.5 商标
Eco-mode, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
7.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
7.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
8 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通
知,且不会对此文档进行修订。如欲获取此数据表的浏览器版本,请参阅左侧的导航。
84
机械、封装和可订购信息
版权 © 2015–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: TPS65917-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Feb-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
Qty
(1)
(2)
(3)
(4/5)
(6)
O917A130TRGZRQ1
O917A130TRGZTQ1
O917A131TRGZRQ1
O917A131TRGZTQ1
O917A132TRGZRQ1
O917A132TRGZTQ1
O917A133TRGZRQ1
O917A133TRGZTQ1
O917A14DTRGZRQ1
O917A14DTRGZTQ1
O917A14FTRGZRQ1
O917A14FTRGZTQ1
O917A151TRGZRQ1
O917A152TRGZRQ1
O917A152TRGZTQ1
O917A154TRGZRQ1
O917A154TRGZTQ1
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
TPS65917
OTP 30 1.1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
TPS65917
OTP 30 1.1
TPS65917
OTP 31 1.1
TPS65917
OTP 31 1.1
TPS65917
OTP 32 1.1
TPS65917
OTP 32 1.1
TPS65917
OTP 33 1.1
TPS65917
OTP 33 1.1
TPS65917
OTP 4D 1.1
TPS65917
OTP 4D 1.1
TPS65917
OTP 4F 1.1
TPS65917
OTP 4F 1.1
2500 RoHS & Green
2500 RoHS & Green
TPS65917
OTP 51 1.1
TPS65917
OTP 52 1.1
250
RoHS & Green
TPS65917
OTP 52 1.1
2500 RoHS & Green
TPS65917
OTP 54 1.1
250
RoHS & Green
TPS65917
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Feb-2022
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OTP 54 1.1
O917A186TRGZRQ1
ACTIVE
VQFN
RGZ
48
2500 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
TPS65917
OTP 86 1.1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
O917A130TRGZRQ1
O917A130TRGZTQ1
O917A131TRGZRQ1
O917A131TRGZTQ1
O917A132TRGZRQ1
O917A132TRGZTQ1
O917A133TRGZRQ1
O917A133TRGZTQ1
O917A14DTRGZRQ1
O917A14DTRGZTQ1
O917A14FTRGZRQ1
O917A14FTRGZTQ1
O917A151TRGZRQ1
O917A152TRGZRQ1
O917A152TRGZTQ1
O917A154TRGZRQ1
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
2500
250
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
330.0
180.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
2500
250
2500
250
2500
250
2500
250
2500
250
2500
2500
250
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
O917A154TRGZTQ1
O917A186TRGZRQ1
VQFN
VQFN
RGZ
RGZ
48
48
250
180.0
330.0
16.4
16.4
7.3
7.3
7.3
7.3
1.1
1.1
12.0
12.0
16.0
16.0
Q2
Q2
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
O917A130TRGZRQ1
O917A130TRGZTQ1
O917A131TRGZRQ1
O917A131TRGZTQ1
O917A132TRGZRQ1
O917A132TRGZTQ1
O917A133TRGZRQ1
O917A133TRGZTQ1
O917A14DTRGZRQ1
O917A14DTRGZTQ1
O917A14FTRGZRQ1
O917A14FTRGZTQ1
O917A151TRGZRQ1
O917A152TRGZRQ1
O917A152TRGZTQ1
O917A154TRGZRQ1
O917A154TRGZTQ1
O917A186TRGZRQ1
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
2500
250
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
367.0
210.0
367.0
210.0
367.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
367.0
185.0
367.0
185.0
367.0
38.0
35.0
38.0
35.0
38.0
35.0
38.0
35.0
38.0
35.0
38.0
35.0
38.0
38.0
35.0
38.0
35.0
35.0
2500
250
2500
250
2500
250
2500
250
2500
250
2500
2500
250
2500
250
2500
Pack Materials-Page 3
GENERIC PACKAGE VIEW
RGZ 48
7 x 7, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
RGZ0048D
VQFN - 1 mm max height
S
C
A
L
E
1
.
9
0
0
PLASTIC QUAD FLATPACK - NO LEAD
7.1
6.9
A
B
0.5
0.3
PIN 1 INDEX AREA
7.1
6.9
0.30
0.18
DETAIL
OPTIONAL TERMINAL
TYPICAL
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
5.6 0.1
2X 5.5
(0.2) TYP
13
24
44X 0.5
12
25
EXPOSED
THERMAL PAD
2X
49
SYMM
5.5
SEE TERMINAL
DETAIL
1
36
0.30
48X
0.18
37
48
PIN 1 ID
(OPTIONAL)
SYMM
0.1
C A B
0.5
0.3
48X
0.05
4219046/B 11/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGZ0048D
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
5.6)
SYMM
48
37
48X (0.6)
1
36
48X (0.24)
6X
(1.22)
44X (0.5)
SYMM
10X
(1.33)
49
(6.8)
(R0.05)
TYP
(
0.2) TYP
VIA
25
12
13
24
10X (1.33)
6X (1.22)
(6.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219046/B 11/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGZ0048D
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.665 TYP)
(1.33) TYP
16X ( 1.13)
37
48
48X (0.6)
49
36
1
48X (0.24)
44X (0.5)
(1.33)
TYP
(0.665)
TYP
SYMM
(6.8)
(R0.05) TYP
25
12
METAL
TYP
13
24
SYMM
(6.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 49
66% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:15X
4219046/B 11/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,
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