OMAP3530ECBB_技术文档

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

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SPRS599–JUNE 2009

1 OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

1.1 Features

–

Additional C64x+™ Enhancements

•

OMAP3525 and OMAP3530 Applications

Processors:

•

Protected Mode Operation

Exceptions Support for Error Detection

and Program Redirection

–

OMAP™ 3 Architecture

MPU Subsystem

•

Hardware Support for Modulo Loop

Operation

•

600-MHz ARM Cortex™-A8 Core

NEON™ SIMD Coprocessor

•

C64x+ L1/L2 Memory Architecture

–

High Performance Image, Video, Audio

(IVA2.2™) Accelerator Subsystem

–

32K-Byte L1P Program RAM/Cache (Direct

Mapped)

80K-Byte L1D Data RAM/Cache (2-Way

Set-Associative)

64K-Byte L2 Unified Mapped RAM/Cache

(4-Way Set-Associative)

32K-Byte L2 Shared SRAM and 16K-Byte L2

ROM

•

430-MHz TMS320C64x+™ DSP Core

Enhanced Direct Memory Access

(EDMA) Controller (128 Independent

Channels)

•

Video Hardware Accelerators

POWERVR SGX™ 2D/3D Graphics

Accelerator (OMAP3530 Device Only)

•

C64x+ Instruction Set Features

•

Tile Based Architecture Delivering up to

10 MPoly/sec

Universal Scalable Shader Engine:

Multi-threaded Engine Incorporating

Pixel and Vertex Shader Functionality

Industry Standard API Support:

OpenGLES 1.1 and 2.0, OpenVG1.0

Fine Grained Task Switching, Load

Balancing, and Power Management

Programmable High Quality Image

Anti-Aliasing

–

Byte-Addressable (8-/16-/32-/64-Bit Data)

8-Bit Overflow Protection

Bit-Field Extract, Set, Clear

Normalization, Saturation. Bit-Counting

Compact 16-Bit Instructions

Additional Instructions to Support Complex

Multiplies

•

ARM Cortex™-A8 Core

–

ARMv7 Architecture

•

Trust Zone®

Thumb®-2

MMU Enhancements

–

Fully Software-Compatible With C64x and

ARM9™

Commercial and Extended Temperature

Grades

–

In-Order, Dual-Issue, Superscalar

Microprocessor Core

•

Advanced Very-Long-Instruction-Word (VLIW)

TMS320C64x+™ DSP Core

–

NEON™ Multimedia Architecture

Over 2x Performance of ARMv6 SIMD

Supports Both Integer and Floating Point

SIMD

–

Eight Highly Independent Functional Units

•

+Six ALUs (32-/40-Bit), Each Supports

Single 32-Bit, Dual 16-Bit, or Quad 8-Bit

Arithmetic per Clock Cycle

Two Multipliers Support Four 16 x 16-Bit

Multiplies (32-Bit Results) per Clock

Cycle or Eight 8 x 8-Bit Multiplies (16-Bit

Results) per Clock Cycle

–

Jazelle® RCT Execution Environment

Architecture

Dynamic Branch Prediction with Branch

Target Address Cache, Global History

Buffer, and 8-Entry Return Stack

•

–

Embedded Trace Macrocell (ETM) Support

for Non-Invasive Debug

–

Load-Store Architecture With Non-Aligned

Support

–

64 32-Bit General-Purpose Registers

Instruction Packing Reduces Code Size

All Instructions Conditional

•

ARM Cortex™-A8 Memory Architecture:

–

16K-Byte Instruction Cache (4-Way

Set-Associative)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this document.

POWERVR SGX is a trademark of Imagination Technologies Ltd.

OMAP is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

PRODUCT PREVIEW information concerns products in the

formative or design phase of development. Characteristic data and

other specifications are design goals. Texas Instruments reserves

the right to change or discontinue these products without notice.

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–

16K-Byte Data Cache (4-Way

Set-Associative)

256K-Byte L2 Cache

•

Up to 24-Bit RGB

HD Maximum Resolution

Supports Up to 2 LCD Panels

Support for Remote Frame Buffer

Interface (RFBI) LCD Panels

•

112K-Byte ROM

64K-Byte Shared SRAM

Endianess:

–

2 10-Bit Digital-to-Analog Converters

(DACs) Supporting:

•

Rotation 90-, 180-, and 270-degrees

Resize Images From 1/4x to 8x

Color Space Converter

ARM Instructions - Little Endian

ARM Data – Configurable

DSP Instruction/Data - Little Endian

Composite NTSC/PAL Video

Luma/Chroma Separate Video (S-Video)

–

•

External Memory Interfaces:

–

SDRAM Controller (SDRC)

•

16, 32-bit Memory Controller With

1G-Byte Total Address Space

Interfaces to Low-Power Double Data

Rate (LPDDR) SDRAM

SDRAM Memory Scheduler (SMS) and

Rotation Engine

8-bit Alpha Blending

•

Serial Communication

–

5 Multichannel Buffered Serial Ports

(McBSPs)

•

512 Byte Transmit/Receive Buffer

(McBSP1/3/4/5)

5K-Byte Transmit/Receive Buffer

(McBSP2)

SIDETONE Core Support (McBSP2 and 3

Only) For Filter, Gain, and Mix

Operations

Direct Interface to I2S and PCM Device

and TDM Buses

–

General Purpose Memory Controller

(GPMC)

•

16-bit Wide Multiplexed Address/Data

Bus

Up to 8 Chip Select Pins With 128M-Byte

Address Space per Chip Select Pin

Glueless Interface to NOR Flash, NAND

Flash (With ECC Hamming Code

•

128 Channel Transmit/Receive Mode

Calculation), SRAM and Pseudo-SRAM

–

Four Master/Slave Multichannel Serial Port

Interface (McSPI) Ports

High-Speed/Full-Speed/Low-Speed USB

OTG Subsystem (12-/8-Pin ULPI Interface)

High-Speed/Full-Speed/Low-Speed

Multiport USB Host Subsystem

•

Flexible Asynchronous Protocol Control

for Interface to Custom Logic (FPGA,

CPLD, ASICs, etc.)

Nonmultiplexed Address/Data Mode

(Limited 2K-Byte Address Space)

•

System Direct Memory Access (sDMA)

Controller (32 Logical Channels With

Configurable Priority)

12-/8-Pin ULPI Interface or 6-/4-/3-Pin

Serial Interface

Supports Transceiverless Link Logic

(TLL)

•

Camera Image Signal Processing (ISP)

–

CCD and CMOS Imager Interface

Memory Data Input

RAW Data Interface

BT.601/BT.656 Digital YCbCr 4:2:2

(8-/16-Bit) Interface

A-Law Compression and Decompression

Preview Engine for Real-Time Image

Processing

Glueless Interface to Common Video

Decoders

Histogram Module/Auto-Exposure,

Auto-White Balance, and Auto-Focus

Engine

–

One HDQ/1-Wire Interface

Three UARTs (One with Infrared Data

Association [IrDA] and Consumer Infrared

[CIR] Modes)

Three Master/Slave High-Speed

Inter-Integrated Circuit (I2C) Controllers

–

•

Removable Media Interfaces:

–

Three Multimedia Card (MMC)/ Secure

Digital (SD) With Secure Data I/O (SDIO)

One Memory Stick Pro Host Controller

Universal Subscriber Identity Module

(USIM)

–

Comprehensive Power, Reset, and Clock

Management

–

Resize Engine

•

Resize Images From 1/4x to 4x

Separate Horizontal/Vertical Control

–

SmartReflex™ Technology

Dynamic Voltage and Frequency Scaling

(DVFS)

•

Display Subsystem

Parallel Digital Output

–

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(Bottom)

•

Test Interfaces

–

IEEE-1149.1 (JTAG) Boundary-Scan

Compatible

Embedded Trace Macro Interface (ETM)

Serial Data Transport Interface (SDTI)

•

1.8-V I/O and 3.0-V (MMC1 only),

0.975-V to 1.35-V Adaptive Processor Core

Voltage,

0.975-V to 1.35-V Adaptive Core Logic Voltage

Note: These are default Operating

Performance Point (OPP) voltages and could

be optimized to lower values using

SmartReflex™ AVS.

–

•

12 32-bit General Purpose Timers

2 32-bit Watchdog Timers

1 32-bit Secure Watchdog Timer

1 32-bit 32-kHz Sync Timer

•

Applications:

Up to 188 General-Purpose I/O (GPIO) Pins

(Multiplexed With Other Device Functions)

–

Portable Navigation Devices

Portable Media Player

Advanced Portable Consumer Electronics

Digital TV

Digital Video Camera

Portable Data Collection

Point-of-Sale Devices

Gaming

•

65-nm CMOS Technology

Package-On-Package (POP) Implementation

for Memory Stacking

•

Discrete Memory Interface (Not Available in

CBC Package)

Packages:

–

Web Tablet

515-pin s-PBGA package (CBB Suffix),

.5mm Ball Pitch (Top), .4mm Ball Pitch

(Bottom)

515-pin s-PBGA package (CBC Suffix),

.65mm Ball Pitch (Top), .5mm Ball Pitch

Smart White Goods

Smart Home Controllers

Ultra Mobile Devices

–

1.2 SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS

•

Controlled Baseline

One Assembly/Test Site

One Fabrication Site

Extended Product Life Cycle

Extended Product-Change Notification

Product Traceability

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1.3 Description

OMAP3530 and OMAP3525 high-performance, applications processors are based on the enhanced

OMAP™ 3 architecture.

The OMAP™ 3 architecture is designed to provide best-in-class video, image, and graphics processing

sufficient to support the following:

•

Streaming video

2D/3D mobile gaming

Video conferencing

High-resolution still image

The device supports high-level operating systems (OSs), such as:

•

Linux

Windows CE

Symbian OS

Palm OS

This OMAP device includes state-of-the-art power-management techniques required for high-performance

mobile products.

The following subsystems are part of the device:

•

Microprocessor unit (MPU) subsystem based on the ARM Cortex™-A8 microprocessor

IVA2.2 subsystem with a C64x+ digital signal processor (DSP) core

POWERVR SGX™ subsystem for 2D and 3D graphics acceleration to support display and gaming

effects (3530only)

•

Camera image signal processor (ISP) that supports multiple formats and interfacing options connected

to a wide variety of image sensors

Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a

programmable interface supporting a wide variety of displays. The display subsystem also supports

NTSC/PAL video out.

•

Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple

initiators to the internal and external memory controllers and to on-chip peripherals

The device also offers:

•

A comprehensive power and clock-management scheme that enables high-performance, low-power

operation, and ultralow-power standby features. The device also supports SmartReflex™ adaptative

voltage control. This power management technique for automatic control of the operating voltage of a

module reduces the active power consumption.

•

Memory stacking feature using the package-on-package (POP) implementation (CBB and CBC

packages only)

OMAP3530 is available in a 515-pin s-PBGA package (CBB suffix) and the OMAP3525 is available in

515-pin s-PBGA (CBC suffix). Table 1-1 lists the differences between the CBB and CBC packages.

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Table 1-1. Differences Between CBB and CBC Packages

FEATURE

CBB PACKAGE

CBC PACKAGE

For CBB package pin assignments

seeTable 2-1, Ball Characteristics (CBB

Pkg.)

For CBC package pin assignments see

Table 2-2, Ball Characteristics (CBC Pkg.)

Pin Assignments

Package-On-Package (POP) Interface

Discrete Memory Interface

POP interface supported

Discrete Memory Interface supported

Eight chip select pins available

Four wait pins available

Discrete Memory Interface not supported

Eight chip select pins available

Four wait pins available

GPMC

The following signals are either available on

two (double muxed) or three pins (triple

muxed): uart1_cts (AE21 / T19 / W2),

uart1_rts (AE22 / R2), uart1_rx (H3 / H25 /

AE4), uart1_tx (L4 / G26)

CTS signal is available on 3 pins (triple

muxed): uart1_cts (AG22 / W8 / T21),

uart1_rts (AH22 / AA9), uart1_tx (F28 / Y8 /

AE7), uart1_rx (E26 / AA8)

UART1

The following signals are available on two

pins (double muxed): uart2_cts (AF6/AB26), pins (double muxed): uart2_cts (Y24/P3),

uart2_rts (AE6/AB25), uart2_tx (AF5/AA25), uart2_rts (AA24/N3), uart2_tx (AD22/U3),

UART2

uart2_rx (AE5/AD25)

uart2_rx (AD21/W3)

The following signals are available on three

The following signals are available on two

pins (triple muxed): mcbsp3_dx (AF6 / AB26 pins (triple muxed): mcbsp3_dx (U17/ Y24/

McBSP3

/ V21), mcbsp3_dr (AE6 / AB25 / U21),

mcbsp3_clkx (AF5 / AA25 / W21), and

mcbsp3_fsx (AE5 / AD25 / K26)

P3), mcbsp3_dr (T20/ AA24 / N3),

mcbsp3_clkx (T17/ AD22 / U3), mcbsp3_fsx

(P20/ AD21 / W3)

The following signals are available on three

pins (triple muxed): gpt8_pwm_evt (N8 /

The following signals are available on three

pins (triple muxed): gpt8_pwm_evt

GP Timer

McBSP4

AD25 / V3), gpt9_pwm_evt (T8 / AB26 / Y2), (C5/AD21/V9), gpt9_pwm_evt (B4/W8/Y24),

gpt10_pwm_evt (R8 / AB25 / Y3), and

gpt11_pwm_evt (P8 / AA25 / Y4)

gpt10_pwm_evt(C4/U8/AA24),

gpt11_pwm_evt(B5/V8/AD22)

The following signals are available on two

pins (double muxed): mcbsp4_clkx (T8/AE1), pins(double muxed): mcbsp4_clkx (B4 / V3),

mcbsp4_dr (R8/AD1), mcbsp4_dx (P8/AD2), mcbsp4_dr (C4 / U4), mcbsp4_dx (B5 / R3),

mcbsp4_fsx (N8/AC1)

mcbsp4_fsx (C5 / T3)

HSUSB3_TLL

MM_FSUSB3

McSPI1

Supported

Four chip select pins are available

The following signals are available on two

pins (double muxed): mmc3_cmd (AC3 /

AE10), and mmc3_clk (AB1 / AF10)

The following signals are available on two

pins (double muxed): mmc3_cmd (R8 / AB3),

mmc3_clk (R9 / AB2)

MMC3

GPIO

DSI

A maximum of 188 GPIO pins are supported. A maximum of 188 GPIO pins are supported.

Supported

SDI

This OMAP3525 and OMAP3530 Applications Processors data manual presents the electrical and

mechanical specifications for the OMAP3525 and OMAP3530 Applications Processors. The information

contained in this data manual applies to both the commercial and extended temperature versions of the

OMAP3525 and OMAP3530 Applications Processors unless otherwise indicated. It consists of the

following sections:

•

A description of the OMAP3525 and OMAP3530 terminals: assignment, electrical characteristics,

multiplexing, and functional description (Section 2)

•

A presentation of the electrical characteristics requirements: power domains, operating conditions,

power consumption, and dc characteristics (Section 3)

•

The clock specifications: input and output clocks, DPLL and DLL (Section 4)

The video DAC specification (Section 5)

The timing requirements and switching characteristics (ac timings) of the interfaces (Section 6)

A description of thermal characteristics, device nomenclature, and mechanical data about the available

packaging (Section 7)

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1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the OMAP3525/30 Applications Processor.

OMAP Applications Processor

CVBS

or

S-Video

Camera

(Parallel)

LCD Panel

Parallel

MPU

Subsystem

IVA 2.2 Subsystem

Amp

TV

TMS320DM64x+ DSP

Imaging Video and

Audio Processor

32K/32K L1$

ARM Cortex-

A8^TMCore

16K/16K L1$

Camera

ISP

Image

Capture

Hardware

Image

Pipeline

and

Preview

HS USB

Host

(with

USB

TTL)

HS

48K L1D RAM

64K L2$

32K L2 RAM

Dual Output 3-Layer

Display Processor

(1xGraphics, 2xVideo)

Temporal Dithering

SDTV → QCIF Support

POWERVR

SGX^TM

Graphics

Accelerator

(3530 only)

32

Channel

System

DMA

16K L2 ROM

Video Hardware

Accelerators

USB

OTG

L2$

256K

64

Async

64

32

64

32

32 32

32

64

32

Async

64

L3 Interconnect Network-Hierarchial, Performance, and Power Driven

32 64 32 32

SMS:

32

L4 Interconnect

64K

On-Chip

RAM

112K

SDRAM

Memory

Scheduler/

Rotation

On-Chip

ROM

80KB

Secure/

32KB

BOOT

GPMC:

General

Purpose

Memory

Controller

NAND/

System

Controls

PRCM

2KB

Peripherals:

3xUART, 3xHigh-Speed I2C,

5xMcBSP

Public/

62KB

Secure

2xSmartReflex^TM

Control

Module

(2x with Sidetone/Audio Buffer)

4xMcSPI, 6xGPIO,

3xHigh-Speed MMC/SDIO,

HDQ/1 Wire,

NOR

Flash,

SRAM

SDRC:

SDRAM

Memory

Controller

2xMailboxes

12xGPTimers, 2xWDT,

32K Sync Timer

External

Peripherals

Interfaces

Emulation

Debug: SDTI, ETM, JTAG,

External and

Stacked Memories

Coresight^TMDAP

Figure 1-1. OMAP3525/30 Functional Block Diagram

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Contents

1

OMAP3525-HiRel and OMAP3530-HiRel

4.2 Output Clock Specifications........................ 113

Applications Processors ............................... 1

4.3 DPLL and DLL Specifications...................... 115

VIDEO DAC SPECIFICATIONS ..................... 122

5.1 Interface Description ............................... 122

1.1 Features .............................................. 1

5

6

1.2

SUPPORTS DEFENSE, AEROSPACE, AND

MEDICAL APPLICATIONS........................... 3

5.2

Electrical Specifications Over Recommended

1.3 Description............................................ 4

1.4 Functional Block Diagram ............................ 6

TERMINAL DESCRIPTION.............................. 8

2.1 Terminal Assignment ................................. 8

2.2 Ball Characteristics.................................. 12

2.3 Multiplexing Characteristics ......................... 50

2.4 Signal Description ................................... 66

ELECTRICAL CHARACTERISTICS.................. 93

3.1 Power Domains ..................................... 93

3.2 Absolute Maximum Ratings ......................... 95

3.3 Recommended Operating Conditions............... 97

3.4 DC Electrical Characteristics........................ 99

3.5 Core Voltage Decoupling .......................... 102

3.6 Power-up and Power-down ........................ 104

CLOCK SPECIFICATIONS........................... 107

4.1 Input Clock Specifications ......................... 108

Operating Conditions .............................. 124

5.3

Analog Supply (vdda_dac) Noise Requirements .. 126

2

3

5.4 External Component Value Choice ................ 127

TIMING REQUIREMENTS AND SWITCHING

CHARACTERISTICS.................................. 128

6.1 Timing Test Conditions ............................ 128

6.2 Interface Clock Specifications ..................... 128

6.3 Timing Parameters................................. 129

6.4 External Memory Interfaces........................ 130

6.5 Video Interfaces.................................... 159

6.6 Serial Communications Interfaces ................. 179

6.7 Removable Media Interfaces ...................... 212

6.8 Test Interfaces ..................................... 227

PACKAGE CHARACTERISTICS.................... 233

7.1 Package Thermal Resistance...................... 233

7.2 Device Support..................................... 233

7

4

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2 TERMINAL DESCRIPTION

2.1 Terminal Assignment

Figure 2-1 through Figure 2-4 show the ball locations for the 515-ball plastic ball grid array (s-PBGA)

packages. Table 2-1 and Table 2-2 indicate the signal names and ball grid numbers for both packages.

AH

AG

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1

3

5

7

9

11

13

17

19

21

23

25

27

15

2

4

6

8

10

12

14

16

18

20

22

24

26

28

030-001

Figure 2-1. OMAP3525/30 Applications Processor CBB s-PBGA-N515 Package (Bottom View)

8

TERMINAL DESCRIPTION

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AC

AB

AA

Y

W

V

U

T

R

P

N

L

J

M

K

H

G

E

C

A

F

D

B

23

19

17

15

13

11

9

7

5

3

1

21

22

20

18

16

14

12

10

8

6

4

2

030-002

Balls A1, A2, A22, A23, AB1, AB2, AB22, AB23, AC1, AC2, AC22, AC23, B1, B2, B22, and B23 are unused.

Figure 2-2. OMAP3525/30 Applications Processor CBB s-PBGA-N515 Package (Top View)

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AF

AE

AD

AC

AB

AA

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1

2 3 4 5 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

6 8

Figure 2-3. OMAP3525/30 Applications Processor CBC s-PBGA-515 Package (Bottom View)

10

TERMINAL DESCRIPTION

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AA

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

Figure 2-4. OMAP3525/30 Applications Processor CBC s-PBGA-515 Package (Top View)

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2.2 Ball Characteristics

Table 2-1 and Table 2-2 describe the terminal characteristics and the signals multiplexed on each pin for

the CBB and CBC packages, respectively. The following list describes the table column headers.

1. BALL BOTTOM: Ball number(s) on the bottom side associated with each signal(s) on the bottom.

2. BALL TOP: Ball number(s) on the top side associated with each signal(s) on the top.

3. PIN NAME: Names of signals multiplexed on each ball (also notice that the name of the pin is the

signal name in mode 0).

Note: Table 2-1 and Table 2-2 do not take into account subsystem pin multiplexing options.

Subsystem pin multiplexing options are described in Section 2.4, Signal Descriptions.

4. MODE: Multiplexing mode number.

a. Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the pin

corresponds to the name of the pin. There is always a function mapped on the primary mode.

Notice that primary mode is not necessarily the default mode.

Note: The default mode is the mode which is automatically configured on release of the internal

GLOBAL_PWRON reset; also see the RESET REL. MODE column.

b. Modes 1 to 7 are possible modes for alternate functions. On each pin, some modes are effectively

used for alternate functions, while some modes are not used and do not correspond to a functional

configuration.

5. TYPE: Signal direction

–

I = Input

O = Output

I/O = Input/Output

D = Open drain

DS = Differential

A = Analog

Note: In the safe_mode, the buffer is configured in high-impedance.

6. BALL RESET STATE: The state of the terminal at reset (power up).

–

0: The buffer drives V_OL(pulldown/pullup resistor not activated)

0(PD): The buffer drives V_OLwith an active pulldown resistor.

1: The buffer drives V_OH(pulldown/pullup resistor not activated)

1(PU): The buffer drives V_OHwith an active pullup resistor.

Z: High-impedance

–

L: High-impedance with an active pulldown resistor

H : High-impedance with an active pullup resistor

7. BALL RESET REL. STATE: The state of the terminal at reset release.

–

0: The buffer drives V_OL(pulldown/pullup resistor not activated)

0(PD): The buffer drives V_OLwith an active pulldown resistor.

1: The buffer drives V_OH(pulldown/pullup resistor not activated)

1(PU): The buffer drives V_OHwith an active pullup resistor.

Z: High-impedance

–

L: High-impedance with an active pulldown resistor

H : High-impedance with an active pullup resistor

8. RESET REL. MODE: This mode is automatically configured on release of the internal

GLOBAL_PWRON reset.

9. POWER: The voltage supply that powers the terminal’s I/O buffers.

10. HYS: Indicates if the input buffer is with hysteresis.

11. BUFFER STRENGTH: Drive strength of the associated output buffer.

12. PULL U/D - TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and

pulldown resistors can be enabled or disabled via software.

12

TERMINAL DESCRIPTION

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Note: The pullup/pulldown drive strength is equal to 100 µA except for CBB balls P27, P26, R27, and

R25, which the pulldown drive strength is equal to 1.8 kΩ.

13. IO CELL: IO cell information.

Note: Configuring two pins to the same input signal is not supported as it can yield unexpected results.

This can be easily prevented with the proper software configuration.

Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾

BALL

BOTTOM [1]

BALL

TOP [2]

NAME [3]

MODE [4] TYPE [5]

BALL

RESET

STATE [6]

BALL

RESET

REL.

RESET

REL.

MODE [8]

POWER [9]

HYS

[10]

BUFFER

STRENGTH

(mA) [11]

PULL

U/D

TYPE

[12]

IO

CELL [13]

STATE [7]

D6

C6

J2

J1

sdrc_d0

sdrc_d1

sdrc_d2

sdrc_d3

sdrc_d4

sdrc_d5

sdrc_d6

sdrc_d7

sdrc_d8

sdrc_d9

sdrc_d10

sdrc_d11

sdrc_d12

sdrc_d13

sdrc_d14

sdrc_d15

sdrc_d16

sdrc_d17

sdrc_d18

sdrc_d19

sdrc_d20

sdrc_d21

sdrc_d22

sdrc_d23

sdrc_d24

sdrc_d25

sdrc_d26

sdrc_d27

sdrc_d28

sdrc_d29

sdrc_d30

sdrc_d31

sdrc_ba0

sdrc_ba1

sdrc_a0

sdrc_a1

sdrc_a2

sdrc_a3

sdrc_a4

sdrc_a5

sdrc_a6

sdrc_a7

sdrc_a8

sdrc_a9

sdrc_a10

0

IO

O

L

0

Z

0

VDDS_ MEM

Yes

No

4

PU/ PD

NA

LVCMOS

B6

G2

C8

G1

C9

F2

A7

F1

B9

D2

A9

D1

C14

B14

C15

B16

D17

C17

B17

D18

D11

B10

C11

D12

C12

A11

B13

D14

C18

A19

B19

B20

D20

A21

B21

C21

H9

B13

A13

B14

A14

B16

A16

B19

A19

B3

A3

B5

A5

B8

A8

B9

A9

B21

A21

D22

D23

E22

E23

G22

G23

AB21

AC21

N22

N23

P22

P23

R22

R23

T22

T23

U22

U23

V22

H10

A4

O

No

NA

O

No

NA

B4

O

No

NA

B3

O

No

NA

C5

O

No

NA

C4

O

No

NA

D5

O

No

NA

C3

O

No

NA

C2

O

No

NA

C1

O

No

NA

D4

O

No

NA

D3

O

No

NA

(1) NA in this table stands for Not Applicable.

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Table 2-1. Ball Characteristics (CBB Pkg.) (continued)

BALL

BOTTOM [1]

BALL

TOP [2]

NAME [3]

MODE [4] TYPE [5]

BALL

RESET

STATE [6]

BALL

RESET

REL.

RESET

REL.

MODE [8]

POWER [9]

HYS

[10]

BUFFER

STRENGTH

(mA) [11]

PULL

U/D

TYPE

[12]

IO

CELL [13]

STATE [7]

D2

D1

V23

W22

W23

Y22

M22

M23

A11

B11

J22

sdrc_a11

sdrc_a12

sdrc_a13

sdrc_a14

sdrc_ncs0

sdrc_ncs1

sdrc_clk

0

7

0

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

1

4

7

0

1

4

O

IO

O

0

1

L

1

H

0

1

0

1

0

7

VDDS_ MEM

No

Yes

No

Yes

4

NA

LVCMOS

E2

NA

E1

NA

H11

H12

A13

A14

H16

NA

PU/ PD

NA

sdrc_nclk

sdrc_cke0

safe_mode

sdrc_cke1

safe_mode

sdrc_nras

sdrc_ncas

sdrc_nwe

sdrc_dm0

sdrc_dm1

sdrc_dm2

sdrc_dm3

sdrc_dqs0

sdrc_dqs1

sdrc_dqs2

sdrc_dqs3

gpmc_a1

gpio_34

PU/ PD

H17

J23

O

H

1

7

VDDS_ MEM

Yes

4

PU/ PD

LVCMOS

H14

H13

H15

B7

L23

L22

K23

C1

O

1

0

L

1

0

Z

L

0

7

VDDS_ MEM

No

4

NA

LVCMOS

O

No

NA

O

No

NA

A16

B11

C20

A6

A17

A6

O

No

NA

O

No

NA

A20

C2

O

No

NA

IO

O

Yes

PU/ PD

A17

A10

A20

N4

B17

B6

B20

AC15

IO

safe_mode

gpmc_a2

gpio_35

M4

L4

AB15

AC16

AB16

AC17

AB17

AC18

AB18

AC19

O

L

7

VDDS_ MEM

Yes

4

PU/ PD

LVCMOS

IO

safe_mode

gpmc_a3

gpio_36

O

IO

safe_mode

gpmc_a4

gpio_37

K4

T3

R3

N3

M3

L3

O

L

IO

safe_mode

gpmc_a5

gpio_38

O

L

IO

safe_mode

gpmc_a6

gpio_39

O

H

IO

safe_mode

gpmc_a7

gpio_40

O

IO

safe_mode

gpmc_a8

gpio_41

O

IO

safe_mode

gpmc_a9

sys_ ndmareq2

gpio_42

O

I

IO

safe_mode

gpmc_a10

sys_ ndmareq3

gpio_43

K3

AB19

O

I

H

7

VDDS_ MEM

Yes

4

PU/ PD

LVCMOS

IO

14

TERMINAL DESCRIPTION

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Table 2-1. Ball Characteristics (CBB Pkg.) (continued)

BALL

BOTTOM [1]

BALL

TOP [2]

NAME [3]

MODE [4] TYPE [5]

BALL

RESET

STATE [6]

BALL

RESET

REL.

RESET

REL.

MODE [8]

POWER [9]

HYS

[10]

BUFFER

STRENGTH

(mA) [11]

PULL

U/D

TYPE

[12]

IO

CELL [13]

STATE [7]

safe_mode

gpmc_d0

7

K1

L1

M2

M1

N2

N1

R2

R1

T2

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

1

4

7

0

1

2

3

4

7

0

1

2

3

IO

H

0

VDDS_ MEM

Yes

4

PU/ PD

LVCMOS

gpmc_d1

L2

gpmc_d2

P2

T1

V1

V2

W2

H2

gpmc_d3

gpmc_d4

gpmc_d5

gpmc_d6

T1

gpmc_d7

AB3

gpmc_d8

gpio_44

safe_mode

gpmc_d9

K2

P1

R1

R2

T2

AC3

AB4

AC4

AB6

AC6

AB7

AC7

IO

H

0

VDDS_ MEM

Yes

4

PU/ PD

LVCMOS

gpio_45

safe_mode

gpmc_d10

gpio_46

IO

safe_mode

gpmc_d11

gpio_47

IO

safe_mode

gpmc_d12

gpio_48

IO

safe_mode

gpmc_d13

gpio_49

IO

safe_mode

gpmc_d14

gpio_50

W1

Y1

IO

safe_mode

gpmc_d15

gpio_51

IO

safe_mode

gpmc_ncs0

gpmc_ncs1

gpio_52

G4

H3

Y2

Y1

O

1

0

VDDS_ MEM

No

4

NA

LVCMOS

H

Yes

PU/ PD

IO

safe_mode

gpmc_ncs2

gpio_53

V8

U8

NA

O

H

7

VDDS_ MEM

Yes

4

PU/ PD

LVCMOS

IO

safe_mode

gpmc_ncs3

sys_ ndmareq0

gpio_54

O

I

IO

safe_mode

gpmc_ncs4

sys_ ndmareq1

mcbsp4_ clkx

gpt9_pwm_evt

gpio_55

T8

NA

O

I

H

7

VDDS_ MEM

Yes

4

PU/ PD

LVCMOS

IO

safe_mode

gpmc_ncs5

sys_ ndmareq2

mcbsp4_dr

gpt10_pwm_evt

R8

NA

O

I

H

7

VDDS_ MEM

Yes

4

PU/ PD

LVCMOS

I

IO

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Table 2-1. Ball Characteristics (CBB Pkg.) (continued)

BALL

BOTTOM [1]

BALL

TOP [2]

NAME [3]

MODE [4] TYPE [5]

BALL

RESET

STATE [6]

BALL

RESET

REL.

RESET

REL.

MODE [8]

POWER [9]

HYS

[10]

BUFFER

STRENGTH

(mA) [11]

PULL

U/D

TYPE

[12]

IO

CELL [13]

STATE [7]

gpio_56

safe_mode

gpmc_ncs6

sys_ ndmareq3

mcbsp4_dx

gpt11_pwm_evt

gpio_57

4

7

0

1

2

3

4

7

0

1

2

3

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

1

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

2

IO

P8

N8

T4

NA

W2

O

I

H

L

H

0

7

0

VDDS_ MEM

Yes

4

PU/ PD

LVCMOS

IO

safe_mode

gpmc_ncs7

gpmc_io_dir

mcbsp4_fsx

gpt8_pwm_evt

gpio_58

O

VDDS_ MEM

IO

safe_mode

gpmc_clk

O

VDDS_ MEM

gpio_59

IO

safe_mode

gpmc_nadv_ale

gpmc_noe

gpmc_nwe

gpmc_nbe0_cle

gpio_60

F3

G2

F4

G3

W1

V2

O

0

1

L

0

1

0

VDDS_ MEM

No

4

NA

LVCMOS

V1

O

No

NA

AC12

O

Yes

PU/ PD

IO

safe_mode

gpmc_nbe1

gpio_61

U3

H1

NA

O

L

0

7

0

VDDS_ MEM

Yes

4

PU/ PD

LVCMOS

IO

safe_mode

gpmc_nwp

gpio_62

AB10

O

IO

safe_mode

gpmc_wait0

gpmc_wait1

gpio_63

M8

L8

AB12

AC10

I

H

0

7

VDDS_ MEM

Yes

NA

4

PU/ PD

LVCMOS

IO

safe_mode

gpmc_wait2

gpio_64

K8

J8

NA

I

H

7

VDDS_ MEM

Yes

4

PU/ PD

LVCMOS

IO

safe_mode

gpmc_wait3

sys_ ndmareq1

gpio_65

I

IO

safe_mode

dss_pclk

D28

D26

NA

O

H

L

H

L

7

VDDS

Yes

8

PU/ PD

LVCMOS

gpio_66

IO

safe_mode

dss_hsync

gpio_67

O

IO

safe_mode

dss_vsync

gpio_68

D27

O

IO

safe_mode

dss_acbias

gpio_69

E27

O

IO

safe_mode

dss_data0

uart1_cts

AG22

IO

I

L

PU/ PD LVDS/ CMOS

16

TERMINAL DESCRIPTION

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SPRS599–JUNE 2009

Table 2-1. Ball Characteristics (CBB Pkg.) (continued)

BALL

BOTTOM [1]

BALL

TOP [2]

NAME [3]

MODE [4] TYPE [5]

BALL

RESET

STATE [6]

BALL

RESET

REL.

RESET

REL.

MODE [8]

POWER [9]

HYS

[10]

BUFFER

STRENGTH

(mA) [11]

PULL

U/D

TYPE

[12]

IO

CELL [13]

STATE [7]

gpio_70

safe_mode

dss_data1

uart1_rts

4

7

0

2

4

7

0

4

7

0

4

7

0

2

4

7

0

2

4

7

0

2

4

7

0

2

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

IO

AH22

NA

IO

O

L

7

VDDS

Yes

8

PU/ PD LVDS/ CMOS

gpio_71

IO

safe_mode

dss_data2

gpio_72

AG23

AH23

AG24

NA

IO

L

7

VDDS

Yes

8

PU/ PD LVDS/ CMOS

safe_mode

dss_data3

gpio_73

IO

safe_mode

dss_data4

uart3_rx_ irrx

gpio_74

IO

I

IO

safe_mode

dss_data5

uart3_tx_ irtx

gpio_75

AH24

E26

NA

IO

O

L

7

VDDS

Yes

8

PU/ PD LVDS/ CMOS

IO

safe_mode

dss_data6

uart1_tx

IO

O

PU/ PD

LVCMOS

gpio_76

IO

safe_mode

dss_data7

uart1_rx

F28

IO

I

gpio_77

IO

safe_mode

dss_data8

gpio_78

F27

G26

NA

IO

L

7

VDDS

Yes

＝Yes

Yes

8

PU/ PD

LVCMOS

safe_mode

dss_data9

gpio_79

IO

safe_mode

dss_data10

gpio_80

AD28

AD27

AB28

AB27

AA28

AA27

G25

IO

PU/ PD LVDS/ CMOS

safe_mode

dss_data11

gpio_81

IO

safe_mode

dss_data12

gpio_82

IO

safe_mode

dss_data13

gpio_83

IO

safe_mode

dss_data14

gpio_84

IO

safe_mode

dss_data15

gpio_85

IO

safe_mode

dss_data16

gpio_86

IO

PU/ PD

LVCMOS

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TERMINAL DESCRIPTION

17

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

SPRS599–JUNE 2009

www.ti.com

Table 2-1. Ball Characteristics (CBB Pkg.) (continued)

BALL

BOTTOM [1]

BALL

TOP [2]

NAME [3]

MODE [4] TYPE [5]

BALL

RESET

STATE [6]

BALL

RESET

REL.

RESET

REL.

MODE [8]

POWER [9]

HYS

[10]

BUFFER

STRENGTH

(mA) [11]

PULL

U/D

TYPE

[12]

IO

CELL [13]

STATE [7]

safe_mode

dss_data17

gpio_87

7

H27

H26

NA

0

4

7

0

2

3

4

7

0

2

3

4

7

0

2

3

4

7

0

2

3

4

7

0

2

3

4

7

0

3

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

2

4

IO

L

7

VDDS

Yes

8

PU/ PD

LVCMOS

safe_mode

dss_data18

mcspi3_clk

dss_data0

gpio_88

IO

safe_mode

dss_data19

mcspi3_ simo

dss_data1

gpio_89

H25

E28

NA

IO

L

H

L

H

L

7

VDDS

Yes

8

PU/ PD

LVCMOS

safe_mode

dss_data20

mcspi3_ somi

dss_data2

gpio_90

O

IO

safe_mode

dss_data21

mcspi3_cs0

dss_data3

gpio_91

J26

O

IO

safe_mode

dss_data22

mcspi3_cs1

dss_data4

gpio_92

AC27

AC28

O

PU/ PD LVDS/ CMOS

IO

safe_mode

dss_data23

dss_data5

gpio_93

O

PU/ PD LVDS/ CMOS

IO

safe_mode

tv_out2

W28

Y28

Y27

W27

W26

A24

NA

O

Z

L

0

7

VDDADAC

VDDS

NA⁽²⁾

4

NA

10-bit DAC

LVCMOS

tv_out1

tv_vfb1

AO

IO

NA

L

NA

tv_vfb2

NA

tv_vref

NA

cam_hs

Yes

PU/ PD

gpio_94

IO

safe_mode

cam_vs

A23

C25

C27

C23

NA

IO

L

7

VDDS

4

PU/ PD

LVCMOS

gpio_95

safe_mode

cam_ xclka

gpio_96

O

IO

safe_mode

cam_pclk

gpio_97

I

IO

safe_mode

cam_fld

IO

cam_global_reset

gpio_98

(2) The drive strength is fixed regardless of the load. The driver is designed to drive 75Ω for video applications.

18 TERMINAL DESCRIPTION Submit Documentation Feedback

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SPRS599–JUNE 2009

Table 2-1. Ball Characteristics (CBB Pkg.) (continued)

BALL

BOTTOM [1]

BALL

TOP [2]

NAME [3]

MODE [4] TYPE [5]

BALL

RESET

STATE [6]

BALL

RESET

REL.

RESET

REL.

MODE [8]

POWER [9]

HYS

[10]

BUFFER

STRENGTH

(mA) [11]

PULL

U/D

TYPE

[12]

IO

CELL [13]

STATE [7]

safe_mode

cam_d0

7

AG17

AH17

B24

C24

D24

A25

K28

L28

NA

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

2

4

7

0

4

7

4

7

4

7

4

7

4

I

L

7

VDDS

Yes＝

Yes

NA

4

PU/PD

PU/ PD

PU/PD

PU/ PD

LVDS/ CMOS

LVCMOS

gpio_99

safe_mode

cam_d1

I

gpio_100

safe_mode

cam_d2

I

gpio_101

safe_mode

cam_d3

IO

I

4

LVCMOS

gpio_102

safe_mode

cam_d4

IO

I

4

LVCMOS

gpio_103

safe_mode

cam_d5

IO

I

4

LVCMOS

gpio_104

safe_mode

cam_d6

IO

I

NA

8

LVDS/ CMOS

LVCMOS

gpio_105

safe_mode

cam_d7

IO

NA

8

I

gpio_106

safe_mode

cam_d8

IO

NA

8

K27

L27

I

gpio_107

safe_mode

cam_d9

IO

NA

8

I

gpio_108

safe_mode

cam_d10

gpio_109

safe_mode

cam_d11

gpio_110

safe_mode

cam_ xclkb

gpio_111

safe_mode

cam_wen

cam_ shutter

gpio_167

safe_mode

cam_ strobe

gpio_126

safe_mode

gpio_112

safe_mode

gpio_113

safe_mode

gpio_114

safe_mode

gpio_115

IO

NA

4

B25

C26

B26

B23

I

IO

I

4

LVCMOS

IO

O

LVCMOS

IO

I

LVCMOS

O

IO

D25

NA

O

L

7

VDDS

Yes

4

PU/ PD

LVCMOS

IO

AG19

AH19

AG18

AH18

NA

I

L

7

VDDS

Yes

NA

PU/PD

LVDS/ CMOS

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TERMINAL DESCRIPTION

19

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

SPRS599–JUNE 2009

www.ti.com

Table 2-1. Ball Characteristics (CBB Pkg.) (continued)

BALL

BOTTOM [1]

BALL

TOP [2]

NAME [3]

MODE [4] TYPE [5]

BALL

RESET

STATE [6]

BALL

RESET

REL.

RESET

REL.

MODE [8]

POWER [9]

HYS

[10]

BUFFER

STRENGTH

(mA) [11]

PULL

U/D

TYPE

[12]

IO

CELL [13]

STATE [7]

safe_mode

mcbsp2_fsx

gpio_116

7

P21

N21

R21

M21

N28

M27

N27

N26

N25

P28

P27

P26

R27

R25

AE2

NA

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

1

4

7

0

1

4

IO

L

7

VDDS

Yes

No＝

No

4⁽³⁾

8

PU/ PD

PU/ PD⁽⁴⁾

PD⁽⁴⁾

LVCMOS

safe_mode

mcbsp2_ clkx

gpio_117

IO

VDDS

safe_mode

mcbsp2_dr

gpio_118

I

VDDS

IO

safe_mode

mcbsp2_dx

gpio_119

IO

VDDS

safe_mode

mmc1_clk

gpio_120

O

VDDS_MMC1

VDDS_MMC1a

VDDS

IO

safe_mode

mmc1_cmd

gpio_121

IO

8

safe_mode

mmc1_dat0

gpio_122

IO

8

safe_mode

mmc1_dat1

gpio_123

IO

8

safe_mode

mmc1_dat2

gpio_124

IO

8

safe_mode

mmc1_dat3

gpio_125

IO

8

safe_mode

mmc1_dat4

gpio_126

IO

8

safe_mode

mmc1_dat5

gpio_127

IO

8

PD⁽⁴⁾

safe_mode

mmc1_dat6

gpio_128

IO

8

PD⁽⁴⁾

safe_mode

mmc1_dat7

gpio_129

IO

No

8

PD⁽⁴⁾

safe_mode

mmc2_clk

mcspi3_clk

gpio_130

O

Yes

4

PU/ PD

IO

safe_mode

mmc2_ cmd

mcspi3_ simo

gpio_131

AG5

NA

IO

H

7

VDDS

Yes

4

PU/ PD

LVCMOS

(3) The buffer strength of this IO cell is programmable (2, 4, 6, or 8 mA) according to the selected mode; the default value is described in

the above table.

(4) The PU nominal drive strength of this IO cell is equal to 25 µA @ 1.8V and 41.6 µA @ 3.0V. The PD nominal drive strength of this IO

cell is equal to 1 mA @ 1.8V and 1.66 mA @ 3.0V.

20

TERMINAL DESCRIPTION

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SPRS599–JUNE 2009

Table 2-1. Ball Characteristics (CBB Pkg.) (continued)

BALL

BOTTOM [1]

BALL

TOP [2]

NAME [3]

MODE [4] TYPE [5]

BALL

RESET

STATE [6]

BALL

RESET

REL.

RESET

REL.

MODE [8]

POWER [9]

HYS

[10]

BUFFER

STRENGTH

(mA) [11]

PULL

U/D

TYPE

[12]

IO

CELL [13]

STATE [7]

safe_mode

mmc2_ dat0

mcspi3_ somi

gpio_132

7

AH5

NA

0

1

4

7

0

4

7

0

1

4

7

0

1

4

7

0

1

3

4

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

7

0

1

3

4

5

6

7

0

1

4

5

7

0

1

4

5

7

IO

H

7

VDDS

Yes

4

PU/ PD

LVCMOS

safe_mode

mmc2_ dat1

gpio_133

AH4

AG4

NA

IO

H

7

VDDS

Yes

4

PU/ PD

LVCMOS

safe_mode

mmc2_ dat2

mcspi3_cs1

gpio_134

IO

O

IO

safe_mode

mmc2_ dat3

mcspi3_cs0

gpio_135

AF4

AE4

NA

IO

H

L

H

L

7

VDDS

Yes

4

PU/ PD

LVCMOS

safe_mode

mmc2_ dat4

mmc2_dir_dat0

mmc3_dat0

gpio_136

IO

O

IO

safe_mode

mmc2_ dat5

mmc2_dir_dat1

cam_global_reset

mmc3_dat1

gpio_137

AH3

NA

IO

O

L

7

VDDS

Yes

4

PU/ PD

LVCMOS

IO

hsusb3_tll_stp

mm3_rxdp

safe_mode

mmc2_ dat6

mmc2_dir_ cmd

cam_ shutter

mmc3_dat2

gpio_138

AF3

NA

IO

O

L

7

VDDS

Yes

4

PU/ PD

LVCMOS

O

IO

hsusb3_tll_dir

safe_mode

mmc2_ dat7

mmc2_ clkin

mmc3_dat3

gpio_139

AE3

NA

IO

I

L

7

VDDS

Yes

4

PU/ PD

LVCMOS

IO

hsusb3_tll_nxt

mm3_rxdm

safe_mode

mcbsp3_dx

uart2_cts

AF6

AE6

NA

IO

I

L

7

VDDS

Yes

4

PU/ PD

LVCMOS

gpio_140

IO

hsusb3_tll_ data4

safe_mode

mcbsp3_dr

uart2_rts

I

PU/ PD

O

gpio_141

IO

hsusb3_tll_ data5

safe_mode

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TERMINAL DESCRIPTION

21

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

SPRS599–JUNE 2009

www.ti.com

Table 2-1. Ball Characteristics (CBB Pkg.) (continued)

BALL

BOTTOM [1]

BALL

TOP [2]

NAME [3]

MODE [4] TYPE [5]

BALL

RESET

STATE [6]

BALL

RESET

REL.

RESET

REL.

MODE [8]

POWER [9]

HYS

[10]

BUFFER

STRENGTH

(mA) [11]

PULL

U/D

TYPE

[12]

IO

CELL [13]

STATE [7]

AF5

AE5

NA

mcbsp3_ clkx

uart2_tx

0

1

4

5

7

0

1

4

5

7

0

1

2

4

7

0

1

2

4

7

0

1

2

4

7

0

1

2

4

7

0

4

7

0

4

7

0

4

5

7

0

2

3

4

7

0

4

5

6

7

0

4

5

6

IO

O

L

7

VDDS

Yes

4

PU/ PD

LVCMOS

gpio_142

IO

hsusb3_tll_ data6

safe_mode

mcbsp3_fsx

uart2_rx

IO

I

L

VDDS

gpio_143

IO

hsusb3_tll_ data7

safe_mode

uart2_cts

AB26

AB25

AA25

AD25

I

H

mcbsp3_dx

gpt9_pwm_evt

gpio_144

IO

safe_mode

uart2_rts

O

I

mcbsp3_dr

gpt10_pwm_evt

gpio_145

IO

safe_mode

uart2_tx

O

mcbsp3_ clkx

gpt11_pwm _evt

gpio_146

IO

safe_mode

uart2_rx

I

mcbsp3_fsx

gpt8_pwm_evt

gpio_147

IO

safe_mode

uart1_tx

AA8

AA9

W8

NA

O

L

7

VDDS

Yes

4

PU/ PD

LVCMOS

gpio_148

IO

safe_mode

uart1_rts

O

gpio_149

IO

safe_mode

uart1_cts

I

gpio_150

IO

O

hsusb3_tll_clk

safe_mode

uart1_rx

Y8

NA

I

L

7

VDDS

Yes

4

PU/ PD

LVCMOS

mcbsp1_ clkr

mcspi4_clk

gpio_151

IO

safe_mode

mcbsp4_ clkx

gpio_152

AE1

AD1

IO

hsusb3_tll_ data1

mm3_txse0

safe_mode

mcbsp4_dr

gpio_153

I

IO

hsusb3_tll_ data0

mm3_rxrcv

22

TERMINAL DESCRIPTION

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SPRS599–JUNE 2009

Table 2-1. Ball Characteristics (CBB Pkg.) (continued)

BALL

BOTTOM [1]

BALL

TOP [2]

NAME [3]

MODE [4] TYPE [5]

BALL

RESET

STATE [6]

BALL

RESET

REL.

RESET

REL.

MODE [8]

POWER [9]

HYS

[10]

BUFFER

STRENGTH

(mA) [11]

PULL

U/D

TYPE

[12]

IO

CELL [13]

STATE [7]

safe_mode

mcbsp4_dx

gpio_154

7

AD2

AC1

NA

0

4

5

6

7

0

4

5

6

7

0

1

4

7

0

2

4

7

0

1

2

4

7

0

1

2

4

7

0

2

4

5

7

0

1

2

4

7

0

2

4

7

0

4

7

0

4

7

0

4

7

0

4

IO

L

7

VDDS

Yes

4

PU/ PD

LVCMOS

hsusb3_tll_ data2

mm3_txdat

safe_mode

mcbsp4_fsx

gpio_155

IO

VDDS

PU/ PD

hsusb3_tll_ data3

mm3_txen_n

safe_mode

mcbsp1_ clkr

mcspi4_clk

gpio_156

Y21

AA21

V21

NA

IO

L

7

VDDS

Yes

4

PU/ PD

LVCMOS

safe_mode

mcbsp1_fsr

cam_global_reset

gpio_157

IO

safe_mode

mcbsp1_dx

mcspi4_ simo

mcbsp3_dx

gpio_158

IO

safe_mode

mcbsp1_dr

mcspi4_ somi

mcbsp3_dr

gpio_159

U21

T21

K26

W21

NA

I

L

7

VDDS

Yes

4

PU/ PD

LVCMOS

IO

O

IO

safe_mode

mcbsp_clks

cam_ shutter

gpio_160

I

O

IO

I

uart1_cts

safe_mode

mcbsp1_fsx

mcspi4_cs0

mcbsp3_fsx

gpio_161

IO

safe_mode

mcbsp1_ clkx

mcbsp3_ clkx

gpio_162

IO

safe_mode

uart3_cts_ rctx

gpio_163

H18

H19

H20

H21

NA

IO

H

7

VDDS

Yes

4

PU/ PD

LVCMOS

safe_mode

uart3_rts_ sd

gpio_164

O

IO

safe_mode

uart3_rx_ irrx

gpio_165

I

IO

safe_mode

uart3_tx_ irtx

gpio_166

O

IO

Submit Documentation Feedback

TERMINAL DESCRIPTION

23

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

SPRS599–JUNE 2009

www.ti.com

Table 2-1. Ball Characteristics (CBB Pkg.) (continued)

BALL

BOTTOM [1]

BALL

TOP [2]

NAME [3]

MODE [4] TYPE [5]

BALL

RESET

STATE [6]

BALL

RESET

REL.

RESET

REL.

MODE [8]

POWER [9]

HYS

[10]

BUFFER

STRENGTH

(mA) [11]

PULL

U/D

TYPE

[12]

IO

CELL [13]

STATE [7]

safe_mode

hsusb0_clk

gpio_120

7

T28

T25

R28

T26

T27

NA

0

4

7

0

4

7

0

4

7

0

4

7

0

2

4

7

0

2

4

7

0

2

4

7

0

2

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

I

L

H

L

H

L

7

VDDS

Yes

4

PU/ PD

LVCMOS

IO

safe_mode

hsusb0_stp

gpio_121

O

IO

safe_mode

hsusb0_dir

gpio_122

I

IO

safe_mode

hsusb0_nxt

gpio_124

I

IO

safe_mode

hsusb0_ data0

uart3_tx_ irtx

gpio_125

IO

O

IO

safe_mode

hsusb0_ data1

uart3_rx_ irrx

gpio_130

U28

U27

U26

NA

IO

I

L

7

VDDS

Yes

4

PU/ PD

LVCMOS

IO

safe_mode

hsusb0_ data2

uart3_rts_ sd

gpio_131

IO

O

IO

safe_mode

hsusb0_ data3

uart3_cts_ rctx

gpio_169

IO

safe_mode

hsusb0_ data4

gpio_188

U25

V28

V27

V26

NA

IO

L

7

VDDS

Yes

4

PU/ PD

LVCMOS

safe_mode

hsusb0_ data5

gpio_189

IO

safe_mode

hsusb0_ data6

gpio_190

IO

safe_mode

hsusb0_ data7

gpio_191

IO

safe_mode

i2c1_scl

K21

J21

NA

IOD

IO

H

0

7

VDDS

Yes

4

PU/ PD

Open Drain

i2c1_sda

AF15

i2c2_scl

gpio_168

safe_mode

i2c2_sda

AE15

AF14

AG14

NA

IOD

IO

H

7

VDDS

Yes

4

PU/ PD

Open Drain

gpio_183

safe_mode

i2c3_scl

IOD

IO

gpio_184

safe_mode

i2c3_sda

IOD

IO

gpio_185

24

TERMINAL DESCRIPTION

Submit Documentation Feedback

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SPRS599–JUNE 2009

Table 2-1. Ball Characteristics (CBB Pkg.) (continued)

BALL

BOTTOM [1]

BALL

TOP [2]

NAME [3]

MODE [4] TYPE [5]

BALL

RESET

STATE [6]

BALL

RESET

REL.

RESET

REL.

MODE [8]

POWER [9]

HYS

[10]

BUFFER

STRENGTH

(mA) [11]

PULL

U/D

TYPE

[12]

IO

CELL [13]

STATE [7]

safe_mode

i2c4_scl

7

AD26

AE26

J25

NA

0

1

7

0

1

7

0

1

2

3

4

7

0

1

4

7

0

1

4

7

0

1

4

7

0

1

4

7

0

3

4

7

0

3

4

7

0

2

3

4

5

7

0

2

3

4

7

0

1

2

3

4

7

IOD

O

H

0

7

VDDS

Yes

4

PU/ PD

Open Drain

LVCMOS

sys_ nvmode1

safe_mode

i2c4_sda

IOD

O

sys_ nvmode2

safe_mode

hdq_sio

IOD

I

sys_altclk

i2c2_sccbe

i2c3_sccbe

gpio_170

O

IO

safe_mode

mcspi1_clk

mmc2_dat4

gpio_171

AB3

AB4

AA4

AC2

AC3

AB1

AB2

NA

IO

L

7

VDDS

Yes

4⁽³⁾

4

PU/ PD

LVCMOS

safe_mode

mcspi1_ simo

mmc2_dat5

gpio_172

IO

safe_mode

mcspi1_ somi

mmc2_dat6

gpio_173

IO

L

safe_mode

mcspi1_cs0

mmc2_dat7

gpio_174

IO

H

L

H

safe_mode

mcspi1_cs1

mmc3_cmd

gpio_175

O

IO

safe_mode

mcspi1_cs2

mmc3_clk

O

L

gpio_176

IO

safe_mode

mcspi1_cs3

hsusb2_tll_ data2

hsusb2_ data2

gpio_177

O

H

IO

mm2_txdat

safe_mode

mcspi2_clk

hsusb2_tll_ data7

hsusb2_ data7

gpio_178

AA3

NA

IO

O

L

7

VDDS

Yes

4

PU/ PD

LVCMOS

IO

safe_mode

mcspi2_ simo

gpt9_pwm_evt

hsusb2_tll_ data4

hsusb2_ data4

gpio_179

Y2

IO

I

PU/ PD

IO

safe_mode

Submit Documentation Feedback

TERMINAL DESCRIPTION

25

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

SPRS599–JUNE 2009

www.ti.com

Table 2-1. Ball Characteristics (CBB Pkg.) (continued)

BALL

BOTTOM [1]

BALL

TOP [2]

NAME [3]

MODE [4] TYPE [5]

BALL

RESET

STATE [6]

BALL

RESET

REL.

RESET

REL.

MODE [8]

POWER [9]

HYS

[10]

BUFFER

STRENGTH

(mA) [11]

PULL

U/D

TYPE

[12]

IO

CELL [13]

STATE [7]

Y3

Y4

V3

NA

mcspi2_ somi

gpt10_pwm_evt

hsusb2_tll_ data5

hsusb2_ data5

gpio_180

0

1

2

3

4

7

0

1

2

3

4

7

0

1

2

3

4

5

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

1

4

7

0

1

4

7

0

4

IO

O

L

H

L

H

L

7

VDDS

Yes

4

PU/ PD

LVCMOS

IO

safe_mode

mcspi2_cs0

gpt11_pwm_evt

hsusb2_tll_ data6

hsusb2_ data6

gpio_181

IO

O

VDDS

IO

safe_mode

mcspi2_cs1

gpt8_pwm_evt

hsusb2_tll_ data3

hsusb2_ data3

gpio_182

O

VDDS

IO

mm2_txen_n

safe_mode

sys_32k

AE25

AE17

AF17

AF25

NA

I

Z

0

I

NA

0

VDDS

Yes

NA

8

NA

LVCMOS

sys_xtalin

I

sys_xtalout

sys_clkreq

gpio_1

O

IO

O

1

NA

Yes

PU/ PD

safe_mode

sys_nirq

AF26

NA

I

H

7

VDDS

Yes

4

PU/ PD

LVCMOS

gpio_0

IO

safe_mode

sys_ nrespwron

sys_ nreswarm

gpio_30

AH25

AF24

NA

I

Z

0

I

NA

0

VDDS

Yes

NA＝

NA

LVCMOS

IOD

IO

1 (PU)

8

PU/ PD

Open Drain

safe_mode

sys_boot0

gpio_2

AH26

AG26

AE14

AF18

AF19

NA

I

Z

0

VDDS

Yes

4

PU/ PD

LVCMOS

IO

safe_mode

sys_boot1

gpio_3

I

IO

safe_mode

sys_boot2

gpio_4

I

IO

safe_mode

sys_boot3

gpio_5

I

IO

safe_mode

sys_boot4

mmc2_dir_dat2

gpio_6

I

O

IO

safe_mode

sys_boot5

mmc2_dir_dat3

gpio_7

AE21

AF21

NA

I

Z

0

VDDS

Yes

4

PU/ PD

LVCMOS

O

IO

safe_mode

sys_boot6

gpio_8

I

IO

26

TERMINAL DESCRIPTION

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OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

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SPRS599–JUNE 2009

Table 2-1. Ball Characteristics (CBB Pkg.) (continued)

BALL

BOTTOM [1]

BALL

TOP [2]

NAME [3]

MODE [4] TYPE [5]

BALL

RESET

STATE [6]

BALL

RESET

REL.

RESET

REL.

MODE [8]

POWER [9]

HYS

[10]

BUFFER

STRENGTH

(mA) [11]

PULL

U/D

TYPE

[12]

IO

CELL [13]

STATE [7]

safe_mode

sys_off_ mode

gpio_9

7

AF22

AG25

AE22

NA

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

1

2

3

4

5

6

0

2

3

4

6

0

1

2

3

4

5

6

0

1

3

4

5

6

O

0

L

7

VDDS

Yes

8

4

PU/ PD

LVCMOS

IO

safe_mode

sys_clkout1

gpio_10

O

IO

safe_mode

sys_clkout2

gpio_186

O

IO

safe_mode

sys_ ipmcsws

sys_ opmcsws

jtag_ntrst

B1

NA

AI

AO

I

Z

0

AI

AO

L

NA

0

VDDS

＝NA

No

NA

＝NA

8

NA

Analog

A1

NA

LVCMOS

AA17

AA13

AA12

AA18

AA20

AA19

AA11

L

Yes

PU/ PD

jtag_tck

I

L

0

jtag_rtck

O

IO

I

L

0

jtag_tms_tmsc

jtag_tdi

H

L

H

Z

0

8

0

＝NA

8

jtag_tdo

O

IO

0

jtag_emu0

gpio_11

H

0

8

safe_mode

jtag_emu1

gpio_31

AA10

AF10

NA

IO

H

0

4

VDDS

Yes

8

4

PU/ PD

LVCMOS

safe_mode

etk_clk

O

IO

O

mcbsp5_ clkx

mmc3_clk

hsusb1_stp

gpio_12

O

IO

I

mm1_rxdp

hsusb1_tll_stp

etk_ctl

AE10

AF11

NA

O

H

4

VDDS

Yes

4

PU/ PD

LVCMOS

mmc3_cmd

hsusb1_clk

gpio_13

IO

O

IO

O

hsusb1_tll_clk

etk_d0

O

PU/ PD

mcspi3_ simo

mmc3_dat4

hsusb1_ data0

gpio_14

IO

O

mm1_rxrcv

hsusb1_tll_ data0

etk_d1

AG12

NA

H

4

VDDS

Yes

4

PU/ PD

LVCMOS

mcspi3_ somi

hsusb1_ data1

gpio_15

IO

mm1_txse0

hsusb1_tll_ data1

Submit Documentation Feedback

TERMINAL DESCRIPTION

27

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

SPRS599–JUNE 2009

www.ti.com

Table 2-1. Ball Characteristics (CBB Pkg.) (continued)

BALL

BOTTOM [1]

BALL

TOP [2]

NAME [3]

MODE [4] TYPE [5]

BALL

RESET

STATE [6]

BALL

RESET

REL.

RESET

REL.

MODE [8]

POWER [9]

HYS

[10]

BUFFER

STRENGTH

(mA) [11]

PULL

U/D

TYPE

[12]

IO

CELL [13]

STATE [7]

AH12

AE13

AE11

AH9

NA

etk_d2

mcspi3_cs0

hsusb1_ data2

gpio_16

0

1

3

4

5

6

0

1

2

3

4

6

0

1

2

3

4

6

0

1

2

3

4

6

0

1

2

3

4

6

0

1

2

3

4

5

6

0

1

O

IO

O

H

L

H

L

4

VDDS

Yes

4

PU/ PD

LVCMOS

mm1_txdat

hsusb1_tll_data2

etk_d3

VDDS

mcspi3_clk

mmc3_dat3

hsusb1_ data7

gpio_17

IO

O

hsusb1_tll_ data7

etk_d4

mcbsp5_dr

mmc3_dat0

hsusb1_ data4

gpio_18

I

IO

O

hsusb1_tll_ data4

etk_d5

mcbsp5_fsx

mmc3_dat1

hsusb1_ data5

gpio_19

IO

O

hsusb1_tll_ data5

etk_d6

AF13

mcbsp5_dx

mmc3_dat2

hsusb1_ data6

gpio_20

IO

O

hsusb1_tll_ data6

etk_d7

AH14

mcspi3_cs1

mmc3_dat7

hsusb1_ data3

gpio_21

O

IO

O

mm1_txen_n

hsusb1_tll_ data3

etk_d8

AF9

NA

L

4

VDDS

Yes

4

PU/ PD

LVCMOS

sys_drm_

msecure

O

mmc3_dat6

hsusb1_dir

gpio_22

2

3

4

6

0

1

IO

I

IO

O

hsusb1_tll_dir

etk_d9

AG9

NA

L

4

VDDS

Yes

4

PU/ PD

LVCMOS

sys_secure_indic

ator

mmc3_dat5

hsusb1_nxt

gpio_23

2

3

4

5

6

IO

I

IO

O

mm1_rxdm

hsusb1_tll_nxt

28

TERMINAL DESCRIPTION

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OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

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SPRS599–JUNE 2009

Table 2-1. Ball Characteristics (CBB Pkg.) (continued)

BALL

BOTTOM [1]

BALL

TOP [2]

NAME [3]

MODE [4] TYPE [5]

BALL

RESET

STATE [6]

BALL

RESET

REL.

RESET

REL.

MODE [8]

POWER [9]

HYS

[10]

BUFFER

STRENGTH

(mA) [11]

PULL

U/D

TYPE

[12]

IO

CELL [13]

STATE [7]

AE7

NA

etk_d10

uart1_rx

0

2

3

4

6

0

3

4

5

6

0

3

4

6

0

3

4

5

6

0

3

4

5

6

0

3

4

5

6

O

I

L

4

VDDS

Yes

4

PU/ PD

LVCMOS

hsusb2_clk

gpio_24

O

IO

O

IO

I

hsusb2_tll_clk

etk_d11

AF7

NA

L

4

VDDS

4

PU/ PD

hsusb2_stp

gpio_25

mm2_rxdp

hsusb2_tll_stp

etk_d12

AG7

AH7

NA

O

I

L

4

VDDS

Yes

4

PU/ PD

LVCMOS

hsusb2_dir

gpio_26

IO

O

I

hsusb2_tll_dir

etk_d13

hsusb2_nxt

gpio_27

IO

O

IO

O

IO

mm2_rxdm

hsusb2_tll_nxt

etk_d14

AG8

AH8

NA

L

4

VDDS

Yes

4

PU/ PD

LVCMOS

hsusb2_ data0

gpio_28

mm2_rxrcv

hsusb2_tll_ data0

etk_d15

PU/ PD

hsusb2_ data1

gpio_29

mm2_txse0

hsusb2_tll_ data1

Submit Documentation Feedback

TERMINAL DESCRIPTION

29

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

SPRS599–JUNE 2009

www.ti.com

Table 2-2. Ball Characteristics (CBC Pkg.)

BALL

BOTTOM

[1]

BALL

TOP

[2]

NAME

[4]

MODE

[5]

TYPE

[6]

BALL

RESET

STATE

[7]

BALL

RESET

REL.

STATE

[8]

RESET

REL.

MODE

[9]

POWER

[10]

HYS

[11]

BUFFER PULLUP

IO

CELL

[14]

STRENG

TH

/DOWN

TYPE

[13]

(mA)

[12]

AE16

-

cam_d0

-

0

2

4

7

0

2

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

I

L

7

-

Yes

4

PU100/

PD100

LVDS/

CMOS

IDS

gpio_99

I

safe_mode

cam_d1

-

AE15

-

I

L

4

PU100/

PD100

LVDS/

CMOS

IDS

gpio_100

safe_mode

-

I

-

AD17

AE18

AD16

AE17

-

IDS

L

7

-

Yes

4

PU100/

PD100

LVDS/

CMOS

gpio_112

safe_mode

-

I

-

IDS

PU100/

PD100

LVDS/

CMOS

gpio_114

safe_mode

-

I

-

IDS

PU100/

PD100

LVDS/

CMOS

gpio_113

safe_mode

-

I

-

IDS

I

PU100/

PD100

LVDS/

CMOS

gpio_115

safe_mode

sdrc_a0

-

G20

K20

J20

O

0

H

0

1

0

7

vdds_io

No

Yes

4⁽¹⁾

NA

LVDS/

CMOS

sdrc_a1

sdrc_a2

sdrc_a3

sdrc_a4

sdrc_a5

sdrc_a6

sdrc_a7

sdrc_a8

sdrc_a9

sdrc_a10

sdrc_a11

sdrc_a12

sdrc_a13

sdrc_a14

sdrc_ba0

sdrc_ba1

0

O

LVDS/

CMOS

LVDS/

CMOS

J21

LVDS/

CMOS

U21

R20

M21

M20

N20

K21

Y16

N21

R21

AA15

Y12

AA18

V20

Y15

LVDS/

CMOS

LVDS/

CMOS

LVDS/

CMOS

LVDS/

CMOS

LVDS/

CMOS

LVDS/

CMOS

LVDS/

CMOS

LVDS/

CMOS

LVDS/

CMOS

LVDS/

CMOS

LVDS/

CMOS

LVDS/

CMOS

LVDS/

CMOS

sdrc_cke0

safe_mode

sdrc_cke1

safe_mode

0

7

0

7

PU100/

PD100

LVDS/

CMOS

-

Y13

O

H

1

7

vdds_io

Yes

4⁽¹⁾

PU100/

PD100

LVDS/

CMOS

(1) The drive strength is programmable vs the capacity load: load range = [2 pF to 6 pF] per default or [6 pF to 12 pF] according to the

selected mode.

30

TERMINAL DESCRIPTION

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OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

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SPRS599–JUNE 2009

Table 2-2. Ball Characteristics (CBC Pkg.) (continued)

BALL

BOTTOM

[1]

BALL

TOP

[2]

NAME

[4]

MODE

[5]

TYPE

[6]

BALL

RESET

STATE

[7]

BALL

RESET

REL.

STATE

[8]

RESET

REL.

MODE

[9]

POWER

[10]

HYS

[11]

BUFFER PULLUP

IO

CELL

[14]

STRENG

TH

/DOWN

TYPE

[13]

(mA)

[12]

-

A12

D1

sdrc_clk

sdrc_d0

0

IO

L

0

Z

0

vdds_io

Yes

4⁽¹⁾

PU100/

PD100

LVDS/

CMOS

PU100/

PD100

LVDS/

CMOS

G1

sdrc_d1

PU100/

PD100

LVDS/

CMOS

G2

sdrc_d2

PU100/

PD100

LVDS/

CMOS

E1

sdrc_d3

PU100/

PD100

LVDS/

CMOS

D2

sdrc_d4

PU100/

PD100

LVDS/

CMOS

E2

sdrc_d5

PU100/

PD100

LVDS/

CMOS

B3

sdrc_d6

PU100/

PD100

LVDS/

CMOS

B4

sdrc_d7

PU100/

PD100

LVDS/

CMOS

A10

B11

A11

B12

A16

A17

B17

B18

B7

sdrc_d8

PU100/

PD100

LVDS/

CMOS

sdrc_d9

PU100/

PD100

LVDS/

CMOS

sdrc_d10

sdrc_d11

sdrc_d12

sdrc_d13

sdrc_d14

sdrc_d15

sdrc_d16

sdrc_d17

sdrc_d18

sdrc_d19

sdrc_d20

sdrc_d21

sdrc_d22

sdrc_d23

sdrc_d24

sdrc_d25

sdrc_d26

sdrc_d27

sdrc_d28

sdrc_d29

sdrc_d30

PU100/

PD100

LVDS/

CMOS

PU100/

PD100

LVDS/

CMOS

PU100/

PD100

LVDS/

CMOS

PU100/

PD100

LVDS/

CMOS

PU100/

PD100

LVDS/

CMOS

PU100/

PD100

LVDS/

CMOS

PU100/

PD100

LVDS/

CMOS

A5

PU100/

PD100

LVDS/

CMOS

B6

PU100/

PD100

LVDS/

CMOS

A6

PU100/

PD100

LVDS/

CMOS

A8

PU100/

PD100

LVDS/

CMOS

B9

PU100/

PD100

LVDS/

CMOS

A9

PU100/

PD100

LVDS/

CMOS

B10

C21

D20

B19

C20

D21

E20

E21

PU100/

PD100

LVDS/

CMOS

PU100/

PD100

LVDS/

CMOS

PU100/

PD100

LVDS/

CMOS

PU100/

PD100

LVDS/

CMOS

PU100/

PD100

LVDS/

CMOS

PU100/

PD100

LVDS/

CMOS

PU100/

PD100

LVDS/

CMOS

PU100/

PD100

LVDS/

CMOS

Submit Documentation Feedback

TERMINAL DESCRIPTION

31

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

SPRS599–JUNE 2009

www.ti.com

Table 2-2. Ball Characteristics (CBC Pkg.) (continued)

BALL

BOTTOM

[1]

BALL

TOP

[2]

NAME

[4]

MODE

[5]

TYPE

[6]

BALL

RESET

STATE

[7]

BALL

RESET

REL.

STATE

[8]

RESET

REL.

MODE

[9]

POWER

[10]

HYS

[11]

BUFFER PULLUP

IO

CELL

[14]

STRENG

TH

/DOWN

TYPE

[13]

(mA)

[12]

-

G21

H1

sdrc_d31

sdrc_dm0

sdrc_dm1

sdrc_dm2

sdrc_dm3

sdrc_dqs0

sdrc_dqs1

sdrc_dqs2

sdrc_dqs3

sdrc_ncas

sdrc_nclk

sdrc_ncs0

sdrc_ncs1

sdrc_nras

sdrc_nwe

0

IO

O

L

0

L

1

L

Z

0

Z

1

L

0

7

vdds_io

-

Yes

No

4⁽¹⁾

4

PU100/

PD100

LVDS/

CMOS

-

NA

LVDS/

CMOS

-

A14

A4

O

No

LVDS/

CMOS

-

O

No

LVDS/

CMOS

-

A18

C2

O

No

LVDS/

CMOS

-

IO

O

Yes

No

PU100/

PD100

LVDS/

CMOS

-

B15

B8

PU100/

PD100

LVDS/

CMOS

-

PU100/

PD100

LVDS/

CMOS

-

A19

U20

B13

T21

T20

V21

Y18

-

PU100/

PD100

LVDS/

CMOS

-

NA

LVDS/

CMOS

-

O

No

LVDS/

CMOS

-

O

No

LVDS/

CMOS

-

O

No

LVDS/

CMOS

-

O

No

LVDS/

CMOS

O

No

LVDS/

CMOS

AE21

dss_data0

-

0

1

2

4

7

0

1

2

4

7

0

1

4

7

0

1

4

7

0

1

2

4

7

0

1

2

4

7

IO

ODS

I

No

PU100/

PD100

LVDS/

CMOS

uart1_cts

gpio_70

IO

-

safe_mode

dss_data1

-

AE22

-

IO

ODS

O

L

7

-

No

4

PU100/

PD100

LVDS/

CMOS

uart1_rts

gpio_71

safe_mode

dss_data2

-

IO

-

AE23

AE24

AD23

-

IO

ODS

IO

-

L

7

-

No

4

PU100/

PD100

LVDS/

CMOS

gpio_72

safe_mode

dss_data3

-

IO

ODS

IO

-

PU100/

PD100

LVDS/

CMOS

gpio_73

safe_mode

dss_data4

-

IO

ODS

I

PU100/

PD100

LVDS/

CMOS

uart3_rx_irrx

gpio_74

safe_mode

dss_data5

-

IO

-

AD24

-

IO

ODS

O

L

7

-

No

4

PU100/

PD100

LVDS/

CMOS

uart3_tx_irtx

gpio_75

safe_mode

IO

-

32

TERMINAL DESCRIPTION

Submit Documentation Feedback

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

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SPRS599–JUNE 2009

Table 2-2. Ball Characteristics (CBC Pkg.) (continued)

BALL

BOTTOM

[1]

BALL

TOP

[2]

NAME

[4]

MODE

[5]

TYPE

[6]

BALL

RESET

STATE

[7]

BALL

RESET

REL.

STATE

[8]

RESET

REL.

MODE

[9]

POWER

[10]

HYS

[11]

BUFFER PULLUP

IO

CELL

[14]

STRENG

TH

/DOWN

TYPE

[13]

(mA)

[12]

AC26

AD26

AA25

Y25

-

dss_data10

0

1

4

7

0

1

4

7

0

1

4

7

0

1

4

7

0

1

4

7

0

1

4

7

0

1

2

3

4

7

0

1

2

3

4

7

0

1

3

4

7

0

4

5

7

0

4

7

0

4

7

0

4

IO

ODS

IO

-

L

H

L

H

7

-

NA

Yes

4

PU100/

PD100

LVDS/

CMOS

-

gpio_80

safe_mode

dss_data11

-

IO

ODS

IO

-

PU100/

PD100

LVDS/

CMOS

gpio_81

safe_mode

dss_data12

-

IO

ODS

IO

-

PU100/

PD100

LVDS/

CMOS

gpio_82

safe_mode

dss_data13

-

IO

ODS

IO

-

PU100/

PD100

LVDS/

CMOS

gpio_83

safe_mode

dss_data14

-

AA26

AB26

F25

IO

ODS

IO

-

PU100/

PD100

LVDS/

CMOS

gpio_84

safe_mode

dss_data15

-

IO

ODS

IO

-

PU100/

PD100

LVDS/

CMOS

gpio_85

safe_mode

dss_data20

-

O

vdds_io

PU100/

PD100

LVCMOS

O

mcspi3_somi

dss_data2

gpio_90

safe_mode

dss_data22

-

IO

-

AC25

-

O

L

7

-

NA

4

PU100/

PD100

LVDS/

CMOS

ODS

O

mcspi3_cs1

dss_data4

gpio_92

safe_mode

dss_data23

-

IO

-

AB25

-

O

L

7

-

NA

4

PU100/

PD100

LVDS/

CMOS

ODS

IO

-

dss_data5

gpio_93

safe_mode

dss_pclk

gpio_66

hw_dbg12

safe_mode

gpmc_a1

gpio_34

safe_mode

gpmc_a2

gpio_35

safe_mode

gpmc_a3

gpio_36

G25

O

H

vdds_io

Yes

PU100/

PD100

LVCMOS

IO

O

-

J2

H1

H2

-

O

L

7

vdds_io

Yes

4⁽¹⁾

PU100/

PD100

LVCMOS

IO

-

O

PU100/

PD100

IO

-

O

PU100/

PD100

IO

Submit Documentation Feedback

TERMINAL DESCRIPTION

33

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

SPRS599–JUNE 2009

www.ti.com

Table 2-2. Ball Characteristics (CBC Pkg.) (continued)

BALL

BOTTOM

[1]

BALL

TOP

[2]

NAME

[4]

MODE

[5]

TYPE

[6]

BALL

RESET

STATE

[7]

BALL

RESET

REL.

STATE

[8]

RESET

REL.

MODE

[9]

POWER

[10]

HYS

[11]

BUFFER PULLUP

IO

CELL

[14]

STRENG

TH

/DOWN

TYPE

[13]

(mA)

[12]

safe_mode

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

1

4

7

0

1

4

7

0

4

7

0

-

O

IO

-

G2

F1

F2

E1

E2

D1

-

gpmc_a4

gpio_37

L

7

vdds_io

Yes

4⁽¹⁾

PU100/

PD100

LVCMOS

safe_mode

gpmc_a5

gpio_38

O

IO

-

PU100/

PD100

safe_mode

gpmc_a6

gpio_39

O

IO

-

H

PU100/

PD100

safe_mode

gpmc_a7

gpio_40

O

IO

-

PU100/

PD100

safe_mode

gpmc_a8

gpio_41

O

IO

-

PU100/

PD100

safe_mode

gpmc_a9

sys_ndmareq2

gpio_42

O

I

PU100/

PD100

IO

-

safe_mode

gpmc_a10

sys_ndmareq3

gpio_43

D2

N1

-

O

I

H

L

H

0

7

0

vdds_io

Yes

4⁽¹⁾

PU100/

PD100

LVCMOS

IO

-

safe_mode

gpmc_clk

gpio_59

L1

O

IO

-

4⁽¹⁾

PU100/

PD100

safe_mode

gpmc_d0

AA2

AA1

AC2

AC1

AE5

AD6

AD5

AC5

V1

U2

U1

IO

H

0

vdds_io

Yes

4⁽¹⁾

PU100/

PD100

LVCMOS

gpmc_d1

gpmc_d2

gpmc_d3

gpmc_d4

gpmc_d5

gpmc_d6

gpmc_d7

0

IO

PU100/

PD100

V2

PU100/

PD100

V1

PU100/

PD100

AA3

AA4

Y3

PU100/

PD100

PU100/

PD100

PU100/

PD100

Y4

PU100/

PD100

R1

gpmc_d8

gpio_44

0

4

7

0

4

7

0

4

7

0

4

7

IO

-

PU100/

PD100

safe_mode

gpmc_d9

gpio_45

Y1

T1

U2

T1

N1

P2

IO

-

H

0

vdds_io

Yes

4⁽¹⁾

PU100/

PD100

LVCMOS

safe_mode

gpmc_d10

gpio_46

IO

-

PU100/

PD100

safe_mode

gpmc_d11

gpio_47

IO

-

PU100/

PD100

safe_mode

34

TERMINAL DESCRIPTION

Submit Documentation Feedback

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

www.ti.com

SPRS599–JUNE 2009

Table 2-2. Ball Characteristics (CBC Pkg.) (continued)

BALL

BOTTOM

[1]

BALL

TOP

[2]

NAME

[4]

MODE

[5]

TYPE

[6]

BALL

RESET

STATE

[7]

BALL

RESET

REL.

STATE

[8]

RESET

REL.

MODE

[9]

POWER

[10]

HYS

[11]

BUFFER PULLUP

IO

CELL

[14]

STRENG

TH

/DOWN

TYPE

[13]

(mA)

[12]

U1

P1

L2

P1

M1

J2

gpmc_d12

gpio_48

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

1

4

7

0

1

2

3

4

7

0

1

2

3

4

7

0

1

2

3

4

7

0

1

2

3

4

IO

-

H

0

vdds_io

Yes

4⁽¹⁾

PU100/

PD100

LVCMOS

safe_mode

gpmc_d13

gpio_49

IO

-

PU100/

PD100

safe_mode

gpmc_d14

gpio_50

IO

-

PU100/

PD100

safe_mode

gpmc_d15

gpio_51

M2

K2

IO

-

PU100/

PD100

safe_mode

gpmc_nadv_ale

gpmc_nbe0_cle

gpio_60

AD10

K2

AA9

-

O

IO

-

0

L

0

vdds_io

No

4⁽¹⁾

NA

LVCMOS

Yes

PU100/

PD100

safe_mode

gpmc_nbe1

gpio_61

J1

-

O

IO

-

L

7

vdds_io

Yes

4⁽¹⁾

PU100/

PD100

LVCMOS

safe_mode

gpmc_ncs0

gpmc_ncs1

gpio_52

AD8

AD1

AA8

W1

O

IO

-

1

0

vdds_io

No

4⁽¹⁾

NA

LVCMOS

H

Yes

PU100/

PD100

safe_mode

gpmc_ncs2

gpio_53

A3

B6

-

O

IO

-

H

7

vdds_io

Yes

4⁽¹⁾

PU100/

PD100

LVCMOS

safe_mode

gpmc_ncs3

sys_ndmareq0

gpio_54

O

I

4⁽¹⁾

PU100/

PD100

IO

-

safe_mode

gpmc_ncs4

sys_ndmareq1

mcbsp4_clkx

gpt9_pwm_evt

gpio_55

B4

C4

B5

C5

-

O

I

H

7

vdds_io

Yes

4⁽¹⁾

PU100/

PD100

LVCMOS

IO

-

safe_mode

gpmc_ncs5

sys_ndmareq2

mcbsp4_dr

gpt10_pwm_evt

gpio_56

O

I

PU100/

PD100

I

IO

-

safe_mode

gpmc_ncs6

sys_ndmareq3

mcbsp4_dx

gpt11_pwm_evt

gpio_57

O

I

PU100/

PD100

IO

-

safe_mode

gpmc_ncs7

gpmc_io_dir

mcbsp4_fsx

gpt8_pwm_evt

gpio_58

O

IO

PU100/

PD100

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TERMINAL DESCRIPTION

35

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

SPRS599–JUNE 2009

www.ti.com

Table 2-2. Ball Characteristics (CBC Pkg.) (continued)

BALL

BOTTOM

[1]

BALL

TOP

[2]

NAME

[4]

MODE

[5]

TYPE

[6]

BALL

RESET

STATE

[7]

BALL

RESET

REL.

STATE

[8]

RESET

REL.

MODE

[9]

POWER

[10]

HYS

[11]

BUFFER PULLUP

IO

CELL

[14]

STRENG

TH

/DOWN

TYPE

[13]

(mA)

[12]

safe_mode

7

0

4

7

0

-

O

IO

-

N2

M1

L2

K1

Y5

gpmc_noe

gpmc_nwe

gpmc_nwp

gpio_62

1

L

1

0

vdds_io

No

4⁽¹⁾

NA

LVCMOS

AC6

Yes

PU100/

PD100

safe_mode

gpmc_wait0

AC11

AC8

Y10

Y8

I

H

0

7

vdds_io

Yes

4⁽¹⁾

PU100/

PD100

LVCMOS

gpmc_wait1

gpio_63

0

4

7

0

4

7

0

1

4

7

0

4

7

0

2

4

7

0

2

4

7

0

2

4

7

0

2

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

I

IO

-

PU100/

PD100

safe_mode

gpmc_wait2

gpio_64

B3

C6

-

I

H

7

vdds_io

Yes

4⁽¹⁾

PU100/

PD100

LVCMOS

IO

-

safe_mode

gpmc_wait3

sys_ndmareq1

gpio_65

I

4⁽¹⁾

PU100/

PD100

I

IO

-

safe_mode

hsusb0_clk

gpio_120

W19

V20

-

I

L

7

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

IO

-

safe_mode

hsusb0_data0

uart3_tx_irtx

gpio_125

IO

O

IO

-

4⁽²⁾

PU100/

PD100

safe_mode

hsusb0_data1

uart3_rx_irrx

gpio_130

Y20

V18

W20

-

IO

I

L

7

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

IO

-

safe_mode

hsusb0_data2

uart3_rts_sd

gpio_131

IO

O

IO

-

PU100/

PD100

safe_mode

hsusb0_data3

uart3_cts_rctx

gpio_169

IO

-

PU100/

PD100

safe_mode

hsusb0_data4

gpio_188

W17

Y18

Y19

Y17

V19

-

IO

-

L

7

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

safe_mode

hsusb0_data5

gpio_189

IO

-

PU100/

PD100

safe_mode

hsusb0_data6

gpio_190

IO

-

PU100/

PD100

safe_mode

hsusb0_data7

gpio_191

IO

-

PU100/

PD100

safe_mode

hsusb0_dir

gpio_122

I

PU100/

PD100

IO

-

safe_mode

(2) The capacity load range is [2 pf to 6 pF].

36 TERMINAL DESCRIPTION

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OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

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SPRS599–JUNE 2009

Table 2-2. Ball Characteristics (CBC Pkg.) (continued)

BALL

BOTTOM

[1]

BALL

TOP

[2]

NAME

[4]

MODE

[5]

TYPE

[6]

BALL

RESET

STATE

[7]

BALL

RESET

REL.

STATE

[8]

RESET

REL.

MODE

[9]

POWER

[10]

HYS

[11]

BUFFER PULLUP

IO

CELL

[14]

STRENG

TH

/DOWN

TYPE

[13]

(mA)

[12]

W18

U20

-

hsusb0_nxt

0

4

7

0

4

7

0

I

IO

-

L

7

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

gpio_124

safe_mode

hsusb0_stp

gpio_121

O

IO

-

H

7

4⁽²⁾

PU100/

PD100

safe_mode

jtag_ntrst

U15

W13

V14

U16

Y13

V15

N19

-

I

L

0

7

vdds_io

Yes

NA

4

PU100/

PD100

LVCMOS

jtag_rtck

jtag_tck

0

O

I

PU100/

PD100

L

vdds_io

NA

N A

4

PU100/

PD100

jtag_tdi

I

H

L

H

Z

H

L

vdds_io

PU100/

PD100

jtag_tdo

O

IO

vdds_io

PU100/

PD100

jtag_tms_tmsc

H

L

vdds_io

4

PU100/

PD100

mmc1_clk

-

0

1

4

7

0

1

4

7

0

1

4

7

0

1

4

7

0

1

4

7

0

1

4

7

0

2

4

7

0

2

4

7

0

2

4

7

O

IO

-

vdds_mmc1

8

PU100/

PD100

gpio_120

safe_mode

mmc1_cmd

-

L18

M19

M18

K18

N20

M20

P17

P18

-

IO

O

IO

-

L

7

vdds_mmc1

vdds_mmc1a

Yes

No

8

PU100/

PD100

LVCMOS

gpio_121

safe_mode

mmc1_dat0

-

IO

-

PU100/

PD100

gpio_122

safe_mode

mmc1_dat1

-

IO

-

PU100/

PD100

gpio_123

safe_mode

mmc1_dat2

-

IO

-

PU100/

PD100

gpio_124

safe_mode

mmc1_dat3

-

IO

-

PU100/

PD100

gpio_125

safe_mode

mmc1_dat4

-

IO

-

PU/PD⁽³⁾

gpio_126

safe_mode

mmc1_dat5

-

IO

O

IO

-

No

gpio_127

safe_mode

mmc1_dat6

-

IO

O

IO

-

No

gpio_128

safe_mode

(3) The PU nominal drive strength of this IO cell is equal to 25 µA @ 1.8 V and 41.6 µA @ 3.0 V.

The PD nominal drive strength of this IO cell is equal to 1 mA @ 1.8 V and 1.66 mA @ 3.0 V.

Submit Documentation Feedback

TERMINAL DESCRIPTION

37

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

SPRS599–JUNE 2009

www.ti.com

Table 2-2. Ball Characteristics (CBC Pkg.) (continued)

BALL

BOTTOM

[1]

BALL

TOP

[2]

NAME

[4]

MODE

[5]

TYPE

[6]

BALL

RESET

STATE

[7]

BALL

RESET

REL.

STATE

[8]

RESET

REL.

MODE

[9]

POWER

[10]

HYS

[11]

BUFFER PULLUP

IO

CELL

[14]

STRENG

TH

/DOWN

TYPE

[13]

(mA)

[12]

P19

-

mmc1_dat7

0

2

4

7

0

IO

O

L

7

vdds_mmc1a

No

8

PU/PD⁽³⁾

LVCMOS

-

gpio_129

safe_mode

i2c1_scl

IO

-

J25

J24

C2

-

IOD

H

0

7

vdds_io

Yes

3

PU100/

PD100

Open Drain

i2c1_sda

0

IOD

PU100/

PD100

i2c2_scl

0

4

7

0

4

7

0

4

7

0

4

7

0

1

2

4

7

0

2

4

7

0

1

2

4

7

0

1

2

4

7

0

1

2

4

7

0

1

2

4

7

0

4

7

IOD

IO

-

3

4

PU100/

PD100

LVCMOS

Open Drain

gpio_168

safe_mode

i2c2_sda

4

C1

-

IOD

IO

-

H

L

H

L

7

vdds_io

Yes

3

PU100/

PD100

LVCMOS

Open Drain

gpio_183

4

safe_mode

i2c3_scl

4

AB4

AC4

U19

IOD

IO

-

3

PU100/

PD100

LVCMOS

Open Drain

gpio_184

4

safe_mode

i2c3_sda

4

IOD

IO

-

3

PU100/

PD100

LVCMOS

Open Drain

gpio_185

4

safe_mode

mcbsp1_clkr

mcspi4_clk

-

4

IO

I

4⁽²⁾

PU100/

PD100

LVCMOS

gpio_156

IO

-

safe_mode

mcbsp1_clkx

mcbsp3_clkx

gpio_162

T17

T20

-

IO

-

L

7

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

safe_mode

mcbsp1_dr

mcspi4_somi

mcbsp3_dr

gpio_159

I

4⁽²⁾

PU100/

PD100

IO

I

IO

-

safe_mode

mcbsp1_dx

mcspi4_simo

mcbsp3_dx

gpio_158

U17

V17

P20

R18

-

IO

-

L

7

vdds_io

Yes

4⁽²⁾

4⁽⁴⁾

PU100/

PD100

LVCMOS

safe_mode

mcbsp1_fsr

-

IO

I

PU100/

PD100

cam_global_reset

gpio_157

IO

-

safe_mode

mcbsp1_fsx

mcspi4_cs0

mcbsp3_fsx

gpio_161

IO

-

PU100/

PD100

safe_mode

mcbsp2_clkx

gpio_117

IO

-

PU100/

PD100

safe_mode

(4) The buffer strength of this IO cell is programmable (2, 4, 6, or 8 mA) according to the selected mode; the default value is described in

the above table.

38

TERMINAL DESCRIPTION

Submit Documentation Feedback

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

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SPRS599–JUNE 2009

Table 2-2. Ball Characteristics (CBC Pkg.) (continued)

BALL

BOTTOM

[1]

BALL

TOP

[2]

NAME

[4]

MODE

[5]

TYPE

[6]

BALL

RESET

STATE

[7]

BALL

RESET

REL.

STATE

[8]

RESET

REL.

MODE

[9]

POWER

[10]

HYS

[11]

BUFFER PULLUP

IO

CELL

[14]

STRENG

TH

/DOWN

TYPE

[13]

(mA)

[12]

T18

R19

U18

P9

-

mcbsp2_dr

0

4

7

0

4

7

0

4

7

0

1

4

7

0

1

4

7

0

3

4

7

0

1

4

7

0

1

4

7

0

2

3

4

7

0

1

2

3

4

7

0

1

2

3

4

7

0

1

2

3

4

7

I

L

7

vdds_io

Yes

4⁽⁴⁾

PU100/

PD100

LVCMOS

gpio_118

IO

-

safe_mode

mcbsp2_dx

gpio_119

IO

-

PU100/

PD100

safe_mode

mcbsp2_fsx

gpio_116

IO

-

PU100/

PD100

safe_mode

mcspi1_clk

mmc2_dat4

gpio_171

IO

-

PU100/

PD100

safe_mode

mcspi1_cs0

mmc2_dat7

gpio_174

R7

R9

P8

P7

W7

-

IO

-

H

L

H

L

7

vdds_io

Yes

4⁽⁴⁾

4⁽²⁾

PU100/

PD100

LVCMOS

safe_mode

mcspi1_cs2

mmc3_clk

O

IO

-

PU100/

PD100

gpio_176

safe_mode

mcspi1_simo

mmc2_dat5

gpio_172

IO

-

PU100/

PD100

safe_mode

mcspi1_somi

mmc2_dat6

gpio_173

IO

-

L

PU100/

PD100

safe_mode

mcspi2_clk

hsusb2_tll_data7

hsusb2_data7

gpio_178

IO

O

IO

-

L

PU100/

PD100

safe_mode

mcspi2_cs0

gpt11_pwm_evt

hsusb2_tll_data6

hsusb2_data6

gpio_181

V8

W8

U8

-

IO

O

IO

-

H

L

H

L

7

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

safe_mode

mcspi2_simo

gpt9_pwm_evt

hsusb2_tll_data4

hsusb2_data4

gpio_179

IO

I

PU100/

PD100

IO

-

safe_mode

mcspi2_somi

gpt10_pwm_evt

hsusb2_tll_data5

hsusb2_data5

gpio_180

IO

O

IO

-

PU100/

PD100

safe_mode

Submit Documentation Feedback

TERMINAL DESCRIPTION

39

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

SPRS599–JUNE 2009

www.ti.com

Table 2-2. Ball Characteristics (CBC Pkg.) (continued)

BALL

BOTTOM

[1]

BALL

TOP

[2]

NAME

[4]

MODE

[5]

TYPE

[6]

BALL

RESET

STATE

[7]

BALL

RESET

REL.

STATE

[8]

RESET

REL.

MODE

[9]

POWER

[10]

HYS

[11]

BUFFER PULLUP

IO

CELL

[14]

STRENG

TH

/DOWN

TYPE

[13]

(mA)

[12]

W10

R10

T10

-

mmc2_clk

0

1

4

7

0

1

4

7

0

1

4

7

0

4

7

0

1

4

7

0

1

4

7

0

1

3

4

7

0

1

4

7

0

2

3

4

7

0

1

4

7

0

1

2

4

7

0

1

2

4

7

0

1

O

IO

-

L

H

L

H

7

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

mcspi3_clk

gpio_130

safe_mode

mmc2_cmd

mcspi3_simo

gpio_131

IO

-

PU100/

PD100

safe_mode

mmc2_dat0

mcspi3_somi

gpio_132

IO

-

PU100/

PD100

safe_mode

mmc2_dat1

gpio_133

T9

-

IO

-

H

7

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

safe_mode

mmc2_dat2

mcspi3_cs1

gpio_134

U10

IO

O

IO

-

4⁽²⁾

PU100/

PD100

safe_mode

mmc2_dat3

mcspi3_cs0

gpio_135

U9

-

IO

-

H

L

H

L

7

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

safe_mode

mmc2_dat4

mmc2_dir_dat0

mmc3_dat0

gpio_136

V10

IO

O

IO

-

4⁽²⁾

PU100/

PD100

safe_mode

uart1_rts

R2

H3

-

O

IO

-

L

7

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

-

gpio_149

safe_mode

uart1_rx

I

4⁽²⁾

PU100/

PD100

mcbsp1_clkr

mcspi4_clk

gpio_151

IO

-

safe_mode

uart1_tx

L4

-

O

IO

-

L

7

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

-

gpio_148

safe_mode

uart2_cts

Y24

I

H

4

PU100/

PD100

mcbsp3_dx

gpt9_pwm_evt

gpio_144

IO

-

safe_mode

uart2_rts

AA24

AD21

-

O

I

H

7

vdds_io

Yes

4

PU100/

PD100

LVCMOS

mcbsp3_dr

gpt10_pwm_evt

gpio_145

IO

-

safe_mode

uart2_rx

I

PU100/

PD100

mcbsp3_fsx

IO

40

TERMINAL DESCRIPTION

Submit Documentation Feedback

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

www.ti.com

SPRS599–JUNE 2009

Table 2-2. Ball Characteristics (CBC Pkg.) (continued)

BALL

BOTTOM

[1]

BALL

TOP

[2]

NAME

[4]

MODE

[5]

TYPE

[6]

BALL

RESET

STATE

[7]

BALL

RESET

REL.

STATE

[8]

RESET

REL.

MODE

[9]

POWER

[10]

HYS

[11]

BUFFER PULLUP

IO

CELL

[14]

STRENG

TH

/DOWN

TYPE

[13]

(mA)

[12]

gpt8_pwm_evt

2

4

7

0

1

2

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

1

2

3

4

7

0

1

7

0

1

7

0

4

7

0

4

7

0

4

7

0

4

7

0

1

4

7

0

1

4

7

IO

-

gpio_147

safe_mode

uart2_tx

AD22

-

O

IO

-

H

7

vdds_io

Yes

4

PU100/

PD100

LVCMOS

mcbsp3_clkx

gpt11_pwm_evt

gpio_146

safe_mode

uart3_cts_rctx

gpio_163

F23

F24

H24

G24

J23

-

IO

-

H

7

vdds_io

Yes

4

PU100/

PD100

LVCMOS

safe_mode

uart3_rts_sd

gpio_164

O

IO

-

PU100/

PD100

safe_mode

uart3_rx_irrx

gpio_165

I

PU100/

PD100

IO

-

safe_mode

uart3_tx_irtx

gpio_166

O

IO

-

PU100/

PD100

safe_mode

hdq_sio

IOD

I

PU100/

PD100

LVCMOS

Open Drain

sys_altclk

i2c2_sccbe

i2c3_sccbe

gpio_170

O

IO

-

safe_mode

i2c4_scl

AD15

W16

F3

-

IOD

O

-

H

Z

H

Z

0

vdds_io

Yes

3

4

3

4

PU100/

PD100

LVCMOS

Open Drain

sys_nvmode1

safe_mode

i2c4_sda

IOD

O

-

PU100/

PD100

LVCMOS

Open Drain

sys_nvmode2

safe_mode

sys_boot0

gpio_2

I

PU100/

PD100

LVCMOS

IO

-

safe_mode

sys_boot1

gpio_3

D3

I

4

PU100/

PD100

IO

-

safe_mode

sys_boot2

gpio_4

C3

I

PU100/

PD100

IO

-

safe_mode

sys_boot3

gpio_5

E3

I

PU100/

PD100

IO

-

safe_mode

sys_boot4

mmc2_dir_dat2

gpio_6

E4

I

PU100/

PD100

O

IO

-

safe_mode

sys_boot5

mmc2_dir_dat3

gpio_7

G3

-

I

Z

0

vdds_io

Yes

4

PU100/

PD100

LVCMOS

O

IO

-

safe_mode

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TERMINAL DESCRIPTION

41

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

SPRS599–JUNE 2009

www.ti.com

Table 2-2. Ball Characteristics (CBC Pkg.) (continued)

BALL

BOTTOM

[1]

BALL

TOP

[2]

NAME

[4]

MODE

[5]

TYPE

[6]

BALL

RESET

STATE

[7]

BALL

RESET

REL.

STATE

[8]

RESET

REL.

MODE

[9]

POWER

[10]

HYS

[11]

BUFFER PULLUP

IO

CELL

[14]

STRENG

TH

/DOWN

TYPE

[13]

(mA)

[12]

D4

AE14

W11

W15

V16

-

sys_boot6

gpio_8

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

1

4

5

7

0

1

4

5

7

0

1

4

5

7

0

1

4

5

7

I

IO

-

Z

0

7

0

7

vdds_io

Yes

4

PU100/

PD100

LVCMOS

safe_mode

sys_clkout1

gpio_10

O

IO

-

L

4

PU100/

PD100

safe_mode

sys_clkout2

gpio_186

safe_mode

sys_clkreq

gpio_1

O

IO

-

L

4⁽²⁾

PU100/

PD100

IO

-

0

1

4

PU100/

PD100

safe_mode

sys_nirq

gpio_0

I

H

4

PU100/

PD100

IO

-

safe_mode

sys_nrespwron

sys_nreswarm

gpio_30

V13

AD7

-

I

Z

0

I

NA

0

vdds_io

Yes

NA

4

NA

AA5

IOD

IO

-

1 (PU)

PU100/

PD100

LVCMOS

Open Drain

safe_mode

sys_off_mode

gpio_9

V12

-

O

IO

-

0

L

7

vdds_io

Yes

4

PU100/

PD100

LVCMOS

safe_mode

sys_xtalin

sys_xtalout

sys_ipmcsws

sys_opmcsws

tv_out1

AF19

AF20

B1

-

I

Z

0

Z

L

I

NA

0

vdds_io

Yes

No

NA

8

NA

LVCMOS

Analog

O

AI

AO

O

I

O

NA

0

vdds_io

A2

vdds_io

No

Analog

W26

V26

W25

U24

V23

AE20

A24

vdda_dac

vdds_io

No

10-bit DAC

LVCMOS

tv_out2

0

No

8

tv_vfb1

NA

I

0

No

2

tv_vfb2

0

No

2

tv_vref

0

No

NA

4⁽²⁾

sys_32k

I

NA

7

Yes

cam_d2

I

L

vdds_io

PU100/

PD100

-

I

gpio_101

hw_dbg4

safe_mode

cam_d3

IO

O

-

B24

D24

C24

-

I

L

7

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

-

I

gpio_102

hw_dbg5

safe_mode

cam_d4

IO

O

-

I

PU100/

PD100

-

I

gpio_103

hw_dbg6

safe_mode

cam_d5

IO

O

-

I

PU100/

PD100

-

O

IO

O

-

gpio_104

hw_dbg7

safe_mode

42

TERMINAL DESCRIPTION

Submit Documentation Feedback

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

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SPRS599–JUNE 2009

Table 2-2. Ball Characteristics (CBC Pkg.) (continued)

BALL

BOTTOM

[1]

BALL

TOP

[2]

NAME

[4]

MODE

[5]

TYPE

[6]

BALL

RESET

STATE

[7]

BALL

RESET

REL.

STATE

[8]

RESET

REL.

MODE

[9]

POWER

[10]

HYS

[11]

BUFFER PULLUP

IO

CELL

[14]

STRENG

TH

/DOWN

TYPE

[13]

(mA)

[12]

D25

-

cam_d10

-

0

1

4

5

7

0

4

5

7

0

2

4

5

7

0

1

4

5

7

0

4

5

7

0

4

5

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

1

4

5

7

I

O

IO

O

-

L

7

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

gpio_109

hw_dbg8

safe_mode

cam_d11

gpio_110

hw_dbg9

safe_mode

cam_fld

E26

B23

-

I

L

7

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

IO

O

-

IO

O

-

4⁽²⁾

PU100/

PD100

cam_global_reset

gpio_98

hw_dbg3

safe_mode

cam_hs

C23

-

IO

O

IO

O

-

L

7

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

-

gpio_94

hw_dbg0

safe_mode

cam_pclk

gpio_97

C26

D26

-

I

L

7

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

IO

O

-

hw_dbg2

safe_mode

cam_strobe

gpio_126

hw_dbg11

safe_mode

cam_xclka

gpio_96

O

IO

O

-

4⁽²⁾

PU100/

PD100

C25

E25

P25

P26

N25

N26

D23

-

O

IO

-

L

7

vdds_io

Yes

NA

4⁽²⁾

4

PU100/

PD100

LVCMOS

SubLVDS

LVCMOS

safe_mode

cam_xclkb

gpio_111

safe_mode

cam_d6

O

IO

-

PU100/

PD100

I

vdds_csib

vdds_io

PU100/

PD100

gpio_105

safe_mode

cam_d7

IO

-

I

NA

4

PU100/

PD100

gpio_106

safe_mode

cam_d8

IO

-

I

NA

4

PU100/

PD100

gpio_107

safe_mode

cam_d9

IO

-

I

NA

4

PU100/

PD100

gpio_108

safe_mode

cam_vs

IO

-

IO

O

IO

O

-

Yes

4⁽²⁾

PU100/

PD100

-

gpio_95

hw_dbg1

safe_mode

Submit Documentation Feedback

TERMINAL DESCRIPTION

43

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

SPRS599–JUNE 2009

www.ti.com

Table 2-2. Ball Characteristics (CBC Pkg.) (continued)

BALL

BOTTOM

[1]

BALL

TOP

[2]

NAME

[4]

MODE

[5]

TYPE

[6]

BALL

RESET

STATE

[7]

BALL

RESET

REL.

STATE

[8]

RESET

REL.

MODE

[9]

POWER

[10]

HYS

[11]

BUFFER PULLUP

IO

CELL

[14]

STRENG

TH

/DOWN

TYPE

[13]

(mA)

[12]

A23

-

cam_wen

0

2

4

5

7

0

4

7

0

2

4

5

7

0

2

4

5

7

0

4

5

7

0

4

5

7

0

4

7

0

4

7

0

1

2

3

4

7

0

1

2

3

4

7

0

1

2

3

4

7

I

L

7

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

cam_shutter

gpio_167

hw_dbg10

safe_mode

dss_acbias

gpio_69

O

IO

O

-

F26

G26

-

O

IO

-

L

7

vdds_io

Yes

8

PU100/

PD100

LVCMOS

safe_mode

dss_data6

uart1_tx

IO

O

IO

O

-

PU100/

PD100

gpio_76

hw_dbg14

safe_mode

dss_data7

uart1_rx

H25

-

IO

I

L

7

vdds_io

Yes

8

PU100/

PD100

LVCMOS

gpio_77

IO

O

-

hw_dbg15

safe_mode

dss_data8

gpio_78

H26

J26

-

IO

O

-

L

7

vdds_io

Yes

8

PU100/

PD100

LVCMOS

hw_dbg16

safe_mode

dss_data9

gpio_79

IO

O

-

PU100/

PD100

hw_dbg17

safe_mode

dss_data16

gpio_86

L25

L26

M24

-

IO

-

L

7

vdds_io

Yes

8

PU100/

PD100

LVCMOS

safe_mode

dss_data17

gpio_87

IO

-

PU100/

PD100

safe_mode

dss_data18

-

IO

O

IO

-

PU100/

PD100

mcspi3_clk

dss_data0

gpio_88

safe_mode

dss_data19

-

M26

-

IO

O

IO

-

L

7

vdds_io

Yes

8

PU100/

PD100

LVCMOS

mcspi3_simo

dss_data1

gpio_89

safe_mode

dss_data21

-

N24

-

O

IO

-

L

7

vdds_io

Yes

8

PU100/

PD100

LVCMOS

mcspi3_cs0

dss_data3

gpio_91

safe_mode

44

TERMINAL DESCRIPTION

Submit Documentation Feedback

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

www.ti.com

SPRS599–JUNE 2009

Table 2-2. Ball Characteristics (CBC Pkg.) (continued)

BALL

BOTTOM

[1]

BALL

TOP

[2]

NAME

[4]

MODE

[5]

TYPE

[6]

BALL

RESET

STATE

[7]

BALL

RESET

REL.

STATE

[8]

RESET

REL.

MODE

[9]

POWER

[10]

HYS

[11]

BUFFER PULLUP

IO

CELL

[14]

STRENG

TH

/DOWN

TYPE

[13]

(mA)

[12]

K24

-

dss_hsync

0

4

5

7

0

4

7

0

O

IO

O

-

H

7

vdds_io

Yes

4

PU100/

PD100

LVCMOS

gpio_67

hw_dbg13

safe_mode

dss_vsync

gpio_68

M25

R8

-

O

IO

-

H

7

vdds_io

Yes

4

PU100/

PD100

LVCMOS

safe_mode

mcspi1_cs1

O

4⁽⁴⁾

PU100/

PD100

-

1

3

4

7

0

2

3

4

5

7

0

1

2

3

4

5

7

0

2

4

5

7

0

1

2

3

4

5

6

7

0

2

3

4

6

7

0

1

2

3

4

5

6

7

I

mmc3_cmd

gpio_175

IO

-

safe_mode

mcspi1_cs3

hsusb2_tll_data2

hsusb2_data2

gpio_177

T8

-

O

IO

-

H

7

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

mm2_txdat

safe_mode

mcspi2_cs1

gpt8_pwm_evt

hsusb2_tll_data3

hsusb2_data3

gpio_182

V9

-

O

IO

-

L

7

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

mm2_txen_n

safe_mode

mcbsp_clks

cam_shutter

gpio_160

T19

AB2

-

I

L

7

4

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

O

IO

I

uart1_cts

safe_mode

etk_clk

-

O

IO

O

IO

I

H

4⁽²⁾

PU100/

PD100

mcbsp5_clkx

mmc3_clk

hsusb1_stp

gpio_12

mm1_rxdp

hsusb1_tll_stp

hw_dbg0

O

IO

O

IO

O

IO

O

AB3

-

etk_ctl

H

4

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

mmc3_cmd

hsusb1_clk

gpio_13

hsusb1_tll_clk

hw_dbg1

AC3

-

etk_d0

H

4

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

mcspi3_simo

mmc3_dat4

hsusb1_data0

gpio_14

mm1_rxrcv

hsusb1_tll_data0

hw_dbg2

Submit Documentation Feedback

TERMINAL DESCRIPTION

45

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

SPRS599–JUNE 2009

www.ti.com

Table 2-2. Ball Characteristics (CBC Pkg.) (continued)

BALL

BOTTOM

[1]

BALL

TOP

[2]

NAME

[4]

MODE

[5]

TYPE

[6]

BALL

RESET

STATE

[7]

BALL

RESET

REL.

STATE

[8]

RESET

REL.

MODE

[9]

POWER

[10]

HYS

[11]

BUFFER PULLUP

IO

CELL

[14]

STRENG

TH

/DOWN

TYPE

[13]

(mA)

[12]

AD4

AD3

AA3

Y3

-

etk_d1

0

1

3

4

5

6

7

0

1

3

4

5

6

7

0

1

2

3

4

6

7

0

1

2

3

4

6

7

0

1

2

3

4

6

7

0

1

2

3

4

6

7

0

1

2

3

4

5

6

7

0

1

2

O

IO

O

H

L

H

L

4

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

mcspi3_somi

hsusb1_data1

gpio_15

mm1_txse0

hsusb1_tll_data1

hw_dbg3

etk_d2

O

PU100/

PD100

mcspi3_cs0

hsusb1_data2

gpio_16

IO

O

mm1_txdat

hsusb1_tll_data2

hw_dbg4

etk_d3

O

PU100/

PD100

mcspi3_clk

mmc3_dat3

hsusb1_data7

gpio_17

IO

O

hsusb1_tll_data7

hw_dbg5

etk_d4

O

PU100/

PD100

mcbsp5_dr

mmc3_dat0

hsusb1_data4

gpio_18

I

IO

O

hsusb1_tll_data4

hw_dbg6

AB1

AE3

AD2

etk_d5

O

L

PU100/

PD100

mcbsp5_fsx

mmc3_dat1

hsusb1_data5

gpio_19

IO

O

hsusb1_tll_data5

hw_dbg7

etk_d6

O

L

PU100/

PD100

mcbsp5_dx

mmc3_dat2

hsusb1_data6

gpio_20

IO

O

hsusb1_tll_data6

hw_dbg8

etk_d7

O

L

PU100/

PD100

mcspi3_cs1

mmc3_dat7

hsusb1_data3

gpio_21

O

IO

O

mm1_txen_n

hsusb1_tll_data3

hw_dbg9

AA4

-

etk_d8

O

L

4

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

sys_drm_msecure

mmc3_dat6

O

IO

46

TERMINAL DESCRIPTION

Submit Documentation Feedback

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

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SPRS599–JUNE 2009

Table 2-2. Ball Characteristics (CBC Pkg.) (continued)

BALL

BOTTOM

[1]

BALL

TOP

[2]

NAME

[4]

MODE

[5]

TYPE

[6]

BALL

RESET

STATE

[7]

BALL

RESET

REL.

STATE

[8]

RESET

REL.

MODE

[9]

POWER

[10]

HYS

[11]

BUFFER PULLUP

IO

CELL

[14]

STRENG

TH

/DOWN

TYPE

[13]

(mA)

[12]

hsusb1_dir

3

4

6

7

0

1

2

3

4

5

6

7

0

2

3

4

6

7

0

3

4

5

6

7

0

3

4

6

7

0

3

4

5

6

7

0

3

4

5

6

7

0

3

4

5

6

7

0

4

7

0

4

7

I

gpio_22

IO

O

IO

I

hsusb1_tll_dir

hw_dbg10

etk_d9

V2

-

L

4

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

sys_secure_indicator

mmc3_dat5

hsusb1_nxt

gpio_23

IO

O

I

mm1_rxdm

hsusb1_tll_nxt

hw_dbg11

etk_d10

AE4

-

L

4

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

uart1_rx

hsusb2_clk

gpio_24

O

IO

O

IO

I

hsusb2_tll_clk

hw_dbg12

etk_d11

AF6

-

L

4

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

hsusb2_stp

gpio_25

mm2_rxdp

hsusb2_tll_stp

hw_dbg13

etk_d12

O

I

AE6

AF7

-

L

4

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

hsusb2_dir

gpio_26

IO

O

I

hsusb2_tll_dir

hw_dbg14

etk_d13

4⁽²⁾

PU100/

PD100

hsusb2_nxt

gpio_27

IO

O

IO

O

IO

O

IO

-

mm2_rxdm

hsusb2_tll_nxt

hw_dbg15

etk_d14

AF9

-

L

4

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

hsusb2_data0

gpio_28

mm2_rxrcv

hsusb2_tll_data0

hw_dbg16

etk_d15

AE9

-

L

4

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

hsusb2_data1

gpio_29

mm2_txse0

hsusb2_tll_data1

hw_dbg17

jtag_emu0

gpio_11

Y15

Y14

-

H

0

vdds_io

Yes

4

PU100/

PD100

LVCMOS

safe_mode

jtag_emu1

gpio_31

IO

-

PU100/

PD100

safe_mode

Submit Documentation Feedback

TERMINAL DESCRIPTION

47

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

SPRS599–JUNE 2009

www.ti.com

Table 2-2. Ball Characteristics (CBC Pkg.) (continued)

BALL

BOTTOM

[1]

BALL

TOP

[2]

NAME

[4]

MODE

[5]

TYPE

[6]

BALL

RESET

STATE

[7]

BALL

RESET

REL.

STATE

[8]

RESET

REL.

MODE

[9]

POWER

[10]

HYS

[11]

BUFFER PULLUP

IO

CELL

[14]

STRENG

TH

/DOWN

TYPE

[13]

(mA)

[12]

U3

N3

P3

W3

V3

-

mcbsp3_clkx

0

1

4

5

7

0

1

4

5

7

0

1

4

5

7

0

1

4

5

7

0

1

4

5

6

7

0

1

4

5

6

7

0

1

4

5

6

7

0

1

4

5

6

7

0

1

2

3

4

5

6

7

IO

O

IO

-

L

7

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

uart2_tx

gpio_142

hsusb3_tll_data6

safe_mode

mcbsp3_dr

uart2_rts

I

PU100/

PD100

O

IO

-

gpio_141

hsusb3_tll_data5

safe_mode

mcbsp3_dx

uart2_cts

IO

I

PU100/

PD100

gpio_140

IO

-

hsusb3_tll_data4

safe_mode

mcbsp3_fsx

uart2_rx

IO

I

PU100/

PD100

gpio_143

IO

-

hsusb3_tll_data7

safe_mode

mcbsp4_clkx

-

IO

I

PU100/

PD100

gpio_152

IO

-

hsusb3_tll_data1

mm3_txse0

safe_mode

mcbsp4_dr

-

U4

R3

T3

-

I

L

7

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

I

gpio_153

IO

-

hsusb3_tll_data0

mm3_rxrcv

safe_mode

mcbsp4_dx

-

IO

O

IO

-

PU100/

PD100

gpio_154

hsusb3_tll_data2

mm3_txdat

safe_mode

mcbsp4_fsx

-

IO

O

IO

-

PU100/

PD100

gpio_155

hsusb3_tll_data3

mm3_txen_n

safe_mode

mmc2_dat5

mmc2_dir_dat1

cam_global_reset

mmc3_dat1

gpio_137

M3

IO

O

IO

I

PU100/

PD100

hsusb3_tll_stp

mm3_rxdp

safe_mode

IO

-

48

TERMINAL DESCRIPTION

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Table 2-2. Ball Characteristics (CBC Pkg.) (continued)

BALL

BOTTOM

[1]

BALL

TOP

[2]

NAME

[4]

MODE

[5]

TYPE

[6]

BALL

RESET

STATE

[7]

BALL

RESET

REL.

STATE

[8]

RESET

REL.

MODE

[9]

POWER

[10]

HYS

[11]

BUFFER PULLUP

IO

CELL

[14]

STRENG

TH

/DOWN

TYPE

[13]

(mA)

[12]

L3

K3

W2

-

mmc2_dat6

0

1

2

3

4

5

7

0

1

3

4

5

6

7

0

1

4

5

7

IO

O

IO

O

-

L

7

vdds_io

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

mmc2_dir_cmd

cam_shutter

mmc3_dat2

gpio_138

hsusb3_tll_dir

safe_mode

mmc2_dat7

mmc2_clkin

mmc3_dat3

gpio_139

IO

I

PU100/

PD100

IO

-

hsusb3_tll_nxt

mm3_rxdm

safe_mode

uart1_cts

I

PU100/

PD100

-

I

gpio_150

IO

O

-

hsusb3_tll_clk

safe_mode

pop_gpmc_A9

AF4

-

AF12

pop_dpd_f_gpmc_nbeo_cl

e

AC16

AD18

L19

-

vss_csi2

VDDS_CSI2

vss_csib

AC19

AD19

L20

VSS_DSI

VDDS_DSI

VDDS_CSIb

pbias_mmc1a

VDDS_SDI

pop_gpmc_a7

vss

K23

AB24

AE25

Y26

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2.3 Multiplexing Characteristics

Table 2-3 and Table 2-4 provide a description of the OMAP3525 and OMAP3530 multiplexing on the CBB

and CBC packages, respectively.

Note: Table 2-3 and Table 2-4 do not take into account subsystem pin multiplexing options. Subsystem

pin multiplexing options are described in Section 2.4, Signal Description.

Table 2-3. Multiplexing Characteristics (CBB Pkg.)⁽¹⁾

Ball

Bottom

Ball

Top

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

Mode 6

Mode 7

D6

C6

J2

J1

sdrc_d0

sdrc_d1

sdrc_d2

sdrc_d3

sdrc_d4

sdrc_d5

sdrc_d6

sdrc_d7

sdrc_d8

sdrc_d9

sdrc_d10

sdrc_d11

sdrc_d12

sdrc_d13

sdrc_d14

sdrc_d15

sdrc_d16

sdrc_d17

sdrc_d18

sdrc_d19

sdrc_d20

sdrc_d21

sdrc_d22

sdrc_d23

sdrc_d24

sdrc_d25

sdrc_d26

sdrc_d27

sdrc_d28

sdrc_d29

sdrc_d30

sdrc_d31

sdrc_ba0

sdrc_ba1

sdrc_a0

sdrc_a1

sdrc_a2

sdrc_a3

sdrc_a4

-

B6

G2

C8

G1

C9

F2

A7

F1

B9

D2

A9

D1

C14

B14

C15

B16

D17

C17

B17

D18

D11

B10

C11

D12

C12

A11

B13

D14

C18

A19

B19

B20

D20

A21

B21

C21

H9

B13

A13

B14

A14

B16

A16

B19

A19

B3

A3

B5

A5

B8

A8

B9

A9

B21

A21

D22

D23

E22

E23

G22

G23

AB21

AC21

N22

N 23

P22

P23

R22

H10

A4

B4

B3

C5

C4

(1) NA in table stands for Not Applicable.

50 TERMINAL DESCRIPTION

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Table 2-3. Multiplexing Characteristics (CBB Pkg.) (continued)

Ball

Bottom

Ball

Top

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

Mode 6

Mode 7

D5

C3

R23

T22

sdrc_a5

sdrc_a6

-

C2

T23

sdrc_a7

-

C1

U22

U23

V22

V23

W22

W23

Y22

M22

M23

A11

B11

J22

sdrc_a8

-

D4

sdrc_a9

-

D3

sdrc_a10

sdrc_a11

sdrc_a12

sdrc_a13

sdrc_a14

sdrc_ncs0

sdrc_ncs1

sdrc_clk

-

D2

-

D1

-

E2

-

E1

-

H11

H12

A13

A14

H16

H17

H14

H13

H15

B7

-

sdrc_nclk

sdrc_cke0

sdrc_cke1

sdrc_nras

sdrc_ncas

sdrc_nwe

sdrc_dm0

sdrc_dm1

sdrc_dm2

sdrc_dm3

sdrc_dqs0

sdrc_dqs1

sdrc_dqs2

sdrc_dqs3

gpmc_a1

gpmc_a2

gpmc_a3

gpmc_a4

gpmc_a5

gpmc_a6

gpmc_a7

gpmc_a8

gpmc_a9

-

safe_mode

J23

-

safe_mode

L23

-

L22

-

K23

C1

-

A16

B11

C20

A6

A17

A6

-

A20

C2

-

A17

A10

A20

N4

B17

B6

-

B20

AC15

AB15

AC16

AB16

AC17

AB17

AC18

AB18

AC19

-

gpio_34

gpio_35

gpio_36

gpio_37

gpio_38

gpio_39

gpio_40

gpio_41

gpio_42

safe_mode

M4

L4

K4

T3

R3

N3

M3

L3

sys_

ndmareq2

K3

AB19

gpmc_a10

sys_

-

gpio_43

-

safe_mode

ndmareq3

K1

L1

M2

M1

N2

N 1

R2

R1

T2

gpmc_d0

gpmc_d1

gpmc_d2

gpmc_d3

gpmc_d4

gpmc_d5

gpmc_d6

gpmc_d7

-

L2

P2

T1

V1

V2

W2

T1

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Table 2-3. Multiplexing Characteristics (CBB Pkg.) (continued)

Ball

Bottom

Ball

Top

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

Mode 6

Mode 7

H2

K2

P1

R1

R2

T2

W1

Y1

G4

H3

V8

U8

AB3

AC3

AB4

AC4

AB6

AC6

AB7

AC7

Y2

gpmc_d8

gpmc_d9

-

gpio_44

gpio_45

gpio_46

gpio_47

gpio_48

gpio_49

gpio_50

gpio_51

-

safe_mode

-

gpmc_d10

gpmc_d11

gpmc_d12

gpmc_d13

gpmc_d14

gpmc_d15

gpmc_ncs0

gpmc_ncs1

gpmc_ncs2

gpmc_ncs3

Y1

gpio_52

gpio_53

gpio_54

safe_mode

NA

sys_

ndmareq0

T8

R8

P8

N8

NA

gpmc_ncs4

gpmc_ncs5

gpmc_ncs6

sys_

ndmareq1

mcbsp4_clkx gpt9_pwm_

evt

gpio_55

gpio_56

gpio_57

gpio_58

-

safe_mode

sys_

ndmareq2

mcbsp4_dr gpt10_pwm_

evt

sys_

ndmareq3

mcbsp4_dx gpt11_pwm_

evt

gpmc_ncs7 gpmc_io_dir mcbsp4_fsx gpt8_pwm_

evt

T4

F3

W2

W1

gpmc_clk

-

gpio_59

-

safe_mode

-

gpmc_nadv_

ale

G2

F4

G3

V2

V1

gpmc_noe

gpmc_nwe

-

AC12 gpmc_nbe0_

cle

gpio_60

safe_mode

U3

H1

M8

L8

NA

AB10

AB12

AC10

NA

gpmc_nbe1

gpmc_nwp

gpmc_wait0

gpmc_wait1

gpmc_wait2

gpmc_wait3

-

gpio_61

gpio_62

-

safe_mode

-

gpio_63

gpio_64

gpio_65

safe_mode

K8

J8

NA

sys_

ndmareq1

D28

D26

NA

dss_pclk

dss_hsync

dss_vsync

dss_acbias

dss_data0

dss_data1

dss_data2

dss_data3

dss_data4

dss_data5

dss_data6

dss_data7

dss_data8

dss_data9

-

gpio_66

gpio_67

gpio_68

gpio_69

gpio_70

gpio_71

gpio_72

gpio_73

gpio_74

gpio_75

gpio_76

gpio_77

gpio_78

gpio_79

-

safe_mode

-

D27

-

E27

-

AG22

AH22

AG23

AH23

AG24

AH24

E26

uart1_cts

uart1_rts

-

uart3_rx_irrx

uart3_tx_irtx

uart1_tx

uart1_rx

-

F28

F27

G26

-

52

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Table 2-3. Multiplexing Characteristics (CBB Pkg.) (continued)

Ball

Bottom

Ball

Top

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

Mode 6

Mode 7

AD28

AD27

AB28

AB27

AA28

AA27

G25

H27

NA

dss_data10

dss_data11

dss_data12

dss_data13

dss_data14

dss_data15

dss_data16

dss_data17

dss_data18

dss_data19

dss_data20

dss_data21

dss_data22

dss_data23

tv_out2

-

gpio_80

gpio_81

gpio_82

gpio_83

gpio_84

gpio_85

gpio_86

gpio_87

gpio_88

gpio_89

gpio_90

gpio_91

gpio_92

gpio_93

-

safe_mode

-

H26

mcspi3_clk

dss_data0

H25

mcspi3_simo

dss_data1

E28

mcspi3_somi

dss_data2

J26

mcspi3_cs0

dss_data3

AC27

AC28

W28

Y28

mcspi3_cs1

dss_data4

-

dss_data5

-

tv_out1

-

Y27

tv_vfb1

-

W27

W26

A24

tv_vfb2

-

tv_vref

-

cam_hs

gpio_94

gpio_95

gpio_96

gpio_97

gpio_98

safe_mode

A23

cam_vs

C25

cam_xclka

cam_pclk

cam_fld

C27

C23

cam_global_

reset

AG17

AH17

B24

NA

cam_d0

cam_d1

cam_d2

cam_d3

cam_d4

cam_d5

cam_d6

cam_d7

cam_d8

cam_d9

cam_d10

cam_d11

cam_xclkb

cam_wen

cam_strobe

-

gpio_99

gpio_100

gpio_101

gpio_102

gpio_103

gpio_104

gpio_105

gpio_106

gpio_107

gpio_108

gpio_109

gpio_110

gpio_111

gpio_167

gpio_126

gpio_112

gpio_113

gpio_114

gpio_115

gpio_116

gpio_117

gpio_118

-

safe_mode

-

C24

D24

A25

-

K28

-

L28

-

K27

-

L27

-

B25

-

C26

B26

-

B23

cam_shutter

D25

AG19

AH19

AG18

AH18

P21

-

mcbsp2_fsx

mcbsp2_clkx

mcbsp2_dr

N21

R21

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Table 2-3. Multiplexing Characteristics (CBB Pkg.) (continued)

Ball

Bottom

Ball

Top

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

Mode 6

Mode 7

M21

N28

M27

N27

N26

N25

P28

P27

P26

R27

R25

AE2

AG5

AH5

AH4

AG4

AF4

AE4

NA

N A

NA

mcbsp2_dx

mmc1_clk

-

gpio_119

gpio_120

gpio_121

gpio_122

gpio_123

gpio_124

gpio_125

gpio_126

gpio_127

gpio_128

gpio_129

gpio_130

gpio_131

gpio_132

gpio_133

gpio_134

gpio_135

gpio_136

-

safe_mode

-

mmc1_cmd

mmc1_dat0

mmc1_dat1

mmc1_dat2

mmc1_dat3

mmc1_dat4

mmc1_dat5

mmc1_dat6

mmc1_dat7

mmc2_clk

-

mcspi3_clk

-

mmc2_cmd mcspi3_simo

mmc2_dat0 mcspi3_somi

-

mmc2_dat1

-

mmc2_dat2 mcspi3_cs1

mmc2_dat3 mcspi3_cs0

-

mmc2_dat4

mmc2_dat5

mmc2_dat6

mmc2_dir_

dat0

mmc3_dat0

AH3

AF3

NA

mmc2_dir_ cam_global_ mmc3_dat1

gpio_137

gpio_138

gpio_139

gpio_140

gpio_141

gpio_142

gpio_143

gpio_144

gpio_145

gpio_146

gpio_147

hsusb3_tll_

stp

mm3_rxdp

safe_mode

dat1

reset

mmc2_dir_

cmd

cam_shutter mmc3_dat2

hsusb3_tll_

dir

-

AE3

mmc2_dat7 mmc2_clkin

-

mmc3_dat3

hsusb3_tll_

nxt

mm3_rxdm

AF6

mcbsp3_dx

mcbsp3_dr

mcbsp3_clkx

mcbsp3_fsx

uart2_cts

uart2_rts

uart2_tx

-

hsusb3_tll_

data4

-

AE6

hsusb3_tll_

data5

AF5

hsusb3_tll_

data6

AE5

uart2_rx

hsusb3_tll_

data7

AB26

AB25

AA25

AD25

mcbsp3_dx

gpt9_pwm_

evt

-

uart2_rts

mcbsp3_dr gpt10_pwm_

evt

uart2_tx

mcbsp3_clkx gpt11_pwm_

evt

uart2_rx

mcbsp3_fsx gpt8_pwm_

evt

AA8

AA9

W8

NA

uart1_tx

uart1_rts

uart1_cts

-

gpio_148

gpio_149

gpio_150

-

safe_mode

hsusb3_tll_

clk

Y8

NA

uart1_rx

-

mcbsp1_clkr mcspi4_clk

gpio_151

gpio_152

-

safe_mode

AE1

mcbsp4_clkx

-

hsusb3_tll_

data1

mm3_txse0

AD1

NA

mcbsp4_dr

-

gpio_153

hsusb3_tll_

data0

mm3_rxrcv

safe_mode

54

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Table 2-3. Multiplexing Characteristics (CBB Pkg.) (continued)

Ball

Bottom

Ball

Top

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

gpio_154

gpio_155

Mode 5

Mode 6

Mode 7

AD2

NA

mcbsp4_dx

mcbsp4_fsx

-

hsusb3_tll_

data2

mm3_txdat

safe_mode

AC1

NA

hsusb3_tll_ mm3_txen_n safe_mode

data3

Y21

NA

mcbsp1_clkr mcspi4_clk

mcbsp1_fsr

-

gpio_156

gpio_157

-

safe_mode

AA21

-

cam_global_

reset

V21

U21

T21

K26

W21

H18

NA

N A

NA

mcbsp1_dx mcspi4_simo mcbsp3_dx

mcbsp1_dr mcspi4_somi mcbsp3_dr

-

gpio_158

gpio_159

gpio_160

gpio_161

gpio_162

gpio_163

-

safe_mode

-

mcbsp_clks

-

cam_shutter

uart1_cts

mcbsp1_fsx mcspi4_cs0 mcbsp3_fsx

-

mcbsp1_clkx

-

mcbsp3_clkx

-

uart3_cts_rct

x

H19

H20

H21

T28

T25

R28

T26

T27

NA

N A

NA

uart3_rts_sd

uart3_rx_irrx

uart3_tx_irtx

hsusb0_clk

hsusb0_stp

hsusb0_dir

hsusb0_nxt

-

gpio_164

gpio_165

gpio_166

gpio_120

gpio_121

gpio_122

gpio_124

gpio_125

-

safe_mode

-

hsusb0_

data0

uart3_tx_irtx

U28

U27

U26

U25

V28

V27

V26

NA

hsusb0_

data1

-

uart3_rx_irrx

uart3_rts_sd

-

gpio_130

gpio_131

gpio_169

gpio_188

gpio_189

gpio_190

gpio_191

-

safe_mode

hsusb0_

data2

hsusb0_

data3

uart3_cts_

rctx

hsusb0_

data4

-

hsusb0_

data5

hsusb0_

data6

hsusb0_

data7

K21

J21

NA

i2c1_scl

i2c1_sda

i2c2_scl

i2c2_sda

i2c3_scl

i2c3_sda

i2c4_scl

-

AF15

AE15

AF14

AG14

AD26

gpio_168

gpio_183

gpio_184

gpio_185

-

safe_mode

sys_

nvmode1

AE26

NA

i2c4_sda

sys_

-

safe_mode

nvmode2

J25

AB3

AB4

AA4

NA

hdq_sio

sys_altclk

i2c2_sccbe

i2c3_sccbe

gpio_170

gpio_171

gpio_172

gpio_173

-

safe_mode

mcspi1_clk

mmc2_dat4

-

mcspi1_simo mmc2_dat5

mcspi1_somi mmc2_dat6

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Table 2-3. Multiplexing Characteristics (CBB Pkg.) (continued)

Ball

Bottom

Ball

Top

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

Mode 6

Mode 7

AC2

AC3

AB1

AB2

NA

mcspi1_cs0 mmc2_dat7

-

gpio_174

gpio_175

gpio_176

gpio_177

-

safe_mode

mcspi1_cs1

mcspi1_cs2

mcspi1_cs3

-

mmc3_cmd

mmc3_clk

-

hsusb2_tll_

data2

hsusb2_

data2

mm2_txdat

AA3

Y2

NA

mcspi2_clk

-

hsusb2_tll_

data7

hsusb2_

data7

gpio_178

gpio_179

gpio_180

gpio_181

gpio_182

-

safe_mode

mcspi2_simo gpt9_pwm_

evt

hsusb2_tll_

data4

hsusb2_

data4

-

Y3

mcspi2_somi gpt10_pwm_ hsusb2_tll_

evt data5

hsusb2_

data5

-

Y4

mcspi2_cs0 gpt11_pwm_ hsusb2_tll_

hsusb2_

data6

-

evt

data6

V3

mcspi2_cs1

gpt8_pwm_

evt

hsusb2_tll_

data3

hsusb2_

data3

mm2_txen_n

AE25

AE17

AF17

AF25

AF26

AH25

NA

sys_32k

sys_xtalin

sys_xtalout

sys_clkreq

sys_nirq

-

gpio_1

gpio_0

-

safe_mode

-

sys_nrespwr

on

AF24

NA

sys_nreswar

m

-

gpio_30

-

safe_mode

AH26

AG26

AE14

AF18

AF19

NA

sys_boot0

sys_boot1

sys_boot2

sys_boot3

sys_boot4

-

gpio_2

gpio_3

gpio_4

gpio_5

gpio_6

-

safe_mode

mmc2_dir_

dat2

AE21

NA

sys_boot5

mmc2_dir_

dat3

-

gpio_7

-

safe_mode

AF21

AF22

N A

NA

sys_boot6

-

gpio_8

gpio_9

-

safe_mode

sys_off_

mode

AG25

AE22

B1

NA

sys_clkout1

sys_clkout2

sys_ipmcsws

-

gpio_10

-

safe_mode

gpio_186

safe_mode

-

A1

sys_

opmcsws

AA17

AA13

AA12

AA18

NA

jtag_ntrst

jtag_tck

jtag_rtck

-

jtag_tms_

tmsc

AA20

AA19

AA11

AA10

AF10

NA

jtag_tdi

jtag_tdo

-

jtag_emu0

jtag_emu1

etk_clk

-

gpio_11

gpio_31

gpio_12

-

safe_mode

-

mcbsp5_clkx

mmc3_clk

hsusb1_stp

mm1_rxdp

hsusb1_tll_

stp

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Table 2-3. Multiplexing Characteristics (CBB Pkg.) (continued)

Ball

Bottom

Ball

Top

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

gpio_13

gpio_14

gpio_15

gpio_16

gpio_17

gpio_18

gpio_19

gpio_20

gpio_21

gpio_22

gpio_23

gpio_24

gpio_25

gpio_26

gpio_27

gpio_28

gpio_29

Mode 5

Mode 6

Mode 7

AE10

AF11

AG12

AH12

AE13

AE11

AH9

NA

etk_ctl

-

mmc3_cmd

hsusb1_clk

-

hsusb1_tll_

clk

-

etk_d0

etk_d1

etk_d2

etk_d3

etk_d4

etk_d5

etk_d6

etk_d7

etk_d8

etk_d9

etk_d10

etk_d11

etk_d12

etk_d13

etk_d14

etk_d15

mcspi3_simo mmc3_dat4

hsusb1_

data0

mm1_rxrcv

hsusb1_tll_

data0

mcspi3_somi

mcspi3_cs0

mcspi3_clk

mcbsp5_dr

-

hsusb1_

data1

mm1_txse0

hsusb1_tll_

data1

-

hsusb1_

data2

mm1_txdat

hsusb1_tll_

data2

mmc3_dat3

mmc3_dat0

hsusb1_

data7

-

hsusb1_tll_

data7

hsusb1_

data4

hsusb1_tll_

data4

mcbsp5_fsx mmc3_dat1

mcbsp5_dx mmc3_dat2

mcspi3_cs1 mmc3_dat7

hsusb1_

data5

hsusb1_tll_

data5

AF13

AH14

AF9

hsusb1_

data6

hsusb1_tll_

data6

hsusb1_

data3

mm1_txen_n hsusb1_tll_

data3

sys_drm_

msecure

mmc3_dat6

hsusb1_dir

hsusb1_nxt

hsusb2_clk

hsusb2_stp

hsusb2_dir

hsusb2_nxt

-

hsusb1_tll_

dir

AG9

AE7

sys_secure_ mmc3_dat5

indicator

mm1_rxdm

-

hsusb1_tll_

nxt

-

uart1_rx

hsusb2_tll_

clk

AF7

-

mm2_rxdp

-

hsusb2_tll_

stp

AG7

AH7

hsusb2_tll_

dir

mm2_rxdm

mm2_rxrcv

mm2_txse0

hsusb2_tll_

nxt

AG8

AH8

hsusb2_

data0

hsusb2_tll_

data0

hsusb2_

data1

hsusb2_tll_

data1

Table 2-4. Multiplexing Characteristics (CBC Pkg.)

Ball

Ball Top

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

Mode 6

Mode 7

Bottom

AE16

-

cam_d0

cam_d1

-

gpio_99

-

safe_mode

AE15

-

gpio_100

safe_mode

AD17

-

gpio_112

safe_mode

AE18

-

gpio_114

safe_mode

AD16

-

gpio_113

safe_mode

AE17

-

gpio_115

safe_mode

-

G20

K20

J20

J21

U21

R20

M21

M20

sdrc_a0

sdrc_a1

sdrc_a2

sdrc_a3

sdrc_a4

sdrc_a5

sdrc_a6

sdrc_a7

-

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57

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

SPRS599–JUNE 2009

www.ti.com

Table 2-4. Multiplexing Characteristics (CBC Pkg.) (continued)

Ball

Ball Top

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

Mode 6

Mode 7

Bottom

-

–

-

N20

K21

Y16

N21

R21

AA15

Y12

AA18

V20

Y15

Y13

A12

D1

sdrc_a8

-

sdrc_a9

-

sdrc_a10

sdrc_a11

sdrc_a12

sdrc_a13

sdrc_a14

sdrc_ba0

sdrc_ba1

sdrc_cke0

sdrc_cke1

sdrc_clk

sdrc_d0

-

safe_mode

-

G1

sdrc_d1

G2

sdrc_d2

E1

sdrc_d3

D2

sdrc_d4

E2

sdrc_d5

B3

sdrc_d6

B4

sdrc_d7

A10

B11

A11

B12

A16

A17

B17

B18

B7

sdrc_d8

sdrc_d9

sdrc_d10

sdrc_d11

sdrc_d12

sdrc_d13

sdrc_d14

sdrc_d15

sdrc_d16

sdrc_d17

sdrc_d18

sdrc_d19

sdrc_d20

sdrc_d21

sdrc_d22

sdrc_d23

sdrc_d24

sdrc_d25

sdrc_d26

sdrc_d27

sdrc_d28

sdrc_d29

sdrc_d30

sdrc_d31

sdrc_dm0

sdrc_dm1

A5

B6

A6

A8

B9

A9

B10

C21

D20

B19

C20

D21

E20

E21

G21

H1

A14

58

TERMINAL DESCRIPTION

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SPRS599–JUNE 2009

Table 2-4. Multiplexing Characteristics (CBC Pkg.) (continued)

Ball

Ball Top

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

Mode 6

Mode 7

Bottom

-

A4

sdrc_dm2

sdrc_dm3

sdrc_dqs0

sdrc_dqs1

sdrc_dqs2

sdrc_dqs3

sdrc_ncas

sdrc_nclk

-

A18

-

C2

-

B15

-

B8

-

A19

-

U20

-

B13

-

T21

sdrc_ncs0

sdrc_ncs1

sdrc_nras

sdrc_nwe

-

T20

-

V21

-

Y18

-

AE21

AE22

AE23

AE24

AC26

AD26

AA25

Y25

AA26

AB26

F25

-

dss_data0

dss_data1

dss_data2

dss_data3

dss_data10

dss_data11

dss_data12

dss_data13

dss_data14

dss_data15

dss_data20

dx0

uart1_cts

-

gpio_70

gpio_71

gpio_72

gpio_73

gpio_80

gpio_81

gpio_82

gpio_83

gpio_84

gpio_85

gpio_90

safe_mode

dy0

uart1_rts

-

dx1

-

dy1

-

mcspi3_so

mi

dss_data2

AC25

AB25

G25

J2

-

dss_data22

dss_data23

dss_pclk

gpmc_a1

gpmc_a2

gpmc_a3

gpmc_a4

gpmc_a5

gpmc_a6

gpmc_a7

gpmc_a8

gpmc_a9

-

mcspi3_cs1 dss_data4

gpio_92

gpio_93

gpio_66

gpio_34

gpio_35

gpio_36

gpio_37

gpio_38

gpio_39

gpio_40

gpio_41

gpio_42

-

safe_mode

-

dss_data5

-

hw_dbg12

AA13

-

H1

-

H2

G2

F1

F2

E1

E2

D1

sys_ndmare

q2

D2

-

gpmc_a10

sys_ndmare

q3

-

gpio_43

-

safe_mode

N 1

-

gpmc_clk

gpmc_d0

gpmc_d1

gpmc_d2

gpmc_d3

gpmc_d4

gpmc_d5

gpmc_d6

-

gpio_59

-

safe_mode

AA2

AA1

AC2

AC1

AE5

AD6

AD5

-

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OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

SPRS599–JUNE 2009

www.ti.com

Table 2-4. Multiplexing Characteristics (CBC Pkg.) (continued)

Ball

Ball Top

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

Mode 6

Mode 7

Bottom

AC5

V1

-

gpmc_d7

gpmc_d8

gpmc_d9

gpmc_d10

gpmc_d11

gpmc_d12

gpmc_d13

gpmc_d14

gpmc_d15

-

gpio_44

gpio_45

gpio_46

gpio_47

gpio_48

gpio_49

gpio_50

gpio_51

-

safe_mode

-

Y1

T1

U2

U1

P1

L2

M2

AD10

gpmc_nadv

_ale

K2

-

gpmc_nbe0

_cle

-

gpio_60

-

safe_mode

J1

-

gpmc_nbe1

gpmc_ncs0

gpmc_ncs1

gpmc_ncs2

-

gpio_61

-

safe_mode

-

AD8

AD1

A3

gpio_52

gpio_53

gpio_54

safe_mode

B6

gpmc_ncs3 sys_ndmare

q0

B4

C4

B5

C5

-

gpmc_ncs4 sys_ndmare mcbsp4_clk gpt9_pwm_ gpio_55

q1 evt

-

safe_mode

x

gpmc_ncs5 sys_ndmare mcbsp4_dr gpt10_pwm gpio_56

q2 _evt

gpmc_ncs6 sys_ndmare mcbsp4_dx gpt11_pwm gpio_57

q3 _evt

gpmc_ncs7 gpmc_io_dir mcbsp4_fsx gpt8_pwm_ gpio_58

evt

N2

-

gpmc_noe

gpmc_nwe

gpmc_nwp

gpmc_wait0

gpmc_wait1

gpmc_wait2

-

M1

-

AC6

AC11

AC8

B3

gpio_62

-

safe_mode

-

gpio_63

gpio_64

gpio_65

safe_mode

C6

gpmc_wait3 sys_ndmare

q1

W19

V20

-

hsusb0_clk

-

gpio_120

gpio_125

-

safe_mode

hsusb0_dat

a0

uart3_tx_irtx

Y20

V18

W20

W17

Y18

Y19

-

hsusb0_dat

a1

-

uart3_rx_irr

x

-

gpio_130

gpio_131

gpio_169

gpio_188

gpio_189

gpio_190

-

safe_mode

hsusb0_dat

a2

uart3_rts_s

d

hsusb0_dat

a3

uart3_cts_rc

tx

hsusb0_dat

a4

-

hsusb0_dat

a5

hsusb0_dat

a6

60

TERMINAL DESCRIPTION

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SPRS599–JUNE 2009

Table 2-4. Multiplexing Characteristics (CBC Pkg.) (continued)

Ball

Ball Top

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

Mode 6

Mode 7

Bottom

Y17

-

hsusb0_dat

a7

-

gpio_191

-

safe_mode

V19

W18

U20

U15

W13

V14

U16

Y13

V15

-

hsusb0_dir

hsusb0_nxt

hsusb0_stp

jtag_ntrst

jtag_rtck

jtag_tck

-

gpio_122

-

safe_mode

gpio_124

safe_mode

gpio_121

safe_mode

-

jtag_tdi

jtag_tdo

jtag_tms_tm

sc

AE19

K20

-

vdd_dsi

-

vdd_sram_c

ore

N9

-

vdd_sram_

mpu_iva

-

K14

-

vdd_wkup

-

vdd_sram_e

mu

N19

L18

M19

M18

K18

N20

M20

P17

P18

P19

J25

J24

C2

-

mmc1_clk

ms_clk

-

gpio_120

gpio_121

gpio_122

gpio_123

gpio_124

gpio_125

gpio_126

gpio_127

gpio_128

gpio_129

-

safe_mode

-

mmc1_cmd ms_bs

mmc1_dat0 ms_dat0

mmc1_dat1 ms_dat1

mmc1_dat2 ms_dat2

mmc1_dat3 ms_dat3

mmc1_dat4

mmc1_dat5

mmc1_dat6

mmc1_dat7

i2c1_scl

-

i2c1_sda

i2c2_scl

-

gpio_168

gpio_183

gpio_184

gpio_185

gpio_156

safe_mode

C1

i2c2_sda

i2c3_scl

AB4

AC4

U19

i2c3_sda

mcbsp1_clk mcspi4_clk

r

T17

T20

U17

V17

-

mcbsp1_clk

x

-

mcbsp3_clk

x

-

gpio_162

gpio_159

gpio_158

gpio_157

-

safe_mode

mcbsp1_dr mcspi4_so

mi

mcbsp3_dr

mcbsp1_dx mcspi4_sim mcbsp3_dx

o

mcbsp1_fsr

-

cam_global

_reset

P20

R18

-

mcbsp1_fsx mcspi4_cs0 mcbsp3_fsx

-

gpio_161

gpio_117

-

safe_mode

mcbsp2_clk

x

-

T18

-

mcbsp2_dr

-

gpio_118

-

safe_mode

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61

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

SPRS599–JUNE 2009

www.ti.com

Table 2-4. Multiplexing Characteristics (CBC Pkg.) (continued)

Ball

Ball Top

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

Mode 6

Mode 7

Bottom

R19

U18

P9

-

mcbsp2_dx

mcbsp2_fsx

-

gpio_119

gpio_116

gpio_171

gpio_174

gpio_176

gpio_172

-

safe_mode

-

mcspi1_clk mmc2_dat4

mcspi1_cs0 mmc2_dat7

-

R7

-

R9

mcspi1_cs2

-

mmc3_clk

-

P8

mcspi1_sim mmc2_dat5

o

P7

-

mcspi1_so

mi

mmc2_dat6

-

gpio_173

-

safe_mode

W10

R10

-

mmc2_clk

mcspi3_clk

-

gpio_130

gpio_131

-

safe_mode

mmc2_cmd mcspi3_sim

o

T10

-

mmc2_dat0 mcspi3_so

mi

-

gpio_132

-

safe_mode

T9

-

mmc2_dat1

-

gpio_133

gpio_134

gpio_135

-

safe_mode

U10

U9

mmc2_dat2 mcspi3_cs1

mmc2_dat3 mcspi3_cs0

V10

mmc2_dat4 mmc2_dir_d

at0

mmc3_dat0 gpio_136

R2

H3

-

uart1_rts

uart1_rx

-

gpio_149

-

safe_mode

mcbsp1_clk mcspi4_clk gpio_151

r

L4

-

uart1_tx

-

gpio_148

gpio_144

-

safe_mode

Y24

uart2_cts

mcbsp3_dx gpt9_pwm_

evt

AA24

AD21

AD22

F23

-

uart2_rts

uart2_rx

uart2_tx

mcbsp3_dr gpt10_pwm

_evt

-

gpio_145

gpio_147

gpio_146

gpio_163

gpio_164

gpio_165

gpio_166

-

safe_mode

mcbsp3_fsx gpt8_pwm_

evt

mcbsp3_clk gpt11_pwm

x

_evt

uart3_cts_rc

tx

-

F24

uart3_rts_s

d

-

H24

uart3_rx_irr

x

G24

J23

-

uart3_tx_irtx

hdq_sio

-

safe_mode

sys_altclk

i2c2_sccbe i2c3_sccbe gpio_170

AD15

i2c4_scl

sys_nvmod

e1

-

W16

-

i2c4_sda

sys_nvmod

e2

-

safe_mode

F3

D3

C3

E3

E4

-

sys_boot0

sys_boot1

sys_boot2

sys_boot3

sys_boot4

-

gpio_2

gpio_3

gpio_4

gpio_5

gpio_6

-

safe_mode

mmc2_dir_d

at2

G3

D4

-

sys_boot5

sys_boot6

mmc2_dir_d

at3

-

gpio_7

gpio_8

-

safe_mode

-

62

TERMINAL DESCRIPTION

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SPRS599–JUNE 2009

Table 2-4. Multiplexing Characteristics (CBC Pkg.) (continued)

Ball

Ball Top

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

Mode 6

Mode 7

Bottom

AE14

W11

W15

V16

-

sys_clkout1

sys_clkout2

sys_clkreq

sys_nirq

-

gpio_10

gpio_186

gpio_1

gpio_0

-

safe_mode

-

V13

sys_nrespw

ron

AD7

V12

-

sys_nreswa

rm

-

gpio_30

gpio_9

-

safe_mode

sys_off_mo

de

AF19

D6

-

sys_xtalin

bg_testout

-

N18

pbias_mmc

1

K23

B1

-

pbias_mmc

1a

-

sys_ipmcsw

s

A2

sys_opmcs

ws

W26

V26

W25

U24

V23

AE20

A24

B24

D24

C24

D25

E26

B23

-

tv_out1

tv_out2

tv_vfb1

tv_vfb2

tv_vref

-

sys_32k

cam_d2

cam_d3

cam_d4

cam_d5

cam_d10

cam_d11

cam_fld

-

gpio_101

gpio_102

gpio_103

gpio_104

gpio_109

gpio_110

gpio_98

hw_dbg4

hw_dbg5

hw_dbg6

hw_dbg7

hw_dbg8

hw_dbg9

hw_dbg3

safe_mode

cam_global

_reset

C23

C26

D26

C25

E25

P25

P26

N25

N26

D23

A23

F26

G26

H25

H26

-

cam_hs

-

gpio_94

gpio_97

gpio_126

gpio_96

gpio_111

gpio_105

gpio_106

gpio_107

gpio_108

gpio_95

gpio_167

gpio_69

gpio_76

gpio_77

gpio_78

hw_dbg0

-

safe_mode

cam_pclk

cam_strobe

cam_xclka

cam_xclkb

cam_d6

-

hw_dbg2

-

hw_dbg11

-

cam_d7

-

cam_d8

-

cam_d9

-

cam_vs

-

hw_dbg1

hw_dbg10

-

cam_wen

dss_acbias

dss_data6

dss_data7

dss_data8

cam_shutter

-

uart1_tx

uart1_rx

-

hw_dbg14

hw_dbg15

hw_dbg16

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OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

SPRS599–JUNE 2009

www.ti.com

Table 2-4. Multiplexing Characteristics (CBC Pkg.) (continued)

Ball

Ball Top

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

Mode 6

Mode 7

Bottom

J26

L25

L26

M24

M26

-

dss_data9

dss_data16

dss_data17

dss_data18

dss_data19

-

gpio_79

gpio_86

gpio_87

gpio_88

gpio_89

hw_dbg17

-

safe_mode

-

mcspi3_clk dss_data0

mcspi3_sim dss_data1

o

N24

K24

M25

R8

-

dss_data21

dss_hsync

dss_vsync

mcspi1_cs1

mcspi1_cs3

-

mcspi3_cs0 dss_data3

gpio_91

gpio_67

gpio_68

-

safe_mode

-

hw_dbg13

-

mmc3_cmd gpio_175

-

T8

hsusb2_tll_ hsusb2_dat gpio_177

data2 a2

mm2_txdat

V9

-

mcspi2_cs1 gpt8_pwm_ hsusb2_tll_ hsusb2_dat gpio_182

mm2_txen_

n

-

safe_mode

evt

data3

a3

T19

AB2

-

mcbsp_clks

etk_clk

-

cam_shutter

-

gpio_160

uart1_cts

mcbsp5_clk mmc3_clk

x

hsusb1_stp gpio_12

mm1_rxdp

hsusb1_tll_ hw_dbg0

stp

AB3

AC3

AD4

AD3

AA3

Y3

-

etk_ctl

-

mmc3_cmd hsusb1_clk gpio_13

-

hsusb1_tll_ hw_dbg1

clk

etk_d0

etk_d1

etk_d2

etk_d3

etk_d4

etk_d5

etk_d6

etk_d7

etk_d8

etk_d9

etk_d10

etk_d11

etk_d12

etk_d13

etk_d14

etk_d15

mcspi3_sim mmc3_dat4 hsusb1_dat gpio_14

o

mm1_rxrcv hsusb1_tll_ hw_dbg2

data0

a0

mcspi3_so

mi

-

hsusb1_dat gpio_15

a1

mm1_txse0 hsusb1_tll_ hw_dbg3

data1

mcspi3_cs0

hsusb1_dat gpio_16

a2

mm1_txdat hsusb1_tll_ hw_dbg4

data2

mcspi3_clk mmc3_dat3 hsusb1_dat gpio_17

a7

-

hsusb1_tll_ hw_dbg5

data7

mcbsp5_dr mmc3_dat0 hsusb1_dat gpio_18

a4

hsusb1_tll_ hw_dbg6

data4

AB1

AE3

AD2

AA4

V2

mcbsp5_fsx mmc3_dat1 hsusb1_dat gpio_19

a5

hsusb1_tll_ hw_dbg7

data5

mcbsp5_dx mmc3_dat2 hsusb1_dat gpio_20

a6

hsusb1_tll_ hw_dbg8

data6

mcspi3_cs1 mmc3_dat7 hsusb1_dat gpio_21

a3

mm1_txen_ hsusb1_tll_ hw_dbg9

n

data3

sys_drm_m mmc3_dat6 hsusb1_dir gpio_22

secure

-

hsusb1_tll_ hw_dbg10

dir

sys_secure mmc3_dat5 hsusb1_nxt gpio_23

_indicator

mm1_rxdm hsusb1_tll_ hw_dbg11

nxt

AE4

AF6

AE6

AF7

AF9

AE9

-

uart1_rx

hsusb2_clk gpio_24

hsusb2_stp gpio_25

hsusb2_dir gpio_26

hsusb2_nxt gpio_27

-

hsusb2_tll_ hw_dbg12

clk

-

mm2_rxdp

-

hsusb2_tll_ hw_dbg13

stp

hsusb2_tll_ hw_dbg14

dir

mm2_rxdm hsusb2_tll_ hw_dbg15

nxt

hsusb2_dat gpio_28

a0

mm2_rxrcv hsusb2_tll_ hw_dbg16

data0

hsusb2_dat gpio_29

a1

mm2_txse0 hsusb2_tll_ hw_dbg17

data1

Y15

Y14

-

jtag_emu0

jtag_emu1

-

gpio_11

gpio_31

-

safe_mode

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Table 2-4. Multiplexing Characteristics (CBC Pkg.) (continued)

Ball

Ball Top

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

Mode 6

Mode 7

Bottom

U3

N3

P3

W3

V3

U4

R3

T3

-

mcbsp3_clk uart2_tx

x

-

gpio_142

gpio_141

gpio_140

gpio_143

gpio_152

gpio_153

gpio_154

gpio_155

hsusb3_tll_

data6

-

safe_mode

mcbsp3_dr uart2_rts

mcbsp3_dx uart2_cts

mcbsp3_fsx uart2_rx

hsusb3_tll_

data5

hsusb3_tll_

data4

hsusb3_tll_

data7

mcbsp4_clk

x

-

hsusb3_tll_ mm3_txse0 safe_mode

data1

mcbsp4_dr

mcbsp4_dx

mcbsp4_fsx

hsusb3_tll_ mm3_rxrcv safe_mode

data0

hsusb3_tll_ mm3_txdat safe_mode

data2

hsusb3_tll_ mm3_txen_ safe_mode

data3

n

M3

L3

mmc2_dat5 mmc2_dir_d cam_global mmc3_dat1 gpio_137

at1 _reset

hsusb3_tll_ mm3_rxdp

stp

safe_mode

mmc2_dat6 mmc2_dir_c cam_shutter mmc3_dat2 gpio_138

md

hsusb3_tll_

dir

-

K3

W2

mmc2_dat7 mmc2_clkin

-

mmc3_dat3 gpio_139

hsusb3_tll_ mm3_rxdm safe_mode

nxt

uart1_cts

-

gpio_150

hsusb3_tll_

clk

-

safe_mode

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2.4 Signal Description

Many signals are available on multiple pins according to the software configuration of the pin multiplexing

options.

1. SIGNAL NAME: The signal name

2. DESCRIPTION: Description of the signal

3. TYPE: Type = Ball type for this specific function:

–

I = Input

O = Output

Z = High-impedance

D = Open Drain

DS = Differential

A = Analog

4. BALL BOTTOM: Associated ball(s) bottom

5. BALL TOP: Associated ball(s) top

6. SUBSYSTEM PIN MULTIPLEXING: Contains a list of the pin multiplexing options at the

module/subsystem level. The pin function is selected at the module/system level.

Note: The Subsystem Multiplexing Signals are not described in Table 2-1 through Table 2-4.

2.4.1 External Memory Interfaces

Table 2-5. External Memory Interfaces – GPMC Signals Description

SIGNAL

NAME [1]

DESCRIPTION [2]

TYPE

[3]

BALL

BOTTOM

(CBB

BALL

TOP

(CBB

BALL BOTTOM

(CBC Pkg.) [4] (CBC Pkg.) [5]

BALL TOP

SUBSYSTEM

MULTIPLEXIN

Pkg.) [4]

Pkg.) [5]

G

[6]

gpmc_a1

General-purpose memory

address bit 1

O

N4 / K1

M4 / L1

L4 / L2

K4 / P2

T3 / T1

R3 / V1

N3 / V2

M3 / W2

L3 / H2

K3 / K2

P1

AC15 / M2

AB15 / M1

AC16 / N2

AB16 / N1

AC17 / R2

AB17 / R1

AC18 / T2

AB18 / T1

J2 / AA2

H1 / AA1

H2 / AC2

G2 / AC1

F1 / AE5

F2 / AD6

E1 / AD5

E2 / AC5

D1 / V1

D2 / Y1

T1

AA13 / U2

AA14 / U1

AA17 / V2

Y17 / V1

AA19 / AA3

AF24 / AA4

Y19 / Y3

W2 / Y4

Y2 / R1

T1

gpmc_a17/

gpmc_d0

gpmc_a2

gpmc_a3

gpmc_a4

gpmc_a5

gpmc_a6

gpmc_a7

gpmc_a8

gpmc_a9

gpmc_a10

gpmc_a11

gpmc_a12

gpmc_a13

gpmc_a14

General-purpose memory

address bit 2

gpmc_a18/

gpmc_d1

General-purpose memory

address bit 3

gpmc_a19/

gpmc_d2

General-purpose memory

address bit 4

gpmc_a20/

gpmc_d3

General-purpose memory

address bit 5

gpmc_a21/

gpmc_d4

General-purpose memory

address bit 6

gpmc_a22/

gpmc_d5

General-purpose memory

address bit 7

gpmc_a23/

gpmc_d6

General-purpose memory

address bit 8

gpmc_a24/

gpmc_d7

General-purpose memory

address bit 9

AC19 /

AB3

gpmc_a25/

gpmc_d8

General-purpose memory

address bit 10

AB19 /

AC3

gpmc_a26/

gpmc_d9

General-purpose memory

address bit 11

AB4

AC4

AB6

AC6

N1

gpmc_d10

gpmc_d11

gpmc_d12

gpmc_d13

General-purpose memory

address bit 12

R1

U2

P2

General-purpose memory

address bit 13

R2

U1

P1

General-purpose memory

address bit 14

T2

P1

M1

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Table 2-5. External Memory Interfaces – GPMC Signals Description (continued)

SIGNAL

NAME [1]

DESCRIPTION [2]

TYPE

[3]

BALL

BOTTOM

(CBB

BALL

TOP

(CBB

BALL BOTTOM

(CBC Pkg.) [4] (CBC Pkg.) [5]

BALL TOP

SUBSYSTEM

MULTIPLEXIN

Pkg.) [4]

Pkg.) [5]

G

[6]

gpmc_a15

gpmc_a16

gpmc_a17

gpmc_a18

gpmc_a19

gpmc_a20

gpmc_a21

gpmc_a22

gpmc_a23

gpmc_a24

gpmc_a25

gpmc_a26

gpmc_d0

gpmc_d1

gpmc_d2

gpmc_d3

gpmc_d4

gpmc_d5

gpmc_d6

gpmc_d7

gpmc_d8

gpmc_d9

gpmc_d10

gpmc_d11

gpmc_d12

gpmc_d13

General-purpose memory

address bit 15

O

W1

Y1

N4

M4

L4

AB7

AC7

AC15

AB15

AC16

AB16

AC17

AB17

AC18

AB18

AC19

AB19

M2

L2

M2

J2

K2

gpmc_d14

gpmc_d15

gpmc_a1

gpmc_a2

gpmc_a3

gpmc_a4

gpmc_a5

gpmc_a6

gpmc_a7

gpmc_a8

gpmc_a9

gpmc_a10

General-purpose memory

address bit 16

General-purpose memory

address bit 17

O

AA13

AA14

AA17

Y17

AA19

AF24

Y19

W2

Y2

General-purpose memory

address bit 18

O

H1

General-purpose memory

address bit 19

O

H2

General-purpose memory

address bit 20

O

K4

T3

R3

N3

M3

L3

G2

F1

General-purpose memory

address bit 21

O

General-purpose memory

address bit 22

O

F2

General-purpose memory

address bit 23

O

E1

General-purpose memory

address bit 24

O

E2

General-purpose memory

address bit 25

O

D1

General-purpose memory

address bit 26

O

K3

K1

L1

D2

-

GPMC Data bit 0

GPMC Data bit 1

GPMC Data bit 2

GPMC Data bit 3

GPMC Data bit 4

GPMC Data bit 5

GPMC Data bit 6

GPMC Data bit 7

GPMC Data bit 8

GPMC Data bit 9

GPMC Data bit 10

GPMC Data bit 11

GPMC Data bit 12

GPMC Data bit 13

IO

AA1

AC2

AC1

AE5

AD6

AD5

AC5

V1

U2

gpmc_a1/

gpmc_d0

M1

U1

gpmc_a2/

gpmc_d1

L2

N2

V2

gpmc_a3/

gpmc_d2

P2

T1

V1

V2

W2

H2

K2

P1

R1

R2

T2

N1

V1

gpmc_a4/

gpmc_d3

R2

AA3

AA4

Y3

gpmc_a5/

gpmc_d4

R1

gpmc_a6/

gpmc_d5

T2

gpmc_a7

/gpmc_d6

T1

Y4

gpmc_a8/

gpmc_d7

AB3

AC3

AB4

AC4

AB6

AC6

R1

gpmc_a9/

gpmc_d8

Y1

T1

gpmc_a10/

gpmc_d9

T1

N1

gpmc_a11/

gpmc_d10

U2

P2

gpmc_a12/

gpmc_d11

U1

P1

gpmc_a13/

gpmc_d12

P1

M1

gpmc_a14/

gpmc_d13

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Table 2-5. External Memory Interfaces – GPMC Signals Description (continued)

SIGNAL

NAME [1]

DESCRIPTION [2]

TYPE

[3]

BALL

BOTTOM

(CBB

BALL

TOP

(CBB

BALL BOTTOM

(CBC Pkg.) [4] (CBC Pkg.) [5]

BALL TOP

SUBSYSTEM

MULTIPLEXIN

Pkg.) [4]

Pkg.) [5]

G

[6]

gpmc_d14

gpmc_d15

GPMC Data bit 14

IO

W1

Y1

AB7

AC7

L2

J2

gpmc_a15/

gpmc_d14

GPMC Data bit 15

M2

K2

gpmc_a16/

gpmc_d15

gpmc_ncs0

gpmc_ncs1

gpmc_ncs2

gpmc_ncs3

gpmc_ncs4

gpmc_ncs5

gpmc_ncs6

gpmc_ncs7

gpmc_io_dir

GPMC Chip Select bit 0

GPMC Chip Select bit 1

GPMC Chip Select bit 2

GPMC Chip Select bit 3

GPMC Chip Select bit 4

GPMC Chip Select bit 5

GPMC Chip Select bit 6

GPMC Chip Select bit 7

O

G4

H3

V8

U8

T8

R8

P8

N8

Y2

Y1

AD8

AD1

A3

AA8

-

W1

NA

-

B6

B4

C4

B5

C5

GPMC IO direction control for

use with external transceivers

gpmc_clk

GPMC clock

O

T4

F3

W2

W1

N1

L1

-

gpmc_nadv_al Address Valid or Address Latch

AD10

AA9

e

Enable

gpmc_noe

gpmc_nwe

Output Enable

Write Enable

O

G2

F4

G3

V2

V1

N2

M1

K2

L2

K1

-

gpmc_nbe0_cl Lower Byte Enable. Also used for

AC12

e

Command Latch Enable

gpmc_nbe1

gpmc_nwp

gpmc_wait0

gpmc_wait1

gpmc_wait2

gpmc_wait3

Upper Byte Enable

O

I

U3

H1

M8

L8

NA

AB10

AB12

AC10

NA

J1

AC6

AC11

AC8

B3

-

Y5

Y10

Y8

-

Flash Write Protect

External indication of wait

I

K8

J8

I

NA

C6

-

Table 2-6. External Memory Interfaces – SDRC Signals Description

SIGNAL

NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM BALL TOP

BALL BOTTOM

(CBC Pkg.)

BALL TOP

(CBC Pkg.)

(CBB Pkg.)

sdrc_d0

sdrc_d1

sdrc_d2

sdrc_d3

sdrc_d4

sdrc_d5

sdrc_d6

sdrc_d7

sdrc_d8

sdrc_d9

sdrc_d10

sdrc_d11

sdrc_d12

sdrc_d13

SDRAM data bit 0

SDRAM data bit 1

SDRAM data bit 2

SDRAM data bit 3

SDRAM data bit 4

SDRAM data bit 5

SDRAM data bit 6

SDRAM data bit 7

SDRAM data bit 8

SDRAM data bit 9

SDRAM data bit 10

SDRAM data bit 11

SDRAM data bit 12

SDRAM data bit 13

IO

D6

J2

-

D1

G1

C6

J1

B6

G2

C8

G1

E1

C9

F2

D2

A7

F1

E2

B9

D2

B3

A9

D1

B4

C14

B14

C15

B16

D17

C17

B13

A13

B14

A14

B16

A16

A10

B11

A11

B12

A16

A17

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog).

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Table 2-6. External Memory Interfaces – SDRC Signals Description (continued)

SIGNAL

NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM BALL TOP

BALL BOTTOM

(CBC Pkg.)

BALL TOP

(CBC Pkg.)

(CBB Pkg.)

B17

D18

D11

B10

C11

D12

C12

A11

B13

D14

C18

A19

B19

B20

D20

A21

B21

C21

H9

(CBB Pkg.)

B19

A19

B3

sdrc_d14

sdrc_d15

sdrc_d16

sdrc_d17

sdrc_d18

sdrc_d19

sdrc_d20

sdrc_d21

sdrc_d22

sdrc_d23

sdrc_d24

sdrc_d25

sdrc_d26

sdrc_d27

sdrc_d28

sdrc_d29

sdrc_d30

sdrc_d31

sdrc_ba0

sdrc_ba1

sdrc_a0

SDRAM data bit 14

SDRAM data bit 15

SDRAM data bit 16

SDRAM data bit 17

SDRAM data bit 18

SDRAM data bit 19

SDRAM data bit 20

SDRAM data bit 21

SDRAM data bit 22

SDRAM data bit 23

SDRAM data bit 24

SDRAM data bit 25

SDRAM data bit 26

SDRAM data bit 27

SDRAM data bit 28

SDRAM data bit 29

SDRAM data bit 30

SDRAM data bit 31

SDRAM bank select 0

SDRAM bank select 1

SDRAM address bit 0

SDRAM address bit 1

SDRAM address bit 2

SDRAM address bit 3

SDRAM address bit 4

SDRAM address bit 5

SDRAM address bit 6

SDRAM address bit 7

SDRAM address bit 8

SDRAM address bit 9

SDRAM address bit 10

SDRAM address bit 11

SDRAM address bit 12

SDRAM address bit 13

SDRAM address bit 14

Chip select 0

IO

O

-

–

-

B17

B18

B7

A3

A5

B5

B6

A5

A6

B8

A8

B9

A9

B10

C21

D20

B19

C20

D21

E20

E21

G21

AA18

V20

G20

K20

J20

J21

U21

R20

M21

M20

N20

K21

Y16

N21

R21

AA15

Y12

T21

T20

A12

B13

Y15

Y13

V21

U20

B21

A21

D22

D23

E22

E23

G22

G23

AB21

AC21

N22

N23

P22

P23

R22

R23

T22

T23

U22

U23

V22

V23

W22

W23

Y22

M22

M23

A11

B11

J22

O

H10

A4

O

sdrc_a1

O

B4

sdrc_a2

O

B3

sdrc_a3

O

C5

sdrc_a4

O

C4

sdrc_a5

O

D5

sdrc_a6

O

C3

sdrc_a7

O

C2

sdrc_a8

O

C1

sdrc_a9

O

D4

sdrc_a10

sdrc_a11

sdrc_a12

sdrc_a13

sdrc_a14

sdrc_ncs0

sdrc_ncs1

sdrc_clk

O

D3

O

D2

O

D1

O

E2

O

E1

O

H11

H12

A13

A14

H16

H17

H14

H13

Chip select 1

O

Clock

IO

O

sdrc_nclk

sdrc_cke0

sdrc_cke1

sdrc_nras

sdrc_ncas

Clock Invert

Clock Enable 0

O

Clock Enable 1

O

J23

SDRAM Row Access

O

L23

L22

SDRAM column address

strobe

O

sdrc_nwe

sdrc_dm0

sdrc_dm1

SDRAM write enable

Data Mask 0

O

H15

B7

K23

C1

-

Y18

H1

Data Mask 1

A16

A17

A14

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Table 2-6. External Memory Interfaces – SDRC Signals Description (continued)

SIGNAL

NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM BALL TOP

BALL BOTTOM

(CBC Pkg.)

BALL TOP

(CBC Pkg.)

(CBB Pkg.)

sdrc_dm2

sdrc_dm3

sdrc_dqs0

sdrc_dqs1

sdrc_dqs2

sdrc_dqs3

Data Mask 2

O

B11

A6

A20

C2

-

A4

A18

C2

Data Mask 3

Data Strobe 0

Data Strobe 1

Data Strobe 2

Data Strobe 3

C20

IO

A6

A17

B17

B6

B15

B8

A10

A20

B20

A19

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2.4.2 Video Interfaces

Table 2-7. Video Interfaces – CAM Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

cam_hs

Camera Horizontal Synchronization

Camera Vertical Synchronization

Camera Clock Output a

IO

O

I

A24

A23

C23

D23

cam_vs

cam_xclka

cam_xclkb

cam_d0

C25

Camera Clock Output b

B26

E25

Camera digital image data bit 0

Camera digital image data bit 1

Camera digital image data bit 2

Camera digital image data bit 3

Camera digital image data bit 4

Camera digital image data bit 5

Camera digital image data bit 6

Camera digital image data bit 7

Camera digital image data bit 8

Camera digital image data bit 9

Camera digital image data bit 10

Camera digital image data bit 11

Camera field identification

AG17

AH17

B24

AE16

AE15

A24

cam_d1

I

cam_d2

I

cam_d3

I

C24

B24

cam_d4

I

D24

cam_d5

I

A25

C24

cam_d6

I

K28

P25

cam_d7

I

L28

P26

cam_d8

I

K27

N25

cam_d9

I

L27

N26

cam_d10

cam_d11

cam_fld

I

B25

D25

I

C26

E26

IO

I

C23

B23

cam_pclk

cam_wen

cam_strobe

cam_global_reset

Camera pixel clock

C27

C26

Camera Write Enable

I

B23

A23

Flash strobe control signal

O

IO

D25

D26

Global reset is used strobe

synchronization

C23 / AH3 / AA21

V17 / B23

cam_shutter

Mechanical shutter control signal

O

B23 / AF3 / T21

A23 / T19

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog).

Table 2-8. Video Interfaces – DSS Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

dss_pclk

LCD Pixel Clock

O

D28

D26

G25

K24

dss_hsync

dss_vsync

dss_acbias

dss_data0

dss_data1

dss_data2

dss_data3

dss_data4

dss_data5

dss_data6

dss_data7

dss_data8

dss_data9

dss_data10

dss_data11

LCD Horizontal Synchronization

LCD Vertical Synchronization

AC bias control (STN) or pixel data enable (TFT) output

LCD Pixel Data bit 0

O

D27

M25

O

E27

F26

IO

AG22 / H26

AH22 / H25

AG23 / E28

AH23 / J26

AG24 / AC27

AH24 / AC28

E26

AE21 / M24

AE22 / M26

AE23 / F25

AE24 / N24

AD23 / AC25

AD24/ AB25

G26

LCD Pixel Data bit 1

LCD Pixel Data bit 2

LCD Pixel Data bit 3

LCD Pixel Data bit 4

LCD Pixel Data bit 5

LCD Pixel Data bit 6

LCD Pixel Data bit 7

F28

H25

LCD Pixel Data bit 8

F27

H26

LCD Pixel Data bit 9

G26

J26

LCD Pixel Data bit 10

AD28

AC26

LCD Pixel Data bit 11

AD27

AD26

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog).

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Table 2-8. Video Interfaces – DSS Signals Description (continued)

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

AA25

Y25

dss_data12

dss_data13

dss_data14

dss_data15

dss_data16

dss_data17

dss_data18

dss_data19

dss_data20

dss_data21

dss_data22

dss_data23

LCD Pixel Data bit 12

LCD Pixel Data bit 13

LCD Pixel Data bit 14

LCD Pixel Data bit 15

LCD Pixel Data bit 16

LCD Pixel Data bit 17

LCD Pixel Data bit 18

LCD Pixel Data bit 19

LCD Pixel Data bit 20

LCD Pixel Data bit 21

LCD Pixel Data bit 22

LCD Pixel Data bit 23

IO

O

AB28

AB27

AA28

AA27

G25

AA26

AB26

L25

H27

L26

H26

M24

H25

M26

E28

F25

O

J26

N24

O

AC27

AC28

AC25

AB25

O

Table 2-9. Video Interfaces – RFBI Signals Description

SIGNAL

NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

SUBSYSTEM PIN

MULTIPLEXING⁽²⁾

rfbi_a0

RFBI command/data control

1st LCD chip select

RFBI data bus 0

O

E27

D26

F26

K24

dss_acbias

dss_hsync

dss_data0

dss_data1

dss_data2

dss_data3

dss_data4

dss_data5

dss_data6

dss_data7

dss_data8

dss_data9

dss_data10

dss_data11

dss_data12

dss_data13

dss_data14

dss_data15

dss_pclk

rfbi_cs0

rfbi_da0

rfbi_da1

rfbi_da2

rfbi_da3

rfbi_da4

rfbi_da5

rfbi_da6

rfbi_da7

rfbi_da8

rfbi_da9

rfbi_da10

rfbi_da11

rfbi_da12

rfbi_da13

rfbi_da14

rfbi_da15

rfbi_rd

IO

O

AG22

AH22

AG23

AH23

AG24

AH24

E26

AE21

AE22

AE23

AE24

AD23

AD24

G26

RFBI data bus 1

RFBI data bus 2

RFBI data bus 3

RFBI data bus 4

RFBI data bus 5

RFBI data bus 6

RFBI data bus 7

F28

H25

RFBI data bus 8

F27

H26

RFBI data bus 9

G26

J26

RFBI data bus 10

RFBI data bus 11

RFBI data bus 12

RFBI data bus 13

RFBI data bus 14

RFBI data bus 15

Read enable for RFBI

Write Enable for RFBI

AD28

AD27

AB28

AB27

AA28

AA27

D28

AC26

AD26

AA25

Y25

AA26

AB26

G25

rfbi_wr

O

D27

M25

dss_vsync

dss_data16

rfbi_te_vsync0 tearing effect removal and Vsync input

from 1st LCD

I

G25

L25

rfbi_hsync0

Hsync for 1st LCD

I

H27

L26

dss_data17

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog).

(2) The subsystem pin multiplexing options are not described in Table 2-1 and Table 2-3

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Table 2-10. Video Interfaces – TV Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

tv_out1

tv_out2

tv_vfb1

TV analog output Composite: tv_out1

TV analog output S-VIDEO: tv_out2

O

Y28

W28

Y27

W26

V26

tv_vfb1: Feedback through external

AO

W25

resistor＝to composite

tv_vfb2

tv_vref

tv_vfb2: Feedback through external

resistor＝to S-VIDEO

AO

W27

W26

U24

V23

External capacitor

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog).

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2.4.3 Serial Communication Interfaces

Table 2-11. Serial Communication Interfaces – HDQ/1-Wire Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

hdq_sio

Bidirectional HDQ 1-Wire control and data

Interface. Output is open drain.

IOD

J25

J23

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog).

Table 2-12. Serial Communication Interfaces – I²C Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

INTER-INTEGRATED CIRCUIT INTERFACE (I2C1)

i2c1_scl

I²C Master Serial clock. Output is open

drain.

I²C Serial Bidirectional Data. Output is open

drain.

IOD

K21

J21

J25

J24

i2c1_sda

INTER-INTEGRATED CIRCUIT INTERFACE (I2C3)

i2c3_scl

I²C Master Serial clock. Output is open

drain.

I²C Serial Bidirectional Data. Output is open

drain.

IOD

O

AF14

AG14

J25

C2

C1

i2c3_sda

i2c3_sccbe

Serial Camera Control Bus Enable

J23

INTER-INTEGRATED CIRCUIT INTERFACE (I2C2)

i2c2_scl

I²C Master Serial clock. Output is open

drain.

I²C Serial Bidirectional Data. Output is open

drain.

IOD

O

AF15

AE15

J25

AB4

AC4

J23

i2c2_sda

i2c2_sccbe

Serial Camera Control Bus Enable

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog).

Table 2-13. Serial Communication Interfaces – SmartReflex Signals Description⁽¹⁾

SIGNAL NAME

DESCRIPTION

TYPE⁽²⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

INTER-INTEGRATED CIRCUIT INTERFACE (I2C4)

i2c4_scl

I²C Master Serial clock. Output is open

drain.

I²C Serial Bidirectional Data. Output is open

drain.

IOD

AD26

AE26

AD15

W16

i2c4_sda

(1) For more information on SmartReflex voltage control, see the PRCM chapter of the OMAP35x Technical Reference Manual (TRM)

[literature number SPRUFA5].

(2) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog).

Table 2-14. Serial Communication Interfaces – McBSP LP Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

MULTICHANNEL SERIAL (McBSP LP 1)

mcbsp1_dr

mcbsp1_clkr

mcbsp1_fsr

mcbsp1_dx

mcbsp1_clkx

Received serial data

Receive Clock

I

U21

Y8 / Y21

AA21

V21

T20

U19 / H3

V17

IO

Receive frame synchronization

Transmitted serial data

Transmit clock

U17

W21

T17

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

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Table 2-14. Serial Communication Interfaces – McBSP LP Signals Description (continued)

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

mcbsp1_fsx

mcbsp_clks

Transmit frame synchronization

IO

I

K26

T21

P20

T19

External clock input (shared by McBSP1, 2,

3, 4, and 5)

MULTICHANNEL SERIAL (McBSP LP 2)

mcbsp2_dr

mcbsp2_dx

mcbsp2_clkx

mcbsp2_fsx

Received serial data

I

R21

M21

N21

P21

T18

R19

R18

U18

Transmitted serial data

Combined serial clock

IO

Combined frame synchronization

MULTICHANNEL SERIAL (McBSP LP 3)

mcbsp3_dr

mcbsp3_dx

mcbsp3_clkx

mcbsp3_fsx

Received serial data

I

AE6 / AB25 / U21

AF6 / AB26 / V21

AF5 / AA25 / W21

AE5 / AD25 / K26

T20 / AA24 / N3

U17 / Y24 / P3

T17 / AD22 / U3

P20 / AD21 / W3

Transmitted serial data

Combined serial clock

IO

Combined frame synchronization

MULTICHANNEL SERIAL (McBSP LP 4)

mcbsp4_dr

mcbsp4_dx

mcbsp4_clkx

mcbsp4_fsx

Received serial data

I

R8 / AD1

P8 / AD2

T8 / AE1

N8 / AC1

C4 / U4

B5 / R3

B4 / V3

C5 / T3

Transmitted serial data

Combined serial clock

IO

Combined frame synchronization

MULTICHANNEL SERIAL (McBSP LP 5)

mcbsp5_dr

mcbsp5_dx

mcbsp5_clkx

mcbsp5_fsx

Received serial data

I

AE11

AF13

AF10

AH9

Y3

Transmitted serial data

Combined serial clock

IO

AE3

AB2

AB1

Combined frame synchronization

Table 2-15. Serial Communication Interfaces – McSPI Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

MULTICHANNEL SERIAL PORT INTERFACE (McSPI1)

mcspi1_clk

SPI Clock

IO

AB3

AB4

AA4

AC2

P9

P8

P7

R7

mcspi1_simo

mcspi1_somi

mcspi1_cs0

Slave data in, master data out

Slave data out, master data in

SPI Enable 0, polarity configured by

software

mcspi1_cs1

mcspi1_cs2

mcspi1_cs3

SPI Enable 1, polarity configured by

software

O

AC3

AB1

AB2

R8

R9

T8

SPI Enable 2, polarity configured by

software

SPI Enable 3, polarity configured by

software

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

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Table 2-15. Serial Communication Interfaces – McSPI Signals Description (continued)

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

MULTICHANNEL SERIAL PORT INTERFACE (McSPI2)

mcspi2_clk

SPI Clock

IO

AA3

Y2

W7

W8

U8

V8

mcspi2_simo

mcspi2_somi

mcspi2_cs0

Slave data in, master data out

Slave data out, master data in

Y3

SPI Enable 0, polarity configured by

software

Y4

mcspi2_cs1

SPI Enable 1, polarity configured by

software

O

V3

V9

MULTICHANNEL SERIAL PORT INTERFACE (McSPI3)

mcspi3_clk

SPI Clock

IO

H26 / AE2 / AE13

H25 / AG5 / AF11

E28 / AH5 / AG12

J26 / AF4 / AH12

W10 / M24 / AA3

R10 / M26 / AC3

F25 / T10 / AD4

U9 / N24 / AD3

mcspi3_simo

mcspi3_somi

mcspi3_cs0

Slave data in, master data out

Slave data out, master data in

SPI Enable 0, polarity configured by

software

mcspi3_cs1

SPI Enable 1, polarity configured by

software

O

AC27 / AG4 / AH14

AC25 / U10 / AD2

MULTICHANNEL SERIAL PORT INTERFACE (McSPI4)

mcspi4_clk

SPI Clock

IO

Y8 / Y21

V21

U19 / H3

U17

mcspi4_simo

mcspi4_somi

mcspi4_cs0

Slave data in, master data out

Slave data out, master data in

U21

T20

SPI Enable 0, polarity configured by

software

K26

P20

Table 2-16. Serial Communication Interfaces – UARTs Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART1)

uart1_cts

uart1_rts

uart1_rx

uart1_tx

UART1 Clear To Send

UART1 Request To Send

UART1 Receive data

UART1 Transmit data

I

AG22 / W8 / T21

AH22 / AA9

AE21 / T19 / W2

AE22 / R2

O

I

F28 / Y8 / AE7

E26 / AA8

H3 / H25 / AE4

L4 / G26

O

UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART2)

uart2_cts

uart2_rts

uart2_rx

uart2_tx

UART2 Clear To Send

UART2 Request To Send

UART2 Receive data

UART2 Transmit data

I

AF6 / AB26

AE6 / AB25

AE5 / AD25

AF5 / AA25

Y24

O

I

AA24

AD21

AD22

O

UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART3) / IrDA

uart3_cts_rctx

UART3 Clear To Send (input), Remote

TX (output)

IO

H18 / U26

W20 / F23

uart3_rts_sd

uart3_rx_irrx

UART3 Request To Send, IR enable

O

I

H19 / U27

V18 / F24

UART3 Receive data, IR and Remote

RX

AG24 / H20 / U28

AD23 / Y20 / H24

uart3_tx_irtx

UART3 Transmit data, IR TX

O

AH24 / H21 / T27

AD24 / V20 / G24

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

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Table 2-17. Serial Communication Interfaces – USB Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

HIGH-SPEED UNIVERSAL SERIAL BUS INTERFACE (HSUSB0)

hsusb0_clk

Dedicated for external transceiver 60-MHz clock input from

PHY

I

T28

W19

hsusb0_stp

hsusb0_dir

Dedicated for external transceiver Stop signal

O

I

T25

R28

U20

V19

Dedicated for external transceiver Data direction control from

PHY

hsusb0_nxt

Dedicated for external transceiver Next signal from PHY

Dedicated for external transceiver Bidirectional data bus

I

T26

T27

U28

U27

U26

U25

W18

V20

Y20

V18

W20

W17

hsusb0_data0

hsusb0_data1

hsusb0_data2

hsusb0_data3

hsusb0_data4

IO

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

hsusb0_data5

hsusb0_data6

hsusb0_data7

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

IO

V28

V27

V26

Y18

Y19

Y17

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

MM_FSUSB3

mm3_rxdm

mm3_rxdp

Vminus receive data (not used in 3- or 4-pin configurations)

Vplus receive data (not used in 3- or 4-pin configurations)

Differential receiver signal input (not used in 3-pin mode)

Single-ended zero. Used as VM in 4-pin VP_VM mode.

USB data. Used as VP in 4-pin VP_VM mode.

Transmit enable

IO

AE3

AH3

AD1

AE1

AD2

AC1

AE3

M3

U4

V3

mm3_rxrcv

mm3_txse0

mm3_txdat

mm3_txen_n

MM_FSUSB2

mm2_rxdm

mm2_rxdp

R3

T3

Vminus receive data (not used in 3- or 4-pin configurations)

Vplus receive data (not used in 3- or 4-pin configurations)

Differential receiver signal input (not used in 3-pin mode)

Single-ended zero. Used as VM in 4-pin VP_VM mode.

USB data. Used as VP in 4-pin VP_VM mode.

Transmit enable

IO

AH7

AF7

AG8

AH8

AB2

V3

AF7

AF6

AF9

AE9

T8

mm2_rxrcv

mm2_txse0

mm2_txdat

mm2_txen_n

MM_FSUSB1

mm1_rxdm

mm1_rxdp

V9

Vminus receive data (not used in 3- or 4-pin configurations)

Vplus receive data (not used in 3- or 4-pin configurations)

Differential receiver signal input (not used in 3-pin mode)

Single-ended zero. Used as VM in 4-pin VP_VM mode.

USB data. Used as VP in 4-pin VP_VM mode.

Transmit enable

IO

AG9

AF10

AF11

AG12

AH12

AH14

V2

AB2

AC3

AD4

AD3

AD2

mm1_rxrcv

mm1_txse0

mm1_txdat

mm1_txen_n

HSUSB3_TLL

hsusb3_tll_clk

Dedicated for external transceiver 60-MHz clock input from

PHY

O

W8

W2

hsusb3_tll_stp

hsusb3_tll_dir

Dedicated for external transceiver Stop signal

I

AH3

AF3

M3

L3

dedicated for external transceiver Data direction control from

PHY

O

hsusb3_tll_nxt

Dedicated for external transceiver Next signal from PHY

Dedicated for external transceiver Bidirectional data bus

O

AE3

AD1

K3

U4

hsusb3_tll_data0

IO

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

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Table 2-17. Serial Communication Interfaces – USB Signals Description (continued)

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

hsusb3_tll_data1

hsusb3_tll_data2

hsusb3_tll_data3

hsusb3_tll_data4

hsusb3_tll_data5

hsusb3_tll_data6

hsusb3_tll_data7

HSUSB2

Dedicated for external transceiver Bidirectional data bus

IO

AE1

AD2

AC1

AF6

AE6

AF5

AE5

V3

R3

T3

P3

N3

U3

W3

hsusb2_clk

Dedicated for external transceiver 60-MHz clock input from

PHY

O

AE7

AE4

hsusb2_stp

hsusb2_dir

Dedicated for external transceiver Stop signal

O

I

AF7

AG7

AF6

AE6

Dedicated for external transceiver Data direction control from

PHY

hsusb2_nxt

Dedicated for external transceiver Next signal from PHY

Dedicated for external transceiver Bidirectional data bus

I

AH7

AG8

AH8

AB2

V3

AF7

AF9

AE9

T8

hsusb2_data0

hsusb2_data1

hsusb2_data2

hsusb2_data3

hsusb2_data4

IO

V9

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

Y2

W8

hsusb2_data5

hsusb2_data6

hsusb2_data7

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

IO

Y3

Y4

U8

V8

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

AA3

W7

HSUSB2_TLL

hsusb2_tll_clk

Dedicated for external transceiver 60-MHz clock input from

PHY

O

AE7

AE4

hsusb2_tll_stp

hsusb2_tll_dir

Dedicated for external transceiver Stop signal

I

AF7

AG7

AF6

AE6

Dedicated for external transceiver data direction control from

PHY

O

hsusb2_tll_nxt

Dedicated for external transceiver Next signal from PHY

Dedicated for external transceiver Bidirectional data bus

O

AH7

AG8

AH8

AB2

V3

AF7

AF9

AE9

T8

hsusb2_tll_data0

hsusb2_tll_data1

hsusb2_tll_data2

hsusb2_tll_data3

hsusb2_tll_data4

IO

V9

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

Y2

W8

hsusb2_tll_data5

hsusb2_tll_data6

hsusb2_tll_data7

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

IO

Y3

Y4

U8

V8

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

AA3

W7

HSUSB1

hsusb1_clk

Dedicated for external transceiver 60-MHz clock input from

PHY

O

AE10

AB3

hsusb1_stp

hsusb1_dir

Dedicated for external transceiver Stop signal

O

I

AF10

AF9

AB2

AA4

Dedicated for external transceiver data direction control from

PHY

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Table 2-17. Serial Communication Interfaces – USB Signals Description (continued)

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

hsusb1_nxt

Dedicated for external transceiver Next signal from PHY

Dedicated for external transceiver Bidirectional data bus

I

AG9

AF11

AG12

AH12

AH14

AE11

V2

hsusb1_data0

hsusb1_data1

hsusb1_data2

hsusb1_data3

hsusb1_data4

IO

AC3

AD4

AD3

AD2

Y3

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

hsusb1_data5

hsusb1_data6

hsusb1_data7

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

IO

AH9

AF13

AE13

AB1

AE3

AA7

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

HSUSB1_TLL

hsusb1_tll_clk

Dedicated for external transceiver 60-MHz clock input from

PHY

O

AE10

AB3

hsusb1_tll_stp

hsusb1_tll_dir

Dedicated for external transceiver Stop signal

I

AF10

AF9

AB2

AA4

Dedicated for external transceiver data direction control from

PHY

O

hsusb1_tll_nxt

Dedicated for external transceiver Next signal from PHY

Dedicated for external transceiver Bidirectional data bus

O

AG9

AF11

AG12

AH12

AH14

AE11

V2

hsusb1_tll_data0

hsusb1_tll_data1

hsusb1_tll_data2

hsusb1_tll_data3

hsusb1_tll_data4

IO

AC3

AD4

AD3

AD2

Y3

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

hsusb1_tll_data5

hsusb1_tll_data6

hsusb1_tll_data7

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

IO

AH9

AF13

AE13

AB1

AE3

AA3

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

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2.4.4 Removable Media Interfaces

Table 2-18. Removable Media Interfaces – MMC/SDIO Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

MULTIMEDIA MEMORY CARD (MMC1) / SECURE DIGITAL IO (SDIO1)

mmc1_clk

MMC/SD Output Clock

O

N28

M27

N27

N26

N25

P28

P27

P26

R27

R25

N19

L18

mmc1_cmd

mmc1_dat0

mmc1_dat1

mmc1_dat2

mmc1_dat3

mmc1_dat4

mmc1_dat5

mmc1_dat6

mmc1_dat7

MMC/SD command signal

MMC/SD Card Data bit 0 / SPI Serial Input

MMC/SD Card Data bit 1

MMC/SD Card Data bit 2

MMC/SD Card Data bit 3

MMC/SD Card Data bit 4

MMC/SD Card Data bit 5

MMC/SD Card Data bit 6

MMC/SD Card Data bit 7

IO

M19

M18

K18

N20

M20

P17

P18

P19

MULTIMEDIA MEMORY CARD (MMC2) / SECURE DIGITAL IO (SDIO2)

mmc2_clk

MMC/SD Output Clock

O

AE2

AE4

W10

V10

mmc2_dir_dat0

Direction control for DAT0 signal case an external

transceiver used

mmc2_dir_dat1

mmc2_dir_dat2

mmc2_dir_dat3

Direction control for DAT1 and DAT3 signals case an

external transceiver used

O

AH3

AF19

AE21

M3

E4

G3

Direction control for DAT2 signal case an external

transceiver used

Direction control for DAT4, DAT5, DAT6, and DAT7 signals

case an external transceiver used

mmc2_clkin

mmc2_dat0

mmc2_dat1

mmc2_dat2

mmc2_dat3

mmc2_dat4

mmc2_dat5

mmc2_dat6

mmc2_dat7

mmc2_dir_cmd

MMC/SD input Clock

I

AE3

AH5

K3

T10

T9

MMC/SD Card Data bit 0

MMC/SD Card Data bit 1

MMC/SD Card Data bit 2

MMC/SD Card Data bit 3

MMC/SD Card Data bit 4

MMC/SD Card Data bit 5

MMC/SD Card Data bit 6

MMC/SD Card Data bit 7

IO

O

AH4

AG4

U10

U9

AF4

AE4 / AB3

AH3 / AB4

AF3 / AA4

AE3 / AC2

AF3

P9 / V10

P8

P7

R7

Direction control for CMD signal case an external

transceiver is used

L3

mmc2_cmd

MMC/SD command signal

IO

AG5

R10

MULTIMEDIA MEMORY CARD (MMC3) / SECURE DIGITAL IO (SDIO3)

mmc3_clk

MMC/SD Output Clock

O

AB1 / AF10

AC3 / AE10

AE4 / AE11

AH3 / AH9

AF3 / AF13

AE3 / AE13

AF11

R9 / AB2

R8 / AB3

V10 / Y3

AB1

mmc3_cmd

mmc3_dat0

mmc3_dat1

mmc3_dat2

mmc3_dat3

mmc3_dat4

mmc3_dat5

mmc3_dat6

mmc3_dat7

MMC/SD command signal

MMC/SD Card Data bit 0 / SPI Serial Input

MMC/SD Card Data bit 1

MMC/SD Card Data bit 2

MMC/SD Card Data bit 3

MMC/SD Card Data bit 4

MMC/SD Card Data bit 5

MMC/SD Card Data bit 6

MMC/SD Card Data bit 7

IO

AE3

AA3

AC3

AG9

V2

AF9

AA4

AH14

AD2

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

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2.4.5 Test Interfaces

Table 2-19. Test Interfaces – ETK Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

etk_ctl

etk_clk

etk_d0

etk_d1

etk_d2

etk_d3

etk_d4

etk_d5

etk_d6

etk_d7

etk_d8

etk_d9

etk_d10

etk_d11

etk_d12

etk_d13

etk_d14

etk_d15

ETK trace ctl

ETK trace clock

ETK data 0

ETK data 1

ETK data 2

ETK data 3

ETK data 4

ETK data 5

ETK data 6

ETK data 7

ETK data 8

ETK data 9

ETK data 10

ETK data 11

ETK data 12

ETK data 13

ETK data 14

ETK data 15

O

AE10

AF10

AF11

AG12

AH12

AE13

AE11

AH9

AB2

AB3

AC3

AD4

AD3

AA3

Y3

AB1

AE3

AD2

AA4

V2

AF13

AH14

AF9

AG9

AE7

AE4

AF6

AE6

AF7

AF9

AE9

AF7

AG7

AH7

AG8

AH8

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

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Table 2-20. Test Interfaces – JTAG Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

jtag_ntrst

jtag_tck

Test Reset

Test Clock

I

AA17

AA13

AA12

AA18

AA20

AA19

AA11

AA10

U15

I

V14

jtag_rtck

ARM Clock Emulation

Test Mode Select

Test Data Input

Test Data Output

Test emulation 0

Test emulation 1

O

IO

I

W13

V15

jtag_tms_tmsc

jtag_tdi

U16

jtag_tdo

O

IO

Y13

jtag_emu0

jtag_emu1

Y15

Y14

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

Table 2-21. Test Interfaces – SDTI Signals Description

SIGNAL

NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

SUBSYSTEM

SIGNAL

MULTIPLEXING⁽²⁾

sdti_clk

sdti_txd0

sdti_txd1

sdti_txd2

sdti_txd3

Serial clock dual edge

O

AF7 / AA11 / AG8

AG7 / AA10 / AA11

AH7 / AA10

AG8

AF6 / Y15 / AF9

AE6 / Y14 / Y15

AF7 / Y14

AF9

etk_d11 / jtag_emu0 /

etk_d14

Serial data out (System Trace

messages)

etk_d12 / jtag_emu1 /

jtag_emu0

Serial data out (System Trace

messages)

etk_d13 / jtag_emu1

Serial data out (System Trace

messages)

etk_d14

Serial data out (System Trace

messages)

AH8

AE9

etk_d15

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

(2) The subsystem pin multiplexing options are not described in Table 2-1 and Table 2-3

Table 2-22. Test Interfaces – HWDBG Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

hw_dbg0

hw_dbg1

hw_dbg2

hw_dbg3

hw_dbg4

hw_dbg5

hw_dbg6

hw_dbg7

hw_dbg8

hw_dbg9

hw_dbg10

hw_dbg11

hw_dbg12

hw_dbg13

hw_dbg14

hw_dbg15

hw_dbg16

hw_dbg17

Debug signal 0

Debug signal 1

Debug signal 2

Debug signal 3

Debug signal 4

Debug signal 5

Debug signal 6

Debug signal 7

Debug signal 8

Debug signal 9

Debug signal 10

Debug signal 11

Debug signal 12

Debug signal 13

Debug signal 14

Debug signal 15

Debug signal 16

Debug signal 17

O

A24 / AF10

A23 / AE10

C27/ AF11

C23 / AG12

B24 / AH12

C24 / AE13

D24 / AE11

A25 / AH9

B25 / AF13

C26 / AH14

B23 / AF9

D25 / AG9

D28 / AE7

D26 / AF7

E26 / AG7

F28 / AH7

F27 / AG8

G26 / AH8

C23/AB2

D23/AB3

C26/AC3

B23/AD4

A24/AD3

B24/AA3

D24/Y3

C24/AB1

D25/AE3

E26/AD2

A23/AA4

D26/V2

G25/AE4

K24/AF6

G26/AE6

H25/AF7

H26/AF9

J26/AE9

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

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2.4.6 Miscellaneous

Table 2-23. Miscellaneous – GP Timer Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

gpt8_pwm_evt

gpt9_pwm_evt

gpt10_pwm_evt

gpt11_pwm_evt

PWM or event for GP

timer 8

IO

N8 / AD25 / V3

T8 / AB26 / Y2

R8 / AB25 / Y3

P8 / AA25 / Y4

C5 / AD21/ V9

B4 / W8 / Y24

C4 / U8 / AA24

B5 / V8 / AD22

PWM or event for GP

timer 9

PWM or event for GP

timer 10

PWM or event for GP

timer 11

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

Table 2-24. Miscellaneous - Reserved Pins

BALL BOTTOM

(CBB Pkg.)

SIGNAL NAME

DESCRIPTION

TYPE

rsv01

Reserved pin. Leave unconnected

NA

AH20

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2.4.7 General-Purpose IOs

Table 2-25. General-Purpose IOs Signals Description⁽¹⁾

SIGNAL NAME

DESCRIPTION

TYPE⁽²⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

V16

W15

F3

gpio_0

gpio_1

General-purpose IO 0

General-purpose IO 1

General-purpose IO 2

General-purpose IO 3

General-purpose IO 4

General-purpose IO 5

General-purpose IO 6

General-purpose IO 7

General-purpose IO 8

General-purpose IO 9

General-purpose IO 10

General-purpose IO 11

General-purpose IO 12

General-purpose IO 13

General-purpose IO 14

General-purpose IO 15

General-purpose IO 16

General-purpose IO 17

General-purpose IO 18

General-purpose IO 19

General-purpose IO 20

General-purpose IO 21

General-purpose IO 22

General-purpose IO 23

General-purpose IO 24

General-purpose IO 25

General-purpose IO 26

General-purpose IO 27

General-purpose IO 28

General-purpose IO 29

General-purpose IO 30

General-purpose IO 31

General-purpose IO 34

General-purpose IO 35

General-purpose IO 36

General-purpose IO 37

General-purpose IO 38

General-purpose IO 39

General-purpose IO 40

General-purpose IO 41

General-purpose IO 42

General-purpose IO 43

General-purpose IO 44

IO

AF26

AF25

AH26

AG26

AE14

AF18

AF19

AE21

AF21

AF22

AG25

AA11

AF10

AE10

AF11

AG12

AH12

AE13

AE11

AH9

AF13

AH14

AF9

gpio_2

gpio_3

D3

gpio_4

C3

gpio_5

E3

gpio_6

E4

gpio_7

G3

gpio_8

D4

gpio_9

V12

AE14

Y15

AB2

AB3

AC3

AD4

AD3

AA3

Y3

gpio_10

gpio_11

gpio_12

gpio_13

gpio_14

gpio_15

gpio_16

gpio_17

gpio_18

gpio_19

gpio_20

gpio_21

gpio_22

gpio_23

gpio_24

gpio_25

gpio_26

gpio_27

gpio_28

gpio_29

gpio_30

gpio_31

gpio_34

gpio_35

gpio_36

gpio_37

gpio_38

gpio_39

gpio_40

gpio_41

gpio_42

gpio_43

gpio_44

AB1

AE3

AA2

AA4

V2

AG9

AE7

AF7

AE4

AF6

AE6

AF7

AF9

AE9

AD7

Y14

J2

AG7

AH7

AG8

AH8

AF24

AA10

N4

M4

H1

L4

H2

K4

G2

T3

F1

R3

F2

N3

E1

M3

E2

L3

D1

K3

D2

H2

V1

(1) NA in table stands for Not Applicable.

(2) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

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Table 2-25. General-Purpose IOs Signals Description (continued)

SIGNAL NAME

DESCRIPTION

TYPE⁽²⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

gpio_45

gpio_46

gpio_47

gpio_48

gpio_49

gpio_50

gpio_51

gpio_52

gpio_53

gpio_54

gpio_55

gpio_56

gpio_57

gpio_58

gpio_59

gpio_60

gpio_61

gpio_62

gpio_63

gpio_64

gpio_65

gpio_66

gpio_67

gpio_68

gpio_69

gpio_70

gpio_71

gpio_72

gpio_73

gpio_74

gpio_75

gpio_76

gpio_77

gpio_78

gpio_79

gpio_80

gpio_81

gpio_82

gpio_83

gpio_84

gpio_85

gpio_86

gpio_87

gpio_88

gpio_89

gpio_90

General-purpose IO 45

General-purpose IO 46

General-purpose IO 47

General-purpose IO 48

General-purpose IO 49

General-purpose IO 50

General-purpose IO 51

General-purpose IO 52

General-purpose IO 53

General-purpose IO 54

General-purpose IO 55

General-purpose IO 56

General-purpose IO 57

General-purpose IO 58

General-purpose IO 59

General-purpose IO 60

General-purpose IO 61

General-purpose IO 62

General-purpose IO 63

General-purpose IO 64

General-purpose IO 65

General-purpose IO 66

General-purpose IO 67

General-purpose IO 68

General-purpose IO 69

General-purpose IO 70

General-purpose IO 71

General-purpose IO 72

General-purpose IO 73

General-purpose IO 74

General-purpose IO 75

General-purpose IO 76

General-purpose IO 77

General-purpose IO 78

General-purpose IO 79

General-purpose IO 80

General-purpose IO 81

General-purpose IO 82

General-purpose IO 83

General-purpose IO 84

General-purpose IO 85

General-purpose IO 86

General-purpose IO 87

General-purpose IO 88

General-purpose IO 89

General-purpose IO 90

IO

K2

P1

Y1

T1

R1

U2

R2

U1

T2

P1

W1

L2

Y1

M2

H3

AD1

A3

V8

U8

B6

T8

B4

R8

C4

P8

B5

N8

C5

T4

N1

G3

K2

U3

J1

H1

AC6

AC8

B3

L8

K8

J8

C6

D28

D26

D27

E27

AG22

AH22

AG23

AH23

AG24

AH24

E26

F28

F27

G26

AD28

AD27

G25

K24

M25

F26

AE21

AE22

AE23

AE24

AD23

AD24

G26

H25

H26

J26

AC26

AD26

AA25

Y25

AA26

AB26

L25

L26

M24

M26

F25

G25

H27

H26

H25

E28

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Table 2-25. General-Purpose IOs Signals Description (continued)

SIGNAL NAME

DESCRIPTION

TYPE⁽²⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

gpio_91

gpio_92

General-purpose IO 91

General-purpose IO 92

General-purpose IO 93

General-purpose IO 94

General-purpose IO 95

General-purpose IO 96

General-purpose IO 97

General-purpose IO 98

General-purpose IO 99

General-purpose IO 100

General-purpose IO 101

General-purpose IO 102

General-purpose IO 103

General-purpose IO 104

General-purpose IO 105

General-purpose IO 106

General-purpose IO 107

General-purpose IO 108

General-purpose IO 109

General-purpose IO 110

General-purpose IO 111

General-purpose IO 112

General-purpose IO 113

General-purpose IO 114

General-purpose IO 115

General-purpose IO 116

General-purpose IO 117

General-purpose IO 118

General-purpose IO 119

General-purpose IO 120

General-purpose IO 121

General-purpose IO 122

General-purpose IO 123

General-purpose IO 124

General-purpose IO 125

General-purpose IO 126

General-purpose IO 127

General-purpose IO 128

General-purpose IO 129

General-purpose IO 130

General-purpose IO 131

General-purpose IO 132

General-purpose IO 133

General-purpose IO 134

General-purpose IO 135

General-purpose IO 136

IO

I

J26

AC27

AC28

A24

N24

AC25

AB25

C23

gpio_93

gpio_94

gpio_95

A23

D23

gpio_96

C25

gpio_97

C27

C26

gpio_98

C23

B23

gpio_99

AG17

AH17

B24

AE16

AE15

A24

gpio_100

gpio_101

gpio_102

gpio_103

gpio_104

gpio_105

gpio_106

gpio_107

gpio_108

gpio_109

gpio_110

gpio_111

gpio_112

gpio_113

gpio_114

gpio_115

gpio_116

gpio_117

gpio_118

gpio_119

gpio_120

gpio_121

gpio_122

gpio_123

gpio_124

gpio_125

gpio_126

gpio_127

gpio_128

gpio_129

gpio_130

gpio_131

gpio_132

gpio_133

gpio_134

gpio_135

gpio_136

I

IO

I

C24

B24

D24

A25

C24

K28

P25

L28

P26

K27

N25

L27

N26

B25

D25

C26

E26

B26

E25

AG19

AH19

AG18

AH18

P21

AD17

AD16

AE18

AE17

U18

I

IO

N21

R18

R21

T18

M21

R19

N28 / T28

M27 / T25

N27 / R28

N26

W19 / N19

U20 / L18

V19 / M19

M18

N25 / T26

P28 / T27

D25 / P27

P26

W18 / K18

V20 / N20

M20 / D26

P17

R27

P18

R25

P19

AE2 / U28

AG5 / U27

AH5

Y20 / W10

V18 / R10

T10

AH4

T9

AG4

U10

AF4

U9

AE4

V10

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Table 2-25. General-Purpose IOs Signals Description (continued)

SIGNAL NAME

DESCRIPTION

TYPE⁽²⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

gpio_137

gpio_138

gpio_139

gpio_140

gpio_141

gpio_142

gpio_143

gpio_144

gpio_145

gpio_146

gpio_147

gpio_148

gpio_149

gpio_150

gpio_151

gpio_152

gpio_153

gpio_154

gpio_155

gpio_156

gpio_157

gpio_158

gpio_159

gpio_160

gpio_161

gpio_162

gpio_163

gpio_164

gpio_165

gpio_166

gpio_167

gpio_168

gpio_169

gpio_170

gpio_171

gpio_172

gpio_173

gpio_174

gpio_175

gpio_176

gpio_177

gpio_178

gpio_179

gpio_180

gpio_181

gpio_182

General-purpose IO 137

General-purpose IO 138

General-purpose IO 139

General-purpose IO 140

General-purpose IO 141

General-purpose IO 142

General-purpose IO 143

General-purpose IO 144

General-purpose IO 145

General-purpose IO 146

General-purpose IO 147

General-purpose IO 148

General-purpose IO 149

General-purpose IO 150

General-purpose IO 151

General-purpose IO 152

General-purpose IO 153

General-purpose IO 154

General-purpose IO 155

General-purpose IO 156

General-purpose IO 157

General-purpose IO 158

General-purpose IO 159

General-purpose IO 160

General-purpose IO 161

General-purpose IO 162

General-purpose IO 163

General-purpose IO 164

General-purpose IO 165

General-purpose IO 166

General-purpose IO 167

General-purpose IO 168

General-purpose IO 169

General-purpose IO 170

General-purpose IO 171

General-purpose IO 172

General-purpose IO 173

General-purpose IO 174

General-purpose IO 175

General-purpose IO 176

General-purpose IO 177

General-purpose IO 178

General-purpose IO 179

General-purpose IO 180

General-purpose IO 181

General-purpose IO 182

IO

AH3

AF3

AE3

AF6

AE6

AF5

AE5

AB26

AB25

AA25

AD25

AA8

AA9

W8

-

Y24

AA24

AD22

AD21

L4

R2

-

Y8

H3

-

AE1

AD1

AD2

AC1

Y21

AA21

V21

U21

T21

K26

W21

H18

H19

H20

H21

B23

AF15

U26

J25

-

U19

V17

U17

T20

T19

P20

T17

F23

F24

H24

G24

A23

C2

W20

J23

P9

P8

P7

R7

R8

R9

T8

AB3

AB4

AA4

AC2

AC3

AB1

AB2

AA3

Y2

W7

W8

U8

V8

V9

Y3

Y4

V3

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Table 2-25. General-Purpose IOs Signals Description (continued)

SIGNAL NAME

DESCRIPTION

TYPE⁽²⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

gpio_183

gpio_184

gpio_185

gpio_186

gpio_188

gpio_189

gpio_190

gpio_191

General-purpose IO 183

General-purpose IO 184

General-purpose IO 185

General-purpose IO 186

General-purpose IO 188

General-purpose IO 189

General-purpose IO 190

General-purpose IO 191

IO

AE15

AF14

AG14

AE22

U25

C1

AB4

AC4

W11

W17

Y18

V28

V27

Y19

V26

Y17

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2.4.8 Power Supplies

Table 2-26. Power Supplies Signals Description⁽¹⁾

SIGNAL NAME

DESCRIPTION

BALL BOTTOM

(CBB Pkg.)

BALL TOP

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL TOP

(CBC Pkg.)

vdd_mpu_iva

ARM/IVA power

domain

Y9 / W9 / T9 / R9 /

M9 / L9 / J9 / Y10 /

U10 / T10 / R10 /

N10 / M10 / L10 /

J10 / Y11 / W11 /

K11 / J11 / W12 /

K13 / Y14 / K14 /

J14 / Y15 / W15 /

J15

NA

H7/ N7/ U7/ V7/ N8/

G9/ L9/ M9/ W9/ Y9/

M10/ P10/ K11/ U11/

V11/ Y11/ G12/ D13/

U13

NA

vdd_core

Core power domain

AC4 / J4 / H4 / D8 /

AE9 / D9 / D15 /

Y16 / AE18 / Y18 /

W18 / K18 / J18 /

AE19 / Y19 / U19 /

T19 / N19 / M19 /

J19 / Y20 / W20 /

V20 / U20 / P20 /

N20 / K20 / J20 /

D22 / D23 / AE24 /

M25 / L25 / E25

NA

M7/ T7/ Y8/ G11/ Y12/

D15/ M17/ G18/ H20/

R20/ AC21

NA

cap_vdd_wkup

Wakeup/EMU/memor

y domains, connect

capacitor

AA15

NA

bg_testout⁽²⁾

vdds_dpll_dll

Used for band gap

test

U4

NA

D6

NA

DLL IO power domain

(1.8 V): internal

connection to

K15

K13

PLL_VDDS, power

supply for 3PLL (1.8

V)

vpp

eFuse programmation

G1

NA

D5

NA

vdda_dac

Video DAC power

plane

V25

vssa_dac

vdds

Video DAC ground

plane

Y26

NA

V24

NA

-

IO power plane

AD3 / AD4 / W4 /

AF8 / AE8 / AF16 /

AE16 / AF23 / AE23

/ F25 / F26 / AG27/

AE27/ AG20/ H28/

AG21

G4/ M4/ T4/ Y4/ L7/

AC7/ D9/ AE10/ C11/

J15/ AC15/ A18/ J18/

AC18/ AD20/ E24/ L24/

T24/ W24/ AC24

vdds_mem

Memory IO power

plane

U1 / J1 / F1 / J2 / F2 AC5 / P1 / H1 / F23

/ R4 / B5 / A5 / AH6 / E1 / C23 / A4 / A7 /

/ B8 / A8 / B12 / A12

/ D16 / C16 / B18 /

A18 / B22 / A22 /

G28 / C28

A10 / A15 / A18

vdds_dpll_per

vdds_wkup_bg

Peripheral DPLLs

power rail

AA16

NA

U14

NA

For wakeup LDO and

VDDA (2 LDOs

AA14

W14

SRAM and BG)

(1) NA = Not Applicable.

(2) For proper device operation, this pin must be left unconnected.

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Table 2-26. Power Supplies Signals Description (continued)

SIGNAL NAME

vss

DESCRIPTION

BALL BOTTOM

(CBB Pkg.)

BALL TOP

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL TOP

(CBC Pkg.)

Ground

AG2 / U2 / B2 / AG3

/ W3 / P3 / J3 / E3 / AB5 / AB14 / AB20 / H4/ N4/ R4/ W4/ AB5/

A3 / P4 / E4 / AG6 / P2 / F22 / E2 / C22 /

H2 / B18 / AC20 /

G1/ K1/ R1/ W1/ B2/

C1/ F1/ H2/ M2/ R2/

Y6/AA7/ Y11/ AA16/

W20/P20/ L21/ H20/

F20/ B14/A13/ A7

A6/ D7/ Y7/AE7/ A8/

G8/ D10/ G10/ L10/

N10/ Y10/ AC10/ C12/

D12/A13/ D14/ AD14/

K15/ Y16/ L17/ N17/

R17/ D18/ D20/G20/

E22/ AB22/ G23/ L23/

T23/ W23/ AF23/ B25/

K25/U25/ AD25

D7 / C7 / V9 / U9 /

P9 / N9 / K9 / W10 /

V10 / P10 / K10 /

D10 / C10 / AF12 /

AE12 / Y12 / K12 /

J12 / Y13 / W13 /

J13 / D13 / C13 /

W14 / K16 / J16 /

Y17 / W17 / K17 /

J17 / W19 / V19 /

R19 / P19 / L19 /

K19 / D19 / C19 /

AF20 / AE20 / T20 /

R20 / M20 / L20 /

D21 / C22 / AC25 /

Y25 / W25 / AC26 /

R26 / L26 / A26 /

G27 / B27/ AA26/

M28/ AG16/ AH21=

B4 / B7 / B10 / B15

vdds_sram

SRAM LDOs

W16

K25

NA

U12

N23

NA

vdds_mmc1

MMC IO power

domain for CMD,

CLK, and DAT(0..3)

pbias_mmc1⁽³⁾

vdds_mmc1a

MMC1 Pbias

NA

N18

P23

NA

Power supply for

MMC DAT [4..7]

P25

(4)

pbias_mmc1a

MMC1a Pbias

NA

V4

NA

K23

N9⁽²⁾

NA

cap_vdd_sram_mp SRAM LDO

u_iva

capacitance for

VDDRAM1

cap_vdd_sram_cor SRAM LDO

L21

NA

K20⁽²⁾

NA

e

capacitance for

VDDRAM2

pop_ddr_vdd_ft

POPed SDRAM

power

A15 / J28 / M1 /

AF28 / AE28

AA23 / Y23 / K1 /

H23 / A12

L1/AF13/AF17/AF18/A J1/AA11/Y14/AA17/B1

20/U26/K26

6/P21/H21

pop_flash_vpp_ft

pop_flash_vdd_ft

POPed flash vpp

AH13

AC11

AF13

AA11

POPed flash power

N1 / AA1 / AF1 /

AH10 / AH15

AC8 / AC13 / AA1 / AF16/AF22/T2/Y2/AF8/ AA14/AA19/N2/T2/Y7/

U1 / L1

AF5

AA6

pop_vss_ft

POPed devices

ground

B15 / J27 / M2 /

M26 / N2 / AA2 /

AF2 / AF27 / AG10 /

AG15

AB8 / AB13 / AA2 /

AA22 / U2 / L2 / K2 /

K22 / H22 / B12

AF15/AF21/AF24

AA13/Y17/Y19

(3) The recommended configuration is pbias_mmc1 = vdds_mmc1.

(4) The recommended configuration is pbias_mmc1a = vdds_mmc1a

90

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2.4.9 System and Miscellaneous Terminals

Table 2-27. System and Miscellaneous Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL

BOTTOM

(CBB Pkg.)

BALL TOP

(CBB Pkg.)

BALL

BOTTOM

(CBC Pkg.)

BALL TOP

(CBC Pkg.)

sys_32k

32-kHz clock input

I

AE25

AE17

NA

AE20

AF19

-

sys_xtalin

Main input clock. Oscillator input or LVCMOS at

19.2, 13, or 12 MHz.

sys_xtalout

sys_altclk

Output of oscillator

O

I

AF17

J25

NA

AF20

J23

-

Alternate clock source selectable for GPTIMERs

(maximum 54 MHz), USB (48 MHz), or

NTSC/PAL (54 MHz)

sys_clkreq

Request from OMAP3525/30 device for system

clock (open source type)

IO

AF25

NA

W15

-

sys_clkout1

sys_clkout2

sys_boot0

Configurable output clock1

Configurable output clock2

Boot configuration mode bit 0

Boot configuration mode bit 1

Boot configuration mode bit 2

Boot configuration mode bit 3

Boot configuration mode bit 4

Boot configuration mode bit 5

Boot configuration mode bit 6

Power On Reset

O

AG25

AE22

AH26

AG26

AE14

AF18

AF19

AE21

AF21

AH25

AF24

AF26

AD26

AE26

AF22

U8

NA

AE14

W11

F3

-

O

I

sys_boot1

I

D3

sys_boot2

I

C3

sys_boot3

I

E3

sys_boot4

I

E4

sys_boot5

I

G3

sys_boot6

I

D4

sys_nrespwron

sys_nreswarm

sys_nirq

V13

AD7

V16

AD15

W16

V12

B6

Warm Boot Reset (open drain output)

External FIQ input

IOD

I

sys_nvmode1

sys_nvmode2

sys_off_mode

sys_ndmareq0

Indicates the voltage mode

O

I

External DMA request 0 (system expansion).

Level (active low) or edge (falling) selectable.

sys_ndmareq1

sys_ndmareq2

sys_ndmareq3

External DMA request 1 (system expansion).

Level (active low) or edge (falling) selectable.

I

T8 / J8

L3 / R8

K3 / P8

AG9

NA

B4 / C6

D1 / C4

D2 / B5

V2

-

External DMA request 2 (system expansion).

Level (active low) or edge (falling) selectable.

External DMA request 3 (system expansion).

Level (active low) or edge (falling) selectable.

I

sys_secure_

indicator

MSECURE transactions indicator

O

sys_drm_

msecure

MSECURE output

AF9

AA4

sys_ipmcsws⁽²⁾Reserved

sys_opmcsws⁽²⁾Reserved

AI

AO

O

B1

NA

B1

A2

-

A1

pop_int0_ft⁽³⁾

pop_int1_ft⁽³⁾

POP dedicated control signal

AG11

AH11

AH16

AB9

AC9

AC14

AF10

AE2

AF14

Y9

POP dedicated control signal

O

W2

AA12

pop_tq_temp_

sense_ft⁽³⁾

NA

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

(2) sys_ipmcsws and sys_opmcsws pins must be left unconnected.

(3) Top feed-through pop_int0_ft, pop_int1_ft are routed as feed-through for loopback to a GPIO to detect the POP OneNAND die event

and respond accordingly. Top pop_tq_temp_sense_ft is routed as feed-through for loopback to a GPIO to monitor the temperature of the

POP DDR. Top pop_reset_rp_ft is typically looped back to sys_nreswarm to reset the flash memories when a warm reset event occurs

on the processor side.

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Table 2-27. System and Miscellaneous Signals Description (continued)

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL

BOTTOM

(CBB Pkg.)

BALL TOP

(CBB Pkg.)

BALL

BOTTOM

(CBC Pkg.)

BALL TOP

(CBC Pkg.)

pop_reset_rp_ft⁽POP dedicated control signal

NA

AG13

AB11

-

AA5

3)

92

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3 ELECTRICAL CHARACTERISTICS

3.1 Power Domains

The OMAP3525 and OMAP3530 devices integrate enhanced features that dynamically adapt energy

consumption according to application needs and performance requirements.

The OMAP3525 and OMAP3530 devices includes an enhanced power-management scheme based on:

•

Nine independent functional voltage domains on chip partitioning

Multiple voltage domains

Voltage scaling support

Enhanced memory retention support

Optimized device off mode

Centralized management of power, reset, and clock

The external power supplies of OMAP3525 and OMAP3530 are:

•

vdd_mpu_iva for the ARM and IVA2.2 processors

vdd_core for macros

vdds for IO macros

vdds_mem for memory macros

vdds_sram for SRAM LDOs

vdds_dpll_dll for DLL IO

vdds_dpll_per for peripheral DPLLs

vdds_wkup_bg for wakeup LDO and VDDA (2 LDOs: SRAM and BandGap)

vdda_dac for video DAC

vdds_mmc1 for MMC IO

vpp for eFuse

The supply voltages are detailed in Table 3-3.

Figure 3-1 illustrates the power domains:

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vdd_mpu_iva

vdds_dpll_dll

DLL/DCDL

BandGap

vdds_wkup_bg

LDO3

1.0 V/1.2 V

LDO

in 1.8 V

out 1.2 V

IVA2

SRAM1

ARRAY

WKUP

cap_vdd_wkup

EMU

BCK

DPLL_IVA

MEM

cap_vdd_sram_mpu_iva

vdds_mem

SRAM 1 LDO

0 V/1.0 V/1.2 V

LDO

in 1.8 V

out 1.2 V

MPU

DPLL_MPU

vdds

vdd_mpu_iva1 domain

vdds_sram

vpp

eFUSE

LDO

in 1.8 V

out 1.2 V

SRAM2

ARRAY

SRAM 2 LDO

0 V/1.0 V/1.2 V

vdd_core

Core

cap_vdd_sram_core

DPLL_CORE

vdds_mmc1

MMC1

vdds_mmc1a

LDO

in 1.8 V

out 1.2 V

LDO

tv_ref

(for capacitor)

HSDIVIDER

Periph1

DPLL4

vdds_dpll_per

vdda_dac

LDO

HSDIVIDER

Dual Video DAC

LDO

in 1.8 V

out 1.2 V

Periph2

DPLL5

vdd_core domain

vss

OMAP Device

vssa_dac

030-003

Figure 3-1. OMAP3525/30 Power Domains

This power domain segmentation switches off (or places in retention state) domains that are unused while

keeping others active. This implementation is based on internal switches that independently control each

power domain.

A power domain regular logic is attached to one of the device V_DDsupplies through a primary domain

switch. When the primary switch is open, most of the logic supply is off, resulting in a low-leakage state of

the domain. Embedded switches are implemented for all power domains except the wake-up domain. This

allows the domain to be powered off, if not being used, to give maximum power savings. For more

information, see the PRCM chapter of the OMAP35x Technical Reference Manual (TRM) [literature

number SPRUFA5].

All domain output signals at the interface between power domains are connected through isolation latch

cells. These cells ensure a proper electrical isolation between the domains and an appropriate interface

state at the domain boundaries.

94

ELECTRICAL CHARACTERISTICS

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3.2 Absolute Maximum Ratings

The following table specifies the absolute maximum ratings over the operating junction temperature range

of OMAP commercial and extended temperature devices. Stresses beyond those listed under absolute

maximum ratings may cause permanent damage to the device. These are stress ratings only and

functional operation of the device at these or any other conditions beyond those indicated under

recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for

extended periods may affect device reliability.

Notes:

•

Logic functions and parameter values are not assured out of the range specified in the recommended

operating conditions.

•

The OMAP3525 and OMAP3530 devices adhere to EIA/JESD22–A114, Electrostatic Discharge (ESD)

Sensitivity Testing Human Body Model (HBM). Minimum pass level for HBM is ±2 kV.

Table 3-1. Absolute Maximum Ratings Over Operating Junction Temperature Range

PARAMETER

MIN

MAX

UNIT

vdd_mpu_iva

vdd_core

Supply voltage range for core macros

–0.5

1.6

V

vdds

vdds_mem

Second supply voltage range for 1.8-V I/O macros

–0.5

2.25

V

vdds_mmc1

Supply voltage range for MMC1 CMD, CLK and

DAT[3:0] and for memory stick I/Os

1.8-V mode

3.0-V mode

1.8-V mode

3.0-V mode

–0.5

-0.5

–0.5

-0.5

–0.5

2.45

3.50

2.45

3.50

2.10

vdds_vdds_mm Second supply voltage range for =MMC1 DAT[7:4]

c1a

V

vdds_dpll_dll

vdds_dpll_per

Supply voltage for DLL DPLL

Supply voltage for Per DPLL

V

vdds_sram

Supply voltage for SRAM LDOs

–0.5

2.25

vdds_wkup_bg Supply voltage for wakeup LDO and VDDA (2 LDOs SRAM and BG)

V_PAD

Voltage range MMC1, MS (Balls N28, M27, N27,

Supply voltage range

for 1.8-V IOs

–0.54⁽¹⁾

–0.45⁽²⁾

–0.63⁽¹⁾

2.34⁽¹⁾

3.45⁽²⁾

2.73⁽¹⁾

at PAD

N26, N25, P28)

MMC1(Balls P27, P26, R27, R25)

Supply voltage range

for 3.0-V IOs

I2C1, I2C2, I2C3, I2C4 (Balls K21, J21, AF15, AE15, AF14,

AG14, AD26, AE26)

Crystal (xtalin/xtalout) (Balls AE17, AF17)

Other balls

–0.5

2.71

vddsx⁽³⁾+ 0.5

2.43

vdda_dac

V_ESD

Supply voltage range for analog macros

V

ESD stress

voltage⁽⁴⁾

HBM (human body model)⁽⁵⁾

CDM (charged device model)⁽⁶⁾

2000

500

I_IOI

Current-pulse injection on each I/O pin⁽⁷⁾

Clamp current for an input or output

Storage temperature range⁽⁸⁾

200

mA

°C

I_clamp

T_stg

–20

–65

20

150

(1) For a maximum time of 30% time period.

(2) For a maximum time of 15% time period.

(3) ) Depending on ball, vddsx can be vdds_mem or vdds.

(4) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.

(5) JEDEC JESD22–A114 D with the following exception-no connect pins are not stressed. 2000V Human Body Model (HBM)

(6) JEDEC JESD22–C101C with the following exception-split out pin groupings to eliminate cumulative stress effect

(7) Each device is tested with I/O pin injection of 200 mA with a stress voltage of 1.5 times maximum vdd at room temperature.

(8) These temperatures extreme do not simulate actual operating conditions but exaggerate any faults that might exist.

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This section includes the maximum power consumption for each power domain (core, IVA2, etc.).

Table 3-2 summarizes the power consumption at the ball level.

Table 3-2. Estimated Maximum Power Consumption At Ball Level

PARAMETER

MAX

UNIT

( T = 90°C)

( T = 105°C)

Signal

Description＝

vdd_mpu_iva

Processors

OMAP3525/30 (SmartReflex™ Enabled)

1137

1384

1209

1520

mA

OMAP35=25/30 (SmartReflex™

Disabled)

vdd_core

Core

OMAP3530 (SmartReflex™ Enabled)

OMAP3530 (SmartReflex™ Disabled)

OMAP3525 (SmartReflex™ Enabled)

OMAP3525(SmartReflex™ Disabled)

OMAP3515 (SmartReflex™ Enabled)

OMAP3515 (SmartReflex™ Disabled)

OMAP3503 (SmartReflex™ Enabled)

OMAP3503(SmartReflex™ Disabled)

433

509

328

378

433

509

328

378

65

490

599

382

485

490

599

382

485

65

mA

Core

vdda_dac

Video DAC

vdss_dpll_dll

vdds_dpll_per

vdds_sram

vdds_wkup_bg

vdds_mem

vdds

DLL + DPLL MPU, DSP, and core

DPLL peripheral 1 and peripheral 2

Processors and core LDO (LDO1 and LDO2)

Bandgap, wakeup + LDO, EMU off

Standard I/Os (SDRC+GPMC)

Standard I/Os (all excluding SDRC and GPMC)

MMC I/O⁽¹⁾

25

15

41

6

37

63

mA

vdds_mmc1

vdds_mmc1a

vpp

20

Power supply for MMC IO [DAT4 – DAT7]

eFuse

2

50

(1) MMC card and I/O card are not included.

96

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3.3 Recommended Operating Conditions

All OMAP3525 and OMAP3530 modules are used under the operating conditions contained in Table 3-3.

Note:

To avoid significant device degradation for commercial temperature OMAP3530/OMAP3525 devices

(–40°C ≤ T_J≤ 90°C), the device power-on hours (POH) must be limited to one of the following:

•

100K total POH when operating across all OPPs and keeping the time spent at OPP5 to less than 23K

POH.

•

50K total POH when operating exclusively at OPP5.

44K total POH with no restrictions to the proportion of these POH at operating points OPP1 - OPP5.

Note: Logic functions and parameter values are not assured out of the range specified in the

recommended operating conditions.

Table 3-3. Recommended Operating Conditions

PARAMETER

DESCRIPTION

MIN

NOM

MAX

UNIT

V_DD1

OMAP processor logic supply

OPP5: Overdrive

V_DD1NOM

-

1.35

V_DD1NOM

+

V

(vdd_mpu_iva),

SmartReflex

Disabled

(0.05*V_DD1NOM

V_DD1NOM

(0.05*V_DD1NOM

V_DD1NOM

(0.05*V_DD1NOM

V_DD1NOM

(0.05*V_DD1NOM

V_DD1NOM

(0.05*V_DD1NOM

V_DD2NOM

(0.05*V_DD2NOM

V_DD2NOM

(0.05*V_DD2NOM

V_DD2NOM

)

(0.05*V_DD1NOM

V_DD1NOM

(0.05*V_DD1NOM

V_DD1NOM

(0.05*V_DD1NOM

V_DD1NOM

(0.05*V_DD1NOM

V_DD1NOM

(0.05*V_DD1NOM

V_DD2NOM

(0.05*V_DD2NOM

V_DD2NOM

(0.05*V_DD2NOM

V_DD2NOM

)

OPP4: Mid-Overdrive

OPP3: Nominal

-

1.27

1.20

1.05

0.975

1.15

1.05

0.975

1.8

+

V

-

+

OPP2: Low-Power

OPP1: Ultra Low-Power

OPP3: Nominal

-

+

-

+

V_DD2(vdd_core) OMAP core logic supply⁽¹⁾

SmartReflex

Disabled

-

+

OPP2: Low-Power

OPP1: Ultra Low-Power

-

+

-

+

(0.05*V_DD2NOM

vdds

Supply voltage for I/O macros

Noise (peak-peak)

1.71

1.91

90

V

mVpp

V

vdds_mem

vdds_mmc1

Supply voltage for memory I/O macros

Noise (peak-peak)

1.71

1.8

1.89

90

mVpp

V

Supply voltage range for MMC1

CMD, CLK and DAT[3:0] and for

memory stick I/Os

1.8-V mode

3.0-V mode

1.71

2.7

1.8

3.0

1.89

3.3

V

Noise (peak-peak)

1.8-V mode

3.0-V mode

1.8-V mode

3.0-V mode

1.8-V mode

3.0-V mode

90

150

1.89

3.3

mVpp

V

vdds_mmc1a

Second supply voltage range for

SIM I/Os and MMC1 DAT[7:4]

1.71

2.7

1.8

3.0

Noise (peak-peak)

90

mVpp

150

1.89

50

vdds_wkup_bg Wakeup LDO

Noise (peak-peak)

1.71

1.8

V

mVpp

V

vdda_dac

Analog supply voltage for video DAC

Noise (peak-peak)

1.89

30

For a frequency of 0 to

100 kHz

mVpp

(For a frequency < 100

kHz, decreases 20dB /

sec)

(1) Core logic includes interconnect, graphics processor, and peripherals.

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Table 3-3. Recommended Operating Conditions (continued)

PARAMETER

DESCRIPTION

MIN

NOM

MAX

1.89

50

UNIT

V

vdds_sram

SRAM LDOs

1.71

1.8

Noise (peak-peak)

mVpp

V

vdds_dpll_per

vdds_dpll_dll

vdds_csi2

vdds_csib

vdds_sdi

Peripherals DPLLs power supply

Noise (peak-peak)

1.71

1.8

1.89

36

mVpp

V

Supply voltage for DPLLs I/Os

Noise (peak-peak)

1.89

30

mVpp

V

VDDS for serial camera interface

Noise (peak-peak)

1.89

25

mVpp

V

VDDS for serial camera interface

Noise (peak-peak) for a frequency from dc to 10 MHz

Dedicated VDDS for SDI IO cell

Noise (peak-peak)

1.89

20

mVpp

V

1.89

20

mVpp

V

vdds_dsi

1.8-V analog supply pad for the module

1.89

50

Noise (peak-peak)

For a frequency from 0

mVpp

to 10 MHz

For any frequency > 400

MHz

2.5

vpp⁽²⁾

vss

eFuse programming

Ground

V

0

-

0

vssa_dac

T_J

Dedicated ground for DAC

Operating junction temperature⁽³⁾

V

-40

90

°C

(2) It is recommended not to connect this pin. It is just used for eFuse programming on package unit.

(3) For proper device operation, Tj must be within the specified range.

98

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3.4 DC Electrical Characteristics

Table 3-4 summarizes the DC electrical characteristics.

Table 3-4. DC Electrical Characteristics

PARAMETER

MIN

NOM

MAX

UNIT

LVCMOS Pin Buffers - CBB: N28, M27, N27, N26, N25, P28,P27, P26, R27, R25/ CBC: N19, L18, M19, M18, K18, N20, M20, P17, P18,

P19

V_IH

High-level input voltage

vdds⁽¹⁾= 1.8 V

vdds⁽¹⁾= 3.0 V

0.65 × vdds⁽¹⁾

vdds + 0.3

V

0.625 ×

vdds⁽¹⁾

V_IL

V_OH

V_OL

Low-level input voltage

vdds⁽¹⁾= 1.8 V

vdds⁽¹⁾= 3.0 V

vdds⁽¹⁾= 1.8 V

vdds⁽¹⁾= 3.0 V

vdds⁽¹⁾= 1.8 V

vdds⁽¹⁾= 3.0 V

–0.3

vdds⁽¹⁾– 0.2

0.75 × vdds⁽¹⁾

0.35 × vdds

0.25 × vdds

V

High-level output voltage⁽²⁾

Low-level output voltage⁽²⁾

0.2

0.125 ×

vdds⁽¹⁾

t_T

Input transition time (rise time, t_Ror fall time, Normal Mode

10

3

ns

t_Fevaluated between 10% and 90% at PAD)

High-Speed

Mode

LVDS/CMOS Pin Buffers - CBB: AG19, AH19, AG18, AH18, AG17, AH17/ CBC: AE16, AE15, AD17, AE18, AD16, AE17

Low-Power Receiver (LP-RX)

V_IL

V_IH

Low-level input threshold

High-level input threshold

Input hysteresis

500

300

mV

800

25

V_HYS

Ultralow-Power Receiver (ULP-RX)

V_IL-ULPMLow-level input threshold, ULPM

mV

V_IH

High-level input threshold

880

High-Speed Receiver (HS-RX)

70

V_IDTH

V_IDTL

Differential input high threshold

Differential input low threshold

Maximum differential input voltage

Single-ended input low voltage

Single-ended input high voltage

mV

–70

270

V_IDMAX

V_ILHS

–40

70

V_IHHS

460

330

V_CMRXDCCommon-mode voltage

LVDS/CMOS Pin Buffers - CBB: K28, L28, K27, L27/ CBC: P25, P26, N25, N26

V_CM

Vos

Vid

t_T

Input common mode voltage range

Receiver Input dc offset

600

–20

70

900

1200

20

mV

mV⁽³⁾

Receiver input differential amplitude

100

200

533

Input transition time (rise time, t_Ror fall time, t_Fevaluated

between 10% and 90% at PAD)

267

ps

LVDS/CMOS Pin Buffers - CBB: AG22, AH22, AG23, AH23, AG24, AH24/ CBC: AE21, AE22, AE23, AE24, AD23, AD24

High-Speed Transceiver (HS-TX)

V_OHHS

|V_OD

V_CMTX

HS output high voltage

360

270

250

mV

|

HS transmit differential voltage

HS transmit static common mode voltage

140

150

200

Low-Power Transceiver (LP-TX)

–50

V_OL

Thevenin output low level

50

mV

(1) This global value may be overridden on a per interface basis if another value is explicitly defined for that interface (for example, I²C).

(2) With 100 µA sink / source current at vddsxmin.

(3) Corresponds to peak-to-peak values: minimum = 140 mV_pp; nominal = 200 mV_pp; maximum = 400 mV_pp

.

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Table 3-4. DC Electrical Characteristics (continued)

PARAMETER

Thevenin output high level

MIN

NOM

MAX

UNIT

V_OH

1.1

1.2

1.3

V

Low-Power Receiver (LP-RX)

V_IL

V_IH

Low-level input threshold

High-level input threshold

Input hysteresis

550

300

mV

880

25

V_HYST

Ultralow-Power Receiver (ULP-RX)

V_IL-ULPSLow-level input threshold, ULPM

V_IHHigh-level input threshold

mV

880

subLVDS/CMOS Pin Buffers - CBB: AA27, AA28, AB27, AB28, AD27, AD28, AC28, AC27/ CBC: AC26, AD26, AA25, Y25, AA26,

AB26, AC25, AB25

Vod

Vocm

t_T

Differential voltage range @ R_L= 100 Ω

100

0.8

150

0.9

200

1

mV

V

Common mode voltage range

Input transition time (Vod rise time, t_Ror Vod fall time, t_F

evaluated between 20% and 80% at PAD)

200

500

ps

Standard LVCMOS Pin Buffers

(4)

V_IH

High-level input voltage (Standard LVCMOS)

Low-level input voltage (Standard LVCMOS)

Hysteresis voltage at an input⁽⁵⁾

0.65 × vdds

vdds + 0.3

V

(4)

V_IL

- 0.3

0.35 × vdds

V_HYS

V_OH

0.1

High-level output voltage, driver enabled,

pullup or pulldown disabled

I_O= I_OHor

I_O= –2 mA

vdds – 0.45

vdds – 0.40

I_O= I_OH< |–2|

mA

V_OL

Low-level output voltage with , driver enabled, I_O= I_OLor

0.45

V

pullup or pulldown disabled

I_O= 2 mA

I_O= I_OL< 2 mA

0.40

10⁽¹⁾

t_T

Input transition time (rise time, t_Ror fall time, t_Fevaluated

between 10% and 90% at PAD)

0

ns

I_I

Input current with V_I= V_Imax

–1

1

µA

I_OZ

Off-state output current for output in high impedance with driver

only, driver disabled

–20

20

Off-state output current for output in high impedance with

driver/receiver/pullup only, driver disabled, pullup not inhibited

–100

100

Off-state output current for output in high impedance with

driver/receiver/pulldown only, driver disabled, pulldown not

inhibited

I_Z

Total leakage current through the PAD connection of a

driver/receiver combination that may include a pullup or pulldown.

The driver output is disabled and the pullup or pulldown is

inhibited.

– 20

20

µA

LVCMOS Open-Drain Pin Buffers Dedicated to I2C IOs - CBB: K21, J21, AF14, AG14, AF15, AE15, AD26, AE26/ CBC: J25, J24, C2,

C1, AB4, AC4, AD15, W16, A21, C21

V_IH

V_IL

V_OL

I_I

High level input voltage

0.7 x vdds

vdds + 0.5

0.3 x vdds

0.2 x vdds

10

V

Low level input voltage

- 0.5

0

Low-level output voltage open-drain at 3-mA sink current

V

Input current at each I/O pin with an input voltage between 0.1 x

vdds to 0.9 x vdds

- 10

µA

C_I

Capacitance for each I/O pin

10

pF

(4) V_IH/V_IL(Standard LVCMOS) parameters are applicable for sys_altclk input clocks.

(5) V_hysis the magnitude of the difference between the positive-going threshold voltage V_T+and the negative-going voltage V_T-

.

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Table 3-4. DC Electrical Characteristics (continued)

PARAMETER

MIN

NOM

MAX

250

40

UNIT

T_OF

Output fall time from V_IHminto V_ILmaxwith a

bus capacitance C_Bfrom 10 pF to 400 pF

Fast mode

20 + 0.1C_B

ns

Standard mode

Output fall time with a capacitive load from 10 High-speed mode

pF to 100 pF at 3-mA sink current

10

20

Output fall time with a capacitive load of 400

pF at 3-mA sink current

80

20

Output fall time with a capacitive load of 40

pF (for CBUS compatibility)

LVCMOS Open-Drain Pin Buffers Dedicated in GPIO mode - CBB: AF15, AE15, AF14, AG14, AD26, AE26 / CBC: C2, C1, AB4, AC4,

AD15, W16, A21, C21

V_IH

V_IL

High-level input voltage

0.7 x vdds

- 0.5

vdds + 0.5

0.3 x vdds

V

Low-level input voltage

V_OH

V_OL

High-level output voltage at 4-mA sink current

Low-level output voltage at 4-mA sink current

vdds - 0.45

0.45

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3.5 Core Voltage Decoupling

For module performance, decoupling capacitors are required to suppress the switching noise generated

by high frequency and to stabilize the supply voltage. A decoupling capacitor is most effective when it is

close to the device because this minimizes the inductance of the circuit board wiring and interconnects.

Table 3-5 summarizes the power supplies decoupling characteristics.

Table 3-5. Core Voltage Decoupling Characteristics

PARAMETER

MIN

50

TYP

100

1.0

MAX

120

UNIT

nF

µF

nF

Cvdd_mpu_iva⁽¹⁾

Cvdd_core⁽¹⁾

Cvdds_sram

50

120

Ccap_vdd_sram_mpu_iva

Ccap_vdd_sram_core

Ccap_vdd_wkup

Cvdds_wkup_bg

Cvdds_dpll_dll

Cvdds_dpll_per

Cvdda_dac

0.7

1.3

1.0

100

Cvdds_mmc1

Cvdds_mmca

Cvdds

Cvdds_mem

(1) 1 capacitor per 2 to 4 balls

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Figure 3-2 illustrates an example of power supply decoupling.

OMAP Device

vdds_sram

Cvdds_sram

vdds_sram

vdda_dac

Cvdda_dac

vdda_dac

vssa_dac

Video DAC

cap_vdd_sram_mpu_

iva

Ccap_vdd_sram_mpu_iva

Ccap_vdd_sram_core

SRAM_LDO1

cap_vdd_sram_core

vdds_wkup_bg

SRAM_LDO2

BG

vdds_wkup_bg

Cvdds_wkup_bg

WKUP_LDO

vdds_mmc1

Cvdds_mmc1

vdds_mmc1

cap_vdd_wkup

MMC IOs

Cvdd_wkup

DPLL_MPU

DPLL_IVA

vdds_dpll_dll

Cvdds_dpll_dll

DPLL_CORE

vdds_dpll_per

DPLL5

Cvdds_dpll_per

DPLL4

Core

Vdd_core

vdd_mpu_iva

Cvdd_mpu_iva

Vdd_mpu_iva

vdd_core

VSS

MPU

Cvdd_core

030-004

(1) Decoupling capacitors must be placed as closed as possible to the power ball. Choose the ground located closest to the power pin

for each decoupling capacitor. Place the decoupling capacitor Ci in a group of 1, 2, or 3 balls; the total must be equal to the

decoupling requirement. In case you interconnect powers, first insert the decoupling capacitor and then interconnect the powers.

(2) The decoupling capacitor value depends on the board characteristics.

Figure 3-2. Power Supply Decoupling

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3.6 Power-up and Power-down

This section provides the timing requirements for the OMAP3525 and OMAP3530 hardware signals.

3.6.1 Power-up Sequence

The following steps give an example of power-up sequence supported by the OMAP3525 and OMAP3530

devices.

1. vdds and vdds_mem are ramped ensuring a level on the IO domain and sys_nrespwron must be low.

At the same time, vdds_sram and vdds_wkup_bg can also be ramped.

2. Once vdds_wkup_bg rail is stabilized, vdd_core can be ramped.

3. Once vdd_core is stabilized, then vdd_mpu_iva can be ramped.

4. vdds_dpll_dll and vdds_dpll_per rails can be ramped at any time during the above sequence.

5. sys_nrespwron can be released as soon as the vdds_pll_dll rail is stabilized, and sys_xtalin and

sys_32k clocks are stabilized.

6. During the whole sequence above, sys_nreswarm is held low by OMAP3525 and OMAP3530.

sys_nreswarm is released after the eFuse check has been performed; that is, after sys_nrespwron is

released.

7. The other power supplies can then be turned on upon software request.

Figure 3-3 shows the power-up sequence.

Notes:

•

If an external square clock is provided, it could be started after sys_nrespwron release provided it is

clean: no glitch, stable frequency, and duty cycle.

•

Higher voltage can be used. See the operating condition addendum for values. OPP voltage values

may change following the silicon characterization result.

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1.8 V

vdds_wkup_bg

1.8 V

vdds_mem,vdds,

vdds_sram

ldo3 (internal)

(2)

vdd_core

vdd_mpu_iva

vdds_dpll_dll

vdds_dpll_per

(2)

1.8 V

sys_32k

sys_nrespwron

sys_xtalin

EFUSE.RSTPWRON(internal)

sys_nreswarm

vdds_mmc1,vdds_sim,

vdda_dac⁽¹⁾, vpp

030-005

Figure 3-3. Power-up Sequence

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3.6.2 Power-down Sequence

The OMAP3525 and OMAP3530 devices proceed with the power-down sequence shown in Figure 3-4.

sys_nrespwron

vdds_mmc1,

vdda_dac,

vdds_wkup_bg

vdd_mpu_iva

vdd_core

vdds_mem, vdds,

vdds_sram

vdds_dpll_dll,

vdds_dpll_per

sys_32kin

sys.clk

030-006

Figure 3-4. Power-down Sequence

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4 CLOCK SPECIFICATIONS

The OMAP3525 and OMAP3530 devices have three external input clocks, a low frequency (sys_32k), a

high frequency (sys_xtalin), and an optional (sys_altclk). The OMAP3525 and OMAP3530 devices haver

two configurable output clocks, sys_clkout1 and sys_clkout2.

Figure 4-1 shows the interface to the external clock sources and clock outputs.

OMAP

sys_32k

Power IC

Alternate Clock Source Selectable (54, 48 MHz or other [up

to 59 MHz])

sys_altclk

To Peripherals (From OSC_CLK: 12, 13,16.8, 19.2, 26, or

38.4 MHz)

sys_clkout1

sys_clkout2

sys_xtalout

To Peripherals (From OSC_CLK: 12,13, 16.8, 19.2, 26, or

38.4 MHz, core_clk [DPLL, up to 332 MHz], DPLL-96 MHz

or DPLL-54 MHz outputs with a divider of 1, 2, 4, 8, or 16)

To Quartz (Oscillator output) or Unconnected

sys_xtalin

sys_clkreq

sys_xtalout

sys_xtalin

To Quartz (Oscillator input) or Square Clock

Clock Request. To Square Clock Source or from Peripherals

sys_xtalout

Unconnected

Oscillator

is Bypassed

Oscillator

is Used

sys_xtalin

Square

Clock

Source

sys_clkreq

GPin

030-007

Figure 4-1. Clock Interface

The OMAP3525 and OMAP3530 devices operation requires the following three input clocks:

•

The 32-kHz frequency is used for low frequency operation. It supplies the wake-up domain for

operation in lowest power mode (off mode). This clock is provided through the sys_32k pin.

The system alternative clock can be used (through the sys_altclk pin) to provide alternative 48 or 54

MHz or other clock source (up to 59 MHz).

The system clock input (12, 13, 16.8, 19.2, 26, or 38.4 MHz) is used to generate the main source clock

of the OMAP3525 and OMAP3530 devices. It supplies the DPLLs as well as several OMAP modules.

The system clock input can be connected to either:

–

A crystal oscillator clock managed by sys_xtalin and sys_xtalout. In this case, the sys_clkreq is

used as an input (GPIN).

–

A CMOS digital clock through the sys_xtalin pin. In this case, the sys_clkreq is used as an output to

request the external system clock.

The OMAP3525 and OMAP3530 outputs externally two clocks:

•

sys_clkout1 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz) at any time. It can be

controlled by software or externally using sys_clkreq control. When the device is in the off state, the

sys_clkreq can be asserted to enable the oscillator and activate the sys_clkout1 without waking up the

device. The off state polarity of sys_clkout1 is programmable.

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•

sys_clkout2 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz), core_clk (core DPLL

output), 96 MHz or 54 MHz. It can be divided by 2, 4, 8, or 16 and its off state polarity is

programmable. This output is active only when the core power domain is active.

For more information on the OMAP3525 and OMAP3530 Applications Processors clocking structure, see

the Power, Reset, and Clock management (PRCM) chapter of the OMAP35x Applications Processor TRM

(literature number SPRUFA5).

4.1 Input Clock Specifications

The clock system accepts three input clock sources:

•

32-kHz digital CMOS clock

Crystal oscillator clock or CMOS digital clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz)

Alternate clock (48 or 54 MHz, or other up to 59 MHz)

4.1.1 Clock Source Requirements

Table 4-1 illustrates the requirements to supply a clock to the OMAP3525 and OMAP3530 devices.

Table 4-1. Clock Source Requirements

PAD

CLOCK FREQUENCY

STABILITY

± 25 ppm

± 50 ppm

DUTY CYCLE

na

JITTER

na

TRANSITION

na

sys_xtalout

sys_xtalin

12, 13, 16.8, or 19.2 MHz

Crystal

12, 13, 16.8, 19.2, 26, or 38.4 MHz Square

48,54 or up to 59 MHz

45% to 55%

40% to 60%

< 1%

< 3.6 ns

< 5 ns

sys_altclk

4.1.2 External Crystal Description

To supply a 12-, 13-, 16.8-, or 19.2-MHz clock to the OMAP3525 and OMAP3530, an external crystal can

be connected to the sys_xtalin and sys_xtalout pins. Figure 4-2 describes the crystal implementation.

OMAP Device

sys_xtalin

sys_xtalout

Optional R_bias

Optional R_d

C_f2

C_f1

Crystal

030-008

Figure 4-2. Crystal Implementation^(1)(2)(3)(4)

(1) On the PCB, the oscillator components (crystal, foot capacitors, optional R_biasand R_d) must be located close to the package. All these

components must be routed first with the lowest possible number of board vias.

(2) An optional resistor R_dcan be added in series with the crystal to debug or filter the harmonics; a footprint must be reserved on the PCB

for use with 10-MHz crystals and feature low-drive levels.

(3) A 120-kΩ internal bias resistor R_biasis used. The feedback resistor R_biasprovides negative feedback to the oscillator to put it in the

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linear operating region; thus oscillation begins when power is applied.

(4) C_f1and C_f2represent the total capacitance of the PCB and components excluding the power IC and crystal. Their values in fact depend

on the crystal datasheet. In the datasheet of the crystal, the frequency is specified at a specific load capacitor value which is the

equivalent capacitor of the two capacitors C_f1and C_f2connected to sys_xtalin and sys_xtalout. The frequency of the oscillations

depends on the value of the capacitors (10 pF corresponds to a load capacitor of 5 pF for the crystal).

The crystal must be in the fundamental mode of operation and parallel resonant. Table 4-2 summarizes

the required electrical constraints.

Table 4-2. Crystal Electrical Characteristics

NAME

DESCRIPTION

Parallel resonance crystal frequency⁽¹⁾

Load capacitance for crystal parallel resonance

Crystal ESR (12 and 13 MHz)⁽¹⁾

MIN

TYP

MAX

UNIT

MHz

pF

f_p

12, 13, 16.8, or 19.2

C_L

5

20

80

ESR12&13

Ω

ESR16.8&19.2 Crystal ESR (16.8 and 19.2 MHz)⁽¹⁾

50

Ω

C_o

Crystal shunt capacitance

Crystal motional inductance for f_p= 12 MHz

Crystal motional capacitance

Crystal drive level

1

5

7

pF

L_m

35

mH

fF

C_m

DL

R_bias

100

0.5

300

mW

kΩ

Internal bias resistor

30

120

(1) Measured with the load capacitance specified by the crystal manufacturer. This load is defined by the foot capacitances tied in series. If

C_L= 20 pF, then both foot capacitors will be C_f1= C_f2= 40 pF. Parasitic capacitance from package and board must also be taken in

account.

2

C

0

ESR=R 1+

m

C

L

When selecting a crystal, the system design must take into account the temperature and aging

characteristics of a crystal versus the user environment and expected lifetime of the system. Table 4-3

details the switching characteristics of the oscillator and the input requirements of the 12-, 13-, 16.8-, or

19.2-MHz input clock.

Table 4-3. Base Oscillator Switching Characteristics

NAME

f_p

t_sX

DESCRIPTION

MIN

TYP

MAX

UNIT

MHz

ms

Oscillation frequency

Start-up time⁽¹⁾⁽²⁾

12, 13, 16.8, or 19.2

8

(1) Start-up time defined as time interval between oscillator control signal release and sys_xtalin amplitude at 50% of its final value (vdd and

vdds supplies ramped and stable). The start-up time can be performed in function of the crystal characteristics. 8-ms minimum only

when using the internal oscillator; it is programmable after reset for wake-up. At power-on reset, the time is adjustable using the pin

itself. The reset must be released when the oscillator or clock source is stable. Before the processor boots up and the oscillator is set to

bypass mode, there is a start-up time when the internal oscillator is in application mode and receives a square wave. The start-up time

in this case is about 100 µs.

(2) For f_p= 12 or 13 MHz: C_L= 13.5 pF and L_m= 35 mH

For f_p= 16.8 or 19.2 MHz: C_L= 9 pF and L_m= 15 mH

4.1.3 Clock Squarer Input Description

A 1.8-V CMOS clock squarer is another source that can supply a 12-, 13-, 16.8-, 19.2-, 26-, or 38.4-MHz

clock to the OMAP3525 and OMAP3530. An analog clock squarer function converts a low-amplitude

sinusoidal clock into a low-jitter digital signal. It can be connected to input pin sys_xtalin (sys_xtalout

unconnected). Figure 4-3 illustrates the effective connections.

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OMAP Device

Oscillator

In Bypass Mode

sys_clkreq

sys_xtalin

sys_xtalout

Clock Squarer Source

030-010

Figure 4-3. Clock Squarer Source Connection

To connect a digital clock source, the oscillator is configured in bypass mode⁽¹⁾. The sys_clkreq⁽²⁾pin is an

OMAP3525 and OMAP3530 output which can be used to switch the clock source on or off.

1. Pin sys_xtalout is not used in this mode. It must be left unconnected.

2. Once the system is powered up, the clock squarer source or crystal oscillator source can be applied;

however, this affects the performance. The input source must be configured after power up to attain

the desired system requirements.

Table 4-4 summarizes the electrical constraints required by the clock squarer used in the fundamental

mode of operation.

Note: There is an internal pulldown resistor of 5k Ω (max.) on sys_xtalin when the oscillator is disabled.

Table 4-4. Base Oscillator Electrical Characteristics (in Bypass Mode)

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

MHz

ms

f

Frequency⁽¹⁾

Start-up time

12, 13, 16.8, 19.2, 26, or 38.4

(2)

t_sX

＝

I_DDQ

Current consumption on VDDS when sys_xtalin = 0 and in

power-down mode

1

µA

(1) Measured with the load capacitance specified by the manufacturer. Parasitic capacitance from package and board must also be taken in

account.

(2) Before the processor boots up and the oscillator is set to bypass mode, there is a start-up time when the internal oscillator is in

application mode and receives a square wave. The start-up time in this case is about 100 µs.

Table 4-5 details the input requirements of the 12-, 13-, 16.8-, 19.2-, 26-, or 38.4-MHz input clock.

Table 4-5. 12-, 13-, 16.8-, 19.2-, 26-, or 38.4-MHz Input Clock Squarer Timing Requirements

NAME

OCS0

DESCRIPTION

MIN

TYP

MAX

UNIT

MHz

ns

1 / t_c(xtalin)

t_w(xtalin)

t_J(xtalin)

Frequency, sys_xtalin

12, 13, 16.8, 19.2, 26, or 38.4

OCS1

OCS2

OCS3

OCS4

OCS5

Pulse duration, sys_xtalin low or high

Peak-to-peak jitter⁽¹⁾, sys_xtalin

Rise time, sys_xtalin

0.45 * t_c(xtalin)

–1%

0.55 * t_c(xtalin)

1%

3.6

±25

t_R(xtalin)

t_F(xtalin)

t_J(xtalin)

ns

Fall time, sys_xtalin

Frequency stability, sys_xtalin

ppm

(1) Peak-to-peak jitter is defined as the difference between the maximum and the minimum output periods on a statistical population of 300

period samples. The sinusoidal noise is added on top of the vdds supply voltage.

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OCS0

OCS1

sys.xtalin

030-011

Figure 4-4. Crystal Oscillator in Bypass Mode

4.1.4 External 32-kHz CMOS Input Clock

A 32.768-kHz clock signal (often abbreviated to 32-kHz) can be supplied by an external 1.8-V CMOS

signal on pin sys_32k.

Table 4-6 summarizes the electrical constraints imposed to the clock source.

Table 4-6. 32-kHz Input Clock Source Electrical Characteristics

NAME

DESCRIPTION

Frequency

MIN

TYP

MAX

UNIT

kHz

pF

f

32.768

C_I

R_I

Input capacitance

Input resistance

0.44

0.25

10⁶

GΩ

Table 4-7 details the input requirements of the 32-kHz input clock.

Table 4-7. 32-kHz Input Clock Source Timing Requirements⁽¹⁾

NAME

DESCRIPTION

Frequency, sys_32k

MIN

TYP

MAX

UNIT

CK0

CK3

CK4

CK5

1 / t_c(32k)

t_R(32k)

t_F(32k)

32.768

kHz

ns

Rise time, sys_32k

20

Fall time, sys_32k

ns

t_J(32k)

Frequency stability, sys_32k

±200

ppm

(1) See Table 3-4, Electrical Characteristics, Standard LVCMOS IOs part for sys_32k V_IH/V_ILparameters.

CK0

CK1

sys_32k

030-012

Figure 4-5. 32-kHz CMOS Clock

4.1.5 External sys_altclk CMOS Input Clock

A 48-, 54-, or up to 59- MHz clock signal can be supplied by an external 1.8-V CMOS signal on pin

sys_altclk.

Table 4-8 summarizes the electrical constraints imposed by the clock source.

Table 4-8. 48-, 54-, or up to 59- MHz Input Clock Source Electrical Characteristics

NAME

DESCRIPTION

Frequency , sys_altclk

Input capacitance

MIN

TYP

48-, 54-, or up to 59- MHz

0.74

MAX

UNIT

MHz

pF

f

C_I

R_I

Input resistance

0.25

10⁶

GΩ

Table 4-9 details the input requirements of the input clock.

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Table 4-9. 48- or 54-MHz Input Clock Source Timing Requirements⁽¹⁾⁽²⁾

NAME

ALT0

DESCRIPTION

MIN

TYP

MAX

UNIT

1 / t_c(altclk)

t_w(altclk)

Frequency, sys_altclk

48-, 54-, or up to 59- MHz

MHz

ns

ALT1

Pulse duration, sys_altclk low or

high

0.40 * t_c(altclk)

0.60 * t_c(altclk)

ALT2

ALT3

ALT4

ALT5

t_J(altclk)

t_R(altclk)

t_F(altclk)

t_J(altclk)

Peak-to-peak jitter⁽¹⁾, sys_altclk

–1%

1%

10

Rise time, sys_altclk

ns

Fall time, sys_altclk

10

Frequency stability, sys_altclk

± 50

ppm

(1) Peak-to-peak jitter is defined as the difference between the maximum and the minimum output periods on a statistical population of 300

period samples. The sinusoidal noise is added on top of the vdds supply voltage.

(2) See Table 3-4, Electrical Characteristics, for sys_altclk V_IH/V_ILparameters.

ALT0

ALT1

sys_altclk

030-013

Figure 4-6. Alternate CMOS Clock

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4.2 Output Clock Specifications

Two output clocks (pin sys_clkout1 and pin sys_clkout2) are available:

•

sys_clkout1 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz) at any time. It can be

controlled by software or externally using sys_clkreq control. When the device is in the off state, the

sys_clkreq can be asserted to enable the oscillator and activate the sys_clkout1 without waking up the

device. The off state polarity of sys_clkout1 is programmable.

•

sys_clkout2 can output sys_clk (12, 13, 16.8, 19.2, 26, or 38.4 MHz), CORE_CLK (core DPLL output,

332 MHz maximum), APLL-96 MHz, or APLL-54 MHz. It can be divided by 2, 4, 8, or 16 and its off

state polarity is programmable. This output is active only when the core domain is active.

Table 4-10 summarizes the sys_clkout1 output clock electrical characteristics.

Table 4-10. sys_clkout1 Output Clock Electrical Characteristics

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

MHz

pF

f

Frequency

Load capacitance⁽¹⁾

12, 13, 16.8, 19.2, 26, or 38.4＝

C_I

f(max) = 38.4 MHz

f(max) = 26 MHz

37

50

(1) The load capacitance is adapted to a frequency.

Table 4-11 details the sys_clkout1 output clock timing characteristics.

Table 4-11. sys_clkout1 Output Clock Switching Characteristics

NAME

DESCRIPTION

Frequency

MIN

TYP

12, 13, 16.8, 19.2, 26, or 38.4

0.60 *

t_c(CLKOUT1)

5.5

MAX

UNIT

MHz

ns

f

1 / CO0

CO1

t_w(CLKOUT1)

Pulse duration, sys_clkout1 low or high

0.40 *

t_c(CLKOUT1)

CO2

CO3

t_R(CLKOUT1)

t_F(CLKOUT1)

Rise time, sys_clkout1⁽¹⁾

Fall time, sys_clkout1⁽¹⁾

ns

5.5

(1) With a load capacitance of 50 pF.

CO0

CO1

sys_clkout

030-014

Figure 4-7. sys_clkout1 System Output Clock

Table 4-12 summarizes the sys_clkout2 output clock electrical characteristics.

Table 4-12. sys_clkout2 Output Clock Electrical Characteristics

NAME

DESCRIPTION

Frequency, sys_clkout2

Load capacitance⁽¹⁾

MIN

TYP

MAX

322

12

UNIT

MHz

pF

f

C_L

f(max) = 166 MHz

2

8

(1) The load capacitance is adapted to a frequency.

Table 4-13 details the sys_clkout2 output clock timing characteristics.

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Table 4-13. sys_clkout2 Output Clock Switching Characteristics

NAME

DESCRIPTION

Frequency

MIN

TYP

MAX

UNIT

MHz

ns

f

1 / CO0

322

CO1

CO2

CO3

t_w(CLKOUT2)

t_R(CLKOUT2)

t_F(CLKOUT2)

Pulse duration, sys_clkout2 low or high

Rise time, sys_clkout2⁽¹⁾

Fall time, sys_clkout2⁽¹⁾

0.40 * t_c(CLKOUT2)

0.60 * t_c(CLKOUT2)

3.7

4.3

ns

(1) With a load capacitance of 12 pF.

CO0

CO1

sys_clkout

030-015

Figure 4-8. sys_clkout2 System Output Clock

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4.3 DPLL and DLL Specifications

The OMAP3525 and OMAP3530 integrate seven DPLLs and a DLL. The PRM and CM drive five of them,

while the sixth (not supported) and the seventh (not supported) are controlled by the display subsystem.

The five main DPLLs are:

•

DPLL1 (MPU)

DPLL2 (IVA2)

DPLL3 (Core)

DPLL4 (Peripherals)

DPLL5 (Second Peripherals DPLL)

Figure 4-10Figure 4-9 illustrates the DLL and DPLL implementation.

OMAP

vdds_dpll_dll Power Rail

DPLL1

DLL

DPLL2

DPLL3

DPLL4

DPLL5

vdds_dpll_per

SDI DPLL

vdds_sdi

DSI DPLL

vdds_dsi

Figure 4-9. DPLL and DLL Implementation

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OMAP

vdds_dpll_dll

Power Rail

DPLL1

DPLL2

DPLL3

DPLL4

DLL

DPLL5

vdds_dpll_per

030-016

Figure 4-10. DPLL and DLL Implementation

For more information on the OMAP3525 and OMAP3530 Applications Processors DPLLs and clocking

structure, see the Power, Reset, and Clock management (PRCM) chapter of the OMAP35x Applications

Processor TRM (literature number SPRUFA5).

4.3.1 Digital Phase-Locked Loop (DPLL)

The DPLL provides all interface clocks and some functional clocks (such as the processor clocks) of the

OMAP3525 and OMAP3530 devices.

DPLL1 and DPLL2 get an always-on clock used to produce the synthesized clock. They get a high-speed

bypass clock used to switch the DPLL output clock on this high-speed clock during bypass mode.

The high-speed bypass clock is an L3 divided clock (programmable by 1 or 2) that saves DPLL processor

power consumption when the processor does not need to run faster than the L3 clock speed, or optimizes

performance during frequency scaling.

Each DPLL synthesized frequency is set by programming M (multiplier) and N (divider) factors. In addition,

all DPLL outputs can be controlled by an independent divider (M2 to M6).

The clock generating DPLLs of the OMAP3525 and OMAP3530 devices have following features:

•

Independent power domain per DPLL

Controlled by clock-manager (CM)

Fed with always-on system clock with independent gating control per DPLL

Analog part supplied through dedicated power supply (1.8 V) and an embedded LDO to get rid of

1-MHz noise

•

Up to five independent output dividers for simultaneous generation of multiple clock frequencies

4.3.1.1 DPLL1 (MPU)

DPLL1 is located in the MPU subsystem and supplies all clocks of the subsystem. All MPU subsystem

clocks are internally generated in the subsystem. When the core domain is on, it can use the DPLL3

(CORE DPLL) output as a high-frequency bypass input clock.

4.3.1.2 DPLL2 (IVA2)

DPLL2 is located in the IVA subsystem and supplies all clocks of the subsystem. All IVA subsystem clocks

are internally generated in the subsystem. When the core domain is on, it can use the DPLL3 (CORE

DPLL) output as a high-frequency bypass input clock.

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4.3.1.3 DPLL3 (CORE)

DPLL3 supplies all interface clocks and also a few module functional clocks. It can be also source of the

emulation trace clock. It is located in the core domain area. All interface clocks and a few module

functional clocks are generated in the CM. When the core domain is on, it can be used as a bypass input

to DPLL1 and DPLL2.

4.3.1.4 DPLL4 (Peripherals)

DPLL4 generates clocks for the peripherals. It supplies five clock sources: 96-MHz functional clocks to

subsystems and peripherals, 54 MHz to TV DAC, display functional clock, camera sensor clock, and

emulation trace clock. It is located in the core domain area. All interface clocks and few module functional

clocks are generated in the CM. Its outputs to the DSS, PER, and EMU domains are propagated with

always-on clock trees.

4.3.1.5 DPLL5 (Second peripherals DPLL)

DPLL5 supplies the 120-MHz functional clock to the CM.

4.3.2 Delay-Locked Loops (DLL)

The SDRC includes analog-controlled delay technology for interfacing high-speed mobile DDR memory

components. For more information, see the SDRC-GPMC chapter of the OMAP35x Technical Reference

Manual (TRM) [literature number SPRUF98]. A DLL is a calibration module used on dynamic track of

voltage and temperature variations, as well as to compensate the silicon process dispersion.

The SDRC DLL has four modes of operation:

1. APPLICATION MODE 0: used to generate 72° delay

2. APPLICATION MODE 1: used to generate 90° delay

3. MODEMAXDELAY: used for low frequency operation where we do not have the requirement of

accurate 72° or 90° phase shift

4. IDLE MODE: a low-power state that allows the DLL to gain lock quickly on exit from this mode

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4.3.3 DPLLs and DLL Characteristics

Several specifications characterize the seven DPLLs.

Table 4-14 summarizes the DPLL characteristics and assumes testing over recommended operating

conditions.

Table 4-14. DPLL Characteristics

NAME

vdds_dpll_per

vdds_dpll_dll

T_J

PARAMETER

MIN

1.71

–40

TYP

1.8

25

MAX

1.89

107

UNIT

V

COMMENTS⁽¹⁾

At ball level (+5%, +10%)

V

Junction temperature

°C

Will not unlock after lock over this range for

slow temperature drifts

f_input

Input reference frequency⁽²⁾

Internal reference frequency

0.75

7.5

25

65

2.1

MHz

FINP

f_internal

FREQSEL3 = 0; FINT = FINP/(N+1)

FREQSEL3 = 1; FINT = FINP/(N+1)

21

f_output

CLKOUT output frequency

900

1800

f_output*2

CLKOUTx2 output

frequency

50

t_lock

Frequency lock time⁽³⁾

71.4

37.1

166.7

46.7

4.8

200

104

µs

150 FINT cycles; FREQSEL3 = 0

780 FINT cycles; FREQSEL3 = 1

350 FINT cycles; FREQSEL3 = 0

980 FINT cycles; FREQSEL3 = 1

10 FINT cycles

p_lock

Phase lock time

466.7

130.7

13.3

t_relock

Relock time – frequency

lock⁽⁴⁾

Lowcurrstby = 0; FREQSEL3 = 0

100 FINT cycles

4.8

19

13.3

53.3

200

µs

Lowcurrstby = 0; FREQSEL3 = 1

40 FINT cycles

Lowcurrstby = 1; FREQSEL3 = 0

400 FINT cycles

19

Lowcurrstby = 1; FREQSEL3 = 1

150 FINT cycles

p_relock

Relock time – Phase lock⁽⁴⁾

71.4

11.9

95.2

26.7

Lowcurrstby = 0; FREQSEL3 = 0

250 FINT cycles

33.3

266.7

74.7

Lowcurrstby = 0; FREQSEL3 = 1

200 FINT cycles

Lowcurrstby = 1; FREQSEL3 = 0

560 FINT cycles

Lowcurrstby = 1; FREQSEL3 = 1

Table 4-15 and Table 4-16 show the DPLL1 and DPLL2 clock frequency ranges.

Note: The DPLL1 and DPLL2 clock frequency ranges depend on the V_DD1(vdd_mpu_iva) operating point.

(1) f_reqselneeds to be programmed accordingly to reference clock and DPLL divider (register setting), Lowcurrstdby depends on the targeted

DPLL power state (dynamic).

Lowcurrstdby = 0 then DPLL is in normal mode

Lowcurrstdby = 1 then DPLL is in low-power mode

(2) Input frequencies below 0.75 MHz are possible with performance penalty.

(3) Maximum frequency for nominal conditions. Speed binning possible above fmax.

(4) Relock time assumes typical operating conditions, 4°C maximum temperature drift (see the Functional Specification for more detailed

information).

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Table 4-15. DPLL1 Clock Frequency Ranges

Clock Signal

Description

Max

600

550

500

250

125

Unit

MHz

OPP5

OPP4

OPP3

OPP2

OPP1

ARM_CLK

DPLL1 output clock.

Table 4-16. DPLL2 Clock Frequency Ranges

Clock Signal

Description

Max

Unit

MHz

OPP5

OPP4

OPP3

OPP2

OPP1

430

400

360

180

90

Generated from DPLL2 output

clock.

IVA2_CLK

Table 4-17 through Table 4-19 show the DPLL3 clock frequency ranges.

Note: The DPLL3 clock frequency ranges depend on the VDD2 (vdd_core) operating point and the L3

clock speed configuration.

Table 4-17. DPLL3 Clock Frequency Ranges, VDD2 OPP3

Config 1

Config 2

Config 3

(166 MHz)

(133 MHz)

(100 MHz)

Unit

Clock Signal

Description

Min

Max

Min

Max

Min

Max

Output of clock manager (CM),

generated directly from DPLL3.

CM: CORE_CLK

-

332

166

-

266

133

-

200

100

MHz

Output of clock manager (CM),

generated using DPLL3.

CM: L3_ICLK

CM: L4_ICLK

Output of clock manager (CM),

generated using CM L3_ICLK and

divider.

-

83

-

66.5

-

50

MHz

SGX input clock, taken from CM

CORE_CLK.

SGX

-

110.67

166

-

88.67

133

-

66.67

100

MHz

SDRC input clock, taken from CM

L3_ICLK.

SDRC

GPMC

GPMC input clock, taken from CM

L3_ICLK.

83

66.5

100

Table 4-18. DPLL3 Clock Frequency Ranges, VDD2 OPP2

Config 1

(83 MHz)

Config 2

(100 MHz)

Unit

Clock Signal

Description

Min

Max

Min

Max

Output of clock manager (CM), generated

directly from DPLL3.

CM: CORE_CLK

-

166

-

200

100

50

MHz

Output of clock manager (CM), generated using

DPLL3.

CM: L3_ICLK

CM: L4_ICLK

-

83

Output of clock manager (CM), generated using

CM L3_ICLK and divider.

41.5

SGX

SGX input clock, taken from CM CORE_CLK.

SDRC input clock, taken from CM L3_ICLK.

GPMC input clock, taken from CM L3_ICLK.

-

55.53

83

-

66.67

100

50

MHz

SDRC

GPMC

83

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Table 4-19. DPLL3 Clock Frequency Ranges, VDD2 OPP1

Config 1

(40 MHz)

Unit

Clock Signal

CM: CORE_CLK

Description

Min

Max

83

Output of clock manager (CM), generated directly from DPLL3.

Output of clock manager (CM), generated using DPLL3.

-

MHz

CM: L3_ICLK

41.5

Output of clock manager (CM), generated using CM L3_ICLK

and divider.

CM: L4_ICLK

-

20.75

MHz

SGX

SGX input clock, taken from CM CORE_CLK.

SDRC input clock, taken from CM L3_ICLK.

GPMC input clock, taken from CM L3_ICLK.

-

N/A

41.5

MHz

SDRC

GPMC

Table 4-20 summarizes the DLL characteristics.

Table 4-20. DLL Characteristics

PARAMETER

MIN

1.71

–40

66

NOM

1.8

MAX

1.89

107

133

166

15

UNIT

V

COMMENTS

Supply voltage vdds_dpll_dll

Junction operating temperature

Input clock frequency

25

°C

120

MHz

APPLICATION MODE 0

APPLICATION MODE 1

83

Input load⁽¹⁾

Lock time⁽²⁾

fF

Clocks

ns

500

372

2

Relock time

IDLE to MODEMAXDELAY

(Mode transitions through idle mode)

150

1

Clocks

µs

IDLE to APPLICATION MODE 1 or 0

IDLE to APPLICATION MODE @133 MHz

IDLE to APPLICATION MODE @166 MHz

1

1.5

µs

(1) This parameter is design goal and is not tested on silicon.

(2) Lock signal would go high from power down within 500 clocks. Lock signal switches to low state when the input clock is switched off

after 3 µs.

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4.3.4 DPLL and DLL Noise Isolation

The DPLL and DLL require dedicated power supply pins to isolate the core analog circuit from the

switching noise generated by the core logic that can cause jitter on the clock output signal. Guard rings

are added to the cell to isolate it from substrate noise injection.

The vdd supplies are the most sensitive to noise; decoupling capacitance is recommended below the

supply rails. The maximum input noise level allowed is 30 mV_PPfor frequencies below 1 MHz.

Figure 4-11= illustrates an example of a noise filter.

OMAP Device

Noise Filter

vdds_dpll_dll

C

DPLL_MPU

DPLL_IVA

DPLL_CORE

DLL

Noise Filter

vdds_dpll_per

C

DPLL5

DPLL4

030-017

Figure 4-11. DPLL and DLL Noise Filter

Table 4-21 specifies the noise filter requirements.

Table 4-21. DPLL and DLL Noise Filter Requirements

NAME

MIN

TYP

MAX

UNIT

nF

Filtering capacitor

100

(1) The capacitors must be inserted between power and ground as close as possible.

(2) This circuit is provided only as an example.

(3) The filter must be located as close as possible to the device.

(4) No filtering required if noise is below 10 mV_PP

.

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5 VIDEO DAC SPECIFICATIONS

A dual-display interface equips the OMAP3525 and OMAP3530 processors. This display subsystem

provides the necessary control signals to interface the memory frame buffer directly to the external

displays (TV-set). Two (one per channel) 10-bit current steering DACs are inserted between the DSS and

the TV set to generate the video analog signal. One of the video DACs also includes TV detection and

power-down mode. Figure 5-1 illustrates the OMAP3525 and OMAP3530 DAC architecture. For more

information, see the DSS chapter of the OMAP35x Technical Reference Manual (TRM) [literature number

SPRUF98].

OMAP Device

TV DCT

tv_vfb1

DIN1[9:0]

TVOUT

BUFFER

Video DAC 1

tv_out1

DSS

tv_vfb2

DIN2[9:0]

TVOUT

BUFFER

Video DAC 2

tv_out2

V_ref

vdda_dac

vssa_dac

tv_vref

CBG

030-018

Figure 5-1. Video DAC Architecture

The following paragraphs detail the 10-bit DAC interface pinout, static and dynamic specifications, and

noise requirements. The operating conditions and absolute maximum ratings are detailed in Table 5-2 and

Table 5-4.

5.1 Interface Description

Table 5-1 summarizes the external pins of the video DAC.

Table 5-1. External Pins of 10-bit Video DAC

PIN NAME

I/O

DESCRIPTION

tv_out1

O

TV analog output composite

DAC1 video output. An external resistor is connected between this

node and tv_vfb1. The nominal value of ROUT1 is 1650 Ω. Finally,

note that this is the output node that drives the load (75 Ω).

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Table 5-1. External Pins of 10-bit Video DAC (continued)

PIN NAME

I/O

DESCRIPTION

tv_out2

O

TV analog output S-VIDEO

DAC2 video output. An external resistor is connected between this

node and tv_vfb2. The nominal value of ROUT2 is 1650 Ω. Finally,

note that this is the output node that drives the load (75 Ω).

tv_vref

tv_vfb1

tv_vfb2

I

Reference output voltage from internal

bandgap

A decoupling capacitor (CBG) needs to be connected for optimum

performance.

O

Amplifier feedback node

Amplifier feedback node. An external resistor is connected between

this node and tv_out1. The nominal value of ROUT1 is 1650 Ω (1%).

Amplifier feedback node

Amplifier feedback node. An external resistor is connected between

this node and tv_out2. The nominal value of ROUT2 is 1650 Ω (1%).

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5.2 Electrical Specifications Over Recommended Operating Conditions

(T_MINto T_MAX, vdda_dac = 1.8 V, R_OUT1/2= 1650 Ω, R_LOAD= 75 Ω, unless otherwise noted)

Table 5-2. DAC – Static Electrical Specification

PARAMETER

Resolution

DC ACCURACY

CONDITIONS/ASSUMPTIONS

MIN

TYP

MAX

UNIT

R

10

Bits

INL⁽¹⁾

DNL⁽²⁾

Integral nonlinearity

–1

1

LSB

Differential nonlinearity

ANALOG OUTPUT

-

Full-scale output voltage

R_LOAD= 75 Ω

0,7

0.88

50

1

V

mV

-

Output offset voltage

Output offset voltage drift

Gain error

-

20

mV/°C

% FS

Ω

-

–17

19

R_VOUT

Output impedance

67.5

75

82.5

REFERENCE

V_REF

-

Reference voltage range

Reference noise density

0.525

3700

0.55

129

0.575

4200

V

100-kHz reference noise

bandwidth

R_SET

P_SRR

Full-scale current adjust resistor

Reference PSRR⁽³⁾(Up to 6 MHz)

4000

40

Ω

dB

POWER CONSUMPTION

I_vdda-up

Analog Supply Current⁽⁴⁾

-

2 channels, no load

2 channels

8

mA

Analog supply driving a 75-Ω load

50

(RMS)

I_vdda-up(peak) Peak analog supply current:

Lasts less than 1 ns

60

2

mA

I_vdd-up

Digital supply current⁽⁵⁾

Measured at f_CLK= 54 MHz, f_OUT

= 2 MHz sine wave, vdd = 1.3 V

I_{vdd-up (peak)}

I_vdda-down

I_vdd-down

Peak digital supply current⁽⁶⁾

Analog power at power-down

Digital power at power-down

Lasts less than 1 ns

T = 30°C, vdda = 1.8 V

T = 30°C, vdd = 1.3 V

2.5

1.5

1

mA

(1) The INL is measured at the output of the DAC (accessible at an external pin during bypass mode).

(2) The DNL is measured at the output of the DAC (accessible at an external pin during bypass mode).

(3) Assuming a capacitor of 0.1 µF at the tv_ref node.

(4) The analog supply current I_vddais directly proportional to the full-scale output current IFS and is insensitive to f_CLK

(5) The digital supply current I_VDDis dependent on the digital input waveform, the DAC update rate f_CLK, and the digital supply VDD.

(6) The peak digital supply current occurs at full-scale transition for duration less than 1 ns.

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(T_MINto T_MAX, vdda_dac = 1.8 V, R_OUT1/2= 1650 Ω, R_LOAD= 75 Ω, unless otherwise noted)

Table 5-3. Video DAC – Dynamic Electrical Specification

PARAMETER

Output update rate

Clock jitter

CONDITIONS/ASSUMPTIONS

MIN

TYP

MAX

UNIT

MHz

ps

(1)

f_CLK

Equal to input clock frequency

54

rms clock jitter required in order to assure

10-bit accuracy

40

Attenuation at 5.1 MHz

Attenuation at 54 MHz⁽¹⁾

Output settling time

Corner frequency for signal

Image frequency

0.1

25

0.5

30

85

1.5

33

dB

ns

t_ST

Time from the start of the output transition to

output within ± 1 LSB of final value.

t_Rout

t_Fout

BW

Output rise time

Output fall time

Measured from 10% to 90% of full-scale

transition

25

ns

Measured from 10% to 90% of full-scale

transition

Signal bandwidth

Differential gain⁽²⁾

Differential phase⁽²⁾

Within bandwidth

6

1.5%

1

MHz

deg.

dB

SFDR

SNR

f_CLK= 54 MHz, f_OUT= 1 MHz

45

55⁽³⁾

Signal-to-noise ratio

dB

1 kHz to 6 MHz bandwidth

PSRR

Power supply rejection ratio Up to 6 MHz

20⁽⁴⁾

–50

dB

Crosstalk Between the two video

channels

–40

(1) For internal input clock information, For more information, see the DSS chapter of the OMAP35x Technical Reference Manual (TRM)

[literature number SPRUF98].

(2) The differential gain and phase value is for dc coupling. Note that there is degradation for the ac coupling.

(3) The SNR value is for dc coupling. Note that there is a 6-dB degradation for ac coupling.

(4) The PSSR value is for dc coupling. Note that there is a 10-dB degradation for ac coupling.

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5.3 Analog Supply (vdda_dac) Noise Requirements

In order to assure 10-bit accuracy of the DAC analog output, the analog supply vdda_dac has to meet the

noise requirements stated in this section.

The DAC Power Supply Rejection Ratio is defined as the relative variation of the full-scale output current

divided by the supply variation. Thus, it is expressed in percentage of Full-Scale Range (FSR) per volt of

DI_OUT

100×

I_OUTFS

% FSR

PSRR_DAC

=

V

V_AC

supply variation as shown in the following equation:

Depending on frequency, the PSRR is defined in Table 5-4.

Table 5-4. Video DAC – Power Supply Rejection Ratio

Supply Noise Frequency

PSRR % FSR/V

0 to 100 kHz

> 100 kHz

1

The rejection decreases 20 dB/dec.

Example: at 1 MHz the PSRR is 10% of FSR/V

A graphic representation is shown in Figure 5-2.

PSRR (% FSR/V)

First pole of

DAC output load

10

1

f

1 MHz

100 kHz

030-019

Figure 5-2. Video DAC – Power Supply Rejection Ratio

To ensure that the DAC SFDR specification is met, the PSRR values and the clock jitter requirements

translate to the following limits on vdda_dac (for the Video DAC).

The maximum peak-to-peak noise on vdda (ripple) is defined in Table 5-5:

Table 5-5. Video DAC – Maximum Peak-to-Peak Noise on vdda_dac

Tone Frequency

0 to 100 kHz

> 100 kHz

Maximum Peak-to-Peak Noise on vdda_dac

< 30 mVpp

Decreases 20 dB/dec.

Example: at 1 MHz the maximum is 3 mVpp

The maximum noise spectral density (white noise) is defined in Table 5-6:

Table 5-6. Video DAC – Maximum Noise Spectral Density

Supply Noise Bandwidth

0 to 100 kHz

Maximum Supply Noise Density

< 20 µV / √Hz

> 100 kHz

Decreases 20 dB/dec.

Example: at 1 MHz the maximum noise density is 2 µ / √Hz

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Because the DAC PSRR deteriorates at a rate of 20 dB/dec after 100 kHz, it is highly recommended to

have vdda_dac low pass filtered (proper decoupling) (see the illustrated application: Section 5.4, External

Component Value Choice).

5.4 External Component Value Choice

The full-scale output voltage V_OUTMAXis regulated by the reference amplifier, and is set by an internal

resistor R_SET. I_OUTMAXcan be expressed as:

I_OUTMAX= I_REF/8 * (63 + 15/16)

Where:

V_REF= 0.55V

I_REF= V_REF/ (2* R_SET

)

The output current I_OUTappearing at DAC output is a function of both the input code and I_OUTMAXand can

be expressed as:

I_OUT= (DAC_CODE/1023) * I_OUTMAX

Where:

DAC_CODE = 0 to 1023 is the DAC input code in decimal.

The output voltage is:

V_OUT= I_OUT*N* R_CABLE

Where:

(N = amplifier gain = 21)

R_CABLE= 75 Ω (cable typical impedance)

The TV-out buffer requires a per channel external resistors: R_OUT1/2. The equation below can be used to

select different resistor values (if necessary):

R_OUT= (N+1) R_CABLE= 1650 Ω

Recommended parameter values are:

Table 5-7. Video DAC – Recommended External Components Values

Recommended Value

UNIT

nF

C_BG

100

R_OUT1/2

1650

Ω

In order to limit the reference noise bandwidth and to suppress transients on V_REF, it is necessary to

connect a large decoupling capacitor ＝_BG) between the tv_vref and vssa_dac pins.

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6 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

6.1 Timing Test Conditions

All timing requirements and switching characteristics are valid over the recommended operating conditions

of Table 3-3, unless otherwise specified.

6.2 Interface Clock Specifications

6.2.1 Interface Clock Terminology

The Interface clock is used at the system level to sequence the data and/or control transfers accordingly

with the interface protocol.

6.2.2 Interface Clock Frequency

The two interface clock characteristics are:

•

The maximum clock frequency

The maximum operating frequency

The interface clock frequency documented in this document is the maximum clock frequency, which

corresponds to the maximum frequency programmable on this output clock. This frequency defines the

maximum limit supported by the OMAP3525 and OMAP3530 IC and doesn’t take into account any system

consideration (PCB, peripherals).

The system designer will have to consider these system considerations and OMAP3525 and OMAP3530

IC timings characteristics as well, to define properly the maximum operating frequency, which corresponds

to the maximum frequency supported to transfer the data on this interface.

6.2.3 Clock Jitter Specifications

Jitter is a phase noise, which may alter different characteristics of a clock signal. The jitter specified in this

document is the time difference between the typical cycle period and the actual cycle period affected by

noise sources on the clock. The cycle (or period) jitter terminology identifies this type of jitter.

Cycle (or Period) Jitter

T_n-1

T_n

T_n+1

Max. Cycle Jitter = Max (T_i)

Min. Cycle Jitter = Min (T_i)

Jitter Standard Deviation (or rms Jitter) = Standard Deviation (T_i)

030-020

Figure 6-1. Cycle (or Period) Jitter

6.2.4 Clock Duty Cycle Error

The duty cycle error is the ratio between either the high-level pulse duration or the low-level pulse duration

and the cycle time of a clock signal.

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6.3 Timing Parameters

The timing parameter symbols used in the timing requirement and switching characteristic tables are

created in accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other

related terminologies have been abbreviated as follows:

Table 6-1. Timing Parameters

LOWERCASE SUBSCRIPTS

Symbols

Parameter

Cycle time (period)

Delay time

c

d

dis

en

h

Disable time

Enable time

Hold time

su

START

t

Setup time

Start bit

Transition time

Valid time

v

w

Pulse duration (width)

Unknown, changing, or don’t care level

High

X

H

L

Low

V

Valid

IV

AE

FE

LE

Z

Invalid

Active Edge

First Edge

Last Edge

High impedance

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6.4 External Memory Interfaces

The OMAP3525 and OMAP3530 processors include the following external memory interfaces:

•

General-purpose memory controller (GPMC)

SDRAM controller (SDRC)

6.4.1 General-Purpose Memory Controller (GPMC)

The GPMC is the OMAP3525 and OMAP3530 unified memory controller used to interface external

memory devices such as:

•

Asynchronous SRAM-like memories and ASIC devices

Asynchronous page mode and synchronous burst NOR flash

NAND flash

6.4.1.1 GPMC/NOR Flash Interface Synchronous Timing

Table 6-3 and Table 6-4 assume testing over the recommended operating conditions (see Figure 6-2

through Figure 6-5) and electrical characteristic conditions.

Table 6-2. GPMC/NOR Flash Synchronous Mode Timing Conditions

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

1.8

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

15.94

pF

Table 6-3. GPMC/NOR Flash Interface Timing Requirements – Synchronous Mode⁽¹⁾

NO.

PARAMETER

OPP3

OPP2

OPP1

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

F12 t_su(DV-CLKH)

F13 t_h(CLKH-DV)

F21 t_{su(WAITV-CLKH)}

F22 t_{h(CLKH-WAITV)}

Setup time, read gpmc_d[15:0]

valid before gpmc_clk high

1.9

3.2

ns

Hold time, read gpmc_d[15:0]

valid after gpmc_clk high

Setup time, gpmc_waitx⁽²⁾valid

before gpmc_clk high

Hold Time, gpmc_waitx⁽²⁾valid

after gpmc_clk high

1.9

2.5

1.9

2.5

1.9

3.2

2.5

(1) For VDD2 (vdd_core) OPP voltages, see Table 3-3, Recommended Operating Conditions.

(2) Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see the OMAP35x

Technical Reference Manual (literature number SPRUF988).

Table 6-4. GPMC/NOR Flash Interface Switching Characteristics – Synchronous Mode

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

F0

F1

t_c(CLK)

Cycle time⁽¹⁵⁾, output

clock gpmc_clk period

10

12.05

25

ns

t_w(CLKH)

Typical pulse duration,

output clock gpmc_clk

high

0.5 P⁽¹²⁾

F1

t_w(CLKL)

t_dc(CLK)

Typical pulse duration,

output clock gpmc_clk low

0.5 P⁽¹²⁾

–500

0.5 P⁽¹²⁾

500

0.5 P⁽¹²⁾

–602

0.5 P⁽¹²⁾

602

0.5 P⁽¹²⁾

–1250

0.5 P⁽¹²⁾

1250

ns

ps

Duty cycle error, output

clk gpmc_clk

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Table 6-4. GPMC/NOR Flash Interface Switching Characteristics – Synchronous Mode (continued)

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

t_j(CLK)

Jitter standard

33.3

ps

deviation⁽¹⁶⁾, output clock

gpmc_clk

t_R(CLK)

t_F(CLK)

Rise time, output clock

gpmc_clk

1.6

2

ns

Fall time, output clock

gpmc_clk

t_R(DO)

Rise time, output data

Fall time, output data

2

ns

t_F(DO)

F2

F3

F4

F5

F6

t_d(CLKH-nCSV)

Delay time, gpmc_clk

rising edge to

F⁽⁶⁾– 1.9

E⁽⁵⁾– 1.9

B⁽²⁾– 4.1

–2.1

F⁽⁶⁾+ 3.3

F⁽⁶⁾– 1.8

E⁽⁵⁾– 1.8

B⁽²⁾– 4.1

–2.1

F⁽⁶⁾+ 4.1

F⁽⁶⁾– 2.6

E⁽⁵⁾– 2.6

B⁽²⁾– 4.9

–2.6

F⁽⁶⁾+ 4.9

gpmc_ncsx⁽¹¹⁾transition

t_{d(CLKH-nCSIV)}

t_d(ADDV-CLK)

t_{d(CLKH-ADDIV)}

t_d(nBEV-CLK)

Delay time, gpmc_clk

rising edge to

E⁽⁵⁾+ 3.3

B⁽²⁾+ 2.1

E⁽⁵⁾+ 4.1

B⁽²⁾+ 2.1

E⁽⁵⁾+ 4.9

B⁽²⁾+ 2.6

ns

gpmc_ncsx⁽¹¹⁾invalid

Delay time, address bus

valid to gpmc_clk first

edge

Delay time, gpmc_clk

rising edge to

gpmc_a[16:1] invalid

Delay time,

B⁽²⁾– 1.1

B⁽²⁾+ 2.1

B⁽²⁾– 0.9

B⁽²⁾+ 1.9

B⁽²⁾– 2.6

B⁽²⁾+ 2.6

gpmc_nbe0_cle,

gpmc_nbe1 valid to

gpmc_clk first edge

F7

t_{d(CLKH-nBEIV)}

Delay time, gpmc_clk

rising edge to

D⁽⁴⁾– 2.1 D⁽⁴⁾+ 1.1 D⁽⁴⁾– 1.9 D⁽⁴⁾+ 0.9 D⁽⁴⁾– 2.6 D⁽⁴⁾+ 2.6

ns

gpmc_nbe0_cle,

gpmc_nbe1 invalid

F8

t_d(CLKH-nADV)

Delay time, gpmc_clk

rising edge to

gpmc_nadv_ale transition

G⁽⁷⁾– 1.9 G⁽⁷⁾+ 4.1 G⁽⁷⁾– 2.1 G⁽⁷⁾+ 4.1 G⁽⁷⁾– 2.6 G⁽⁷⁾+ 4.9

D⁽⁴⁾– 1.9 D⁽⁴⁾+ 4.1 D⁽⁴⁾– 2.1 D⁽⁴⁾+ 4.1 D⁽⁴⁾– 2.6 D⁽⁴⁾+ 4.9

H⁽⁸⁾– 2.1 H⁽⁸⁾+ 2.1 H⁽⁸⁾– 2.1 H⁽⁸⁾+ 2.1 H⁽⁸⁾– 2.6 H⁽⁸⁾+ 4.9

ns

F9

t_{d(CLKH-nADVIV)}Delay time, gpmc_clk

rising edge to

gpmc_nadv_ale invalid

F10

t_d(CLKH-nOE)

Delay time, gpmc_clk

rising edge to gpmc_noe

transition

F11

F14

t_{d(CLKH-nOEIV)}

t_d(CLKH-nWE)

Delay time, gpcm rising

edge to gpmc_noe invalid

E⁽⁵⁾– 2.1

I⁽⁹⁾– 1.9

E⁽⁵⁾+ 2.1

I⁽⁹⁾+ 4.1

E⁽⁵⁾– 2.1

I⁽⁹⁾– 2.1

E⁽⁵⁾+ 2.1

I⁽⁹⁾+ 4.1

E⁽⁵⁾– 2.6

I⁽⁹⁾– 2.6

E⁽⁵⁾+ 4.9

I⁽⁹⁾+ 4.9

ns

Delay time, gpmc_clk

rising edge to gpmc_nwe

transition

F15

F17

F18

F19

F20

t_d(CLKH-Data)

t_d(CLKH-nBE)

t_W(nCSV)

Delay time, gpmc_clk

rising edge to data bus

transition

J⁽¹⁰⁾– 2.1 J⁽¹⁰⁾+ 1.1 J⁽¹⁰⁾– 1.9 J⁽¹⁰⁾+ 0.9 J⁽¹⁰⁾– 2.6 J⁽¹⁰⁾+ 2.6

ns

Delay time, gpmc_clk

rising edge to

gpmc_nbex_cle transition

J⁽¹⁰⁾– 2.1 J⁽¹⁰⁾+ 1.1 J⁽¹⁰⁾– 1.9 J⁽¹⁰⁾+ 0.9 J⁽¹⁰⁾– 2.6 J⁽¹⁰⁾+ 2.6

Pulse duration, Read

A⁽¹⁾

ns

gpmc_ncsx⁽¹¹⁾

Write

low

t_W(nBEV)

Pulse duration, Read

C⁽³⁾

ns

gpmc_nbe0_cle,

gpmc_nbe1 low

Write

t_W(nADVV)

Pulse duration, Read

K⁽¹³⁾

ns

gpmc_nadv_ale

Write

low

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Table 6-4. GPMC/NOR Flash Interface Switching Characteristics – Synchronous Mode (continued)

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

F23

t_{d(CLKH-IODIR)}

Delay time, gpmc_clk

rising edge to gpmc_io_dir

high (IN direction)

H⁽⁸⁾– 2.1 H⁽⁸⁾+ 4.1 H⁽⁸⁾– 2.1 H⁽⁸⁾+ 4.1 H⁽⁸⁾– 2.6 H⁽⁸⁾+ 4.9

ns

F24

t_{d(CLKH-IODIV)}

Delay time, gpmc_clk

rising edge to gpmc_io_dir

low (OUT direction)

M⁽¹⁷⁾– 2.1 M⁽¹⁷⁾+ 4.1 M⁽¹⁷⁾– 2.1 M⁽¹⁷⁾+ 4.1 M⁽¹⁷⁾– 2.6 M⁽¹⁷⁾+ 4.9

ns

(1) For single read: A = (CSRdOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK period

For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period

For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period

with n being the page burst access number.

(2) B = ClkActivationTime * GPMC_FCLK

(3) For single read: C = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: C = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst write: C = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK with n being the

page burst access number.

(4) For single read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst write: D = (WrCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

(5) For single read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst write: E = (CSWrOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

(6) For nCS falling edge (CS activated):

–

Case GpmcFCLKDivider = 0:

F = 0.5 * CSExtraDelay * GPMC_FCLK

Case GpmcFCLKDivider = 1:

–

F = 0.5 * CSExtraDelay * GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime

are even)

–

F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK otherwise

–

Case GpmcFCLKDivider = 2:

–

F = 0.5 * CSExtraDelay * GPMC_FCLK if ((CSOnTime – ClkActivationTime) is a multiple of 3)

F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime – ClkActivationTime – 1) is a multiple of 3)

F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime – ClkActivationTime – 2) is a multiple of 3)

(7) For ADV falling edge (ADV activated):

–

Case GpmcFCLKDivider = 0:

G = 0.5 * ADVExtraDelay * GPMC_FCLK

Case GpmcFCLKDivider = 1:

–

G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and

ADVOnTime are even)

–

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise

–

Case GpmcFCLKDivider = 2:

–

G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVOnTime – ClkActivationTime) is a multiple of 3)

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 1) is a multiple of 3)

G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Reading mode:

–

Case GpmcFCLKDivider = 0:

G = 0.5 * ADVExtraDelay * GPMC_FCLK

Case GpmcFCLKDivider = 1:

–

G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and

ADVRdOffTime are even)

–

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise

–

Case GpmcFCLKDivider = 2:

–

G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime) is a multiple of 3)

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 3)

G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Writing mode:

–

Case GpmcFCLKDivider = 0:

G = 0.5 * ADVExtraDelay * GPMC_FCLK

Case GpmcFCLKDivider = 1:

–

G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and

ADVWrOffTime are even)

–

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise

–

Case GpmcFCLKDivider = 2:

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–

G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime) is a multiple of 3)

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 3)

G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 3)

(8) For OE falling edge (OE activated) / IO DIR rising edge (Data Bus input direction):

–

Case GpmcFCLKDivider = 0:

H = 0.5 * OEExtraDelay * GPMC_FCLK

Case GpmcFCLKDivider = 1:

–

H = 0.5 * OEExtraDelay * GPMC_FCLK if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime

are even)

–

H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise

–

Case GpmcFCLKDivider = 2:

–

H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOnTime – ClkActivationTime) is a multiple of 3)

H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime – ClkActivationTime – 1) is a multiple of 3)

H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime – ClkActivationTime – 2) is a multiple of 3)

For OE rising edge (OE deactivated):

–

GpmcFCLKDivider = 0:

H = 0.5 * OEExtraDelay * GPMC_FCLK

Case GpmcFCLKDivider = 1:

–

H = 0.5 * OEExtraDelay * GPMC_FC if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are

even)

–

H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise

–

Case GpmcFCLKDivider = 2:

–

H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOffTime – ClkActivationTime) is a multiple of 3)

H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime – ClkActivationTime – 1) is a multiple of 3)

H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime – ClkActivationTime – 2) is a multiple of 3)

(9) For WE falling edge (WE activated):

–

Case GpmcFCLKDivider = 0:

I = 0.5 * WEExtraDelay * GPMC_FCLK

Case GpmcFCLKDivider = 1:

–

I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime

are even)

–

I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise

–

Case GpmcFCLKDivider = 2:

–

I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOnTime – ClkActivationTime) is a multiple of 3)

I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime – ClkActivationTime – 1) is a multiple of 3)

I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime – ClkActivationTime – 2) is a multiple of 3)

For WE rising edge (WE deactivated):

–

Case GpmcFCLKDivider = 0:

I = 0.5 * WEExtraDelay * GPMC_FCLK

Case GpmcFCLKDivider = 1:

–

I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime

are even)

–

I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise

–

Case GpmcFCLKDivider = 2:

–

I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOffTime – ClkActivationTime) is a multiple of 3)

I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime – ClkActivationTime – 1) is a multiple of 3)

I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime – ClkActivationTime – 2) is a multiple of 3)

(10) J = GPMC_FCLK period

(11) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

(12) P = gpmc_clk period

(13) For read: K = (ADVRdOffTime – ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For write: K = (ADVWrOffTime – ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

(14) GPMC_FCLK is General-Purpose Memory Controller internal functional clock.

(15) Related to the gpmc_clk output clock maximum and minimum frequencies programmable in the I/F module by setting the

GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider.

(16) The jitter probability density can be approximated by a Gaussian function.

(17) M = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

Above M parameter expression is given as one example of GPMC programming. IO DIR signal will go from IN to OUT after both

RdCycleTime and BusTurnAround completion. Behavior of IO direction signal does depend on kind of successive Read/Write accesses

performed to Memory and multiplexed or non-multiplexed memory addressing scheme, bus keeping feature enabled or not. IO DIR

behavior is automatically handled by GPMC controller. For a full description of the gpmc_io_dir feature, see the OMAP35x Technical

Reference Manual (TRM) [literature number SPRUF98].

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F1

F0

F1

gpmc_clk

F2

F3

F7

F18

gpmc_ncsx

F4

F6

gpmc_a[10:1]

Valid Address

F19

gpmc_nbe0_cle

gpmc_nbe1

F19

F6

F8

F20

F9

gpmc_nadv_ale

gpmc_noe

F10

F11

F13

F12

D 0

gpmc_d[15:0]

gpmc_waitx

gpmc_io_dir

F23

F24

OUT

IN

OUT

030-021

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-2. GPMC/NOR Flash – Synchronous Single Read – (GpmcFCLKDivider = 0)

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F1

F0

gpmc_clk

F2

F3

gpmc_ncsx

F4

F6

gpmc_a[10:1]

gpmc_nbe0_cle

gpmc_nbe1

Valid Address

F7

F9

F6

F8

gpmc_nadv_ale

gpmc_noe

F10

F11

F13

F12

D 0

F22

F12

D 3

gpmc_d[15:0]

gpmc_waitx

gpmc_io_dir

D 1

D 2

F21

F23

F24

OUT

IN

OUT

030-022

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-3. GPMC/NOR Flash – Synchronous Burst Read – 4x16-bit (GpmcFCLKDivider = 0)

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F1

F0

gpmc_clk

gpmc_ncsx

F2

F3

F4

F6

gpmc_a[10:1]

Valid Address

F17

gpmc_nbe0_cle

gpmc_nbe1

gpmc_nadv_ale

gpmc_nwe

F6

F8

F9

F14

F15

D 1

F15

D 2

F15

gpmc_d[15:0]

gpmc_waitx

D 0

D 3

gpmc_io_dir

OUT

030-023

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-4. GPMC/NOR Flash – Synchronous Burst Write – (GpmcFCLKDivider = 0)

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F1

F0

F1

gpmc_clk

gpmc_ncsx

F2

F3

F6

F4

F7

gpmc_nbe0_cle

gpmc_nbe1

Valid

F7

Valid

gpmc_a[26:17]

Address (MSB)

F5

F12

F13

D1 D2

F4

F12

gpmc_a[16:1]_d[15:0]

gpmc_nadv_ale

gpmc_noe

Address (LSB)

F8

D0

D3

F8

F9

F10

F11

gpmc_waitx

F24

F23

gpmc_io_dir

OUT

IN

OUT

030-024

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-5. GPMC/Multiplexed NOR Flash – Synchronous Burst Read

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F1

F0

gpmc_clk

gpmc_ncsx

F2

F3

F4

F6

gpmc_a[26:17]

Address (MSB)

F17

gpmc_nbe0_cle

gpmc_nbe1

gpmc_nadv_ale

gpmc_nwe

F6

F8

F9

F14

F15

D 1

F15

D 2

F15

gpmc_d[15:0]

gpmc_waitx

Address (LSB)

D 0

D 3

gpmc_io_dir

OUT

030-025

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-6. GPMC/Multiplexed NOR Flash – Synchronous Burst Write

6.4.1.2 GPMC/NOR Flash Interface Asynchronous Timing

Table 6-7 and Table 6-8 assume testing over the recommended operating conditions (see Figure 6-7

through Figure 6-12) and electrical characteristic conditions.

Table 6-5. GPMC/NOR Flash Asynchronous Mode Timing Conditions

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

1.8

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

15.94

pF

Table 6-6. GPMC/NOR Flash Interface Asynchronous Timing – Internal Parameters⁽¹⁾⁽²⁾

NO.

PARAMETER

1.15 V

MAX

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

FI1

FI2

FI3

Maximum output data generation delay from internal

functional clock

6.5

9.1

13.7

ns

Maximum input data capture delay by internal

functional clock

4

5.6

9.1

8.1

Maximum device select generation delay from internal

functional clock

6.5

13.7

(1) The internal parameters table must be used to calculate Data Access Time stored in the corresponding CS register bit field.

(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.

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Table 6-6. GPMC/NOR Flash Interface Asynchronous Timing – Internal Parameters (continued)

NO.

PARAMETER

1.15 V

MAX

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

FI4

FI5

FI6

FI7

FI8

FI9

Maximum address generation delay from internal

functional clock

6.5

100

9.1

13.7

ns

ps

Maximum address valid generation delay from internal

functional clock

9.1

170

13.7

200

Maximum byte enable generation delay from internal

functional clock

Maximum output enable generation delay from internal

functional clock

Maximum write enable generation delay from internal

functional clock

Maximum functional clock skew

Table 6-7. GPMC/NOR Flash Interface Timing Requirements – Asynchronous Mode

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN MAX

MIN

MAX

MIN

MAX

FA5⁽¹⁾

t_acc(DAT)

Data maximum access

time

H⁽²⁾

P⁽⁴⁾

H⁽²⁾

GPMC_FCLK cycles

FA20⁽³⁾t_{acc1-pgmode(DAT)}Page mode successive

P⁽⁴⁾

data maximum access

time

FA21⁽⁵⁾t_{acc2-pgmode(DAT)}Page mode first data

maximum access time

H⁽²⁾

GPMC_FCLK cycles

(1) The FA5 parameter illustrates the amount of time required to internally sample input Data. It is expressed in number of GPMC functional

clock cycles. From start of read cycle and after FA5 functional clock cycles, input Data is internally sampled by active functional clock

edge. FA5 value must be stored inside the AccessTime register bit field.

(2) H = AccessTime * (TimeParaGranularity + 1)

(3) The FA20 parameter illustrates amount of time required to internally sample successive input Page Data. It is expressed in number of

GPMC functional clock cycles. After each access to input Page Data, next input Page Data is internally sampled by active functional

clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.

(4) P = PageBurstAccessTime * (TimeParaGranularity + 1)

(5) The FA21 parameter illustrates amount of time required to internally sample first input Page Data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA21 functional clock cycles, First input Page Data is internally sampled by

active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.

Table 6-8. GPMC/NOR Flash Interface Switching Characteristics – Asynchronous Mode

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

2.0

MIN

MAX

2.0

MIN

MAX

2.0

t_R(DO)

Rise time, output data

ns

t_F(DO)

Fall time, output data

Pulse duration, Read

2.0

FA0

t_W(nBEV)

N⁽¹²⁾

gpmc_nbe0_cl

e, gpmc_nbe1

Write

valid time

FA1

FA3

t_W(nCSV)

Pulse duration, Read

A⁽¹⁾

ns

gpmc_ncsx⁽¹³⁾

Write

v low

t_{d(nCSV-nADVIV)}

Delay time,

gpmc_ncsx⁽¹³⁾

valid to

Read

Write

B⁽²⁾– 0.2

B⁽²⁾+ 2.0

B⁽²⁾– 0.2

B⁽²⁾+ 2.6

B⁽²⁾– 0.2

B⁽²⁾+ 3.7

ns

gpmc_nadv_al

e invalid

FA4

t_{d(nCSV-nOEIV)}

Delay time,

C⁽³⁾– 0.2

C⁽³⁾+ 2.0

C⁽³⁾– 0.2

C⁽³⁾+ 2.6

C⁽³⁾– 0.2

C⁽³⁾+ 3.7

ns

gpmc_ncsx⁽¹³⁾valid to

gpmc_noe invalid

(Single read)

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Table 6-8. GPMC/NOR Flash Interface Switching Characteristics – Asynchronous Mode (continued)

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

FA9

t_d(AV-nCSV)

Delay time, address

J⁽⁹⁾– 0.2

J⁽⁹⁾+ 2.0

J⁽⁹⁾– 0.2

J⁽⁹⁾+ 2.6

J⁽⁹⁾– 0.2

J⁽⁹⁾+ 3.7

ns

bus valid to

gpmc_ncsx⁽¹³⁾valid

FA10 t_d(nBEV-nCSV)

Delay time,

J⁽⁹⁾– 0.2

J⁽⁹⁾+ 2.0

J⁽⁹⁾– 0.2

J⁽⁹⁾+ 2.6

J⁽⁹⁾– 0.2

J⁽⁹⁾+ 3.7

ns

gpmc_nbe0_cle,

gpmc_nbe1 valid to

gpmc_ncsx⁽¹³⁾valid

FA12 t_{d(nCSV-nADVV)}

FA13 t_d(nCSV-nOEV)

FA14 t_{d(nCSV-IODIR)}

FA15 t_{d(nCSV-IODIR)}

FA16 t_w(AIV)

Delay time,

K⁽¹⁰⁾– 0.2 K⁽¹⁰⁾+ 2.0 K⁽¹⁰⁾– 0.2 K⁽¹⁰⁾+ 2.6 K⁽¹⁰⁾– 0.2 K⁽¹⁰⁾+ 3.7

L⁽¹¹⁾– 0.2 L⁽¹¹⁾+ 2.0 L⁽¹¹⁾– 0.2 L⁽¹¹⁾+ 2.6 L⁽¹¹⁾– 0.2 L⁽¹¹⁾+ 3.7

M⁽¹⁴⁾– 0.2 M⁽¹⁴⁾+ 2.0 M⁽¹⁴⁾– 0.2 M⁽¹⁴⁾+ 2.6 M⁽¹⁴⁾– 0.2 M⁽¹⁴⁾+ 3.7

ns

gpmc_ncsx⁽¹³⁾valid to

gpmc_nadv_ale valid

Delay time,

gpmc_ncsx⁽¹³⁾valid to

gpmc_noe valid

Delay time,

gpmc_ncsx⁽¹³⁾valid to

gpmc_io_dir high

Delay time,

gpmc_ncsx⁽¹³⁾valid to

gpmc_io_dir low

Address invalid

duration between 2

successive R/W

accesses

G⁽⁷⁾

FA18 t_{d(nCSV-nOEIV)}

Delay time,

I⁽⁸⁾– 0.2

I⁽⁸⁾+ 2.0

I⁽⁸⁾– 0.2

I⁽⁸⁾+ 2.6

I⁽⁸⁾– 0.2

I⁽⁸⁾+ 3.7

ns

gpmc_ncsx⁽¹³⁾valid to

gpmc_noe invalid

(Burst read)

FA20 t_w(AV)

Pulse duration, address

valid – 2nd, 3rd, and

4th accesses

D⁽⁴⁾

ns

FA25 t_d(nCSV-nWEV)

Delay time,

E⁽⁵⁾– 0.2

F⁽⁶⁾– 0.2

E⁽⁵⁾+ 2.0

F⁽⁶⁾+ 2.0

E⁽⁵⁾– 0.2

F⁽⁶⁾– 0.2

E⁽⁵⁾+ 2.6

F⁽⁶⁾+ 2.6

E⁽⁵⁾– 0.2

F⁽⁶⁾– 0.2

E⁽⁵⁾+ 3.7

F⁽⁶⁾+ 3.7

gpmc_ncsx⁽¹³⁾valid to

gpmc_nwe valid

FA27 t_{d(nCSV-nWEIV)}

Delay time,

gpmc_ncsx⁽¹³⁾valid to

gpmc_nwe invalid

FA28 t_d(nWEV-DV)

FA29 t_d(DV-nCSV)

Delay time, gpmc_ new

valid to data bus valid

2.0

2.6

3.7

ns

Delay time, data bus

valid to gpmc_ncsx⁽¹³⁾

valid

J⁽⁹⁾– 0.2

J⁽⁹⁾+ 2.0

J⁽⁹⁾– 0.2

J⁽⁹⁾+ 2.6

J⁽⁹⁾– 0.2

J⁽⁹⁾+ 3.7

FA37 t_d(nOEV-AIV)

Delay time, gpmc_noe

valid to

2.0

2.6

3.7

ns

gpmc_a[16:1]_d[15:0]

address phase end

(1) For single read: A = (CSRdOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For single write: A = (CSWrOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK with n

being the page burst access number

(2) For reading: B = ((ADVRdOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK

For writing: B = ((ADVWrOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK

(3) C = ((OEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK

(4) D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK

(5) E = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK

(6) F = ((WEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK

(7) G = Cycle2CycleDelay * GPMC_FCLK

(8) I = ((OEOffTime + (n – 1) * PageBurstAccessTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) *

GPMC_FCLK

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(9) J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK

(10) K = ((ADVOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK

(11) L = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK

(12) For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK

For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: N = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst write: N = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

(13) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.

(14) M = ((RdCycleTime - CSOnTime) * (TimeParaGranularity + 1) - 0.5 * CSExtraDelay) * GPMC_FCLK

Above M parameter expression is given as one example of GPMC programming. IO DIR signal will go from IN to OUT after both

RdCycleTime and BusTurnAround completion. Behavior of IO direction signal does depend on kind of successive Read/Write accesses

performed to Memory and multiplexed or non-multiplexed memory addressing scheme, bus keeping feature enabled or not. IO DIR

behavior is automatically handled by GPMC controller. For a full description of the gpmc_io_dir feature, see the OMAP35x Technical

Reference Manual (TRM) [literature number SPRUF98].

GPMC_FCLK

gpmc_clk

FA5

FA1

gpmc_ncsx

FA9

gpmc_a[10:1]

Valid Address

FA0

FA10

gpmc_nbe0_cle

gpmc_nbe1

Valid

FA0

Valid

FA10

FA3

FA12

gpmc_nadv_ale

FA4

FA13

gpmc_noe

gpmc_d[15:0]

Data IN 0

gpmc_waitx

gpmc_io_dir

FA15

FA14

OUT

IN

OUT

030-026

Figure 6-7. GPMC/NOR Flash – Asynchronous Read – Single Word Timing^(1)(2)(3)

(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock

cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge.

FA5 value must be stored inside AccessTime register bit field.

(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

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GPMC_FCLK

gpmc_clk

FA5

FA1

gpmc_ncsx

FA16

FA9

gpmc_a[10:1]

Address 0

FA0

Address 1

FA0

FA10

gpmc_nbe0_cle

gpmc_nbe1

Valid

FA0

Valid

FA0

Valid

FA10

FA3

FA12

FA3

FA12

gpmc_nadv_ale

FA4

FA13

gpmc_noe

Data Upper

gpmc_d[15:0]

gpmc_waitx

gpmc_io_dir

FA15

FA14

OUT

FA14

OUT

IN

030-027

Figure 6-8. GPMC/NOR Flash – Asynchronous Read – 32-bit Timing^(1)(2)(3)

(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock

cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge.

FA5 value must be stored inside AccessTime register bit field.

(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

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GPMC_FCLK

gpmc_clk

FA21

FA20

Add1

FA20

Add3

FA20

FA1

gpmc_ncsx

FA9

gpmc_a[10:1]

Add0

Add2

Add4

FA0

FA10

gpmc_nbe0_cle

FA0

gpmc_nbe1

FA12

gpmc_nadv_ale

FA18

FA13

gpmc_noe

D3

gpmc_d[15:0]

D0

D1

D2

D3

gpmc_waitx

gpmc_io_dir

FA15

FA14

OUT

IN

030-028

Figure 6-9. GPMC/NOR Flash – Asynchronous Read – Page Mode 4x16-bit Timing^(1)(2)(3)(4)

(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

(2) FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by

active functional clock edge. FA21 value must be stored inside AccessTime register bit field.

(3) FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC

functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock edge

after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first input

page data). FA20 value must be stored in PageBurstAccessTime register bit field.

(4) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

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gpmc_fclk

gpmc_clk

FA1

gpmc_ncsx

FA9

gpmc_a[10:1]

gpmc_nbe0_cle

gpmc_nbe1

Valid Address

FA0

FA10

FA0

FA3

FA12

gpmc_nadv_ale

FA27

FA25

gpmc_nwe

gpmc_d[15:0]

gpmc_waitx

gpmc_io_dir

FA29

Data OUT

OUT

030-029

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-10. GPMC/NOR Flash – Asynchronous Write – Single Word Timing

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GPMC_FCLK

gpmc_clk

FA1

FA5

gpmc_ncsx

FA9

gpmc_a[26:17]

Address (MSB)

FA0

FA10

gpmc_nbe0_cle

gpmc_nbe1

Valid

FA0

Valid

FA3

FA12

gpmc_nadv_ale

gpmc_noe

FA4

FA13

FA29

FA37

Data IN

gpmc_a[16:1]_d[15:0]

gpmc_io_dir

Address (LSB)

FA15

FA14

OUT

IN

gpmc_waitx

030-030

Figure 6-11. GPMC/Multiplexed NOR Flash – Asynchronous Read – Single Word Timing^(1)(2)(3)

(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock

cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge.

FA5 value must be stored inside AccessTime register bit field.

(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

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gpmc_fclk

gpmc_clk

FA1

gpmc_ncsx

FA9

gpmc_a[26:17]

gpmc_nbe0_cle

gpmc_nbe1

Address (MSB)

FA0

FA10

FA0

FA3

FA12

gpmc_nadv_ale

FA27

FA25

gpmc_nwe

gpmc_a[16:1]_d[15:0]

gpmc_waitx

FA29

FA28

Valid Address (LSB)

Data OUT

gpmc_io_dir

OUT

030-031

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-12. GPMC/Multiplexed NOR Flash – Asynchronous Write – Single Word Timing

6.4.1.3 GPMC/NAND Flash Interface Timing

Table 6-10 through Table 6-12 assume testing over the recommended operating conditions (see

Figure 6-13 through Figure 6-16) and electrical characteristic conditions.

Table 6-9. GPMC/NAND Flash Asynchronous Mode Timing Conditions

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

1.8

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

15.94

pF

Table 6-10. GPMC/NAND Flash Interface Asynchronous Timing – Internal Parameters⁽¹⁾⁽²⁾

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

GNFI1

GNFI2

Maximum output data generation delay from

internal functional clock

6.5

9.1

13.7

ns

Maximum input data capture delay by internal

functional clock

4

5.6

8.1

(1) Internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.

(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.

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Table 6-10. GPMC/NAND Flash Interface Asynchronous Timing – Internal Parameters (continued)

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

GNFI3

GNFI4

GNFI5

GNFI6

GNFI7

GNFI8

Maximum device select generation delay from

internal functional clock

6.5

9.1

13.7

ns

ps

Maximum address latch enable generation delay

from internal functional clock

6.5

100

9.1

170

13.7

200

Maximum command latch enable generation

delay from internal functional clock

Maximum output enable generation delay from

internal functional clock

Maximum write enable generation delay from

internal functional clock

Maximum functional clock skew

Table 6-11. GPMC/NAND Flash Interface Timing Requirements

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

J⁽²⁾

MIN

MAX

J⁽²⁾

MIN

MAX

J⁽²⁾

GNF12⁽¹⁾t_acc(DAT)

Data maximum access time

GPMC_FCLK

cycles

(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC

functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the

active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.

(2) J = AccessTime * (TimeParaGranularity + 1)

Table 6-12. GPMC/NAND Flash Interface Switching Characteristics

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

t_R(DO)

Rise time, output

data

2.0

ns

t_F(DO)

Fall time, output

data

2.0

GNF0

GNF1

t_w(nWEV)

Pulse duration,

gpmc_nwe valid

time

A⁽¹⁾

t_d(nCSV-nWEV)

t_w(CLEH-nWEV)

t_w(nWEV-DV)

Delay time,

gpmc_ncsx⁽¹³⁾

valid to

B⁽²⁾– 0.2

C⁽³⁾– 0.2

D⁽⁴⁾– 0.2

E⁽⁵⁾– 0.2

F⁽⁶⁾– 0.2

B⁽²⁾+ 2.0

C⁽³⁾+ 2.0

D⁽⁴⁾+ 2.0

E⁽⁵⁾+ 2.0

F⁽⁶⁾+ 2.0

B⁽²⁾– 0.2

C⁽³⁾– 0.2

D⁽⁴⁾– 0.2

E⁽⁵⁾– 0.2

F⁽⁶⁾– 0.2

B⁽²⁾+ 2.6

C⁽³⁾+ 2.6

D⁽⁴⁾+ 2.6

E⁽⁵⁾+ 2.6

F⁽⁶⁾+ 2.6

B⁽²⁾– 0.2

C⁽³⁾– 0.2

D⁽⁴⁾– 0.2

E⁽⁵⁾– 0.2

F⁽⁶⁾– 0.2

B⁽²⁾+ 3.7

C⁽³⁾+ 3.7

D⁽⁴⁾+ 3.7

E⁽⁵⁾+ 3.7

F⁽⁶⁾+ 3.7

ns

gpmc_nwe valid

GNF2

GNF3

GNF4

GNF5

Delay time,

gpmc_nbe0_cle

high to gpmc_nwe

valid

Delay time,

gpmc_d[15:0]

valid to

gpmc_nwe valid

t_w(nWEIV-DIV)

Delay time,

gpmc_nwe invalid

to gpmc_d[15:0]

invalid

t_{w(nWEIV-CLEIV)}

Delay time,

gpmc_nwe invalid

to

gpmc_nbe0_cle

invalid

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Table 6-12. GPMC/NAND Flash Interface Switching Characteristics (continued)

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

GNF6

t_{w(nWEIV-nCSIV)}

t_w(ALEH-nWEV)

t_{w(nWEIV-ALEIV)}

Delay time,

G⁽⁷⁾– 0.2 G⁽⁷⁾+ 2.0

G⁽⁷⁾– 0.2

G⁽⁷⁾+ 2.6 G⁽⁷⁾– 0.2 G⁽⁷⁾+ 3.7

ns

gpmc_nwe invalid

to gpmc_ncsx⁽¹³⁾

invalid

GNF7

GNF8

Delay time,

gpmc_nadv_ale

High to

C⁽³⁾– 0.2

F⁽⁶⁾– 0.2

C⁽³⁾+ 2.0

F⁽⁶⁾+ 2.0

C⁽³⁾– 0.2

F⁽⁶⁾– 0.2

C⁽³⁾+ 2.6

F⁽⁶⁾+ 2.6

C⁽³⁾– 0.2

F⁽⁶⁾– 0.2

C⁽³⁾+ 3.7

F⁽⁶⁾+ 3.7

ns

gpmc_nwe valid

Delay time,

gpmc_nwe invalid

to

gpmc_nadv_ale

invalid

GNF9

t_c(nWE)

Cycle time, Write

cycle time

H⁽⁸⁾

ns

GNF10

t_d(nCSV-nOEV)

Delay time,

gpmc_ncsx⁽¹³⁾

valid to gpmc_noe

valid

I⁽⁹⁾– 0.2

I⁽⁹⁾+ 2.0

I⁽⁹⁾– 0.2

I⁽⁹⁾+ 2.6

I⁽⁹⁾– 0.2

I⁽⁹⁾+ 3.7

GNF13

t_w(nOEV)

Pulse duration,

gpmc_noe valid

time

K⁽¹⁰⁾

ns

GN F14

GNF15

t_c(nOE)

Cycle time, Read

cycle time

L⁽¹¹⁾

ns

t_{w(nOEIV-nCSIV)}

Delay time,

M⁽¹²⁾– 0.2 M⁽¹²⁾+ 2.0 M⁽¹²⁾– 0.2 M⁽¹²⁾+ 2.6 M⁽¹²⁾– 0.2 M⁽¹²⁾+ 3.7

gpmc_noe invalid

to gpmc_ncsx⁽¹³⁾

invalid

(1) A = (WEOffTime – WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

(2) B = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK

(3) C = ((WEOnTime – ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – ADVExtraDelay)) * GPMC_FCLK

(4) D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay ) * GPMC_FCLK

(5) E = ((WrCycleTime – WEOffTime) * (TimeParaGranularity + 1) – 0.5 * WEExtraDelay ) * GPMC_FCLK

(6) F = ((ADVWrOffTime – WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – WEExtraDelay )) * GPMC_FCLK

(7) G = ((CSWrOffTime – WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – WEExtraDelay )) * GPMC_FCLK

(8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK

(9) I = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK

(10) K = (OEOffTime – OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK

(11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK

(12) M = ((CSRdOffTime – OEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – OEExtraDelay )) * GPMC_FCLK

(13) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.

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GPMC_FCLK

gpmc_ncsx

GNF1

GNF2

GNF6

GNF5

gpmc_nbe0_cle

gpmc_nadv_ale

gpmc_noe

GNF0

gpmc_nwe

GNF3

GNF4

gpmc_a[16:1]_d[15:0]

Command

030-032

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.

Figure 6-13. GPMC/NAND Flash – Command Latch Cycle Timing

GPMC_FCLK

gpmc_ncsx

GNF1

GNF7

GNF6

GNF8

gpmc_nbe0_cle

gpmc_nadv_ale

gpmc_noe

GNF9

GNF0

gpmc_nwe

GNF3

GNF4

gpmc_a[16:1]_d[15:0]

Address

030-033

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.

Figure 6-14. GPMC/NAND Flash – Address Latch Cycle Timing

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GPMC_FCLK

GNF12

GNF10

GNF15

gpmc_ncsx

gpmc_nbe0_cle

gpmc_nadv_ale

GNF14

GNF13

gpmc_noe

gpmc_a[16:1]_d[15:0]

DATA

gpmc_waitx

030-034

Figure 6-15. GPMC/NAND Flash – Data Read Cycle Timing^(1)(2)(3)

(1) The GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional

clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data is internally sampled by active functional clock

edge. The GNF12 value must be stored inside AccessTime register bit field.

(2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

(3) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0 ,1, 2, or 3.

GPMC_FCLK

GNF1

GNF6

gpmc_ncsx

gpmc_nbe0_cle

gpmc_nadv_ale

gpmc_noe

GNF9

GNF0

gpmc_nwe

GNF3

GNF4

gpmc_a[16:1]_d[15:0]

DATA

030-035

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0 or 1.

Figure 6-16. GPMC/NAND Flash – Data Write Cycle Timing

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6.4.2 SDRAM Controller Subsystem (SDRC)

The SDRAM controller subsystem (SDRC) module provides connectivity between the OMAP3525 and

OMAP3530 Applications Processors and external DRAM memory components. The SDRC module only

supports low-power double-data-rate (LPDDR) SDRAM devices. Memory devices can be interfaced to the

SDRC using a stacked-memory approach or through the printed circuit board (PCB). The stacked-memory

approach uses the package on package interface pins (available on CBB & CBC package).

6.4.2.1 SDRAM Controller Subsystem Device-Specific Information

The approach to specifying interface timing for the SDRC memory bus is different than on other interfaces

such as the general-purpose memory controller (GPMC) and the multi-channel buffered serial ports

(McBSPs). For these other interfaces the device timing was specified in terms of data manual

specifications and I/O buffer information specification (IBIS) models.

For the SDRC memory bus, the approach is to specify compatible memory devices and provide the

printed circuit board (PCB) solution and guidelines directly to the user. Texas Instruments (TI) has

performed the simulation and system characterization to ensure all interface timings in this solution are

met.

6.4.2.2 LPDDR Interface

The LPDDR interface is balled out on the bottom side of all OMAP35x packages and on the top side of

OMAP35x POP packages. The LPDDR interface on the top of the POP package has been designed for

compatibility any POP LPDDR device with a matching footprint and compliance with the JEDEC

LPDDR-266 specification.

This section provides the timing specification for the bottom-side LPDDR interface as a PCB design and

manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal

integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable LPDDR memory

system without the need for a complex timing closure process. For more information regarding guidelines

for using this LPDDR specification, see the Understanding TI's PCB Routing Rule-Based DDR Timing

Specification Application Report (literature number SPRAAV0).

6.4.2.2.1 LPDDR Interface Schematic

Figure 6-17 and Figure 6-18 show the LPDDR interface schematics for a LPDDR memory system. The 1

x16 LPDDR system schematic is identical to Figure 6-17 except that the high word LPDDR device is

deleted.

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OMAP35x

LPDDR

DQ0

T

sdrc_d0

T

sdrc_d7

DQ7

T

sdrc_dm0

LDM

LDQS

DQ8

T

sdrc_dqs0

T

sdrc_d8

T

sdrc_d15

DQ15

UDM

T

sdrc_dm1

T

sdrc_dqs1

UDQS

LPDDR

T

sdrc_d16

DQ0

T

sdrc_d23

sdrc_dm2

sdrc_dqs2

sdrc_d24

DQ7

LDM

LDQS

DQ8

T

sdrc_d31

sdrc_dm3

sdrc_dqs3

sdrc_ba0

sdrc_ba1

sdrc_a0

DQ15

UDM

UDQS

BA0

BA1

A0

T

BA0

BA1

A0

T

sdrc_a14

sdrc_ncs0

sdrc_ncs1

sdrc_ncas

sdrc_nras

sdrc_nwe

sdrc_cke0

sdrc_cke1

sdrc_clk

A14

CS

A14

CS

N/C

T

CAS

RAS

WE

CAS

RAS

WE

CKE

N/C

T

CK

T

sdrc_nclk

Figure 6-17. OMAP35x LPDDR High Level Schematic (x16 memories)

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sdrc_d0

LPDDR

T

DQ0

T

sdrc_d7

sdrc_dm0

sdrc_dqs0

sdrc_d8

DQ7

T

DM0

T

DQS0

T

DQ8

T

sdrc_d15

sdrc_dm1

sdrc_dqs1

DQ15

T

DM1

T

DQS1

T

sdrc_d16

DQ16

T

sdrc_d23

sdrc_dm2

sdrc_dqs2

sdrc_d24

DQ23

T

DM2

T

DQS2

T

DQ24

T

sdrc_d31

sdrc_dm3

sdrc_dqs3

sdrc_ba0

sdrc_ba1

sdrc_a0

DQ31

T

DM3

T

DQS3

T

BA0

T

BA1

T

A0

T

sdrc_a14

sdrc_ncs0

sdrc_ncs1

sdrc_ncas

sdrc_nras

sdrc_nwe

sdrc_cke0

sdrc_cke1

sdrc_clk

A14

T

CS

N/C

T

CAS

T

RAS

T

WE

T

CKE

N/C

T

CK

T

sdrc_nclk

CK

Figure 6-18. OMAP35x LPDDR High Level Schematic (x32 memory)

6.4.2.2.2 Compatible JEDEC LPDDR Devices

Table 6-13 shows the parameters of the JEDEC LPDDR devices that are compatible with this interface.

Generally, the LPDDR interface is compatible with x16 and x32 LPDDR266 and LPDDR333 speed grade

LPDDR devices.

Table 6-13. Compatible JEDEC LPDDR Devices

NO.

PARAMETER

MIN

MAX

UNIT

NOTES

JEDEC LPDDR Device Speed

Grade

(1)

(2)

1

LPDDR-266

See Note

2

3

JEDEC LPDDR Device Bit Width

JEDEC LPDDR Device Count

16

1

32

2

Bits

Devices

See Note

JEDEC LPDDR Device Ball

Count

4

60

90

Balls

(1) Higher LPDDR speed grades are supported due to inherent JEDEC LPDDR backwards compatibility.

(2) 1 x16 LPDDR device is used for 16 bit LPDDR memory system. 1x32 or 2x16 LPDDR devices are used for a 32-bit LPDDR memory

system.

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6.4.2.2.3 PCB Stackup

The minimum stackup required for routing the OMAP35x is a six layer stack as shown in Table 6-14.

Additional layers may be added to the PCB stack up to accommodate other circuity or to reduce the size

of the PCB footprint.

Table 6-14. OMAP35x Minimum PCB Stack Up

LAYER

TYPE

Signal

Plane

Signal

Plane

Signal

DESCRIPTION

Top Routing Mostly Horizontal

Ground

1

2

3

4

5

6

Power

Internal Routing

Ground

Bottom Routing Mostly Vertical

Table 6-15. PCB Stack Up Specifications

NO.

1

PARAMETER

MIN

6

TYP

MAX

UNIT

NOTES

PCB Routing/Plane Layers

Signal Routing Layers

2

3

Full ground layers under LPDDR routing region

2

4

Number of ground plane cuts allowed within LPDDR routing region

0

Number of ground reference planes required for each LPDDR routing 1

layer

5

6

1

Number of layers between LPDDR routing layer and reference ground 0

plane

7

PCB Routing Feature Size

PCB Trace Width w

4

Mils

8

9

PCB BGA escape via pad size

PCB BGA escape via hole size

Device BGA Pad Size

18

8

10

11

12

13

14

See Note⁽¹⁾

See Note⁽²⁾

LPDDR Device BGA Pad Size

Single Ended Impedance, ZO

Impedance Control

50

75

Ω

Z-5

Z

Z + 5

See Note⁽³⁾

(1) Please see the Flip Chip Ball Grid Array Package Reference Guide (literature number SPRU811) for device BGA pad size.

(2) Please see the LPDDR device manufacturer documentation for the LPDDR device BGA pad size.

(3) Z is the nominal singled ended impedance selected for the PCB specified by item 12.

6.4.2.3 Placement

Figure 6-19 shows the required placement for the OMAP35x device as well as the LPDDR devices. The

dimensions for Figure 6-19 are defined in Table 6-16. The placement does not restrict the side of the PCB

that the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace

lengths and allow for proper routing space. For 1x16 and 1x32 LPDDR memory systems, the second

LPDDR device is omitted from the placement.

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X

A1

Y

OFFSET

LPDDR

Device

Y

OMAP

OFFSET

A1

Recommended LPDDR Device

Orientation

Figure 6-19. OMAP35x and LPDDR Device Placement

Table 6-16. Placement Specifications

NO.

1

PARAMETER

MIN

MAX

1440

1030

525

UNIT

Mils

NOTES

See Notes⁽¹⁾

(2)

X

,

2

Y

3

Y Offset

See Notes^{(1) (2) (3)}

, ,

4

LPDDR Keepout Region

See Note⁽⁴⁾

Clearance from non-LPDDR signal to LPDDR

Keepout Region

5

4

w

See Note⁽⁵⁾

(1) See Figure 6-17 for dimension definitions.

(2) Measurements from center of device to center of LPDDR device.

(3) For 16 bit memory systems it is recommended that Y Offset be as small as possible.

(4) LPDDR keepout region to encompass entire LPDDR routing area.

(5) Non-LPDDR signals allowed within LPDDR keepout region provided they are separated from LPDDR routing layers by a ground plane.

6.4.2.4 LPDDR Keep Out Region

The region of the PCB used for the LPDDR circuitry must be isolated from other signals. The LPDDR

keep out region is defined for this purpose and is shown in Figure 6-20. The size of this region varies with

the placement and LPDDR routing. Additional clearances required for the keep out region are shown in

Table 6-16.

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A1

LPDDR Device

A1

Region should encompass all LPDDR circuitry and varies depending

on placement. Non-LPDDR signals should not be routed on the

LPDDR signal layers within the LPDDR keep out region. Non-LPDDR

signals may be routed in the region provided they are routed on

layers separated from LPDDR signal layers by a ground layer. No

breaks should be allowed in the reference ground layers in this

region. In addition, the 1.8 V power plane should cover the entire keep

out region.

Figure 6-20. LPDDR Keepout Region

6.4.2.5 Net Classes

Table 6-17 lists the clock net classes for the LPDDR interface. Table 6-18 lists the signal net classes, and

associated clock net classes, for the signals in the LPDDR interface. These net classes are used for the

termination and routing rules that follow.

Table 6-17. Clock Net Class Definitions

CLOCK NET CLASS

OMAP PIN NAMES

sdrc_clk/sdrc_nclk

sdrc_dqs0

CK

DQS0

DQS1

DQS2

DQS3

sdrc_dqs1

sdrc_dqs2

sdrc_dqs3

Table 6-18. Signal Net Class Definitions

CLOCK NET CLASS

ASSOCIATED CLOCK NET CLASS

OMAP PIN NAMES

sdrc_ba, sdrc_a, sdrc_ncs0, sdrc_ncas,

sdrc_nras, sdrc_nwe, sdrc_cke0

ADDR_CTRL

CK

DQ0

DQ1

DQ2

DQ3

DQS0

DQS1

DQS2

DQS3

sdrc_d, sdrc_dm0

sdrc_d, sdrc_dm1

sdrc_d, sdrc_dm2

sdrc_d, sdrc_dm3

6.4.2.6 LPDDR Signal Termination

No terminations of any kind are required in order to meet signal integrity and overshoot requirements.

Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only

type permitted. Table 6-19 shows the specifications for the series terminators.

Table 6-19. LPDDR Signal Terminations

NO.

PARAMETER

MIN

TYP

MAX

UNIT

NOTES

1

CK Net Class

0

10

Ω

See Note⁽¹⁾

(1) Only series termination is permitted, parallel or SST specifically disallowed.

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Table 6-19. LPDDR Signal Terminations (continued)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

NOTES

See Notes^{(1) (2) (3)}

2

ADDR_CTRL Net Class

0

22

Zo

Ω

,

Data Byte Net Classes

(DQS0-DQS3, DQ0-DQ3)

3

0

22

Zo

Ω

See Notes^{(1) (2) (3)}

, ,

(2) Terminator values larger than typical only recommended to address EMI issues.

(3) Termination value should be uniform across net class.

6.4.2.7 LPDDR CK and ADDR_CTRL Routing

Figure 6-21 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a

balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A

should be maximized.

A1

T

A

OMAP

A1

Figure 6-21. CK and ADDR_CTRL Routing and Topology

Table 6-20. CK and ADDR_CTRL Routing Specification

NO.

1

PARAMETER

MIN

TYP

MAX

2w

UNIT

NOTES

Center to Center CK-CK spacing

CK A to B/A to C Skew Length Mismatch

CK B to C Skew Length Mismatch

2

25

Mils

See Note⁽¹⁾

3

25

Center to Center CK to other

LPDDR trace spacing

4

4w

See Note⁽²⁾

See Note⁽³⁾

5

6

CK/ADDR_CTRL nominal trace length

CACLM-50

CACLM

CACLM+50

100

Mils

ADDR_CTRL to CK Skew Length Mismatch

ADDR_CTRL to ADDR_CTRL

Skew Length Mismatch

7

8

9

100

Mils

Center to Center ADDR_CTRL to other

LPDDR trace 4w spacing

4w

3w

See Note⁽²⁾

See Note⁽¹⁾

Center to Center ADDR_CTRL to other

ADDR_CTRL 3w trace spacing

ADDR_CTRL A to B/A to C Skew Length

Mismatch

10

11

100

Mils

ADDR_CTRL B to C Skew Length Mismatch

(1) Series terminator, if used, should be located closest to device.

(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing

congestion.

(3) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.

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Figure 6-22 shows the topology and routing for the DQS and DQ net classes; the routes are point to point.

Skew matching across bytes is not needed nor recommended.

T

E0

A1

T

E1

OMAP

T

E2

A1

T

E3

Figure 6-22. DQS and DQ Routing and Topology

Table 6-21. DQS and DQ Routing Specification⁽¹⁾

NO.

PARAMETER

MIN

TYP

MAX

UNIT

NOTES

2

DQS E Skew Length Mismatch

25

Mils

Center to Center DQS to other LPDDR

trace spacing

3

4w

See Note⁽²⁾

See Note⁽³⁾

4

5

6

DQS/DQ nominal trace length

DQ to DQS Skew Length Mismatch

DQ to DQ Skew Length Mismatch

DQLM - 50

DQLM

DQLM + 50

100

Mils

100

Center to Center DQ to other LPDDR

trace spacing

7

4w

3w

See Note⁽²⁾

Center to Center DQ to other DQ trace

spacing

8

9

See Note^{(2) (4)}

,

DQ E Skew Length Mismatch

100

Mils

(1) Series terminator, if used, should be located closest to LPDDR.

(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing

congestion.

(3) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing

congestion.

(4) DQLM is the longest Manhattan distance of the DQS and DQ net classes.

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6.5 Video Interfaces

6.5.1 Camera Interface

The camera subsystem provides the system interfaces and the processing capability to connect raw, YUV,

or JPEG image sensor modules to the OMAP3525 and OMAP3530 devices for video-preview,

video-record, and still-image-capture applications. The camera subsystem supports up to two

simultaneous pixel flows but only one of them can use the video processing hardware:

•

PARALLEL: the parallel interface data must go through the video processing hardware.

6.5.1.1 First Camera Serial Interface (CSI2) Timing

First camera serial interface is a MIPI (MIPI CSI2) D-PHY compliant interface connecting a digital camera

module and a mobile phone application. This interface is made of three differential lanes, each of them

being configurable for carrying data or clock. The polarity of each wire of a lane is also configurable.

6.5.1.1.1 Camera Serial Interface in High-Speed Mode

Table 6-23 assumes testing over the recommended operating conditions and electrical characteristic

conditions (see Figure 6-23).

Table 6-22. Camera Serial Intrerface Timing Conditions – High-Speed Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

MIN

MAX

Input Conditions

(1)

t_R

t_F

Input signal rise time

Input signal fall time

0.15

0.4*t_UIINST

ns

(1) For t_UIINSTtiming, please refer to the CS2, CS3, and CS6 parameters defined in Table 6-23

Table 6-23. Camera Serial Interface Timing Requirements – High-Speed Mode⁽¹⁾

NO.

PARAMETER＝

OPP3

OPP2

UNIT

MIN

2.5

MAX

MIN

2.5

MAX

CS1

t_c(clk)

Cycle time⁽²⁾, input clock period

25.0

ns

CS2,

CS3

t_UI(INST,MIN)

Minimum instantaneous unit interval

1.15

CS4

CS5

CS6

t_su(dV-clkH)

t_h(clkH-dV)

Setup time, data valid before clock rising edge

Hold time, data valid after clock rising edge

Minimum instantaneous bit duration

0.172

1.15

0.172

1.15

ns

t_UI(INST,MIN)

(1) The timing requirements are assured up to the minimum instantaneous bit duration.

(2) Related with the input maximum frequency supported by the CSI2 module.

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CS1

CS3

CS2

csi2a_dwi

CS4

CS5

CS6

csi2a_dwi

Data (j-1)

Data_j

Data_k

Data_(j+1)

CS6

Data_(k-1)

Data_(k+1)

030-053

Figure 6-23. Camera Serial Interface Timing Requirements – High-Speed Mode^(1)(2)(3)(4)

(1) w = x and y

(2) I = 0 to 2

(3) The use of each csi2_dwi⁽¹⁾lane (clock or data) is software programmable with the CSI2_COMPLEXIO_CFG1 register, by setting bit

field CLOCK_POSITION to 0x1, 0x2, or 0x3.

(4) The polarity of each csi2_dwi⁽¹⁾lane is software programmable with the CSI2_COMPLEXIO_CFG1 register, DATAi_POL⁽²⁾bit field.

6.5.1.1.2 Camera Serial Interface in Low-Power Mode and Ultralow-Power Mode

Table 6-25 assumes testing over the recommended operating conditions and electrical characteristic

conditions (see Figure 6-24).

Table 6-24. Camera Serial Interface Timing Conditions – Low-Power Mode and Ultralow-Power Mode⁽¹⁾

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

t_F

Input signal rise time

Input signal fall time

25

ns

(1) Low-power and ultralow-power communication modes are asynchronous, data is Spaced-One-Hot bit encoded, data transfer clock is

recovered by means of an XOR between csi2a_dxi and csi2a_dxi.

Table 6-25. Camera Serial Interface Timing Requirements – Low-Power and Ultralow-Power Mode⁽¹⁾

NO.

PARAMETER＝

1.35 V

1.20 V

UNIT

MIN

MAX

MIN

MAX

CS7

t_v(LPsate)

Duration of a low-Power

state⁽¹⁾

50

ns

(1) Low-power and ultralow-power communication modes are asynchronous, data is Spaced-One-Hot bit encoded, data transfer clock is

recovered by means of an XOR between csi2a_dxi and csi2a_dxi.

CS7

csi2a_dxi

mark_j-1

space_j-1

mark_j

space_j

mark_j+1

CS7

mark_k

csi2a_dyi

mark_k-1

space_k-1

space_k

mark_k+1

030-054

Figure 6-24. Camera Serial Interface Timing Requirements – Low-Power and Ultralow-Power Mode⁽¹⁾⁽²⁾

(1) I = 0, 1, or 2

(2) Low-power and ultralow-power communication modes are asynchronous, data is Spaced-One-Hot bit encoded, data transfer clock is

recovered by means of an XOR between csi2a_dxi and csi2a_dyi.

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6.5.1.2 Second Camera Serial Interface (CSIb) Timing

Second camera serial interface is a MIPI serial interface supporting following input data formats: YUV420,

YUV422, RGB444, RGB565, RGB888, RAW8, RAW10, RAW12, and JPEG8. Clock and data are

transferred on a differential SubLVDS link.

Table 6-27 assumes testing over the recommended operating conditions and electrical characteristic

conditions (see Figure 6-25).

Table 6-26. CSIb Timing Conditions

TIMING CONDITION PARAMETER

CSIb – Class 0 Input Conditions

VALUE

UNIT

t_R

t_F

Input signal rise time

Input signal fall time

0.50

ns

CSIb – Class 1 Input Conditions

t_R

t_F

Input signal rise time

Input signal fall time

0.40

ns

CSIb – Class 2 Input Conditions

t_R

Input signal rise time

0.40

ns

t_F

Input signal fall time

Output Condition

C_LOAD

Output load capacitance

20

pF

Table 6-27. CSIb Timing Requirements⁽³⁾⁽⁴⁾

NO.

PARAMETER

OPP3

OPP2

UNIT

MIN

MAX

MIN

MAX

CSIb – Class 0

CS0

t_c(STRB)

t_w(STRB)

Cycle time, csib_strbp/csib_strbn⁽²⁾

4.8

0.45*P⁽¹⁾

4.8

0.45*P⁽¹⁾

ns

CS1/

CS2

Pulse duration, csib_strbp/csib_strbn high/low

duration

0.55*P⁽¹⁾

CS3

t_{su(DATV-STRBH)}Setup time, csib_datp/csib_datn valid before

csib_strbp/csib_strbn rising edge

0.6

2

0.6

2

ns

CS4

t_{h(STRBH-DATV)}Hold time, csib_datp/csib_datn valid after

csib_strbp/csib_strbn rising edge

CSIb – Class 1

Cycle time, csib_strbp/csib_strbn⁽²⁾

Stable duration, csib_strbp/csib_strbn

CS10

CS11

CS12

t_c(STRB)

t_w(STRB)

4.8

0.45*P⁽¹⁾

1.3

4.8

0.45*P⁽¹⁾

1.3

ns

0.55*P⁽¹⁾

t_{s(DATV-STRBH)}Skew time, csib_datp/csib_datn valid before

csib_strbp/csib_strbn rising edge

CS13

t_{s(STRBF-DATV)}Skew time, csib_datp/csib_datn valid after

csib_strbp/csib_strbn falling edge

1.3

ns

CSIb – Class 2

Cycle time, csib_strbp/csib_strbn⁽²⁾

Stable duration, csib_strbp/csib_strbn

CS10

CS11

CS12

t_c(STRB)

t_w(STRB)

3.1

0.45*P⁽¹⁾

0.7

3.1

0.45*P⁽¹⁾

0.7

ns

0.55*P⁽¹⁾

t_{s(DATV-STRBH)}Skew time, csib_datp/csib_datn valid before

csib_strbp/csib_strbn rising edge

CS13

t_{s(STRBF-DATV)}Skew time, csib_datp/csib_datn valid after

csib_strbp/csib_strbn falling edge

0.7

ns

(1) P = csib_strbp/csib_strbn period in ns.

(2) The maximum clock frequency of the CSI must be chosen to be the lowest possible for the application / transmitting device in order to

reduce the power consumption of the sensor, the IO pad of the device and the camera core module itself.

(3) The input timing requirements are given by considering a rising, or a falling, time of 0.50 ns for Class 0, 0.40 ns for Class 1 and Class 2.

(4) See DM Operating Condition Addendum for OPP voltages.

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Table 6-28. CSIb Switching Characteristics⁽³⁾⁽⁴⁾

NO.

PARAMETER

OPP3

OPP2

UNIT

MIN

MAX

MIN

MAX

CSIb – Class 0

CS5

t_c(XCLK)

t_w(XCLK)

Cycle time, cam_xclkb⁽²⁾

Pulse duration, cam_xclkb⁽²⁾high or low duration

4.6

ns

CS6/CS7

0.45*PO⁽¹⁾0.55*PO⁽¹⁾0.45*PO⁽¹⁾0.55*PO⁽¹⁾

CSIb – Class ＝

CS14

t_c(XCLK)

Cycle time, cam_xclkb⁽²⁾

Pulse duration, cam_xclkb⁽²⁾high or low duration

4.6

ns

CS15/CS16 t_w(XCLK)

0.45*PO⁽¹⁾0.55*PO⁽¹⁾0.45*PO⁽¹⁾0.55*PO⁽¹⁾

(1) PO = cam_xclkb period in ns. The duty cycle generated depends on the mode selected with the register TCTRL_CTRL[9:5] DIVB. For

more information, see the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98

(2) The cam_xclkb frequency is programmable by setting the configuration register TCTRL_CTRL[9:5] DIVB.

Caution: You must disable the camera sensor or the camera module to change the frequency configuration. For more information, see

the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98

(3) The capacitive load is equilvalent to 20 pf.

(4) See DM Operating Condition Addendum for OPP voltages.

CS0

CS1

CS2

csib_strb

csib_dat

CS3

CS4

Bit 0

Bit 6

Bit 7

CS5

CS6

CS7

cam_xclkb

030-055

Figure 6-25. Camera Serial Interface (CSIb) – Class 0^(1)(2)(3)

(1) csib_strb and csib_dat are the result of low-voltage differential data signal converters (see the Camera Subsystem section of the

OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98).

(2) The CSI receives up to 208 Mbps data rate or data/clock transmission.

(3) The CSI supports YUV422, YUV420, Bayer RGB444, RGB565, RGB888, RAW Bayer 6-, 7-, 8-, 10-, and 12-bit, and JPEG8 input data

formats.

CS10

CS11

csib_strb

csib_dat

CS12

CS13

CS14

CS15

CS16

cam_xclkb

030-119

Figure 6-26. Camera Serial Interface (CSIb) – Class 1/2^(1)(2)(3)

(1) csib_strb and csib_dat are the result of low-voltage differential data signal converters (see the Camera Subsystem section of the

OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98).

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(2) The CSI receives up to 208 Mbps data rate or data/clock transmission and up to 416 or 650 Mbps data rate for data/strobe

transmission.

(3) The CSI supports YUV422, YUV420, Bayer RGB444, RGB565, RGB888, RAW Bayer 6-, 7-, 8-, 10-, and 12-bit, and JPEG8 input data

format.

6.5.1.3 Parallel Camera Interface Timing

The parallel camera interface is a 12-bit interface which can be used in two modes:

1. SYNC mode: progressive and interlaced image sensor modules for 8-, 10-, 11-, and 12-bit data. The

pixel clock can be up to 75 MHz in 12-bit mode. The pixel clock can be up to 130 MHz in 8-bit packed

mode.

2. ITU mode provides an ITU-R BT 656 compatible data stream with progressive image sensor modules

only in 8- and 10-bit configurations. The pixel clock can be up to 75 MHz.

6.5.1.3.1 SYNC Normal Mode

6.5.1.3.1.1 12-Bit SYNC Normal – Progressive Mode

Table 6-30 and Table 6-31 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-27).

Table 6-29. ISP Timing Conditions – 12-Bit SYNC Normal – Progressive Mode

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

2.7

ns

t_F

Output Condition

C_LOAD

Output load capacitance

8.6

pF

Table 6-30. ISP Timing Requirements – 12-Bit SYNC Normal – Progressive Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

ISP17

ISP18

t_c(pclk)

Cycle time⁽²⁾, cam_pclk period

Typical pulse duration, cam_pclk high

Typical pulse duration, cam_pclk low

Duty cycle error, cam_pclk

13.3

22.2

ns

ps

ns

t_W(pclkH)

t_W(pclkL)

t_dc(pclk)

t_j(pclk)

0.5*P⁽³⁾

667

133

1111

200

Cycle jitter⁽⁴⁾, cam_pclk

ISP19

ISP20

ISP21

t_su(dV-pclkH)

Setup time, cam_d[11:0] valid before cam_pclk rising

edge

1.82

3.25

t_h(pclkH-dV)

t_su(dV-vsH)

Hold time, cam_d[11:0] valid after cam_pclk rising

edge

ns

Setup time, cam_vs valid before cam_pclk rising

edge

ISP22

ISP23

t_h(pclkH-vsV)

t_su(dV-hsH)

Hold time, cam_vs valid after cam_pclk rising edge

1.82

3.25

ns

Setup time, cam_hs valid before cam_pclk rising

edge

ISP24

ISP25

t_h(pclkH-hsV)

t_su(dV-hsH)

Hold time, cam_hs valid after cam_pclk rising edge

1.82

3.25

ns

Setup time, cam_wen valid before cam_pclk rising

edge

ISP26

t_h(pclkH-hsV)

Hold time, cam_wen valid after cam_pclk rising edge

1.82

3.25

ns

(1) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.

(2) Related with the input maximum frequency supported by the ISP module.

(3) P = cam_pclk period in ns

(4) Maximum cycle jitter supported by cam_pclk input clock.

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Table 6-31. ISP Switching Characteristics – 12-Bit SYNC Normal – Progressive Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

ISP15

ISP16

t_c(xclk)

Cycle time⁽¹⁾, cam_xclk period

Typical pulse duration, cam_xclk high

Typical pulse duration, cam_xclk low

Duty cycle error, cam_xclk

4.6

ns

ps

ns

t_W(xclkH)

t_W(xclkL)

t_dc(xclk)

t_j(xclk)

0.5*PO⁽²⁾

231

Jitter standard deviation⁽³⁾, cam_xclk

33

t_R(xclk)

t_F(xclk)

Rise time, cam_xclk

0.93

Fall time, cam_xclk

(1) Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module.

Warning: The camera sensor or the camera module must be disabled to change the frequency configuration. For more information, see

the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]

(2) PO = cam_xclk period in ns

(3) The jitter probability density can be approximated by a Gaussian function.

ISP16

ISP15

ISP16

cam_xclki

cam_pclk

cam_vs

ISP17

ISP18

ISP19

ISP20

ISP22

ISP21

cam_hs

ISP23

D(n-1)

ISP24

D(1)

cam_d[11:0]

D(0)

D(n-3) D(n-2)

D(0)

D(n-1)

ISP25

ISP26

cam_wen

cam_fld

030-056

Figure 6-27. ISP – 12-Bit SYNC Normal – Progressive Mode^{(1)(2)(3)(4)(5)(6)(7)(8)}

(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. If the cam_hs, cam_vs, and cam_fld signals are output, the

signal length can be set.

(2) The parallel camera in SYNC mode supports progressive image sensor modules and 8-, 10-, 11-, or 12-bit data.

(3) When the image sensor has fewer than 12 data lines, it must be connected to the lower data lines and the unused lines must be

grounded.

(4) However, it is possible to shift the data to 0, 2, or 4 data internal lanes.

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(5) The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode, cam_d[11:2] or cam_d[9:0] in 10-bit mode, cam_d[10:0] in 11-bit

mode, and cam_d[11:0] in 12-bit mode.

(6) Optionally, the data write to memory can be qualified by the external cam_wen signal.

(7) The cam_wen signal can be used as a external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and

cam_wen signals are asserted.

(8) In cam_xclki; I is equal to a or b.

6.5.1.3.1.2 8-bit Packed SYNC – Progressive Mode

Table 6-33 and Table 6-34 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-28).

Table 6-32. ISP Timing Conditions – 8-bit Packed SYNC – Progressive Mode

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

2.5

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

8.6

pF

Table 6-33. ISP Timing Requirements – 8-bit Packed SYNC – Progressive Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

ISP3

ISP4

t_c(pclk)

Cycle time⁽²⁾, cam_pclk period

Typical pulse duration, cam_pclk high

Typical pulse duration, cam_pclk low

Duty cycle error, cam_pclk

7.7

15.4

ns

ps

ns

t_W(pclkH)

t_W(pclkL)

t_dc(pclk)

t_j(pclk)

0.5*P⁽³⁾

385

83

769

167

Cycle jitter⁽⁴⁾, cam_pclk

ISP5

ISP6

ISP7

t_su(dV-pclkH)

Setup time, cam_d[11:0] valid before cam_pclk

rising edge

1.08

2.27

t_h(pclkH-dV)

t_su(dV-vsH)

Hold time, cam_d[11:0] valid after cam_pclk rising

edge

ns

Setup time, cam_vs valid before cam_pclk rising

edge

ISP8

ISP9

t_h(pclkH-vsV)

t_su(dV-hsH)

Hold time, cam_vs valid after cam_pclk rising edge

1.08

2.27

ns

Setup time, cam_hs valid before cam_pclk rising

edge

ISP10

ISP11

t_h(pclkH-hsV)

t_su(dV-hsH)

Hold time, cam_hs valid after cam_pclk rising edge

1.08

2.27

ns

Setup time, cam_wen valid before cam_pclk rising

edge

ISP12

t_h(pclkH-hsV)

Hold time, cam_wen valid after cam_pclk rising edge

1.08

2.27

ns

(1) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.

(2) Related with the input maximum frequency supported by the ISP module.

(3) P = cam_pclk period in ns.

(4) Maximum cycle jitter supported by cam_pclk input clock.

Table 6-34. ISP Switching Characteristics – 8-bit packed SYNC – Progressive Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

ISP1

ISP2

t_c(xclk)

Cycle time⁽¹⁾, cam_xclk period

4.6

ns

t_W(xclkH)

Typical pulse duration, cam_xclk high

0.5*PO⁽²⁾

(1) Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module.

Warning: You must disable the camera sensor or the camera module to change the frequency configuration. For more information, see

the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98

(2) PO = cam_xclk period in ns

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Table 6-34. ISP Switching Characteristics – 8-bit packed SYNC – Progressive Mode (continued)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

0.5*PO⁽²⁾

MIN

MAX

0.5*PO⁽²⁾

ISP2

t_W(xclkL)

t_dc(xclk)

t_j(xclk)

Typical pulse duration, cam_xclk low

Duty cycle error, cam_xclk

Jitter standard deviation⁽³⁾, cam_xclk

Rise time, cam_xclk

ns

ps

ns

231

67

231

67

t_R(xclk)

t_F(xclk)

0.93

Fall time, cam_xclk

(3) The jitter probability density can be approximated by a Gaussian function.

ISP1

ISP2

cam_xclki

ISP4

ISP3

ISP4

cam_pclk

cam_vs

ISP5

ISP6

ISP8

ISP7

cam_hs

ISP9

D(n-1)

ISP10

D(1)

cam_d[7:0]

D(0)

D(n-3) D(n-2)

D(0)

D(n-1)

ISP12

ISP11

cam_wen

cam_fld

030-059

Figure 6-28. ISP – 8-bit Packed SYNC – Progressive Mode^{(1)(2)(3)(4)(5)}

(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable.

(2) The image sensor must be connected to the lower data lines and the unused lines must be grounded. However, it is possible to shift the

data to 0, 2, or 4 data internal lanes. The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit packed mode.

(3) Optionally, the data write to memory can be qualified by the external cam_wen signal. The cam_wen signal can be used as a external

memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted. The polarity of

cam_fld is programmable.

(4) The camera module can pack 8-bit data into 16 bits. It doubles the maximum pixel clock. This mode can be particularly useful to transfer

a YCbCr data stream or compressed stream to memory at very high speed.

(5) In cam_xclki; I is equal to a or b.

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6.5.1.3.1.3 12-Bit SYNC Normal – Interlaced Mode

Table 6-36 and Table 6-37 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-29).

Table 6-35. ISP Timing Conditions – 12-Bit SYNC Normal – Interlaced Mode

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

2.7

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

8.6

pF

Table 6-36. ISP Timing Requirements – 12-Bit SYNC Normal – Interlaced Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

ISP17

ISP18

t_c(pclk)

Cycle time⁽²⁾, cam_pclk period

Typical pulse duration, cam_pclk high

Typical pulse duration, cam_pclk low

Duty cycle error, cam_pclk

13.3

22.2

ns

ps

ns

t_W(pclkH)

t_W(pclkL)

t_dc(pclk)

t_j(pclk)

0.5*P⁽³⁾

667

133

1111

200

Cycle jitter⁽⁴⁾, cam_pclk

ISP19

ISP20

ISP21

t_su(dV-pclkH)

Setup time, cam_d[11:0] valid before cam_pclk

rising edge

1.82

3.25

t_h(pclkH-dV)

t_su(dV-vsH)

Hold time, cam_d[11:0] valid after cam_pclk rising

edge

3.25

ns

Setup time, cam_vs valid before cam_pclk rising

edge

ISP22

ISP23

t_h(pclkH-vsV)

t_su(dV-hsH)

Hold time, cam_vs valid after cam_pclk rising edge

1.82

3.25

ns

Setup time, cam_hs valid before cam_pclk rising

edge

ISP24

ISP25

t_h(pclkH-hsV)

t_su(dV-hsH)

Hold time, cam_hs valid after cam_pclk rising edge

1.82

3.25

ns

Setup time, cam_wen valid before cam_pclk rising

edge

ISP26

ISP27

ISP28

t_h(pclkH-hsV)

t_su(dV-fldH)

t_{h(pclkH-fldV)}

Hold time, cam_wen valid after cam_pclk rising

edge

1.82

3.25

ns

Setup time, cam_fld valid before cam_pclk rising

edge

Hold time, cam_fld valid after cam_pclk rising edge

(1) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.

(2) Related with the input maximum frequency supported by the ISP module.

(3) P = cam_lclk period in ns.

(4) Maximum cycle jitter supported by cam_pclk input clock.

Table 6-37. ISP Switching Characteristics – 12-Bit SYNC Normal – Interlaced Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

ISP15

ISP16

t_c(xclk)

Cycle time⁽¹⁾, cam_xclk period

Typical pulse duration, cam_xclk high

Typical pulse duration, cam_xclk low

Duty cycle error, cam_xclk

4.6

ns

ps

t_W(xclkH)

t_W(xclkL)

t_dc(xclk)

0.5*PO⁽²⁾

231

(1) Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module.

Warning: You must disable the camera sensor or the camera module to change the frequency configuration. For more information, see

the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98

(2) PO = cam_xclk period in ns.

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Table 6-37. ISP Switching Characteristics – 12-Bit SYNC Normal – Interlaced Mode (continued)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

33

MIN

MAX

33

t_j(xclk)

t_R(xclk)

t_F(xclk)

Jitter standard deviation⁽³⁾, cam_xclk

Rise time, cam_xclk

ps

ns

0.93

Fall time, cam_xclk

(3) The jitter probability density can be approximated by a Gaussian function.

ISP16

ISP15

ISP16

cam_xclki

cam_pclk

ISP18

ISP17

ISP20

ISP19

cam_vs

cam_hs

FRAME(0)

ISP21

ISP22

L(0)

L(n-1)

L(0)

ISP23

D(1)

ISP24

D(n-1)

cam_d[11:0]

cam_wen

D(0)

D(n-3) D(n-2)

D(n-1)

D(0)

D(2)

ISP25

ISP26

ISP28

ISP27

cam_fld

PAIR

IMPAIR

030-057

Figure 6-29. ISP – 12-Bit SYNC Normal – Interlaced Mode^{(1)(2)(3)(4)(5)(6)(7)(8)}

(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. If the cam_hs, cam_vs, and cam_fld signals are output, the

signal length can be set.

(2) The parallel camera in SYNC mode supports interlaced image sensor modules and 8-, 10-, 11-, or 12-bit data.

(3) When the image sensor has fewer than 12 data lines, it must be connected to the lower data lines and the unused lines must be

grounded.

(4) It is possible to shift the data to 0, 2, or 4 data internal lanes.

(5) The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode, cam_d[11:2] or cam_d[9:0] in 10-bit mode, cam_d[10:0] in 11-bit

mode, and cam_d[11:0] in 12-bit mode.

(6) Optionally, the data write to memory can be qualified by the external cam_wen signal.

(7) The cam_wen signal can be used as a external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and

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cam_wen signals are asserted.

(8) In cam_xclki; I is equal to a or b.

6.5.1.3.1.4 8-bit Packed SYNC – Interlaced Mode

Table 6-39 and Table 6-40 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-30).

Table 6-38. ISP Timing Conditions – 8-bit Packed SYNC – Interlaced Mode

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

2.5

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

8.6

pF

Table 6-39. ISP Timing Requirements – 8-bit Packed SYNC – Interlaced Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

ISP3

ISP4

t_c(pclk)

Cycle time⁽²⁾, cam_pclk period

Typical pulse duration, cam_pclk high

Typical pulse duration, cam_pclk low

Duty cycle error, cam_pclk

7.7

15.4

ns

ps

ns

t_W(pclkH)

t_W(pclkL)

t_dc(pclk)

t_j(pclk)

0.5*P⁽³⁾

385

83

769

167

Cycle jitter⁽⁴⁾, cam_pclk

ISP5

ISP6

ISP7

t_su(dV-pclkH)

Setup time, cam_d[11:0] valid before cam_pclk

rising edge

1.08

2.27

t_h(pclkH-dV)

t_su(dV-vsH)

Hold time, cam_d[11:0] valid after cam_pclk rising

edge

ns

Setup time, cam_vs valid before cam_pclk rising

edge

ISP8

ISP9

t_h(pclkH-vsV)

t_su(dV-hsH)

Hold time, cam_vs valid after cam_pclk rising edge

1.08

2.27

ns

Setup time, cam_hs valid before cam_pclk rising

edge

ISP10 t_h(pclkH-hsV)

ISP11 t_su(dV-hsH)

Hold time, cam_hs valid after cam_pclk rising edge

1.08

2.27

ns

Setup time, cam_wen valid before cam_pclk rising

edge

ISP12 t_h(pclkH-hsV)

ISP13 t_su(dV-fldH)

Hold time, cam_wen valid after cam_pclk rising edge

1.08

2.27

ns

Setup time, cam_fld valid before cam_pclk rising

edge

ISP14 t_{h(pclkH-fldV)}

Hold time, cam_fld valid after cam_pclk rising edge

1.08

2.27

ns

(1) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.

(2) Related with the input maximum frequency supported by the ISP module.

(3) P = cam_lclk period in ns.

(4) Maximum cycle jitter supported by cam_pclk input clock.

Table 6-40. ISP Switching Characteristics – 8-bit Packed SYNC – Interlaced Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

ISP16

ISP2

t_c(xclk)

Cycle time⁽¹⁾, cam_xclk period

4.6

ns

t_W(xclkH)

Typical pulse duration, cam_xclk high

0.5*PO⁽²⁾

(1) Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module.

Warning: You must disable the camera sensor or the camera module to change the frequency configuration. For more information, see

the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98

(2) PO = cam_xclk period in ns.

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Table 6-40. ISP Switching Characteristics – 8-bit Packed SYNC – Interlaced Mode (continued)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

0.5*PO⁽²⁾

231

MAX

MIN

0.5*PO⁽²⁾

231

MAX

ISP2

t_W(xclkL)

t_dc(xclk)

t_j(xclk)

Typical pulse duration, cam_xclk low

Duty cycle error, cam_xclk

Jitter standard deviation⁽³⁾, cam_xclk

Rise time, cam_xclk

ns

ps

ns

67

t_R(xclk)

t_F(xclk)

0.93

Fall time, cam_xclk

(3) The jitter probability density can be approximated by a Gaussian function.

ISP2

ISP1

ISP2

cam_xclki

cam_pclk

ISP4

ISP3

ISP4

ISP6

ISP5

cam_vs

cam_hs

FRAME(0)

ISP7

ISP8

L(0)

L(n-1)

L(0)

ISP9

D(1)

ISP10

D(n-1)

cam_d[7:0]

cam_wen

D(0)

D(n-3)

D(n-2)

D(n-1)

D(0)

D(2)

ISP11

ISP12

ISP14

ISP13

cam_fld

PAIR

IMPAIR

030-060

Figure 6-30. ISP – 8-bit Packed SYNC – Interlaced Mode^{(1)(2)(3)(4)(5)}

(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable.

(2) The image sensor must be connected to the lower data lines and the unused lines must be grounded. However, it is possible to shift the

data to 0, 2, or 4 data internal lanes. The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit packed mode.

(3) Optionally, the data write to memory can be qualified by the external cam_wen signal. The cam_wen signal can be used as a external

memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted.

(4) The camera module can pack 8-bit data into 16 bits. It doubles the maximum pixel clock. This mode can be particularly useful to transfer

a YCbCr data stream or compressed stream to memory at very high speed.

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(5) In cam_xclki; I is equal to a or b.

6.5.1.3.2 ITU Mode

Table 6-42 and Table 6-43 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-31).

Table 6-41. ISP Timing Conditions – ITU Mode

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

2.7

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

8.6

pF

Table 6-42. ISP Timing Requirements – ITU Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

ISP17

ISP18

t_c(pclk)

Cycle time⁽²⁾, cam_pclk period

Typical pulse duration, cam_pclk high

Typical pulse duration, cam_pclk low

Duty cycle error, cam_pclk

13.3

22.2

ns

ps

ns

t_W(pclkH)

t_W(pclkL)

t_dc(pclk)

t_j(pclk)

0.5*P⁽³⁾

667

133

1111

200

Cycle jitter⁽⁴⁾, cam_pclk

ISP23

ISP24

t_su(dV-pclkH)

Setup time, cam_d[9:0] valid before cam_pclk

rising edge

1.82

3.25

t_h(pclkH-dV)

Hold time, cam_d[9:0] valid after cam_pclk rising

edge

ns

(1) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.

(2) Related with the input maximum frequency supported by the ISP module.

(3) P = cam_lclk period in ns.

(4) Maximum cycle jitter supported by cam_lclk input clock.

Table 6-43. ISP Switching Characteristics – ITU Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

ISP15

ISP16

t_c(xclk)

Cycle time⁽¹⁾, cam_xclk period

Typical pulse duration, cam_xclk high

Typical pulse duration, cam_xclk low

Duty cycle error, cam_xclk

4.6

ns

ps

ns

t_W(xclkH)

t_W(xclkL)

t_dc(xclk)

t_j(xclk)

0.5*PO⁽²⁾

231

Jitter standard deviation⁽³⁾, cam_xclk

33

t_R(xclk)

t_F(xclk)

Rise time, cam_xclk

0.93

Fall time, cam_xclk

(1) Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module.

Warning: The camera sensor or the camera module must be disabled to change the frequency configuration. For more information, see

the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98

(2) PO = cam_xclk period in ns

(3) The jitter probability density can be approximated by a Gaussian function.

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ISP16

ISP15

ISP16

cam_xclki

cam_pclk

ISP17

ISP18

ISP23

D (0)

ISP24

D(0)

D(n-1)

cam_d[9:0]

SOF

EOF

SOF

EOF

030-058

Figure 6-31. ISP – ITU Mode⁽¹⁾⁽²⁾

(1) The unused lines must be grounded and the data bus must be connected to the lower data lines. It is possible to shift the data to 0, 2, or

4 data internal lanes. The different configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode and cam_d[11:2] or cam_d[9:0] in 10-bit

mode.

(2) The parallel camera in ITU mode supports progressive camera modules.

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6.5.2 Display Subsystem (DSS)

The display subsystem (DSS) provides the logic to display the video frame from external (SDRAM) or

internal (SRAM) memory on an LCD panel or a TV set. The DSS integrates a display controller, a remote

frame buffer module (RFBI), and a TV-out module. It can be used in two configurations:

•

LCD display in:

–

Bypass mode (RFBI module bypassed)

RFBI mode (through RFBI module)

•

TV display (not discussed in this document because of its analog IO signals)

The two displays can be active at the same time.

NOTE

For more information, see Display Subsystem / Display Subsystem Functional Description

section of the OMAP35x Technical Reference Manual (TRM) [literature number

SPRUF98.

6.5.2.1 LCD Display in Bypass Mode

Two types of LCD panel are supported:

•

Thin film transistor (TFT) or active matrix technology

Supertwisted nematic (STN) or passive matrix technology

Both configurations are discussed in the following paragraphs.

6.5.2.1.1 LCD Display in TFT Mode

6.5.2.1.1.1 LCD Display in TFT Mode – HDTV Application

Table 6-44 assumes testing over the recommended operating conditions (see Figure 6-32).

Table 6-44. LCD Display Switching Characteristics in TFT Mode – HDTV Application^(3)(4)(5)

NO.

PARAMETER

OPP3

OPP2

UNIT

MIN

MAX

MIN

MAX

DL0

DL1

DL2

DL3

t_{d(PCLKA-HSYNCT)}Delay time, dss_pclk active edge to dss_hsync

transition

–4.2

4.2

–4.7

4.7

ns

t_{d(PCLKA-VSYNCT)}Delay time, dss_pclk active edge to dss_vsync

transition

–4.2

4.2

–4.7

4.7

t_{d(PCLKA-ACBIASA)}Delay time, dss_pclk active edge to

dss_acbias active level

t_{d(PCLKA-DATAV)}

Delay time, dss_pclk active edge to dss_data

bus valid

–4.2

–4.7

DL4

DL5

t_c(PCLK)

t_w(PCLK)

Cycle time⁽²⁾, dss_pclk

13.468

0.45*P⁽¹⁾

15.152

0.45*P⁽¹⁾

ns

Pulse duration, dss_pclk low or high

0.55*P⁽¹⁾

(1) P = dss_pclk period.

(2) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the

DISPC_DIVISOR register.

(3) The capacitive load is equivalent to 25 pF at 1.15 V and 30 pF at 1.0 V.

(4) For more information, see the DSS chapter in the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98.

(5) See DM Operating Condition Addendum for OPP voltages.

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DL5

DL4

dss_pclk

DL1

dss_vsync

DL0

dss_hsync

DL2

dss_acbias

DL3

dss_data[23:0]

030-061

Figure 6-32. LCD Display in TFT Mode – HDTV Application^(1)(2)(3)(4)

(1) The pixel data bus depends on the use of 8-, 9-, 12-, 16-, 18-, or 24-bit per pixel data output pins.

(2) The pixel clock frequency is programmable.

(3) All timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk.

(4) For more information, see the DSS chapter in the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98.

6.5.2.1.2 LCD Display in STN Mode

Table 6-45 assumes testing over the recommended operating conditions (see Figure 6-33).

Table 6-45. LCD Display Switching Characteristics in STN Mode^(3)(4)(5)(6)

NO.

PARAMETER

OPP3

OPP2

UNIT

MIN

MAX

MIN

MAX

DL3

t_{d(PCLKA-DATAV)}

Delay time, dss_pclk active edge to dss_data

bus valid

–6.9

6.9

–6.9

6.9

ns

DL4

DL5

t_c(PCLK)

t_w(PCLK)

Cycle time⁽²⁾, dss_pclk

22.727

ns

Pulse duration, dss_pclk low or high

0.45*P⁽¹⁾0.55*P⁽¹⁾0.45*P⁽¹⁾0.55*P⁽¹⁾

(1) P = dss_pclk period.

(2) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the

DISPC_DIVISOR register.

(3) The DSS in STN mode is used with 4 or 8 pins only; unused pixel data bits always remain low.

(4) The capacitive load is equivalent to 40 pF.

(5) For more information, see the DSS chapter in the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98.

(6) See DM Operating Condition Addendum for OPP voltages.

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DL5

DL4

dss_pclk

dss_vsync

dss_hsync

dss_acbias

DL3

dss_data[23:0]

030-062

Figure 6-33. LCD Display in STN Mode^{(1)(2)(3)(4)(5)}

(1) The pixel data bus depends on the use 4-, 8-, 12-, 16-, 18-, or 24-bit per pixel data output pins.

(2) All timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk.

(3) dss_vsync width must be programmed to be as small as possible.

(4) The pixel clock frequency is programmable.

(5) For more information, see the DSS chapter in the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98.

6.5.2.2 LCD Display in RFBI Mode

Table 6-47 and Table 6-48 assume testing over the recommended operating conditions (see Figure 6-34

through Figure 6-36).

Table 6-46. LCD Timing Conditions – RFBI Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

MIN

MAX

Input Conditions

t_R

t_F

Input signal rise time

Input signal fall time

15

ns

Output Conditions

C_LOAD

Output load capacitance

30

pF

Table 6-47. LCD Display Timing Requirements in RFBI Mode⁽²⁾

NO.

PARAMETER

OPP3

MAX

OPP2

MAX

OPP1

MIN MAX

UNIT

MIN

DR0

DR1

t_su(DAV-RDH)

t_h(RDH-DAIV)

Setup time, rfbi_da[15:0] valid to rfbi_rd

high

7.0

9.0

ns

Hold time, rfbi_rd high to rfbi_da[15:0]

invalid

5.0

t_{d(Data sampled)}rfbi_da[15:0] are sampled at the end off

the access time

N⁽¹⁾

(1) N = (AccessTime) * (TimeParaGranularity + 1) * L4CLK

(2) See DM Operating Condition Addendum for OPP voltages.

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Table 6-48. LCD Display Switching Characteristics in RFBI Mode⁽¹⁵⁾

PARAMETER

OPP3

OPP2

OPP1

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

t_{w(rfbi_wrH)}

Pulse duration, rfbi_wr high

Pulse duration, rfbi_wr low

A⁽¹⁾

B⁽²⁾

C⁽³⁾

A⁽¹⁾

B⁽²⁾

C⁽³⁾

ns

t_{w(rfbi_wrL)}

t_{d(rfbi_a0-rfbi_wrL)}

Delay time, rfbi_a0 transition to rfbi_wr

low

t_{d(rfbi_wrH-rfbi_a0)}

Delay time, rfbi_wr high to rfbi_a0

transition

D⁽⁴⁾

ns

t_{d(rfbi_csx-rfbi_wrL)}

t_{d(rfbi_wrH-rfbi_csxH)}

Delay time, rfbi_csx⁽¹⁴⁾low to rfbi_wr low

Delay time, rfbi_wr high to rfbi_csx⁽¹⁴⁾

high

E⁽⁵⁾

F⁽⁶⁾

E⁽⁵⁾

F⁽⁶⁾

ns

t_d(dataV)

rfbi_da[15:0] valid

G⁽⁷⁾

H⁽⁸⁾

I⁽⁹⁾

G⁽⁷⁾

H⁽⁸⁾

I⁽⁹⁾

ns

t_{d(rfbi_a0H-rfbi_rdL)}

t_{d(rfbi_rdlH-rfbi_a0)}

Delay time, rfbi_a0 high to rfbi_rd low

Delay time, rfbi_rd high to rfbi_a0

transition

t_{w(rfbi_rdH)}

Pulse duration, rfbi_rd high

J⁽¹⁰⁾

K⁽¹¹⁾

L⁽¹²⁾

M⁽¹³⁾

J⁽¹⁰⁾

K⁽¹¹⁾

L⁽¹²⁾

M⁽¹³⁾

ns

t_{w(rfbi_rdL)}

Pulse duration, rfbi_rd low

Delay time, rfbi_rd low to rfbi_csx⁽¹⁴⁾low

Delay time, rfbi_rd high to rfbi_csx⁽¹⁴⁾

high

t_{d(rfbi_rdL-rfbi_csxL)}

t_{d(rfbi_rdH-rfbi_csxH)}

t_{R(rfbi_wr)}

Rise time, rfbi_wr

Fall time, rfbi_wr

10

ns

t_{F(rfbi_wr)}

t_{R(rfbi_a0)}

t_{F(rfbi_a0)}

Rise time, rfbi_a0

Fall time, rfbi_a0

t_{R(rfbi_csx)}

t_{F(rfbi_csx)}

t_{R(rfbi_da[15:0])}

t_{F(rfbi_da[15:0])}

t_{R(rfbi_rd)}

Rise time, rfbi_csx⁽¹⁴⁾

Fall time, rfbi_csx⁽¹⁴⁾

Rise time, rfbi_da[15:0]

Fall time, rfbi_da[15:0]

Rise time, rfbi_rd

t_{F(rfbi_rd)}

Fall time, rfbi_rd

(1) A = (WECycleTime – WEOffTime) * (TimeParaGranularity + 1) * L4CLK

(2) B = (WEOffTime – WEOntime) * (TimeParaGranularity + 1) * L4CLK

(3) C = WEOnTime * (TimeParaGranularity + 1) * L4CLK

(4) D = (WECycleTime + CSPulseWidth – WEOffTime) * (TimeParaGranularity + 1) * L4CLK

if mode Write to Read or Read to Write is enabled

(5) E = (WEOnTime – CSOnTime) * (TimeParaGranularity + 1) * L4CLK

(6) F = (CSOffTime – WEOffTime) * (TimeParaGranularity + 1) * L4CLK

(7) G = (WECycleTime) * (TimeParaGranularity + 1) * L4CLK

(8) H = (REOnTime) * (TimeParaGranularity + 1) * L4CLK

(9) I = (RECycleTime + CSPulseWidth – REOffTime) * (TimeParaGranularity + 1) * L4CLK

if mode Write to Read or Read to Write is enabled

(10) J = (RECycleTime – REOffTime) * (TimeParaGranularity + 1) * L4CLK

(11) K = (REOffTime – REOntime) * (TimeParaGranularity + 1) * L4CLK

(12) L = (REOnTime – CSOnTime) * (TimeParaGranularity + 1) * L4CLK

(13) M = (CSOffTime – REOffTime) * (TimeParaGranularity + 1) * L4CLK

(14) In rfbi_csx, x stands for 0 or 1.

(15) See DM Operating Condition Addendum for OPP voltages.

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CsPulseWidth

WeCycleTime

CsOffTime

rfbi_a0

CsOffTime

CsOnTime

rfbi_csx

WeOffTime

WeOnTime

WeOffTime

WeOnTime

rfbi_wr

rfbi_da[15:0]

rfbi_rd

DATA0

DATA1

034-002

Figure 6-34. LCD Display in RFBI Mode – Command / Data Write Mode⁽¹⁾⁽²⁾

(1) In rfbi_csx, x is equal to 0 or 1.

(2) For more information, see the DSS chapter in the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98 .

AccessTime

ReCycleTime

CsPulseWidth

AccessTime

ReCycleTime

rfbi_a0

CsOffTime

CsOnTime

CsOffTime

CsOnTime

rfbi_csx

rfbi_rd

ReOffTime

ReOnTime

ReOffTime

ReOnTime

DR1

DR0

DATA0

rfbi_da[15:0]

rfbi_wr

DATA1

034-003

Figure 6-35. LCD Display in RFBI Mode – Data Read Mode⁽¹⁾⁽²⁾

(1) In rfbi_csx, x is equal to 0 or 1.

(2) For more information, see the DSS chapter in the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98.

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WeCycleTime

ReCycleTime

AccessTime

WeCycleTime

rfbi_a0

CsOffTime

CsOnTime

CsOffTime

CsOnTime

CsOffTime

CsOnTime

rfbi_csx

rfbi_wr

WeOffTime

WeOnTime

WeOffTime

WeOnTime

ReOffTime

ReOnTime

rfbi_rd

CsPulseWidth

WRITE

READ

rfbi_da[15:0]

WRITE

034-004

Figure 6-36. LCD Display in RFBI Mode – Command / Data Write-to-Read and Read-to-Write Timing

Modes⁽¹⁾⁽²⁾

(1) In rfbi_csx, x is equal to 0 or 1.

(2) For more information, see the DSS chapter in the OMAP35x Technical Reference Manual (TRM) [literature number =SPRUF98.

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6.6 Serial Communications Interfaces

6.6.1 Multichannel Buffered Serial Port (McBSP) Timing

There are five McBSP modules called McBSP1 through McBSP5. McBSP provides a full-duplex, direct

serial interface between the OMAP3525 and OMAP3530 devices and other devices in a system such as

other application devices or codecs. It can accommodate a wide range of peripherals and clocked

frame-oriented protocols (I2S, PCM, and TDM) due to its high level of versatility.

The McBSP1-5 modules may support two types of data transfer at the system level:

•

The full-cycle mode, for which one clock period is used to transfer the data, generated on one edge

and captured on the same edge (one clock period later).

•

The half-cycle mode, for which one half clock period is used to transfer the data, generated on one

edge and captured on the opposite edge (one half clock period later). Note that a new data is

generated only every clock period, which secures the required hold time.

The interface clock (CLKX/CLKR) activation edge (data/frame sync capture and generation) has to be

configured accordingly with the external peripheral (activation edge capability) and the type of data

transfer required at the system level.

The OMAP3525 and OMAP3530 McBSP1-5 timing characteristics are described for both rising and falling

activation edges. McBSP1 supports:

•

6-pin mode: dx and dr as data pins; clkx, clkr, fsx, and fsr as control pins.

4-pin mode: dx and dr as data pins; clkx and fsx pins as control pins. The clkx and fsx pins are

internally looped back via software configuration, respectively, to the clkr and fsr internal signals for

data receive.

McBSP2, 3, 4, and 5 support only the 4-pin mode.

The following sections describe the timing characteristics for applications in normal mode (that is,

OMAP3525 and OMAP3530 McBSPx connected to one peripheral) and TDM applications in multipoint

mode.

6.6.1.1 McBSP in Normal Mode

Table 6-49. McBSP Timing Conditions—Normal Mode

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

2

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

10

pF

Table 6-50. McBSP Output Clock Pulse Duration⁽³⁾

NO.

PARAMETER

OPP3

OPP2

UNIT

MIN

MAX

MIN

MAX

Inputs and Outputs

McBSP1 t_c(CLK)

Cycle time, mcbsp1_clkx / mcbsp1_clkr (multiplexing mode

0)

20.83

41.67

ns

McBSP2 t_c(CLK)

McBSP3 t_c(CLK)

Cycle time, mcbsp2_clkx (multiplexing mode 0)

20.83

31.25

20.83

31.25

41.67

62.50

41.67

62.50

ns

Cycle time,

IO set 1 (multiplexing mode 0)

IO set 2 (multiplexing mode 1)

IO set 3 (multiplexing mode 2)

IO set 1 (multiplexing mode 0)

IO set 2 (multiplexing mode 2)

mcbsp3_clkx

McBSP4 t_c(CLK)

Cycle time,

ns

mcbsp4_clkx

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Table 6-50. McBSP Output Clock Pulse Duration⁽³⁾(continued)

NO.

PARAMETER

OPP3

OPP2

UNIT

MIN

MAX

MIN

MAX

McBSP5 t_c(CLK)

Outputs

Cycle time, mcbsp5_clkx (multiplexing mode 1)

31.25

62.50

ns

t_w(CLKH)

Typical pulse duration, mcbsp1_clkr / mcbspx_clkx high⁽²⁾

Typical pulse duration, mcbsp1_clkr / mcbspx_clkx low⁽²⁾

Duty cycle error, mcbsp1_clkr / mcbspx_clkx⁽²⁾

0.5*P⁽¹⁾

ns

t_w(CLKL)

t_dc(CLK)

–0.75

0.75

–0.75

0.75

(1) P = mcbsp1_clkr / mcbspx_clkx clock period.

(2) In mcbspx, x identifies the McBSP number: 1, 2, 3, 4, or 5.

(3) See DM Operating Condition Addendum for OPP voltages.

6.6.1.1.1 Receive Timing with Rising Edge as Activation Edge

Table 6-51 through Table 6-56 assume testing over the recommended operating conditions (see

Figure 6-37 through Figure 6-38).

Table 6-51. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Rising Edge and Receive Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MIN MAX

1.0 V

MIN MAX

UNIT

B3

t_{su(DRV-CLKAE)}

Setup time, mcbspx_dr valid before mcbsp1_clkr /

mcbspx_clkx active edge

Master

Slave

3.5

3.7

1

7.7

7.9

1

ns

B4

t_h(CLKAE-DRV)

Hold time, mcbspx_dr valid after mcbsp1_clkr /

mcbspx_clkx active edge

Master

Slave

0.4

3.7

0.4

7.9

B5

B6

t_{su(FSV-CLKAE)}

t_h(CLKAE-FSV)

Setup time, mcbsp1_fsr / mcbspx_fsx valid before mcbsp1_clkr /

mcbspx_clkx active edge

Hold time, mcbsp1_fsr / mcbspx_fsx valid after mcbsp1_clkr /

mcbspx_clkx active edge

0.5

ns

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

Table 6-52. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics – Rising Edge and Receive

Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

0.7

MAX

MIN

0.7

MAX

B2

t_d(CLKAE-FSV)

Delay time, mcbsp1_clkr / mcbspx_clkx active edge to mcbsp1_fsr /

mcbspx_fsx valid

14.8

29.6

ns

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

Table 6-53. McBSP4 (Set #1) Timing Requirements – Rising Edge and Receive Mode⁽¹⁾

NO.

B3

PARAMETER

1.15 V

MIN MAX

1.0 V

MIN MAX

UNIT

t_{su(DRV-CLKXAE)}

Setup time, mcbspx_dr valid before

mcbspx_clkx active edge

Master

Slave

2.7

3.7

1

7.7

7.9

1

ns

B4

t_{h(CLKXAE-DRV)}

Hold time, mcbspx_dr valid after mcbspx_clkx

active edge

Master

Slave

0.4

3.7

0.5

0.4

7.9

0.5

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time mcbspx_fsx valid before mcbspx_clkx active edge

Hold Time mcbspx_fsx valid after mcbspx_clkx active edge

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-55 and Table 6-56

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Table 6-54. McBSP4 (Set #1) Switching Characteristics – Rising Edge and Receive Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

0.7

MAX

MIN MAX

B2

t_{d(CLKXAE-FSXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx valid

16.6

0.7

33.1

ns

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-55 and Table 6-56

Table 6-55. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Rising Edge and Receive Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MIN MAX

1.0 V

MIN MAX

UNIT

B3

t_{su(DRV-CLKXAE)}

Setup time, mcbspx_dr valid before

mcbspx_clkx active edge

Master

Slave

5.6

5.8

1

12

12.2

1

ns

B4

t_{h(CLKXAE-DRV)}

Hold time, mcbspx_dr valid after mcbspx_clkx Master

active edge

Slave

0.4

5.8

0.5

0.4

12.2

0.5

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time, mcbspx_fsx valid before mcbspx_clkx active edge

Hold time, mcbspx_fsx valid after mcbspx_clkx active edge

(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode

by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are

specified in Table 6-53 and Table 6-54.

For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).

Table 6-56. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Rising Edge and Receive

Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

MAX

44.4

UNIT

MIN

0.7

MAX

MIN

B2

t_{d(CLKXAE-FSXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx valid

22.2

0.7

ns

mcbspx_clkr

B2

mcbspx_fsr

mcbspx_dr

B3

B4

D7

D6

D5

030-068

Figure 6-37. McBSP Rising Edge Receive Timing in Master Mode

mcbspx_clkr

mcbspx_fsr

mcbspx_dr

B5

B6

B3

B4

D7

D6

D5

030-069

Figure 6-38. McBSP Rising Edge Receive Timing in Slave Mode

(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode

by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are

specified in Table 6-53 and Table 6-54.

For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).

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6.6.1.1.2 Transmit Timing with Rising Edge as Activation Edge

Table 6-57 through Table 6-62 assume testing over the recommended operating conditions (see

Figure 6-39 and Figure 6-40).

Table 6-57. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Rising Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time, mcbspx_fsx valid before mcbspx_clkx

active edge

3.7

7.9

ns

Hold time, mcbspx_fsx valid after mcbspx_clkx active

edge

0.5

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

Table 6-58. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics – Rising Edge and Transmit

Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

B2

B8

t_{d(CLKXAE-FSXV)}

t_{d(CLKXAE-DXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx

valid

0.7

14.8

0.7

29.6

ns

Delay time, mcbspx_clkx active edge to Master

0.6

14.8

0.6

29.6

ns

mcbspx_dx valid

Slave

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

Table 6-59. McBSP4 (Set #1) Timing Requirements – Rising Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time, mcbspx_fsx valid before mcbspx_clkx

active edge

3.7

7.9

ns

Hold time, mcbspx_fsx valid after mcbspx_clkx active

edge

0.5

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-61.

Table 6-60. McBSP4 (Set #1) Switching Characteristics – Rising Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

B2

B8

t_{d(CLKXAE-FSXV)}

t_{d(CLKXAE-DXV)}

Delay time, mcbspx_clkx active edge to

mcbspx_fsx valid

0.7

16.6

0.7

33.1

ns

Delay time, mcbspx_clkx active edge

to mcbspx_dx valid

Master

Slave

0.6

16.6

17.3

0.6

33.1

ns

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-61.

Table 6-61. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Rising Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

B5

t_{su(FSXV-CLKXAE)}

Setup time, mcbspx_fsx valid before mcbspx_clkx

active edge

5.8

12.2

ns

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-61.

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Table 6-61. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Rising Edge and Transmit Mode

(continued)

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

B6

t_{h(CLKXAE-FSXV)}

Hold time, mcbspx_fsx valid after mcbspx_clkx active

edge

0.5

ns

Table 6-62. McBSP 3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Rising Edge and Transmit

Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

B2

B8

t_{d(CLKXAE-FSXV)}

t_{d(CLKXAE-DXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx

valid

0.7

22.2

0.7

44.4

ns

Delay time, mcbspx_clkx active edge to Master

0.6

22.2

0.6

44.4

ns

mcbspx_dx valid

Slave

mcbspx_clkx

B2

B8

mcbspx_fsx

mcbspx_dx

D7

D6

D5

030-070

Figure 6-39. McBSP Rising Edge Transmit Timing in Master Mode

mcbspx_clkx

mcbspx_fsx

mcbspx_dx

B5

B6

B8

D7

D6

D5

030-071

Figure 6-40. McBSP Rising Edge Transmit Timing in Slave Mode

(1) In mcbspx, x identifies the McBSP number: 3, 4 or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode

by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are

specified in the table above. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).

6.6.1.1.3 Receive Timing with Falling Edge as Activation Edge

Table 6-63 through Table 6-68 assume testing over the recommended operating conditions (see

Figure 6-41 and Figure 6-42).

Table 6-63. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Falling Edge and Receive Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

3.5

3.7

1

MIN

7.7

7.9

1

MAX

B3

t_{su(DRV-CLKAE)}

t_h(CLKAE-DRV)

t_{su(FSV-CLKAE)}

Setup time, mcbspx_dr valid before

mcbsp1_clkr / mcbspx_clkx active edge

Master

Slave

ns

B4

Hold time, mcbspx_dr valid after

mcbsp1_clkr / mcbspx_clkx active edge

Master

Slave

0.4

3.7

0.4

7.9

B5

Setup time, mcbsp1_fsr / mcbspx_fsx valid before

mcbsp1_clkr /mcbspx_clkx active edge

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

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Table 6-63. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Falling Edge and Receive Mode

(continued)

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

B6

t_h(CLKAE-FSV)

Hold time, mcbsp1_fsr / mcbspx_fsx valid after

mcbsp1_clkr /mcbspx_clkx active edge

0.5

ns

Table 6-64. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics – Falling Edge and Receive

Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

B2

t_d(CLKAE-FSV)

Delay time, mcbsp1_clkr / mcbspx_clkx active edge to

mcbsp1_fsr / mcbspx_fsx valid

0.7

14.8

0.7

29.6

ns

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

Table 6-65. McBSP4 (Set #1) Timing Requirements – Falling Edge and Receive Mode⁽¹⁾

NO.

B3

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

2.7

3.7

1

MIN

7.7

7.9

1

MAX

t_{su(DRV-CLKXAE)}

Setup time, mcbspx_dr valid before

mcbspx_clkx active edge

Master

Slave

ns

B4

t_{h(CLKXAE-DRV)}

Hold time, mcbspx_dr valid after

mcbspx_clkx active edge

Master

Slave

0.4

3.7

0.4

7.9

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time mcbspx_fsx valid before mcbspx_clkx active

edge

Hold time mcbspx_fsx valid after mcbspx_clkx active

edge

0.5

ns

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-67

Table 6-66. McBSP4 (Set #1) Switching Characteristics – Falling Edge and Receive Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MAX

16.6

1.0 V

UNIT

MIN

MAX

B2

t_{d(CLKXAE-FSXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx valid

0.7

33.1

ns

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-67

Table 6-67. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Falling Edge and Receive Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

5.6

5.8

1

MIN

12

MAX

B3

t_{su(DRV-CLKXAE)}

Setup time, mcbspx_dr valid before

mcbspx_clkx active edge

Master

Slave

ns

12.2

1

B4

t_{h(CLKXAE-DRV)}

Hold time, mcbspx_dr valid after mcbspx_clkx Master

active edge

Slave

0.4

5.8

0.4

12.2

B5

B6

t_{su(FSXV-CLKXAE)}Setup time, mcbspx_fsx valid before mcbspx_clkx active

edge

t_{h(CLKXAE-FSXV)}

Hold time, mcbspx_fsx valid after mcbspx_clkx active

edge

0.5

ns

(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode

by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are

specified in the table above. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).

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Table 6-68. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Falling Edge and Receive

Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

B2

t_{d(CLKXAE-FSXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx

valid

0.7

22.2

0.7

44.4

ns

(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode

by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are

specified in the table above. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).

mcbspx_clkr

B2

mcbspx_fsr

mcbspx_dr

B3

B4

D7

D6

D5

030-072

Figure 6-41. McBSP Falling Edge Receive Timing in Master Mode

mcbspx_clkr

mcbspx_fsr

mcbspx_dr

B5

B6

B3

B4

D7

D6

D5

030-073

Figure 6-42. McBSP Falling Edge Receive Timing in Slave Mode

6.6.1.1.4 Transmit Timing with Falling Edge as Activation Edge

Table 6-69 through Table 6-74 assume testing over the recommended operating conditions (see

Figure 6-43 and Figure 6-44).

Table 6-69. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Falling Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time, mcbspx_fsx valid before mcbspx_clkx

active edge

3.7

7.9

ns

Hold time, mcbspx_fsx valid after mcbspx_clkx

active edge

0.5

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

Table 6-70. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics – Falling Edge and Transmit

Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

B2

B8

t_{d(CLKXAE-FSXV)}

t_{d(CLKXAE-DXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx

valid

0.7

14.8

0.7

29.6

ns

Delay time, mcbspx_clkx active edge to Master

0.6

14.8

0.6

29.6

ns

mcbspx_dx valid

Slave

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

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Table 6-71. McBSP4 (Set #1) Timing Requirements – Falling Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time, mcbspx_fsx valid before

mcbspx_clkx active edge

3.7

7.9

ns

Hold time, mcbspx_fsx valid after mcbspx_clkx

active edge

0.5

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-73.

Table 6-72. McBSP4 (Set #1) Switching Characteristics – Falling Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

B2

B8

t_{d(CLKXAE-FSXV)}

t_{d(CLKXAE-DXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx

valid

0.7

16.6

0.7

33.1

ns

Delay time, mcbspx_clkx active edge to

mcbspx_dx valid

Master

Slave

0.6

16.6

17.3

0.6

33.1

ns

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-73.

Table 6-73. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Falling Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time, mcbspx_fsx valid before mcbspx_clkx

active edge

5.8

12.2

ns

Hold time, mcbspx_fsx valid after mcbspx_clkx

active edge

0.5

(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode

by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are

specified in Table 6-73. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).

Table 6-74. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Falling Edge and Transmit

Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MIN

1.0 V

MAX

UNIT

MAX

22.2

MIN

0.7

0.6

B2

B8

t_{d(CLKXAE-FSXV)}

t_{d(CLKXAE-DXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx valid

0.7

0.6

44.4

ns

Delay time, mcbspx_clkx active edge to

mcbspx_dx valid

Master

Slave

(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode

by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are

specified in Table 6-73. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).

mcbspx_clkx

B2

mcbspx_fsx

mcbspx_dx

B8

D7

D6

D5

030-074

Figure 6-43. McBSP Falling Edge Transmit Timing in Master Mode

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mcbspx_clkx

B5

B6

mcbspx_fsx

mcbspx_dx

B8

D7

D6

D5

030-075

Figure 6-44. McBSP Falling Edge Transmit Timing in Slave Mode

6.6.1.2 McBSP in TDM—Multipoint Mode (McBSP3)

For TDM application in multipoint mode, OMAP3525 and OMAP3530 are considered as a slave.

Table 6-76 and Table 6-77 assume testing over the operating conditions and electrical characteristic

conditions described below.

Table 6-75. McBSP3 Timing Conditions—TDM in Multipoint Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

MIN

MAX

Input Conditions

t_R

t_F

Input signal rising time

Input signal falling time

1.0

8.5

ns

Output Conditions

C_LOADOutput Load Capacitance

40

pF

Table 6-76. McBSP3 Timing Requirements—TDM in Multipoint Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

t_W(CLKH)

Cycle Time, mcbsp3_clkx

162.8

ns

t_W(CLKH)

Typical Pulse duration, mcbsp3_clkx high

Typical Pulse duration, mcbsp3_clkx low

Duty cycle error, mcbsp3_clkx

0.5*P⁽²⁾

t_W(CLKL)

t_dc(CLK)

–8.14

8.14

–8.14

8.14

B3⁽³⁾

B4⁽³⁾

B5⁽³⁾

B6⁽³⁾

t_{su(DRV-CLKAE)}

Setup time, mcbsp3_dr valid before

mcbsp3_clkx active edge

9

t_h(CLKAE-DRV)

t_{su(FSV-CLKAE)}

t_h(CLKAE-FSV)

Hold time, mcbsp3_dr valid after mcbsp3_clkx

active edge

2.4

9

2.4

9

ns

Setup time, mcbsp3_fsx valid before

mcbsp3_clkx active edge

Hold time, mcbsp3_fsx valid after

mcbsp3_clkx active edge

2.4

(1) For McBSP3, these timings concern only Set #3 (multiplexing mode in McBSP1 pins).

(2) P = mcbsp3_clkx period in ns

(3) See Section 6.6.1.1, McBSP in Normal Mode for corresponding figures.

Table 6-77. McBSP3 Switching Characteristics—TDM in Multipoint Mode⁽¹⁾

NO.

B8⁽²⁾

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

t_{d(CLKXAE-DXV)}Delay time, mcbsp3_clkx active edge to

mcbsp3_dx valid

0.6

16.8

0.6

29.6

ns

(1) For McBSP3, these timings concern only Set #3 (multiplexing mode in McBSP1 pins).

(2) See Section 6.6.1.1, McBSP in Normal Mode for corresponding figures.

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6.6.2 Multichannel Serial Port Interface (McSPI) Timing

The multichannel SPI is a master/slave synchronous serial bus. The McSPI1 module supports up to four

peripherals and the others (McSPI2, McSPI3, and McSPI4) support up to two peripherals. The following

timings are applicable to the different configurations of McSPI in master/slave mode for any McSPI and

any channel (n).

6.6.2.1 McSPI in Slave Mode

Table 6-78 and Table 6-79 assume testing over the recommended operating conditions (see Figure 6-45).

Table 6-78. McSPI Interface Timing Requirements – Slave Mode⁽¹⁾⁽²⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

1/SS 1/t_c(CLK)

0

Frequency, mcspix_clk

24

12

MHz

t_j(CLK)

Cycle jitter⁽³⁾, mcspix_clk

-200

200

-200

200

0.55*P⁽⁴⁾

ps

ns

SS1 t_w(CLK)

Pulse duration, mcspix_clk high or low

0.45*P⁽⁴⁾0.55*P⁽⁴⁾0.45*P⁽⁴⁾

SS2 t_{su(SIMOV-CLKAE)}

Setup time, mcspix_simo valid before mcspix_clk

active edge

4.2

9.5

SS3 t_{h(SIMOV-CLKAE)}

SS4 t_{su(CS0V-CLKFE)}

SS5 t_{h(CS0I-CLKLE)}

Hold time, mcspix_simo valid after mcspix_clk active

edge

4.6

9.9

ns

Setup time, mcspix_cs0 valid before mcspix_clk first

edge

13.8

28.6

Hold time, mcspix_cs0 invalid after mcspix_clk last

edge

(1) The input timing requirements are given by considering a rise time and a fall time of 4 ns.

(2) In mcspix, x is equal to 1, 2, 3, or 4.

(3) Maximum cycle jitter supported by mcspix_clk input clock.

(4) P = mcspix_clk clock period

Table 6-79. McSPI Interface Switching Requirements^(1)(2)(3)(4)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

SS6 t_{d(CLKAE-SOMIV)}

SS7 t_{d(CS0AE-SOMIV)}

Delay time, mcspix_clk active edge to mcspix_somi

shifted

1.8

15.9

3.2

31.7

ns

Delay time, mcspix_cs0 active edge to Modes 0 and 2

mcspix_somi shifted

15.9

31.7

(1) The capacitive load is equivalent to 20 pF.

(2) In mcspix, x is equal to 1, 2, 3, or 4.

(3) The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all

software configurable.

(4) This timing applies to all configurations regardless of mcspix_clk polarity and which clock edges are used to drive output data and

capture input data.

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Mode 0 & 2

mcspix_cs0(EPOL=1)

SS0

SS4

SS1

SS5

mcspix_clk(POL=0)

mcspix_clk(POL=1)

SS0

SS1

SS2

SS3

Bit n-1

SS7

Bit n-1

mcspix_simo

mcspix_somi

Bit n-2

SS6

Bit n-3

Bit n-4

Bit 0

Bit n-2

Bit n-3

Bit 0

Mode 1 & 3

mcspix_cs0(EPOL=1)

mcspix_clk(POL=0)

mcspix_clk(POL=1)

SS0

SS1

SS0

SS1

SS4

SS5

SS3

SS2

Bit n-1

SS6

Bit n-1

mcspix_simo

mcspix_somi

Bit n-2

Bit n-3

Bit 1

Bit 0

Bit n-3

Bit 1

030-076

Figure 6-45. McSPI Interface – Transmit and Receive in Slave Mode⁽¹⁾⁽²⁾

(1) The active clock edge (rising or falling) on which mcspi_somi is driven and mcspi_simo data is latched is software configurable with the

bit MSPI_CHCONFx[0] = PHA and the bit MSPI_CHCONFx[1] = POL.

(2) The polarity of mcspix_csi is software configurable with the bit MSPI_CHCONFx[6] = EPOL In mcspix, x is equal to 1, 2, 3, or 4.

6.6.2.2 McSPI in Master Mode

Table 6-80 and Table 6-81 assume testing over the recommended operating conditions (see Figure 6-46).

Table 6-80. McSPI1, 2, and 4 Interface Timing Requirements – Master Mode⁽¹⁾⁽²⁾

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

SM2 t_{su(SOMIV-CLKAE)}

SM3 t_{h(SOMIV-CLKAE)}

Setup time, mcspix_somi valid before mcspix_clk

active edge

1.1

1.5

ns

Hold time, mcspix_somi valid after mcspix_clk active

edge

1.9

2.8

(1) The input timing requirements are given by considering a rise time and a fall time of 4 ns.

(2) In mcspix, x is equal to 1, 2, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 4.

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Table 6-81. McSPI1, 2, and 4 Interface Switching Characteristics – Master Mode^(1)(2)(3)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

48

MIN

MAX

24

1/SM0 1/t_c(CLK)

t_j(CLK)

Frequency, mcspix_clk

Cycle jitter⁽⁴⁾, mcspix_clk

MHz

ps

-200

200

-200

200

SM1

SM4

SM5

t_w(CLK)

Pulse duration, mcspix_clk high or low

0.45*P⁽⁵⁾0.55*P⁽⁵⁾0.45*P⁽0.55*P⁽⁵⁾

ns

5)

t_{d(CLKAE-SIMOV)}

t_{d(CSnA-CLKFE)}

Delay time, mcspix_clk active edge to mcspix_simo

shifted

–2.1

5

–2.1

11.3

ns

Delay time, mcspix_csi active to

mcspix_clk first edge

Modes 1

and 3

A⁽⁶⁾– 3.1

B⁽⁷⁾– 3.1

A⁽⁶⁾– 3.1

A⁽⁶⁾

4.4

B⁽⁷⁾

4.4

B⁽⁷⁾

4.4

A⁽⁶⁾

4.4

–

Modes 0

and 2

–

SM6

SM7

t_{d(CLKLE-CSnI)}

Delay time, mcspix_clk last edge to

mcspix_csi inactive

Modes 1

and 3

Modes 0

and 2

t_{d(CSnAE-SIMOV)}

Delay time, mcspix_csi active edge to Modes 0

mcspix_simo shifted and 2

5.0

11.3

(1) Timings are given for a maximum load capacitance of 20 pF for spix_csn signals, 30 pF for spix_clk and spix_simo signals with x = 1 or

2, and 20 pF for spi4_clk and spi4_simo signals.

(2) In mcspix, x is equal to 1, 2, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 4.

(3) The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all

software configurable.

(4) Maximum cycle jitter supported by mcspix_clk input clock.

(5) P = mcspix_clk clock period

(6) Case P = 20.8 ns, A = (TCS+0.5)*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). Case P > 20.8 ns, A = TCS*P (TCS is a

bitfield of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of the OMAP35x Technical Reference Manual

(TRM) [literature number SPRUF98].

(7) B = TCS*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of the OMAP35x

Technical Reference Manual (TRM) [literature number SPRUF98].

Table 6-82 and Table 6-83 assume testing over the recommended operating conditions (see Figure 6-46).

Table 6-82. McSPI 3 Interface Timing Requirements – Master Mode⁽¹⁾⁽²⁾

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

SM2 t_{su(SOMIV-CLKAE)}

SM3 t_{h(SOMIV-CLKAE)}

Setup time, mcspi3_somi valid before

mcspi3_clk active edge

1.5

4.3

ns

Hold time, mcspi3_somi valid after mcspi3_clk

active edge

2.8

5.9

(1) The input timing requirements are given by considering a rise time and a fall time of 4 ns.

(2) In mcspi3_csn, n is equal to 0 or 1. The polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and

mcspi3_somi is latched is all software configurable.

Table 6-83. McSPI3 Interface Switching Requirements – Master Mode^(1)(2)(3)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

1/SM 1/t_c(CLK)

0

Frequency, mcspix_clk

Cycle jitter⁽⁴⁾, mcspix_clk

24

12

MHz

ps

t_j(CLK)

-200

200

-200

200

(1) The capacitive load is equivalent to 20 pF.

(2) In mcspi3_csn, n is equal to 0 or 1. The polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and

mcspi3_somi is latched is all software configurable.

(3) This timing applies to all configurations regardless of McSPI3_CLK polarity and which clock edges are used to drive output data and

capture input data.

(4) Maximum cycle jitter supported by mcspix_clk input clock.

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Table 6-83. McSPI3 Interface Switching Requirements – Master Mode (continued)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

0.45*P⁽⁵⁾

MAX

0.55*P⁽⁵⁾

11.3

MIN

0.45*P⁽⁵⁾

–5.3

MAX

0.55*P⁽⁵⁾

23.6

SM1 t_w(CLK)

Pulse duration, mcspix_clk high or low

ns

SM4 t_{d(CLKAE-SIMOV)}

Delay time, mcspix_clk active edge to

mcspix_simo shifted

–2.1

SM5 t_{d(CSnA-CLKFE)}

Delay time, mcspix_csi active Modes 1

–4.4 + A⁽⁶⁾

–4.4 + B⁽⁷⁾

B – 4.4⁽⁷⁾

A⁽⁶⁾– 4.4

–10.1 + A⁽⁶⁾

–10.1 + B⁽⁷⁾

B – 10.1⁽⁷⁾

A⁽⁶⁾– 10.1

ns

to mcspix_clk first edge

and 3

Modes 0

and 2

SM6 t_d(CLK-CSn)

Delay time, mcspix_clk last

edge to mcspix_csi inactive

Modes 1

and 3

Modes 0

and 2

SM7 t_{d(CSnAE-SIMOV)}

Delay time, mcspix_csi active Modes 0

edge to mcspix_simo shifted and 2

11.3

23.6

(5) P = mcspi3_clk clock period

(6) Case P = 20.8 ns, A = (TCS + 0.5)*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). Case P > 20.8 ns, A = TCS*P (TCS is a bit

field of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of the OMAP35x Technical Reference Manual

(TRM) [literature number SPRUF98].

(7) B = TCS*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of the OMAP35x

Technical Reference Manual (TRM) [literature number SPRUF98].

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Mode 0 & 2

mcspix_csn(EPOL=1)

SM0

SM5

SM1

SM6

mcspix_clk(POL=0)

mcspix_clk(POL=1)

mcspix_simo

SM0

SM1

SM7

SM4

Bit n-2

Bit n-1

SM2

Bit n-3

Bit n-4

Bit 0

SM3

Bit n-1

mcspix_somi

Bit n-2

Bit n-3

Bit 0

Mode 1 & 3

mcspix_csn(EPOL=1)

mcspix_clk(POL=0)

SM0

SM1

SM0

SM1

SM5

SM6

mcspix_clk(POL=1)

mcspix_simo

SM4

Bit n-1

SM2

Bit n-2

Bit n-3

Bit 1

Bit 0

SM3

mcspix_somi

Bit n-1

Bit n-3

Bit 1

030-077

Figure 6-46. McSPI Interface – Transmit and Receive in Master Mode^(1)(2)(3)

(1) The active clock edge (rising or falling) on which mcspix_simo is driven and mcspi_somi data is latched is software configurable with the

bit MSPI_CHCONFx[0] = PHA and the bit MSPI_CHCONFx[1] = POL.

(2) The polarity of mcspix_csi is software configurable with the bit MSPI_CHCONFx[6] = EPOL.

(3) In mcspix, x is equal to 1. In mcspix_csn, n is equal to 0, 1, 2, or 3.

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6.6.3 Multiport Full-Speed Universal Serial Bus (USB) Interface

The OMAP3525 and OMAP3530 processors provide three USB ports working in full- and low-speed data

transactions (up to 12Mbit/s).

Connected to either a serial link controller (TLL modes) or a serial PHY (PHY interface modes) it supports:

•

6-pin (Tx: Dat/Se0 or Tx: Dp/Dm) unidirectional mode

4-pin bidirectional mode

3-pin bidirectional mode

6.6.3.1 Multiport Full-Speed Universal Serial Bus (USB) – Unidirectional Standard 6-pin Mode

Table 6-85 and Table 6-86 assume testing over the recommended operating conditions (see Figure 6-47).

Table 6-84. Low-/Full-Speed USB Timing Conditions – Unidirectional Standard 6-pin Mode

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

2.0

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

15.0

pF

Table 6-85. Low-/Full-Speed USB Timing Requirements – Unidirectional Standard 6-pin Mode

NO.

PARAMETER

1.15 V

MIN MAX

1.0 V

UNIT

MIN

MAX

FSU1

FSU2

FSU3

FSU4

t_d(Vp,Vm)

t_d(RCVU0)

t_d(RCVU1)

Time duration, mmx_rxdp and mmx_rxdm low together during

transition

14.0

ns

Time duration, mmx_rxdp and mmx_rxdm high together during

transition

8.0

14.0

8.0

Time duration, mmx_rrxcv undefine during a single end 0

(mmx_rxdp and mmx_rxdm low together)

14.0

8.0

Time duration, mmx_rxrcv undefine during a single end 1

(mmx_rxdp and mmx_rxdm high together)

Table 6-86. Low-/Full-Speed USB Switching Characteristics – Unidirectional Standard 6-pin Mode

NO.

PARAMETER

1.15 V

MIN

1.0 V

UNIT

MAX

84.8

1.5

MIN

81.8

MAX

84.8

1.5

FSU5

FSU6

FSU7

FSU8

FSU9

t_{d(TXENL-DATV)}

t_{d(TXENL-SE0V)}

t_s(DAT-SE0)

t_{d(DATI-TXENH)}

t_{d(SE0I-TXENH)}

t_R(do)

Delay time, mmx_txen_n low to mmx_txdat valid

Delay time, mmx_txen_n low to mmx_txse0 valid

Skew between mmx_txdat and mmx_txse0 transition

Delay time, mmx_txdat invalid to mmx_txen_n high

Delay time, mmx_txse0 invalid to mmx_txen_n high

Rise time, mmx_txen_n

81.8

ns

81.8

4.0

t_F(do)

Fall time, mmx_txen_n

t_R(do)

Rise time, mmx_txdat

t_F(do)

Fall time, mmx_txdat

t_R(do)

Rise time, mmx_txse0

t_F(do)

Fall time, mmx_txse0

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Transmit

mmx_txen_n

Receive

FSU5

FSU6

FSU8

FSU9

mmx_txdat

mmx_txse0

mmx_rxdp

mmx_rxdm

mmx_rxrcv

FSU7

FSU1

FSU2

FSU4

FSU1

FSU3

030-080

In mmx, x is equal to 0, 1, or 2.

Figure 6-47. Low-/Full-Speed USB – Unidirectional Standard 6-pin Mode

6.6.3.2 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional Standard 4-pin Mode

Table 6-88 and Table 6-89 assume testing over the recommended operating conditions (see Figure 6-48).

Table 6-87. Low-/Full-Speed USB Timing Conditions – Bidirectional Standard 4-pin Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

t_R

Input signal rise time

Input signal fall time

2.0

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

15.0

pF

Table 6-88. Low-/Full-Speed USB Timing Requirements – Bidirectional Standard 4-pin Mode

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

FSU10 t_d(DAT,SE0)

FSU11 t_d(DAT,SE0)

FSU12 t_d(RCVU0)

FSU13 t_d(RCVU1)

Time duration, mmx_txdat and mmx_txse0 low together

during transition

14.0

ns

Time duration, mmx_txdat and mmx_txse0 high together

during transition

8.0

14.0

8.0

Time duration, mmx_rrxcv undefine during a single end 0

(mmx_txdat and mmx_txse0 low together)

14.0

8.0

Time duration, mmx_rxrcv undefine during a single end 1

(mmx_txdat and mmx_txse0 high together)

Table 6-89. Low-/Full-Speed USB Switching Characteristics – Bidirectional Standard 4-pin Mode

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

81.8

MIN

81.8

MAX

84.8

1.5

FSU14

FSU15

FSU16

t_{d(TXENL-DATV)}

t_{d(TXENL-SE0V)}

t_s(DAT-SE0)

Delay time, mmx_txen_n low to mmx_txdat valid

Delay time, mmx_txen_n low to mmx_txse0 valid

84.8

1.5

ns

Skew between mmx_txdat and mmx_txse0

transition

FSU17

t_{d(DATV-TXENH)}

Delay time, mmx_txdat invalid before mmx_txen_n

high

81.8

ns

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Table 6-89. Low-/Full-Speed USB Switching Characteristics – Bidirectional Standard 4-pin Mode

(continued)

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

FSU18

t_{d(SE0V-TXENH)}

Delay time, mmx_txse0 invalid before mmx_txen_n

high

81.8

ns

t_R(txen)

t_F(txen)

t_R(dat)

t_F(dat)

t_R(se0)

t_F(se0)

Rise time, mmx_txen_n

Fall time, mmx_txen_n

Rise time, mmx_txdat

Fall time, mmx_txdat

Rise time, mmx_txse0

Fall time, mmx_txse0

4.0

ns

Transmit

FSU14

mmx_txen_n

Receive

FSU10

FSU17

FSU18

FSU11

FSU13

mmx_txdat

mmx_txse0

mmx_rxrcv

FSU15

FSU16

FSU10

FSU12

030-081

In mmx, x is equal to 0, 1, or 2.

Figure 6-48. Low-/Full-Speed USB – Bidirectional Standard 4-pin Mode

6.6.3.3 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional Standard 3-pin Mode

Table 6-91 and Table 6-92 assume testing over the recommended operating conditions below (see

Figure 6-49).

Table 6-90. Low-/Full-Speed USB Timing Conditions – Bidirectional Standard 3-pin Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

t_R

Input signal rise time

Input signal fall time

2.0

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

15.0

pF

Table 6-91. Low-/Full-Speed USB Timing Requirements – Bidirectional Standard 3-pin Mode

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

FSU19

FSU20

t_d(DAT,SE0)

Time duration, mmx_txdat and mmx_txse0 low together

during transition

14.0

ns

Time duration, mmx_tsdat and mmx_txse0 high

together during transition

8.0

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Table 6-92. Low-/Full-Speed USB Switching Characteristics – Bidirectional Standard 3-pin Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

81.8

MAX

84.8

1.5

MIN

81.8

MAX

84.8

1.5

FSU21

FSU22

FSU23

t_{d(TXENL-DATV)}

t_{d(TXENL-SE0V)}

t_s(DAT-SE0)

Delay time, mmx_txen_n low to mmx_txdat valid

Delay time, mmx_txen_n low to mmx_txse0 valid

ns

Skew between mmx_txdat and mmx_txse0

transition

FSU24

FSU25

t_{d(DATI-TXENH)}

t_{d(SE0I-TXENH)}

Delay time, mmx_txdat invalid to mmx_txen_n

high

81.8

ns

Delay time, mmx_txse0 invalid to mmx_txen_n

high

t_R(do)

t_F(do)

t_R(do)

t_F(do)

t_R(do)

t_F(do)

Rise time, mmx_txen_n

Fall time, mmx_txen_n

Rise time, mmx_txdat

Fall time, mmx_txdat

Rise time, mmx_txse0

Fall time, mmx_txse0

4.0

ns

Transmit

mmx_txen_n

mmx_txdat

mmx_txse0

Receive

FSU21

FSU24

FSU19

FSU20

FSU22

FSU23

FSU25

FSU19

030-082

In mmx, x is equal to 0, 1, or 2.

Figure 6-49. Low-/Full-Speed USB – Bidirectional Standard 3-pin Mode

6.6.3.4 Multiport Full-Speed Universal Serial Bus (USB) – Unidirectional TLL 6-pin Mode

Table 6-94 and Table 6-95 assume testing over the recommended operating conditions (see Figure 6-50).

Table 6-93. Low-/Full-Speed USB Timing Conditions – Unidirectional TLL 6-pin Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

t_R

Input signal rise time

Input signal fall time

2

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

15

pF

Table 6-94. Low-/Full-Speed USB Timing Requirements – Unidirectional TLL 6-pin Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

FSUT1

FSUT2

t_d(SE0,DAT)

Time duration, mmx_txse0 and mmx_txdat low

together during transition

14

ns

Time duration, mmx_txse0 and mmx_txdat high

together during transition

8

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Table 6-95. Low-/Full-Speed USB Switching Characteristics – Unidirectional TLL 6-pin Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

81.8

MAX

84.8

MIN

81.8

MAX

84.8

FSUT3

FSUT4

FSUT5

FSUT6

FSUT7

t_d(TXENH-DPV)

t_d(TXENH-DMV)

t_d(DPI-TXENL)

t_d(DMI-TXENL)

t_s(DP-DM)

Delay time, mmx_txen_n high to mmx_rxdp valid

Delay time, mmx_txen_n high to mmx_rxdm valid

Delay time, mmx_rxdp invalid mmx_txen_n low

Delay time, mmx_rxdm invalid mmx_txen_n low

ns

Skew between mmx_rxdp and mmx_rxdm

transition

1.5

FSUT8

t_s(DP,DM-RCV)

Skew between mmx_rxdp, mmx_rxdm, and

mmx_rxrcv transition

ns

t_R(rxrcv)

t_F(rxrcv)

t_R(dp)

Rise time, mmx_rxrcv

Fall time, mmx_rxrcv

Rise time, mmx_rxdp

Fall time, mmx_rxdp

Rise time, mmx_rxdm

Fall time, mmx_rxdm

4

ns

t_F(dp)

t_R(dm)

t_F(dm)

mmx_txen_n

Transmit

Receive

FSUT1

FSUT2

mmx_txdat

mmx_txse0

mmx_rxdp

mmx_rxdm

mmx_rxrcv

FSUT1

FSUT2

FSUT3

FSUT5

FSUT6

FSUT4

FSUT7

FSUT8

030-083

In mmx, x is equal to 0, 1, or 2.

Figure 6-50. Low-/Full-Speed USB – Unidirectional TLL 6-pin Mode

6.6.3.5 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional TLL 4-pin Mode

Table 6-97 and Table 6-98 assume testing over the recommended operating conditions (see Figure 6-51).

Table 6-96. Low-/Full-Speed USB Timing Conditions – Bidirectional TLL 4-pin Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

t_R

Input signal rise time

Input signal fall time

2

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

15

pF

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Table 6-97. Low-/Full-Speed USB Timing Requirements – Bidirectional TLL 4-pin Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

FSUT9

t_d(DAT,SE0)

Time duration, mmx_txdat and mmx_txse0 low

together during transition

14

ns

FSUT10 t_d(DAT,SE0)

Time duration, mmx_tsdat and mmx_txse0 high

together during transition

8

Table 6-98. Low-/Full-Speed USB Switching Characteristics – Bidirectional TLL 4-pin Mode

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

81.8

MIN

81.8

MAX

84.8

1.5

FSUT11 t_{d(TXENL-DATV)}

FSUT12 t_{d(TXENL-SE0V)}

FSUT13 t_s(DAT-SE0)

Delay time, mmx_txen_n active to mmx_txdat valid

Delay time, mmx_txen_n active to mmx_txse0 valid

84.8

1.5

ns

Skew between mmx_txdat and mmx_txse0

transition

FSUT14 t_s(DP,DM-RCV)

Skew between mmx_rxdp, mmx_rxdm, and

mmx_rxrcv transition

1.5

ns

FSUT15 t_{d(DATI-TXENL)}

Delay time, mmx_txse0 invalid to mmx_txen_n Low

Delay time, mmx_txdat invalid to mmx_txen_n Low

Rise time, mmx_rxrcv

81.8

ns

FSUT16 t_{d(SE0I-TXENL)}

t_R(rcv)

t_F(rcv)

t_R(dat)

t_F(dat)

t_R(se0)

t_F(se0)

4

Fall time, mmx_rxrcv

Rise time, mmx_txdat

Fall time, mmx_txdat

Rise time, mmx_txse0

Fall time, mmx_txse0

mmx_txen_n

mmx_txdat

mmx_txse0

mmx_rxrcv

Transmit

FSUT11

Receive

FSUT9

FSUT15

FSUT16

FSUT10

FSUT12

FSUT13

FSUT14

FSUT9

FSUT10

030-084

In mmx, x is equal to 0, 1, or 2.

Figure 6-51. Low-/Full-Speed USB – Bidirectional TLL 4-pin Mode

6.6.3.6 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional TLL 3-pin Mode

Table 6-100 and Table 6-101 assume testing over the recommended operating conditions (see

Figure 6-52).

Table 6-99. Low-/Full-Speed USB Timing Conditions – Bidirectional TLL 3-pin Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

t_R

Input signal rise time

2

ns

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Table 6-99. Low-/Full-Speed USB Timing Conditions – Bidirectional TLL 3-pin Mode (continued)

TIMING CONDITION PARAMETER

VALUE

UNIT

t_F

Input signal fall time

2

ns

Output Conditions

C_LOAD

Output load capacitance

15

pF

Table 6-100. Low-/Full-Speed USB Timing Requirements – Bidirectional TLL 3-pin Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

FSUT17 t_d(DAT,SE0)Time duration, mmx_txdat and mmx_txse0 low

together during transition

14

ns

FSUT18 t_d(DAT,SE0)Time duration, mmx_tsdat and mmx_txse0 high

together during transition

8

Table 6-101. Low-/Full-Speed USB Switching Characteristics – Bidirectional TLL 3-pin Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

81.8

MAX

84.8

1.5

MIN

81.8

MAX

84.8

1.5

FSUT19 t_{d(TXENH-DATV)}

FSUT20 t_{d(TXENH-SE0V)}

FSUT21 t_s(DAT-SE0)

Delay time, mmx_txen_n high to mmx_txdat valid

Delay time, mmx_txen_n high to mmx_txse0 valid

ns

Skew between mmx_txdat and mmx_txse0

transition

FSUT22 t_{d(DATI-TXENL)}

Delay time, mmx_txdat invalid mmx_txen_n low

Delay time, mmx_txse0 invalid mmx_txen_n low

Rise time, mmx_txdat

81.8

ns

FSUT23 t_{d(SE0I-TXENL)}

t_R(dat)

t_F(dat)

t_R(se0)

t_F(se0)

t_R(do)

t_F(do)

4

Fall time, mmx_txdat

Rise time, mmx_txse0

Fall time, mmx_txse0

Rise time, mmx_txse0

Fall time, mmx_txse0

Receive

FSUT17

mmx_txen_n

mmx_txdat

mmx_txse0

Transmit

FSUT19

FSUT22

FSUT23

FSUT18

FSUT20

FSUT21

FSUT17

FSUT18

030-085

In mmx, x is equal to 0, 1, or 2.

Figure 6-52. Low-/Full-Speed USB – Bidirectional TLL 3-pin Mode

6.6.4 Multiport High-Speed Universal Serial Bus (USB) Timing

In addition to the full-speed USB controller, a high-speed (HS) USB OTG controller is instantiated inside

OMAP3525 and OMAP3530. It allows high-speed transactions (up to 480 Mbit/s) on the USB ports 0, 1, 2,

and 3.

•

Port 0:

–

12-bit slave mode (SDR)

•

Port 1 and port 2:

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–

12-bit master mode (SDR)

12-bit TLL master mode (SDR)

8-bit TLL master mode (DDR)

•

Port 3:

–

12-bit TLL master mode (SDR)

8-bit TLL master mode (DDR)

6.6.4.1 High-Speed Universal Serial Bus (USB) on Port 0 – 12-bit Slave Mode

Table 6-103 and Table 6-104 assume testing over the recommended operating conditions (see

Figure 6-53).

Table 6-102. High-Speed USB Timing Conditions – 12-bit Slave Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

t_r

Input Signal Rising Time

Input Signal Falling Time

2.00

ns

t_f

Output Conditions

C_load

Output Load Capacitance

3.50

pF

Table 6-103. High-Speed USB Timing Requirements – 12-bit Slave Mode⁽¹⁾

NO.

PARAMETER

1.15 V

UNIT

MIN

MAX

60.03

500.00

HSU0＝ f_p(CLK)

hsusb0_clk clock frequency⁽²⁾⁽³⁾

Cycle Jitter⁽³⁾, hsusb0_clk

MHz

ps

t_j(CLK)

HSU3

HSU4

t_s(DIRV-CLKH)

t_s(NXTV-CLKH)

t_{h(CLKH-DIRIV)}

t_{h(CLKH-NXT/IV)}

t_{s(DATAV-CLKH)}

t_{h(CLKH-DATIV)}

Setup time, hsusb0_dir valid before hsusb0_clk rising edge

Setup time, hsusb0_nxt valid before hsusb0_clk rising edge

Hold time, hsusb0_dir valid after hsusb0_clk rising edge

Hold time, hsusb0_nxt valid after hsusb0_clk rising edge

Setup time, hsusb0_data[0:7] valid before hsusb0_clk rising edge

Hold time, hsusb0_data[0:7] valid after hsusb0_clk rising edge

6.7

0.0

6.7

0.0

ns

HSU5

HSU6

ns

(1) The timing requirements are assured for the cycle jitter error condition specified.

(2) Related with the input maximum frequency supported by the I/F module.

(3) Maximum cycle jitter supported by clk input clock.

Table 6-104. High-Speed USB Switching Characteristics – 12-bit Slave Mode

NO.

PARAMETER

1.15 V

UNIT

MIN

0.5

MAX

HSU1 t_d(clkL-STPV)

t_{d(clkL-STPIV)}

HSU2 t_d(clkL-DV)

t_d(clkL-DIV)

Delay time, hsusb0_clk high to output usb0_stp valid

Delay time, hsusb0_clk high to output usb0_stp invalid

Delay time, hsusb0_clk high to output hsusb0_data[0:7] valid

Delay time, hsusb0_clk high to output hsusb0_data[0:7] invalid

Rising time, output signals

9.0

ns

9.0

0.5

t_r(do)

2.0

t_f(do)

Falling time, output signals

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HSU0

hsusb0_clk

HSU1

hsusb0_stp

hsusb0_dir_&_nxt

hsusb0_data[7:0]

HSU3

HSU4

HSU5

HSU2

HSU6

Data_OUT

Data_IN

030-086

Figure 6-53. High-Speed USB – 12-bit Slave Mode

6.6.4.2 High-Speed Universal Serial Bus (USB) on Ports 1 and 2 – 12-bit Master Mode

Table 6-106 and Table 6-107 assume testing over the recommended operating conditions (see

Figure 6-54).

Table 6-105. High-Speed USB Timing Conditions – 12-bit Master Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

t_R

Input signal rise time

Input signal fall time

2

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

3

pF

Table 6-106. High-Speed USB Timing Requirements – 12-bit Master Mode⁽¹⁾

NO.

PARAMETER

1.15 V

UNIT

MIN

9.3

0.2

9.3

0.2

MAX

HSU3 t_s(DIRV-CLKH)

t_s(NXTV-CLKH)

HSU4 t_{h(CLKH-DIRIV)}

t_{h(CLKH-NXT/IV)}

Setup time, hsusbx_dir valid before hsusbx_clk rising edge

Setup time, hsusbx_nxt valid before hsusbx_clk rising edge

Hold time, hsusbx_dir valid after hsusbx_clk rising edge

Hold time, hsusbx_nxt valid after hsusbx_clk rising edge

Setup time, hsusbx_data[0:7] valid before hsusbx_clk rising edge

Hold time, hsusbx_data[0:7] valid after hsusbx_clk rising edge

ns

HSU5 t_{s(DATAV-CLKH)}

HSU6 t_{h(CLKH-DATIV)}

(1) In hsusbx, x is equal to 1 or 2.

Table 6-107. High-Speed USB Switching Characteristics – 12-bit Master Mode⁽¹⁾

N O.

PARAMETER

1.15 V

UNIT

MIN

MAX

60

HSU0

HSU1

HSU2

f_p(CLK)

hsusbx_clk clock frequency

Jitter standard deviation⁽²⁾, hsusbx_clk

MHz

ps

t_j(CLK)

200

13

t_d(clkL-STPV)

t_{d(clkL-STPIV)}

t_d(clkL-DV)

t_d(clkL-DIV)

Delay time, hsusbx_clk high to output hsusbx_stp valid

Delay time, hsusbx_clk high to output hsusbx_stp invalid

Delay time, hsusbx_clk high to output hsusbx_data[0:7] valid

Delay time, hsusbx_clk high to output hsusbx_data[0:7] invalid

ns

2

ns

13

ns

(1) In hsusbx, x is equal to 1 or 2.

(2) The jitter probability density can be approximated by a Gaussian function.

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Table 6-107. High-Speed USB Switching Characteristics – 12-bit Master Mode (continued)

N O.

PARAMETER

1.15 V

UNIT

MIN

MAX

t_R(do)

t_F(do)

Rise time, output signals

Fall time, output signals

2

ns

HSU0

hsusbx_clk

hsusbx_stp

HSU1

HSU3

HSU4

HSU6

hsusbx_dir_&_nxt

hsusbx_data[7:0]

HSU5

HSU2

Data_OUT

Data_IN

030-087

In hsusbx, x is equal to 1 or 2.

Figure 6-54. High-Speed USB – 12-bit Master Mode

6.6.4.3 High-Speed Universal Serial Bus (USB) on Ports 1, 2, and 3 – 12-bit TLL Master Mode

Table 6-109 and Table 6-110 assume testing over the recommended operating conditions (see

Figure 6-55).

Table 6-108. High-Speed USB Timing Conditions – 12-bit TLL Master Mode

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

2

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

3

pF

Table 6-109. High-Speed USB Timing Requirements – 12-bit TLL Master Mode⁽¹⁾

NO.

PARAMETER

1.15 V

UNIT

MIN

6

MAX

HSU2 t_s(STPV-CLKH)

HSU3 t_{s(CLKH-STPIV)}

HSU4 t_{s(DATAV-CLKH)}

HSU5 t_{h(CLKH-DATIV)}

Setup time, hsusbx_tll_stp valid before hsusbx_tll_clk rising edge

Hold time, hsusbx_tll_stp valid after hsusbx_tll_clk rising edge

Setup time, hsusbx_tll_data[7:0] valid before hsusbx_tll_clk rising edge

Hold time, hsusbx_tll_data[7:0] valid after hsusbx_tll_clk rising edge

ns

0

6

0

(1) In hsusbx, x is equal to 1, 2, or 3.

Table 6-110. High-Speed USB Switching Characteristics – 12-bit TLL Master Mode⁽¹⁾

NO.

PARAMETER

1.15 V

UNIT

MIN

MAX

HSU0 f_p(CLK)

hsusbx_tll_clk clock frequency

60

MHz

(1) In hsusbx, x is equal to 1, 2, or 3.

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Table 6-110. High-Speed USB Switching Characteristics – 12-bit TLL Master Mode (continued)

NO.

PARAMETER

1.15 V

UNIT

MIN

MAX

200

9

t_j(CLK)

Jitter standard deviation⁽²⁾, hsusbx_tll_clk

ps

ns

HSU6 t_d(CLKL-DIRV)

t_{d(CLKL-DIRIV)}

t_d(CLKL-NXTV)

t_{d(CLKL-NXTIV)}

HSU7 t_d(CLKL-DV)

t_d(CLKL-DIV)

Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir valid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir invalid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt valid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt invalid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[7:0] valid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[7:0] invalid

Rise time, output signals

0

9

t_R(do)

2

t_F(do)

Fall time, output signals

(2) The jitter probability density can be approximated by a Gaussian function.

HSU0

hsusbx_tll_clk

HSU3

HSU2

hsusbx_tll_stp

HSU6

HSU7

hsusbx_tll_dir_&_nxt

HSU4

HSU7

HSU5

Data_IN

Data_OUT

hsusbx_tll_data[7:0]

030-088

In hsusbx, x is equal to 1, 2, or 3.

Figure 6-55. High-Speed USB – 12-bit TLL Master Mode

6.6.4.4 High-Speed Universal Serial Bus (USB) on Ports 1, 2, and 3 – 8-bit TLL Master Mode

Table 6-112 and Table 6-113 assume testing over the recommended operating conditions (see

Figure 6-56).

Table 6-111. High-Speed USB Timing Conditions – 8-bit TLL Master Mode

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

2

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

3

pF

Table 6-112. High-Speed USB Timing Requirements – 8-bit TLL Master Mode⁽¹⁾

NO.

PARAMETER

1.15 V

UNIT

MIN

6

MAX

HSU2 t_s(STPV-CLKH)

HSU3 t_{s(CLKH-STPIV)}

HSU4 t_{s(DATAV-CLKH)}

Setup time, hsusbx_tll_stp valid before hsusbx_tll_clk rising edge

Hold time, hsusbx_tll_stp valid after hsusbx_tll_clk rising edge

Setup time, hsusbx_tll_data[3:0] valid before hsusbx_tll_clk rising edge

ns

0

3

(1) In hsusbx, x is equal to 1, 2, or 3.

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Table 6-112. High-Speed USB Timing Requirements – 8-bit TLL Master Mode (continued)

NO.

PARAMETER

1.15 V

UNIT

MIN

MAX

HSU5 t_{h(CLKH-DATIV)}

Hold time, hsusbx_tll_data[3:0] valid after hsusbx_tll_clk rising edge

–0.8

ns

Table 6-113. High-Speed USB Switching Characteristics – 8-bit TLL Master Mode⁽¹⁾

NO.

PARAMETER

1.15 V

UNIT

MIN

MAX

60

HSU0

f_p(CLK)

hsusbx_tll_clk clock frequency

Jitter standard deviation⁽²⁾, hsusbx_tll_clk

MHz

ps

t_j(CLK)

200

52.4%

9

HSU1

HSU6

t_j(CLK)

Duty cycle, hsusbx_tll_clk pulse duration (low and high)

Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir valid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir invalid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt valid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt invalid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[3:0] valid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[3:0] invalid

Rise time, output signals

47.6%

t_d(CLKL-DIRV)

t_{d(CLKL-DIRIV)}

t_d(CLKL-NXTV)

t_{d(CLKL-NXTIV)}

t_d(CLKL-DV)

t_d(CLKL-DIV)

t_R(do)

ns

0

9

4

HSU7

HSU8

2

t_F(do)

Fall time, output signals

(1) In hsusbx, x is equal to 1, 2, or 3.

(2) The jitter probability density can be approximated by a Gaussian function.

HSU0

HSU1

hsusbx_tll_clk

HSU3

HSU2

hsusbx_tll_stp

HSU6

hsusbx_tll_dir_&_nxt

HSU5

HSU4

HSU5

HSU8

HSU7

HSU4

HSU7

Data_IN

Data_IN_(n+1)

Data_IN_(n+2)

Data_OUT

Data_OUT_(n+1)

hsusbx_tll_data[3:0]

030-089

In hsusbx, x is equal to 1, 2, or 3.

Figure 6-56. High-Speed USB – 8-bit TLL Master Mode

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6.6.5 I²C Interface

The multimaster I²C peripheral provides an interface between two or more devices via an I²C serial bus.

The I²C controller supports the multimaster mode which allows more than one device capable of

controlling the bus to be connected to it. Each I²C device is recognized by a unique address and can

operate as either transmitter or receiver, according to the function of the device. In addition to being a

transmitter or receiver, a device connected to the I²C bus can also be considered as master or slave when

performing data transfers. This data transfer is carried out via two serial bidirectional wires:

•

An SDA data line

An SCL clock line

The following sections illustrate the data transfer is in master or slave configuration with 7-bit addressing

format. The I²C interface is compliant with Philips I²C specification version 2.1. It supports standard mode

(up to 100K bits/s), fast mode (up to 400K bits/s) and high-speed mode (up to 3.4Mb/s) .

6.6.5.1 I²C Standard/Fast-Speed Mode

Table 6-114. I²C Standard/Fast-Speed Mode Timings

NO.

PARAMETER⁽¹⁾

Standard Mode

Fast Mode

UNIT

MIN

MAX

MIN

MAX

f_SCL

Clock Frequency, i2cX_scl

100

400

kHz

µs

ns

I1

I2

I3

I4

I5

t_w(SCLH)

Pulse Duration, i2cX_scl high

4

0.6

1.3

100⁽²⁾

0⁽³⁾

t_w(SCLL)

Pulse Duration, i2cX_scl low

4.7

250

0⁽³⁾

4.7

t_{su(SDAV-SCLH)}

t_{h(SCLH–SDAV)}

t_{su(SDAL-SCLH)}

Setup time, i2cX_sda valid before i2cX_scl active level

Hold time, i2cX_sda valid after i2cX_scl active level

3.45⁽⁴⁾

0.9⁽⁴⁾

µs

Setup time, i2cX_scl high after i2cX_sda low (for a

START⁽⁵⁾condition or a repeated START condition)

0.6

I6

I7

I8

t_{h(SCLH–SDAH)}

t_{h(SCLH–RSTART)}

t_w(SDAH)

Hold time, i2cX_sda low level after i2cX_scl high level

(STOP condition)

4

0.6

1.3

µs

Hold time, i2cX_sda low level after i2cX_scl high level (for

a repeated START condition)

Pulse duration, i2cX_sda high between STOP and START

conditions

4.7

t_R(SCL)

t_F(SCL)

t_R(SDA)

t_F(SDA)

CB

Rise time, i2cX_scl

1000

300

60⁽⁶⁾

ns

pF

Fall time, i2cX_scl

Rise time, i2cX_sda

Fall time, i2cX_sda

1000

300

60⁽⁶⁾

Capacitive load for each bus line

(1) In i2cX, X is equal to 1, 2, 3, or 4. Note that I2C4 is master transmitter only.

(2) A fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement t_{su(SDAV-SCLH)}≥ 250 ns must then be

met. This is automatically the case if the device does not stretch the low period of the i2cx_scl. If such a device does stretch the low

period of the i2cx_scl, it must output the next data bit to the i2cx_sda line t_r(SDA)max + t_{su(SDAV-SCLH)}= 1000 + 250 = 1250 ns (according

to the standard-mode I²C-bus specification) before the i2cx_scl line is released.

(3) The device provides (via the I²C bus) a hold time of at least 300 ns for the i2cx_sda signal (refer to the fall and rise time of i2cx_scl) to

bridge the undefined region of the falling edge of i2cx_scl.

(4) The maximum t_h(SCLH-SDA)has only to be met if the device does not stretch the low period of the i2cx_scl signal.

(5) After this time, the first clock is generated.

(6) Maximum reference load for i2c4_scl and i2c4_sda is CB = 15 pF.

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START

START REPEAT

START

STOP

i2cX_sda

i2cX_scl

I2

I5

I8

I7

I6

I1

I3

I4

I6

030-093

Figure 6-57. I²C – Standard/Fast Mode

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6.6.5.2 I²C High-Speed Mode

Table 6-115. I²C HighSpeed Mode Timings⁽¹⁾⁽²⁾

NO.

PARAMETER

CB = 100 pF MAX

CB = 400 pF MAX

UNIT

MIN

MAX

MIN

MAX

f_SCL

Clock frequency, i2cX_scl

Pulse duration, i2cX_scl high

Pulse duration, i2cX_scl low

3.4

1.7

MHz

µs

I1

I2

I3

t_w(SCLH)

t_w(SCLL)

60⁽³⁾

160⁽³⁾

10

120⁽³⁾

320⁽³⁾

10

µs

t_{su(SDAV-SCLH)}

Setup time, i2cX_sda valid before i2cX_scl

active level

ns

I4

I5

t_{h(SCLH–SDAV)}

t_{su(SDAL-SCLH)}

Hold time, i2cX_sda valid after i2cX_scl active

level

0⁽²⁾

160

70

0⁽²⁾

160

150

µs

Setup time, i2cX_scl high after i2cX_sda low

(for a START⁽⁴⁾condition or a repeated START

condition)

I6

I7

t_{h(SCLH–SDAH)}

Hold time, i2cX_sda low level after i2cX_scl high

level (STOP condition)

160

µs

t_{h(SCLH–RSTART)}

Hold time, i2cX_sda low level after i2cX_scl high

level (for a repeated START condition)

ns

t_R(SCL)

Rise time, i2cX_scl

40

80

ns

Rise time, i2cX_scl after a repeated START

condition and after a bit acknowledge

160

t_F(SCL)

t_R(SDA)

t_F(SDA)

C_B

Fall time, i2cX_scl

40

80

ns

Rise time, i2cX_sda

160

Fall time, i2cX_sda

80

60⁽⁵⁾

Capacitive load for each bus line

pF

(1) In i2cX, X is equal to 1, 2, 3, or 4. Note that I2C4 is master transmitter only.

(2) The device provides (via the I²C bus) a hold time of at least 300 ns for the i2cx_sda signal (refer to the fall and rise time of i2cx_scl) to

bridge the undefined region of the falling edge of i2cx_scl.

(3) HS-mode master devices generate a serial clock signal with a high to low ratio of 1 to 2. t_w(SCLL)> 2 × t_w(SCLH)

.

(4) After this time, the first clock is generated.

(5) Maximum reference load for i2c4_scl and i2c4_sda is C_B= 15 pF.

START REPEAT

STOP

I7

i2cX_sda

I5

I6

I1

I2

I3

I4

i2cX_scl

030-094

Figure 6-58. I²C – High-Speed Mode^(1)(2)(3)

(1) HS-mode master devices generate a serial clock signal with a high-to-low ratio of 1 to 2. t_w(SCLL)> 2 x t_w(SCLH)

(2) In i2cX, X is equal to 1, 2, 3, or 4. Note that I2C4 is master transmitter only.

(3) After this time, the first clock is generated.

.

Table 6-116. Correspondence Standard vs. TI Timing References

TI-OMAP

STANDARD-I²C

S/F Mode

F_SCL

HS Mode

F_SCLH

f_SCL

I1

I2

I3

I4

I5

t_w(SCLH)

T_HIGH

t_w(SCLL)

T_LOW

t_{su(SDAV-SCLH)}

t_h(SCLH-SDAV)

t_{su(SDAL-SCLH)}

T_SU;DAT

T_SU;STA

T_SU;DAT

T_SU;STA

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Table 6-116. Correspondence Standard vs. TI Timing References (continued)

TI-OMAP

STANDARD-I²C

S/F Mode

T_HD;STA

T_SU;STO

T_BUF

HS Mode

T_HD;STA

T_SU;STO

I6

I7

I8

t_h(SCLH-SDAH)

t_{h(SCLH-RSTART)}

t_w(SDAH)

6.6.6 HDQ / 1-Wire Interfaces

This module is intended to work with both the HDQ and the 1-Wire protocols. The protocols use a single

wire to communicate between the master and the slave. The protocols employ an asynchronous return to

1 mechanism where, after any command, the line is pulled high.

6.6.6.1 HDQ Protocol

Table 6-117 and Table 6-118 assume testing over the recommended operating conditions (see

Figure 6-59 through Figure 6-62).

Table 6-117. HDQ Timing Requirements

PARAMETER

t_CYCD

DESCRIPTION

Bit window

MIN

MAX

UNIT

253

µs

t_HW1

68

t_HW0

180

t_RSPS

Command to host respond time⁽¹⁾

(1) Defined by software.

Table 6-118. HDQ Switching Characteristics

PARAMETER

DESCRIPTION

MIN

TYP

193

63

MAX

UNIT

t_B

Break timing

Break recovery

Bit window

µs

t_BR

t_CYCH

t_DW1

t_DW0

253

1.3

Sends1 (write)

Sends0 (write)

101

tB

tBR

HDQ

030-095

Figure 6-59. HDQ Break (Reset) Timing

tCYCH

tHW0

tHW1

HDQ

030-096

Figure 6-60. HDQ Read Bit Timing (Data)

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tCYCD

tDW0

tDW1

HDQ

030-097

Figure 6-61. HDQ Write Bit Timing (Command/Address or Data)

Command _byte_written

0_(LSB)

Data_byte_received

tRSPS

1

Break

1

6

7_(MSB)

0_(LSB)

6

HDQ

030-098

Figure 6-62. HDQ Communication Timing

6.6.6.2 1-Wire Protocol

Table 6-119 and Table 6-120 assume testing over the recommended operating conditions (see

Figure 6-63 through Figure 6-65).

Table 6-119. 1-Wire Timing Requirements

PARAMETER

t_PDH

DESCRIPTION

MIN

MAX

UNIT

Presence pulse delay high

Presence pulse delay low

Read bit-zero time

68

µs

t_PDL

68 – t_PDH

t_RDV+ t_REL

102

Table 6-120. 1-Wire Switching Characteristics

PARAMETER

t_RSTL

DESCRIPTION

MIN

TYP

484

102

1.3

MAX

UNIT

Reset time low

µs

t_RSTH

Reset time high

Write bit cycle time

Write bit-one time

Write bit-zero time

Recovery time

t_SLOT

t_LOW1

t_LOW0

101

134

13

t_REC

t_LOWR

Read bit strobe time

tRSTH

tPDL

tRTSL

tPDH

1-WIRE

030-099

Figure 6-63. 1-Wire Break (Reset) Timing

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tSLOT_and_ tREC

tRDV_and_ tREL

tLOWR

1-WIRE

030-100

Figure 6-64. 1-Wire Read Bit Timing (Data)

tSLOT_and_tREC

tLOW0

1-WIRE

tLOW1

030-101

Figure 6-65. 1-Wire Write Bit Timing (Command/Address or Data)

6.6.7 UART IrDA Interface

The IrDA module can operate in three different modes:

•

Slow infrared (SIR) (≤115.2 Kbits/s)

Medium infrared (MIR) (0.576 Mbits/s and 1.152 Mbits/s)

Fast infrared (FIR) (4 Mbits/s)

For more information about this interface, see the UART/IrDA chapter in the OMAP35x Technical

Reference Manual (TRM) [literature number SPRUF98].

Pulse duration

90%

50%

10%

t_r

t_f

030-118

Figure 6-66. UART IrDA Pulse Parameters

6.6.7.1 IrDA—Receive Mode

Table 6-121. UART IrDA—Signaling Rate and Pulse Duration—Receive Mode

ELECTRICAL PULSE DURATION

SIGNALING RATE

UNIT

MIN

NOMINAL

SIR

MAX

2.4 Kbit/s

9.6 Kbit/s

19.2 Kbit/s

1.41

78.1

19.5

9.75

88.55

22.13

11.07

µs

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Table 6-121. UART IrDA—Signaling Rate and Pulse Duration—Receive Mode

(continued)

ELECTRICAL PULSE DURATION

SIGNALING RATE

UNIT

MIN

1.41

NOMINAL

4.87

MAX

5.96

4.34

2.23

38.4 Kbit/s

57.6 Kbit/s

115.2 Kbit/s

µs

3.25

1.62

MIR

0.576 Mbit/s

1.152 Mbit/s

297.2

149.6

416

208

518.8

258.4

ns

FIR

4.0 Mbit/s (Single pulse)

4.0 Mbit/s (Double pulse)

67

125

250

164

289

ns

190

Table 6-122. UART IrDA—Rise and Fall Time—Receive

Mode

PARAMETER

MAX

UNIT

t_R

t_F

Rising time,

uart3_rx_irrx

200

ns

Falling time,

uart3_rx_irrx

200

ns

6.6.7.2 IrDA—Transmit Mode

Table 6-123. UART IrDA—Signaling Rate and Pulse Duration—Transmit Mode

SIGNALING RATE

ELECTRICAL PULSE DURATION

UNIT

MIN

NOMINAL

SIR

MAX

2.4 Kbit/s

9.6 Kbit/s

78.1

19.5

9.75

4.87

3.25

1.62

78.1

19.5

9.75

4.87

3.25

1.62

MIR

78.1

19.5

9.75

4.87

3.25

1.62

µs

19.2 Kbit/s

38.4 Kbit/s

57.6 Kbit/s

115.2 Kbit/s

0.576 Mbit/s

1.152 Mbit/s

414

206

416

419

211

ns

208

FIR

4.0 Mbit/s (Single pulse)

4.0 Mbit/s (Double pulse)

123

248

125

128

253

ns

250

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6.7 Removable Media Interfaces

6.7.1 High-Speed Multimedia Memory Card (MMC) and Secure Digital IO Card (SDIO) Timing

The MMC/SDIO host controller provides an interface to high-speed and standard MMC, SD memory

cards, or SDIO cards. The application interface is responsible for managing transaction semantics. The

MMC/SDIO host controller deals with MMC/SDIO protocol at transmission level, packing data, adding

CRC, start/end bit, and checking for syntactical correctness.

There are three MMC interfaces on the OMAP3525 and OMAP3530:

•

MMC/SD/SDIO Interface 1:

–

1.8 V/3 V support

8 bits

•

MMC/SD/SDIO Interface 2:

–

1.8 V support

8 bits

4 bits with external transceiver allowing to support 3 V peripherals. Transceiver direction control

signals are multiplexed with the upper four data bits.

•

MMC/SD/SDIO Interface 3:

–

1.8 V support

8 bits

6.7.1.1 MMC/SD/SDIO in SD Identification Mode

Table 6-125 and Table 6-126 assume testing over the recommended operating conditions and electrical

characteristic conditions.

Table 6-124. MMC/SD/SDIO Timing Conditions – SD Identification Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

SD Identification Mode

Input Conditions

t_R

Input signal rise time

Input signal fall time

10

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

40

pF

Table 6-125. MMC/SD/SDIO Timing Requirements – SD Identification Mode^(1)(2)(3)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

SD Identification Mode

MMC/SD/SDIO Interface 1 (1.8 V IO)

HSSD3/SD3 t_{su(CMDV-CLKIH)}

Setup time, mmc1_cmd valid before

mmc1_clk rising clock edge

1198.4

1249.2

1198.4

1249.2

ns

HSSD4/SD4 t_{su(CLKIH-CMDIV)}

Hold time, mmc1_cmd valid after

mmc1_clk rising clock edge

MMC/SD/SDIO Interface 1 (3.0 V IO)

HSSD3/SD3 t_{su(CMDV-CLKIH)}

HSSD4/SD4 t_{su(CLKIH-CMDIV)}

MMC/SD/SDIO Interface 2

Setup time, mmc1_cmd valid before

mmc1_clk rising clock edge

1198.4

1249.2

1198.4

1249.2

ns

Hold time, mmc1_cmd valid after

mmc1_clk rising clock edge

(1) Timing parameters are referred to output clock specified in Table 6-126.

(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-126.

(3) Corresponding figures showing timing parameters are common with other interface modes. (See SD and HS SD modes).

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Table 6-125. MMC/SD/SDIO Timing Requirements – SD Identification Mode (continued)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

HSSD3/SD3 t_{su(CMDV-CLKIH)}

HSSD4/SD4 t_{su(CLKIH-CMDIV)}

Setup time, mmc2_cmd valid before

mmc2_clk rising clock edge

1198.4

ns

Hold time, mmc2_cmd valid after

mmc2_clk rising clock edge

1249.2

MMC/SD/SDIO Interface 3

HSSD3/SD3 t_{su(CMDV-CLKIH)}

Setup time, mmc3_cmd valid before

mmc3_clk rising clock edge

1198.4

1249.2

1198.4

1249.2

ns

HSSD4/SD4 t_{su(CLKIH-CMDIV)}

Hold time, mmc3_cmd valid after

mmc3_clk rising clock edge

Table 6-126. MMC/SD/SDIO Switching Characteristics – SD Identification Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

SD Identification Mode

(3)

1 /

1/t_c(clk)

Frequency⁽²⁾, mmcx_ clk

0.4

MHz

(HSSD1/SD1

)

HSSD2/SD2 t_W(clkH)

HSSD2/SD2 t_W(clkL)

t_dc(clk)

Typical pulse duration, output clk high

Typical pulse duration, output clk low

Duty cycle error, output clk

X⁽⁴⁾*PO⁽⁵⁾

Y⁽⁶⁾*PO⁽⁵⁾

X⁽⁴⁾*PO⁽⁵⁾

Y⁽⁶⁾*PO⁽⁵⁾

ns

ps

125

t_j(clk)

Jitter standard deviation⁽⁷⁾, output clk

200

MMC/SD/SDIO Interface 1 (1.8 V IO)

t_c(clk)

Rise time, output clk

10

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

Fall time, output clk

Rise time, output data

Fall time, output data

10

HSSD5/SD5 t_d(CLKOH-CMD)Delay time, mmc1_clk rising clock edge to

mmc1_cmd transition

6.3

2492.7

6.3

2492.7

MMC/SD/SDIO Interface 1 (3.0 V IO)

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

10

0

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

10

HSSD5/SD5 t_d(CLKOH-CMD)Delay time, mmc1_clk rising clock edge to

mmc1_cmd transition

2492.7

MMC/SD/SDIO Interface 2

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

10

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

10

HSSD5/SD5 t_d(CLKOH-CMD)Delay time, mmc2_clk rising clock edge to

mmc2_cmd transition

2492.7

MMC/SD/SDIO Interface 3

t_c(clk)

Rise time, output clk

10

ns

(1) Corresponding figures showing timing parameters are common with other interface modes (see SD and HS SD modes).

(2) Related with the output clk maximum and minimum frequencies programmable in I/F module.

(3) In mmcx_clk, 'x' is equal to 1, 2, or 3.

(4) The X parameter is defined as shown in Table 6-127.

(5) PO = output clk period in ns.

(6) The Y parameter is defined as shown in Table 6-128.

(7) The jitter probability density can be approximated by a Gaussian function.

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Table 6-126. MMC/SD/SDIO Switching Characteristics – SD Identification Mode (continued)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

10

MIN

MAX

10

t_W(clkH)

t_W(clkL)

t_dc(clk)

Fall time, output clk

Rise time, output data

Fall time, output data

ns

10

HSSD5/SD5 t_d(CLKOH-CMD)Delay time, mmc3_clk rising clock edge to

mmc3_cmd transition

6.3

2492.7

6.3

2492.7

Table 6-127. X Parameter

CLKD

1 or Even

Odd

X

0.5

(trunk[CLKD/2]+1)/CLKD

Table 6-128. Y Parameter

CLKD

1 or Even

Odd

Y

0.5

(trunk[CLKD/2])/CLKD

For details about clock division factor CLKD, see the OMAP35x Technical Reference Manual (TRM)

[literature number SPRUF98].

6.7.1.2 MMC/SD/SDIO in High-Speed MMC Mode

Table 6-130 and Table 6-131 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-67 and Figure 6-68).

Table 6-129. MMC/SD/SDIO Timing Conditions – High-Speed MMC Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

High-Speed MMC Mode

Input Conditions

t_R

Input signal rise time

Input signal fall time

3

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

30

pF

Table 6-130. MMC/SD/SDIO Timing Requirements – High-Speed MMC Mode^(1)(2)(3)(4)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

High-Speed MMC Mode

MMC/SD/SDIO Interface 1 (1.8 V IO)

MMC3 t_{su(CMDV-CLKIH)}

MMC4 t_{su(CLKIH-CMDIV)}

MMC7 t_{su(DATxV-CLKIH)}

MMC8 t_{su(CLKIH-DATxIV)}

Setup time, mmc1_cmd valid before mmc1_clk

rising clock edge

5.6

2.3

5.6

2.3

26

1.9

26

ns

Hold time, mmc1_cmd valid after mmc1_clk

rising clock edge

Setup time, mmc1_datx valid before mmc1_clk

rising clock edge

Hold time, mmc1_datx valid after mmc1_clk

rising clock edge

1.9

(1) Timing parameters are referred to output clock specified in Table 6-131.

(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-131.

(3) Corresponding figures showing timing parameters are common with Standard MMC mode (See Figure 6-67 and Figure 6-68)

(4) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.

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Table 6-130. MMC/SD/SDIO Timing Requirements – High-Speed MMC Mode (continued)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

MMC/SD/SDIO Interface 1 (3.0 V IO)

MMC3 t_{su(CMDV-CLKIH)}

MMC4 t_{su(CLKIH-CMDIV)}

MMC7 t_{su(DATxV-CLKIH)}

MMC8 t_{su(CLKIH-DATxIV)}

Setup time, mmc1_cmd valid before mmc1_clk

rising clock edge

5.6

2.3

5.6

2.3

26

1.9

26

ns

Hold time, mmc1_cmd valid after mmc1_clk

rising clock edge

Setup time, mmc1_datx valid before mmc1_clk

rising clock edge

Hold time, mmc1_datx valid after mmc1_clk

rising clock edge

1.9

MMC/SD/SDIO Interface 2

MMC3 t_{su(CMDV-CLKIH)}

Setup time, mmc2_cmd valid before mmc2_clk

rising clock edge

5.6

2.3

5.6

2.3

26

1.9

26

ns

MMC4 t_{su(CLKIH-CMDIV)}

MMC7 t_{su(DATxV-CLKIH)}

MMC8 t_{su(CLKIH-DATxIV)}

Hold time, mmc2_cmd valid after mmc2_clk

rising clock edge

Setup time, mmc2_datx valid before mmc2_clk

rising clock edge

Hold time, mmc2_datx valid after mmc2_clk

rising clock edge

1.9

MMC/SD/SDIO Interface 3

MMC3 t_{su(CMDV-CLKIH)}

Setup time, mmc3_cmd valid before mmc3_clk

rising clock edge

5.6

2.3

5.6

2.3

26

1.9

26

ns

MMC4 t_{su(CLKIH-CMDIV)}

MMC7 t_{su(DATxV-CLKIH)}

MMC8 t_{su(CLKIH-DATxIV)}

Hold time, mmc3_cmd valid after mmc3_clk

rising clock edge

Setup time, mmc3_datx valid before mmc3_clk

rising clock edge

Hold time, mmc3_datx valid after mmc3_clk

rising clock edge

1.9

Table 6-131. MMC/SD/SDIO Switching Characteristics – High-Speed MMC Mode⁽¹⁾

N O.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

High-Speed MMC Mode

(3)

1/MMC 1/t_c(clk)

1

Frequency⁽²⁾, mmcx_ clk

48

24

MHz

MMC2

t_W(clkH)

t_W(clkL)

t_dc(clk)

t_j(clk)

Typical pulse duration, output clk high

Typical pulse duration, output clk low

Duty cycle error, output clk

X⁽⁴⁾*PO⁽⁵⁾

Y⁽⁶⁾*PO⁽⁵⁾

X⁽⁴⁾*PO⁽⁵⁾

Y⁽⁶⁾*PO⁽⁵⁾

ns

ps

1041.7

200

2083.3

200

Jitter standard deviation⁽⁷⁾, output clk

MMC/SD/SDIO Interface 1 (1.8 V IO)

t_c(clk)

Rise time, output clk

3

ns

t_W(clkH)

t_W(clkL)

Fall time, output clk

Rise time, output data

Fall time, output data

3

t_dc(clk)

3

MMC5

t_d(CLKOH-CMD)

Delay time, mmc1_clk rising clock edge to

mmc1_cmd transition

3.7

14.1

4.1

34.5

(1) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.

(2) Related with the output clk maximum and minimum frequencies programmable in I/F module.

(3) In mmcx_clk, 'x' is equal to 1, 2, or 3.

(4) The X parameter is defined as shown in Table 6-132.

(5) PO = output clk period in ns.

(6) The Y parameter is defined as shown in Table 6-133.

(7) The jitter probability density can be approximated by a Gaussian function.

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Table 6-131. MMC/SD/SDIO Switching Characteristics – High-Speed MMC Mode (continued)

N O.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

MMC6

t_{d(CLKOH-DATx)}

Delay time, mmc1_clk rising clock edge to

mmc1_datx transition

3.7

14.1

4.1

34.5

ns

MMC/SD/SDIO Interface 1 (3.0 V IO)

t_c(clk)

Rise time, output clk

3

ns

t_W(clkH)

t_W(clkL)

Fall time, output clk

Rise time, output data

Fall time, output data

3

t_dc(clk)

3

MMC5

MMC6

t_d(CLKOH-CMD)

Delay time, mmc1_clk rising clock edge to

mmc1_cmd transition

3.7

14.1

4.1

34.5

t_{d(CLKOH-DATx)}

Delay time, mmc1_clk rising clock edge to

mmc1_datx transition

14.1

34.5

ns

MMC/SD/SDIO Interface 2

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

3

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

3

MMC5

MMC6

t_d(CLKOH-CMD)

Delay time, mmc2_clk rising clock edge to

mmc2_cmd transition

3.7

14.1

4.1

34.5

t_{d(CLKOH-DATx)}

Delay time, mmc2_clk rising clock edge to

mmc2_datx transition

16.5

36.9

ns

MMC/SD/SDIO Interface 3

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

3

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

3

MMC5

MMC6

t_d(CLKOH-CMD)

Delay time, mmc3_clk rising clock edge to

mmc3_cmd transition

3.7

14.1

4.1

34.5

t_{d(CLKOH-DATx)}

Delay time, mmc3_clk rising clock edge to

mmc3_datx transition

14.1

34.5

ns

Table 6-132. X Parameter

CLKD

1 or Even

Odd

X

0.5

(trunk[CLKD/2]+1)/CLKD

Table 6-133. Y Parameter

CLKD

1 or Even

Odd

Y

0.5

(trunk[CLKD/2])/CLKD

For details about clock division factor CLKD, see the OMAP35x Technical Reference Manual (TRM)

[literature number SPRUF98].

6.7.1.3 MMC/SD/SDIO in Standard MMC Mode and MMC Identification Mode

Table 6-135 and Table 6-136 assume testing over the recommended operating conditions and electrical

characteristic conditions.

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Table 6-134. MMC/SD/SDIO Timing Conditions – Standard MMC Mode and MMC Identification Mode

TIMING CONDITION PARAMETER

Standard MMC Mode and MMC Identification Mode

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

10

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

30

pF

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Table 6-135. MMC/SD/SDIO Timing Requirements – Standard MMC Mode and MMC Identification

Mode⁽¹⁾⁽²⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

Standard MMC Mode and MMC Identification Mode

MMC/SD/SDIO Interface 1 (1.8 V IO)

MMC3 t_{su(CMDV-CLKIH)}

MMC4 t_{su(CLKIH-CMDIV)}

MMC7 t_{su(DATxV-CLKIH)}

MMC8 t_{su(CLKIH-DATxIV)}

Setup time, mmc1_cmd valid before

mmc1_clk rising clock edge

13.6

8.9

65.7

8.9

ns

Hold time, mmc1_cmd valid after mmc1_clk

rising clock edge

Setup time, mmc1_datx valid before

mmc1_clk rising clock edge

13.6

8.9

65.7

8.9

Hold time, mmc1_datx valid after mmc1_clk

rising clock edge

MMC/SD/SDIO Interface 1 (3.0 V IO)

MMC3 t_{su(CMDV-CLKIH)}

MMC4 t_{su(CLKIH-CMDIV)}

MMC7 t_{su(DATxV-CLKIH)}

MMC8 t_{su(CLKIH-DATxIV)}

Setup time, mmc1_cmd valid before

mmc1_clk rising clock edge

13.6

8.9

65.7

8.9

ns

Hold time, mmc1_cmd valid after mmc1_clk

rising clock edge

Setup time, mmc1_datx valid before

mmc1_clk rising clock edge

13.6

8.9

65.7

8.9

Hold time, mmc1_datx valid after mmc1_clk

rising clock edge

MMC/SD/SDIO Interface 2

MMC3 t_{su(CMDV-CLKIH)}

Setup time, mmc2_cmd valid before

mmc2_clk rising clock edge

13.6

8.9

65.7

8.9

ns

MMC4 t_{su(CLKIH-CMDIV)}

MMC7 t_{su(DATxV-CLKIH)}

MMC8 t_{su(CLKIH-DATxIV)}

Hold time, mmc2_cmd valid after mmc2_clk

rising clock edge

Setup time, mmc2_datx valid before

mmc2_clk rising clock edge

13.6

8.9

65.7

8.9

Hold time, mmc2_datx valid after mmc2_clk

rising clock edge

MMC/SD/SDIO Interface 3

MMC3 t_{su(CMDV-CLKIH)}

Setup time, mmc3_cmd valid before

mmc3_clk rising clock edge

13.6

8.9

65.7

8.9

ns

MMC4 t_{su(CLKIH-CMDIV)}

MMC7 t_{su(DATxV-CLKIH)}

MMC8 t_{su(CLKIH-DATxIV)}

Hold time, mmc3_cmd valid after mmc3_clk

rising clock edge

Setup time, mmc3_datx valid before

mmc3_clk rising clock edge

13.6

8.9

65.7

8.9

Hold time, mmc3_datx valid after mmc3_clk

rising clock edge

(1) Timing parameters are referred to output clock specified in Table 6-136.

(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-136.

Table 6-136. MMC/SD/SDIO Switching Characteristics – Standard MMC Mode and MMC Identification

Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

MMC Identification Mode

(2)

1/MMC 1/t_c(clk)

1

Frequency⁽¹⁾, mmcx_ clk

0.4

MHz

ns

MMC2

t_W(clkH)

Typical pulse duration, output clk high

X⁽³⁾*PO⁽⁴⁾

(1) Related with the output clk maximum and minimum frequencies programmable in I/F module.

(2) In mmcx_clk, 'x' is equal to 1, 2, or 3.

(3) The X parameter is defined as shown in Table 6-137.

(4) PO = output clk period in ns.

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Table 6-136. MMC/SD/SDIO Switching Characteristics – Standard MMC Mode and MMC Identification

Mode (continued)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

MMC2

t_W(clkL)

t_dc(clk)

t_j(clk)

Typical pulse duration, output clk low

Duty cycle error, output clk

Jitter standard deviation⁽⁵⁾, output clk

Y*PO⁽⁴⁾

ns

ps

125

200

125

200

Standard MMC Mode

(2)

1/MMC 1/t_c(clk)

1

Frequency⁽¹⁾, mmcx_ clk

19.2

9.6

MHz

MMC2

t_W(clkH)

t_W(clkL)

t_dc(clk)

t_j(clk)

Typical pulse duration, output clk high

Typical pulse duration, output clk low

Duty cycle error, output clk

X⁽³⁾*PO⁽⁴⁾

Y*PO⁽⁴⁾

X⁽³⁾*PO⁽⁴⁾

Y*PO⁽⁴⁾

ns

ps

2604.2

200

5208.3

200

Jitter standard deviation⁽⁵⁾, output clk

MMC/SD/SDIO Interface 1 (1.8 V IO)

t_c(clk)

Rise time, output clk

10

ns

t_W(clkH)

t_W(clkL)

Fall time, output clk

Rise time, output data

Fall time, output data

10

t_dc(clk)

10

MMC5

MMC6

t_d(CLKOH-CMD)

Delay time, mmc1_clk rising clock edge to

mmc1_cmd transition

4.3

47.8

4.3

99.9

t_{d(CLKOH-DATx)}

Delay time, mmc1_clk rising clock edge to

mmc1_datx transition

47.8

99.9

ns

MMC/SD/SDIO Interface 1 (3.0 V IO)

t_c(clk)

Rise time, output clk

10

ns

t_W(clkH)

t_W(clkL)

Fall time, output clk

Rise time, output data

Fall time, output data

10

t_dc(clk)

10

MMC5

MMC6

t_d(CLKOH-CMD)

Delay time, mmc1_clk rising clock edge to

mmc1_cmd transition

4.3

47.8

4.3

99.9

t_{d(CLKOH-DATx)}

Delay time, mmc1_clk rising clock edge to

mmc1_datx transition

47.8

99.9

ns

MMC/SD/SDIO Interface 2

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

10

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

10

MMC5

MMC6

t_d(CLKOH-CMD)

Delay time, mmc2_clk rising clock edge to

mmc2_cmd transition

4.3

47.8

4.3

99.9

t_{d(CLKOH-DATx)}

Delay time, mmc2_clk rising clock edge to

mmc2_datx transition

47.8

99.9

ns

MMC/SD/SDIO Interface 3

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

10

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

10

MMC5

MMC6

t_d(CLKOH-CMD)

Delay time, mmc3_clk rising clock edge to

mmc3_cmd transition

4.3

47.8

4.3

99.9

t_{d(CLKOH-DATx)}

Delay time, mmc3_clk rising clock edge to

mmc3_datx transition

47.8

99.9

ns

(5) The jitter probability density can be approximated by a Gaussian function.

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Table 6-137. X Parameter

CLKD

1 or Even

Odd

X

0.5

(trunk[CLKD/2]+1)/CLKD

Table 6-138. Y Parameter

CLKD

1 or Even

Odd

Y

0.5

(trunk[CLKD/2])/CLKD

For details about clock division factor CLKD, see the OMAP35x Technical Reference Manual (TRM)

[literature number SPRUF98].

MMC1

MMC2

mmcx_clk

MMC3

MMC7

MMC4

mmcx_cmd

MMC8

mmcx_dat[3:0]

030-104

In mmcx, x is equal to 1, 2, or 3.

Figure 6-67. MMC/SD/SDIO – High-Speed and Standard MMC Modes – Data/Command Receive

MMC1

MMC2

mmcx_clk

MMC5

MMC6

MMC5

mmcx_cmd

MMC6

mmcx_dat[3:0]

030-105

In mmcx, x is equal to 1, 2, or 3.

Figure 6-68. MMC/SD/SDIO – High-Speed and Standard MMC Modes – Data/Command Transmit

6.7.1.4 MMC/SD/SDIO in High-Speed SD Mode

Table 6-140 and Table 6-141 assume testing over the recommended operating conditions and electrical

characteristic conditions.

Table 6-139. MMC/SD/SDIO Timing Conditions – High-Speed SD Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

High-Speed SD Mode

Input Conditions

t_R

Input signal rise time

Input signal fall time

3

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

40

pF

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Table 6-140. MMC/SD/SDIO Timing Requirements – High-Speed SD Mode^(1)(2)(3)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

High-Speed SD Mode

MMC/SD/SDIO Interface 1 (1.8 V IO)

HSSD3 t_{su(CMDV-CLKIH)}

HSSD4 t_{su(CLKIH-CMDIV)}

HSSD7 t_{su(DATxV-CLKIH)}

HSSD8 t_{su(CLKIH-DATxIV)}

Setup time, mmc1_cmd valid before

mmc1_clk rising clock edge

5.6

2.3

5.6

2.3

26

1.9

26

ns

Hold time, mmc1_cmd valid after mmc1_clk

rising clock edge

Setup time, mmc1_datx valid before

mmc1_clk rising clock edge

Hold time, mmc1_datx valid after mmc1_clk

rising clock edge

1.9

MMC/SD/SDIO Interface 1 (3.0 V IO)

HSSD3 t_{su(CMDV-CLKIH)}

HSSD4 t_{su(CLKIH-CMDIV)}

HSSD7 t_{su(DATxV-CLKIH)}

HSSD8 t_{su(CLKIH-DATxIV)}

Setup time, mmc1_cmd valid before

mmc1_clk rising clock edge

5.6

2.3

5.6

2.3

26

1.9

26

ns

Hold time, mmc1_cmd valid after mmc1_clk

rising clock edge

Setup time, mmc1_datx valid before

mmc1_clk rising clock edge

Hold time, mmc1_datx valid after mmc1_clk

rising clock edge

1.9

MMC/SD/SDIO Interface 2

HSSD3 t_{su(CMDV-CLKIH)}

Setup time, mmc2_cmd valid before

mmc2_clk rising clock edge

5.6

2.3

5.6

2.3

26

1.9

26

ns

HSSD4 t_{su(CLKIH-CMDIV)}

HSSD7 t_{su(DATxV-CLKIH)}

HSSD8 t_{su(CLKIH-DATxIV)}

Hold time, mmc2_cmd valid after mmc2_clk

rising clock edge

Setup time, mmc2_datx valid before

mmc2_clk rising clock edge

Hold time, mmc2_datx valid after mmc2_clk

rising clock edge

1.9

MMC/SD/SDIO Interface 3

HSSD3 t_{su(CMDV-CLKIH)}

Setup time, mmc3_cmd valid before

mmc3_clk rising clock edge

5.6

2.3

5.6

2.3

26

1.9

26

ns

HSSD4 t_{su(CLKIH-CMDIV)}

HSSD7 t_{su(DATxV-CLKIH)}

HSSD8 t_{su(CLKIH-DATxIV)}

Hold time, mmc3_cmd valid after mmc3_clk

rising clock edge

Setup time, mmc3_datx valid before

mmc3_clk rising clock edge

Hold time, mmc3_datx valid after mmc3_clk

rising clock edge

1.9

(1) Timing Parameters are referred to output clock specified in Table 6-141.

(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-141.

(3) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.

Table 6-141. MMC/SD/SDIO Switching Characteristics – High-Speed SD Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

High-Speed SD Mode

(2)

1/HSSD 1/t_c(clk)

1

Frequency⁽¹⁾, mmcx_ clk

48

24

ns

HSSD2 t_W(clkH)

Typical pulse duration, output clk high

X⁽³⁾*PO⁽⁴⁾

(1) Related with the output clk maximum and minimum frequencies programmable in I/F module.

(2) In mmcx_clk, 'x' is equal to 1, 2, or 3.

(3) The X parameter is defined as shown in Table 6-142.

(4) PO = output clk period in ns.

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Table 6-141. MMC/SD/SDIO Switching Characteristics – High-Speed SD Mode (continued)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

HSSD2 t_W(clkL)

t_dc(clk)

Typical pulse duration, output clk low

Duty cycle error, output clk

Jitter standard deviation⁽⁶⁾, output clk

Y⁽⁵⁾*PO⁽⁴⁾

ns

ps

1041.7

200

2083.3

200

t_j(clk)

MMC/SD/SDIO Interface 1 (1.8 V IO)

t_c(clk)Rise time, output clk

t_W(clkH)

3

ns

Fall time, output clk

Rise time, output data

Fall time, output data

t_W(clkL)

3

t_dc(clk)

3

HSSD5 t_d(CLKOH-CMD)

Delay time, mmc1_clk rising clock edge to

mmc1_cmd transition

3.7

14.1

4.1

34.5

HSSD6 t_{d(CLKOH-DATx)}

Delay time, mmc1_clk rising clock edge to

mmc1_datx transition

14.1

34.5

ns

MMC/SD/SDIO Interface 1 (3.0 V IO)

t_c(clk)Rise time, output clk

t_W(clkH)

3

ns

Fall time, output clk

Rise time, output data

Fall time, output data

t_W(clkL)

3

t_dc(clk)

3

HSSD5 t_d(CLKOH-CMD)

Delay time, mmc1_clk rising clock edge to

mmc1_cmd transition

3.7

14.1

4.1

34.5

HSSD6 t_{d(CLKOH-DATx)}

Delay time, mmc1_clk rising clock edge to

mmc1_datx transition

14.1

34.5

ns

MMC/SD/SDIO Interface 2

t_c(clk)

t_W(clkH)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

3

ns

t_W(clkL)

3

t_dc(clk)

3

HSSD5 t_d(CLKOH-CMD)

Delay time, mmc2_clk rising clock edge to

mmc2_cmd transition

3.7

14.1

4.1

34.5

HSSD6 t_{d(CLKOH-DATx)}

Delay time, mmc2_clk rising clock edge to

mmc2_datx transition

14.1

34.5

ns

MMC/SD/SDIO Interface 3

t_c(clk)

t_W(clkH)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

3

ns

t_W(clkL)

3

t_dc(clk)

3

HSSD5 t_d(CLKOH-CMD)

Delay time, mmc3_clk rising clock edge to

mmc3_cmd transition

3.7

14.1

4.1

34.5

HSSD6 t_{d(CLKOH-DATx)}

Delay time, mmc3_clk rising clock edge to

mmc3_datx transition

14.1

34.5

ns

(5) The Y parameter is defined as shown in Table 6-143.

(6) The jitter probability density can be approximated by a Gaussian function.

Table 6-142. X Parameters

CLKD

1 or Even

Odd

X

0.5

(trunk[CLKD/2]+1)/CLKD

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Table 6-143. Y Parameters

CLKD

1 or Even

Odd

Y

0.5

(trunk[CLKD/2])/CLKD

For details about clock division factor CLKD, see the OMAP35x Technical Reference Manual (TRM)

[literature number SPRUF98].

HSSD1

HSSD2

mmcx_clk

HSSD3

HSSD7

HSSD4

mmcx_cmd

HSSD8

mmcx_dat[3:0]

030-106

In mmcx, x is equal to 1, 2, or 3.

Figure 6-69. MMC/SD/SDIO – High-Speed SD Mode – Data/Command Receive

HSSD1

HSSD2

mmcx_clk

HSSD5

HSSD6

HSSD5

mmcx_cmd

HSSD6

mmcx_dat[3:0]

030-107

In mmcx, x is equal to 1, 2, or 3.

Figure 6-70. MMC/SD/SDIO – High-Speed SD Mode – Data/Command Transmit

6.7.1.5 MMC/SD/SDIO in Standard SD Mode

Table 6-145 and Table 6-146 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-71).

Table 6-144. MMC/SD/SDIO Timing Conditions – Standard SD Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Standard SD Mode

Input Conditions

t_R

Input signal rise time

Input signal fall time

10

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

40

pF

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Table 6-145. MMC/SD/SDIO Timing Requirements – Standard SD Mode^(1)(2)(3)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

Standard SD Mode

MMC/SD/SDIO Interface 1 (1.8 V IO)

SD3 t_{su(CMDV-CLKIH)}

SD4 t_{su(CLKIH-CMDIV)}

SD7 t_{su(DATxV-CLKIH)}

SD8 t_{su(CLKIH-DATxIV)}

Setup time, mmc1_cmd valid before mmc1_clk

rising clock edge

6.2

19.4

6.2

47.7

19.2

47.7

19.2

ns

Hold time, mmc1_cmd valid after mmc1_clk

rising clock edge

Setup time, mmc1_datx valid before mmc1_clk

rising clock edge

Hold time, mmc1_datx valid after mmc1_clk

rising clock edge

19.4

MMC/SD/SDIO Interface 1 (3.0 V IO)

SD3 t_{su(CMDV-CLKIH)}

SD4 t_{su(CLKIH-CMDIV)}

SD7 t_{su(DATxV-CLKIH)}

SD8 t_{su(CLKIH-DATxIV)}

Setup time, mmc1_cmd valid before mmc1_clk

rising clock edge

6.2

19.4

6.2

47.7

19.2

47.7

19.2

ns

Hold time, mmc1_cmd valid after mmc1_clk

rising clock edge

Setup time, mmc1_datx valid before mmc1_clk

rising clock edge

Hold time, mmc1_datx valid after mmc1_clk

rising clock edge

19.4

MMC/SD/SDIO Interface 2

SD3 t_{su(CMDV-CLKIH)}

Setup time, mmc2_cmd valid before mmc2_clk

rising clock edge

6.2

19.4

6.2

47.7

19.2

47.7

19.2

ns

SD4 t_{su(CLKIH-CMDIV)}

SD7 t_{su(DATxV-CLKIH)}

SD8 t_{su(CLKIH-DATxIV)}

Hold time, mmc2_cmd valid after mmc2_clk

rising clock edge

Setup time, mmc2_datx valid before mmc2_clk

rising clock edge

Hold time, mmc2_datx valid after mmc2_clk

rising clock edge

19.4

MMC/SD/SDIO Interface 3

SD3 t_{su(CMDV-CLKIH)}

Setup time, mmc3_cmd valid before mmc3_clk

rising clock edge

6.2

19.4

6.2

47.7

19.2

47.7

19.2

ns

SD4 t_{su(CLKIH-CMDIV)}

SD7 t_{su(DATxV-CLKIH)}

SD8 t_{su(CLKIH-DATxIV)}

Hold time, mmc3_cmd valid after mmc3_clk

rising clock edge

Setup time, mmc3_datx valid before mmc3_clk

rising clock edge

Hold time, mmc3_datx valid after mmc3_clk

rising clock edge

19.4

(1) Timing parameters are referred to output clock specified in Table 6-146.

(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-146.

(3) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.

Table 6-146. MMC/SD/SDIO Switching Characteristics – Standard SD Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

Standard SD Mode

1/SD 1/t_c(clk)

1

Frequency ⁽¹⁾, mmcx_clk⁽²⁾

24

12

MHz

ns

SD2 t_W(clkH)

Typical pulse duration, output clk high

X⁽³⁾*PO⁽⁴⁾

(1) Related with the output clk maximum and minimum frequencies programmable in I/F module.

(2) In mmcx_clk, 'x' is equal to 1, 2, or 3.

(3) The X parameter is defined as shown in Table 6-147.

(4) PO = output clk period in ns.

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Table 6-146. MMC/SD/SDIO Switching Characteristics – Standard SD Mode (continued)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

SD2 t_W(clkL)

t_dc(clk)

Typical pulse duration, output clk low

Duty cycle error, output clk

Jitter standard deviation⁽⁶⁾, output clk

Y⁽⁵⁾*PO⁽⁴⁾

ns

ps

2083.3

200

4166.7

200

t_j(clk)

MMC/SD/SDIO Interface 1 (1.8 V IO)

t_c(clk)Rise time, output clk

t_W(clkH)

10

77

ns

Fall time, output clk

Rise time, output data

Fall time, output data

t_W(clkL)

10

t_dc(clk)

10

SD5 t_d(CLKOH-CMD)

Delay time, mmc1_clk rising clock edge to

mmc1_cmd transition

6.1

35.5

6.3

SD6 t_{d(CLKOH-DATx)}

Delay time, mmc1_clk rising clock edge to

mmc1_datx transition

35.5

77

ns

MMC/SD/SDIO Interface 1 (3.0 V IO)

t_c(clk)Rise time, output clk

t_W(clkH)

10

77

ns

Fall time, output clk

Rise time, output data

Fall time, output data

t_W(clkL)

10

t_dc(clk)

10

SD5 t_d(CLKOH-CMD)

Delay time, mmc1_clk rising clock edge to

mmc1_cmd transition

6.1

35.5

6.3

SD6 t_{d(CLKOH-DATx)}

Delay time, mmc1_clk rising clock edge to

mmc1_datx transition

35.5

77

ns

MMC/SD/SDIO Interface 2

t_c(clk)Rise time, output clk

t_W(clkH)

10

77

ns

Fall time, output clk

Rise time, output data

Fall time, output data

t_W(clkL)

10

t_dc(clk)

10

SD5 t_d(CLKOH-CMD)

Delay time, mmc2_clk rising clock edge to

mmc2_cmd transition

6.1

35.5

6.3

SD6 t_{d(CLKOH-DATx)}

Delay time, mmc2_clk rising clock edge to

mmc2_datx transition

35.5

77

ns

MMC/SD/SDIO Interface 3

t_c(clk)Rise time, output clk

t_W(clkH)

10

77

ns

Fall time, output clk

Rise time, output data

Fall time, output data

t_W(clkL)

10

t_dc(clk)

10

SD5 t_d(CLKOH-CMD)

Delay time, mmc3_clk rising clock edge to

mmc3_cmd transition

6.1

35.5

6.3

SD6 t_{d(CLKOH-DATx)}

Delay time, mmc3_clk rising clock edge to

mmc3_datx transition

35.5

77

ns

(5) The Y parameter is defined as shown in Table 6-148.

(6) The jitter probability density can be approximated by a Gaussian function.

Table 6-147. X Parameter

CLKD

1 or Even

Odd

X

0.5

(trunk[CLKD/2]+1)/CLKD

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Table 6-148. Y Parameter

CLKD

1 or Even

Odd

Y

0.5

(trunk[CLKD/2])/CLKD

For details about clock division factor CLKD, see the OMAP35x Technical Reference Manual (TRM)

[literature number SPRUF98].

SD1

SD2

mmcx_clk

SD3

SD4

mmcx_cmd

SD7

SD8

mmcx_dat[3:0]

030-108

In mmcx, x is equal to 1, 2, or 3.

Figure 6-71. MMC/SD/SDIO – Standard SD Mode – Data/Command Receive

SD1

SD2

mmcx_clk

SD5

SD6

SD5

mmcx_cmd

SD6

mmcx_dat[3:0]

030-109

In mmcx, x is equal to 1, 2, or 3.

Figure 6-72. MMC/SD/SDIO – Standard SD Mode – Data/Command Transmit

226

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6.8 Test Interfaces

The emulation and trace interfaces allow tracing activities of the following CPUs:

•

ARM1136JF-STM through an Embedded Trace Macro-cell (ETM11) dedicated to enable real-time

trace of the ARM subsystem operations and a Serial Debug Trace Interface (SDTI)

•

IVA2 DSP through a high-speed real-time data exchange (HS-RTDX) controller

All processors can be emulated via JTAG ports.

6.8.1 Embedded Trace Macro Interface (ETM)

Table 6-149 assumes testing over the recommended operating conditions (see Figure 6-73).

Table 6-149. Embedded Trace Macro Interface Switching Characteristics⁽¹⁾

NO.

PARAMETER

1.15 V

UNIT

MIN

MAX

f

1/t_c(CLK)

Frequency, etk_clk

Cycle time⁽²⁾, etk_clk

166

MHz

ns

ETM0 t_c(CLK)

6

ETM1 t_W(CLK)

ETM2 t_d(CLK-CTL)

ETM3 t_d(CLK-D)

Clock pulse width, etk_clk

2.7

ns

Delay time, etk_clk clock edge to etk_ctl transition

Delay time, etk_clk clock high to etk_d[15:0] transition

–0.5

0.5

ns

(1) The capacitive load is equivalent to 25 pF.

(2) Cycle time is given by considering a jitter of 5%.

ETM0

ETM1

etk_clk

ETM2

etk_ctl

ETM2

ETM3

etk_d[15:0]

030-110

Figure 6-73. Embedded Trace Macro Interface

6.8.2 System Debug Trace Interface (SDTI)

The system debug trace interface (SDTI) module provides real-time software tracing functionality to the

OMAP3525 and OMAP3530 devices.

The trace interface has four trace data pins and a trace clock pin.

This interface is a dual-edge interface: the data are available on rising and falling edges of sdti_clk but can

be also configured in single edge mode where data are available on falling edge of sdti_clk.

Serial interface operates in clock stop regime: serial clock is not free running, when there is no trace data

there is no trace clock.

6.8.2.1 System Debug Trace Interface in Dual-Edge Mode

Table 6-151 assumes testing over the recommended operating conditions and electrical characteristic

conditions (see Figure 6-74).

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Table 6-150. System Debug Trace Interface Timing Conditions – Dual-Edge Mode

TIMING CONDITION PARAMETER

Output Conditions

VALUE

UNIT

C_LOAD

Output load capacitance

25

pF

Table 6-151. System Debug Trace Interface Switching Characteristics – Dual-Edge Mode

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

SD1 t_c(CLK)

SD2 t_w(CLK)

t_dc(CLK)

Cycle time, sdti_clk period

29

ns

Typical pulse duration, sdti_clk high or low

Duty cycle error, sdti_clk

Rise time, sdti_clk

0.5*P⁽¹⁾

–1.2

1.2

5

–1.2

1.2

5

t_R(CLK)

t_F(CLK)

Fall time, sdti_clk

5

SD3 t_d(CLK-TxD)

Delay time, sdti_clk

transition to sdti_txd[3:0]

transition

Multiplexing mode on etk pins

2.3

10.9

13.9

2.3

10.9

13.9

Multiplexing mode on

jtag_emu pins

t_R(CLK)

t_F(CLK)

Rise time, sdti_txd[3:0]

Fall time, sdti_txd[3:0]

5

ns

(1) P = sdti_clk clock period

SD1

SD2

sdti_clk

SD3

sdti_txd[3:0]

Header Header Ad[7:4]

Ad[3:0] Da[15:12] Da[11:8] Da[7:4]

Da[3:0]

030-111

Figure 6-74. System Debug Trace Interface – Dual-Edge Mode

6.8.2.2 System Debug Trace Interface in Single-Edge Mode

Table 6-153 assumes testing over the recommended operating conditions and electrical characteristic

conditions (see Figure 6-75).

Table 6-152. System Debug Trace Interface Timing Conditions – Single-Edge Mode

TIMING CONDITION PARAMETER

Output Conditions

VALUE

UNIT

C_LOAD

Output load capacitance

25

pF

Table 6-153. System Debug Trace Interface Switching Characteristics – Single-Edge Mode

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

SD1 t_c(CLK)

SD2 t_w(CLK)

t_dc(CLK)

Cycle time, sdti_clk period

29

ns

Typical pulse duration, sdti_clk high or low

Duty cycle error, sdti_clk

Rise time, sdti_clk

0.5*P⁽¹⁾

–1.2

1.2

5

–1.2

1.2

5

t_R(CLK)

t_F(CLK)

Fall time, sdti_clk

5

SD3 t_d(CLK-TxD)

Delay time, sdti_clk

transition to sdti_txd[3:0]

transition

Multiplexing mode on etk pins

2.3

26.5

33.2

2.3

26.5

33.2

Multiplexing mode on jtag_emu

pins

t_R(CLK)

Rise time, sdti_txd[3:0]

5

ns

(1) P = sdti_clk clock period.

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Table 6-153. System Debug Trace Interface Switching Characteristics – Single-Edge Mode (continued)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

t_F(CLK)

Fall time, sdti_txd[3:0]

5

ns

SD1

SD2

sdti_clk

SD3

Ad[7:4]

sdti_txd[3:0]

Header

Ad[3:0]

Da[15:12]

Da[11:8]

Da[7:4]

Da[3:0]

030-112

Figure 6-75. System Debug Trace Interface – Single-Edge Mode

6.8.3 JTAG Interfaces

OMAP3525 and OMAP3530 JTAG TAP controllers handle standard IEEE JTAG interfaces. The following

sections define the timing requirements for several tools used to test the OMAP3525 and OMAP3530

processors as:

•

Free running clock tool, like XDS560 and XDS510 tools

Adaptive clock tool, like RealView® ICE tool and Lauterbach™ tool

6.8.3.1 JTAG – Free Running Clock Mode

Table 6-155 and Table 6-156 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-76).

Table 6-154. JTAG Timing Conditions – Free Running Clock Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

t_R

Input signal rise time

Input signal fall time

5

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

30

pF

Table 6-155. JTAG Timing Requirements – Free Running Clock Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

JT4 t_c(tck)

Cycle time⁽²⁾, jtag_tck period

25

33

ns

ps

ns

JT5 t_w(tckL)

JT6 t_w(tckH)

t_dc(tck)

Typical pulse duration, jtag_tck low

Typical pulse duration, jtag_tck high

Duty cycle error, jtag_tck

0.5*P⁽³⁾

–1250

1.8

1250

–1667

1.8

1667

t_j(tck)

Cycle jitter⁽⁴⁾, jtag_tck

JT7 t_{su(tdiV-rtckH)}

JT8 t_{h(tdiV-rtckH)}

JT9 t_{su(tmsV-rtckH)}

JT10 t_{h(tmsV-rtckH)}

JT12 t_{su(emuxV-rtckH)}

Setup time, jtag_tdi valid before jtag_rtck high

Hold time, jtag_tdi valid after jtag_rtck high

Setup time, jtag_tms valid before jtag_rtck high

Hold time, jtag_tms valid after jtag_rtck high

Setup time, jtag_emux⁽⁵⁾valid before jtag_rtck

high

0.7

1

1.8

0.7

1

14.6

19.8

(1) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.

(2) Related with the input maximum frequency supported by the JTAG module.

(3) P = jtag _tck period in ns.

(4) Maximum cycle jitter supported by jtag _tck input clock.

(5) x = 0 to 1

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Table 6-155. JTAG Timing Requirements – Free Running Clock Mode (continued)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

JT13 t_{h(emuxV-rtckH)}

Hold time,jtag_emux⁽⁵⁾valid after jtag_rtck high

2

2.7

ns

Table 6-156. JTAG Switching Characteristics – Free Running Clock Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT＝

MIN

MAX

MIN

MAX

JT1 t_c(rtck)

JT2 t_w(rtckL)

JT3 t_w(rtckH)

t_dc(rtck)

Cycle time⁽¹⁾, jtag_rtck period

Typical pulse duration, jtag_rtck low

Typical pulse duration, jtag_rtck high

Duty cycle error, jtag_rtck

25

33

ns

ps

ns

0.5*PO⁽²⁾

–1250

1250

–1667

1667

t_j(rtck)

Jitter standard deviation⁽³⁾, jtag_rtck

33.3

4

33.3

4

t_R(rtck)

Rise time, jtag_rtck

t_F(rtck)

Fall time, jtag_rtck

4

JT11 t_{d(rtckL-tdoV)}

t_R(tdo)

Delay time, jtag_rtck low to jtag_tdo valid

Rise time, jtag_tdo

–5.8

2.7

5.8

4

–7.9

2.7

7.9

4

t_F(tdo)

Fall time, jtag_tdo

4

JT14 t_{d(rtckH-emuxV)}

t_R(emux)

Delay time, jtag_rtck high to ,jtag_emux⁽⁴⁾valid

Rise time, jtag_emux⁽⁴⁾

Fall time, jtag_emux⁽⁴⁾

15.1

6

20.4

6

t_F(emux)

6

(1) Related with the jtag_rtck maximum frequency.

(2) PO = jtag _rtck period in ns.

(3) The jitter probability density can be approximated by a Gaussian function.

(4) x = 0 to 1

JT4

JT1

JT5

JT6

JT3

jtag_tck

JT2

jtag_rtck

JT7

JT8

jtag_tdi

JT9

JT10

JT13

jtag_tms

JT12

jtag_emux(IN)

JT11

jtag_tdo

JT14

jtag_emux(OUT)

030-113

In jtag_emux, x is equal to 0 to 1.

Figure 6-76. JTAG Interface Timing – Free Running Clock Mode

6.8.3.2 JTAG – Adaptive Clock Mode

Table 6-158 and Table 6-159 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-77):

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Table 6-157. JTAG Timing Conditions – Adaptive Clock Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

t_R

Input signal rise time

Input signal fall time

5

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

30

pF

Table 6-158. JTAG Timing Requirements – Adaptive Clock Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

JA4

JA5

JA6

t_c(tck)

Cycle time⁽²⁾, jtag_tck period

50

ns

ps

ns

t_w(tckL)

Typical pulse duration, jtag_tck low

Typical pulse duration, jtag_tck high

Duty cycle error, jtag_tck

0.5*P⁽³⁾

t_w(tckH)

t_dc(lclk)

–2500

–1500

13.8

2500

1500

–2500

–1500

13.8

2500

1500

t_j(lclk)

Cycle jitter⁽⁴⁾, jtag_tck

JA7

JA8

JA9

t_{su(tdiV-tckH)}

t_h(tdiV-tckH)

t_{su(tmsV-tckH)}

Setup time, jtag_tdi valid before jtag_tck high

Hold time, jtag_tdi valid after jtag_tck high

Setup time, jtag_tms valid before jtag_tck high

Hold time, jtag_tms valid after jtag_tck high

13.8

JA10 t_h(tmsV-tckH)

13.8

(1) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.

(2) Related with the input maximum frequency supported by the JTAG module.

(3) P = jtag _tck period in ns.

(4) Maximum cycle jitter supported by jtag _tck input clock.

Table 6-159. JTAG Switching Characteristics – Adaptive Clock Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

JA1

JA2

JA3

t_c(rtck)

Cycle time⁽¹⁾, jtag_rtck period

Typical pulse duration, jtag_rtck low

Typical pulse duration, jtag_rtck high

Duty cycle error, jtag_rtck

Jitter standard deviation⁽³⁾, jtag_rtck

Rise time, jtag_rtck

50

ns

ps

ns

t_w(rtckL)

t_w(rtckH)

t_dc(rtck)

t_j(rtck)

0.5*PO⁽²⁾

2500

–2500

–14.6

2500

–2500

–14.6

33.3

4

33.3

4

t_R(rtck)

t_F(rtck)

Fall time, jtag_rtck

4

JA11 t_{d(rtckL-tdoV)}

Delay time, jtag_rtck low to jtag_tdo valid

Rise time, jtag_tdo,

14.6

4

14.6

4

t_R(tdo)

t_F(tdo)

Fall time, jtag_tdo

4

(1) Related with the jtag _rtck maximum frequency programmable.

(2) PO = jtag _rtck period in ns.

(3) The jitter probability density can be approximated by a Gaussian function.

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JA4

JA5

JA6

jtag_tck

JA7

JA8

JA10

JA1

jtag_tdi

JA9

jtag_tms

JA2

JA3

jtag_rtck

JA11

jtag_tdo

030-114

Figure 6-77. JTAG Interface Timing – Adaptive Clock Mode

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7 PACKAGE CHARACTERISTICS

7.1 Package Thermal Resistance

Table 7-1 provides the thermal resistance characteristics for the recommended package types used on the

OMAP3525 and OMAP3530 Applications Processors.

Table 7-1. OMAP3525/30 Thermal Resistance Characteristics^{(1) (2)}

Package

Power (W)⁽³⁾

R_θJA(°C/W)

R_θJB(°C/W)

R

_θJC(°C/W)⁽⁴⁾

Board Type

OMAP3525/30

(CBB Pkg.)

0.92871

24.46

10.94

0.01⁽⁵⁾

2S2P⁽⁶⁾

(5)

OMAP3525/30

(CBC Pkg.)

0.92871

21.89

6.23

2S2P⁽⁶⁾

(1) R_θJA(Theta-JA) = Thermal Resistance Junction-to-Ambient, °C/W

(2) This table provides simulation data and may not represent actual use-case values.

R_θJB(Theta-JB) = Thermal Resistance Junction-to-Board, °C/W

R_θJC(Theta-JC) = Thermal Resistance Junction-to-Case, °C/W

(3) These numbers are based on simulation results and don’t necessarily represent the wattage that the part will take in actual use.

(4) It is recommended to dissipate the heat to the board instead of attempting to remove it from the top of the chip; therefore, top-side heat

sinks should not be used for package.

(5) Not applicable if the POP package has a memory package on top; no heat sink can be used.

(6) The board types are defined by JEDEC (reference JEDEC standard JESD51-9, Test Board for Area Array Surface Mount Package

Thermal Measurements).

7.2 Device Support

7.2.1 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

OMAP processors and support tools. Each OMAP device has one of three prefixes: X, P, or null (no

prefix). Texas Instruments recommends two of three possible prefix designators for its support tools:

TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering

prototypes (TMDX) through fully qualified production devices/tools (TMDS).

Device development evolutionary flow:

X

Experimental device that is not necessarily representative of the final device’s electrical

specifications and may not use production assembly flow. (TMX definition)

P

Prototype device that is not necessarily the final silicon die and may not necessarily meet

final electrical specifications. (TMP definition)

null

Production version of the silicon die that is fully qualified. (TMS definition)

Support tool development evolutionary flow:

TMDX

TMDS

Development support product that has not yet completed Texas Instruments internal

qualification testing.

Fully qualified development support product.

TMX and TMP devices and TMDX development-support tools are shipped against the following

disclaimer:

“Developmental product is intended for internal evaluation purposes.”

Production devices and TMDS development-support tools have been characterized fully, and the quality

and reliability of the device have been demonstrated fully. TI’s standard warranty applies.

Predictions show that prototype devices (X or P), have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system

because their expected end-use failure rate still is undefined. Only qualified production devices are to be

used.

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For additional description of the device nomenclature markings, see the OMAP35x Applications Processor

Silicon Errata (literature number SPRZ278).

X

OMAP3530

D

CBB

( ) ( )( )

Z

60 = 600 MHz Cortex - A8

PREFIX

X = Experimental Device

P = Prototype Device

blank= Production Device

blank = Tray

R

= Tape and Reel

blank = -40° C to 90° C

= -40° C to 105° C (preview)

A

DEVICE

PACKAGE TYPE

SILICON REVISION

TI HIREL RELEASE

CBB = 515 pin s-PBGA

CBC = 515 pin s-PBGA

CUS = 423 pin s-PBGA

A. For more information on the silicon revision, please see the OMAP3530/25/15/03 Applications Processor Silicon

Errata (literature number SPRZ278).

Figure 7-1. Device Nomenclature^(A)

7.2.2 Documentation Support

7.2.2.1 Related Documentation from Texas Instruments

The following documents describe the OMAP3525 and OMAP3530 Applications Processors. Copies of

these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the

search box provided at www.ti.com.

The current documentation that describes the OMAP3525 and OMAP3530 Applications Processors,

related peripherals, and other technical collateral, is available in the product folder at: www.ti.com.

SPRUF98 OMAP35x Technical Reference Manual. Collection of documents providing detailed

information on the OMAP3 architecture including power, reset, and clock control, interrupts,

memory map, and switch fabric interconnect. Detailed information on the microprocessor unit

(MPU) subsystem, the image, video, and audio (IVA2.2) subsystem, as well a functional

description of the peripherals supported on OMAP35x devices is also included.

SPRU732

TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide.Describes the CPU

architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+

digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP

generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an

enhancement of the C64x DSP with added functionality and an expanded instruction set.

SPRU871

SPRU889

TMS320C64x+ DSP Megamodule Reference Guide.Describes the TMS320C64x+ digital

signal processor (DSP) megamodule. Included is a discussion on the internal direct memory

access (IDMA) controller, the interrupt controller, the power-down controller, memory

protection, bandwidth management, and the memory and cache.

High-Speed DSP Systems Design Reference Guide. Provides recommendations for

meeting the many challenges of high-speed DSP system design. These recommendations

include information about DSP audio, video, and communications systems for the C5000 and

C6000 DSP platforms.

7.2.2.2 Related Documentation from Other Sources

The following documents are related to the OMAP3525 and OMAP3530 Applications Processors. Copies

of these documents can be obtained directly from the internet or from your Texas Instruments

representative.

234

PACKAGE CHARACTERISTICS

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Cortex™-A8 Technical Reference Manual. This is the technical reference manual for the Cortex-A8

processor. A copy of this document can be obtained via the internet at http://infocenter.arm.com. Please

see the OMAP35x Applications Processor Silicon Errata (literature number SPRZ278) to determine the

revision of the Cortex-A8 core used on your device.

ARM Core CortexTM-A8 (AT400/AT401) Errata Notice. Provides a list of advisories for the different

revisions of the Cortex-A8 processor. Contact your TI representative for a copy of this document. Please

see the OMAP35x Applications Processor Silicon Errata (literature number SPRZ278) to determine the

revision of the Cortex-A8 core used on your device.

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PACKAGE OPTION ADDENDUM

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18-Jun-2009

PACKAGING INFORMATION

Orderable Device

OMAP3525DZCBC

OMAP3530DZCBB

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

POP-

CBC

515

Pb-Free

(RoHS)

Call TI

Level-3-260C-168 HR

FCBGA

POP-

CBB

515

119 Green (RoHS &

no Sb/Br)

SNAGCU

Level-3-260C-168 HR

FCBGA

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

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TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably

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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Amplifiers

Applications

Audio

Automotive

Broadband

Digital Control

Medical

Military

Optical Networking

Security

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

www.ti.com/audio

Data Converters

DLP® Products

DSP

Clocks and Timers

Interface

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/medical

www.ti.com/military

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

dsp.ti.com

www.ti.com/clocks

interface.ti.com

logic.ti.com

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Logic

Power Mgmt

Microcontrollers

RFID

Telephony

Video & Imaging

Wireless

RF/IF and ZigBee® Solutions www.ti.com/lprf

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	OMAP3530ECBB
厂家：	TEXAS INSTRUMENTS
描述：	应用处理器 \| CBB \| 515 \| 0 to 90 外围集成电路
文件：	总239页 (文件大小：3505K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

OMAP3530ECBB [TI]

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