ONET1130ECRSMT [TI]
具有双 CDR 和集成式调制器驱动器的 11.7Gbps 收发器 | RSM | 32 | -40 to 100;
| 型号： | ONET1130ECRSMT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有双 CDR 和集成式调制器驱动器的 11.7Gbps 收发器 | RSM | 32 | -40 to 100 ATM 异步传输模式 驱动 CD 电信 电信集成电路 驱动器 |
| 文件： | 总64页 (文件大小：3255K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ONET1130EC
ZHCSDW5A –JUNE 2015–REVISED JULY 2015
ONET1130EC 具有双 CDR 和调制器驱动器的 11.7Gbps 收发器
1 特性
发送路径包含 1 个可调节输入均衡器（用于均衡长达
300mm
1
•
双时钟和数据恢复 (CDR) 功能，支持 9.80-
11.7Gbps 无参考运行
（12 英寸）的 FR4 印刷电路板的微带传输线或带状传
输线）、1 个多速率 CDR 和 1 个输出调制器驱动器。
该器件以交叉点调节和去加重的形式提供输出波形控
制，从而增加光学眼图波罩余量。 该器件提供激光二
极管偏置电流，并且包含集成自动功率控制 (APC) 回
路，用于对平均光学功率随电压、温度和时间的变化进
行补偿。
•
两线制数字接口搭配集成的数模转换器 (DAC) 和模
数转换器 (ADC) 进行控制和诊断管理
•
•
•
•
•
TX 和 RX 输出极性选择
可编程的抖动传输带宽
电气和光学环回
CDR 旁路模式，支持以低数据速率运行
集成调制器驱动器，输出幅值最高可达 2 VPP（单
端），偏置电流最高可达 150mA（拉电流）。
接收路径包含 1 个具有可编程均衡和阈值调节功能的
限幅放大器、1 个多速率 CDR 和输出去加重功能（用
于对器件输出端所连接的连接器、微带传输线或带状传
输线上与频率相关的损耗进行补偿）。接收器输出幅值
和信号损失有效电平都是可以调节的。
•
具有可选监视器光电二极管 (PD) 范围的自动功率
控制 (APC) 回路
•
•
•
•
•
•
•
•
•
•
可编程的 TX 输入均衡器
TX 交叉点调节和去加重功能
包括激光安全特性
器件信息
具有可编程信号损耗 (LOS) 阈值的集成限幅放大器
可调节的 RX 均衡和输入阈值
可编程的 RX 输出电压和去加重功能
电源监视器和温度传感器
订货编号
封装（引脚）
封装尺寸
ONET1130EC
VQFN (32)
4.00mm x 4.00mm
简化电路原理图
VCC_T
VCC
2.5V 单电源
工作温度范围：-40°C 至 100°C
4.7kꢁ
4.7kꢁ
4.7kꢁ
to10kꢁ
to10kꢁ
to10kꢁ
表面贴装 4mm x 4mm 32 引脚四方扁平无引线
(QFN) 封装（间距为 0.4mm）
0.1ꢀF
0.1ꢀF
RXOUT-
RXOUT+
2.2nF
VCC_R
TX_FLT
TX_DIS
2 应用
0.1ꢀF
0.1ꢀF
VCC_RX
•
XFP 和 SFP+ 10Gbps SONET OC-192 光学收发
器
4.7kꢁ
to10kꢁ
LOL
RX_LOS
LOS
LOL
0.01ꢀF
•
XFP 和 SFP+ 10 GBASE-ER/ZR 光学收发器
MONB
GND
TXIN+
TXIN-
GND
PD
COMP
GND
MONB
0.1ꢀF
0.1ꢀF
0.1ꢀF
RXIN-
RXIN+
GND
SCK
3 说明
RXIN-
RXIN+
TXIN+
TXIN-
ONET1130EC
ONET1130EC 是一款具有收发时钟和数据恢复 (CDR)
功能的 2.5V 集成调制器驱动器和限幅放大器，无需参
考时钟即可以 9.80Gbps 至 11.7Gbps 范围内的速率运
行。 该器件包含光学和电气环回。 在 CDR 旁路模式
下，器件可以较低的数据速率运行。器件可利用两线制
串行接口进行数字控制。
0.1ꢀF
PD
SCK
SDA
MONP
SDA
MONP
4.7kꢁ
to10kꢁ
4.7kꢁ
to10kꢁ
VCC
VDD
VCC_TX
0.1ꢀF
Modulator Anode
0.1ꢀF
2.2nF
0.1ꢀF
0.1ꢀF
50ꢁ
Laser
PD
PD
EA BIAS
EML TOSA
0.1ꢀF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEJ3
ONET1130EC
ZHCSDW5A –JUNE 2015–REVISED JULY 2015
www.ti.com.cn
目录
8.2 Functional Block Diagram ....................................... 20
8.3 Feature Description................................................. 21
8.4 Device Functional Modes........................................ 31
8.5 Programming .......................................................... 31
8.6 Register Mapping.................................................... 32
Application Information and Implementations . 49
9.1 Application Information............................................ 49
9.2 Typical Application, Transmitter Differential Mode.. 49
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明（续）............................................................... 3
Pin Configuration and Function........................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ..................................... 5
7.2 ESD Ratings ............................................................ 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 6
7.5 DC Electrical Characteristics .................................... 6
7.6 Transmitter AC Electrical Characteristics ................. 8
7.7 Receiver AC Electrical Characteristics ..................... 9
7.8 Timing Requirements.............................................. 10
7.9 Typical Characteristics............................................ 13
Detailed Description ............................................ 19
8.1 Overview ................................................................. 19
9
10 Power Supply Recommendations ..................... 53
11 Layout................................................................... 54
11.1 Layout Guidelines ................................................. 54
11.2 Layout Example .................................................... 54
12 器件和文档支持 ..................................................... 55
12.1 社区资源................................................................ 55
12.2 商标....................................................................... 55
12.3 静电放电警告......................................................... 55
12.4 Glossary................................................................ 55
13 机械、封装和可订购信息....................................... 55
8
4 修订历史记录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 2015) to Revision A
Page
•
已从“产品预览”更改为“量产数据” ............................................................................................................................................ 1
2
版权 © 2015, Texas Instruments Incorporated
ONET1130EC
www.ti.com.cn
ZHCSDW5A –JUNE 2015–REVISED JULY 2015
5 说明（续）
ONET1130EC 内置模数转换器和数模转换器，可对收发器进行管理并且消除了对专用微控制器的需求。
收发器的额定工作温度范围为 –40°C 至 100°C（外壳温度），并且采用符合 RoHS 标准的小型 4mm × 4mm 32 引
脚超薄型四方扁平无引线 (VQFN) 封装。
6 Pin Configuration and Function
RSM PACKAGE
32 PIN VQFN
(TOP VIEW)
32 31 30 29 28 27 26
25
LOL
MONB
GND
1
2
3
4
5
6
7
8
24 RX_LOS
23 COMP
22 GND
21 RXINœ
20 RXIN+
19 GND
18 SCK
TXIN+
TXINœ
GND
PD
EP
MONP
17 SDA
11
13
10
12
14 15
9
16
Pin Functions
NUMBER
AMP
NAME
Type
DESCRIPTION
Output amplitude control. Output amplitude can be adjusted by applying a voltage of
0 to 2 V to this pin. Leave open when not used.
16
10
Analog-in
Analog
Analog
Supply
BIAS
COMP
GND
Sinks or sources the bias current for the laser in both APC and open loop modes.
Compensation pin used to control the bandwidth of the APC loop. Connect a 0.01-µF
capacitor to ground.
23
3, 6, 19, 22
Circuit ground.
Transmitter and receiver loss of lock indicator. High level indicates the transmitter or
the receiver is out of lock. Open drain output. Requires an external 4.7 kΩ to 10 kΩ
pull-up resistor to VCC for proper operation. This pin is 3.3 V tolerant.
LOL
1
Digital-out
MONB
MONP
PD
2
8
7
Analog-out
Analog-out
Analog
Bias current monitor.
Photodiode current monitor.
Photodiode input. Pin can source or sink current dependent on register setting.
Disables the receiver output buffer when set to a high level. Includes a 250-kΩ pull-
up resistor to VCC. Ground the pin to enable the output. This is an ORed function
with the RXOUT_DIS bit (bit 6 in register 4). This pin is 3.3-V tolerant.
RX_DIS
RX_LF
26
25
24
Digital-in
Analog-in
Digital-out
Receiver loop filter capacitor.
Receiver loss of signal. High level indicates that the receiver input signal amplitude is
below the programmed threshold level. Open drain output. Requires an external 4.7-
kΩ to 10-kΩ pull-up resistor to VCC for proper operation. This pin is 3.3-V tolerant.
RX_LOS
Non-inverted receiver data input. On-chip differentially 100 Ω terminated to RXIN–.
Must be AC coupled.
RXIN+
RXIN-
20
21
Analog-in
Analog-in
Inverted receiver data input. On-chip differentially 100 Ω terminated to RXIN+. Must
be AC coupled.
RXOUT–
RXOUT+
28
29
CML-out
CML-out
Inverted receiver data output. 45 Ω back-terminated to VCC.
Non-inverted data output. 45 Ω back-terminated to VCC.
Copyright © 2015, Texas Instruments Incorporated
3
ONET1130EC
ZHCSDW5A –JUNE 2015–REVISED JULY 2015
www.ti.com.cn
Pin Functions (continued)
NUMBER
SDA
NAME
Type
DESCRIPTION
2-wire interface serial data input. Requires an external 4.7-kΩ to10-kΩ pull-up resistor
17
Digital-in/out
to VCC. This pin is 3.3-V tolerant.
2-wire interface serial clock input. Requires an external 4.7-kΩ to10-kΩ pull-up
resistor to VCC. This pin is 3.3-V tolerant.
SCK
18
32
4
Digital-in
Digital-in
Analog-in
Disables both bias and modulation currents when set to high state. Includes a 250-kΩ
pull-up resistor to VCC. Requires an external 4.7 kΩ to 10 kΩ pull-up resistor to VCC
for proper operation Toggle to reset a fault condition. This is an ORed function with
the TXBIASEN bit (bit 2 in register 1). This pin is 3.3-V tolerant.
TX_DIS
TXIN+
Non-inverted transmitter data input. On-chip differentially 100 Ω terminated to TXIN–.
Must be AC coupled.
Inverted transmitter data input. On-chip differentially 100 Ω terminated to TXIN+. Must
be AC coupled.
TXIN–
TX_LF
5
9
Analog-in
Analog-in
Transmitter loop filter capacitor.
Transmitter fault detection flag. High level indicates that a fault has occurred. Open
drain output. Requires an external 4.7 kΩ to 10 kΩ pull-up resistor to VCC for proper
operation. This pin is 3.3-V tolerant.
TX_FLT
31
Digital-out
Inverted transmitter data output. Internally terminated in single-ended operation
mode.
TXOUT–
12
CML-out
TXOUT+
VCC_RX
VCC_TX
VDD
13
27, 30
11, 14
15
CML-out
Supply
Supply
Supply
Non-Inverted transmitter data output.
2.5 V ± 5% supply for the receiver.
2.5 V ± 5% supply for the transmitter.
2.5 V ± 5% supply for the digital circuitry.
Exposed die pad. Solder to the PCB.
Exposed Pad
EP
4
Copyright © 2015, Texas Instruments Incorporated
ONET1130EC
www.ti.com.cn
ZHCSDW5A –JUNE 2015–REVISED JULY 2015
7 Specifications
7.1 Absolute Maximum Ratings
(1)(2)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
Supply voltage
Voltage
at VCC_TX, VCC_RX, VDD
–0.5
3
at 3.3-V tolerant pins LOL, SDA, SCK, RX_LOS, RX_DIS,
TX_FLT, TX_DIS
V
–0.5
3.6
at all other pins MONB, TXIN+, TXIN–, PD, MONP, TX_LF,
BIAS, TXOUT–, TXOUT+, AMP, RXIN+, RXIN–, COMP,
RX_LF, RXOUT–, RXOUT+,
–0.5
3
V
Maximum current at transmitter input pins TXIN+, TXIN–
Maximum current at transmitter output
pins
10
mA
mA
TXOUT+, TXOUT–
125
Maximum current at receiver input pins
RXIN+, RXIN–
10
30
mA
mA
°C
Maximum current at receiver output pins RXOUT+, RXOUT–
Maximum junction temperature, TJ
125
150
Storage temperature, Tstg
–65
°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.37
2
TYP
MAX
UNIT
VCC
VIH
VIL
Supply Voltage
2.5
2.63
V
V
V
Digital input high voltage
Digital input low voltage
TX_DIS, RX_DIS, SCK, SDA, 3.3-V tolerant IOs
0.8
Control bit TXPDRNG = 1x, step size = 3 µA
Control bit TXPDRNG = 01, step size = 1.5 µA
Control bit TXPDRNG = 00, step size = 0.75 µA
TXCDR_DIS = 0 and RXCDR_DIS = 0
3080
1540
770
Photodiode current range
µA
9.8
1
11.7
11.7
2
Serial Data rate
Gbps
TXCDR_DIS = 1 and RXCDR_DIS = 1
VAMP
tR-IN
tF-IN
TC
Amplitude control input voltage range
0
V
Input rise time
20%–80%
20%–80%
30
30
45
ps
ps
°C
Input fall time
45
Temperature at thermal pad
–40
100
Copyright © 2015, Texas Instruments Incorporated
5
ONET1130EC
ZHCSDW5A –JUNE 2015–REVISED JULY 2015
www.ti.com.cn
UNIT
7.4 Thermal Information
RSM (VQFN)
32 PINS
37.2
THERMAL METRIC(1)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
30.1
7.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ψJB
7.6
RθJCbot
2.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 DC Electrical Characteristics
Over recommended operating conditions, open loop operation, VOUT = 2 VPP single-ended, I(BIAS) = 80 mA, unless otherwise
noted. Typical operating condition is at VCC = 2.5 V and TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC
Supply voltage
2.37
2.5
2.63
V
Supply current in single-ended TX
mode with CDRs enabled
225
563
270
675
161
403
206
266
699
310
815
185
487
242
636
mA
mW
mA
mW
mA
mW
mA
TXMODE = 1, TXCDR_DIS = 0, TX VOUT = 2 VPP single-
ended, I(BIAS) = 0 mA; RXCDR_DIS = 0, 600 mVPP
differential RX output
Power dissipation in single-ended TX
mode with CDRs enabled
Supply current in differential TX
mode with CDRs enabled
TXMODE = 0, TXCDR_DIS = 0, TX VOUT = 1.8 VPP
single-ended, I(BIAS) = 0 mA; RXCDR_DIS = 0, 600 mVPP
differential RX output
Power dissipation in differential TX
mode with CDRs enabled
IVCC
Supply current in single-ended TX
mode with CDRs disabled
TXMODE = 1, TXCDR_DIS = 1, TX VOUT = 2 VPP single-
ended, I(BIAS) = 0 mA; RXCDR_DIS = 1, 600 mVPP
differential RX output
Power dissipation in single-ended TX
mode with CDRs disabled
Supply current in differential TX
mode with CDRs disabled
TXMODE = 0, TXCDR_DIS = 1, TX VOUT = 1.8 VPP
single-ended, I(BIAS) = 0 mA; RXCDR_DIS = 1, 600 mVPP
differential RX output
Power dissipation in differential TX
mode with CDRs disabled
515
100
mW
R(TXIN)
Transmitter data input resistance
Differential between TXIN+ / TXIN–
Ω
Transmitter data input termination
mismatch
5%
R(RXIN)
R(OUT)
Receiver data input resistance
Transmitter output resistance
Receiver data output resistance
Differential between RXIN+ / RXIN–
Single-ended at TXOUT+ or TXOUT–
Differential between RXOUT+ or RXOUT–
100
60
Ω
Ω
Ω
R(RXOUT)
90
Receiver data output termination
mismatch
5%
20
Digital input current
TX_DIS, RX_DIS pull up to VCC
–20
2.1
µA
V
LOL, TX_FLT, RX_LOS, pull-up to VCC
ISOURCE = 37.5 μA
,
VOH
Digital output high voltage
LOL, TX_FLT, RX_LOS, pull-up to VCC
ISINK = 350 μA
,
VOL
Digital output low voltage
Minimum bias current
0.4
5
V
(1)
I(BIAS-MIN)
See
mA
Source. BIASPOL = 0, DAC set to maximum, open and
closed loop
145
95
150
100
I(BIAS-MAX)
Maximum bias current
mA
Sink. BIASPOL = 1, DAC set to maximum, open and
closed loop
I(BIAS-DIS)
Bias current during disable
Average power stability
100
µA
dB
V
APC loop enabled
±0.5
Source. TXBIASPOL = 0
Sink. TXBIASPOL = 1
VCC-0.45
Bias pin compliance voltage
Temperature sensor accuracy
0.45
With 1-point external mid-scale calibration
±3
°C
(1) The bias current can be set below the specified minimum according to the corresponding register setting; however, in closed loop
operation settings below the specified value may trigger a fault.
6
Copyright © 2015, Texas Instruments Incorporated
ONET1130EC
www.ti.com.cn
ZHCSDW5A –JUNE 2015–REVISED JULY 2015
DC Electrical Characteristics (continued)
Over recommended operating conditions, open loop operation, VOUT = 2 VPP single-ended, I(BIAS) = 80 mA, unless otherwise
noted. Typical operating condition is at VCC = 2.5 V and TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Photodiode reverse bias voltage
Photodiode fault current level
APC active, I(PD) = 1500 μA
1.3
2.3
V
(2)
Percent of target I(PD)
150%
12.5%
25%
V(PD)
I(MONP) / I(PD) with control bit PDRNG = 1X
I(MONP) / I(PD) with control bit PDRNG = 01
I(MONP) / I(PD) with control bit TXPDRNG = 00
With external mid-scale calibration
10%
20%
40%
15%
30%
60%
Photodiode current monitor ratio
50%
Monitor diode DMI accuracy
Bias current monitor ratio
Bias current DMI accuracy
Power supply monitor accuracy
VCC reset threshold voltage
±10%
1%
I(MONB) / I(BIAS) (nominal 1/100 = 1%), V(MONB) < 1.5V
0.9%
–15%
–2%
1.1%
15%
2%
I(BIAS) ≥ 20 mA
With external mid-scale calibration
V(CC-RST)
VCC voltage level which triggers power-on reset
1.8
2.1
V
V(CC-
VCC reset threshold voltage
hysteresis
100
mV
RSTHYS)
TXFLTEN = 1, TXDMONB = 0, Fault occurs if voltage at
MONB exceeds this value
V(MONB-FLT) Fault voltage at MONB
V(MONP-FLT) Fault voltage at MONP
1.15
1.15
1.2
1.2
1.25
1.25
V
V
TXFLTEN = 1, TXMONPFLT = 1, TXDMONP = 0, Fault
occurs if voltage at MONP exceeds this value
(2) Assured by design over process, supply and temperature variation
Copyright © 2015, Texas Instruments Incorporated
7
ONET1130EC
ZHCSDW5A –JUNE 2015–REVISED JULY 2015
www.ti.com.cn
7.6 Transmitter AC Electrical Characteristics
Over recommended operating conditions, open loop operation, VOUT = 2 VPP single-ended, I(BIAS) = 80 mA unless otherwise
noted. Typical operating condition is at VCC = 2.5 V and TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Gbps
dB
TX INPUT SPECIFICATIONS
CDR lock range
CPRI, Ethernet, SONET, Fibre Channel
0.05 GHz < f ≤ 0.1 GHz
0.1 GHz < f ≤ 5.5 GHz
9.80
20
12
8
11.7
Differential input return loss
15
15
5.5 GHz < f < 12 GHz
Differential to common mode conversion
Common mode input return loss
Input AC common mode voltage tolerance
Total Non-DDJ
0.1 GHz < f < 12 GHz
10
3
dB
dB
0.1 GHz < f < 12 GHz
15
mV
Total jitter less ISI
0.45
0.65
UIPP
UIPP
UIPP
mVPP
dB
T(J_TX)
S(J_TX)
VIN
Total Jitter
Sinusoidal Jitter Tolerance
Differential input voltage swing
EQ high freq boost
With addition of input jitter, See 图 1
Maximum setting; 7 GHz
100
6
1000
EQ(boost)
9
TX OUTPUT SPECIFICATIONS
Differential output return loss
Minimum output amplitude
0.01 GHz < f < 12 GHz
12
dB
VO(MIN)
AC Coupled Outputs, 50-Ω single-ended load
0.5
VPP
TX OUTPUT SPECIFICATIONS in SINGLE-ENDED MODE of OPERATION (TXMODE = 1)
VO(MAX)
Maximum output amplitude
Output amplitude stability
High Cross Point Control Range
Low Cross Point Control Range
Cross Point Stability
AC Coupled Outputs, 50-Ω load, single-ended
AC Coupled Outputs, 50-Ω load, single-ended
50-Ω load, single-ended
2
70%
-5
VPP
230
75%
35%
mVPP
50-Ω load, single-ended
40%
5
50-Ω load, single-ended
pp
dB
TXDEADJ[0..3] = 1111, TXPKSEL = 0
TXDEADJ[0..3] = 1111, TXPKSEL = 1
5
6
Output de-emphasis
TX OUTPUT SPECIFICATIONS in DIFFERENTIAL MODE of OPERATION (TXMODE = 0)
VO(MAX)
Maximum output amplitude
Output amplitude stability
High Cross Point Control Range
Low Cross Point Control Range
Cross Point Stability
AC Coupled Outputs, 100-Ω differential load
AC Coupled Outputs, 100-Ω differential load
100-Ω differential load
3.6
65%
–5
VPP
230
75%
35%
mVPP
100-Ω differential load
40%
5
100-Ω differential load
pp
dB
TXDEADJ[0..3] = 1111, TXPKSEL = 0
TXDEADJ[0..3] = 1111, TXPKSEL = 1
5
6
Output de-emphasis
TX CDR SPECIFICATIONS
BW(TX)
J(P_TX)
Jitter Transfer Bandwidth
9.95 Gbps, PRBS31
8
1
MHz
dB
Jitter Peaking
> 120 kHz
JGEN(rms)
JGEN(PP)
Random RMS jitter generation
Total jitter generation
Clock pattern, 50 kHz to 80 MHz
Clock pattern, 50 kHz to 80 MHz, BER = 10-12
6
mUIrms
mUIPP
60
8
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ONET1130EC
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ZHCSDW5A –JUNE 2015–REVISED JULY 2015
7.7 Receiver AC Electrical Characteristics
Over recommended operating conditions, outputs connected to a 50-Ω load, VOD = 600 mVpp differential unless otherwise
noted. Typical operating condition is at VCC = 2.5 V and TA = 25°C
PARAMETER
RX INPUT SPECIFICATIONS
CDR lock range
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CPRI, Ethernet, SONET, Fibre Channel
0.01 GHz < f ≤ 5 GHz
9.8
11.7
Gbps
dB
15
8
Differential input return loss
5 GHz < f < 12 GHz
Differential to common mode
conversion
0.1 GHz < f < 12 GHz
15
6
dB
TXOUT_DIS = 1, PRBS31 pattern at 11.7Gbps,
BER < 10-12
VI(RX,MIN)
VI(RX,MAX)
Data input sensitivity
Data input overload
9
mVPP
mVPP
800
1.5
0.4
0.4
9.95 Gbps, BER = 10-12, f = 400kHz
9.95 Gbps, BER = 10-12, f = 4MHz
9.95 Gbps, BER = 10-12, f = 80MHz
J(T_RX)
Sinusoidal jitter tolerance
UIPP
RX OUTPUT SPECIFICATIONS
0.05 GHz < f ≤ 0.1 GHz
0.1 GHz < f < 5.5 GHz
20
8
Differential output return loss
15
20
dB
5.5 GHz < f < 12 GHz
8
Common mode input return loss
0.1 GHz < f < 12 GHz
3
dB
mVrms
kHz
CMOV(RX) Output AC common mode voltage
PRBS31 pattern, RXAMP[0..3] = 0001
7
50
f3dB-L
Low frequency –3dB bandwidth
Deterministic output jitter
Total output jitter
D(J_RX)
T(J_RX)
0.1
0.2
UIPP
UIPP
mVPP
mVPP
mVrms
dB
VIN > 25 mVPP, RX_DIS = 0, RXAMP[0..3] = 0000
VIN > 25 mVPP, RX_DIS = 0, RXAMP[0..3] = 1111
RX_DIS = 1
300
900
VOD
Differential data output voltage
5
Output De-emphasis
RXDADJ[0..1] = 11
1
RX LOS SPECIFICATIONS
LOW LOS assert threshold range
PRBS7 pattern at 11.3Gbps, RXLOSRNG = 1
PRBS7 pattern at 11.3Gbps, RXLOSRNG = 1
PRBS7 pattern at 11.3Gbps, RXLOSRNG = 0
PRBS7 pattern at 11.3Gbps, RXLOSRNG = 0
10
50
min
VTH
mVPP
LOW LOS assert threshold range
max
HIGH LOS assert threshold range
min
40
VTH
mVPP
HIGH LOS assert threshold range
max
130
LOS hysteresis (electrical)
2
4
1.5
1
6
dB
dB
Versus temperature
Versus supply voltage
Versus data rate
LOS threshold variation
1.5
RX CDR SPECIFICATIONS
BW(RX)
J(P_TX)
Jitter Transfer Bandwidth
Jitter Peaking
9.95 Gbps, PRBS31
> 50 kHz
8
1
MHz
dB
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7.8 Timing Requirements
Over recommended operating conditions, open loop operation, TXOUT+ = 2 VPP singled-ended, I(BIAS) = 80 mA, VOD = 600
mVPP differential (unless otherwise noted). Typical operating condition is at VCC = 2.5 V and TA = 25°C
MIN
TYP
MAX
UNIT
CAPC 0.01 µF, IPD = 500 µA, PD coupling ratio CR = 150,
PDRNG = 01
t(APC)
APC time constant
50
µs
t(INIT1)
t(INIT2)
t(OFF)
Power-on to initialize
Initialize to transmit
Transmitter disable time
Disable negate time
TX_DIS pulse width
Fault assert time
Power-on to registers ready to be loaded
0.2
1
2
5
1
ms
ms
µs
Register load STOP command to part ready to transmit valid data
Rising edge of TX_DIS to I(BIAS) ≤ 0.1 × I(BIAS-NOMINAL)
Falling edge of TX_DIS to I(BIAS) ≥ 0.9 × I(BIAS-NOMINAL)
Time TX_DIS must held high to reset part
1
t(ON)
ms
ns
t(RESET)
t(FAULT)
100
Time from fault condition to FLT high
50
µs
TX OUTPUT SPECIFICATIONS in SINGLE-ENDED MODE of OPERATION (TXMODE = 1)
tR(OUTTX)
tF(OUTTX)
Output rise time
Output fall time
20% - 80%, AC Coupled Outputs, 50-Ω load, single-ended
20% - 80%, AC Coupled Outputs, 50-Ω load, single-ended
30
30
42
42
ps
ps
TXEQ_DIS = 1, 11.3 Gbps, PRBS9 pattern, 150-mVpp,
600-mVpp, 1200-mVpp differential input voltage
4
7
12
ISI(TX)
Intersymbol interference
ps
TXEQ_DIS = 0, 11.3 Gbps, PRBS9 pattern, 150-mVpp,
600-mVpp, 1200-mVpp differential input voltage, maximum
equalization with 18-inch transmission line at the input.
Serial data output random
jitter
R(J_TX)
0.4
0.7.5
psRMS
ps
TXPKSEL = 0
TXPKSEL = 1
28
35
Output de-emphasis width
TX OUTPUT SPECIFICATIONS in DIFFERENTIAL MODE of OPERATION (TXMODE = 0)
tR(OUTTX)
tF(OUTTX)
Output rise time
Output fall time
20%–80%, AC Coupled Outputs, 100-Ω differential load
20%–80%, AC Coupled Outputs, 100-Ω differential load
30
30
42
42
ps
ps
TXEQ_DIS = 1, 11.3 Gbps, PRBS9 pattern, 150-mVpp,
600-mVpp, 1200-mVpp differential input voltage
4
7
10
ISI(TX)
Intersymbol interference
ps
TXEQ_DIS = 0, 11.3 Gbps, PRBS9 pattern, 150-mVpp,
600-mVpp, 1200-mVpp differential input voltage, maximum
equalization with 18-inch transmission line at the input.
Serial data output random
jitter
R(J_TX)
0.4
0.75
psRMS
ps
TXPKSEL = 0
TXPKSEL = 1
28
35
Output Peaking Width
TX CDR SPECIFICATIONS
t(Lock,TX) CDR Acquisition time
LOL assert time
RX OUTPUT SPECIFICATIONS
2
ms
500
μs
tR(OUTRX)
tF(OUTRX)
Output rise time
Output fall time
20%–80%, 100-Ω differential load, adjustable
20%–80%, 100-Ω differential load, adjustable
30
30
40
40
ps
ps
Serial data output
deterministic jitter
PRBS9 pattern 11.3 Gbps, VIN = 15 mVpp to 900 mVpp
3
10
ps
RX LOS SPECIFICATIONS
t(LOS_AST)
t(LOS, DEA)
LOS assert time
2.5
2.5
10
10
50
50
μs
μs
LOS deassert time
RX CDR SPECIFICATIONS
t(Lock,RX) CDR Acquisition time
LOL assert time
2
ms
500
μs
10
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ZHCSDW5A –JUNE 2015–REVISED JULY 2015
图 1. Transmitter Input Sinusoidal Jitter Tolerance (INF-8077i Rev. 4.5 XFP MSA)
SDA
tBUFœ
tLOW
tf
tHDSTA
tr
tHIGH
SCK
P
S
S
P
tHDDAT
tSUDAT
tHDSTA
tSUSTA
tSUSTO
图 2. 2-Wire Interface Diagram
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表 1. Timing Diagram Definitions
Symbol
Description
Min
Max
Unit
kHz
µs
fSCK
tBUF
SCK clock frequency
400
Bus free time between START and STOP conditions
1.3
0.6
Hold time after repeated START condition. After this period, the first clock pulse is
generated
tHDSTA
µs
tLOW
tHIGH
tSUSTA
tHDDAT
tSUDAT
tR
Low period of the SCK clock
High period of the SCK clock
Setup time for a repeated START condition
Data HOLD time
1.3
0.6
0.6
0
µs
µs
µs
µs
ns
ns
ns
µs
Data setup time
100
Rise time of both SDA and SCK signals
Fall time of both SDA and SCK signals
Setup time for STOP condition
300
300
tF
tSUSTO
0.6
12
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7.9 Typical Characteristics
Typical operating condition is at VCC = 2.5 V, TA = 25°C, TXOUT+ = 2 VPP Single-ended, RXOUT = 600 mVPP differential,
TXIN = 600 mVPP differential, TX and RX CDRs enabled (unless otherwise noted).
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
0
20
40
60
80 100 120 140 160 180 200
0
20
40
60
80 100 120 140 160 180 200
TXMOD Register 12 Setting (Decimal)
TXMOD Register 12 Setting (Decimal)
D010
D011
TXMODE = 0
TXMODE = 1
Figure 3. TX Deterministic Jitter vs Modulation Current
Figure 4. TX Deterministic Jitter vs Modulation Current
8
8
6
4
2
0
6
4
2
0
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Free-Air Temperature (°C)
Free-Air Temperature (°C)
D012
D013
TXMODE = 0
TXMODE = 1
Figure 5. TX Deterministic Jitter vs Temperature
Figure 6. TX Deterministic Jitter vs Temperature
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
20 40 60 80 100 120 140 160 180 200 220
Modulation Current Register Setting (Decimal)
-40
-20
0
20
40
60
80
100
Free-Air Temperature (°C)
D014
D015
TXMODE = 1
Figure 7. TX Random Jitter vs Modulation Current
TXMODE = 1
Figure 8. TX Random Jitter vs Temperature
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Typical Characteristics (continued)
Typical operating condition is at VCC = 2.5 V, TA = 25°C, TXOUT+ = 2 VPP Single-ended, RXOUT = 600 mVPP differential,
TXIN = 600 mVPP differential, TX and RX CDRs enabled (unless otherwise noted).
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
Rise Time
Fall Time
Rise Time
Fall Time
0
0
0
20 40 60 80 100 120 140 160 180 200 220
TXMOD Register 12 Setting - Decimal
-40
-20
0
20
40
60
80
100
Free-Air Temperature (°C)
D016
D017
TXMODE = 1
TXMODE = 1
Figure 9. TX Rise-Time and Fall-Time vs Modulation Current
Figure 10. TX Rise-Time and Fall-Time vs Temperature
180
180
160
140
120
100
80
160
140
120
100
80
60
60
40
40
20
20
0
0
0
200
400
600
800
1000
1200
0
200
400
600
800
1000
1200
TXBIAS Register 15 and 16 Setting (Decimal)
TXBIAS Register 15 and 16 Setting (Decimal)
D018
D019
Figure 11. Source Bias Current in Open Loop Mode vs Bias
Register Setting
Figure 12. Sink Bias Current in Open Loop Mode vs Bias
Register Setting
0.5
0.4
0.3
0.2
0.1
0
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
20
40
60
80
100 120 140 160 180
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Photodiode Current (mA)
1
Bias Current (mA)
D020
D021
TXPDRNG[0..1] = 00
Figure 13. Bias-Monitor Current I(MONB) vs Bias Current
Figure 14. Photodiode-Monitor Current I(MONP) vs PD Current
14
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Typical Characteristics (continued)
Typical operating condition is at VCC = 2.5 V, TA = 25°C, TXOUT+ = 2 VPP Single-ended, RXOUT = 600 mVPP differential,
TXIN = 600 mVPP differential, TX and RX CDRs enabled (unless otherwise noted).
4.5
2.5
4
2
3.5
3
1.5
1
2.5
2
1.5
1
0.5
0
0.5
0
0
20 40 60 80 100 120 140 160 180 200 220
TXMOD Register 12 Setting (Decimal)
0
20 40 60 80 100 120 140 160 180 200 220
TXMOD Register 12 Setting (Decimal)
D022
D023
TXMODE = 0
TXMODE = 1
Figure 15. Output Voltage vs Modulation Current
Figure 16. Output Voltage vs Modulation Current
300
290
280
270
260
250
240
230
220
260
250
240
230
220
210
200
190
180
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Free Air Temperature (°C
Free Air Temperature (°C)
D024
D025
TXMODE = 0
Bias Current = 0
TXMODE = 1
Bias Current = 0
Figure 17. Supply Current vs Temperature
Figure 18. Supply Current vs Temperature
180
160
140
120
100
80
1.2
1
0.8
0.6
0.4
0.2
0
60
40
20
0
0
50
100
150
200
250
300
0
50
100
150
200
250
300
TXBMF Register 17 Setting (Decimal)
TXPMF Register 18 Setting (Decimal)
D026
D027
Figure 19. Bias Current Monitor Fault vs TXBMF Register
Setting
Figure 20. Photodiode Current Monitor Fault vs TXPMF
Register Setting
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Typical Characteristics (continued)
Typical operating condition is at VCC = 2.5 V, TA = 25°C, TXOUT+ = 2 VPP Single-ended, RXOUT = 600 mVPP differential,
TXIN = 600 mVPP differential, TX and RX CDRs enabled (unless otherwise noted).
TXMODE = 0
15 ps/Div
TXMODE = 1
15 ps/Div
Figure 21. TX Eye-Diagram at 11.3 Gbps
Figure 22. TX Eye-Diagram at 11.3 Gbps
800
700
600
500
400
300
200
100
0
50
45
40
35
30
25
20
15
10
5
0
0.1
1
10
100
0
50
100
150
200
250
300
Frequency (GHz)
Input Voltage (mVPP
)
D001
D002
Figure 23. RX Frequency Response (CDR Disabled)
Figure 24. RX Transfer Function
0
-5
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-10
-15
-20
-25
-30
-35
-40
-45
-50
0.1
1
10
100
0.1
1
10
100
Frequency (GHz)
Frequency (GHz)
D003
D004
Figure 25. RX Differential Input Return Gain vs Frequency
Figure 26. RX Differential Output Return Gain vs Frequency
16
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Typical Characteristics (continued)
Typical operating condition is at VCC = 2.5 V, TA = 25°C, TXOUT+ = 2 VPP Single-ended, RXOUT = 600 mVPP differential,
TXIN = 600 mVPP differential, TX and RX CDRs enabled (unless otherwise noted).
8
7
6
5
4
3
2
1
0
1E-3
1E-4
1E-5
1E-6
1E-7
1E-8
1E-9
1E-10
1E-11
1E-12
0
1
2
3
4
5
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Input Voltage (mVPP
Input Voltage (mVPP
)
)
D005
D006
11.3 Gbps
TX Disabled
Figure 27. RX Bit-Error Ratio vs Input Amplitude
Figure 28. RX Deterministic Jitter vs Input Amplitude
260
240
220
200
180
160
140
120
100
80
1
0.8
0.6
0.4
0.2
0
60
40
LOS Assert Voltage
LOS Deassert Voltage
20
0
20
30
40
50
60
70
80
90
100
0
10
20
30
40
Input Voltage (mVPP
)
Register Setting (Decimal)
D007
D008
RX LOSRNG = 0
Figure 29. RX Random Jitter vs Input Amplitude
Figure 30. LOS Assert / Deassert Voltage vs Register 7
Setting
160
8
LOS Assert Voltage
LOS Deassert Voltage
140
120
100
80
7
6
5
4
3
2
1
0
60
40
20
0
0
10
20
30
40
50
0
10
20
30
40
Register Setting (Decimal)
Register Setting (Decimal)
D009
D028
RX LOSRNG = 1
RX LOSRNG = 0
Figure 32. LOS Hysteresis vs Register 7 Setting
Figure 31. LOS Assert / Deassert Voltage vs Register 7
Setting
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Typical Characteristics (continued)
Typical operating condition is at VCC = 2.5 V, TA = 25°C, TXOUT+ = 2 VPP Single-ended, RXOUT = 600 mVPP differential,
TXIN = 600 mVPP differential, TX and RX CDRs enabled (unless otherwise noted).
8
7
6
5
4
3
2
1
0
0
10
20
30
40
50
Register Setting (Decimal)
VI = 20 mVPP
D028
RX LOSRNG = 1
Figure 33. LOS Hysteresis vs Register Setting
Figure 34. RX Output Eye-Diagram at 11.3 Gbps
Pin = –20 dBm
CDR Disabled
Pin = –20 dBm
CDR Enabled
Figure 36. RX Output Eye-diagram at 10.71 Gbps
Figure 35. RX Output Eye-diagram at 10.71 Gbps
18
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ZHCSDW5A –JUNE 2015–REVISED JULY 2015
8 Detailed Description
8.1 Overview
A simplified block diagram of the ONET1130EC is shown in Functional Block Diagram.
The ONET1130EC consists of a transmitter path, a receiver path, an analog reference block, an analog to digital
converter and a 2-wire serial interface and control logic block with power-on reset.
The transmit path consists of an adjustable input equalizer, a multi-rate CDR and an output modulator driver. The
output driver provides a differential output voltage but can be operated in a single-ended mode to reduce the
power consumption. Output waveform control, in the form of cross-point adjustment and de-emphasis are
available to improve the optical eye mask margin. Bias current for the laser is provided and an integrated
automatic power control (APC) loop to compensate for variations in average optical power over voltage,
temperature and time is included.
The receive path consists of a limiting amplifier with programmable equalization and threshold adjustment, a
multi-rate CDR and an output driver with de-emphasis to compensate for frequency dependent loss of
connectors and transmission lines. The receiver output amplitude, de-emphasis and loss of signal assert level
can be adjusted.
The ONET1130EC contains an analog to digital converter to support transceiver digital diagnostics and can
report the supply voltage, laser bias current, laser photodiode current and internal temperature.
The 2-wire serial interface is used to control the operation of the device and read the status of the control
registers.
The device contains internal EEPROM for trimming purposes only.
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8.2 Functional Block Diagram
VCC_TX
Modulator
Driver
60ꢀ
60ꢀ
TX_LF
TXIN+
Referenceless
CDR and
EQ
100ꢀ
Retimer
TXIN-
TXOUT+
TXOUT-
AMP
AMP
BIAS
FLT
Modulation
and Bias
Current
BIAS
CDR_CTRL
2-Wire Interface
& Control Logic
VDD
TX_FLT
Generator &
APC
TX_LOL
PD
PD
EEPROM
COMP
MONB
COMP
Electrical
Loopback
Optical
Loopback
MONB
MONP
MONB
MONP
Power-On
Reset
MONP
Band-Gap, Analog
References, Power
Supply Monitor &
Temperature Sensor
Analog to
Digital
Conversion
SCK
SDA
PSM
TS
TX_DIS
RX_DIS
RX_LOL
CDR_CTRL
LOL
VCC_RX
Limiting
Amplifier
Threshold
45ꢀ
LOS
RX_LOS
45ꢀ
RXOUT+
RXOUT-
RXIN+
RXIN-
Referenceless
CDR and
Retimer
EQ
100ꢀ
RX_LF
Offset
Cancellation
with
Threshold
Adjust
20
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ZHCSDW5A –JUNE 2015–REVISED JULY 2015
8.3 Feature Description
8.3.1 Transmitter
8.3.1.1 Equalizer
The data signal is applied to an input equalizer by means of the input signal pins TXIN+ / TXIN–, which provide
on-chip differential 100-Ω line termination. The equalizer is enabled by default and can be disabled by setting the
transmitter equalizer disable bit TXEQ_DIS = 1 (bit 1 of register 10). Equalization of up to 300 mm (12 inches) of
microstrip or stripline transmission line on FR4 printed circuit boards can be achieved. The amount of
equalization is set through register settings TXCTLE [0..3] (register 11). The device can accept input amplitude
levels from 100 mVpp up to 1000 mVpp.
8.3.1.2 CDR
The clock and data recovery function consists of a Phase-Locked Loop (PLL) and retimer. The CDR can be
operated without a reference clock and the Voltage Controlled Oscillator (VCO) can cover 9.8 Gbps to 11.7 Gbps
data rates. The PLL is phase locked to the incoming data stream and attenuates the high frequency jitter on the
data, producing a recovered clean clock with substantially reduced jitter. An external capacitor for the PLL loop
filter is connected to the TX_LF pin. A value of 2.2 nF is recommended. The clean clock is used to retime the
incoming data, producing an output signal with reduced jitter, and in effect, resetting the jitter budget for the
transmitter.
The CDR is enabled by default. The CDR can be disabled and bypassed by setting the transmitter CDR disable
bit TXCDR_DIS = 1 (bit 4 of register 10). Alternatively, the CDR can be left powered on but bypassed by setting
the transmitter CDR bypass bit TX_CDRBP = 1 (bit 3 of register 10); however, this function only works if the
receiver CDR bypass bit RX_CDRBP (bit 3 of register 4) is also set to 1.
The CDR is designed to meet the XFP Datacom requirements and Telecom requirements for a maximum of 1-dB
jitter peaking at a frequency greater than 120 kHz. The CDR is not designed to meet the Telecom regenerator
requirements of jitter peaking less than 0.03 dB at a frequency less than 120 kHz. The default CDR bandwidth is
typically 4.5 MHz and can be adjusted using the SEL_RES[0..2] bits (bits 5 to 7 of register 51). Adjusting these
bits changes the bandwidth of both the transmitter and receiver CDRs.
For the majority of applications, the default settings in register 19 for the transmitter CDR can be used. However,
for some applications or for test purposes, some modes of operation may be useful. The frequency detector for
the PLL is set to an automatic mode of operation by default. When a signal is applied to the transmitter input the
frequency detector search algorithm will be initiated to determine the frequency of the data. The default algorithm
ensures a fast CDR lock time of less than 2 ms. The fast lock can be disabled by setting the transmitter CDR fast
lock disable bit TXFL_DIS = 1 (bit 3 of register 19). Once the frequency has been detected then the frequency
detector will be disabled and the supply current will decrease by approximately 10mA. In some applications, such
as when there are long periods of idle data, it may be advantageous to keep the frequency detector permanently
enabled by setting the transmitter frequency detector enable bit TXFD_EN = 1 (bit 5 of register 19). For test
purposes, the frequency detector can be permanently disabled by setting the transmitter frequency detector
disable bit TXFD_DIS = 1 (bit 4 of register 19). For fast lock times the frequency detector can be set to one of
two preselected data rates using the transmitter frequency detection mode selection bits TXFD_MOD[0..1] (bits 6
and 7 of register 19). If it is desired to use the retimer at lower data rates than the standard 9.8 to 11.7Gbps then
the transmitter divider ratio should be adjusted accordingly through TXDIV[0..2] (bits 0 to 2 of register 19). For
example, for re-timed operation at 2.5 Gbps the divider should be set to divide by 4.
8.3.1.3 Modulator Driver
The modulation current is sunk from the common emitter node of the limiting output driver differential pair by
means of a modulation current generator, which is digitally controlled by the 2-wire serial interface.
The collector nodes of the output stages are connected to the transmitter output pins TXOUT+ and TXOUT–.
The collectors have internal 50Ω back termination resistors to VCC_TX. The outputs are optimized to drive a 50
Ω single-ended load and to obtain the maximum single-ended output voltage of 2.0Vpp, AC coupling and
inductive pull-ups to VCC are required. For reduced power consumption the DC resistance of the inductive pull-
ups should be minimized to provide sufficient headroom on the TXOUT+ and TXOUT– pins.
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Feature Description (接下页)
The polarity of the output pins can be inverted by setting the transmitter output polarity switch bit, TXOUTPOL
(bit 5 of register 10) to 1. In addition, the output driver can be disabled by setting the transmitter output driver
disable bit TXOUT_DIS = 1 (bit 6 of register 10).
The output driver is set to differential output by default. In order to reduce the power consumption for single-
ended applications driving an electroabsorptive modulated laser (EML) the output drive register 13 should be set
to single-ended mode. The single-ended output signal is enabled by setting the transmitter mode select bit
TXMODE = 1 (bit 6 of register 13). The positive output is active by default. To enable the negative output and
disable the positive output set TXOUTSEL = 1 (bit 7 of register 13).
Output de-emphasis can be applied to the signal by adjusting the transmitter de-emphasis bits TXDEADJ[0..3]
(bits 0 to 3 of register 13). In addition, the width of the applied de-emphasis can be increased by setting the
transmitter output peaking width TXPKSEL = 1 (bit 6 of register 11). The wide peaking width would typically be
useful for a more capacitive transmitter load. How de-emphasis is applied is controlled through the TXSTEP bit
(bit 5 of register 13). Setting TXSTEP = 1 delays the time of the applied de-emphasis and has more of an impact
on the falling edge. A graphical representation of the two de-emphasis modes is shown in 图 37. Using de-
emphasis can help to optimize the transmitted output signal; however, it will add to the power consumption.
The output edge speed can be set to slow mode of operation through the TXSLOW bit (bit 4 of register 13). For
transmitter modulation output settings (TXMOD - register 12) below 0xC0 it is recommended to set TXSLOW = 1
to reduce the output jitter.
Register 13
Register 13
Bits 0œ3
Bits 0œ3
Register 11
Bit 6
Register 11
Bit 6
Transmitter De-Emphasis
Register 13 Bit 5 = 0
Transmitter De-Emphasis
Register 13 Bit 5 = 1
图 37. Transmitter De-Emphasis Modes
8.3.1.4 Modulation Current Generator
The modulation current generator provides the current for the high speed output driver described above. The
circuit can be digitally controlled through the 2-wire interface block or controlled by applying an analog voltage in
the range of 0 to 2V to the AMP pin. The default method of control is through the 2-wire interface. To use the
AMP pin set the transmitter amplitude control bit TXAMPCTRL = 1 (bit 0 of register 10).
An 8-bit wide control bus, TXMOD[0..7] (register 12), is used to set the desired modulation current and the output
voltage.
The entire transmitter signal path, including CDR, can be disabled and powered down by setting TX_DIS = 1 (bit
7 of register 10).
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Feature Description (接下页)
8.3.1.5 DC Offset Cancellation and Cross Point Control
The ONET1130EC transmitter has DC offset cancellation to compensate for internal offset voltages. The offset
cancellation can be disabled by setting TXOC_DIS = 1 (bit 2 of register 10).
The crossing point can be moved toward the one level by setting TXCPSGN = 1 (bit 7 of register 14) and it can
be moved toward the zero level by setting TXCPSGN = 0. The percentage of shift depends upon the register
settings of the transmitter cross-point adjustment bits TXCPADJ[0..6] (register 14).
8.3.1.6 Transmitter Loopback (Electrical Loopback)
The signal input to the TXIN+ and TXIN– pins can be looped back to the receiver output after the retimer as
shown in 图 38 by setting TX_LBMUX = 1 (bit 0 of register 2). Loopback from the receiver input to the transmitter
output (optical loopback) can be enabled at the same time.
If it is desired to loopback the signal input to the TXIN+ and TXIN– pins to the receiver output with the CDR
disabled then the transmit CDR must be disabled and bypassed by setting TXCDR_DIS = 1 (bit 4 of register 10)
and the receiver CDR must also be disabled and bypassed by setting RXCDR_DIS =1 (bit 4 of register 4).
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Feature Description (接下页)
VCC_TX
Modulator
Driver
60ꢀ
60ꢀ
TX_LF
TXIN+
Referenceless
CDR and
EQ
100ꢀ
Retimer
TXIN-
TXOUT+
TXOUT-
AMP
BIAS
FLT
AMP
BIAS
Modulation
and Bias
Current
Generator &
APC
CDR_CTRL
2-Wire Interface
& Control Logic
VDD
TX_FLT
TX_LOL
PD
PD
EEPROM
COMP
MONB
COMP
Electrical
Loopback
Optical
Loopback
MONB
MONP
MONB
MONP
Power-On
Reset
MONP
Band-Gap, Analog
References, Power
Supply Monitor &
Temperature Sensor
Analog to
Digital
Conversion
SCK
SDA
PSM
TS
TX_DIS
RX_DIS
RX_LOL
CDR_CTRL
LOL
VCC_RX
Limiting
Amplifier
Threshold
45ꢀ
LOS
RX_LOS
RXIN+
45ꢀ
RXOUT+
RXOUT-
Referenceless
EQ
CDR and
Retimer
100ꢀ
RXIN-
RX_LF
Offset
Cancellation
with
Threshold
Adjust
图 38. Electrical Loopback
24
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Feature Description (接下页)
8.3.1.7 Bias Current Generation and APC Loop
The bias current for the laser is turned off by default and has to be enabled by setting the laser bias current
enable bit TXBIASEN = 1 (bit 2 of register 1). In open loop operation, selected by setting TXOLENA = 1 (bit 4 of
register 1), the bias current is set directly by the 10-bit wide control word TXBIAS[0..9] (register 15 and register
16). In Automatic Power Control (APC) mode, selected by setting TXOLENA = 0, the bias current depends on
the register settings TXBIAS[0..9] and the coupling ratio (CR) between the laser bias current and the photodiode
current. CR = IBIAS/IPD. If the photodiode cathode is connected to VCC and the anode is connected to the PD pin
(PD pin is sinking current) set TXPDPOL = 1 (bit 0 of register 1). If the photodiode anode is connected to ground
and the cathode is connected to the PD pin (PD pin is sourcing current), set TXPDPOL = 0.
Three photodiode current ranges can be selected by means of the photodiode current range bits TXPDRNG[0..1]
(bits 5 and 6 of register 1). The photodiode range should be chosen to keep the laser bias control DAC,
TXBIAS[0..9], close to the center of its range. This keeps the laser bias current set point resolution high. For
details regarding the bias current setting in open-loop mode as well as in closed-loop mode, see the Register
Mapping table.
The ONET1130EC has the ability to source or sink the bias current. The default condition is for the BIAS pin to
source the current (TXBIASPOL = 0). To act as a sink, set TXBIASPOL = 1 (bit 1 of register 1).
The bias current is monitored using a current mirror with a gain equal to 1/100. By connecting a resistor between
MONB and GND, the bias current can be monitored as a voltage across the resistor. A low temperature
coefficient precision resistor should be used. The bias current can also be monitored as a 10 bit unsigned digital
word by setting the transmitter bias current digital monitor selection bit TXDMONB = 1 (bit 5 of register 16) and
removing the resistor from MONB to ground.
The photodiode current is monitored using a current mirror with various gains that are dependent upon the
photodiode current range being used. By connecting a resistor between MONP and GND, the photodiode current
can be monitored as a voltage across the resistor. A low temperature coefficient precision resistor should be
used. The photodiode current can also be monitored as a 10 bit unsigned digital word by setting the transmitter
photodiode current digital monitor selection bit TXDMONP = 1 (bit 6 of register 16) and removing the resistor
from MONP to ground.
8.3.1.8 Laser Safety Features and Fault Recovery Procedure
The ONET1130EC provides built in laser safety features. The following fault conditions are detected if the
transmitter fault detection enable bit TXFLTEN = 1 (bit 3 of register 1):
1. Voltage at MONB exceeds the bandgap voltage (1.2 V) or, alternately, if TXDMONB = 1 and the bias current
exceeds the bias current monitor fault threshold set by TXBMF[0..7] (register 17). When using the digital
monitor, the resistor from the MONB pin to ground must be removed.
2. Voltage at MONP exceeds the bandgap voltage (1.2 V) and the analog photodiode current monitor fault
trigger bit, TXMONPFLT (bit 7 of register 1), is set to 1. Alternately, a fault can be triggered if TXDMONP = 1
and the photodiode current exceeds the photodiode current monitor fault threshold set by TXPMF[0..7]
(register 18). When using the digital monitor, the resistor from the MONP pin to ground must be removed.
3. Photodiode current exceeds 150% of its set value,
4. Bias control DAC drops in value by more than 50% in one step.
If the fault detection is being used then to avoid a fault from occurring at start-up it is recommended to set up the
required bias current and APC loop conditions first and enable the laser bias current (TXBIASEN = 1) as the last
step in the sequence of commands.
If one or more fault conditions occur and the transmitter fault enable bit TXFLTEN is set to 1, the ONET1130EC
responds by:
1. Setting the bias current to zero.
2. Asserting and latching the TX_FLT pin.
3. Setting the TX_FLT bit (bit 5 of register 43) to 1.
Fault recovery is performed by the following procedure:
1. The transmitter disable pin TX_DIS and/or the transmitter bias current enable bit TXBIASEN are toggled for
at least the fault latch reset time.
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Feature Description (接下页)
2. The TX_FLT pin de-asserts while the transmitter disable pin TX_DIS is asserted or the transmitter bias
current enable bit TXBIASEN is de-asserted.
3. If the fault condition is no longer present, the part will return to normal operation with its prior output settings
after the disable negate time.
4. If the fault condition is still present, TX_FLT re-asserts once TX_DIS is set to a low level and/or TXBIASEN is
set to 0 and the part will not return to normal operation.
8.3.2 Receiver
8.3.2.1 Equalizer
The data signal is applied to an input equalizer by means of the input signal pins RXIN+ / RXIN–, which provide
on-chip differential 100 Ω line-termination. The equalizer is enabled by default and can be disabled by setting the
receiver equalizer disable bit RXEQ_DIS = 1 (bit 1 of register 4). Equalization is provided for bandwidth
compensation of the optical receiver. The amount of equalization is set through the register settings RXCTLE
[0..2] (register 5). The device can accept input amplitude levels from 6 mVpp up to 800 mVpp.
8.3.2.2 DC Offset Cancellation and Cross Point Control
Receiver offset cancellation compensates for internal offset voltages and thus ensures proper operation even for
very small input data signals. The offset cancellation is enabled by default and the input threshold voltage can be
adjusted using register settings RXTHADJ[0..3] (register 6) to optimize the bit error rate or change the eye
crossing point to compensate for input signal pulse width distortion. The offset cancellation can be disabled by
setting RXOC_DIS = 1 (bit 2 of register 4) and this also disables the cross point adjustment.
8.3.2.3 CDR
The receiver clock and data recovery function consists of a Phase-Locked Loop (PLL) and retimer. The CDR can
be operated without a reference clock and the Voltage Controlled Oscillator (VCO) can cover 9.8Gbps to 11.7
Gbps data rates. The PLL is phase locked to the incoming data stream and attenuates the high frequency jitter
on the data, producing a recovered clean clock with substantially reduced jitter. An external capacitor for the PLL
loop filter is connected to the RX_LF pin. A value of 2.2 nF is recommended. The clean clock is used to retime
the incoming data, producing an output signal with reduced jitter, and in effect, resetting the jitter budget for the
receiver.
The CDR is enabled by default. The CDR can be disabled and bypassed by setting the receiver CDR disable bit
RXCDR_DIS = 1 (bit 4 of register 4). Alternatively, the CDR can be left powered on but bypassed by setting the
receiver CDR bypass bit RX_CDRBP = 1 (bit 3 of register 4); however, this only works if the transmitter CDR
bypass bit TX_CDRBP (bit 3 of register 10) is also set to 1.
The CDR is designed to meet the XFP Datacom requirements and Telecom requirements for a maximum of 1 dB
jitter peaking at a frequency greater than 120 kHz. The CDR is not designed to meet the Telecom regenerator
requirements of jitter peaking less than 0.03 dB at a frequency less than 120 kHz.The default CDR bandwidth is
typically 4.5 MHz and can be adjusted using the SEL_RES[0..2] bits (bits 5 to 7 of register 51). Adjusting these
bits changes the bandwidth of both the receiver and transmitter CDRs.
For the majority of applications the default settings in register 9 for the receiver CDR can be used. However, for
some applications or for test purposes, some modes of operation may be useful. The frequency detector for the
PLL is set to an automatic mode of operation by default. When a signal is applied to the receiver input the
frequency detector search algorithm will be initiated to determine the frequency of the data. The default algorithm
ensures a fast CDR lock time of less than 2 ms. The fast lock can be disabled by setting the receiver CDR fast
lock disable bit RXFL_DIS = 1 (bit 3 of register 9). Once the frequency has been detected then the frequency
detector will be disabled and the supply current will decrease by approximately 10 mA. In some applications,
such as when there are long periods of idle data, it may be advantageous to keep the frequency detector
permanently enabled by setting the receiver frequency detector enable bit RXFD_EN = 1 (bit 5 of register 9). For
test purposes, the frequency detector can be permanently disabled by setting the receiver frequency detector
26
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Feature Description (接下页)
disable bit RXFD_DIS = 1 (bit 4 of register 9). For fast lock times the frequency detector can be set to one of two
preselected data rates using the receiver frequency detection mode selection bits RXFD_MOD[0..1] (bits 6 and 7
of register 9). If it is desired to use the retimer at lower data rates than the standard 9.8 to 11.7 Gbps then the
receiver divider ratio should be adjusted accordingly through RXDIV[0..2] (bits 0 to 2 of register 9). For example,
for retimed operation at 2.5 Gbps the divider should be set to divide by 4.
8.3.2.4 Output Driver
The output amplitude of the driver can be varied from 300 mVpp to 900 mVpp using the register settings
RXAMP[0..3] (register 8). The default amplitude setting is 300 mVpp. To compensate for frequency dependent
losses of transmission lines connected to the output, adjustable de-emphasis is provided. The de-emphasis can
be adjusted using RXDADJ[0..2] (register 8). The polarity of the output pins can be inverted by setting the
receiver output polarity switch bit RXOUTPOL = 1 (bit 5 of register 4).
In addition, the output driver can be disabled by setting the receiver output driver disable bit RXOUT_DIS = 1 (bit
6 of register 4) or the receiver signal path can be disabled and powered down by setting RX_DIS = 1 (bit 7 of
register 4).
8.3.2.5 Receiver Loopback (Optical Loopback)
The signal input to the RXIN+ and RXIN– pins can be looped back to the transmitter output after the retimer as
shown in 图 39 by setting RX_LBMUX = 1 (bit 1 of register 2). Loopback from the transmitter input to the receiver
output (electrical loopback) can be enabled at the same time.
If it is desired to loopback the signal input to the RXIN+ and RXIN– pins to the transmitter output with the CDR
disabled then the receive CDR must be disabled and bypassed by setting RXCDR_DIS = 1 (bit 4 of register 4)
and the transmit CDR must also be disabled and bypassed by setting TXCDR_DIS =1 (bit 4 of register 10).
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Feature Description (接下页)
VCC_TX
Modulator
Driver
60ꢀ
60ꢀ
TX_LF
TXIN+
Referenceless
CDR and
EQ
100ꢀ
Retimer
TXIN-
TXOUT+
TXOUT-
AMP
BIAS
FLT
AMP
BIAS
Modulation
and Bias
Current
Generator &
APC
CDR_CTRL
2-Wire Interface
& Control Logic
VDD
TX_FLT
TX_LOL
PD
PD
EEPROM
COMP
MONB
COMP
Electrical
Loopback
Optical
Loopback
MONB
MONP
MONB
MONP
Power-On
Reset
MONP
Band-Gap, Analog
References, Power
Supply Monitor &
Temperature Sensor
Analog to
Digital
Conversion
SCK
SDA
PSM
TS
TX_DIS
RX_DIS
RX_LOL
CDR_CTRL
LOL
VCC_RX
Limiting
Amplifier
Threshold
45ꢀ
LOS
RX_LOS
RXIN+
45ꢀ
RXOUT+
RXOUT-
Referenceless
EQ
CDR and
Retimer
100ꢀ
RXIN-
RX_LF
Offset
Cancellation
with
Threshold
Adjust
图 39. Optical Loopback
28
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Feature Description (接下页)
8.3.2.6 Loss of Signal Detection
The loss of signal (LOS) detection is done by 2 separate level detectors to cover a wide dynamic range. The
peak values of the input signal are monitored by a peak detector and compared to a pre-defined loss of signal
threshold voltage inside the loss of signal detection block. As a result of the comparison, the LOS signal, which
indicates that the input signal amplitude is below the defined threshold level, is generated. There are 2 LOS
ranges settable with the RXLOSRNG bit (bit 0 of register 4). With RXLOSRNG = 0 the high range of the LOS
assert values are used (40 mVPP to 130 mVPP) and by setting RXLOSRNG = 1 the low range of the LOS assert
values are used (10 mVPP to 50 mVPP). There are 64 possible internal LOS settings set with RXLOSA[0..5]
(register 7) for each LOS range to adjust the LOS assert level.
The typical LOS hysteresis, as defined by 20log(LOS de-assert voltage/LOS assert voltage) is 4 dB. This can be
reduced by approximately 2 dB by setting receiver hysteresis RXHYS = 1 (bit 7 of register 6). In addition, the
LOS detection time can be reduced by setting the receiver fast LOS bit RXFLOS = 1 (bit 3 of register 5);
however, this may result in chatter (LOS bounce).
8.3.3 Analog Block
8.3.3.1 Analog Reference and Temperature Sensor
The ONET1130EC is supplied by a single 2.5 V ±5% supply voltage connected to the VCC_TX, VCC_RX and
VDD pins. This voltage is referred to ground (GND) and can be monitored as a 10 bit unsigned digital word
through the 2-wire interface.
On-chip bandgap voltage circuitry generates a reference voltage, independent of the supply voltage, from which
all other internally required voltages and bias currents are derived.
In order to minimize the module component count, the ONET1130ECprovides an on-chip temperature sensor.
The temperature can be monitored as a 10 bit unsigned digital word through the 2-wire interface.
8.3.3.2 Power-On Reset
The ONET1130EC has power on reset circuitry which ensures that all registers are reset to default values during
startup. After the power-on to initialize time (tINIT1), the internal registers are ready to be loaded. The part is ready
to transmit data after the initialize to transmit time (tINIT2), assuming that the enable chip bit EN_CHIP = 1 (bit 0 of
register 0). In addition, the transmitter disable pin TX_DIS and receiver disable pin RX_DIS must be set to zero.
The ONET1130EC bias current can be disabled by setting the TX_DIS pin high. The internal registers are not
reset. After the transmitter disable pin TX_DIS is set low the part returns to its prior output settings.
8.3.3.3 Analog to Digital Converter
The ONET1130EC has an internal 10 bit analog to digital converter (ADC) that converts the analog monitors for
temperature, power supply voltage, bias current and photodiode current into a 10 bit unsigned digital word. The
first 8 most significant bits (MSBs) are available in register 40 and the 2 least significant bits (LSBs) are available
in register 41. Depending on the accuracy required, 8 bits or 10 bits can be read. However, due to the
architecture of the 2-wire interface, in order to read the 2 registers, 2 separate read commands have to be sent.
The ADC is enabled by default so to monitor a particular parameter, select the parameter with ADCSEL[0..2]
(bits 0 to 2 of register 3). 表 2 shows the ADCSEL bits and the parameter that is monitored.
表 2. ADC Selection Bits and the Monitored Parameter
ADCSEL2
ADCSEL1
ADCSEL0
MONITORED PARAMETER
Temperature
0
0
0
0
0
0
1
1
0
1
0
1
Supply voltage
Bias current
Photodiode current
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To digitally monitor the photodiode current, ensure that TXDMONP = 1 (bit 6 of register 16) and that a resistor is
not connected to the MONP pin. To digitally monitor the bias current, ensure that TXDMONB = 1 (bit 5 of register
16) and that a resistor is not connected to the MONB pin. The ADC is disabled by default. To enable the ADC,
set the ADC oscillator enable bit OSCEN = 1 (bit 6 of register 3) and set the ADC enable bit ADCEN = 1 (bit 7 of
register 3).
The digital word read from the ADC can be converted to its analog equivalent through the following formulas.
Temperature (°C) = (0.5475 × ADCx) – 273
(1)
(2)
(3)
(4)
(5)
(6)
Power supply voltage (V) = (1.36m × ADCx) + 1.76
IPD(μA) = 2 x [ (0.62 × ADCx) – 16] for TXPDRNG00
IPD(μA) = 4 x [ (0.62 × ADCx) – 16] for TXPDRNG01
IPD(μA) = 8 x [ (0.62 × ADCx) – 16] for TXPDRNG1x
IBIAS (mA) = (0.2 × ADCx) – 4.5
Where: ADCx = the decimal value read from the ADC
8.3.3.4 2-Wire Interface and Control Logic
The ONET1130EC uses a 2-wire serial interface for digital control. The two circuit inputs, SDA and SCK, are
driven, respectively, by the serial data and serial clock from a microprocessor, for example. The SDA and SCK
pins require external 4.7-kΩ to 10-kΩ pull-up resistor to VCC for proper operation.
The 2-wire interface allows write access to the internal memory map to modify control registers and read access
to read out the control signals. The ONET1130EC is a slave device only which means that it cannot initiate a
transmission itself; it always relies on the availability of the SCK signal for the duration of the transmission. The
master device provides the clock signal as well as the START and STOP commands. The protocol for a data
transmission is as follows:
1. START command
2. Seven (7) bit slave address (0001000) followed by an eighth bit which is the data direction bit (R/W). A zero
indicates a WRITE and a 1 indicates a READ.
3. 8 bit register address
4. 8 bit register data word
5. STOP command
Regarding timing, the ONET1130EC is I2C compatible. The typical timing is shown in 图 2 and a complete data
transfer is shown in 图 40. Parameters for 图 2 are defined in 表 1.
8.3.3.5 Bus Idle
Both SDA and SCK lines remain HIGH
8.3.3.6 Start Data Transfer
A change in the state of the SDA line, from HIGH to LOW, while the SCK line is HIGH, defines a START
condition (S). Each data transfer is initiated with a START condition.
8.3.3.7 Stop Data Transfer
A change in the state of the SDA line from LOW to HIGH while the SCK line is HIGH defines a STOP condition
(P). Each data transfer is terminated with a STOP condition; however, if the master still wishes to communicate
on the bus, it can generate a repeated START condition and address another slave without first generating a
STOP condition.
8.3.3.8 Data Transfer
Only one data byte can be transferred between a START and a STOP condition. The receiver acknowledges the
transfer of data.
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8.3.4 Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge bit. The transmitter releases the
SDA line and a device that acknowledges must pull down the SDA line during the acknowledge clock pulse in
such a way that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Setup and
hold times must be taken into account. When a slave-receiver doesn’t acknowledge the slave address, the data
line must be left HIGH by the slave. The master can then generate a STOP condition to abort the transfer. If the
slave-receiver does acknowledge the slave address but some time later in the transfer cannot receive any more
data bytes, the master must abort the transfer. This is indicated by the slave generating the not acknowledge on
the first byte to follow. The slave leaves the data line HIGH and the master generates the STOP condition, see
图 2.
8.4 Device Functional Modes
The ONET1130EC has two main functional modes of operation: differential transmitter output and single-ended
transmitter output.
8.4.1 Differential Transmitter Output
Operation with differential output is the default mode of operation. This mode is intended for externally modulated
lasers requiring differential drive such as Mach Zehnder modulators.
8.4.2 Single-Ended Transmitter Output
In order to reduce the power consumption for single-ended EML applications the output driver should be set to
single-ended mode. The single-ended output signal can be enabled by setting the transmitter mode select bit
TXMODE = 1 (bit 6 of register 13). The positive output is active by default. To enable the negative output and
disable the positive output set TXOUTSEL = 1 (bit 7 of register 13).
8.5 Programming
Write Sequence
1
1
1
8
1
8
1
1
7
S
Slave Address
Wr
A
Register Address
A
Data Byte
A
P
Read Sequence
1
1
1
8
1
1
1
1
8
1
1
7
7
S
Slave Address
Wr
A
Register Address
A
S
Slave Address
Rd
A
Data Byte
N
P
Legend
S
Start Condition
Wr
Rd
A
Write Bit (Bit Value = 0)
Read Bit (Bit Value = 1)
Acknowledge
N
Not Acknowledge
Stop Condition
P
图 40. Programming Sequence
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8.6 Register Mapping
8.6.1 R/W Control Registers
8.6.1.1 Core Level Register 0 (offset = 0100 0001 [reset = 41h]
图 41. Core Level Register 0
7
0
6
5
–
4
3
2
1
0
0
1
Reserved
–
RWSC
RW
–
RWSC
RWSC
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset. RWSC = Read/Write self clearing (always reads back to zero)
表 3. Core Level Register 0 Field Descriptions
Bit
Field
Type
Reset
Description
7
GLOBAL SW_PIN RESET
RWSC 0h
Global Reset SW
1 = reset, resets all I2C and EEPROM modules to default
0 = normal operation (self-clearing, always reads back ‘0’)
6 :2
1
–
R/W
4h
Reserved
I2C RESET
RWSC 0h
Chip reset bit
1 = resets all I2C registers to default
0 = normal operation (self-clearing, always reads back ‘0’)
0
EN_CHIP
R/W
1h
Enable chip bit
1 = Chip enabled
8.6.1.2 Core Level Register 1 (offset = 0000 0000) [reset = 0h]
图 42. Core Level Register 1
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 4. Core Level Register 1 Field Descriptions
Bit
Field
Type
Reset
Description
Analog photodiode current monitor fault trigger bit
1 = Fault trigger on MONP pin is enabled
0 = Fault trigger on MONP pin is disabled
7
TXMONPFLT
R/W
0
Photodiode current range bits
1X: up to 3080μA / 3μA resolution
01: up to 1540μA / 1.5μA resolution
00: up to 770μA / 0.75μA resolution
6
5
TXPDRNG1
TXPDRNG0
R/W
0
Open loop enable bit
4
3
2
1
TXOLENA
TXFLTEN
R/W
R/W
R/W
R/W
0
0
0
0
1 = Open loop bias current control
0 = Closed loop bias current control
Fault detection enable bit
1 = Fault detection on
0 = Fault detection off
Laser Bias current enable bit
1 = Bias current enabled. Toggle to 0 to reset a fault condition.
0 = Bias current disabled
TXBIASEN
TXBIASPOL
Laser Bias current polarity bit
1 = Bias pin sinks current
0 = Bias pin sources current
32
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表 4. Core Level Register 1 Field Descriptions (接下页)
Bit
Field
Type
Reset
Description
Photodiode polarity bit
0
TXPDPOL
R/W
0
1 = Photodiode cathode connected to VCC
0 = Photodiode anode connected to GND
8.6.1.3 Core Level Register 2 (offset = 0000 0000 ) [reset = 0h]
图 43. Core Level Register 2
7
6
5
4
3
2
1
0
0
0
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 5. Core Level Register 2 Field Descriptions
Bit
7:4
3
Field
Type
R/W
R/W
R/W
R/W
Reset
0h
Description
Reserved
Reserved
Reserved
–
–
0h
2
–
0h
1
RX_LBMUX
0h
RX-Loopback MUX Setting (optical LB)
1 = Loopback from TX-CDR output selected.
0 = Normal operation: RX-CDR output selected
0
TX_LBMUX
R/W
0h
TX-Loopback MUX Setting (electrical LB)
1 = Loopback from RX-CDR output selected.
0 = Normal operation: TX-CDR output selected
8.6.1.4 Core Level Register 3 (offset = 0000 0000) [reset = 0h]
图 44. Core Level Register 3
7
0
6
0
5
–
4
0
3
–
2
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 6. Core Level Register 3 Field Descriptions
Bit
Field
Type
Reset
Description
ADC enabled bit
1 = ADC enabled
0 = ADC disabled
7
ADCEN
R/W
0h
ADC oscillator bit
6
5
4
OSCEN
–
R/W
R/W
R/W
0h
0h
0h
1 = Oscillator enabled
0 = Oscillator disabled
Reserved
ADC reset
1 = ADC reset
0 = ADC no reset
ADCRST
3
2
1
–
R/W
R/W
R/W
0h
0h
0h
Reserved
ADCSEL2
ADCSEL1
ADC input selection bits <2:0>
000 selects the temperature sensor
001 selects the power supply monitor
010 selects IMONB
0
ADCSEL0
R/W
0h
011 selects IMONP
1XX are reserved
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8.6.2 RX Registers
8.6.2.1 RX Register 4 (offset = 0000 0000) [reset = 0h]
图 45. RX Register 4
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 7. RX Register 4 Field Descriptions
Bit
Field
Type
Reset
Description
RX disable bit
7
RX_DIS
R/W
0h
1 = RX disabled (power-down)
0 = RX enabled
RX Output Driver disable bit
1 = output driver is disabled
0 = output driver is enabled
6
5
4
RXOUT_DIS
RXOUTPOL
RXCDR_DIS
R/W
R/W
R/W
0h
0h
0h
RX Output polarity switch bit
1 = inverted polarity
0 = normal polarity
RX CDR disable bit
1 = RX CDR is disabled and bypassed
0 = RX CDR is enabled
RX CDR bypass bit
1 = RX-CDR bypassed. TX_CDRBP must be set to 1 for this function to
operate.
3
RX_CDRBP
R/W
0h
0 = RX-CDR not bypassed
RX Offset cancellation disable bit
2
1
0
RXOC_DIS
RXEQ_DIS
RXLOSRNG
R/W
R/W
R/W
0h
0h
0h
1 = offset cancellation and threshold adjust is disabled
0 = offset cancellation and threshold adjust is enabled
RX Equalizer disable bit
1 = RX Equalizer is disabled and bypassed
0 = RX Equalizer is enabled
LOS range bit
1 = low LOS assert voltage range
0 = high LOS assert voltage range
34
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8.6.2.2 RX Register 5 (offset = 0000 0000) [reset = 0h]
图 46. RX Register 5
7
6
5
4
3
0
2
0
1
0
0
0
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 8. RX Register 5 Field Descriptions
Bit
Field
Type
Reset
Description
7:4
–
R/W
0h
Reserved
Receiver fast LOS bit
1 = Fast LOS
3
RXFLOS
R/W
0h
0 = normal operation
2
1
0
RXCTLE2
RXCTLE1
RXCTLE0
R/W
R/W
R/W
0h
0h
0h
RX input CTLE setting
000 = minimum
111 = maximum
8.6.2.3 RX Register 6 (offset = 0000 0000) [reset = 0h]
图 47. RX Register 6
7
0
6
5
4
0
3
0
2
0
1
0
0
0
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 9. RX Register 6 Field Descriptions
Bit
Field
Type
Reset
Description
Receiver Hysteresis
7
RXHYS
R/W
0h
1 = Reduce hysteresis level by approximately 2dB
0 = default level of hysteresis (approximately 4dB)
6:5
4
–
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
Reserved
RXTHSGN
RXTHADJ3
RXTHADJ2
RXTHADJ1
RX Eye cross-point adjustment setting
RXTHSGN = 1 (positive shift)
3
Maximum shift for 1111
2
Minimum shift for 0000
RXTHSGN = 0 (negative shift)
1
Maximum shift for 1111
Minimum shift for 0000
0
RXTHADJ0
R/W
0h
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8.6.2.4 RX Register 7 (offset = 0000 0000) [reset = 0h]
图 48. RX Register 7
7
6
5
0
4
0
3
0
2
0
1
0
0
0
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 10. RX Register 7 Field Descriptions
Bit
7:6
5
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0h
Description
–
Reserved
RXLOSA5
RXLOSA4
RXLOSA3
RXLOSA2
RXLOSA1
RXLOSA0
0h
LOS assert level
Minimum LOS assert level for 000000
Maximum LOS assert level for 111111
4
0h
3
0h
2
0h
1
0h
0
0h
8.6.2.5 RX Register 8 (offset = 0000 0000) [reset = 0h]
图 49. RX Register 8
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 11. RX Register 8 Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
0h
Description
–
Reserved
6
RXDADJ1
0h
RX output de-emphasis setting
00 = minimum de-emphasis
11 = maximum de-emphasis
5
RXDADJ0
R/W
0h
RX driver short circuit protection
1 = short circuit protection enabled
0 = normal operation
4
RXDRVSC
R/W
0h
3
2
1
0
RXAMP3
RXAMP2
RXAMP1
RXAMP0
R/W
R/W
R/W
R/W
0h
0h
0h
0h
RX output amplitude adjustment
0000 = minimum amplitude
1111 = maximum amplitude
36
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8.6.2.6 RX Register 9 (offset = 0000 0000) [reset = 0h]
图 50. RX Register 9
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 12. RX Register 9 Field Descriptions
Bit
Field
Type
Reset
Description
7
RXFD_MOD1
R/W
0h
RX frequency detection mode selection
00 = auto selection enabled
01 = Pre-selected to 10.3Gbps
10 = Pre-select to 11.1Gbps
6
RXFD_MOD0
R/W
0h
11 = test mode (do not use)
RX frequency detector enable bit
5
4
3
RXFD_EN
RXFD_DIS
RXFL_DIS
R/W
R/W
R/W
0h
0h
0h
1 = RX frequency detector is always enabled
0 = RX frequency detector in automatic mode
RX frequency detector disable bit
1 = RX frequency detector is always disabled
0 = RX frequency detector is in automatic mode
RX CDR fast lock disable bit
1 = RX CDR fast lock disabled
0 = RX CDR in fast lock mode
2
1
RXDIV2
RXDIV1
R/W
R/W
0h
0h
RX Divider Ratio
000: Full-Rate,
001: Divide by 2
010: Divide by 4
011: Divide by 8
100: Divide by 16
101: Divide by 32
0
RXDIV0
R/W
0h
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8.6.3 TX Registers
8.6.3.1 TX Register 10 (offset = 0000 0000) [reset = 0h]
图 51. TX Register 10
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 13. TX Register 10 Field Descriptions
Bit
Field
Type
Reset
Description
TX disable bit
7
TX_DIS
R/W
0h
1 = TX disabled (power-down)
0 = TX enabled
TX Output Driver disable bit
1 = output disabled
0 = output enabled
6
5
4
TXOUT_DIS
TXOUTPOL
TXCDR_DIS
R/W
R/W
R/W
0h
0h
0h
TX Output polarity switch bit
1 = inverted polarity
0 = normal polarity
TX CDR disable bit
1 = TX CDR is disabled and bypassed
0 = TX CDR is enabled
TX CDR bypass bit
1 = TX-CDR bypassed. RX_CDRBP must be set to 1 for this function to
operate.
3
TX_CDRBP
R/W
0h
0 = TX-CDR not bypassed
TX OC disable bit
2
1
0
TXOC_DIS
TXEQ_DIS
TXAMPCTRL
R/W
R/W
R/W
0h
0h
0h
1 = TX Offset Cancellation disabled
0 = TX Offset Cancellation enabled
TX Equalizer disable bit
1 = TX Equalizer is disabled and bypassed
0 = TX Equalizer is enabled
TX AMP Ctrl
1 = TX AMP Control is enabled (analog amplitude control)
0 = TX AMP Control is disabled (digital amplitude control)
38
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8.6.3.2 TX Register 11 (offset = 0000 0000) [reset = 0h]
图 52. TX Register 11
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 14. TX Register 11 Field Descriptions
Bit
Field
Type
Reset
Description
TX output AMP range
7
TXAMPRNG
R/W
0h
1 = Half TX output amplitude range
0 = Full TX output amplitude range
TX output peaking width
1 = wide peaking width
0 = narrow peaking width
6
TXPKSEL
R/W
0h
5
4
3
2
1
0
TXTCSEL1
TXTCSEL0
TXCTLE3
TXCTLE2
TXCTLE1
TXCTLE0
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
TXOUT temperature compensation select bit 1
TXOUT temperature compensation select bit 0
TX input CTLE setting
0000 = minimum
1111 = maximum
8.6.3.3 TX Register 12 (offset = 0000 0000) [reset = 0h]
图 53. TX Register 12
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 15. TX Register 12 Field Descriptions
Bit
7
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0h
Description
TXMOD7
TXMOD6
TXMOD5
TXMOD4
TXMOD3
TXMOD2
TXMOD1
TXMOD0
6
0h
5
0h
4
0h
TX Modulation current setting: sets the output voltage
Output Voltage: 2.4 Vpp / 9.5 mVpp steps
3
0h
2
0h
1
0h
0
0h
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8.6.3.4 TX Register 13 (offset = 0h) [reset = 0]
图 54. TX Register 13
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 16. TX Register 13 Field Descriptions
Bit
Field
Type
Reset
Description
TX output selection bit
7
TXOUTSEL
R/W
0h
1 = The negative output TXOUT– is active if TXMODE = 1
0 = The positive output TXOUT+ is active if TXMODE = 1
TX output mode selection bit
1 = Single-ended mode
0 = Differential mode
6
5
4
TXMODE
TXSTEP
TXSLOW
R/W
R/W
R/W
0h
0h
0h
TX output de-emphasis mode selection bit
1 = Delayed de-emphasis
0 = Normal de-emphasis
TX edge speed selection bit
1 = Slow edge speed
0 = Normal operation
3
2
1
0
TXDEADJ3
TXDEADJ2
TXDEADJ1
TXDEADJ0
R/W
R/W
R/W
R/W
0h
0h
0h
0h
TX de-emphasis setting
0000 = minimum
1111 = maximum
8.6.3.5 TX Register 14 (offset = 0000 0000) [reset = 0h]
图 55. TX Register 14
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 17. TX Register 14 Field Descriptions
Bit
7
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0h
Description
TXCPSGN
TXCPADJ6
TXCPADJ5
TXCPADJ4
TXCPADJ3
TXCPADJ2
TXCPADJ1
TXCPADJ0
TX Eye cross-point adjustment setting
TXCPSGN = 1 (positive shift)
6
0h
Maximum shift for 1111111
5
0h
Minimum shift for 0000000
TXCPSGN = 0 (negative shift)
4
0h
3
0h
Maximum shift for 1111111
Minimum shift for 0000000
2
0h
1
0h
0
0h
40
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8.6.3.6 TX Register 15 (offset = 0000 0000) [reset = 0h]
图 56. TX Register 15
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 18. TX Register 15 Field Descriptions
Bit
7
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0h
Description
TXBIAS9
TXBIAS8
TXBIAS7
TXBIAS6
TXBIAS5
TXBIAS4
TXBIAS3
TXBIAS2
Bias current settings (8MSB; 2LSBs are in register 16)
Closed loop (APC):
Coupling ratio CR = IBIAS / IPD, TXBIAS = 0..1023, IBIAS ≤ 150mA:
TXPDRNG = 00; IBIAS = 0.75μA x CR x TXBIAS
TXPDRNG = 01; IBIAS = 1.5μA x CR x TXBIAS
TXPDRNG = 1X; IBIAS = 3μA x CR x TXBIAS
6
0h
5
0 h
0h
4
3
0h
Open Loop:
IBIAS ~ 156μA x TXBIAS in source mode
IBIAS ~ 156μA x TXBIAS in sink mode
2
0h
1
0h
0
0h
8.6.3.7 TX Register 16 (offset = 0000 0000) [reset = 0h]
图 57. TX Register 16
7
6
0
5
0
4
3
2
1
0
0
0
Reserved
R/W
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 19. TX Register 16 Field Descriptions
Bit
Field
Type
Reset
Description
7
–
R/W
0h
Reserved
Digital photodiode current monitor selection bit (MONP)
6
5
TXDMONP
TXDMONB
R/W
R/W
0h
0h
1 = Digital photodiode monitor is active (no external resistor is needed)
0 = Analog photodiode monitor is active (external resistor is required)
Digital bias current monitor selection bit (MONB)
1 = Digital bias current monitor is active (no external resistor is needed)
0 = Analog bias current monitor is active (external resistor is required)
4:2
1
–
R/W
R/W
R/W
0h
0h
0h
Reserved
TXBIAS1
TXBIAS0
Bias current setting (2 LSBs)
0
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8.6.3.8 TX Register 17 (offset = 0000 0000) [reset = 0h]
图 58. TX Register 17
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 20. TX Register 17 Field Descriptions
Bit
7
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0h
Description
TXBMF7
TXBMF6
TXBMF5
TXBMF4
TXBMF3
TXBMF2
TXBMF1
TXBMF0
Bias current monitor fault threshold
With TXDMONB = 1
Register sets the value of the bias current that will trigger a fault.
The external resistor on the MONB pin must be removed to use this
feature.
6
0h
5
0h
4
0h
3
0h
2
0h
1
0h
0
0h
8.6.3.9 TX Register 18 (offset = 0000 0000) [reset = 0h]
图 59. TX Register 18
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 21. TX Register 18 Field Descriptions
Bit
7
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0h
Description
TXPMF7
TXPMF6
TXPMF5
TXPMF4
TXPMF3
TXPMF2
TXPMF1
TXPMF0
Power monitor fault threshold
With TXDMONP = 1
Register sets the value of the photodiode current that will trigger a fault.
The external resistor on the MONP pin must be removed to use this
feature.
6
0h
5
0h
4
0h
3
0h
2
0h
1
0h
0
0h
42
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ZHCSDW5A –JUNE 2015–REVISED JULY 2015
8.6.3.10 TX Register 19 (offset = 0000 0000) [reset = 0h]
图 60. TX Register 19
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 22. TX Register 19 Field Descriptions
Bit
Field
Type
Reset
Description
7
TXFD_MOD1
R/W
0
TX frequency detection mode selection
00 = auto selection enabled
01 = Pre-selected to 10.3Gbps
10 = Pre-select to 11.1Gbps
6
TXFD_MOD0
R/W
0
11 = test mode (do not use)
TX frequency detector enable bit
5
4
3
TXFD_EN
TXFD_DIS
TXFL_DIS
R/W
R/W
R/W
0
0
0
1 =TX frequency detector is always enabled
0 = TX frequency detector in automatic mode
TX frequency detector disable bit
1 = TX frequency detector is always disabled
0 = TX frequency detector is in automatic mode
TX CDR fast lock disable bit
1 = TX CDR fast lock disabled
0 = TX CDR in fast lock mode
2
1
TXDIV2
TXDIV1
R/W
R/W
0
0
TX Divider Ratio
000: Full-Rate,
001: Divide by 2
010: Divide by 4
011: Divide by 8
100: Divide by 16
101: Divide by 32
0
TXDIV0
R/W
0
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8.6.4 Reserved Registers
8.6.4.1 Reserved Registers 20-39
图 61. Reserved Registers 20-39
7
6
5
4
3
2
1
0
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 23. Reserved Registers 20-39 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
–
–
–
Reserved
44
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ZHCSDW5A –JUNE 2015–REVISED JULY 2015
8.6.5 Read Only Registers
8.6.5.1 Core Level Register 40 (offset = 0000 0000) [reset = 0h]
图 62. Core Level Register 40
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 24. Core Level Register 40 Field Descriptions
Bit
7
Field
Type
R
Reset
0h
Description
Digital representation of the ADC input source (read only)
ADC9 (MSB)
ADC8
6
R
0h
5
ADC7
R
0h
4
ADC6
R
0h
3
ADC5
R
0h
2
ADC4
R
0h
1
ADC3
R
0h
0
ADC2
R
0h
8.6.5.2 Core Level Register 41 (offset = 0000 0000) [reset = 0h]
图 63. Core Level Register 41
7
6
5
4
3
2
1
0
0
0
Reserved
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 25. Core Level Register 41 Field Descriptions
Bit
7:2
1
Field
Type
R
Reset
0h
Description
–
Reserved
ADC1
ADC0 (LSB)
R
0h
Digital representation of the ADC input source (read only)
0
R
0h
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8.6.5.3 RX Registers 42 (offset = 0000 0000) [reset = 0h]
图 64. RX Registers 42
7
0
6
0
5
0
4
0
3
2
1
0
Reserved
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; RCLR = Read clear
表 26. RX Registers 42 Field Descriptions
Bit
Field
Type
Reset
Description
RX CDR lock status bit
1 = RX CDR is not locked
0 = RX CDR is locked
7
RXCDRLock
R
0
Latched low status of bit 7. Cleared when read.
6
5
RXCDRlock (latched LOW)
RXLOS
RCLR
R
0
0
Latched low bit set to 0 when raw status goes low and keep it low even if
raw status goes high.
RX LOS status bit
1 = RX LOS asserted
0 = RX LOS de-asserted
Latched high status of RXLOS(bit5). Cleared when read.
Latched high status set to 1 when raw status goes high and keep it high
even if raw status goes low.
4
RX_LOS (latched high)
–
RCLR
R
0
0
3:0
Reserved
46
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ZHCSDW5A –JUNE 2015–REVISED JULY 2015
8.6.5.4 TX Register 43 (offset = 0000 0000) [reset = 0h]
图 65. Core Level Register 43
7
0
6
0
5
0
4
0
3
2
1
0
Reserved
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; RCLR = Read clear
表 27. TX Registers 43 Field Descriptions
Bit
Field
Type
Reset
Description
TX CDR lock status bit
1 = TX CDR is not locked
0 = TX CDR is locked
7
TXCDRLock
R
0
Latched low status of bit 7. Cleared when read.
6
5
TXCDRLock (latched Low)
TX_FLT
RCLR
R
0
0
Latched low bit set to 0 when raw status goes low and keep it low even if
raw status goes high.
TX fault status bit
1 = TX fault detected
0 = TX fault not detected
TX driver disable status bit
4
TX_DRVDIS
–
R
R
0
0
1 = TX fault logic disables the driver
0 = TX fault logic does not disable the driver
3:0
Reserved
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8.6.6 Adjustment Registers
8.6.6.1 Adjustment Registers 44-50
图 66. Adjustment Registers 44-50
7
6
5
4
3
2
1
0
Reserved
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 28. Adjustment Registers 44-50 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
–
–
–
Reserved
8.6.6.2 Adjustment Register 51 (offset = 0100 0000) [reset = 40h]
图 67. Adjustment Register 51
7
0
6
1
5
0
4
3
2
Reserved
R
1
0
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 29. Adjustment Register 51 Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
Description
SEL_RES_2
SEL_RES_1
0
1
TX and RX CDR Loop Filter Resistor
000: 75,
6
001: 150
010: 225
011: 300
100: 375
101: 450
110: 525
111: 600
Default = 225
5
SEL_RES_0
R/W
R/W
0
0
4:0
–
Reserved
48
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ZHCSDW5A –JUNE 2015–REVISED JULY 2015
9 Application Information and Implementations
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ONET1130EC is designed to be used in conjunction with a Transmitter Optical Sub-Assembly (TOSA) and a
Receiver Optical Sub-Assembly (ROSA). The ONET1130EC, TOSA, ROSA, microcontroller and power
management circuitry will typically be used in an XFP or SFP+ 10 Gbps optical transceiver. 图 68 shows the
ONET1130EC in differential mode of operation modulating a differentially driven Mach Zehnder (MZ) modulator
TOSA and 图 70 and 图 71 show the device in single-ended output mode with an Electroabsorptive Modulated
Laser (EML) TOSA. 图 70 has the photodiode cathode available and 图 71 has the photodiode anode available.
9.2 Typical Application, Transmitter Differential Mode
VCC_T
VCC
4.7kꢁ
4.7kꢁ
4.7kꢁ
to10kꢁ
to10kꢁ
to10kꢁ
0.1ꢀF
0.1ꢀF
RXOUT-
RXOUT+
2.2nF
VCC_R
TX_FLT
TX_DIS
0.1ꢀF
0.1ꢀF
VCC_RX
4.7kꢁ
to10kꢁ
LOL
RX_LOS
COMP
GND
LOS
LOL
0.01ꢀF
MONB
GND
TXIN+
TXIN-
GND
PD
MONB
0.1ꢀF
0.1ꢀF
0.1ꢀF
RXIN-
RXIN+
GND
SCK
RXIN-
RXIN+
TXIN+
TXIN-
ONET1130EC
0.1ꢀF
SCK
SDA
MONP
SDA
MONP
4.7kꢁ
to10kꢁ
4.7kꢁ
to10kꢁ
VCC
2.2nF
VDD
0.1ꢀF
VCC_TX
0.1ꢀF
0.1ꢀF
0.1ꢀF
MZ MOD+
MZ MOD-
图 68. Typical Application Circuit in Differential Mode
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Typical Application, Transmitter Differential Mode (接下页)
9.2.1 Design Requirements
表 30. Design Parameters
PARAMETER
VALUE
Supply voltage
2.5 V
Transmitter input voltage
Transmitter output voltage
Receiver input voltage
Receiver output voltage
100 mVpp to 1000 mVpp differential
1 Vpp to 3.6 Vpp differential
6 mVpp to 800 mVpp differential
300 mVpp to 900 mVpp differential
9.2.2 Detailed Design Procedure
In the transmitter differential mode of operation, the output driver is intended to be used with a differentially
driven Mach Zehnder (MZ) modulator TOSA. On the input side, the TXIN+ and TXIN- pins are required to be AC
coupled to the signal from the host system and the input voltage should be between 100 mVpp and 1000 mVpp
differential. On the output side, the TXOUT+ pin is AC coupled to the modulator positive input and the TXOUT–
pin is AC coupled to the modulator negative input. A bias-T from VCC to both the TXOUT+ and TXOUT– pins is
required to supply sufficient headroom voltage for the output driver transistors. It is recommended that the
inductance in the bias-T have low DC resistance to limit the DC voltage drop and maximize the voltage supplied
to the TXOUT+ and TXOUT– pins. If the voltage on these pins drops below approximately 2.1V then the output
rise and fall times can be adversely affected.
The receiver inputs, RXIN+ and RXIN–, are AC coupled to the output of ROSA and the input voltage should be
between 6 mVpp and 800 mVpp differential. The receiver outputs, RXOUT+ and RXOUT–, are AC coupled to the
receiver input of the host system.
9.2.3 Application Curve
图 69. Differential Mode Transmitter Output Eye Diagram
50
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ZHCSDW5A –JUNE 2015–REVISED JULY 2015
9.2.4 Typical Application, Transmitter Single-Ended Mode
VCC_T
VCC
4.7kꢁ
to10kꢁ
4.7kꢁ
to10kꢁ
4.7kꢁ
to10kꢁ
0.1ꢀF
0.1ꢀF
RXOUT-
RXOUT+
2.2nF
VCC_R
TX_FLT
TX_DIS
0.1ꢀF
0.1ꢀF
VCC_RX
4.7kꢁ
to10kꢁ
LOL
RX_LOS
LOS
LOL
0.01ꢀF
MONB
GND
TXIN+
TXIN-
GND
PD
COMP
GND
MONB
0.1ꢀF
0.1ꢀF
RXIN-
RXIN+
GND
SCK
RXIN-
RXIN+
TXIN+
TXIN-
ONET1130EC
0.1ꢀF
0.1ꢀF
PD
SCK
SDA
MONP
SDA
MONP
4.7kꢁ
to10kꢁ
4.7kꢁ
to10kꢁ
VCC
VDD
VCC_TX
0.1ꢀF
Modulator Anode
0.1ꢀF
2.2nF
0.1ꢀF
0.1ꢀF
50ꢁ
Laser
PD
PD
EA BIAS
EML TOSA
0.1ꢀF
图 70. Typical Application Circuit in Single-Ended Mode with an EML and the PD Monitor Cathode
Available
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VCC_T
VCC
4.7kꢁ to
10kꢁ
4.7kꢁ
to10kꢁ
4.7kꢁ to
10kꢁ
0.1ꢀF
RXOUT-
RXOUT+
0.1ꢀF
2.2nF
VCC_R
TX_FLT
TX_DIS
0.1ꢀF
0.1ꢀF
VCC_RX
4.7kꢁ to
10kꢁ
LOL
RX_LOS
COMP
GND
LOS
LOL
0.01ꢀF
MONB
GND
TXIN+
TXIN-
GND
PD
MONB
0.1ꢀF
0.1ꢀF
0.1ꢀF
RXIN-
RXIN+
GND
SCK
RXIN-
RXIN+
TXIN+
TXIN-
ONET1130EC
0.1ꢀF
PD
SCK
SDA
MONP
SDA
MONP
4.7kꢁ
to10kꢁ
4.7kꢁ
to10kꢁ
VCC
VDD
VCC_TX
0.1ꢀF
Modulator Anode
0.1ꢀF
PD
2.2nF
0.1ꢀF
0.1ꢀF
50ꢁ
Laser
PD
EA BIAS
EML TOSA
0.1ꢀF
-3V
图 71. Typical Application Circuit in Single-Ended Mode with an EML and the PD Monitor Anode
Available
52
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ZHCSDW5A –JUNE 2015–REVISED JULY 2015
9.2.4.1 Design Requirements
表 31. Design Parameters
PARAMETER
VALUE
Supply voltage
2.5 V
Transmitter input voltage
Transmitter output voltage
Receiver input voltage
Receiver output voltage
100 mVpp to 1000 mVpp differential
0.5 Vpp to 2 Vpp single-ended
6 mVpp to 800 mVpp differential
300 mVpp to 900 mVpp differential
9.2.4.2 Detailed Design Procedure
In the transmitter single-ended mode of operation, the output driver is intended to be used with a single-ended
driven Electroabsorptive Modulated Laser (EML) TOSA. On the input side, the TXIN+ and TXIN– pins are
required to be AC coupled to the signal from the host system and the input voltage should be between 100mVpp
and 1000mVpp differential. On the output side, it is recommended that the TXOUT+ pin is AC coupled to the
modulator input and the TXOUT– pin can be left unterminated or terminated to VCC through a 50Ω resistor. A
bias-T from VCC to the TXOUT+ pin is required to supply sufficient headroom voltage for the output driver
transistors. It is recommended that the inductance in the bias-T have low DC resistance to limit the DC voltage
drop and maximize the voltage supplied to the TXOUT+ pin. If the voltage on this pins drops below
approximately 2.1V then the output rise and fall times can be adversely affected.
The receiver inputs, RXIN+ and RXIN–, are AC coupled to the output of ROSA and the input voltage should be
between 6mVpp and 800mVpp differential. The receiver outputs, RXOUT+ and RXOUT–, are AC coupled to the
receiver input of the host system.
9.2.4.3 Application Curves
图 72. Single-Ended Mode Transmitter Output Eye Diagram
10 Power Supply Recommendations
The ONET1130EC is designed to operate from an input supply voltage range between 2.37 V and 2.63 V. To
reduce transmitter and receiver power supply coupling, as well as digital coupling into the analog circuitry, there
are separate supplies for the transmitter, receiver and digital circuitry. VCC_TX is used to supply power to the
transmitter, VCC_RX is used to supply power to the receiver and VDD is used to supply power to the digital
block. Power supply decoupling capacitors should be placed as close as possibly to the respective power supply
pins.
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11 Layout
11.1 Layout Guidelines
For optimum performance, use 50-Ω transmission lines (100-Ω differential) for connecting the high speed inputs
and outputs. The length of transmission lines should be kept as short as possible to reduce loss and pattern-
dependent jitter. It is recommended to maximize the separation of the TXOUT+ and TXOUT- transmission lines
from the RXIN+ and RXIN- transmission lines to minimize transmitter to receiver crosstalk.
If the single-ended mode of operation is being used (TXMODE = 1) then it is recommended to terminate the
unused output with a 50-Ω resistor to VCC. 图 73 shows a typical layout for the high speed inputs and outputs.
11.2 Layout Example
!/-coupling
capacitors
ÇóLb+
ÇóLb-
wóLb-
wóLb+
Crom
Iost
Crom
wh{!
ÇóhÜÇ-
.ias-Ç
Cerrites
50O to ë//
Çermination
图 73. Board Layout
54
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12 器件和文档支持
12.1 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ONET1130ECRSMR
ONET1130ECRSMT
ACTIVE
VQFN
VQFN
RSM
32
32
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 100
-40 to 100
ONET
1130EC
ACTIVE
RSM
NIPDAU
ONET
1130EC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ONET1130ECRSMR
ONET1130ECRSMT
VQFN
VQFN
RSM
RSM
32
32
3000
250
330.0
180.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ONET1130ECRSMR
ONET1130ECRSMT
VQFN
VQFN
RSM
RSM
32
32
3000
250
346.0
210.0
346.0
185.0
33.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RSM 32
4 x 4, 0.4 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224982/A
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PACKAGE OUTLINE
RSM0032B
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
B
4.1
3.9
A
0.45
0.25
0.25
0.15
PIN 1 INDEX AREA
DETAIL
OPTIONAL TERMINAL
TYPICAL
4.1
3.9
(0.1)
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2.8 0.05
2X 2.8
(0.2) TYP
4X (0.45)
28X 0.4
9
16
SEE SIDE WALL
DETAIL
8
17
EXPOSED
THERMAL PAD
2X
SYMM
33
2.8
24
0.25
32X
1
SEE TERMINAL
DETAIL
0.15
0.1
C A B
25
32
PIN 1 ID
(OPTIONAL)
0.05
SYMM
0.45
0.25
32X
4219108/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RSM0032B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.8)
SYMM
32
25
32X (0.55)
1
32X (0.2)
24
(
0.2) TYP
VIA
(1.15)
SYMM
33
(3.85)
28X (0.4)
17
8
(R0.05)
TYP
9
16
(1.15)
(3.85)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219108/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RSM0032B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.715)
4X ( 1.23)
(R0.05) TYP
25
32
32X (0.55)
1
24
32X (0.2)
(0.715)
(3.85)
33
SYMM
28X (0.4)
17
8
METAL
TYP
16
9
SYMM
(3.85)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 33:
77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219108/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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