OP07-W [TI]
精密运算放大器 | YS | 0;
| 型号： | OP07-W |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 精密运算放大器 | YS | 0 放大器 运算放大器 |
| 文件： | 总24页 (文件大小：1337K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OP07, OP07C, OP07D
ZHCSRX0H –SEPTEMBER 1983 –REVISED MARCH 2023
OP07x 精密运算放大器
1 特性
3 说明
• 低噪声
• 无需外部元件
• 以更低的成本更换斩波放大器
• 宽输入电压范围：
0V 至±14V（典型值，±15V 电源）
• 宽电源电压范围：±3V 至±18V
通过低噪声、无斩波、双极输入晶体管放大器电路，
OP07C 和 OP07D (OP07x) 器件可提供低失调电压和
长期稳定性。对于大多数应用，无需外部元件即可实现
失调电压归零和频率补偿。真差分输入连同宽输入电压
范围和出色的共模抑制能力，有助于在高噪声环境和同
相应用中提供出色的灵活性和性能。在整个温度范围
内，该类器件可维持低偏置电流和超高的输入阻抗。
2 应用
要获得更高的性能和更宽的温度范围，请参阅下一代具
有低功耗的 OPA207 和具有重容性负载驱动能力的
OPA202。
• 模拟输入模块
• 电池测试
• 实验室和现场仪表
• 温度变送器
封装信息
• 商用网络和服务器PSU
封装(1)
D（SOIC，8）
P（PDIP，8）
PS（SO，8）
封装尺寸（标称值）
4.90mm × 3.91mm
9.81mm × 6.35mm
6.20mm × 5.30mm
器件型号
OP07C、OP07D
(1) 如需了解所有可用封装和OP07，请参阅数据表末尾的可订购
产品附录。
1
3
OFFSET N1
IN+
+
6
OUT
2
8
IN−
−
OFFSET N2
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLOS099
OP07, OP07C, OP07D
ZHCSRX0H –SEPTEMBER 1983 –REVISED MARCH 2023
www.ti.com.cn
Table of Contents
7.3 Feature Description.....................................................8
7.4 Device Functional Modes............................................8
8 Application and Implementation....................................9
8.1 Application Information............................................... 9
8.2 Typical Application...................................................... 9
8.3 Power Supply Recommendations.............................10
8.4 Layout....................................................................... 12
9 Device and Documentation Support............................13
9.1 接收文档更新通知..................................................... 13
9.2 支持资源....................................................................13
9.3 Trademarks...............................................................13
9.4 静电放电警告............................................................ 13
9.5 术语表....................................................................... 13
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................7
7 Detailed Description........................................................8
7.1 Overview.....................................................................8
7.2 Functional Block Diagram...........................................8
Information.................................................................... 13
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision G (November 2014) to Revision H (July 2022)
Page
• 向宽输入电压范围特性要点添加了电源条件....................................................................................................... 1
• Changed VCC+ to V+ and VCC− to V−...............................................................................................................3
• Changed supply voltage abbreviation from VCC+ and VCC–to VS in Absolute Maximum Ratings and
throughout the data sheet...................................................................................................................................4
• Changed note 5 in Absolute Maximum Ratings to include a note that fast-ramping shorts to the positive
supply can damage the device........................................................................................................................... 4
• Changed Electrostatic discharge Human-body model and Charged-device model from 1000 V to ±1000 V.... 4
• Added new values to Thermal Information ........................................................................................................ 4
• Changed Electrical Characteristics format .........................................................................................................5
• Changed parameter name from supply-voltage sensitivity to power supply rejection ratio in Electrical
Characteristics ...................................................................................................................................................5
• Changed parameter name from input offset voltage to Input voltage noise density in Electrical Characteristics
............................................................................................................................................................................5
• Changed input current noise density unit from nV/√Hz to pA/√Hz in Electrical Characteristics ..................... 5
• Changed parameter name from large-signal differential voltage gain to open-loop voltage gain in Electrical
Characteristics ...................................................................................................................................................5
• Changed parameter name from peak output voltage to voltage output swing in Electrical Characteristics....... 5
• Changed functional block diagram..................................................................................................................... 8
• Changed text to clarify how to adjust input mismatches using null pins in Application Information ...................9
Changes from Revision F (January 2014) to Revision G (November 2014)
Page
• 添加了应用、器件信息表、引脚功能表、处理等级表、热性能信息表、典型特性、特性说明部分、器件功能
模式、应用和实施部分、电源相关建议部分、布局部分、器件和文档支持部分以及机械、封装和可订购信息
部分.................................................................................................................................................................... 1
Changes from Revision E (May 2004) to Revision F (January 2014)
Page
• 删除了订购信息 表..............................................................................................................................................1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLOS099
2
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ZHCSRX0H –SEPTEMBER 1983 –REVISED MARCH 2023
www.ti.com.cn
5 Pin Configuration and Functions
1
2
3
4
8
7
6
5
OFFSET N2
OFFSET N1
IN–
IN+
V–
–
+
V+
OUT
NC
Not to scale
图5-1. D Package, 8-Pin SOIC,
P Package, 8-Pin PDIP,
and PS Package, 8-Pin SO
(Top View)
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
IN+
NO.
3
Input
Input
Noninverting input
2
Inverting input
IN–
NC
5
Do not connect
—
OFFSET N1
OFFSET N2
OUT
1
Input
Input
Output
External input offset voltage adjustment
External input offset voltage adjustment
Output
8
6
V+
7
Positive supply
—
—
4
Negative supply
V–
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English Data Sheet: SLOS099
OP07, OP07C, OP07D
ZHCSRX0H –SEPTEMBER 1983 –REVISED MARCH 2023
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
44
UNIT
Single supply
VS
Supply voltage((2))
Input voltage
V
Dual supply
±22
±30
±22
Differential(3)
Single-ended(4)
V
Output short-circuit(5)
Continous
–55
TJ
Operating junction temperature
Storage temperature
150
150
°C
°C
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values, unless otherwise noted, are with respect to the midpoint between V+ and V−.
(3) Differential voltages are at IN+ with respect to IN−.
(4) The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
(5) The output can be shorted to ground or to the negative power supply. Fast ramping shorts to the positive supply can cause permanent
damage and eventual destruction.
6.2 ESD Ratings
VALUE
±1000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
6
NOM
MAX
36
UNIT
Single supply
Dual supply
VS = ±15 V
VS
Supply voltage
V
±3
±18
13
VCM
TA
Common-mode input voltage
Operating ambient temperature
V
–13
0
70
°C
6.4 Thermal Information
OP07x
THERMAL METRIC(1)
D (SOIC)
8 PINS
127.6
67.1
P (PDIP)
8 PINS
85
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
68.6
71.4
55..6
38.3
18.7
ψJT
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
70.6
55.2
ψJB
RθJC(bot)
—
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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English Data Sheet: SLOS099
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ZHCSRX0H –SEPTEMBER 1983 –REVISED MARCH 2023
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6.5 Electrical Characteristics
at TA = 25°C, VS = ±15 V, RL = 2 kΩ connected to mid-supply, and VCM = VOUT = mid-supply (unless otherwise noted)(1)
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
±60
±85
OP07C
TA = 0°C to 70°C
VOS
Input offset voltage
μV
±150
±250
OP07D
TA = 0°C to 70°C
OP07C
±0.5
±0.4
dVOS/dT
Input offset voltage drift
TA = 0°C to 70°C
μV/°C
OP07D
±2.5
Long-term drift of input
offset voltage(2)
µV/mo
mV
Offset adjustment range
±4
7
Rs = 20 kΩ, see 节8.1
32
51
Power supply rejection
ratio
PSRR
VS = ±3 V to ±18 V
μV/V
TA = 0°C to 70°C
10
INPUT BIAS CURRENT
±1.8
±2.2
OP07C
OP07D
TA = 0°C to 70°C
TA = 0°C to 70°C
IB
Input bias current
nA
pA/°C
nA
±12
±14
OP07C
OP07D
±18
Input bias current drift
Input offset current
±50
±0.8
±1.6
OP07C
OP07D
TA = 0°C to 70°C
TA = 0°C to 70°C
IOS
±6
±8
OP07C
OP07D
12
Input offset current drift
Input voltage noise
pA/°C
±50
NOISE
f = 0.1 Hz to 10 Hz
f = 10 Hz
0.38
10.5
10.2
9.8
μVPP
nV/√Hz
pApp
Input voltage noise
density
eN
f = 100 Hz
f = 1 kHz
Input current noise
f = 0.1 Hz to 10 Hz
f = 10 Hz
15
0.35
0.15
0.13
iN
Input current noise density f = 100 Hz
f = 1 kHz
pA/√Hz
INPUT VOLTAGE RANGE
±13
±13
100
97
±14
±13.5
120
VCM
Common-mode voltage
V
TA = 0°C to 70°C
OP07C
VCM = ±13 V
TA = 0°C to 70°C
TA = 0°C to 70°C
120
Common-mode rejection
ratio
CMRR
dB
94
110
OP07D
VCM = ±13 V
94
106
INPUT CAPACITANCE
rI
Input resistance
7
33
MΩ
OPEN-LOOP GAIN
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English Data Sheet: SLOS099
OP07, OP07C, OP07D
ZHCSRX0H –SEPTEMBER 1983 –REVISED MARCH 2023
www.ti.com.cn
6.5 Electrical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 2 kΩ connected to mid-supply, and VCM = VOUT = mid-supply (unless otherwise noted)(1)
.
PARAMETER
TEST CONDITIONS
MIN
TYP
400
400
400
MAX
UNIT
OP07C
100
1.4 V < VO < 11.4 V,
RL = 500 kΩ
OP07D
AOL
Open-loop voltage gain
V/mV
120
100
VO = ±10 V
TA = –40°C to
+125°C
400
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English Data Sheet: SLOS099
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ZHCSRX0H –SEPTEMBER 1983 –REVISED MARCH 2023
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6.5 Electrical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 2 kΩ connected to mid-supply, and VCM = VOUT = mid-supply (unless otherwise noted)(1)
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
Unity gain bandwidth
Slew rate
0.4
0.6
0.3
MHz
SR
VS = 5 V, RL = 2 kΩ
V/μs
OUTPUT
±11.5
±11
±12.8
±12.6
±13
TA = 0°C to 70°C
RL = 10 kΩ
Voltage output swing
V
±12
±12
RL = 1 kΩ
POWER SUPPLY
PD Power dissipation
No load
80
4
150
8
mW
VS = ±3 V, no load
(1) The specifications listed in the Electrical Characteristics apply to OP07C and OP07D.
(2) Because long-term drift cannot be measured on the individual devices before shipment, this specification is not intended to be a
warranty. This specification is an engineering estimate of the averaged trend line of drift versus time over extended periods after the
first 30 days of operation.
6.6 Typical Characteristics
200
Low
Mean
High
150
100
50
0
–50
–50
0
50
Temperature (ºC)
100
150
图6-1. Input-Offset Voltage vs Temperature
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English Data Sheet: SLOS099
OP07, OP07C, OP07D
ZHCSRX0H –SEPTEMBER 1983 –REVISED MARCH 2023
www.ti.com.cn
7 Detailed Description
7.1 Overview
These devices offer low offset and long-term stability by means of a low-noise, chopperless, bipolar-input-
transistor amplifier circuit. For most applications, external components are not required for offset nulling and
frequency compensation. The true differential input, with a wide input-voltage range and outstanding common-
mode rejection, provides maximum flexibility and performance in high-noise environments and in noninverting
applications. Low bias currents and extremely high input impedances are maintained over the entire temperature
range.
These devices are characterized for operation from 0°C to 70°C.
7.2 Functional Block Diagram
V+
OFFSET N1
OFFSET N2
Input Bias
Cancellation
Second Stage
Amplifier and
Biasing
OUT
IN+
IN
V
7.3 Feature Description
7.3.1 Offset-Voltage Null Capability
The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the
differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, current-
gain betas (β), collector or emitter resistors, and so on. The input offset pins allow the designer to adjust for
these mismatches by external circuitry. See 节8 for more details on design techniques.
7.3.2 Slew Rate
The slew rate is the rate at which an operational amplifier can change the output when there is a change on the
input. The OP07x have a 0.3-V/μs slew rate.
7.4 Device Functional Modes
The OP07x are powered on when the supply is connected. The devices can be operated as single-supply
operational amplifiers or dual-supply amplifiers, depending on the application.
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English Data Sheet: SLOS099
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ZHCSRX0H –SEPTEMBER 1983 –REVISED MARCH 2023
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the
differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, current-
gain betas (β), collector or emitter resistors, and so on. The input offset pins allow the designer to adjust for
these mismatches with external circuitry. 图 8-1 shows how these input mismatches can be adjusted by putting
resistors or a potentiometer between the null pins. Use a potentiometer to fine tune the circuit during testing or
for applications that require precision offset control. For more information about designing using the input-offset
pins, see the Nulling Input Offset Voltage of Operational Amplifiers application report.
20 kΩ
V+
OFFSET
N2
8
OFFSET N1
1
3
IN+
+
7
4
6
OUT
2
IN
–
V
图8-1. Input Offset-Voltage Null Circuit
8.2 Typical Application
The voltage follower configuration of the operational amplifier is used for applications where a weak signal is
used to drive a relatively high current load. This circuit is also called a buffer amplifier or unity gain amplifier. The
inputs of an operational amplifier have a very high resistance that puts a negligible current load on the voltage
source. The output resistance of the operational amplifier is almost negligible, so the amplifier can provide as
much current as necessary to the output load.
10 kꢀ
12 V
VOUT
+
VIN
图8-2. Voltage Follower Schematic
8.2.1 Design Requirements
• Output range of 2 V to 11 V
• Input range of 2 V to 11 V
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8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Swing
The output voltage of an operational amplifier is limited by the internal circuitry to some level less than the supply
rails. For this amplifier, the output voltage swing is within ±12 V, which accommodates the input and output
voltage requirements.
8.2.2.2 Supply and Input Voltage
For correct operation of the amplifier, neither input must be higher than the recommended positive supply rail
voltage or lower than the recommended negative supply rail voltage. The chosen amplifier must be able to
operate at the supply voltage that accommodates the inputs. Because the input for this application goes up to
11 V, the supply voltage must be 12 V. Using a negative voltage on the lower rail, rather than ground, allows the
amplifier to maintain linearity for inputs below 2 V.
8.2.3 Application Curves
12
10
8
0.4
0.3
0.2
0.1
6
0.0
4
œ0.1
œ0.2
œ0.3
2
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
VIN (V)
VIN (V)
C001
C002
图8-3. Output Voltage vs Input Voltage
图8-4. Current Drawn by the Input of the Voltage
Follower (IIO) vs Input Voltage
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
2
4
6
8
10
12
VIN (V)
C003
图8-5. Current Drawn from Supply (ICC) vs Input Voltage
8.3 Power Supply Recommendations
The OP07x operate from ±3 V to ±18 V supplies; many specifications apply from 0°C to 70°C.
CAUTION
Supply voltages larger than ±22 V can permanently damage the device. See also 节6.1.
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Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more details on bypass capacitor placement, see 节8.4.1.
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OP07, OP07C, OP07D
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8.4 Layout
8.4.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. On multilayer PCBs, one or more layers are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it
is not possible to keep them separate, it is much better to cross the sensitive trace perpendicularly, as
opposed to in parallel, with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in 节8.4.2.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
8.4.2 Layout Example
RIN
VIN
+
VOUT
RG
RF
图8-6. Operational Amplifier Schematic for Noninverting Configuration
Place components close to
device and to each other to
reduce parasitic errors
Run the input traces as far
away from the supply lines
as possible
RF
VS+
OFFSET N1
OFFSET N2
Use low-ESR, ceramic
bypass capacitor
RG
GND
VIN
IN−
IN+
V−
V+
OUT
NC
RIN
GND
Only needed for
dual-supply
operation
GND
VS-
(or GND for single supply)
VOUT
Ground (GND) plane on another layer
图8-7. Operational Amplifier Board Layout for Noninverting Configuration
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English Data Sheet: SLOS099
OP07, OP07C, OP07D
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www.ti.com.cn
9 Device and Documentation Support
9.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: OP07 OP07C OP07D
English Data Sheet: SLOS099
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OP-07DP
OP-07DPS
OP-07DPSR
ACTIVE
ACTIVE
ACTIVE
LIFEBUY
PDIP
SO
P
8
8
8
50
80
RoHS & Green
RoHS & Green
NIPDAU
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
0 to 70
0 to 70
0 to 70
OP-07DP
Samples
Samples
Samples
PS
PS
NIPDAU
NIPDAU
OP-07D
OP-07D
OP-07D
SO
2000 RoHS & Green
OP-07DPSRG4
OP07-W
SO
PS
YS
8
0
2000 RoHS & Green
NIPDAU
Call TI
Level-1-260C-UNLIM
Call TI
ACTIVE WAFERSALE
3603
75
TBD
Samples
Samples
Samples
Samples
Samples
OP07CD
OP07CDE4
OP07CDG4
OP07CDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
0 to 70
0 to 70
0 to 70
OP07C
OP07C
OP07C
OP07C
75
75
NIPDAU
2500 RoHS & Green
NIPDAU | SN
OP07CDRE4
OP07CDRG4
OP07CP
LIFEBUY
LIFEBUY
ACTIVE
SOIC
SOIC
PDIP
D
D
P
8
8
8
2500 RoHS & Green
2500 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
0 to 70
OP07C
OP07C
OP07CP
50
RoHS & Green
Samples
OP07CPE4
OP07DD
LIFEBUY
ACTIVE
PDIP
SOIC
P
D
8
8
50
75
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
N / A for Pkg Type
0 to 70
0 to 70
OP07CP
OP07D
Level-1-260C-UNLIM
Samples
Samples
OP07DDR
ACTIVE
SOIC
D
8
2500 RoHS & Green
2500 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
OP07D
OP07DDRE4
OP07DP
LIFEBUY
ACTIVE
SOIC
PDIP
D
P
8
8
NIPDAU
NIPDAU
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
OP07D
50
RoHS & Green
OP07DP
Samples
Samples
OP07DPE4
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
OP07DP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OP-07DPSR
OP07CDR
SO
PS
D
8
8
8
8
2000
2500
2500
2500
330.0
330.0
330.0
330.0
16.4
12.4
12.4
12.4
8.35
6.4
6.4
6.4
6.6
5.2
5.2
5.2
2.4
2.1
2.1
2.1
12.0
8.0
8.0
8.0
16.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
SOIC
SOIC
SOIC
OP07CDRG4
OP07DDR
D
D
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OP-07DPSR
OP07CDR
SO
PS
D
8
8
8
8
2000
2500
2500
2500
356.0
340.5
340.5
340.5
356.0
336.1
336.1
336.1
35.0
25.0
25.0
25.0
SOIC
SOIC
SOIC
OP07CDRG4
OP07DDR
D
D
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Apr-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
OP-07DP
OP-07DPS
OP07CD
P
PS
D
D
D
P
PDIP
SOP
8
8
8
8
8
8
8
8
8
8
8
8
50
80
75
75
75
50
50
50
50
75
50
50
506
530
507
507
507
506
506
506
506
507
506
506
13.97
10.5
8
11230
4000
4.32
4.1
SOIC
SOIC
SOIC
PDIP
PDIP
PDIP
PDIP
SOIC
PDIP
PDIP
3940
4.32
4.32
4.32
4.32
4.32
4.32
4.32
4.32
4.32
4.32
OP07CDE4
OP07CDG4
OP07CP
8
3940
8
3940
13.97
13.97
13.97
13.97
8
11230
11230
11230
11230
3940
OP07CP
P
OP07CPE4
OP07CPE4
OP07DD
P
P
D
P
OP07DP
13.97
13.97
11230
11230
OP07DPE4
P
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
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这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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