OPA121KU/2K5 [TI]
OPERATIONAL AMPLIFIER;
| 型号： | OPA121KU/2K5 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OPERATIONAL AMPLIFIER 放大器 光电二极管 |
| 文件： | 总10页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
OPA121
Low Cost Precision Difet®
OPERATIONAL AMPLIFIER
FEATURES
APPLICATIONS
● LOW NOISE: 6nV/√Hz typ at 10kHz
● LOW BIAS CURRENT: 5pA max
● LOW OFFSET: 2mV max
● OPTOELECTRONICS
● DATA ACQUISITION
● TEST EQUIPMENT
● LOW DRIFT: 3µV/°C typ
● MEDICAL EQUIPMENT
● HIGH OPEN-LOOP GAIN: 110dB min
● RADIATION HARD EQUIPMENT
● HIGH COMMON-MODE
REJECTION: 86dB min
Case (TO-99) and Substrate
8
DESCRIPTION
7
The OPA121 is a precision monolithic dielectrically-
isolated FET (Difet®) operational amplifier. Out-
standing performance characteristics are now
available for low-cost applications.
+V
CC
–In
2
Noise, bias current, voltage offset, drift, open-loop
gain, common-mode rejection, and power supply
rejection are superior to BIFET® amplifiers.
3
Noise-Free
Cascode*
+In
Very low bias current is obtained by dielectric
isolation with on-chip guarding.
6
Output
Laser-trimming of thin-film resistors gives very low
offset and drift. Extremely low noise is achieved with
new circuit design techniques (patented). A new
cascode design allows high precision input specifica-
tions and reduced susceptibility to flicker noise.
2kΩ
2kΩ
2kΩ
2kΩ
Trim
1
10kΩ
10kΩ
5
Trim
Standard 741 pin configuration allows upgrading of
existing designs to higher performance levels.
4
–V
*Patented
CC
OPA121 Simplified Circuit
Difet®, Burr-Brown Corp.
BIFET®, National Semiconductor Corp.
International Airport Industrial Park
•
Mailing Address: PO Box 11400
Cable: BBRCORP
•
Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd.
•
Tucson, AZ 85706
Tel: (520) 746-1111 Twx: 910-952-1111
•
•
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
© 1984 Burr-Brown Corporation
PDS-539F
Printed in U.S.A. September, 1993
SBOS139
SPECIFICATIONS
ELECTRICAL
At VCC = ±15VDC and TA = +25°C unless otherwise noted. Pin 8 connected to ground.
OPA121KM
OPA121KP, KU
TYP
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
INPUT
NOISE
Voltage, fO = 10Hz
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
40
15
8
50
18
10
7
0.8
2
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
µVrms
µVp-p
f
f
f
f
f
O = 100Hz
O = 1kHz
O = 10kHz
B = 10Hz to 10kHz
B = 0.1Hz to 10 Hz
6
0.7
1.6
15
0.8
Current, fB = 0.1Hz to 10Hz
O = 0.1Hz thru 20kHz
21
1.1
fA, p-p
fA/√Hz
f
OFFSET VOLTAGE(2)
Input Offset Voltage
Average Drift
VCM = 0VDC
A = TMIN to TMAX
±0.5
±3
104
±6
±2
±10
±0.5
±3
104
±6
±3
±10
mV
µV/°C
dB
T
Supply Rejection
86
86
±50
±5
±50
±10
µV/V
BIAS CURRENT(2)
Input Bias Current
VCM = 0VDC
Device Operating
±1
±1
pA
pA
OFFSET CURRENT(2)
Input Offset Current
VCM = 0VDC
±0.7
±4
±0.7
±8
Device Operating
IMPEDANCE
Differential
Common-Mode
1013 || 1
1014 || 3
1013 || 1
1014 || 3
Ω || pF
Ω || pF
VOLTAGE RANGE
Common-Mode Input Range
Common-Mode Rejection
±10
86
±11
104
±10
82
±11
100
V
dB
V
IN = ±10VDC
OPEN-LOOP GAIN, DC
Open-Loop Voltage Gain
R
L ≥ 2kΩ
110
120
106
114
dB
FREQUENCY RESPONSE
Unity Gain, Small Signal
Full Power Response
Slew Rate
Settling Time, 0.1%
0.01%
2
32
2
6
10
2
32
2
6
10
MHz
kHz
V/µs
µs
20Vp-p, RL = 2kΩ
O = ±10V, RL = 2kΩ
Gain = –1, RL = 2kΩ
V
10V Step
µs
Overload Recovery,
50% Overdrive(3)
Gain = –1
5
5
µs
RATED OUTPUT
Voltage Output
Current Output
Output Resistance
Load Capacitance Stability
Short Circuit Current
RL = 2kΩ
O = ±10VDC
DC, Open Loop
Gain = +1
±11
±5.5
±12
±10
100
1000
40
±11
±5.5
±12
±10
100
1000
40
V
mA
Ω
pF
mA
V
10
10
POWER SUPPLY
Rated Voltage
±15
±15
VDC
Voltage Range,
Derated Performance
Current, Quiescent
±5
±18
4
±5
±18
4.5
VDC
mA
IO = 0mADC
2.5
2.5
TEMPERATURE RANGE
Specification
Operating
Storage
θ Junction-Ambient
Ambient Temperature
Ambient Temperature
Ambient Temperature
0
–40
–65
+70
+85
+150
0
–25
–55
+70
+85
+125
°C
°C
°C
200
150(4)
°C/W
NOTES: (1) Sample tested. (2) Offset voltage, offset current, and bias current are specified with the units fully warmed up. (3) Overload recovery is defined as
the time required for the output to return from saturation to linear operation following the removal of a 50% input overdrive. (4) 100°C/W for KU grade.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
2
OPA121
ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS)
At VCC = ±15VDC and TA = TMIN to TMAX unless otherwise noted.
OPA121KM
OPA121KP, KU
TYP
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
TEMPERATURE RANGE
Specification Range
Ambient Temperature
0
+70
0
+70
°C
INPUT
OFFSET VOLTAGE(1)
Input Offset Voltage
Average Drift
VCM = 0VDC
±1
±3
94
±3
±10
±1
±3
94
±5
±10
mV
µV/°C
dB
Supply Rejection
82
82
±20
±80
±20
±80
µV/V
BIAS CURRENT(1)
Input Bias Current
VCM = 0VDC
Device Operating
±23
±16
±115
±23
±16
±250
pA
pA
OFFSET CURRENT(1)
Input Offset Current
VCM = 0VDC
±100
±200
Device Operating
VOLTAGE RANGE
Common-Mode Input Range
Common-Mode Rejection
±10
82
±11
98
±10
80
±11
96
V
dB
VIN = ±10VDC
OPEN-LOOP GAIN, DC
Open-Loop Voltage Gain
RL ≥ 2kΩ
106
116
100
110
dB
RATED OUTPUT
Voltage Output
Current Output
RL = 2kΩ
O = ±10VDC
VO = 0VDC
±10.5
±5.25
10
±11
±10
40
±10.5
±5.25
10
±11
±10
40
V
mA
mA
V
Short Circuit Current
POWER SUPPLY
Current, Quiescent
IO = 0mADC
2.5
4.5
2.5
5
mA
NOTE: (1) Offset voltage, offset current, and bias current are measured with the units fully warmed up.
ABSOLUTE MAXIMUM RATINGS
CONNECTION DIAGRAMS
Top View
M-Package TO-99 (Hermetic)
Supply ........................................................................................... ±18VDC
Internal Power Dissipation(1) ......................................................... 500mW
Differential Input Voltage ............................................................... ±36VDC
Input Voltage Range ..................................................................... ±18VDC
Storage Temperature Range
M package .................................................................... –65°C to +150°C
P, U packages............................................................... –55°C to +125°C
Operating Temperature Range
Substrate and Case
8
Offset
Trim
+VCC
1
3
7
–In
2
OPA121
6
Output
M package ...................................................................... –40°C to +85°C
P, U packages................................................................. –25°C to +85°C
Offset
Trim
5
Lead Temperature
+In
M, P packages (soldering, 10s) ................................................... +300°C
U package (soldering, 3s) ........................................................... +260°C
Output Short-Circuit Duration(2) ............................................... Continuous
Junction Temperature .................................................................... +175°C
4
–VCC
NOTES: (1) Packages must be derated based on θJA = 150°C/W
(P package); θJA = 200°C/W (M package); θJA = 100°C/W (U package).
(2) Short circuit may be to power supply common only. Rating applies to
+25°C ambient. Observe dissipation limit and TJ.
Top View
P-Package Plastic Mini-DIP
U-Package Plastic SOIC
Offset Trim
1
2
3
4
8
7
6
5
Substrate
+VCC
PACKAGE INFORMATION
–In
+In
PACKAGE DRAWING
OPA121
MODEL
PACKAGE
NUMBER(1)
Output
OPA121KM
OPA121KP
OPA121KU
TO-99
8-Pin Plastic DIP
8-Pin SOIC
001
006
182
–VCC
Offset Trim
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
ORDERING INFORMATION
TEMPERATURE
MODEL
PACKAGE
RANGE
OPA121KM
OPA121KP
OPA121KU
TO-99
8-Pin Plastic DIP
8-Pin SOIC
0°C to +70°C
0°C to +70°C
0°C to +70°C
®
3
OPA121
TYPICAL PERFORMANCE CURVES
TA = +25°C, VCC = ±15VDC unless otherwise noted.
BIAS AND OFFSET CURRENT
vs TEMPERATURE
INPUT VOLTAGE NOISE SPECTRAL DENSITY
1k
1k
100
10
1k
100
10
1
KM
KP, KU
100
1
KM
10
0.1
0.1
1
0.01
0.01
1
10
100
1k
10k
100k
1M
–50
–25
0
+25
+50
+75
+100
+125
Frequency (Hz)
Ambient Temperature (°C)
POWER SUPPLY REJECTION
vs FREQUENCY
BIAS AND OFFSET CURRENT
vs INPUT COMMON-MODE VOLTAGE
140
120
100
80
10
1
10
1
Bias Current
Offset Current
60
KM
0.1
0.1
40
20
0
0.01
0.01
1
10
100
1k
10k
100k
1M
10M
–15
–10
–5
0
+5
+10
+15
Frequency (Hz)
Common-Mode Voltage (V)
COMMON-MODE REJECTION
vs FREQUENCY
OPEN-LOOP FREQUENCY RESPONSE
KM
140
120
100
80
140
120
100
80
KM
–45
Gain
Ø
–90
60
60
Phase
Margin
65°
–135
–180
40
40
20
0
20
0
1
10
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
®
4
OPA121
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, VCC = ±15VDC unless otherwise noted.
SMALL SIGNAL TRANSIENT RESPONSE
LARGE SIGNAL TRANSIENT RESPONSE
+80
+15
+40
0
0
+40
-15
+80
0
1
2
3
4
5
0
25
50
Time(µs)
Time(µs)
INPUT CURRENTS vs INPUT VOLTAGE
WITH ±VCC PINS GROUNDED
+2
+1
0
Maximum Safe Current
I
IN
V
–1
–2
Maximum Safe Current
–15
–10
–5
0
+5
+10
+15
Input Voltage (V)
+V
APPLICATIONS INFORMATION
CC
OFFSET VOLTAGE ADJUSTMENT
7
2
3
The OPA121 offset voltage is laser-trimmed and will require
no further trim for most applications. As with most ampli-
fiers, externally trimming the remaining offset can change
drift performance by about 0.3µV/°C for each 100µV of
adjusted offset. Note that the trim (Figure 1) is similar to
operational amplifiers such as 741 and AD547. The OPA121
can replace most BIFET amplifiers by leaving the external
null circuit unconnected.
6
1
OPA121
5
4
±10mV Typical
Trim Range
*
*10kΩ to 1MΩ
Trim Potentiometer
(100kΩ Recommended)
–V
CC
FIGURE 1. Offset Voltage Trim.
INPUT PROTECTION
Conventional monolithic FET operational amplifiers require
external current-limiting resistors to protect their inputs
against destructive currents that can flow when input FET
gate-to-substrate isolation diodes are forward-biased. Most
than 6V more negative than –VCC. A 10kΩ series resistor
will limit input current to a safe level with up to ±15V input
levels even if both supply voltages are lost.
BIFET amplifiers can be destroyed by the loss of –VCC
.
Static damage can cause subtle changes in amplifier input
characteristics without necessarily destroying the device. In
precision operational amplifiers (both bipolar and FET types),
Unlike BIFET amplifiers, the Difet OPA121 requires input
current limiting resistors only if its input voltage is greater
®
5
OPA121
this may cause a noticeable degradation of offset voltage and
drift.
Non-Inverting
Buffer
8
Static protection is recommended when handling any
precision IC operational amplifier.
8
2
2
Out
Out
6
6
OPA121
OPA121
GUARDING AND SHIELDING
3
3
In
In
As in any situation where high impedances are involved,
careful shielding is required to reduce “hum” pickup in input
leads. If large feedback resistors are used, they should also
be shielded along with the external input circuitry.
Inverting
TO-99 Bottom View
5
In
Leakage currents across printed circuit boards can easily
exceed the bias current of the OPA121. To avoid leakage
problems, it is recommended that the signal input lead of the
OPA121 be wired to a Teflon™ standoff. If the OPA121 is
to be soldered directly into a printed circuit board, utmost
care must be used in planning the board layout. A “guard”
pattern should completely surround the high-impedance in-
put leads and should be connected to a low-impedance point
which is at the signal input potential.
4
6
7
3
2
2
3
Out
6
OPA121
8
8
1
Mini-DIP Bottom View
1
8
7
6
5
BOARD LAYOUT
FOR INPUT GUARDING
Guard top and bottom of board.
Alternate: use Teflon standoff
for sensitive input pins.
The amplifier case should be connected to any input shield
or guard via pin 8. This insures that the amplifier itself is
fully surrounded by guard potential, minimizing both leak-
age and noise pickup (see Figure #2).
2
3
4
If guarding is not required, pin 8 (case) should be connected
to ground.
FIGURE 2. Connection of Input Guard.
BIAS CURRENT CHANGE
VERSUS COMMON-MODE VOLTAGE
80
LF156/157
AD547
T = +25°C; curves taken from
mfg. published typical data
60
A
70
The input bias currents of most popular BIFET operational
amplifiers are affected by common-mode voltage (Figure 3).
Higher input FET gate-to-drain voltage causes leakage and
ionization (bias) currents to increase. Due to its cascode
input stage, the extremely-low bias current of the OPA121
is not compromised by common-mode voltage.
50
40
LF155
LF156/157
30
20
LF155
AD547
OPA121
10
0
OPA121
–10
–20
OP-15/16/17 "Perfect Bias Current Cancellation"
Teflon™ E.I. du Pont de Nemours & Co.
–10
–5
0
+5
+10
Common-Mode Voltage (VDC)
FIGURE 3. Input Bias Current vs Common-Mode Voltage.
®
6
OPA121
PACKAGE OPTION ADDENDUM
www.ti.com
12-Feb-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
TO-99
TO-99
PDIP
PDIP
SOIC
Drawing
OPA121KM
OPA121KM3
OPA121KP
OPA121KP4
OPA121KU
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
ACTIVE
LMC
LMC
P
8
8
8
8
8
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
P
D
75 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
OPA121KU/2K5
OPA121KU/2K5G4
OPA121KUE4
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
D
D
D
8
8
8
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
OPA121KU/2K5
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 29.0
OPA121KU/2K5
D
8
2500
Pack Materials-Page 2
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