OPA1633 [TI]
超低失真、195MHz、全差分音频放大器;
| 型号： | OPA1633 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 超低失真、195MHz、全差分音频放大器 放大器 音频放大器 |
| 文件： | 总29页 (文件大小：1905K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA1633
ZHCSRO1 –FEBRUARY 2023
OPA1633 高性能、全差分音频运算放大器
1 特性
3 说明
• 出色音质
OPA1633 是一款全差分放大器，旨在驱动高性能音频
模数转换器 (ADC) 或用作 D 类放大器的前置驱动器。
它可实现卓越的音频质量、极低的噪声、大输出电压摆
幅和高电流驱动。OPA1633 具有 200MHz 的出色增益
带宽以及 80V/μs 的超快压摆率，可实现极低的失
真。非常低的输入电压噪声 1.1nV/√Hz 可进一步确保
更大信噪比和动态范围。
• 超低失真：0.000026%
• 低噪声：1.1nV/√Hz
• 高速：
– 压摆率：80V/μs
– 增益带宽积：200 MHz
• 完全差分架构：
– 平衡输入和输出将单端输入转换为平衡差分输出
• 宽电源电压范围：±2.5V 至±17.5V
• 关断电流：0.77 mA (VS = ± 5V)
全差分架构的灵活性有助于轻松实现单端到全差分输出
转换。差分输出可减少偶次谐波并最大限度地减少共模
噪声干扰。OPA1633 在用于驱动高性能音频ADC（如
PCM1804）时可提供卓越的性能。添加了关断功能以
在器件未使用时节省电量。
• 温度范围：–40°C 至+85°C
2 应用
OPA1633 可在 –40°C 至 +85°C 的温度范围内正常运
行， 采用 SO-8 封装和散热增强型 MSOP-8
PowerPAD™ 封装。
• 专业音频混合器或控制平面
• 专业麦克风和无线系统
• 专业扬声器系统
• 专业音频放大器
• 条形音箱
• 转盘
• 专业摄像机
• 吉他和其他乐器放大器
• 数据采集(DAQ)
• 引脚兼容型升级至OPA1632
封装信息(1)
封装尺寸（标称值）
器件型号
OPA1633
封装
D（SOIC，8）
4.90mm × 3.91mm
DGN（HVSSOP，8） 3.00mm × 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
.
1E-3
RL = 600
RL = 2 k
1E-4
1E-5
10
100
1k
10k
100k
Frequency (Hz)
THD+N 与频率间的关系
应用示意图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOSAC7
OPA1633
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Table of Contents
8.1 Application Information............................................. 12
8.2 Typical Application.................................................... 13
8.3 Power Supply Recommendations.............................14
8.4 Layout....................................................................... 15
9 Device and Documentation Support............................18
9.1 Documentation Support............................................ 18
9.2 第三方产品免责声明..................................................18
9.3 接收文档更新通知..................................................... 18
9.4 支持资源....................................................................18
9.5 Trademarks...............................................................18
9.6 静电放电警告............................................................ 18
9.7 Export Control Notice................................................18
9.8 术语表....................................................................... 19
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Typical Characteristics................................................8
7 Detailed Description......................................................10
7.1 Overview...................................................................10
7.2 Functional Block Diagram.........................................10
7.3 Feature Description...................................................10
7.4 Device Functional Modes..........................................11
8 Application and Implementation..................................12
Information.................................................................... 19
10.1 Mechanical Data..................................................... 20
10.2 Tape and Reel Information......................................23
4 Revision History
DATE
REVISION
NOTES
February 2023
*
Initial Release
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5 Pin Configuration and Functions
VIN-
VIN+
1
2
3
4
8
7
6
5
VOCM
Enable
V+
V-
VOUT+
VOUT-
图5-1. D or DGN(1) Package,
8-Pin SOIC or HVSSOP
(Top View)
表5-1. Pin Functions
PIN
TYPE(2)
DESCRIPTION
NAME
Enable
V+
NO.
7
I
I/O
I/O
I
Active high enable pin
3
Positive supply voltage pin
Negative supply voltage pin
Positive input voltage pin
V-
6
VIN+
8
VIN-
1
I
Negative input voltage pin
Output common-mode control voltage pin
Positive output voltage pin
Negative output voltage pin
VOCM
VOUT+
VOUT-
2
I
4
O
O
5
(1) Solder the exposed DGN package thermal pad to a heat-spreading power or ground plane. This pad is electrically isolated from the
die, but must be connected to a power or ground plane and not floated.
(2) I = input, O = output.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
±18.5
1.7
UNIT
±VS
Supply Voltage
V
V/µs
V
Supply turn-on/off dV/dT(3)
VI
Input Voltage
±VS
150
10
IO
Output Current
mA
V
IIN
VID
TJ
Continuous Input Current
Differential Input Voltage
Maximum Junction Temperature
Operating Free-Air Temperature Range
Storage Temperature Range
±1.5
150
85
–40
–65
°C
TSTG
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
(2) The OPA1633 MSOP-8 package version incorporates a PowerPAD on the underside of the chip. This acts as a heatsink and must be
connected to a thermally-dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction
temperature, which can permanently damage the device. See TI technical brief SLMA002 for more information about using the
PowerPAD thermally-enhanced package.
(3) Staying below this specification ensures that the edge-triggered ESD absorption devices across the supply pins remain off.
6.2 ESD Ratings
VALUE
±2000
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
±17.5
35
UNIT
Dual
±2
4
V
Supply voltage (V+ –V-)
Single
C-suffix
I-suffix
0
70
TA
°C
-40
85
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6.4 Thermal Information
OPA1633
THERMAL METRIC(1)
D (SOIC)
8 PINS
126.3
67.3
DGN (MSOP-PowerPAD)
UNIT
8 PINS
57.3
82.9
29.7
6.3
RθJA
RθJC(top)
RθJB
69.8
°C/W
19.5
ψJT
69.0
29.7
13.9
ψJB
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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MAX UNIT
6.5 Electrical Characteristics
VS = ±15 V; RF = 390 Ω, RL = 800 Ω, and G = +1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Offset Voltage
0.2
2
mV
Input Offset
Voltage
vs temperature, dc
vs Power Supply, dc
dVOS/dT
PSRR
±0.6
μV/°C
13
100
μV/V
Input Bias Current
Input Bias Current IB
Input Offset
6.8
11.5
μA
IOS
±20
±400
nA
Current
Noise
Input Voltage Noise
Input Current Noise
Input Voltage
1.1
1.3
nV/√Hz
pA/√Hz
f = 10 kHz
(V−) +
Common-Mode Input Range
V
(V+) − 1
1.5
Common-Mode Rejection Ratio, dc
80
100
dB
Input Impedance
Measured into each input terminal,
common-mode
MΩ||
pF
320 || 1.3
12 || 2.3
Input Impedance
Measured into each input terminal,
differential
kΩ|| pF
Open-Loop Gain
Open-Loop Gain, dc
Frequency Response
91
97
dB
200
G = +1, RF= 348 Ω
G = +2, RF = 602 Ω
G = +5, RF = 1.5 kΩ
G = +10, RF = 3.01 kΩ
G = +1, VO = 100 mVPP
VO = 100 mVPP
117
Small-Signal
Bandwidth
MHz
(VO = 100mVPP, Peaking < 0.5 dB)
53
26
Bandwidth for 0.1dB Flatness
40
MHz
dB
Peaking at a Gain of 1
Large-Signal Bandwidth
Slew Rate (25% to 75% )
Rise and Fall Time
0.25
G = +2, VO = 20 VPP
G = +1
3
MHz
V/μs
80
G = +1, VO = 5-V Step
62
0.1%
Settling Time to
0.01%
30
ns
G = +1, VO = 2-V Step
40
0.000028%
0.000026%
0.000028%
0.000026%
0.000054%
0.000054%
0.000057%
0.000054%
40
RL = 600 Ω
Differential Input/Output
RL = 2 kΩ
RL = 600 Ω
RL = 2 kΩ
RL = 600 Ω
RL = 2 kΩ
RL = 600 Ω
RL = 2 kΩ
Total Harmonic
Distortion + Noise
G = +1, f = 1
kHz, VO = 3 VRMS
Single-Ended In/Differential Out
Differential Input/Output
Intermodulation
Distortion
G = +1, SMPTE/DIN,
VO = 2 VPP
Single-Ended In/Differential Out
Headroom
VPP
THD < 0.01%, RL = 2 kΩ
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6.5 Electrical Characteristics (continued)
VS = ±15 V; RF = 390 Ω, RL = 800 Ω, and G = +1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Output
(V+) −
(V−) +
V
Voltage Output Swing
RL = 1 kΩ
1.9
1.9
Output Current
IO
65
85
mA
Closed-Loop Output Impedance
G = +1, f = 100 kHz
0.1
Ω
Power-Down(1)
(V−) +
Enable Voltage Threshold
Disable Voltage Threshold
(V−) + 1.45
(V−) + 1.4
1.5
V
(V−) +
0.8
0.77
1.4
VS = ±5 V, VENABLE = −5 V
VENABLE = −15 V
Shutdown Current
mA
Turn-On Delay
0.12
0.03
Time for IQ to Reach 50%
μs
Turn-Off Delay
Power Supply
Quiescent Current IQ
11
13.2
mA
(1) Amplifier has internal 250-kΩ pull-up resistor to V+ pin. This enables the amplifier with no connection to shutdown pin.
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6.6 Typical Characteristics
at TA = 25°C, VS = ±15 V, RF = 348 Ω, G = +1 and RL = 2 kΩ(unless otherwise noted)
1E-3
RL = 600
RL = 2 k
1E-4
1E-5
10
100
1k
10k
100k
Frequency (Hz)
VO = 3 VRMS; Differential Input and Output
VO = 3 VRMS; Single-ended Input to Differential Output
图6-1. THD + Noise vs Frequency
图6-2. THD + Noise vs Frequency
1E-1
1E-1
1E-2
1E-3
1E-4
1E-5
RL = 600
RL = 2 k
RL = 600
RL = 2 k
1E-2
1E-3
1E-4
1E-5
10m
100m
1
10
100
10m
100m
1
10
100
Differential Output Voltage (VRMS
)
Differential Output Voltage (VRMS
)
f = 1 kHz; Differential Input and Output
f = 1 kHz; Single-ended Input to Differential Output
图6-3. THD + Noise vs Output Voltage
图6-4. THD + Noise vs Output Voltage
1E-2
1E-3
1E-4
1E-5
1E-2
1E-3
1E-4
1E-5
RL = 600
RL = 2 k
RL = 600
RL = 2 k
10m
100m
1
10
100
10m
100m
1
10
100
Differential Output Voltage (Vpp
)
Differential Output Voltage (Vpp
)
SMPTE 4:1: 60 Hz, 7 kHz; DIN 4:1: 250 Hz, 8 kHz; Differential
Input and Output
SMPTE 4:1: 60 Hz, 7 kHz; DIN 4:1: 250 Hz, 8 kHz; Differential
Input and Output
图6-5. Intermodulation Distortion vs Output Voltage
图6-6. Intermodulation Distortion vs Output Voltage
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RF = 348 Ω, G = +1 and RL = 2 kΩ(unless otherwise noted)
10
10
1
10
1
10
100
1k
10k
100k
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
.
.
图6-7. Voltage Noise vs Frequency
图6-8. Current Noise vs Frequency
15
10
5
100
10
1
Vcc = 5 V
Vcc = 15 V
0
-5
-10
-15
0.1
100k
100
1k
10k
100k
1M
10M
100M
1G
RL ()
Frequency (Hz)
.
RF= 1 kΩ; G = +2
图6-10. Output Impedance vs Frequency
图6-9. Output Voltage vs Differential Load Resistance
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7 Detailed Description
7.1 Overview
7.1.1 Fully-Differential Amplifiers
The OPA1633 is a fully differential amplifier (FDA). Differential signal processing offers a number of performance
advantages in high-speed analog signal processing systems, including immunity to external common-mode
noise, suppression of even-order non-linearities, and increased dynamic range. FDAs not only serve as the
primary means of providing gain to a differential signal chain, but also provide a monolithic solution for
converting single-ended signals into differential signals allowing for easy, high-performance processing. For
more information on the basic theory of operation for FDAs, refer to the Fully Differential Amplifiers application
note.
7.2 Functional Block Diagram
V+
Output Buffer
V
IN−
x1
V
OUT+
C
R
R
V
IN+
Vcm Error
+
_
C
x1
V
OUT−
Output Buffer
V+
30 kW
V−
30 kW
V−
V
OCM
7.3 Feature Description
图 7-1 and 图 7-2 depict the differences between the operation of the OPA1633 in two different modes. FDAs
can work with differential input or can be implemented as single in/differential out.
RG
RG
RF
V+
RF
V+
VSource
–
+
–
+
VOUT+
VOUT-
VOUT+
VOUT-
+
–
+
–
VOCM
VSource
VOCM
V-
RF
V-
RF
RG
RG
图7-2. Amplifying Single-ended Input Signals
图7-1. Amplifying Differential Input Signals
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7.4 Device Functional Modes
7.4.1 Shutdown Function
The shutdown (enable) function of the OPA1633 is referenced to the negative supply of the operational amplifier.
A valid logic low (< 0.8 V above negative supply) applied to the enable pin (pin 7) disables the amplifier output.
Voltages applied to pin 7 that are greater than 2 V above the negative supply place the amplifier output in an
active state, and the device is enabled. If pin 7 is left disconnected, an internal pull-up resistor enables the
device. Turn-on and turn-off times are approximately 2 μs each.
Quiescent current is reduced to approximately 0.77 mA when the amplifier is disabled. When disabled, the
output stage is not in a high-impedance state. Thus, the shutdown function cannot be used to create a
multiplexed switching function in series with multiple amplifiers.
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8 Application and Implementation
备注
以下应用部分中的信息不属于 TI 元件规格，TI 不担保其准确性和完整性。TI 的客户负责确定元件是否
适合其用途，以及验证和测试其设计实现以确认系统功能。
8.1 Application Information
8.1.1 Output Common-Mode Voltage
The output common-mode voltage pin sets the dc output voltage of the OPA1633. A voltage applied to the VOCM
pin from a low-impedance source can be used to directly set the output common-mode voltage. If the VOCM pin
is left floating it defaults to the mid-rail voltage, defined as:
V
+ V
+
−
(1)
2
To minimize common-mode noise, connect a 0.1-uF bypass capacitor to the VOCM pin. Output common-mode
voltage causes additional current to flow in the feedback resistor network. Since this current is supplied by the
output stage of the amplifier, this creates additional power dissipation. For commonly-used feedback resistance
values, this current is easily supplied by the amplifier. The additional internal power dissipation created by this
current may be significant in some applications and may dictate use of the MSOP PowerPAD package to
effectively control self-heating.
8.1.1.1 Resistor Matching
Resistor matching is important in FDAs to maintain good output balance. An ideal differential output signal
implies the two outputs of the FDA should be exactly equal in amplitude and shifted 180° in phase. Any
imbalance in amplitude or phase between the two output signals results in an undesirable common-mode signal
at the output. The output balance error is a measure of how well the outputs are balanced and is defined as the
ratio of the output common-mode voltage to the output differential signal.
V
− V
2
OUT +
OUT +
OUT −
Output Balance Error =
(2)
V
− V
OUT −
At low frequencies, resistor mismatch is the primary contributor to output balance errors. Additionally CMRR,
PSRR, and HD2 performance diminish if resistor mismatch occurs. Therefore, it is recommended to use 1%
tolerance resistors or better to optimize performance. 表 8-1 provides the recommended resistor values to use
for a particular gain.
表8-1. Recommended Resistor Values
Gain (V/V)
RG (Ω)
RF (Ω)
390
1
2
390
374
750
5
402
2010
4020
10
402
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8.2 Typical Application
图8-1 shows the OPA1633 used as a differential-output driver for the PCM1804 high-performance audio ADC.
V+
10mF
+
0.1mF
R3
270W
C1
1nF
R1
R5
1kW
3
40W
8
2
1
5
+
Balanced or
Single- Ended
Input
VOCM
C3
1/2
R2
OPA1633
2.7nF
PCM1804
1kW
-
4
6
R6
VCOM
(2.5V)
C2
1nF
7
40W
R4
270W
Enable(1)
OPA134
1kW
0.1mF
0.1mF
10mF
+
V-
图8-1. ADC Driver for Professional Audio
8.2.1 Design Requirements
表 8-2 provides example design parameters and values for the typical application design example shown in 图
7-1.
表8-2. Design Parameters
DESIGN PARAMETERS
VALUE
Supply voltage
±2.5 V to ±17.5 V
Voltage feedback
Amplifier topology
DC coupled with output common
mode control capability
Output control
500 kHz, Multiple feedback low
pass filter
Filter requirement
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8.2.2 Detailed Design Procedure
Supply voltages of ±15 V are commonly used for the OPA1633. The relatively low input voltage swing required
by the ADC allows use of lower power-supply voltage, if desired. Power supplies as low as ±8 V can be used in
this application with excellent performance. This reduces power dissipation and heat rise. Power supplies should
be bypassed with 10-μF tantalum capacitors in parallel with 0.1-μF ceramic capacitors to avoid possible
oscillations and instability.
The VCOM reference voltage output on the PCM1804 ADC provides the proper input common-mode reference
voltage (2.5 V). This VCOM voltage is buffered with op amp by the OPA134 and drives the output common-mode
voltage pin of the OPA1633. This biases the average output voltage of the OPA1633 to 2.5 V.
The signal gain of the circuit is generally set to approximately 0.25 to be compatible with commonly-used audio
line levels. Gain can be adjusted, if necessary, by changing the values of R1 and R2. The feedback resistor
values (R3 and R4) should be kept relatively low, as indicated, for best noise performance.
R5, R6, and C3 provide an input filter and charge glitch reservoir for the ADC. The values shown are generally
satisfactory. Some adjustment of the values may help optimize performance with different ADCs.
It is important to maintain accurate resistor matching on R1/R2 and R3/R4 to achieve good differential signal
balance. Use 1% resistors for highest performance. When connected for single-ended inputs (inverting input
grounded, as shown in 图 8-1), the source impedance must be low. Differential input sources must have well-
balanced or low source impedance.
Capacitors C1, C2, and C3 should be chosen carefully for good distortion performance. Polystyrene,
polypropylene, NPO ceramic, and mica types are generally excellent. Polyester and high-K ceramic types such
as Z5U can create distortion.
8.2.3 Application Curves
1E-1
1E-2
1E-3
1E-4
1E-5
1E-1
1E-2
1E-3
1E-4
1E-5
RL = 600
RL = 2 k
RL = 600
RL = 2 k
10m
100m
1
10
100
10m
100m
1
10
100
Differential Output Voltage (VRMS
)
Differential Output Voltage (VRMS)
图8-2. THD + Noise vs Output Voltage
图8-3. THD + Noise vs Output Voltage
8.3 Power Supply Recommendations
The OPA1633 device was designed to be operated on power supplies ranging from ±2.5 V to ±17.5 V. Single
power supplies ranging from 5 V to 35 V can also be used. TI recommends using a power-supply accuracy of
5%, or better. When operated on a board with high-speed digital signals, it is important to provide isolation
between digital signal noise and the analog input pins. The OPA1633 is connected to power supplies through pin
3 (V+) and pin 6 (V−). Each supply pin should be decoupled to GND as close to the device as possible with a
low-inductance, surface-mount ceramic capacitor of approximately 10 nF. When vias are used to connect the
bypass capacitors to a ground plane the vias should be configured for minimal parasitic inductance. One method
of reducing via inductance is to use multiple vias. For broadband systems, two capacitors per supply pin are
advised.
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To avoid undesirable signal transients, the OPA1633 device should not be powered on with large inputs signals
present. Careful planning of system power on sequencing is especially important to avoid damage to ADC inputs
when an ADC is used in the application.
8.4 Layout
8.4.1 Layout Guidelines
1. The PowerPAD is electrically isolated from the silicon and all leads. Connecting the PowerPAD to any
potential voltage between the power-supply voltages is acceptable, but it is recommended to tie to ground
because it is generally the largest conductive plane.
2. Prepare the PCB with a top-side etch pattern, as shown in 图8-4. There should be etch for the leads as well
as etch for the thermal pad.
3. Place five holes in the area of the thermal pad. These holes should be 13 mils (0,03302 cm) in diameter.
Keep them small so that solder wicking through the holes is not a problem during reflow.
4. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. These vias
help dissipate the heat generated by the OPA1633 IC, and may be larger than the 13-mil diameter vias
directly under the thermal pad. They can be larger because they are not in the thermal pad area to be
soldered so that wicking is not a problem.
5. Connect all holes to the internal ground plane.
6. When connecting these holes to the plane, do not use the typical web or spoke via connection methodology.
Web connections have a high thermal resistance connection that is useful for slowing the heat transfer
during soldering operations. This makes the soldering of vias that have plane connections easier. In this
application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the
holes under the OPA1633 PowerPAD package should make their connection to the internal plane with a
complete connection around the entire circumference of the plated-through hole.
7. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the thermal pad area during the reflow process.
8. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
With these preparatory steps in place, the IC is simply placed in position and runs through the solder reflow
operation as any standard surface-mount component. This results in a part that is properly installed.
Single or Dual
68mils ´ 70mils (0,1727cm ´ 0,1778cm)
(via diameter = 13mils (0,03302cm)
图8-4. PowerPAD PCB Etch and Via Pattern
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8.4.1.1 Layout Example
RG–
RF+
VIN
RT–
V+
CBYP
RO+
–
+
+
FDA
VOCM
CL
–
RO–
PD
V+
CBYP
V–
RG+
RF–
RS+
RT+
图8-5. Representative Schematic for Example Layout
RS+
VIN
RT+
RT–
Remove GND and Power plane
under output and inverting pins to
minimize stray PCB capacitance
1
2
3
4
8
7
6
5
VIN–
VIN+
Place the feedback resistors, RF±, gain
resistors, RG±, and the isolation
resistors, RO±, as close to the device
pins as possible to minimize parasitics
Enable
V–
VOCM
V+
VOUT+
VOUT–
Vias to connect supply pins to
CBYP. Place CBYP capacitors on
the other side of the PCB as
close to the vias as possible.
Ground and power plane exist on
inner layers.
CL
Ground and power plane removed
from inner layers. Ground fill on
outer layers also removed.
图8-6. Example Layout
8.4.1.2 PowerPAD Design Considerations
The OPA1633 is available in a thermally-enhanced PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die is mounted (see 图 8-7(a) and 图 8-7(b)). This
arrangement results in the lead frame being exposed as a thermal pad on the underside of the package (see 图
8-7(c)). Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be
achieved by providing a good thermal path away from the thermal pad.
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DIE
(a) Side View
Thermal
Pad
DIE
(b) End View
(c) Bottom View
图8-7. Views of the Thermally-Enhanced Package
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat-dissipating device.
Soldering the PowerPAD to the printed circuit board (PCB) is always required, even with applications that have
low power dissipation. It provides the necessary thermal and mechanical connection between the lead frame die
pad and the PCB.
8.4.1.3 Power Dissipation and Thermal Considerations
The OPA1633 does not have thermal shutdown protection. Take care to assure that the maximum junction
temperature is not exceeded. Excessive junction temperature can degrade performance or cause permanent
damage. For best performance and reliability, assure that the junction temperature does not exceed 125°C.
The thermal characteristics of the device are dictated by the package and the circuit board. Maximum power
dissipation for a given package can be calculated using the following formula:
T
Max - TA
PDMax
=
qJA
where:
• PDMax is the maximum power dissipation in the amplifier (W)
• TMax is the absolute maximum junction temperature (°C)
• TA is the ambient temperature (°C)
• θJA = θJC + θCA
• θJC is the thermal coefficient from the silicon junctions to the case (°C/W)
• θCA is the thermal coefficient from the case to ambient air (°C/W)
For systems where heat dissipation is more critical, the OPA1633 is offered in an MSOP-8 with PowerPAD. The
thermal coefficient for the MSOP PowerPAD (DGN) package is substantially improved over the traditional SO
package.
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9 Device and Documentation Support
9.1 Documentation Support
9.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Fully Differential Amplifiers application note
• Texas Instruments, TI Precision Labs - Fully Differential Amplifiers video series
• Texas Instruments, Maximizing Signal Chain Distortion Performance Using High Speed Amplifiers application
note
• Texas Instruments, Analog Audio Amplifier Front-end Reference Design with Improved Noise and Distortion
• Texas Instruments, Public Announcement Audio Reference Design utilizing best in class Boost Controller
• Texas Instruments, Motherboard/controller for the AMC1210 reference design
• Texas Instruments,TPA6120A2 Stereo, 9.0 to 33.0-V, analog input headphone amplifier with 128 dB dynamic
range
• Texas Instruments, OPA2863 Dual, low-power, 110-MHz, 12-V, RRIO voltage feedback amplifier
• Texas Instruments, OPA2834 Ultra-low power, 50MHz rail-to-rail out, negative rail in, voltage-feedback op
amp
9.2 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
9.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.5 Trademarks
PowerPAD™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.7 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as
defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled
product restricted by other applicable national regulations, received from disclosing party under nondisclosure
obligations (if any), or any direct product of such technology, to any destination to which such export or re-export
is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent required by those laws.
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9.8 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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10.1 Mechanical Data
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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10.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
OPA1633
SOIC
D
8
3000
330
12.4
6.40
5.20
2.10
8
12
Q1
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
SOIC
Package Drawing Pins
SPQ
Length (mm) Width (mm)
Length Width
Height (mm)
OPA1633
D
8
3000
Height
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PACKAGE OPTION ADDENDUM
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6-Feb-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
POPA1633DR
ACTIVE
SOIC
D
8
2500
TBD
Call TI
Call TI
-40 to 85
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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