OPA177GP [TI]
精密运算放大器 | P | 8 | -40 to 85;
| 型号： | OPA177GP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 精密运算放大器 | P | 8 | -40 to 85 放大器 光电二极管 运算放大器 |
| 文件： | 总13页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
OPA177
OPA177
OPA177
Precision
OPERATIONAL AMPLIFIER
FEATURES
APPLICATIONS
● LOW OFFSET VOLTAGE: 25µV max
● PRECISION INSTRUMENTATION
● LOW DRIFT: 0.3µV/°C
● DATA ACQUISITION
● TEST EQUIPMENT
● HIGH OPEN-LOOP GAIN: 130dB min
● LOW QUIESCENT CURRENT: 1.5mA typ
● BRIDGE AMPLIFIER
● THERMOCOUPLE AMPLIFIER
● REPLACES INDUSTRY-STANDARD OP
AMPS: OP-07, OP-77, OP-177, AD707,
ETC.
DESCRIPTION
The OPA177 precision bipolar op amp feature very
low offset voltage and drift. Laser-trimmed offset,
drift and input bias current virtually eliminate the need
for costly external trimming. The high performance
and low cost make them ideally suited to a wide range
of precision instrumentation.
electric effects in input interconnections. It provides
an effective alternative to chopper-stabilized amplifi-
ers. The low noise of the OPA177 maintains accuracy.
OPA177 performance gradeouts are available. Pack-
aging options include 8-pin plastic DIP
and SO-8 surface-mount packages.
The low quiescent current of the OPA177 dramati-
cally reduce warm-up drift and errors due to thermo-
V+
7
14kΩ
Trim
1
Trim
8
25Ω
VO
6
30Ω
500Ω
500Ω
+In
3
–In
2
20µA
V–
4
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
FAXLine: (800) 548-6133 (US/Canada Only)
• Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
©1990 Burr-Brown Corporation
PDS-1081E
Printed in U.S.A. August, 1997
SBOS008
OPA177 SPECIFICATIONS
At VS = ±15V, TA = +25°C, unless otherwise noted.
OPA177F
MAX
OPA177G
PARAMETER
CONDITION
MIN
TYP
MIN
TYP
MAX
UNITS
OFFSET VOLTAGE
Input Offset Voltage
10
25
20
60
µV
Long-Term Input Offset(1)
Voltage Stability
0.3
0.4
µV/Mo
Offset Adjustment Range
Power Supply Rejection Ratio
R
P = 20kΩ
±3
125
✻
120
mV
dB
V
S = ±3V to ±18V
115
110
INPUT BIAS CURRENT
Input Offset Current
Input Bias Current
0.3
0.5
1.5
±2
✻
✻
2.8
±2.8
nA
nA
NOISE
Input Noise Voltage
Input Noise Current
1Hz to 100Hz(2)
1Hz to 100Hz
85
4.5
150
✻
✻
✻
nVrms
pArms
INPUT IMPEDANCE
Input Resistance
Differential Mode(3)
Common-Mode
26
45
200
18.5
✻
✻
MΩ
GΩ
INPUT VOLTAGE RANGE
Common-Mode Input Range(4)
Common-Mode Rejection
±13
130
±14
140
✻
115
✻
✻
V
dB
V
CM = ±13V
OPEN-LOOP GAIN
Large Signal Voltage Gain
RL ≥ 2kΩ
O = ±10V(5)
V
5110
12,000
2000
6000
V/mV
OUTPUT
Output Voltage Swing
R
R
R
L ≥ 10kΩ
L ≥ 2kΩ
L ≥ 1kΩ
±13.5
±12.5
±12
±14
±13
±12.5
60
✻
✻
✻
✻
✻
✻
✻
V
V
V
Ω
Open-Loop Output Resistance
FREQUENCY RESPONSE
Slew Rate
Closed-Loop Bandwidth
R
L ≥ 2kΩ
0.1
0.4
0.3
0.6
✻
✻
✻
✻
V/µs
MHz
G = +1
POWER SUPPLY
Power Consumption
V
V
S = ±15V, No Load
S = ±3V, No Load
40
3.5
1.3
60
4.5
2
✻
✻
✻
✻
✻
✻
mW
mW
mA
Supply Current
VS = ±15V, No Load
At VS = ±15V, –40°C ≤ TA ≤ +85°C, unless otherwise noted.
OFFSET VOLTAGE
Input Offset Voltage
Average Input Offset
Voltage Drift
15
0.1
40
0.3
20
0.7
100
1.2
µV
µV/°C
Power Supply Rejection Ratio
VS = ±3V to ±18V
110
120
106
115
dB
INPUT BIAS CURRENT
Input Offset Current
Average Input Offset Current
Drift(6)
0.5
1.5
2.2
40
✻
✻
4.5
85
nA
pA/°C
Input Bias Current
Average Input Bias Current
Drift(6)
0.5
8
±4
40
✻
15
±6
60
nA
pA/°C
INPUT VOLTAGE RANGE
Common-Mode Input Range
Common-Mode Rejection
±13
120
±13.5
140
✻
110
✻
✻
V
dB
V
CM = ±13V
OPEN-LOOP GAIN
Large Signal Voltage Gain
R
L ≥ 2kΩ, VO = ±10V
2000
6000
1000
4000
V/mV
V
OUTPUT
Output Voltage Swing
RL ≥ 2kΩ
±12
±13
✻
✻
POWER SUPPLY
Power Consumption
Supply Current
V
V
S = ±15V, No Load
S = ±15V, No Load
60
2
75
25
✻
✻
✻
✻
mW
mA
✻ Same as specification for product to left.
NOTES: (1) Long-Term Input Offset Voltage Stability refers to the averaged trend line of VOS vs time over extended periods after the first 30 days of operation. Excluding
the initial hour of operation, changes in VOS during the first 30 operating days are typically less than 2µV. (2) Sample tested. (3) Guaranteed by design. (4) Guaranteed
by CMRR test condition. (5) To insure high open-loop gain throughout the ±10V output range, AOL is tested at –10V ≤ VO ≤ 0V, 0V ≤ VO ≤ +10V, and –10V ≤ VO ≤ +10V.
(6) Guaranteed by end-point limits.
®
2
OPA177
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage ....................................................................... ±22V
Differential Input Voltage ................................................................... ±30V
Input Voltage ....................................................................................... ±VS
Output Short Circuit ................................................................. Continuous
Operating Temperature:
Plastic DIP (P), SO-8 (S) .............................................. –40°C to +85°C
θJA (PDIP) ................................................................................. 100°C/W
θJA (SOIC)................................................................................. 160°C/W
Storage Temperature:
Plastic DIP (P), SO-8 (S) ............................................ –65°C to +125°C
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering, 10s) P packages ........................... +300°C
(soldering, 3s) S package............................... +260°C
Top View
DIP/SOIC
1
2
3
4
8
7
6
5
Offset Trim
Offset Trim
V+
VO
–In
+In
V–
No Internal Connection
PACKAGE/ORDERING INFORMATION
ELECTROSTATIC
DISCHARGE SENSITIVITY
PACKAGE
DRAWING TEMPERATURE
PRODUCT
PACKAGE
NUMBER(1)
RANGE
Any integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. ESD can cause damage ranging
from subtle performance degradation to complete device
failure. Precision integrated circuits may be more suscep-
tible to damage because very small parametric changes
could cause the device not to meet published specifications.
OPA177FP
OPA177GP
OPA177GS
8-Pin Plastic DIP
8-Pin Plastic DIP
SO-8 Surface-Mount
006
006
182
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
Burr-Brown’s standard ESD test method consists of five
1000V positive and negative discharges (100pF in series
with 1.5kΩ) applied to each pin.
Failure to observe proper handling procedures could result
in small changes to the OPA177’s input bias current.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
OPA177
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = ±15V, unless otherwise noted.
TOTAL HARMONIC DISTORTION AND NOISE
vs FREQUENCY
1
MAXIMUM VOUT vs IOUT
(Negative Swing)
–17.5
–15
–12.5
–10
–7.5
–5
A = 20dB, 3Vrms, 10kΩ load
VS = ±18V
VS = ±15V
VS = ±12V
0.1
Inverting
Noninverting
0.01
VS = ±15V
–2.5
0
30kHz low pass filtered
0.001
1k
10k
100k
0
–2
–4
–6
–8
–10
–12
Frequency (Hz)
–IOUT (mA)
MAXIMUM VOUT vs IOUT
(Positive Swing)
WARM-UP OFFSET VOLTAGE DRIFT
3
2
17.5
15
VS = ±18V
VS = ±15V
12.5
10
1
0
VS = ±12V
7.5
5
–1
–2
–3
2.5
0
VS = ±15V
0
15
30
45
60
75
90
105
120
0
6
12
18
24
30
36
Time from Power Supply Turn-On (s)
I
OUT (mA)
OFFSET VOLTAGE CHANGE
DUE TO THERMAL SHOCK
CLOSED-LOOP RESPONSE vs FREQUENCY
30
25
20
15
10
5
100
80
60
40
20
0
Device Immersed in 70°C Inert Liquid
Plastic DIP
0
–20
0
10
20
30
40
50
60
70
80
10
100
1k
10k
100k
1M
10M
Time (s)
Frequency (Hz)
®
4
OPA177
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±15V, unless otherwise noted.
CMRR vs FREQUENCY
OPEN-LOOP GAIN/PHASE vs FREQUENCY
160
140
120
100
80
0
150
140
130
120
110
100
90
Gain
45
90
135
180
Phase
60
40
20
0
80
0.01
0.1
1
10
100
1k
10k 100k
1M
1
–40
1
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
INPUT BIAS AND INPUT OFFSET CURRENT
vs TEMPERATURE
POWER SUPPLY REJECTION
vs FREQUENCY
2
150
130
110
90
1
0
IB
IOS
–1
–2
70
50
–15
10
35
60
85
0.1
1
10
100
1k
10k
Temperature (°C)
Frequency (Hz)
TOTAL NOISE vs BANDWIDTH
(0.1Hz to Frequency Indicated)
INPUT NOISE VOLTAGE DENSITY vs FREQUENCY
1k
100
10
10
1
RS1 = RS2 = 200kΩ
Thermal noise of
source resistors
included.
RS = 0
0.1
0.01
1
10
100
Frequency (Hz)
1k
10k
100
1k
10k
100k
Bandwidth (Hz)
®
5
OPA177
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±15V, unless otherwise noted.
MAXIMUM OUTPUT SWING vs FREQUENCY
POWER CONSUMPTION vs POWER SUPPLY
100
10
1
32
28
24
20
16
12
8
G = +1
RL = 2kΩ
4
0
1k
10k
100k
Frequency (Hz)
1M
0
10
20
30
40
Total Supply Voltage (V)
OUTPUT SHORT-CIRCUIT CURRENT vs TIME
MAXIMUM OUTPUT VOLTAGE vs LOAD RESISTANCE
40
35
30
25
20
15
20
15
10
5
Positive
Output
Negative
Output
ISC
+
ISC
–
0
0
1
2
3
4
100
1k
10k
Time from Output Being Shorted (min)
Load Resistance to Ground (Ω)
®
6
OPA177
APPLICATIONS INFORMATION
V+
The OPA177 is unity-gain stable, making it easy to use and
free from oscillations in the widest range of circuitry. Ap-
plications with noisy or high impedance power supply lines
may require decoupling capacitors close to the device pins.
In most cases 0.1µF ceramic capacitors are adequate.
20kΩ
1
2
3
8
The OPA177 has very low offset voltage and drift. To
achieve highest performance, circuit layout and mechanical
conditions must be optimized. Offset voltage and drift can
be degraded by small thermoelectric potentials at the op amp
inputs. Connections of dissimilar metals will generate ther-
mal potential which can mask the ultimate performance of
the OPA177. These thermal potentials can be made to cancel
by assuring that they are equal in both input terminals.
VIN
OPA177
VOUT
Trim Range is approximately ±3.0mV
FIGURE 1. Optional Offset Nulling Circuit.
NOISE PERFORMANCE
1. Keep connections made to the two input terminals close
together.
The noise performance of the OPA177 is optimized for
circuit impedances in the range of 2kΩ to 50kΩ. Total noise
in an application is a combination of the op amp’s input
voltage noise and input bias current noise reacting with
circuit impedances. For applications with higher source
impedance, the OPA627 FET-input op amp will generally
provide lower noise. For very low impedance applications,
the OPA27 will provide lower noise.
2. Locate heat sources as far as possible from the critical
input circuitry.
3. Shield the op amp and input circuitry from air currents
such as cooling fans.
OFFSET VOLTAGE ADJUSTMENT
The OPA177 has been laser-trimmed for low offset voltage
and drift so most circuits will not require external adjust-
ment. Figure 1 shows the optional connection of an external
potentiometer to adjust offset voltage. This adjustment should
not be used to compensate for offsets created elsewhere in a
system since this can introduce excessive temperature drift.
INPUT BIAS CURRENT CANCELLATION
The input stage base current of the OPA177 is internally
compensated with an equal and opposite cancellation cur-
rent. The resulting input bias current is the difference
between the input stage base current and the cancellation
current. This residual input bias current can be positive or
negative.
INPUT PROTECTION
The inputs of the OPA177 are protected with 500Ω series
input resistors and diode clamps as shown in the simplified
circuit diagram. The inputs can withstand ±30V differential
inputs without damage. The protection diodes will, of course,
conduct current when the inputs are overdriven. This may
disturb the slewing behavior of unity-gain follower applica-
tions, but will not damage the op amp.
When the bias current is cancelled in this manner, the input
bias current and input offset current are approximately the
same magnitude. As a result, it is not necessary to balance
the DC resistance seen at the two input terminals (Figure 2).
A resistor added to balance the input resistances may actu-
ally increase offset and noise.
R2
R2
R1
Op Amp
R1
OPA177
RB = R2 || R1
No bias current
cancellation resistor needed
(a)
(b)
Conventional op amp with
external bias current
cancellation resistor.
OPA177 with no external
bias current cancellation
resistor.
FIGURE 2. Input Bias Current Cancellation.
®
7
OPA177
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA177FP
OPA177FPG4
OPA177GP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
PDIP
PDIP
PDIP
SOIC
P
P
P
P
D
8
8
8
8
8
50
50
50
50
75
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
Level-3-260C-168 HR
OPA177FP
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
NIPDAU
OPA177FP
OPA177GP
OPA177GP
-40 to 85
-40 to 85
OPA177GPG4
OPA177GS
OPA
177GS
OPA177GS/2K5
OPA177GS/2K5E4
OPA177GS/2K5G4
OPA177GSG4
ACTIVE
ACTIVE
ACTIVE
LIFEBUY
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
2500 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
OPA
177GS
Samples
Samples
Samples
OPA
177GS
OPA
177GS
75
RoHS & Green
OPA
177GS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Dec-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA177GS/2K5
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Dec-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
OPA177GS/2K5
D
8
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Dec-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
OPA177FP
OPA177FPG4
OPA177GP
P
P
P
P
D
D
PDIP
PDIP
PDIP
PDIP
SOIC
SOIC
8
8
8
8
8
8
50
50
50
50
75
75
506
506
13.97
13.97
13.97
13.97
8
11230
11230
11230
11230
3940
4.32
4.32
4.32
4.32
4.32
4.32
506
OPA177GPG4
OPA177GS
506
506.6
506.6
OPA177GSG4
8
3940
Pack Materials-Page 3
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