OPA186DBVT [TI]
具有轨到轨输入和输出的单路 24V、低功耗 (90μA)、5μV 失调电压零漂移运算放大器 | DBV | 5 | -40 to 125;
| 型号： | OPA186DBVT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有轨到轨输入和输出的单路 24V、低功耗 (90μA)、5μV 失调电压零漂移运算放大器 | DBV | 5 | -40 to 125 放大器 运算放大器 |
| 文件： | 总49页 (文件大小：2723K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA186, OPA2186, OPA4186
ZHCSPS9B –JUNE 2022 –REVISED DECEMBER 2022
OPAx186 精密、轨到轨输入和输出、24V、零漂移运算放大器
1 特性
3 说明
• 高精度：
OPA186、OPA2186 和 OPA4186 (OPAx186) 是低功
耗、24V、轨到轨输入和输出、零漂移运算放大器。这
些运算放大器具有仅 10µV 的失调电压（最大值）和
0.04µV/°C 的失调电压温漂（最大值），非常适合精密
仪表、信号测量和有源滤波应用。
– 失调漂移：0.01μV/°C
– 低失调电压：1μV
• 低静态电流：90 µA
• 出色的动态性能：
– 增益带宽：750 kHz
– 压摆率：0.35 V/µs
• 强大设计：
– RFI/EMI 滤波输入
• 轨到轨输入/输出
• 电源电压范围：4.5V 至24V
• 温度：–40°C 至+125°C
低静态电流消耗 (90μA) 使 OPAx186 成为功率敏感型
应用（例如电池供电仪表和便携式系统）的上佳选择。
此外，高共模架构以及低失调电压可实现正电源轨的高
侧电流分流监控。这些器件还在运输、装卸和组装期间
提供强大的ESD 保护。
器件信息
封装(1)
器件型号
OPA186
通道
2 应用
DBV（SOT-23，5）
D（SOIC，8）
单通道
双通道
四通道
• PC PSU 和游戏机单元
• 商用直流/直流
• 流量发送器
OPA2186
OPA4186
DDF（SOT-23，8）
D（SOIC，14）
• 压力变送器
• 商用电池充电器
• 电表
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
4
3
RS
6 V to 24 V
2
1
0
-1
-2
-3
-4
-5
-6
Microcontroller
ADC
Battery /
Power
Supply
OPAx186
+
0 V to 5 V
-12.5 -10 -7.5 -5 -2.5
0
2.5
5
Input Common-mode Voltage (V)
7.5 10 12.5
VOS 与输入共模电压
高侧电流分流监控器应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS968
OPA186, OPA2186, OPA4186
ZHCSPS9B –JUNE 2022 –REVISED DECEMBER 2022
www.ti.com.cn
Table of Contents
7.3 Feature Description...................................................18
7.4 Device Functional Modes..........................................22
8 Application and Implementation..................................23
8.1 Application Information............................................. 23
8.2 Typical Applications.................................................. 25
8.3 Power Supply Recommendations.............................29
8.4 Layout....................................................................... 30
9 Device and Documentation Support............................32
9.1 Device Support......................................................... 32
9.2 Documentation Support............................................ 32
9.3 接收文档更新通知..................................................... 32
9.4 支持资源....................................................................32
9.5 Trademarks...............................................................32
9.6 Electrostatic Discharge Caution................................33
9.7 术语表....................................................................... 33
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information: OPA186.................................... 6
6.5 Thermal Information: OPA2186.................................. 6
6.6 Thermal Information: OPA4186.................................. 6
6.7 Electrical Characteristics.............................................7
6.8 Typical Characteristics................................................9
7 Detailed Description......................................................17
7.1 Overview...................................................................17
7.2 Functional Block Diagram.........................................17
Information.................................................................... 33
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (June 2022) to Revision B (November 2022)
Page
• 添加了OPA186 和OPA4186 器件及相关内容....................................................................................................1
• Changed ESD Ratings table HBM value............................................................................................................ 5
• Changed ESD Ratings table CDM value............................................................................................................5
Changes from Revision * (June 2022) to Revision A (September 2022)
Page
• 将OPA2186 从预告信息（预发布）更改为量产数据（正在供货）.................................................................... 1
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5 Pin Configuration and Functions
OUT
Vœ
1
2
3
5
V+
+IN
4
œIN
Not to scale
图5-1. OPA186: DBV Package, 5-Pin SOT-23 (Top View)
表5-1. Pin Functions: OPA186
PIN
TYPE
DESCRIPTION
NAME
–IN
+IN
NO.
4
Input
Input
Inverting input
3
Noninverting input
OUT
V–
1
Output
Power
Power
Output
2
Negative (lowest) power supply
Positive (highest) power supply
V+
5
OUT A
œIN A
+IN A
Vœ
1
2
3
4
8
7
6
5
V+
OUT B
œIN B
+IN B
Not to scale
图5-2. OPA2186: D, 8-Pin SOIC, and DDF, 8-Pin SOT-23, Packages (Top View)
表5-2. Pin Functions: OPA2186
PIN
TYPE
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
OUT A
OUT B
V–
NO.
2
Input
Input
Inverting input channel A
Noninverting input channel A
Inverting input channel B
Noninverting input channel B
Output channel A
3
6
Input
5
Input
1
Output
Output
Power
Power
7
Output channel B
4
Negative supply
V+
8
Positive supply
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OUT A
œIN A
+IN A
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT D
œIN D
+IN D
Vœ
+IN B
œIN B
OUT B
+IN C
œIN C
OUT C
8
Not to scale
图5-3. OPA4186: D Package, 14-Pin SOIC (Top View)
表5-3. Pin Functions: OPA4186
PIN
TYPE
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
–IN C
+IN C
–IN D
+IN D
OUT A
OUT B
OUT C
OUT D
V–
NO.
2
Input
Input
Inverting input channel A
Noninverting input channel A
Inverting input channel B
Noninverting input channel B
Inverting input channel C
Noninverting input channel C
Inverting input channel D
Noninverting input channel D
Output channel A
3
6
Input
5
Input
9
Input
10
13
12
1
Input
Input
Input
Output
Output
Output
Output
Power
Power
7
Output channel B
8
Output channel C
14
11
4
Output channel D
Negative supply
V+
Positive supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
26
UNIT
VS
V
Supply voltage, VS = (V+) –(V–)
Common-mode
Input voltage
(V+) + 0.5
(V–) –0.5
V
Differential
(V+) –(V–) + 0.2
Output short-circuit(2)
Continuous
TJ
Operating junction temperature
Storage temperature
-40
-65
150
150
°C
°C
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
±1000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
24
UNIT
V
Single supply
Dual supply
Supply
voltage
VS
TA
±2.25
–40
±12
125
Specified temperature
°C
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6.4 Thermal Information: OPA186
OPA186
DBV (SOT-23)
5 PINS
166.8
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
62.2
38.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
12.1
ΨJT
38.2
ΨJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA2186
OPA2186
THERMAL METRIC(1)
DDF (SOT-23)
8 PINS
150.4
85.6
D (SOIC)
8 PINS
128.9
69.2
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
70.0
72.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
8.1
20.7
ΨJT
69.6
71.6
ΨJB
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA4186
OPA4186
THERMAL METRIC(1)
D (SOIC)
14 PINS
84.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
37.4
41.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
6.7
ΨJT
40.8
ΨJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.7 Electrical Characteristics
at TA = 25°C, VS = ±2.25 V to ±12 V, RL = 10 kΩ connected to VS / 2, VCM = VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
OPA186, OPA2186(1)
OPA4186(1)
±1
±6
±10
±40
VOS
Input offset voltage
μV
OPA186, OPA2186
OPA4186
±0.01
±0.025
±0.02
±0.08
±0.04
±0.1
±0.2
±0.4
TA = –40℃to +125℃(1)
TA = –40℃to +125℃(1)
μV/°C
μV/V
dVOS/dT Input offset voltage drift
OPA186, OPA2186
OPA4186
Power-supply rejection
PSRR
ratio
INPUT BIAS CURRENT
±5
±55
pA
nA
TA = –40℃to +85℃(1)
±550
TA = –40℃to
+125℃(1), OPA186,
OPA2186
IB
Input bias current
VS = ±12 V
±4.8
±6.2
TA = –40℃to
+125℃(1), OPA4186
±10
±100
±1
pA
nA
TA = –40℃to +85℃(1)
TA = –40℃to +125℃(1)
IOS
Input offset current
Input voltage noise
OPA186, OPA2186
OPA4186
±1.25
±3.8
NOISE
f = 0.1 Hz to 10 Hz
125
40
nVRMS
nV/√Hz
fA/√Hz
eN
iN
Input voltage noise density f = 1 kHz
Input current noise
f = 1 kHz
120
INPUT VOLTAGE
VCM
Common-mode voltage
(V+) + 0.2
V
(V–) –0.2
120
OPA2186
140
140
120
146
134
120
VS = ±2.25 V,
(V–) –0.1 < VCM < (V+) + 0.1 V
OPA186
118
OPA4186
105
OPA186, OPA2186
OPA4186
120
VS = ±12 V,
(V–) –0.1 < VCM < (V+) + 0.1 V
118
Common-mode rejection
ratio
CMRR
dB
VS = ±2.25 V,
OPA186, OPA2186
106
(V–) –0.1 < VCM < (V+) + 0.1 V,
TA = –40℃to +125℃(1)
OPA4186
100
115
115
114
124
124
VS = ±12 V,
(V–) –0.1 < VCM < (V+) + 0.1 V,
TA = –40℃to +125℃(1)
OPA186, OPA2186
OPA4186
FREQUENCY RESPONSE
GBW
SR
tS
Gain-bandwidth product
750
0.35
7.5
kHz
V/μs
μs
Slew rate
1-V step, G = 1
Settling time
To 0.1%, 1-V step, G = 1
VIN × gain > VS
Overload recovery time
10
μs
INPUT CAPACITANCE
ZID
Differential
100 || 5
50 || 2.5
MΩ|| pF
GΩ|| pF
ZICM
Common-mode
OPEN-LOOP VOLTAGE GAIN
123
123
123
123
148
146
148
146
VS = ±12 V, RL = 10 kΩ,
(V–) + 0.3 V < VO < (V+) –0.3 V
TA = –40℃to +125℃(1)
TA = –40℃to +125℃(1)
AOL
Open-loop voltage gain
dB
VS = ±12 V, RL = 2 kΩ,
(V–) + 0.65 V < VO < (V+) –0.65 V
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6.7 Electrical Characteristics (continued)
at TA = 25°C, VS = ±2.25 V to ±12 V, RL = 10 kΩ connected to VS / 2, VCM = VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
No load
5
65
10
RL = 10 kΩ
RL = 2 kΩ
Positive rail
Negative rail
345
425
120
10
RL = 10 kΩ,
TA = –40℃to +125℃(1)
95
Voltage output swing from
the rail
VO
mV
No load
5
30
90
RL = 10 kΩ
RL = 2 kΩ
120
50
RL = 10 kΩ,
TA = –40℃to +125℃(1)
35
ISC
Short-circuit current
Capacitive load drive
±20
mA
CLOAD
See typical curves
See typical curves
Open-loop output
impedance
RO
POWER SUPPLY
90
130
150
Quiescent current per
amplifier
IQ
VS = ±2.25 V to ±12 V
µA
TA = –40℃to +125℃(1)
(1) Specification established from device population bench system measurements across multiple lots.
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6.8 Typical Characteristics
at TA = 25°C, VS = ±12 V, VCM = VS / 2, RL = 10 kΩ(unless otherwise noted)
表6-1. Typical Characteristic Graphs
DESCRIPTION
FIGURE
图6-1
Offset Voltage Distribution
Offset Voltage Drift (-40°C to +125C°C)
Input Bias Current Distribution
图6-2
图6-3
Input Offset Current Distribution
图6-4
Offset Voltage vs Common-Mode Voltage
Offset Voltage vs Supply Voltage
图6-5
图6-6
Input Bias Current vs Common-Mode Voltage
Open-Loop Gain and Phase vs Frequency
Closed-Loop Gain vs Frequency
图6-7
图6-8
图6-9
Input Bias Current and Offset Current vs Temperature
Output Voltage Swing vs Output Current (Sourcing)
Output Voltage Swing vs Output Current (Sinking)
CMRR and PSRR vs Frequency
图6-10
图6-11
图6-12
图6-13
图6-14
图6-15
图6-16
图6-17
图6-18
图6-19
图6-20
图6-21
图6-22
图6-23
图6-24
CMRR vs Temperature
PSRR vs Temperature
0.1-Hz to 10-Hz Voltage Noise
Input Voltage Noise Spectral Density vs Frequency
THD+N vs Frequency
THD+N vs Output Amplitude
Quiescent Current vs Supply Voltage
Quiescent Current vs Temperature
Open-Loop Gain vs Temperature (10 kΩ)
Open-Loop Gain vs Temperature (2 kΩ)
Open-Loop Output Impedance vs Frequency
Small-Signal Overshoot vs Capacitive Load (Gain = –1, 10-mV
step)
图6-25
Small-Signal Overshoot vs Capacitive Load (Gain = 1, 10-mV step)
No Phase Reversal
图6-26
图6-27
图6-28
图6-29
图6-30
图6-31
图6-32
图6-33
图6-34
图6-35
图6-36
图6-37
图6-38
图6-39
Positive Overload Recovery
Negative Overload Recovery
Small-Signal Step Response (Gain = 1, 10-mV step)
Small-Signal Step Response (Gain = –1, 10-mV step)
Large-Signal Step Response (Gain = 1, 10-V step)
Large-Signal Step Response (Gain = –1, 10-V step)
Phase Margin vs Capacitive Load
Settling Time (1-V Step, 0.1% Settling)
Short Circuit Current vs Temperature
Maximum Output Voltage vs Frequency
EMIRR vs Frequency
Channel Separation
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6.8 Typical Characteristics
at TA = 25°C, VS = ±12 V, VCM = VS / 2, RL = 10 kΩ(unless otherwise noted)
40
36
32
28
24
20
16
12
8
40
36
32
28
24
20
16
12
8
4
4
0
0
-50 -40 -30 -20 -10
0
10
20
30
40
50
-0.1 -0.075 -0.05 -0.025
0
0.025 0.05 0.075 0.1
Input Offset Voltage (µV)
Offset Voltage Drift (µV/°C)
图6-1. Offset Voltage Distribution
图6-2. Offset Voltage Drift (-40°C to 125C°C)
60
54
48
42
36
30
24
18
12
6
72
64
56
48
40
32
24
16
8
0
0
-600
-400
-200
0
200
400
600
-1 -0.8 -0.6 -0.4 -0.2
0
0.2 0.4 0.6 0.8
1
Input Offset Current (pA)
Input Bias Current (nA)
图6-4. Input Offset Current Distribution
图6-3. Input Bias Current Distribution
20
10
0
4
2
0
-10
-2
-4
-20
-12.5 -10 -7.5 -5 -2.5
0
2.5
5
7.5 10 12.5
4
6
8
10
12
14
16
18
20
22
24
Common-mode Voltage (V)
Total Supply Voltage (V)
图6-5. Offset Voltage vs Common-Mode Voltage
图6-6. Offset Voltage vs Supply Voltage
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±12 V, VCM = VS / 2, RL = 10 kΩ(unless otherwise noted)
180
180
50
Gain
Phase
40
150
150
30
120
120
90
60
30
0
20
90
10
0
60
-10
30
-20
0
-30
IB-
IB+
-40
-50
-30
10m 100m
-30
1
10
100 1k
Frequency (Hz)
10k 100k 1M 10M
-12.5 -10 -7.5 -5 -2.5
0
2.5
5
7.5 10 12.5
Common-mode Voltage (V)
图6-8. Open-Loop Gain and Phase vs Frequency
2.5
图6-7. Input Bias Current vs Common-Mode Voltage
30
20
10
0
G = +1
IB-
G= -1
IB+
IOS
2
1.5
1
G= +10
0.5
0
-10
-20
-0.5
100
1k
10k 100k
Frequency (Hz)
1M
10M
-50
-25
0
25
50
75
100
125
Temperature (°C)
图6-9. Closed-Loop Gain vs Frequency
图6-10. Input Bias Current and Offset Current vs Temperature
12
12.5
-40èC
10
8
10
25èC
85èC
125èC
7.5
6
5
4
2.5
0
2
0
-2.5
-5
-2
-4
-6
-8
-10
-40èC
25èC
85èC
125èC
-7.5
-10
-12.5
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Output Current (mA)
0
3
6
9
12
15
Output Current (mA)
18
21
24
27
图6-11. Output Voltage Swing vs
图6-12. Output Voltage Swing vs
Output Current (Sourcing)
Output Current (Sinking)
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±12 V, VCM = VS / 2, RL = 10 kΩ(unless otherwise noted)
160
140
120
100
80
170
165
160
155
150
145
140
135
130
PSRR+
PSRR-
CMRR
0.01
60
40
0.1
20
0
100m
1
10
100
1k
Frequency (Hz)
10k
100k
1M
10M
-50
-30
-10
10
30
50
70
90
110 125
Temperature (°C)
图6-13. CMRR and PSRR vs Frequency
图6-14. CMRR vs Temperature
190
180
170
160
0.001
0.01
125
-50
-25
0
25
50
75
100
Time (1 s/div)
Temperature (°C)
图6-16. 0.1-Hz to 10-Hz Voltage Noise
图6-15. PSRR vs Temperature
1000
100
10
1
0.1
-40
-60
-80
-100
G = +1, RL = 10 kW
G = +1, RL = 2 kW
G = -1, RL = 10 kW
G = -1, RL = 2 kW
0.01
0.001
0.0001
-120
10k
100m
1
10
100
Frequency (Hz)
1k
10k
100k
100
1k
Frequency (Hz)
图6-17. Input Voltage Noise Spectral Density vs Frequency
图6-18. THD+N vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±12 V, VCM = VS / 2, RL = 10 kΩ(unless otherwise noted)
1
-40
-60
-80
-100
100
90
80
70
60
50
40
30
20
10
0
G = +1, RL = 10 kW
G = +1, RL = 2 kW
G = -1, RL = 10 kW
G = -1, RL = 2 kW
0.1
VS Min = 4.5 V
0.01
0.001
10m
100m
Output Amplitude (VRMS
1
10
0
2
4
6
8
10 12 14 16 18 20 22 24
Supply Voltage (V)
)
图6-19. THD+N vs Output Amplitude
图6-20. Quiescent Current vs Supply Voltage
110
180
VS = 4.5 V
VS = 24 V
100
90
80
70
60
160
140
120
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
图6-21. Quiescent Current vs Temperature
图6-22. Open-Loop Gain vs Temperature
180
160
140
120
1000
100
10
1
0.1
0.01
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
10
100
1k 10k
Frequency (Hz)
100k
1M
RL = 2 kΩ
图6-24. Open-Loop Output Impedance vs Frequency
图6-23. Open-Loop Gain vs Temperature
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±12 V, VCM = VS / 2, RL = 10 kΩ(unless otherwise noted)
40
35
30
25
20
15
10
5
100
80
60
40
20
0
RISO = 0 W
RISO = 25 W
RISO = 50 W
RISO = 0 W
RISO = 25 W
RISO = 50 W
10
100
Capactiance (pF)
1000
10
100
Capactiance (pF)
1000
Gain = 1, 10-mV step
Gain = –1, 10-mV step
图6-26. Small-Signal Overshoot vs
图6-25. Small-Signal Overshoot vs
Capacitive Load
Capacitive Load
VIN (V)
VOUT (V)
VIN
VOUT
Time (100 ms/div)
Time (10 ms/div)
图6-27. No Phase Reversal
图6-28. Positive Overload Recovery
VIN
VOUT
VIN
VOUT
Time (10 ms/div)
Time (10 ms/div)
Gain = 1, 10-mV step
图6-29. Negative Overload Recovery
图6-30. Small-Signal Step Response
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±12 V, VCM = VS / 2, RL = 10 kΩ(unless otherwise noted)
VIN
VOUT
VIN (V)
VOUT (V)
Time (10 ms/div)
Time (10 ms/div)
Gain = 1, 10-V step
Gain = –1, 10-mV step
图6-32. Large-Signal Step Response
图6-31. Small-Signal Step Response
65
VIN (V)
VOUT (V)
60
55
50
45
40
35
30
25
20
15
10
100
CLOAD (pF)
1000
Time (10 ms/div)
Gain = –1, 10-V step
图6-34. Phase Margin vs Capacitive Load
图6-33. Large-Signal Step Response
32
31
30
29
28
27
26
25
24
23
22
21
20
Falling
Rising
Sinking
Sourcing
-40
-20
0
20
40
60
80
100
120
Time (5 ms/div)
Temperature (èC)
1-V step, 0.1% settling
图6-35. Settling Time
图6-36. Short Circuit Current vs Temperature
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±12 V, VCM = VS / 2, RL = 10 kΩ(unless otherwise noted)
30
25
20
15
10
5
175
150
125
100
75
VS = ê12 V
VS = ê2.25 V
50
0
25
1
10
100
1k
Frequency (Hz)
10k
100k
1M
10M
100M
Frequency (Hz)
1G
10G
图6-37. Maximum Output Voltage vs Frequency
图6-38. EMIRR vs Frequency
-60
-80
-100
-120
-140
-160
-180
1k
10k
100k
1M
Frequency (Hz)
图6-39. Channel Separation
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7 Detailed Description
7.1 Overview
The OPAx186 operational amplifier combines precision offset and drift with excellent overall performance,
making the device a great choice for a wide variety of precision applications. The precision offset drift of only
0.01 µV/°C provides stability over the entire operating temperature range of –40°C to +125°C. In addition, this
device offers excellent linear performance with high CMRR, PSRR, and AOL. As with all amplifiers, applications
with noisy or high-impedance power supplies require decoupling capacitors close to the device pins. In most
cases, 0.1-µF capacitors are adequate. For details and a layout example, see 节8.4.
The OPAx186 is part of a family of zero-drift, MUX-friendly, rail-to-rail output operational amplifiers. This device
operates from 4.5 V to 24 V, is unity-gain stable, and is designed for a wide range of general-purpose and
precision applications. The zero-drift architecture provides ultra-low input offset voltage and near-zero input
offset voltage drift over temperature and time. This choice of architecture also offers outstanding ac
performance, such as ultra-low broadband noise, zero flicker noise, and outstanding distortion performance
when operating at less than the chopper frequency.
The following section shows a representation of the proprietary OPAx186 architecture.
7.2 Functional Block Diagram
C2
Notch
Filter
CHOP1
CHOP2
GM2
GM3
GM1
OUT
+IN
24-V
Differential
Front End
œIN
GM_FF
C1
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7.3 Feature Description
The OPAx186 operational amplifier has several integrated features to help maintain a high level of precision
through a variety of applications. These include a rail-to-rail inputs, phase-reversal protection, input bias current
clock feedthrough, EMI rejection, electrical overstress protection and MUX-friendly Inputs.
7.3.1 Rail-to-Rail Inputs
Unlike many chopper amplifiers, the OPAx186 has rail-to-rail inputs that allow the input common-mode voltage to
not only reach, but exceed the supply voltages by 200 mV. This configuration simplifies power-supply
requirements by not requiring headroom over the input signal range.
The OPAx186 is specified for operation from 4.5 V to 24 V (±2.25 V to ±12 V) with rail-to-rail inputs. Many
specifications apply from –40°C to +125°C.
7.3.2 Phase-Reversal Protection
The OPAx186 has internal phase-reversal protection. Some op amps exhibit a phase reversal when the input is
driven beyond the linear common-mode range. This condition is most often encountered in noninverting circuits
when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into
the opposite rail. The OPAx186 input prevents phase reversal with excessive common-mode voltage. Instead,
the output limits into the appropriate rail. 图7-1 shows this performance.
VIN (V)
VOUT (V)
Time (100 ms/div)
图7-1. No Phase Reversal
7.3.3 Input Bias Current Clock Feedthrough
Zero-drift amplifiers such as the OPAx186 use a switching architecture on the inputs to correct for the intrinsic
offset and drift of the amplifier. Charge injection from the integrated switches on the inputs can introduce short
transients in the input bias current of the amplifier. The extremely short duration of these pulses prevents the
pulses from amplifying; however, the pulses can be coupled to the output of the amplifier through the feedback
network. The most effective method to prevent transients in the input bias current from producing additional
noise at the amplifier output is to use a low-pass filter, such as an RC network.
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7.3.4 EMI Rejection
The OPAx186 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI
interference from sources such as wireless communications and densely-populated boards with a mix of analog
signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPAx186
benefits from these design improvements. Texas Instruments has developed the ability to accurately measure
and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to
6 GHz. 图 7-2 shows the results of this testing on the OPAx186. 表 7-1lists the EMIRR +IN values for the
OPAx186 at particular frequencies commonly encountered in real-world applications. 表 7-1 lists applications
that can be centered on or operated near the particular frequency shown. See also the EMI Rejection Ratio of
Operational Amplifiers application report, available for download from www.ti.com.
175
150
125
100
75
50
25
10M
100M
Frequency (Hz)
1G
10G
图7-2. EMIRR Testing
表7-1. OPAx186 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION AND ALLOCATION
EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
400 MHz
48.4 dB
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
900 MHz
1.8 GHz
2.4 GHz
3.6 GHz
5 GHz
52.8 dB
69.1 dB
88.9 dB
82.5 dB
95.5 dB
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
Radiolocation, aero communication and navigation, satellite, mobile, S-band
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
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The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of RF
signal rectification. An op amp that is more efficient at rejecting this change in offset as a result of EMI has a
higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in many ways, but this
section provides the EMIRR +IN, which specifically describes the EMIRR performance when the RF signal is
applied to the noninverting input pin of the op amp. In general, only the noninverting input is tested for EMIRR for
the following three reasons:
• Op amp input pins are known to be the most sensitive to EMI, and typically rectify RF signals better than the
supply or output pins.
• The noninverting and inverting op amp inputs have symmetrical physical layouts and exhibit nearly matching
EMIRR performance
• EMIRR is more simple to measure on noninverting pins than on other pins because the noninverting input
terminal can be isolated on a PCB. This isolation allows the RF signal to be applied directly to the
noninverting input terminal with no complex interactions from other components or connecting PCB traces.
High-frequency signals conducted or radiated to any pin of the operational amplifier can result in adverse effects,
as there is insufficient amplifier loop gain to correct for signals with spectral content outside the bandwidth.
Conducted or radiated EMI on inputs, power supply, or output can result in unexpected dc offsets, transient
voltages, or other unknown behavior. Take care to properly shield and isolate sensitive analog nodes from noisy
radio signals and digital clocks and interfaces.
图 7-2 shows the EMIRR +IN of the OPAx186 plotted versus frequency. The OPAx186 unity-gain bandwidth is
750 kHz. EMIRR performance less than this frequency denotes interfering signals that fall within the op-amp
bandwidth.
7.3.4.1 EMIRR +IN Test Configuration
图 7-3 shows the circuit configuration for testing the EMIRR +IN. An RF source is connected to the op-amp
noninverting input pin using a transmission line. The op amp is configured in a unity-gain buffer topology with the
output connected to a low-pass filter (LPF) and a digital multimeter (DMM). A large impedance mismatch at the
op amp input causes a voltage reflection; however, this effect is characterized and accounted for when
determining the EMIRR IN+. The multimeter samples and measures the resulting dc offset voltage. The LPF
isolates the multimeter from residual RF signals that can interfere with multimeter accuracy.
Ambient temperature: 25˘C
V+
œ
+
Low-Pass
Filter
50 ꢀ
RF Source
DC Bias: 0 V
Modulation: None (CW)
Digital
Multimeter
Sample /
Averaging
Vœ
Frequency Sweep: 201 pt. Log
Not shown: 0.1 µF and 10 µF supply decoupling
图7-3. EMIRR +IN Test Configuration
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7.3.5 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect from accidental
ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is
helpful. 图 7-4 shows an illustration of the ESD circuits contained in the OPAx186 (indicated by the dashed line
area). The ESD protection circuitry involves several current-steering diodes connected from the input and output
pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device internal
to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, high-
current pulse while discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device can activate. The
absorption device has a trigger or threshold voltage that is greater than the normal operating voltage of the
OPAx186, but less than the device breakdown voltage level. When this threshold is exceeded, the absorption
device quickly activates and clamps the voltage across the supply rails to a safe level.
图 7-4 shows that when the operational amplifier connects into a circuit, the ESD protection components are
intended to remain inactive, and do not become involved in the application circuit operation. However,
circumstances can arise where an applied voltage exceeds the operating voltage range of a given pin. If this
condition occurs, there is a risk that some internal ESD protection circuits are biased on and conduct current.
Any such current flow occurs through steering-diode paths and rarely involves the absorption device.
TVS(2)
RF
V+
RI
ESD Current-
Steering Diodes
-IN
(3)
OUT
Op Amp
Core
RS
+IN
Edge-Triggered ESD
Absorption Circuit
RL
ID
(1)
VIN
Vœ
TVS(2)
(1) VIN = (V+) + 500 mV
(2) TVS: 26 V > VTVSBR (min) > V+, where VTVSBR (min) is the minimum specified value for the transient voltage suppressor breakdown
voltage.
(3) Suggested value is approximately 5 kΩin example overvoltage condition.
图7-4. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
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图 7-4 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by 500
mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the
current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier, and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input while
the power supplies V+ or V– are at 0 V. Again, this question depends on the supply characteristic while at 0 V,
or at a level below the input signal amplitude. If the supplies appear as high impedance, then the operational
amplifier supply current can be supplied by the input source through the current-steering diodes. This state is not
a normal biasing condition for the amplifier and can result in specification degradation or abnormal operation. If
the supplies are low impedance, then the current through the steering diodes can become quite high. The
current level depends on the ability of the input source to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the
supply pins; see also 图 7-4. The Zener voltage must be selected such that the diode does not turn on during
normal operation. However, the Zener voltage must be low enough so that the Zener diode conducts if the
supply pin begins to rise above the safe operating supply voltage level.
7.3.6 MUX-Friendly Inputs
The OPAx186 features a proprietary input stage design that allows an input differential voltage to be applied
while maintaining high input impedance. Typically, high-voltage CMOS or bipolar-junction input amplifiers feature
antiparallel diodes that protect input transistors from large VGS voltages that can exceed the semiconductor
process maximum and permanently damage the device. Large VGS voltages can be forced when applying a
large input step, switching between channels, or attempting to use the amplifier as a comparator.
The OPAx186 solves these problems with a switched-input technique that prevents large input bias currents
when large differential voltages are applied. This input architecture addresses many issues seen in switched or
multiplexed applications, where large disruptions to RC filtering networks are caused by fast switching between
large potentials. The OPAx186 offers outstanding settling performance as a result of these design innovations
and built-in slew-rate boost and wide bandwidth. The OPAx186 can also be used as a comparator. Differential
and common-mode input ranges still apply.
7.4 Device Functional Modes
The OPAx186 has a single functional mode, and is operational when the power-supply voltage is greater than
4.5 V (±2.25 V). The maximum power supply voltage for the OPAx186 is 24 V (±12 V).
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The OPAx186 operational amplifier combines precision offset and drift with excellent overall performance,
making the device an excellent choice for many precision applications. The precision offset drift of only
0.01 µV/°C provides stability over the entire temperature range. In addition, the device pairs excellent CMRR,
PSRR, and AOL dc performance with outstanding low-noise operation. As with all amplifiers, applications with
noisy or high-impedance power supplies require decoupling capacitors close to the device pins. In most cases,
0.1‑µF capacitors are adequate.
8.1.1 Basic Noise Calculations
Low-noise circuit design requires careful analysis of all noise sources. In many cases, external noise sources
can dominate; consider the effect of source resistance on overall op-amp noise performance. Total noise of the
circuit is the root-sum-square combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the
resistance. The source impedance is usually fixed; consequently, select op amp and the feedback resistors that
minimize the respective contributions to the total noise.
图 8-1 shows both noninverting (A) and inverting (B) op-amp circuit configurations with gain. In circuit
configurations with gain, the feedback network resistors also contribute noise. In general, the current noise of the
op amp reacts with the feedback resistors to create additional noise components. However, the extremely low
current noise of the OPAx186 means that the current noise contribution can be ignored.
The feedback resistor values can generally be chosen to make these noise sources negligible. Low impedance
feedback resistors load the output of the amplifier. The equations for total noise are shown for both
configurations.
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(A) Noise in Noninverting Gain Configuration
Noise at the output is given as EO, where
R1
R2
2
42
41 „ 42
2
2
2
2
¨
: ;
1
:
;
:
;
:
;
>
?
84/5
'
1
= l1 + p „ A5 + A0 + kA4 2 o + E0 „ 45 + lE0 „ d
hp
æ4
1
41
41 + 42
GND
œ
EO
8
: ;
2
A = 4 „ G$ „ 6(-) „ 45
d
h
¥
Thermal noise of RS
+
5
*V
¾
RS
41 „ 42
8
: ;
3
A4
= ¨4 „ G$ „ 6(-) „ d
2
h
d
h
Thermal noise of R1 || R2
æ4
1
41 + 42
*V
¾
+
,
h
VS
Source
GND
G$ = 1.38065 „ 10F23
: ;
4
d
œ
Boltzmann Constant
-
Temperature in kelvins
: ;
>
?
-
5
6(-) = 237.15 + 6(°%)
(B) Noise in Inverting Gain Configuration
Noise at the output is given as EO, where
R1
R2
2
:
;
42
45 + 41 „ 42
'
1
= l1 +
p „ A0 2 + kA4
o2 + FE0 „ H
+4 æ4
5 2
IG
¨
: ;
6
:
;
>
84/5
?
1
45 + 41
45 + 41 + 42
RS
œ
EO
:
;
45 + 41 „ 42
8
+
: ;
7
¨
4 „ G$ „ 6(-) „ H
A4
=
I
d
h
Thermal noise of (R1 + RS) || R2
+4 æ4
5
1
2
45 + 41 + 42
*V
¾
+
VS
œ
,
GND
G$ = 1.38065 „ 10F23
d
h
: ;
8
Boltzmann Constant
Source
GND
-
: ;
9
>
?
6(-) = 237.15 + 6(°%)
-
Temperature in kelvins
Copyright © 2017, Texas Instruments Incorporated
Where en is the voltage noise spectral density of the amplifier. For the OPAx186 operational amplifier, en = 38 nV/√Hz at 1 kHz.
NOTE: For additional resources on noise calculations, visit TI Precision Labs.
图8-1. Noise Calculation in Gain Configurations
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8.2 Typical Applications
8.2.1 High-Side Current Sensing
RL
+
24 V
IL
Load Current
–
R1
R2
+ 24 V –
VO
–
+
R3
OPA2186
R4
R1 = R3, R2 = R4
图8-2. High-Side Current Monitor
8.2.1.1 Design Requirements
A common systems requirement is to monitor the current being delivered to a load. Monitoring makes sure that
normal current levels are being maintained, and also provides an alert if an overcurrent condition occurs.
Fortunately, a relatively simple current monitor solution can be achieved using a precision rail-to-rail input/output
op amp such as the OPAx186. This device has an input common-mode voltage (VCM) range that extends
200 mV beyond each power supply rail allowing for operation at the supply rail.
The OPAx186 is configured as a difference amplifier with a predetermined gain. The difference amplifier inputs
are connected across a sense resistor through which the load current flows. The sense resistor can be
connected to the high side or low side of the circuit through which the load current flows. Commonly, high-side
current sensing is applied. 图 8-2 shows an applicable OPAx186 configuration. Low-side current sensing can be
applied as well if the sense resistor can be placed between the load and ground.
Use the following parameters for this design example:
• Single supply: 24 V
• Linear output voltage range: 0.3 V to 3.3 V
• Load current, IL: 1 A to 11 A
The following design details and equations can be used to reconfigure this design for different output voltage
ranges and current loads.
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8.2.1.2 Detailed Design Procedure
Designing a high-side current monitor circuit is straightforward, provided that the amplifier electrical
characteristics are carefully considered so that linear operation is maintained. Other additional characteristics,
such as the input voltage range of the analog to digital converter (ADC) that follows the current monitor stage,
must also be considered when configuring the system.
For example, consider the design of a OPAx186 high-side current monitor with an output voltage range set to be
compatible with the input of an ADC with an input range of 3.3 V, such as one integrated in a microcontroller.
The full-scale input range of this converter is 0 V to 3.3 V. Although the OPAx186 is specified as a rail-to-rail
input/output (RRIO) amplifier, the linear output operating range (like all amplifiers) does not quite extend all the
way to the supply rails. This linear operating range must be considered.
In this design example, the OPAx186 is powered by 24 V; therefore, the device is easily capable of providing the
3.3-V positive level; or even more, if the ADC has a wider input range. However, because the OPAx186 output
does not swing completely to 0 V, the specified lower swing limit must be observed in the design.
The best measure of an op-amp linear output voltage range comes from the open-loop voltage gain (AOL
)
specification listed in the Electrical Characteristics table. The AOL test conditions specify a linear swing range
300 mV from each supply rail (RL = 10 kΩ). Therefore, the linear swing limit on the low end (VoMIN) is 300 mV,
and 3.3 V is the VoMAX limit, thus yielding an 11:1 VoMAX to VoMIN ratio. This ratio proves important in determining
the difference amplifier operating parameters.
A nominal load current (IL) of 10 A is used in this example. In most applications, however, the ability to monitor
current levels far less than 10 A is useful. This situation is where the 11:1 VoMAX to VoMIN ratio is crucial. If 11 A is
set as the maximum current, this current must correspond to a 3.3-V output. Using the 11:1 ratio, the minimum
current of 1 A corresponds to 300 mV.
Selection of current sense resistor RS comes down to how much voltage drop can be tolerated at maximum
current and the permissible power loss or dissipation. A good compromise for a 10-A sense application is an RS
of 10 mΩ. That value results in a power dissipation of 1 W, and a 0.1-V drop at 10 A.
Next, determine the gain of the OPAx186 difference amplifier circuit. The maximum current of 11 A flowing
through a 10-mΩ sense resistor results in 110 mV across the resistor. That voltage appears as a differential
voltage, VR, that is applied across the OPAx186 difference amplifier circuit inputs:
VS = IL *RS
VS = 11 A *10 mW = 110 mV
(1)
The OPAx186 required voltage gain is determined from:
VOMAX
GA
GA
=
=
VS
3.3 V
0.11 V
V
V
= 30
(2)
(3)
Now, checking the VoMIN using IL = 1 A:
VOMIN = GA *ISMIN *RS
V
VOMIN = 30 *1 A *10 mW = 300 mV
V
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图 8-3 shows the complete OPAx186 high-side current monitor. The circuit is capable of monitoring a current
range of < 1 A to 11 A, with a VCM very close to the 24-V supply voltage.
RL = 10 m
+
24 V
–
IL
Load Current
1 A to 11 A
R1 = 1 k
R2 = 30 k
+ 24 V –
+ 3.3 V –
–
+
µController
ADC
R3 = 1 k
OPA2186
R4 = 30 k
VO = 300 mV to 3.3 V
图8-3. OPAx186 Configured as a High-Side Current Monitor
In this example, the OPAx186 output voltage is intentionally limited to 3.3 V. However, because of the 24-V
supply, the output voltage can be much higher to allow for a higher-voltage data converter with a higher dynamic
range.
The circuit in 图 8-3 was checked using the TINA Spice circuit simulation tool to verify the correct operation of
the OPAx186 high-side current monitor. The simulation results are seen in 图 8-4. The performance is exactly as
expected. Upon careful inspection of the plots, one possible surprise is that VO continues towards zero as the
sense current drops below 1 A, where VO is 300 mV and less.
RL = 10 m
+
24 V
–
IL
Load Current
1 A to 11 A
R1 = 1 k
R2 = 30 k
+ 24 V –
+ 3.3 V –
–
+
µController
ADC
R3 = 1 k
OPA2186
R4 = 30 k
VO = 300 mV to 3.3 V
图8-4. OPAx186 High-Side Current-Monitor Simulation Schematic
The OPAx186 output, as well as other CMOS output amplifiers, often swing closer to 0 V than the linear output
parameters suggest. The voltage output swing, VO (see the Electrical Characteristics table), is not an indication
of the linear output range, but rather how close the output can move towards the supply rail. In that region, the
amplifier output approaches saturation, and the amplifier ceases to operate linearly. Thus, in the current-monitor
application, the current-measurement capability can continue to much less than the 300-mV output level.
However, keep in mind that the linearity errors are becoming large.
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Lastly, some notes about maximizing the high-side current monitor performance:
• All resistor values are critical for accurate gain results. Match resistor pairs of [R1 and R3] and [R2 and R4]
as closely as possible to minimize common-mode mismatch error. Use a 0.1% tolerance, or better. Often,
selecting two adjacent resistors on a reel provides close matching compared to random selection.
• Keep the closed-loop gain, GA, of the OPAx186 difference amplifier set to a reasonable value to reduce gain
error and maximize bandwidth. A GA of 30 V/V is used in the example.
• Although current monitoring is often used for monitoring dc supply currents, ac current can also be monitored.
The –3-dB bandwidth, or upper cutoff frequency, of the circuit is:
GBW
fH =
Noise Gain
(4)
where
• GBW is the amplifier unity gain bandwidth; 750 kHz for the OPAx186.
• 方程式5 shows that the noise gain is equal to the gain as seen looking into the op-amp noninverting input, as
shown in .
R2
GNG = 1+
R1
(5)
For the OPAx186 circuit in 图8-3, the results are:
30 kW
1 kW
V
V
GNG = 1+
= 31
750 kHz
fH =
= 24.2 kHz
31
Make sure that the amplifier slew rate is sufficient to support the expected output voltage swing range and
waveform. Also, if a single power supply (such as 24 V) is used, the ac power source applied to the sense input
must have a positive dc component to keep the VCM greater than 0 V. To maintain normal operation, the input
voltage cannot drop to less than 0 V.
The OPAx186 output can attain a 0 V output level if a small negative voltage is used to power the V– pin
instead of ground. The LM7705 is a switched capacitor voltage inverter with a regulated, low-noise, –0.23-V
fixed voltage output. Powering the OPAx186 V– pin at this level approximately matches the 300‑mV linear
output voltage swing lower limit, thus extending the output swing to 0 V, or very near 0 V. This configuration
greatly improves the resolution at low sense current levels.
The LM7705 requires only about 78 μA of quiescent current, but be aware that the specified supply range is 3 V
to 5.25 V. The 3.3-V or 5-V supply used by the ADC can be used as a power source.
For more information about amplifier-based, high-side current monitors, see the TI Analog Engineer’s Circuit
Cookbook: Amplifiers.
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8.2.1.3 Application Curve
4
3.6
3.2
2.8
2.4
2
24.2
VOUT
VLOAD
24.16
24.12
24.08
24.04
24
1.6
1.2
0.8
0.4
0
23.96
23.92
23.88
23.84
23.8
0
1
2
3
4
5
6
Input Current (A)
7
8
9
10 11
图8-5. High-Side Results
8.2.2 Bridge Amplifier
图 8-6 shows the basic configuration for a bridge amplifier. Click the following link to download the TINA-TI file:
Bridge Amplifier Circuit.
VEX
R1
R
R
R
R
+5V
VOUT
VREF
Copyright © 2017, Texas Instruments Incorporated
图8-6. Bridge Amplifier
8.3 Power Supply Recommendations
The OPAx186 is specified for operation from 4.5 V to 24 V (±2.25 V to ±12 V); many specifications apply from –
40°C to +125°C.
CAUTION
Supply voltages larger than 40 V can permanently damage the device (see the Absolute Maximum
Ratings table).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or
high‑impedance power supplies. For more detailed information on bypass capacitor placement, see 节8.4.
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8.4 Layout
8.4.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices:
• For the lowest offset voltage, avoid temperature gradients that create thermoelectric (Seebeck) effects in the
thermocouple junctions formed from connecting dissimilar conductors. Also:
– Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
– Thermally isolate components from power supplies or other heat sources.
– Shield operational amplifier and input circuitry from air currents, such as cooling fans.
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp
itself. Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the
analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information, see the
The PCB is a component of op amp design analog application journal.
• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed
to in parallel with the noisy trace.
• Place the external components as close as possible to the device. As 图8-7 shows, keep the feedback
resistor (R3) and gain resistor (R4) close to the inverting input to minimize parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• For best performance, clean the PCB following board assembly.
• Any precision integrated circuit can experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture
introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at
85°C for 30 minutes is sufficient for most circumstances.
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8.4.2 Layout Example
Place bypass
capacitors as close to
device as possible
Use ground pours for
shielding the input
signal pairs
GND
(avoid use of vias)
C3
C4
+V
C3
R3
R3
IN–
C4
+V
1
NC
–IN
+IN
V–
NC
V+
8
7
6
5
1
2
3
4
NC
–IN
+IN
V–
NC
V+
8
7
6
5
R1
R1
2
IN–
–
+
OUT
IN+
R2
3
4
OUT
NC
OUT
NC
OUT
R2
–V
C1
R4
IN+
GND
R4
–V
C2
Place components
C1
C2
Use a low-ESR,
ceramic bypass
capacitor
close to device and to
each other to reduce
parasitic errors
图8-7. Operational Amplifier Board Layout for Difference Amplifier Configuration
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support
9.1.1.1 PSpice® for TI
PSpice® for TI 是可帮助评估模拟电路性能的设计和仿真环境。在进行布局和制造之前创建子系统设计和原型解决
方案，可降低开发成本并缩短上市时间。
9.1.1.2 TINA-TI™ 仿真软件（免费下载）
TINA-TI™ 仿真软件是一款简单易用、功能强大且基于 SPICE 引擎的电路仿真程序。TINA-TI 仿真软件是 TINA™
软件的一款免费全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。TINA-TI 仿
真软件提供所有传统的SPICE 直流、瞬态和频域分析，以及其他设计功能。
TINA-TI 仿真软件提供全面的后处理能力，便于用户以多种方式获得结果，用户可从设计工具和仿真网页免费下
载。虚拟仪器提供选择输入波形和探测电路节点、电压以及波形的能力，从而构建一个动态的快速启动工具。
备注
必须安装 TINA 软件或者 TINA-TI 软件后才能使用这些文件。请从 TINA-TI™ 软件文件夹中下载免费的
TINA-TI 仿真软件。
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Zero-drift Amplifiers: Features and Benefits application brief
• Texas Instruments, The PCB is a component of op amp design application note
• Texas Instruments, Operational amplifier gain stability, Part 3: AC gain-error analysis
• Texas Instruments, Operational amplifier gain stability, Part 2: DC gain-error analysis
• Texas Instruments, Using infinite-gain, MFB filter topology in fully differential active filters application note
• Texas Instruments, Op Amp Performance Analysis
• Texas Instruments, Single-Supply Operation of Operational Amplifiers application note
• Texas Instruments, Shelf-Life Evaluation of Lead-Free Component Finishes application note
• Texas Instruments, Feedback Plots Define Op Amp AC Performance application note
• Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application note
• Texas Instruments, Analog Linearization of Resistance Temperature Detectors application note
• Texas Instruments, TI Precision Design TIPD102 High-Side Voltage-to-Current (V-I) Converter
9.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.5 Trademarks
TINA-TI™ and TI E2E™ are trademarks of Texas Instruments.
TINA™ is a trademark of DesignSoft, Inc.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
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PSpice® is a registered trademark of Cadence Design Systems, Inc.
所有商标均为其各自所有者的财产。
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA186DBVR
OPA186DBVT
OPA2186DDFR
OPA2186DR
ACTIVE
ACTIVE
SOT-23
SOT-23
DBV
DBV
DDF
D
5
5
3000 RoHS & Green
250 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
31CQ
31CQ
2MZ3
Samples
Samples
Samples
Samples
Samples
SN
ACTIVE SOT-23-THIN
8
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
ACTIVE
ACTIVE
SOIC
SOIC
8
O2186
OPA4186DR
D
14
OPA4186
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Mar-2023
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Dec-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA186DBVR
OPA186DBVT
OPA2186DDFR
SOT-23
SOT-23
DBV
DBV
DDF
5
5
8
3000
250
178.0
178.0
180.0
9.0
9.0
8.4
3.3
3.3
3.2
3.2
3.2
3.2
1.4
1.4
1.4
4.0
4.0
4.0
8.0
8.0
8.0
Q3
Q3
Q3
SOT-23-
THIN
3000
OPA2186DR
OPA4186DR
SOIC
SOIC
D
D
8
3000
3000
330.0
330.0
12.4
16.4
6.4
6.5
5.2
9.0
2.1
2.1
8.0
8.0
12.0
16.0
Q1
Q1
14
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Dec-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA186DBVR
OPA186DBVT
OPA2186DDFR
OPA2186DR
SOT-23
SOT-23
DBV
DBV
DDF
D
5
5
3000
250
190.0
190.0
210.0
356.0
356.0
190.0
190.0
185.0
356.0
356.0
30.0
30.0
35.0
35.0
35.0
SOT-23-THIN
SOIC
8
3000
3000
3000
8
OPA4186DR
SOIC
D
14
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.38
0.22
8X
0.1
C A B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/C 10/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/C 10/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/C 10/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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