OPA2130 [TI]
Low Power, Precision FET-INPUT OPERATIONAL AMPLIFIERS; 低功耗，高精度FET输入运算放大器
| 型号： | OPA2130 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Low Power, Precision FET-INPUT OPERATIONAL AMPLIFIERS |
| 文件： | 总16页 (文件大小：698K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
O
O
P
A
2
1
OPA130
OPA2130
OPA4130
P
A
1
3
O
3
0
0
P
A
4
1
3
0
O
O
P
P
A
A
2
1
1
3
3
0
0
O
P
A41
3
0
SBOS053A – MAY 1998 – REVISED MARCH 2006
Low Power, Precision
FET-INPUT OPERATIONAL AMPLIFIERS
FEATURES
OPA130
● LOW QUIESCENT CURRENT: 530µA/amp
● LOW OFFSET VOLTAGE: 1mV max
● HIGH OPEN-LOOP GAIN: 120dB min
● HIGH CMRR: 90dB min
Offset Trim
1
2
3
4
8
7
6
5
NC
–In
+In
V–
V+
Output
Offset Trim
● FET INPUT: IB = 20pA max
● EXCELLENT BANDWIDTH: 1MHz
● WIDE SUPPLY RANGE: ±2.25 to ±18V
● SINGLE, DUAL, AND QUAD VERSIONS
DIP-8, SO-8
OPA2130
DESCRIPTION
Out A
–In A
+In A
V–
1
2
3
4
8
7
6
5
V+
The OPA130 series of FET-input op amps combine precision
dc performance with low quiescent current. Single, dual, and
quad versions have identical specifications for maximum
design flexibility. They are ideal for general-purpose, por-
table, and battery operated applications, especially with high
source impedance.
A
Out B
–In B
+In B
B
DIP-8, SO-8
OPA4130
OPA130 op amps are easy to use and free from phase
inversion and overload problems often found in
common FET-input op amps. Input cascode circuitry pro-
vides excellent common-mode rejection and maintains low
input bias current over its wide input voltage range. OPA130
series op amps are stable in unity gain and provide excellent
dynamic behavior over a wide range of load conditions,
including high load capacitance. Dual and quad designs
feature completely independent circuitry for lowest crosstalk
and freedom from interaction, even when overdriven or
overloaded.
Out A
–In A
+In A
V+
1
2
3
4
5
6
7
14 Out D
13 –In D
12 +In D
11 V–
A
B
D
C
+In B
–In B
Out B
10 +In C
Single and dual versions are available in DIP-8 and SO-8
surface-mount packages. Quad is available in DIP-14 and
SO-14 surface-mount packages. All are specified for
–40°C to +85°C operation.
9
8
–In C
Out C
DIP-14, SO-14
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1998-2006, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
Supply Voltage, V+ to V–.................................................................... 36V
Input Voltage .....................................................(V–) –0.7V to (V+) +0.7V
Output Short-Circuit(2) .............................................................. Continuous
Operating Temperature ..................................................–40°C to +125°C
Storage Temperature .....................................................–40°C to +125°C
Junction Temperature ...................................................................... 150°C
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability. (2) Short-circuit to ground, one amplifier per package.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see
the Package Option Addendum at the end of this document,
or see the TI web site at www.ti.com.
OPA130, OPA2130, OPA4130
2
SBOS053A
www.ti.com
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VS = ±15V, and RL = 10kΩ, unless otherwise noted.
OPA130PA, UA
OPA2130PA, UA
OPA4130PA, UA
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
OFFSET VOLTAGE
Input Offset Voltage
±0.2
±2
2
±1
±10
20
mV
µV/°C
µV/V
µV/V
vs Temperature(1)
Operating Temperature Range
vs Power Supply
Channel Separation (dual and quad)
VS = ±2.25V to ±18V
0.3
INPUT BIAS CURRENT(2)
Input Bias Current
vs Temperature
VCM = 0V
VCM = 0V
+5
±20
pA
pA
See Typical Characteristics
Input Offset Current
±2
±20
NOISE
Input Voltage Noise
Noise Density, f = 10Hz
f = 100Hz
f = 1kHz
f = 10kHz
Current Noise Density, f = 1kHz
30
18
16
16
4
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
fA/√Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range, Positive
Negative
(V+)–2
(V–)+2
90
(V+)–1.5
(V–)+1.2
105
V
V
dB
Common-Mode Rejection
VCM = –13V to +13V
VCM = –13V to +13V
INPUT IMPEDANCE
Differential
Common-Mode
1013 || 1
1013 || 3
Ω || pF
Ω || pF
OPEN-LOOP GAIN
Open-loop Voltage Gain
VO = –13.8V to +13V
RL = 2kΩ, VO = –13V to +12V
120
120
135
135
dB
dB
FREQUENCY RESPONSE
Gain-Bandwidth Product
Slew Rate
Settling Time: 0.1%
0.01%
1
MHz
V/µs
µs
µs
µs
2
5.5
7
G = 1, 10V Step, CL = 100pF
G = 1, 10V Step, CL = 100pF
G = 1, VIN = ±15V
Overload Recovery Time
Total Harmonic Distortion + Noise
2
1kHz, G = 1, VO = 3.5Vrms
0.0003
%
OUTPUT
Voltage Output, Positive
Negative
(V+)–2
(V–)+1.2
(V+)–3
(V+)–1.5
(V–)+1
(V+)–2.5
(V–)+1.5
±18
V
V
V
V
mA
nF
Positive
Negative
RL = 2kΩ
RL = 2kΩ
(V–)+2
Short-Circuit Current
Capacitive Load Drive (Stable Operation)
10
POWER SUPPLY
Specified Operating Voltage
Operating Voltage Range
Quiescent Current (per amplifier)
±15
V
V
µA
±2.25
±18
±650
IO = 0
±530
TEMPERATURE RANGE
Operating Range
Storage
–40
–40
+85
+125
°C
°C
Thermal Resistance, θJA
DIP-8
100
150
80
°C/W
°C/W
°C/W
°C/W
SO-8 Surface-Mount
DIP-14
SO-14 Surface-Mount
110
NOTES: (1) Ensured by wafer test. (2) High-speed test at TJ = 25°C.
OPA130, OPA2130, OPA4130
SBOS053A
3
www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = ±15V, and RL = 10kΩ, unless otherwise noted.
POWER SUPPLY AND COMMON-MODE REJECTION
vs FREQUENCY
OPEN-LOOP GAIN/PHASE vs FREQUENCY
120
110
100
90
80
70
60
50
40
30
20
10
0
120
100
80
0
–PSR
–45
–90
–135
–180
CL = 100pF
φ
CMR
60
+PSR
40
20
G
0
–20
10
100
1k
10k
100k
1M
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
INPUT VOLTAGE AND CURRENT NOISE
SPECTRAL DENSITY vs FREQUENCY
CHANNEL SEPARATION vs FREQUENCY
1k
1k
160
140
120
100
80
100
100
10
Voltage Noise
Dual and quad devices.
G = 1, all channels.
Quad measured channel
A to D or B to C—other
combinations yield improved
rejection.
10
1
RL = 10kΩ
Current Noise
1
1
10
100
1k
10k
100k
1M
10
100
1k
Frequency (Hz)
10k
100k
Frequency (Hz)
INPUT BIAS CURRENT
vs INPUT COMMON-MODE VOLTAGE
INPUT BIAS AND INPUT OFFSET CURRENT
vs TEMPERATURE
10
10k
1k
VCM = 0V
100
10
IB
IOS
5
1
0.1
0.01
0
–15
–10
–5
0
5
10
15
–75
–50
–25
0
25
50
75
100
125
Common-Mode Voltage (V)
Ambient Temperature (°C)
OPA130, OPA2130, OPA4130
4
SBOS053A
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = ±15V, and RL = 10kΩ, unless otherwise noted.
QUIESCENT CURRENT AND SHORT-CIRCUIT CURRENT
vs TEMPERATURE
AOL, CMR, PSR vs TEMPERATURE
0.65
40
35
30
25
20
15
10
140
130
120
110
100
0.60
0.55
0.50
0.45
0.40
0.35
IQ
Open-Loop
Gain
IS–C
PSR
IS+C
CMR
–75
–50
–25
0
25
50
75
100
125
–75
–50
–25
0
25
50
75
100
125
Temperature (°C)
Ambient Temperature (°C)
OFFSET VOLTAGE
OFFSET VOLTAGE DRIFT
PRODUCTION DISTRIBUTION
PRODUCTION DISTRIBUTION
15
10
5
20
18
16
14
12
10
8
6
4
2
0
0
Offset Voltage Drift (µV/°C)
Offset Voltage (µV)
TOTAL HARMONIC DISTORTION + NOISE
vs FREQUENCY
MAXIMUM OUTPUT VOLTAGE
vs FREQUENCY
0.1
0.01
30
25
20
15
10
5
VS = ±15V
Maximum output voltage
without slew-rate induced
distortion
G = +10
0.001
VS = ±5V
RL = 10kΩ
RL = 2kΩ
G = +1
VS = ±2.25V
0.0001
0
100
1k
10k
100k
10k
100k
Frequency (Hz)
1M
Frequency (Hz)
OPA130, OPA2130, OPA4130
SBOS053A
5
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = ±15V, and RL = 10kΩ, unless otherwise noted.
SMALL-SIGNAL STEP RESPONSE
G = 1, CL = 1000pF
SMALL-SIGNAL STEP RESPONSE
G =1, CL = 100pF
5µs/div
500ns/div
LARGE-SIGNAL STEP RESPONSE
G = 1, CL = 100pF
SETTLING TIME vs GAIN
0.01%
100
10
1
0.1%
5µs/div
±1
±10
±100
Gain (V/V)
SMALL-SIGNAL OVERSHOOT
vs LOAD CAPACITANCE
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
15
80
14
13
G = +1
70
60
50
40
30
20
10
0
–55°C
12
11
10
+125°C
+25°C
–10
–11
–12
–13
–14
–15
+125°C
G = –1
+85°C
G = ±5
+25°C
–55°C
0
±5
±10
Output Current (mA)
±15
±20
10pF
100pF
1nF
10nF
100nF
Load Capacitance (F)
OPA130, OPA2130, OPA4130
6
SBOS053A
www.ti.com
APPLICATIONS INFORMATION
V+
Trim Range: ±5mV typ
OPA130 series op amps are unity-gain stable and suitable
for a wide range of general-purpose applications. Power
supply pins should be bypassed with 10nF ceramic capaci-
tors or larger.
10nF
100kΩ
7
1
2
3
OPA130 op amps are free from unexpected output phase-
reversal common with FET op amps. Many FET-input op
amps exhibit phase-reversal of the output when the input
common-mode voltage range is exceeded. This can occur in
voltage-follower circuits, causing serious problems in
control loop applications. OPA130 series op amps are free
from this undesirable behavior. All circuitry is completely
independent in dual and quad versions, assuring normal
behavior when one amplifier in a package is overdriven or
short-circuited.
5
6
OPA130
OPA130 single op amp only.
Use offset adjust pins only to null
offset voltage of op amp—see text.
4
10nF
V–
FIGURE 1. OPA130 Offset Voltage Trim Circuit.
INPUT BIAS CURRENT
OPERATING VOLTAGE
The input bias current is approximately 5pA at room tem-
perature and increases with temperature as shown in the
Typical Characteristic curve Input Bias Current vs Tempera-
ture.
OPA130 series op amps operate with power supplies from
±2.25V to ±18V with excellent performance. Although speci-
fications are production tested with ±15V supplies, most
behavior remains unchanged throughout the full operating
voltage range. Parameters which vary significantly with
operating voltage are shown in the typical performance
curves.
Input stage cascode circuitry assures that the input bias
current remains virtually unchanged throughout the full input
common-mode range of the OPA130. See the Typical
Characteristic curve Input Bias Current vs Common-Mode
Voltage.
OFFSET VOLTAGE TRIM
Offset voltage of OPA130 series amplifiers is laser trimmed
and usually requires no user adjustment. The OPA130
(single op amp version) provides offset voltage trim con-
nections on pins 1 and 5. Offset voltage can be adjusted by
connecting a potentiometer as shown in Figure 1. This
adjustment should be used only to null the offset of the op
amp, not to adjust system offset or offset produced by the
signal source. Nulling offset that is not produced by the
amplifier will change the offset voltage drift behavior of the
op amp.
OPA130, OPA2130, OPA4130
SBOS053A
7
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
PDIP
SOIC
Drawing
OPA130PA
OPA130UA
OBSOLETE
ACTIVE
P
D
8
8
TBD
Call TI
Call TI
100
2500
2500
100
Pb-Free
(RoHS)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
OPA130UA/2K5
OPA130UA/2K5E4
OPA130UAE4
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
D
D
D
8
8
8
Pb-Free
(RoHS)
Pb-Free
(RoHS)
Pb-Free
(RoHS)
OPA2130PA
OPA2130UA
OBSOLETE
ACTIVE
PDIP
SOIC
P
D
8
8
TBD
Call TI
Call TI
100
2500
2500
100
Pb-Free
(RoHS)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
OPA2130UA/2K5
OPA2130UA/2K5E4
OPA2130UAE4
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
D
D
D
8
8
8
Pb-Free
(RoHS)
Pb-Free
(RoHS)
Pb-Free
(RoHS)
OPA4130PA
OPA4130UA
OBSOLETE
ACTIVE
PDIP
SOIC
N
D
14
14
TBD
Call TI
Call TI
58
2500
2500
58
Pb-Free
(RoHS)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
OPA4130UA/2K5
OPA4130UA/2K5E4
OPA4130UAE4
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
D
D
D
14
14
14
Pb-Free
(RoHS)
Pb-Free
(RoHS)
Pb-Free
(RoHS)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2007
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
(mm)
12
OPA130UA/2K5
OPA2130UA/2K5
OPA4130UA/2K5
D
D
D
8
8
SITE 41
SITE 41
SITE 41
6.9
6.9
6.5
5.4
5.4
9.5
2.0
2.0
2.1
8
8
8
12
12
16
Q1
Q1
Q1
330
12
14
330
16
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
OPA130UA/2K5
OPA2130UA/2K5
OPA4130UA/2K5
D
D
D
8
8
SITE 41
SITE 41
SITE 41
346.0
346.0
346.0
346.0
346.0
346.0
29.0
29.0
33.0
14
Pack Materials-Page 2
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.430 (10,92)
MAX
0.010 (0,25)
M
0.015 (0,38)
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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