OPA2156 [TI]
低噪声 (3nV/√Hz @10kHz)、高速（25MHz、40V/µs）、CMOS 精密 RRIO 双路运算放大器;
| 型号： | OPA2156 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 低噪声 (3nV/√Hz @10kHz)、高速（25MHz、40V/µs）、CMOS 精密 RRIO 双路运算放大器 放大器 运算放大器 |
| 文件： | 总37页 (文件大小：1761K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA2156
ZHCSIQ3B –SEPTEMBER 2018–REVISED JUNE 2019
OPA2156 36V 超低噪声、高带宽、CMOS、精密轨至轨
运算放大器
1 特性
3 说明
1
•
超低噪声：10kHz 时为 3nV/√Hz
低失调电压：±25µV
OPA2156 是计划推出的新一代 36V 轨至轨运算放大
器中的第一款。
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低失调电压温漂：±0.5µV/°C
低偏置电流：±5pA
这款器件具有非常低的失调电压 (±25μV)、漂移
(±0.5μV/°C) 和低偏置电流 (±5pA)，同时还具有非常低
的宽带电压噪声 (3nV/√Hz)。
共模抑制：120dB
低噪声：10kHz 时为 3nV/√Hz
高带宽：25MHz GBW
OPA2156 拥有 独特特性，例如轨至轨输入和输出电压
范围、宽带宽 (25MHz)、高输出电流 (100mA) 和高压
摆率 (40V/µs)，是一款功能强大、性能出色的运算放
大器，适用于高压精密工业 应用中节省电路板空间。
开环电压增益：154dB
高输出电流：100mA
轨至轨输入和输出
高压摆率：40V/µs
OPA2156 运算放大器可提供 8 引脚 SOIC 和 VSSOP
封装，可在 –40°C 至 +125°C 的工业温度范围内正常
工作。
较短的建立时间：600ns（10V 阶跃，0.01%）
宽电源电压范围：±2.25V 至 ±18V，4.5V 至 36V
行业标准封装：
器件信息(1)
–
SOIC-8 和 VSSOP-8 双列封装
器件型号
OPA2156
封装
SOIC (8)
VSSOP (8)
封装尺寸（标称值）
4.90mm × 3.90mm
3.00mm × 3.00mm
2 应用
•
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数据采集 (DAQ)
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
光电二极管跨阻放大器
振动监控器模块
模拟输入模块
高分辨率 ADC 驱动器放大器
医疗设备
低输入电压噪声频谱密度
OPA2156 跨阻配置
1000
100
10
Vœ
-
OPA2156
Vout
+
1
100m
1
10
100
1k
Frequency (Hz)
10k
100k
1M
10M
V+
D008
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS900
OPA2156
ZHCSIQ3B –SEPTEMBER 2018–REVISED JUNE 2019
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information: OPA2156 ................................ 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 19
8
9
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application .................................................. 21
Power Supply Recommendations...................... 23
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 24
11 器件和文档支持 ..................................................... 25
11.1 器件支持................................................................ 25
11.2 文档支持................................................................ 25
11.3 接收文档更新通知 ................................................. 25
11.4 社区资源................................................................ 25
11.5 商标....................................................................... 25
11.6 静电放电警告......................................................... 26
11.7 Glossary................................................................ 26
12 机械、封装和可订购信息....................................... 26
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (December 2018) to Revision B
Page
•
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•
已添加 向数据表中添加了新的 DGK (VSSOP) 封装和相关内容............................................................................................. 1
已更改 Figure 8, Input Voltage Noise Spectral Density, to include frequencies up to 10 MHz.............................................. 8
已更改 title of input bias and offset current curves (Figures 12 to 14) to specify SOIC package performance .................... 9
Changes from Original (September 2018) to Revision A
Page
•
首次发布生产数据数据表 ........................................................................................................................................................ 1
2
Copyright © 2018–2019, Texas Instruments Incorporated
OPA2156
www.ti.com.cn
ZHCSIQ3B –SEPTEMBER 2018–REVISED JUNE 2019
5 Pin Configuration and Functions
D and DGK Packages
8-Pin SOIC and 8-Pin VSSOP
Top View
OUT A
œIN A
+IN A
Vœ
1
2
3
4
8
7
6
5
V+
OUT B
œIN B
+IN B
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
+IN A
+IN B
–IN A
–IN B
OUT A
OUT B
V+
NO.
3
I
I
Noninverting input, channel A
Noninverting input, channel B
Inverting input, channel A
Inverting input, channel B
Output, channel A
5
2
I
6
I
1
O
O
—
—
7
Output, channel B
8
Positive (highest) power supply
Negative (lowest) power supply
V–
4
Copyright © 2018–2019, Texas Instruments Incorporated
3
OPA2156
ZHCSIQ3B –SEPTEMBER 2018–REVISED JUNE 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
±20
Supply voltage, VS = (V+) – (V–)
V
(+40, single supply)
Common-mode
Voltage
(V–) – 0.5
(V+) + 0.5
0.5
V
Signal input pins
Differential
Current
±10
mA
Output short circuit(2)
Temperature
Continuous
Operating junction
Storage, Tstg
–40
–65
150
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extendedperiods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
±3000
±1000
UNIT
V
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5 (±2.25)
–40
NOM
MAX
36 (±18)
125
UNIT
V
Supply voltage, VS = (V+) – (V–)
Specified temperature (SOIC)(1)
°C
(1) Please see Thermal Considerations section for information on ambient vs device junction temperature
6.4 Thermal Information: OPA2156
OPA2156
THERMAL METRIC(1)
8 PINS
UNIT
D (SOIC)
119.2
51.1
DGK (VSSOP)
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
163.8
52.5
86.5
5.1
°C/W
°C/W
°C/W
°C/W
°C/W
64.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
9.7
ψJB
63.5
84.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2018–2019, Texas Instruments Incorporated
OPA2156
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ZHCSIQ3B –SEPTEMBER 2018–REVISED JUNE 2019
6.5 Electrical Characteristics
at TA = 25°C, VS = ±2.25V to ±18V, VCM =VOUT = VS / 2, and RL = 2 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
±25
±200
±300
µV
µV
Input offset voltage,
PMOS
VOS
TA = –40°C to +85°C
TA = –40°C to +125°C
VCM = (V+) – 1.25 V
See Typical Characteristics
±0.25
±3
±5
mV
mV
Input offset voltage,
NMOS
VOS
VCM = (V+) – 1.25 V, TA = –40°C to +125°C (SOIC)
VCM = (V+) – 1.25 V, TA = –40°C to +105°C (MSOP)
PMOS, SOIC
Input offset voltage drift PMOS, MSOP
NMOS, VCM = (V+) – 1.25 V
TA = –40°C to +125°C
±0.5
±3
dVOS/dT
PSRR
TA = –40°C to +105°C
TA = –40°C to +125°C
µV/°C
µV/V
±1
±0.3
±4.5
±5
Power-supply rejection
ratio
TA = –40°C to +125°C (SOIC)
TA = –40°C to +105°C (MSOP)
INPUT BIAS CURRENT
SOIC
±5
±5
±40
±80
±1.5
±15
pA
pA
nA
nA
nA
pA
nA
nA
nA
MSOP
IB
Input bias current
TA = –40°C to +85°C (SOIC)
TA = –40°C to +85°C (MSOP)
TA = –40°C to +125°C
See Typical Characteristics
±2
±40
±1.5
±2.5
TA = –40°C to +85°C (SOIC)
TA = –40°C to +85°C (MSOP)
TA = –40°C to +125°C
IOS
Input offset current
Input voltage noise
See Typical Characteristics
NOISE
(V–) < VCM < (V+) – 2.25 V
(V+) – 1.25 V < VCM < (V+)
f = 0.1 Hz to 10 Hz
f = 0.1 Hz to 10 Hz
f = 100 Hz
1.9
3.4
12.0
4
En
µVPP
Input voltage noise
density
en
(V–) < VCM < (V+) – 2.25 V
f = 1 kHz
f = 10 kHz
3.0
13.0
9.7
4.0
nV/√Hz
f = 100 Hz
Input voltage noise
density
en
(V+) – 1.25 V < VCM < (V+)
f = 1 kHz
f = 1 kHz
f = 10 kHz
Input current noise
density
in
19
fA/√Hz
INPUT VOLTAGE
Common-mode voltage
range
VCM
(V–) – 0.1
106
(V+) + 0.1
V
Common-mode
rejection ratio, PMOS
CMRR
CMRR
CMRR
CMRR
CMRR
CMRR
(V–) < VCM < (V+) – 2.25 V, VS = ±18 V
TA = –40°C to +125°C (SOIC)
120
120
Common-mode
rejection ratio, PMOS
100
82
Common-mode
rejection ratio, PMOS
TA = –40°C to +105°C (MSOP)
(V+) – 1.25 V < VCM < (V+), VS = ±18 V
TA = –40°C to +125°C (SOIC)
dB
Common-mode
rejection ratio, NMOS
Common-mode
rejection ratio, NMOS
74
Common-mode
rejection ratio, NMOS
TA = –40°C to +105°C (MSOP)
Copyright © 2018–2019, Texas Instruments Incorporated
5
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ZHCSIQ3B –SEPTEMBER 2018–REVISED JUNE 2019
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Electrical Characteristics (continued)
at TA = 25°C, VS = ±2.25V to ±18V, VCM =VOUT = VS / 2, and RL = 2 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT IMPEDANCE
ZID
ZIC
Differential
100 || 9.1
6 || 1.9
MΩ || pF
1012Ω ||
pF
Common-mode
OPEN-LOOP GAIN
(V–) + 0.6 V < VO < (V+) – 0.6 V, VS = ±18 V (SOIC)
130
128
126
154
154
AOL
Open-loop voltage gain (V–) + 0.6 V < VO < (V+) – 0.6 V, VS = ±18 V (MSOP)
TA = –40°C to +85°C
dB
FREQUENCY RESPONSE
GBW
Unity gain bandwidth
Gain bandwidth product G = 100
20
25
MHz
MHz
V/µs
ns
SR
ts
Slew rate
VS = ±18 V, G = –1, 10-V step
To 0.01%, CL = 20 pF
40
Settling time
VS = ±18 V, G = –1, 10-V step
600
100
–132
tOR
Overload recovery time G = –10
ns
dB
G = 1, f = 1 kHz, VO = 3.5 VRMS
0.000025
%
Total harmonic
distortion + noise
THD+N
–126
0.00005%
150
dB
G = 1, f = 20 kHz, VO = 3.5 VRMS
dc
dB
dB
Crosstalk
f = 100 kHz
120
OUTPUT
Voltage output swing
from power supply
VO
200
100
250
mV
ISC
CL
Short-circuit current
Capacitive load drive
VS = ±18 V
mA
pF
See Typical Characteristics
25
Open-loop output
impedance
ZO
f = 1 MHz, IO = 0 A
Ω
POWER SUPPLY
4.4
5.2
5.2
mA
mA
mA
Quiescent current per
amplifier
IQ
IO = 0 A
TA = –40°C to +125°C (SOIC)
TA = –40°C to +105°C (MSOP)
TEMPERATURE
Thermal protection
Thermal hysteresis
170
15
°C
°C
6
版权 © 2018–2019, Texas Instruments Incorporated
OPA2156
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ZHCSIQ3B –SEPTEMBER 2018–REVISED JUNE 2019
6.6 Typical Characteristics
表 1. Table of Graphs
DESCRIPTION
FIGURE
图 1
Offset Voltage Production Distribution
Offset Voltage vs Temperature (PMOS)
Offset Voltage vs Temperature (NMOS)
Offset Voltage vs Power Supply
图 2
图 3
图 4
Offset Voltage vs Common-Mode Voltage
图 5
Offset Voltage vs Common-Mode Voltage in Transition Region
Offset Voltage Drift
图 6
图 7
Input Voltage Noise Spectral Density
0.1-Hz to 10-Hz Noise
图 8
图 9
THD+N vs Frequency
图 10
图 11
图 12
图 13
图 14
图 15
图 16
图 17
图 18
图 19
图 20
图 21
图 22
图 23
图 24
图 26
图 25
图 27
图 28
图 29
图 30
图 31
图 32
图 33
图 34
图 35
图 36
图 37
图 38
图 39
图 40
图 41
THD+N vs Output Amplitude
Input Bias and Offset Current vs Common-Mode Voltage
Input Bias and Offset Current vs Temperature
Input Bias and Offset Current vs Temperature
Open-Loop Output Impedance vs Frequency
Maximum Output Voltage vs Frequency
Open-Loop Gain and Phase Vs Frequency
Open-Loop Gain vs Temperature
Closed-Loop Gain vs Frequency
CMRR vs Frequency
PSRR vs Frequency
CMRR vs Temperature
PSRR vs Temperature
Positive Output Voltage vs Output Current
Negative Output Voltage vs Output Current
Short-Circuit Current vs Temperature
No Phase Reversal
Phase Margin vs Capacitive Load
Small-Signal Overshoot vs Capacitive Load (G = –1)
Small-Signal Overshoot vs Capacitive Load (G= +1)
Settling Time
Negative Overload Recovery
Positive Overload Recovery
Small-Signal Step Response (Noninverting)
Small-Signal Step Response (Inverting)
Large-Signal Step Response (Noninverting)
Large-Signal Step Response (Inverting)
Quiescent Current vs Supply Voltage
Quiescent Current vs Temperature
Channel Separation vs Frequency
EMIRR vs Frequency
版权 © 2018–2019, Texas Instruments Incorporated
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OPA2156
ZHCSIQ3B –SEPTEMBER 2018–REVISED JUNE 2019
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 30 pF (unless otherwise noted)
18%
15%
12%
9%
6%
3%
0
200
150
100
50
5 Typical Units Shown
0
-50
-100
-150
-200
-200 -160 -120 -80 -40
0
40
80 120 160 200
-50
-25
0
25
50
75
100
125
Offset Voltage (mV)
Temperature (èC)
TA = 25°C
PMOS region
图 1. Offset Voltage Production Distribution
图 2. Offset Voltage vs Temperature (PMOS)
1.5
1
150
100
50
5 Typical Units Shown
5 Typical Units Shown
0.5
0
0
-0.5
-1
-50
-100
-150
-1.5
-50
-25
0
25
50
75
100
125
4
8
12
16
20
24
Supply Voltage (V)
28
32
36
Temperature (èC)
NMOS region
图 3. Offset Voltage vs Temperature (NMOS)
图 4. Offset Voltage vs Power Supply
5 Typical Units Shown
2.2
1.8
1.4
1
40
30
85 èC
25 èC
20
0.6
0.2
-0.2
-0.6
-1
10
0
-10
-20
-30
-40
Vcm = 15.75V
Vcm = 16.75V
-40 èC
-1.4
-1.8
-2.2
-18
-14
-10
Input Common-mode Voltage (V)
-6
-2
2
6
10
14
14
14.5
15
Input Common-mode Voltage (V)
15.5
16
16.5
17
17.5
18
Transition between PMOS and NMOS regions
图 5. Offset Voltage vs Common-Mode Voltage
图 6. Offset Voltage vs Common-Mode Voltage in Transition
Region
8
版权 © 2018–2019, Texas Instruments Incorporated
OPA2156
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ZHCSIQ3B –SEPTEMBER 2018–REVISED JUNE 2019
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 30 pF (unless otherwise noted)
30%
25%
20%
15%
10%
5%
1000
100
10
1
100m
0
1
10
100
1k
Frequency (Hz)
10k
100k
1M
10M
-3 -2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
3
Offset Voltage Drift (uV/èC)
D008
TA = –40°C to +125°C
图 7. Offset Voltage Drift
图 8. Input Voltage Noise Spectral Density
0.001
-100
G +1, RLoad = 10KW
G +1, RLoad = 2KW
G -1, RLoad = 10KW
G -1, RLoad = 2KW
0.0001
-120
1E-5
-140
100
1k
Frequency (Hz)
10k
Time (1 s/div)
3.5 VRMS, 80-kHz measurement bandwidth
图 9. 0.1-Hz to 10-Hz Noise
图 10. THD+N vs Frequency
0.1
-60
100
80
G +1, RLoad = 10KW
G +1, RLoad = 2KW
G -1, RLoad = 10KW
G -1, RLoad = 2KW
Ib+
60
0.01
-80
Ib-
40
20
0
0.001
0.0001
1E-5
-100
-120
-140
-20
-40
-60
-80
-100
Ios
-20 -16 -12
-8
-4
0
4
8
Input Common-mode Voltage (V)
12
16
20
10m
100m 1
Output Amplitude (VRMS
10
)
1 kHz, 80-kHz measurement bandwidth
图 12. Input Bias and Offset Current vs Common-Mode
图 11. THD+N vs Output Amplitude
Voltage (SOIC)
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ZHCSIQ3B –SEPTEMBER 2018–REVISED JUNE 2019
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 30 pF (unless otherwise noted)
1.4
1.2
1
45
35
25
15
5
Ib+
0.8
0.6
0.4
0.2
0
Ib-
Ios
-0.2
-5
-60
-40
-20
0
20
40
60
80
100
50
60
70
80
90
100
110
120
130
Temperature (èC)
Temperature (èC)
TA = –55°C to +85°C
TA = –55°C to +125°C
图 13. Input Bias and Offset Current vs Temperature (SOIC)
图 14. Input Bias and Offset Current vs Temperature (SOIC)
100
50
Vs=ê18 V
Vs=ê5 V
Vs=ê2.25 V
40
10
30
20
10
0
1
0.1
1
10
100
1k 10k 100k
Frequency (Hz)
1M
10M 100M
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
图 15. Open-Loop Output Impedance vs Frequency
240
Gain
图 16. Maximum Output Voltage vs Frequency
160
140
120
100
80
170
160
150
140
130
120
210
180
150
120
90
Phase
0.01
0.1
1
Vs = 36V
60
40
60
20
30
Vs = 4.5V
0
0
-20
-30
-40
-20
0
20
40
60
80
100 120 140
100m
1
10
100 1k 10k 100k 1M 10M
Frequency (Hz)
Temperature (èC)
图 18. Open-Loop Gain vs Temperature
图 17. Open-Loop Gain and Phase vs Frequency
10
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 30 pF (unless otherwise noted)
50
40
30
20
10
0
140
120
100
80
G = +1
G= -1
G= +10
G= +100
CMRR
60
40
-10
-20
20
0
100
1k
10k 100k
Frequency (Hz)
1M
10M
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
图 19. Closed-Loop Gain vs Frequency
图 20. CMRR vs Frequency
160
140
120
100
80
122
120
118
116
114
PSRR+
PSRR-
60
40
20
0
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
图 21. PSRR vs Frequency
图 22. CMRR vs Temperature
25 èC
140
135
130
125
120
0.1
0.32
1
18
17.5
17
16.5
16
-40 èC
15.5
15
125 èC
85 èC
14.5
14
13.5
13
12.5
12
-50
-25
0
25
50
75
100
125
0
10 20 30 40 50 60 70 80 90 100 110 120
Output Current (mA)
Temperature (èC)
图 23. PSRR vs Temperature
图 24. Positive Output Voltage vs Output Current
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 30 pF (unless otherwise noted)
-12
-12.5
-13
140
120
100
80
-13.5
-14
85 èC
125 èC
-14.5
-15
-15.5
-16
-16.5
-17
-40 èC
25 èC
-17.5
-18
60
-40
-20
0
20
40
60
80
100
120
0
20
40
60 80
Output Current (mA)
100
120
140
Temperature (èC)
图 25. Short-Circuit Current vs Temperature
图 26. Negative Output Voltage vs Output Current
80
70
60
50
40
30
20
10
0
Vin (V)
Vout (V)
10
100
Cload (pF)
1000
Time (100 ms/div)
图 27. No Phase Reversal
图 28. Phase Margin vs Capacitive Load
100
90
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
RISO = 0
RISO = 25
RISO = 50
RISO = 0
RISO = 25
RISO = 50
10
100
Capactiance (pF)
1000
10
100
Capactiance (pF)
1000
10-mV output step, gain = –1
10-mV output step, gain = +1
图 29. Small Signal Overshoot vs Capacitive Load
图 30. Small Signal Overshoot vs Capacitive Load
12
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 30 pF (unless otherwise noted)
Falling
Rising
VIN
VOUT
Time (200 ns/div)
Time (200 ns/div)
Vin = 5-Vpp
Gain = –10
图 31. Normalized Settling Time
图 32. Negative Overload Recovery
VIN
VOUT
VIN
VOUT
Time (200 ns/div)
Time (1 ms/div)
Gain = –10
Vin = 10 mVpp, gain = 1
图 33. Positive Overload Recovery
图 34. Small-Signal Step Response (Noninverting)
VIN
VOUT
Vin
Vout
Time (1 ms/div)
Time (1 ms/div)
Vin = 10 mVpp, gain = –1
Vin = 5 Vpp, gain = 1
图 35. Small-Signal Step Response (Inverting)
图 36. Large-Signal Step Response (Noninverting)
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 30 pF (unless otherwise noted)
5
Vin
Vout
4.5
4
3.5
Vs = 4.5V
3
2.5
2
Time (1 ms/div)
0
4
8
12
16
20
Supply Voltage (V)
24
28
32
36
Vin = 5 Vpp, gain = –1
图 37. Large Signal Step Response (Inverting)
图 38. Quiescent Current vs Supply Voltage
4.44
4.41
4.38
4.35
4.32
4.29
4.26
4.23
4.2
-60
-80
-100
-120
-140
-160
-180
Vs = 36V
Vs = 4.5V
4.17
4.14
4.11
-60 -40 -20
0
20
40
60
80 100 120 140
1k
10k
100k
Frequency (Hz)
1M
10M
Temperature (èC)
图 39. Quiescent Current vs Temperature
图 40. Channel Separation vs Frequency
120
100
80
60
40
20
10M
100M
Frequency (Hz)
1G
10G
Prf =-10 dBm
图 41. EMIRR vs Frequency
14
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7 Detailed Description
7.1 Overview
The OPA2156 is laser trimmed to improve offset and uses a three-gain-stage architecture to achieve very low
noise and distortion. The Functional Block Diagram shows a simplified schematic of the OPA2156 (one channel
shown). The device consists of a low noise input stage and feed-forward pathway coupled to a high-current
output stage. This topology exhibits superior distortion performance under a wide range of loading conditions
compared to other operational amplifiers.
7.2 Functional Block Diagram
Feedforward
Path
Ca
Cb
+IN
2nd Gain
Stage
High-Current
Output
Stage
Low-Noise
Input Stage
OUT
-IN
7.3 Feature Description
7.3.1 Phase Reversal Protection
The OPA2156 has internal phase-reversal protection. Many op amps exhibit phase reversal when the input is
driven beyond the linear common-mode range. This condition is most often encountered in noninverting circuits
when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into
the opposite rail. The input of the OPA2156 prevents phase reversal with excessive common-mode voltage.
Instead, the appropriate rail limits the output voltage. This performance is shown in 图 42.
20
15
10
5
0
-5
-10
-15
VIN
VOUT
-20
Time (125 ꢀs/div)
C004
图 42. Output Waveform Devoid of Phase Reversal During an Input Overdrive Condition
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Feature Description (接下页)
7.3.2 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
A good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is helpful. 图
43 illustrates the ESD circuits contained in the OPA2156 (indicated by the dashed line area). The ESD
protection circuitry involves several current-steering diodes connected from the input and output pins and routed
back to the internal power-supply lines, where the diodes meet at an absorption device internal to the operational
amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
TVS
RF
+VS
R1
RS
250 Ω
250 Ω
INœ
IN+
+
Power-Supply
ESD Cell
ID
RL
+
VIN
œ
œVS
TVS
图 43. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, high-
current pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device can activate. The absorption
device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPA2156 but below
the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates
and clamps the voltage across the supply rails to a safe level.
16
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Feature Description (接下页)
When the operational amplifier connects into a circuit (see 图 43), the ESD protection components are intended
to remain inactive and do not become involved in the application circuit operation. However, circumstances may
arise where an applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there
is a risk that some internal ESD protection circuits can turn on and conduct current. Any such current flow occurs
through steering-diode paths and rarely involves the absorption device.
图 43 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by 500
mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the
current, one of the upper input steering diodes conducts and directs current to V+. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input when
the power supplies (V+ or V–) are at 0 V. Again, this question depends on the supply characteristic when at 0 V,
or at a level below the input signal amplitude. If the supplies appear as high impedance, then the input source
supplies the operational amplifier current through the current-steering diodes. This state is not a normal bias
condition; most likely, the amplifier does not operate normally. If the supplies are low impedance, then the current
through the steering diodes can become quite high. The current level depends on the ability of the input source
to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the
supply pins; see 图 43. Select the Zener voltage so that the diode does not turn on during normal operation.
However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise
above the safe-operating, supply-voltage level.
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Feature Description (接下页)
7.3.3 Thermal Considerations
Through normal operation the OPA2156 will experience self-heating, a natural increase in the die junction
temperature which occurs in every amplifier. This is a result of several factors including the quiescent power
consumption, the package’s thermal dissipation, PCB layout and the device operating conditions.
To fully ensure the amplifier will operate without entering thermal shutdown it is important to calculate the
approximate junction (die) temperature which can be done using 公式 1.
T = P
D
*QJ
A
+ T
A
J
(1)
公式 2 shows the approximate junction temperature for the OPA2156 while unloaded with an ambient
temperature of 25°C.
T = (36V *4.4mA)*120èC /W + 25èC
J
T = 44èC
J
(2)
For high voltage, high precision amplifiers such as the OPA2156 the junction temperature can easily be 10s of
degrees higher than the ambient temperature in a quiescent (unloaded) condition. If the device then begins to
drive a heavy load the junction temperature may rise and trip the thermal shutdown circuit. The 图 44 shows the
maximum output voltage of the OPA2156 without entering thermal shutdown vs ambient temperature in both a
loaded and unloaded condition.
20
15
10
5
Vs Max (No Load)
Vs Max (600W Load)
0
0
25
50
75
100
125
150
175
Ambient Temperature (èC)
图 44. OPA2156 Thermal Safe Operating Area
18
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Feature Description (接下页)
7.3.4 Thermal Shutdown
The internal power dissipation of any amplifier causes the internal (junction) temperature to rise. This
phenomenon is called self heating. The OPA2156 has a thermal protection feature that prevents damage from
self heating.
This thermal protection works by monitoring the temperature of the output stage and turning off the op amp
output drive for temperatures above approximately 170°C. Thermal protection forces the output to a high-
impedance state. The OPA2156 is also designed with approximately 15°C of thermal hysteresis. Thermal
hysteresis prevents the output stage from cycling in and out of the high-impedance state. The OPA2156 returns
to normal operation when the output stage temperature falls below approximately 155°C.
The absolute maximum junction temperature of the OPA2156 is 150°C. Exceeding the limits shown in the
Absolute Maximum Ratings table may cause damage to the device. Thermal protection triggers at 170°C
because of unit-to-unit variance, but does not interfere with device operation up to the absolute maximum ratings.
This thermal protection is not designed to prevent this device from exceeding absolute maximum ratings, but
rather from excessive thermal overload.
7.3.5 Common-Mode Voltage Range
The OPA2156 is a 36-V, true rail-to-rail input operational amplifier with an input common-mode range that
extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel
and P-channel differential input pairs. The N-channel pair is active for input voltages close to the positive rail,
typically (V+) – 2.25 V to 100 mV above the positive supply. The P-channel pair is active for inputs from 100 mV
below the negative supply to approximately (V+) – 1.25 V. There is a small transition region, typically (V+) –
2.25V to (V+) – 1.25 V in which both input pairs are active. This transition region varies modestly with process
variation. Within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance are degraded
compared to operation outside this region.
To achieve the best performance for two-stage rail-to-rail input amplifiers, avoid the transition region when
possible. The OPA2156 uses a precision trim for both the N-channel and P-channel regions. This technique
enables significantly lower levels of offset than previous-generation devices, causing variance in the transition
region of the input stages to appear exaggerated relative to offset over the full common-mode range.
7.3.6 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a
linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the
rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
7.4 Device Functional Modes
The OPA2156 has a single functional mode and is operational when the power-supply voltage is greater than
4.5 V (±2.25 V). The maximum power supply voltage for the OPA2156 is 36 V (±18 V).
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA2156 offers excellent dc precision and ac performance. The device operates with up to 36-V supply rails
offering true rail-to-rail input/output, low offset voltage and offset voltage drift, as well as
25-MHz bandwidth and low input bias. These features make the OPA2156 a robust, high-performance
operational amplifier for high-voltage industrial applications.
8.1.1 Slew Rate Limit for Input Protection
In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages.
By controlling the slew rate of the command voltages into the drive circuits, the load voltages ramps up and down
at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one
additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high
output current and slew rate of the OPA2156 make the device an optimal amplifier to achieve slew rate control
for both dual- and single-supply systems.图 45 shows the OPA2156 in a slew-rate limit design.
Op Amp Gain Stage
Slew Rate Limiter
C1
R1
VCC
VCC
-
R2
-
OPA2156
+
VIN
OPA2156
+
VOUT
VEE
RL
VEE
图 45. Slew Rate Limiter Uses One Op Amp
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIDU026, Slew Rate Limiter Uses One Op Amp.
20
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8.2 Typical Application
The combination of low input bias, high slew rate and a rail-to-rail input and output enable the OPA2156 to serve
as an accurate differential photodiode transimpedance amplifier. This application example shows the design of
such a system.
CF 2.7pF
RF 54.9kΩ
+12V
OPA2156
-
+
+
-12V
VOUT
-
+
-
OPA2156
+12V
RF 54.9kΩ
CF 2.7pF
图 46. OPA2156 Configured as a Differential Photodiode Transimpedance Amplifier
8.2.1 Design Requirements
The design requirements for this design are:
•
•
•
•
Photodiode current: 0 µA to 90 µA
Output voltage: –5 V to 5 V
Supply voltage: ±12 V
Filter cutoff frequency: 1 MHz
8.2.2 Detailed Design Procedure
In this example the OPA2156 serves as a transimpedance amplifier for a differential photodiode. The differential
configuration allows for a wider output range (0 to 10-V differential) compared to a single-ended configuration (0
V to 5 V). This output can be connected to a differential successive approximation register (SAR) analog-to-
digital converter (ADC). The basic equation for a differential transimpedance amplifier output voltage is shown in
公式 3.
VOUT = IPD ì2ì R
F
(3)
公式 3 can be rearranged to calculate the value of the feedback resistors as shown in 公式 4.
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Typical Application (接下页)
V
OUT (MAX ) -VOUT (MIN )
2 ì IIN (MAX )
Ç R
F
5V - (-5V )
Ç 55.6kW
2 ì90
m
A
(4)
Adding a capacitor to the feedback loop creates a filter which will remove undesired noise beyond its cutoff
frequency. For this application a 1-MHz cutoff frequency was selected. The equation for an RC filter is provided
in 公式 5.
1
fC
=
2 ì
p
ì R
F
ìCF
(5)
Rearranging this equation to solve for the capacitor value is show in 公式 6.
1
CF
Ç
Ç 2.7pF
2ìp ì54kWì1MHz
(6)
For more information on photodiode transimpedance amplifier system design and for a single-ended example,
see TIDU535: 1 MHz, Single-Supply, Photodiode Amplifier Reference Design.
8.2.3 Application Curves
10
9
8
7
6
5
4
3
2
1
0
120
100
80
-3dB = 1.6MHz
60
40
20
0
15
30
45
60
75
90
100
10k
Frequency (Hz)
1M
100M
Input Current (mA)
图 47. Differential Photodiode DC Transfer
图 48. Differential Photodiode AC Transfer
150
100
Phase Margin = 60 deg
120
90
60
30
0
80
60
40
20
0
-30
-60
-20
-40
Gain
Phase
100
10k
Frequency (Hz)
1M
100M
图 49. Differential Photodiode Stability
22
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9 Power Supply Recommendations
The OPA2156 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close
as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-supply
applications.
–
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
•
•
Make sure to physically separate digital and analog grounds paying attention to the flow of the ground
current. Separate grounding for analog and digital portions of circuitry is one of the simplest and most-
effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup.
In order to reduce parasitic coupling, run the input traces as far away as possible from the supply or output
traces. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. As shown in 图 50, keeping RF and RG
close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
•
•
Clean the PCB following board assembly for best performance.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. After any aqueous PCB cleaning process, bake the PCB assembly to remove moisture introduced
into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30
minutes is sufficient for most circumstances.
10.1.1 Power Dissipation
The OPA2156 op amp is capable of driving a variety of loads with a power-supply voltage up to ±18 V and full
operating temperature range. Internal power dissipation increases when operating at high supply voltages and/or
high output currents. Copper leadframe construction used in the OPA2156 improves heat dissipation compared
to conventional materials. Circuit board layout can also help minimize junction temperature rise. Wide copper
traces help dissipate the heat by acting as an additional heat sink. Temperature rise can be further minimized by
soldering the devices to the circuit board rather than using a socket.
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Layout Guidelines (接下页)
The OPA2156 has an internal thermal protection feature which prevents it from being damaged due to self
heating, or the internal heating generated during normal operation. The protection circuitry works by monitoring
the temperature of the output stage and turns of the output drive if the junction temperature of the device rises to
approximately 170°C. The device has a thermal hysteresis of approximately 15°C, which allows the device to
safely cool down before returning to normal operation at approximately 155°C. TI recommends that the system
design takes into account the thermal dissipation of the OPA2156 to ensure that the recommended operating
junction temperature of 125°C is not exceeded to avoid decreasing the lifespan of the device or permanently
damaging the amplifier.
10.2 Layout Example
VIN A
VIN B
+
+
VOUT A
VOUT B
RG
RG
RF
RF
(Schematic Representation)
Place components
close to device and to
each other to reduce
parasitic errors.
Output A
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
VS+
GND
OUTPUT A
V+
RF
Output B
GND
-IN A
+IN A
Vœ
OUTPUT B
-IN B
RF
RG
GND
VIN A
RG
+IN B
VIN B
Keep input traces short
and run the input traces
as far away from
the supply lines
Use low-ESR,
GND
ceramic bypass
capacitor. Place as
close to the device
as possible.
VSœ
Ground (GND) plane on another layer
as possible.
图 50. Operational Amplifier Board Layout for Noninverting Configuration
24
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11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 TINA-TI™（免费软件下载）
TINA™是一款简单、功能强大且易于使用的电路仿真程序，此程序基于 SPICE 引擎。TINA-TI 是 TINA 软件的一
款免费全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。TINA-TI 提供所有传
统的 SPICE 直流、瞬态和频域分析，以及其他设计功能。
TINA-TI 可通过模拟电子实验室设计中心免费下载，该软件提供了丰富的后处理能力，允许用户以各种方式设置结
果的格式。虚拟仪器提供选择输入波形和探测电路节点、电压以及波形的功能，从而构建一个动态的快速入门工
具。
注
这些文件需要安装 TINA 软件（由 DesignSoft™提供）或者 TINA-TI 软件。请从 TINA-TI 文
件夹中下载免费的 TINA-TI 软件（网址为 http://www.ti.com.cn/tool/cn/tina-ti）。
11.1.1.2 TI 高精度设计
TI 高精度设计（请访问 http://www.ti.com.cn/ww/analog/precision-designs/ 获取）是由 TI 公司高精度模拟 应用 专
家创建的模拟解决方案，提供了许多实用电路的工作原理、组件选择、仿真、完整印刷电路板 (PCB) 电路原理图和
布局布线、物料清单以及性能测量结果。
11.2 文档支持
11.2.1 相关文档
•
•
•
德州仪器 (TI)，《运算放大器的 EMI 抑制比》 应用报告
德州仪器 (TI)，《0-1A 单电源低侧电流检测解决方案》 参考设计
德州仪器 (TI)，《适合所有人的运算放大器》 设计参考
11.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 商标
E2E is a trademark of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
版权 © 2018–2019, Texas Instruments Incorporated
25
OPA2156
ZHCSIQ3B –SEPTEMBER 2018–REVISED JUNE 2019
www.ti.com.cn
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
26
版权 © 2018–2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2156ID
OPA2156IDGKR
OPA2156IDGKT
OPA2156IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
VSSOP
VSSOP
SOIC
D
8
8
8
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
OP2156
DGK
DGK
D
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
NIPDAUAG
NIPDAUAG
NIPDAU
1THV
1THV
OP2156
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2156IDGKR
OPA2156IDGKT
OPA2156IDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
2500
250
330.0
330.0
330.0
12.4
12.4
12.4
5.3
5.3
6.4
3.4
3.4
5.2
1.4
1.4
2.1
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2156IDGKR
OPA2156IDGKT
OPA2156IDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
2500
250
366.0
366.0
356.0
364.0
364.0
356.0
50.0
50.0
35.0
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
OPA2156ID
D
8
75
506.6
8
3940
4.32
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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