OPA2182IDGKR [TI]
OPAx182 36-V, 5-MHz, Low-Noise, Zero-Drift, MUX-Friendly, Precision Op Amps;
| 型号： | OPA2182IDGKR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OPAx182 36-V, 5-MHz, Low-Noise, Zero-Drift, MUX-Friendly, Precision Op Amps |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA182, OPA2182, OPA4182
SBOS936D – DECEMBER 2019 – REVISED DECEMBER 2021
OPAx182 36-V, 5-MHz, Low-Noise, Zero-Drift, MUX-Friendly, Precision Op Amps
1 Features
3 Description
•
•
•
•
Ultra-high precision:
The OPA182, OPA2182, and OPA4182 (OPAx182)
are high-precision operational amplifiers in an
ultra-low noise, fast-settling, zero-drift device that
provides rail-to-rail output operation and features
a unique MUX-friendly architecture and controlled
start-up system. These features and excellent ac
performance, combined with only 0.45 µV of offset
voltage and 0.003 µV/°C of drift over temperature,
– Zero-drift: 0.003 μV/°C
– Ultra-low offset voltage: 4 μV (maximum)
Excellent dc precision:
– CMRR: 168 dB
– Open-loop gain: 170 dB
Low noise:
– en at 1 kHz: 5.7 nV/√Hz
– 0.1-Hz to 10-Hz noise: 0.12 µVPP
Excellent dynamic performance:
– Gain bandwidth: 5 MHz
– Slew rate: 10 V/µs
make the OPAx182
a
great choice for data
acquisition, battery test, analog input modules, weigh
scales, and any other systems requiring high dc
precision and low noise.
– Fast settling: 10-V step, 0.01% in 1.7 µs
Robust design:
– MUX-friendly inputs
– RFI/EMI filtered inputs
Wide supply: : ±2.25 V to ±18 V, 4.5 V to 36 V
Quiescent current: 0.85 mA
Rail-to-rail output
The MUX-friendly input architecture prevents inrush
current when applying large input differential voltages
that improves settling performance in multichannel
systems. Moreover, the controlled start-up system
rejects any inrush current upon ramping up the supply
rails, all while providing robust ESD protection during
shipment, handling, and assembly.
•
•
•
•
•
Input includes negative rail
The device is specified from –40°C to +125°C.
2 Applications
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
•
•
•
•
•
•
•
Battery test
DC power supply, ac source, electronic load
Data acquisition (DAQ)
Semiconductor test
Weigh scale
Analog input module
Flow transmitter
SOIC (8)
4.90 mm x 3.90 mm
OPA182
SOT-23 (5) - Preview 2.90 mm x 1.60 mm
SOIC (8)
4.90 mm x 3.90 mm
3.00 mm x 3.00 mm
OPA2182
OPA4182
VSSOP (8)
TSSOP (14) - Preview 5.00 mm x 4.40 mm
SOIC (14) 8.65 mm x 3.91 mm
(1) For all available packages, see the package option
addendum at the end of the data sheet.
36
32
28
24
3.4 Mꢀ
18 V
18 V
10 kꢀ
10 kꢀ
Vexc
5 V
œ
OPA2182
Vout
œ
OPA2182
20
Strain Gauge
+
16
12
8
+
œ18 V
œ18 V
4
0
-0.02
-0.0125
-0.005
0.0025
0.01
0.0175
Input Offset Voltage Drift (mV/èC)
OPA2182 Bridge Sensor Application
OPAx182 Offset Drift
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA182, OPA2182, OPA4182
SBOS936D – DECEMBER 2019 – REVISED DECEMBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information: OPA182.................................... 7
7.5 Thermal Information: OPA2182.................................. 7
7.6 Thermal Information: OPA4182.................................. 7
7.7 Electrical Characteristics.............................................8
7.8 Typical Characteristics..............................................10
8 Detailed Description......................................................18
8.1 Overview...................................................................18
8.2 Functional Block Diagram.........................................18
8.3 Feature Description...................................................19
8.4 Device Functional Modes..........................................22
9 Application and Implementation..................................23
9.1 Application Information............................................. 23
9.2 Typical Applications.................................................. 23
10 Power Supply Recommendations..............................29
11 Layout...........................................................................29
11.1 Layout Guidelines................................................... 29
11.2 Layout Example...................................................... 30
12 Device and Documentation Support..........................31
12.1 Device Support....................................................... 31
12.2 Documentation Support.......................................... 31
12.3 Receiving Notification of Documentation Updates..31
12.4 Support Resources................................................. 32
12.5 Trademarks.............................................................32
12.6 Electrostatic Discharge Caution..............................32
12.7 Glossary..................................................................32
13 Mechanical, Packaging, and Orderable
Information.................................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (January 2021) to Revision D (December 2021)
Page
•
Added OPA182 and OPA4182 production data (active) devices and associated content..................................1
Changes from Revision B (July 2020) to Revision C (January 2021)
Page
•
Changed VSSOP-8 (DGK) package from preview to production data (active)...................................................1
Changes from Revision A (May 2020) to Revision B (July 2020)
Page
•
•
Added VSSOP-8 (DGK) preview package and associated content to data sheet..............................................1
Changed capacitive load drive specification from "TBD" to "See Typical Characteristics".................................8
Changes from Revision * (December 2019) to Revision A (May 2020)
Page
•
Changed device status from advanced information (preview) to production data (active) ................................ 1
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5 Device Comparison Table
PRODUCT
FEATURES
OPA2189
OPA2188
OPA2187
0.4-µV offset, 0.005-µV/°C drift, 5.2-nV/√Hz, rail-to-rail output, 36-V, zero-drift, MUX-friendly CMOS
6-µV offset, 0.03-µV/°C drift, 8.8-nV/√Hz, rail-to-rail output, 36-V, zero-drift, MUX-friendly CMOS
1-µV offset, 0.001-µV/°C drift, 100-µA quiescent current, rail-to-rail output, 36-V, zero-drift CMOS
0.25-µV offset, 0.005-µV/°C drift, 7-nV/√Hz, 10-MHz, true rail-to-rail input/output, 5.5-V, zero-drift, zero-
crossover CMOS
OPA2388
OPA2180
120-µV, 10-MHz, 5.1-nV/√Hz, 36-V JFET input industrial op amp
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6 Pin Configuration and Functions
V+
OUT
V-
1
2
3
5
4
NC
œIN
+IN
Vœ
1
2
3
4
8
7
6
5
NC
V+
œ
-IN
+IN
OUT
NC
+
Figure 6-2. OPA189 DBV (5-Pin SOT-23) Preview
Package, Top View
Not to scale
Figure 6-1. OPA189 D (8-Pin SOIC) Package, Top
View
Table 6-1. Pin Functions: OPA189
PIN
TYPE
DESCRIPTION
DBV
(SOT-23)
NAME
–IN
D (SOIC)
2
4
3
Input
Input
—
Inverting input
+IN
NC
OUT
V–
3
Noninverting input
1, 5, 8
—
1
No internal connection; can be left floating.
Output channel
6
4
7
Output
Power
Power
2
Negative supply
V+
5
Positive supply
OUT A
œIN A
+IN A
Vœ
1
2
3
4
8
7
6
5
V+
OUT B
œIN B
+IN B
Not to scale
Figure 6-3. D (8-Pin SOIC) and DGK (8-Pin VSSOP) Packages, Top View
Table 6-2. Pin Functions: OPA2182
PIN
TYPE
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
OUT A
OUT B
V–
NO.
2
Input
Input
Inverting input channel A
Noninverting input channel A
Inverting input channel B
Noninverting input channel B
Output channel A
3
6
Input
5
Input
1
Output
Output
Power
Power
7
Output channel B
4
Negative supply
V+
8
Positive supply
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OUT A
-IN A
+IN A
V+
1
2
3
4
5
6
7
14 OUT D
13 -IN D
12 +IN D
11 V-
+IN B
-IN B
OUT B
10 +IN C
9
8
-IN C
OUT C
Figure 6-4. D (14-Pin SOIC) and PW (14-Pin TSSOP, Preview) Packages, Top View
Table 6-3. Pin Functions: OPA4182
PIN
TYPE
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
–IN C
+IN C
–IN D
+IN D
OUT A
OUT B
OUT C
OUT D
V–
NO.
2
Input
Input
Inverting input channel A
Noninverting input channel A
Inverting input channel B
Noninverting input channel B
Inverting input channel C
Noninverting input channel C
Inverting input channel D
Noninverting input channel D
Output channel A
3
6
Input
5
Input
9
Input
10
13
12
1
Input
Input
Input
Output
Output
Output
Output
Power
Power
7
Output channel B
8
Output channel C
14
11
4
Output channel D
Negative supply
V+
Positive supply
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
40
UNIT
Single-supply, VS = (V+)
VS
Supply voltage
V
Dual-supply, VS = (V+) – (V–)
Common-mode
±20
(V–) – 0.5
(V+) + 0.5
Signal input voltage
V
(V+) – (V–) +
0.2
Differential
Current
±10
Continuous
150
mA
Output short circuit(2)
Operating temperature
Junction temperature
Storage temperature
Continuous
–55
TA
°C
°C
°C
TJ
150
Tstg
–65
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
36
UNIT
V
Single-supply, VS = (V+)
VS
TA
Supply voltage
Dual-supply, VS = (V+) – (V–)
±2.25
–40
±18
125
Operating temperature
°C
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7.4 Thermal Information: OPA182
OPA182
THERMAL METRIC(1)
D (SOIC)
8 PINS
112.9
50.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
56.2
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
10.1
ΨJB
55.4
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Thermal Information: OPA2182
OPA2182
THERMAL METRIC(1)
D (SOIC)
8 PINS
108.1
45.8
DGK (VSSOP)
8 PINS
150.2
43.9
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
51.3
71.4
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
7.2
2.9
ΨJB
50.6
70.0
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Thermal Information: OPA4182
OPA4182
THERMAL METRIC(1)
D (SOIC)
14 PINS
112.9
50.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
56.2
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
10.1
ΨJB
55.4
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics,see the Semiconductor and IC Package Thermal Metrics application
report.
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UNIT
SBOS936D – DECEMBER 2019 – REVISED DECEMBER 2021
7.7 Electrical Characteristics
at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
OFFSET VOLTAGE
±0.45
±4
±4
µV
µV
µV
VOS
Input offset voltage
TA = 0°C to 85°C
TA = –40°C to +125°C
±4
OPA182ID, OPA2182
OPA4182ID
±0.003
±0.003
±0.003
±0.003
±0.005
±0.012
±0.020
±0.012
±0.020
±0.07
TA = 0°C to 85°C
dVOS/dT Input offset voltage drift
µV/°C
OPA182ID, OPA2182
OPA4182ID
TA = –40°C to +125°C
TA = –40°C to +125°C
OPA182ID
µV/V
µV/V
Power-supply rejection
PSRR
ratio
OPA2182,
OPA4182ID
±0.005
±0.05
INPUT BIAS CURRENT
±50
±350
±1
pA
nA
pA
nA
TA = 0°C to 85°C
IB
Input bias current
Input offset current
ZIN = 100 kΩ || 500 pF
ZIN = 100 kΩ || 500 pF
TA = –40°C to
+125°C
±7
±140
±700
±2
TA = 0°C to 85°C
IOS
TA = –40°C to
+125°C
±3
NOISE
18
0.119
5.7
nVRMS
µVPP
En
Input voltage noise
f = 0.1 Hz to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
5.7
Input voltage noise
density
en
nV/√Hz
5.7
5.7
Input current noise
density
in
f = 1 kHz
165
fA/√Hz
V
INPUT VOLTAGE
Common-mode voltage
range
VCM
(V–) – 0.1
120
(V+) – 2.5
VS = ±2.25 V
VS = ±18 V,
140
168
141
(V–) – 0.1 V ≤ VCM ≤ (V+) – 2.5 OPA182ID
V
VS = ±18
V, OPA2182,
OPA4182ID
143
168
Common-mode
rejection ratio
CMRR
dB
VS = ±2.25 V
120
140
(V–) – 0.1 V ≤ VCM ≤ (V+) – 2.5
V,
TA = –40°C to +125°C
VS = ±18 V,
OPA182ID, OPA2182
(V–) ≤ VCM ≤ (V+) – 2.5 V,
TA = –40°C to +125°C
VS = ±18 V,
OPA4182ID
130
INPUT IMPEDANCE
Differential input
impedance
zid
zic
0.1 || 3.7
60 || 2.3
GΩ || pF
TΩ || pF
Common-mode input
impedance
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7.7 Electrical Characteristics (continued)
at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPEN-LOOP GAIN
OPA182ID, OPA2182
150
145
170
170
VS = ±18 V,
OPA4182ID
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RLOAD = 10 kΩ
TA = –40°C to
+125°C
146
AOL
Open-loop voltage gain
dB
OPA182ID, OPA2182
OPA4182ID
150
145
170
170
VS = ±18 V,
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RLOAD = 2 kΩ
TA = –40°C to
+125°C
140
FREQUENCY RESPONSE
UGB
GBW
SR
Unity-gain bandwith
AV = 1
3.6
5
MHz
MHz
V/µs
Gain-bandwith product AV = 1000
Slew rate
Gain = 1, 10-V step
10
Total harmonic distortion
+ noise
THD+N
Gain = 1, f = 1 kHz, VO = 3.5 VRMS
0.00008%
At dc
150
120
Crosstalk
OPA2182
To 0.1%
dB
f = 10 kHz
VS = ±18 V, gain = 1,
10-V step
1.3
1.7
VS = ±18 V, gain = 1,
10-V step, falling
tS
Settling time
µs
ns
To 0.01%
VS = ±18 V, gain = 1,
10-V step, rising
3.4
tOR
Overload recovery time VIN × gain = VS = ±18V
220
OUTPUT
No load
5
20
80
5
15
110
500
15
Positive rail
RLOAD = 10 kΩ
RLOAD = 2 kΩ
No load
Voltage output swing
from rail
VO
mV
Negative rail
RLOAD = 10 kΩ
RLOAD = 2 kΩ
20
80
20
±65
110
500
120
TA = –40°C to +125°C, both rails
ISC
Short-circuit current
Capacitive load drive
mA
pF
CLOAD
See Typical Characteristics
320
Open-loop output
impedance
ZO
f = 1 MHz
Ω
POWER SUPPLY
TA = 25°C
0.85
1
Quiescent current per
amplifier
IQ
VS = ±2.25 V to ±18 V
mA
TA = –40°C to
+125°C
1.1
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7.8 Typical Characteristics
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Table 7-1. Typical Characteristic Graphs
DESCRIPTION
Offset Voltage Production Distribution
FIGURE
Figure 7-1
Offset Voltage Drift Distribution From –40°C to 125°C
Input Bias Current Production Distribution
Input Offset Current Production Distribution
Offset Voltage vs Temperature
Figure 7-2
Figure 7-3
Figure 7-4
Figure 7-5
Offset Voltage vs Common-Mode Voltage
Offset Voltage vs Supply Voltage
Figure 7-6
Figure 7-7
Open-Loop Gain and Phase vs Frequency
Closed-Loop Gain vs Frequency
Figure 7-8
Figure 7-9
Input Bias Current vs Common-Mode Voltage
Input Bias Current and Offset vs Temperature
Output Voltage Swing vs Output Current (Sourcing)
Output Voltage Swing vs Output Current (Sinking)
CMRR and PSRR vs Frequency
Figure 7-10
Figure 7-11
Figure 7-12
Figure 7-13
Figure 7-14
Figure 7-15
Figure 7-16
Figure 7-17
Figure 7-18
Figure 7-19
Figure 7-20
Figure 7-21
Figure 7-22
Figure 7-23
Figure 7-24
Figure 7-25, Figure 7-26
Figure 7-27
Figure 7-28
Figure 7-29
Figure 7-30, Figure 7-31
Figure 7-32, Figure 7-33
Figure 7-34
Figure 7-35
Figure 7-36
Figure 7-37
Figure 7-38
CMRR vs Temperature
PSRR vs Temperature
0.1-Hz to 10-Hz Voltage Noise
Input Voltage Noise Spectral Density vs Frequency
THD+N Ratio vs Frequency
THD+N vs Output Amplitude
Quiescent Current vs Supply Voltage
Quiescent Current vs Temperature
Open-Loop Gain vs Temperature (10-kΩ)
Open-Loop Output Impedance vs Frequency
Small-Signal Overshoot vs Capacitive Load (10-mV Step)
No Phase Reversal
Positive Overload Recovery
Negative Overload Recovery
Small-Signal Step Response (10-mV Step)
Large-Signal Step Response (10-V Step)
Settling Time
Short Circuit Current vs Temperature
Maximum Output Voltage vs Frequency
EMIRR vs Frequency
Channel Separation
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7.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
20
18
16
14
12
10
8
36
32
28
24
20
16
12
8
6
4
4
2
0
-4
0
-0.02
-3
-2
-1
0
1
Offset Voltage (µV)
2
3
4
-0.0125
-0.005
0.0025
0.01
0.0175
Input Offset Voltage Drift (mV/èC)
Figure 7-1. Offset Voltage Production Distribution
Figure 7-2. Offset Voltage Drift Distribution
27
24
21
18
15
12
9
30
27
24
21
18
15
12
9
6
6
3
3
0
-350
0
-700
-250
-150
-50
Positive Input Bias (pA)
50
150
250
350
-500
-300
-100
Input Offset Current (pA)
100
300
500
700
Figure 7-3. Input Bias Current Production Distribution
Figure 7-4. Input Offset Current Production Distribution
3
5
__ -40 èC
__ 25 èC
4
2
1
__ 125 èC
3
2
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-50
-25
0
25
50
75
100
125
-20
-15
-10
-5
0
5
10
Input Common-mode Voltage (V)
15
20
Temperature (èC)
Figure 7-5. Offset Voltage vs Temperature
Figure 7-6. Offset Voltage vs Common-Mode Voltage
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7.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
1
0.5
0
180
160
140
120
100
80
180
165
150
135
120
105
90
--- 4.5V
Gain
Phase
60
40
75
-0.5
-1
20
60
0
45
-20
10m 100m
30
1
10
100 1k
Frequency (Hz)
10k 100k 1M 10M
0
9
18
Supply Voltage (V)
27
36
Figure 7-8. Open-Loop Gain and Phase vs Frequency
Figure 7-7. Offset Voltage vs Supply Voltage
60
40
500
__ IBP
__ IBN
400
300
200
100
0
20
0
-100
-200
-300
-400
-500
-20
-40
-60
G = -1
G = +1
G = +10
G = +100
-20
-15
-10
-5
0
5
10
Input Common-Mode Voltage (V)
15
20
100
1k
10k 100k
Frequency (Hz)
1M
10M
Figure 7-10. Input Bias Current vs Common-Mode Voltage
Figure 7-9. Closed-Loop Gain vs Frequency
5
4
3
2
1
0
18
IBN (nA)
IBP (nA)
IOS (nA)
-40 èC
25 èC
17
85 èC
125 èC
16
15
14
13
12
-1
0
10
20
30
40
50
Output Current (mA)
60
70
80
90
-50
-25
0
25
50
75
100
125
Temperature (èC)
Figure 7-12. Output Voltage Swing vs Output Current (Sourcing)
Figure 7-11. Input Bias Current and Offset vs Temperature
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7.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
-12
-13
-14
-15
-16
-17
-18
180
160
140
120
100
80
CMRR
PSRR-
PSRR+
-40 èC
25 èC
85 èC
125 èC
60
40
20
0
10m 100m
1
10
100 1k
Frequency (Hz)
10k 100k 1M 10M
0
10
20
30
40
50
Output Current (mA)
60
70
80
Figure 7-14. CMRR and PSRR vs Frequency
Figure 7-13. Output Voltage Swing vs Output Current (Sinking)
180
170
160
150
140
130
120
0.001
0.01
0.1
180
170
160
150
140
130
120
0.001
0.01
0.1
1
1
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature(èC)
Temperature(èC)
Figure 7-15. CMRR vs Temperature
Figure 7-16. PSRR vs Temperature
100
10
1
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
Time (1 s/div)
Figure 7-18. Input Voltage Noise Spectral Density vs Frequency
Figure 7-17. 0.1-Hz to 10-Hz Voltage Noise
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7.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
1
-40
1
0.5
-40
G = -1. 10 kW Load
G = -1. 2 kW Load
G = -1. 600 W Load
G = +1. 10 kW Load
G = +1. 2 kW Load
G = +1. 600 W Load
0.2
0.1
0.05
0.1
-60
-60
0.02
0.01
0.005
0.01
-80
-80
0.002
0.001
0.0005
0.001
0.0001
1E-5
-100
-120
-140
-100
-120
-140
G = -1, 10 kW Load
G = -1, 2 kW Load
G = -1, 600 W Load
G = +1, 10 kW Load
G = +1, 2 kW Load
G = +1, 600 W Load
0.0002
0.0001
5E-5
2E-5
1E-5
20
200
2k
20k
10m
100m
Output Amplitude (VRMS)
1
10
Frequency (Hz)
Figure 7-19. THD+N Ratio vs Frequency
Figure 7-20. THD+N vs Output Amplitude
1.5
1.2
0.9
0.6
0.3
0
2
1.5
1
4.5V
Vs = ê 18V
Vs = ê 2.25V
0.5
0
-50
-25
0
25
50
75
100
125
0
9
18
Supply Voltage (V)
27
36
Temperature (èC)
Figure 7-22. Quiescent Current vs Temperature
Figure 7-21. Quiescent Current vs Supply Voltage
190
180
170
160
150
140
130
120
1000
100
10
0.001
0.01
0.1
1
0.1
0.01
1
100
1k
10k 100k
Frequency (Hz)
1M
10M
-50
-25
0
25
50
75
100
125
Temperature (èC)
Figure 7-24. Open-Loop Output Impedance vs Frequency
Figure 7-23. Open-Loop Gain vs Temperature (10-kΩ)
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7.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
80
60
40
20
0
80
60
40
20
0
Riso = 0 W
Riso = 25 W
Riso = 50 W
Riso = 0 W
Riso = 25 W
Riso = 50 W
100
1k
100
1k
Capacitance (pF)
Capacitance (pF)
Inverting Configuration
Noninverting Configuration
Figure 7-25. Small-Signal Overshoot vs Capacitive Load
Figure 7-26. Small-Signal Overshoot vs Capacitive Load
Input Voltage
Output Voltage
Vin
Vout
Time (100 µs/div)
Time (500 ns/div)
Figure 7-27. No Phase Reversal
Figure 7-28. Positive Overload Recovery
Vin
Vout
Vin
Vout
Time (500 ns/div)
Time (100 µs/div)
Inverting Configuration
Figure 7-29. Negative Overload Recovery
Figure 7-30. Small-Signal Step Response
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7.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Vin
Vout
Vin
Vout
Time (100 µs/div)
Time (10 µs/div)
Noninverting Configuration
Inverting Configuration
Figure 7-31. Small-Signal Step Response
Figure 7-32. Large-Signal Step Response
Vin
Vout
Falling
Rising
0.01% Settling
Time (10 µs/div)
Time (1 µs/div)
Noninverting Configuration
Figure 7-33. Large-Signal Step Response
Figure 7-34. Settling Time
100
90
80
70
60
50
40
40
35
30
25
20
15
10
5
Sinking
Sourcing
Vs = ê18 V
Vs = ê2.25 V
0
-75
-50
-25
0
25
50
75
100 125 150
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
Temperature (èC)
Figure 7-35. Short-Circuit Current vs Temperature
Figure 7-36. Maximum Output Voltage vs Frequency
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7.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
140
130
120
110
100
90
0
-20
-40
-60
80
-80
70
-100
-120
-140
-160
60
50
40
30
20
10M
100M
Frequency (Hz)
1G
5G
100
1k
10k 100k
Frequency (Hz)
1M
10M
Figure 7-37. EMIRR vs Frequency
Figure 7-38. Channel Separation
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8 Detailed Description
8.1 Overview
The OPAx182 family of operational amplifiers combine precision offset and drift with excellent overall
performance, making these devices a great choice for many precision applications. The precision offset drift
of only 0.005 µV/°C provides stability over the entire temperature range. In addition, these devices offer
excellent linear performance with high CMRR, PSRR, and AOL. As with all amplifiers, applications with noisy
or high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF
capacitors are adequate. See the Layout Guidelines section for details and a layout example.
The OPAx182 are zero-drift, MUX-friendly, rail-to-rail output operational amplifiers. The devices operate from
4.5 V to 36 V, are unity-gain stable, and a great choice for a wide range of general-purpose and precision
applications. The zero-drift architecture provides ultra-low input offset voltage and near-zero input offset voltage
drift over temperature and time. This choice of architecture also offers outstanding ac performance, such as
ultra-low broadband noise, zero flicker noise, and outstanding distortion performance when operating below the
chopper frequency.
8.2 Functional Block Diagram
The functional block diagram shows a representation of the proprietary OPAx182 architecture.
Slew Boost
Circuitry
CCOMP
CLK
CLK
+IN
36-V Differential
Front End
OUT
œIN
GM1
GM2
GM3
CCOMP
Ripple Reduction
Technology
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8.3 Feature Description
The OPAx182 operational amplifiers have several integrated features that help maintain a high level of precision
throughout all operating conditions. These features include phase-reveral protection, input bias current clock
feedthrough and MUX-friendly inputs.
8.3.1 Phase-Reversal Protection
The OPAx182 have an internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The OPAx182 input prevents phase reversal with excessive common-mode
voltage. Instead, the output limits into the appropriate rail. This performance is shown in Figure 8-1.
Vout (V)
Vin (V)
Time (1 ms/div)
C017
Figure 8-1. No Phase Reversal
8.3.2 Input Bias Current Clock Feedthrough
Zero-drift amplifiers such as the OPAx182 use switching on the inputs to correct for the intrinsic offset and drift
of the amplifier. Charge injection from the integrated switches on the inputs can introduce short transients in
the input bias current of the amplifier. The extremely short duration of these pulses prevents the pulses from
amplifying; however, the pulses may be coupled to the output of the amplifier through the feedback network.
The most effective method to prevent transients in the input bias current from producing additional noise at the
amplifier output is to use a low-pass filter such as an RC network.
8.3.3 EMI Rejection
The OPAx182 use integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI
interference from sources such as wireless communications and densely-populated boards with a mix of analog
signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPAx182
benefit from these design improvements. Texas Instruments has developed the ability to accurately measure and
quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6
GHz. Figure 8-2 shows the results of this testing on the OPAx182. Table 8-1 lists the EMIRR +IN values for the
OPAx182 at particular frequencies commonly encountered in real-world applications. Applications listed in Table
8-1 may be centered on or operated near the particular frequency shown. Detailed information can also be found
in the EMI Rejection Ratio of Operational Amplifiers application report, available for download from www.ti.com.
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of
RF signal rectification. An op amp that is more efficient at rejecting this change in offset as a result of EMI has
a higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in many ways, but
this section provides the EMIRR +IN, which specifically describes the EMIRR performance when the RF signal is
applied to the noninverting input pin of the op amp. In general, only the noninverting input is tested for EMIRR for
the following three reasons:
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•
•
•
Op amp input pins are known to be the most sensitive to EMI, and typically rectify RF signals better than the
supply or output pins.
The noninverting and inverting op amp inputs have symmetrical physical layouts and exhibit nearly matching
EMIRR performance
EMIRR is more simple to measure on noninverting pins than on other pins because the noninverting
input terminal can be isolated on a PCB. This isolation allows the RF signal to be applied directly to the
noninverting input terminal with no complex interactions from other components or connecting PCB traces.
High-frequency signals conducted or radiated to any pin of the operational amplifier may result in adverse
effects, as the amplifier would not have sufficient loop gain to correct for signals with spectral content outside the
bandwidth. Conducted or radiated EMI on inputs, power supply, or output may result in unexpected dc offsets,
transient voltages, or other unknown behavior. Take care to properly shield and isolate sensitive analog nodes
from noisy radio signals and digital clocks and interfaces.
The EMIRR +IN of the OPAx182 is plotted versus frequency as shown in Figure 8-2. If available, any dual and
quad op amp device versions have nearly similar EMIRR +IN performance. The OPAx182 gain bandwidth is 5
MHz. EMIRR performance below this frequency denotes interfering signals that fall within the op amp bandwidth.
140
130
120
110
100
90
80
70
60
50
40
30
20
10M
100M
Frequency (Hz)
1G
5G
Figure 8-2. EMIRR Testing
Table 8-1. OPAx182 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION AND ALLOCATION
EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency
(UHF) applications
400 MHz
44.9 dB
Global system for mobile communications (GSM) applications, radio
communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF
applications
900 MHz
1.8 GHz
2.4 GHz
48.4 dB
81.7 dB
87.9 dB
GSM applications, mobile personal communications, broadband, satellite, L-band
(1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications,
industrial, scientific and medical (ISM) radio band, amateur radio and satellite,
S-band (2 GHz to 4 GHz)
3.6 GHz
5 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
137.2 dB
99.2 dB
802.11a, 802.11n, aero communication and navigation, mobile communication,
space and satellite operation, C-band (4 GHz to 8 GHz)
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8.3.4 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect from accidental
ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is
helpful. See Figure 8-3 for an illustration of the ESD circuits contained in the OPAx182 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device
internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit
operation.
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, high-
current pulse while discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or
more steering diodes. Depending on the path that the current takes, the absorption device may activate. The
absorption device has a trigger or threshold voltage that is above the normal operating voltage of the OPAx182
but below the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly
activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (as shown in Figure 8-3), the ESD protection components
are intended to remain inactive and do not become involved in the application circuit operation. However,
circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. Should
this condition occur, there is a risk that some internal ESD protection circuits may be biased on, and conduct
current. Any such current flow occurs through steering-diode paths and rarely involves the absorption device.
Figure 8-3 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+)
by 500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can
sink the current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high
current levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier,
and then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise
to levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input while
the power supplies V+ or V– are at 0 V. Again, this question depends on the supply characteristic while at 0 V,
or at a level below the input signal amplitude. If the supplies appear as high impedance, then the operational
amplifier supply current may be supplied by the input source through the current-steering diodes. This state
is not a normal bias condition; the amplifier most likely does not operate normally. If the supplies are low
impedance, then the current through the steering diodes can become quite high. The current level depends on
the ability of the input source to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, external zener diodes must be
added to the supply pins, as shown in Figure 8-3. The zener voltage must be selected such that the diode does
not turn on during normal operation. However, the zener voltage must be low enough so that the zener diode
conducts if the supply pin begins to rise above the safe operating supply voltage level.
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TVS(2)
RF
V+
RI
ESD Current-
Steering Diodes
-IN
(3)
RS
OUT
Op Amp
Core
+IN
Edge-Triggered ESD
Absorption Circuit
RL
ID
(1)
VIN
Vœ
TVS(2)
(1) VIN = V+ + 500 mV.
(2) TVS: 40 V > VTVSBR (min) > V+, where VTVSBR (min) is the minimum specified value for the transient voltage suppressor breakdown
voltage.
(3) Suggested value is approximately 5 kΩ in overvoltage conditions.
Figure 8-3. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
8.3.5 MUX-Friendly Inputs
The OPAx182 feature a proprietary input stage design that allows an input differential voltage to be applied
while maintaining high input impedance. Typically, high-voltage CMOS or bipolar-junction input amplifiers feature
antiparallel diodes that protect input transistors from large VGS voltages that may exceed the semiconductor
process maximum and permanently damage the device. Large VGS voltages can be forced when applying a
large input step, switching between channels, or attempting to use the amplifier as a comparator. For more
information, see the MUX-Friendly Precision Operational Amplifiers application brief.
The OPAx182 solve these problems with a switched-input technique that prevents large input bias currents
when large differential voltages are applied. This input architecture solves many issues seen in switched or
multiplexed applications, where large disruptions to RC filtering networks are caused by fast switching between
large potentials. The OPAx182 offer outstanding settling performance because of these design innovations,
along with built-in slew rate boost and wide bandwidth. The OPAx182 can also be used as a comparator.
Differential and common-mode Absolute Maximum Ratings still apply relative to the power supplies.
8.4 Device Functional Modes
The OPAx182 have a single functional mode, and are operational when the power-supply voltage is greater than
4.5 V (±2.25 V). The maximum power supply voltage is 36 V (±18 V).
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The OPAx182 operational amplifiers combine precision offset and drift with excellent overall performance,
making these devices a great choice for many precision applications. The precision offset drift of only 0.005
µV/°C provides stability over the entire temperature range. In addition, the devices combine excellent CMRR,
PSRR, and AOL dc performance with outstanding low-noise operation. As with all amplifiers, applications with
noisy or high-impedance power supplies require decoupling capacitors close to the device pins. In most cases,
0.1-µF capacitors are adequate.
The following application examples highlight only a few of the circuits where the OPAx182 can be used.
9.2 Typical Applications
9.2.1 Strain Gauge Analog Linearization
3.4 Mꢀ
18 V
18 V
10 kꢀ
10 kꢀ
Vexc
5 V
œ
OPA2182
Vout
œ
OPA2182
Strain Gauge
+
+
œ18 V
œ18 V
Figure 9-1. Bridge Sensor Analog Linearization With the OPA2182
9.2.1.1 Design Requirements
A strain gauge is used to measure an alteration due to external force through the use of electrical resistance
in a Wheatstone-bridge configuration. The Wheatstone bridge is used to precisely measure very low values of
resistances down in the mΩ range. An excitation voltage is applied to the bridge, and the output voltage across
the middle of the bridge is measured. The total change in output voltage is relatively small, typically in the mV
range. Therefore, an op amp is used to amplify the signal. The OPA2182 is designed to construct high-precision
amplification.
Use the following parameters for this design example:
•
Use the op-amp linear output operating range, which is usually specified under the AOL test conditions. The
common-mode voltage is equal to the input signal.
•
Use an op amp that does not add significant noise to the system or else the small output voltage from the
Wheatstone bridge will be lost.
•
•
The input signal must be gained; therefore, use an op amp with low input offset voltage (VOS)
The input signal must be gained; therefore, use an op amp with enough open-loop gain to provide the
required amplification
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9.2.1.2 Detailed Design Procedure
The bridge sensor signal flow model is shown in Figure 9-2.
Figure 9-2. Bridge Sensor Signal Flow Model
The bridge sensor is modeled as a multiplier, with inputs from an excitation voltage and pressure sensor
producing an output voltage given in Equation 1:
Vbridge(P,Vexc ) = Vexc ìKp(P)
(1)
Kp is the sensitivity of the bridge sensor, and is usually specified in mV/V. P represents the pressure relative to
the range of the sensor, normalized to a scale from 0 to 1. Solving this equation with the variables given in the
signal flow model and solving for Vout results in Equation 2:
VOS + V ì GìKp(P)
ref
Vout (P) =
1- GìKlin ìKp(P)
(2)
This equation has three variables, VOS, G and Klin, that require three equations to solve. To solve these
equations. values of Kp at no load, midscale and full load conditions are needed for the sensor. With these
values, the system can be linearized.
With known values for Kp, Klin is calculated as shown in Equation 3:
4ìBv ì V
ref
Klin
=
(Vout _high - Vout _low ) - 2ìBv ì(Vout _high + Vout _low
)
(3)
In this equation, Bv represents the bridge nonlinearity, which is calculated as shown in Equation 4:
Kp(1) + Kp(0)
Kp(0.5) -
2
Bv =
Kp(1) - Kp(0)
(4)
Bv is solved based on the sensor specifications, and the equation is then used to solve for Klin. Next, the system
gain is calculated using Equation 5 and Equation 6.
VOS + V ì GìKp(1)
ref
Vout _high
=
1- GìKlin ìKp(1)
(5)
(6)
VOS + V ì GìKp(0)
ref
Vout _high
=
1- GìKlin ìKp(0)
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Solving for VOS in both equations and combining results in Equation 7.
Vout _high(1- GìKlin ìKp(1)) - V ìGìKp(1) = Vout _low(1- GìKlin ìKp(0)) - V ìGìKp(0)
ref
ref
(7)
Solving for G gives Equation 8.
Vout _high - Vout _low
G =
Kp(1)ì(Klin ì Vout _high + Vref ) -Kp(0)ì(Klin ì Vout _low + V
)
ref
(8)
(9)
With both Klin and G now calculated, VOS is solved as shown in Equation 9.
VOS = Vout _low (1- GìKlin ìKp(0)) - V ìGìKp(0)
ref
For a sensor with a KP of 0.0003 mV/V at no load, 0.0017 mV/V midscale and 0.00289 mV/V, the corresponding
nonlinearity is approximately 4%. Solving for Klin, G, and VOS gives the values shown in Table 9-1.
Table 9-1. Example Bridge Calculations
Klin
0.173913
323.8178
-0.48573
G
VOS
9.2.1.3 Application Curves
Using the same KP values used previously, the bridge nonlinearity is simulated as 4% peak, the output is linear
from 0 V to 5 V, and the corrected system nonlinearity is approximately ±0.1%.
4
3.5
3
5
4.5
4
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Linearized Bridge Pressure
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Linearized Bridge Pressure
1
Figure 9-3. Bridge Nonlinearity
Figure 9-4. Bridge Output
0.12
0.1
0.08
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.1
-0.12
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Linearized Bridge Pressure
1
Figure 9-5. System Nonlinearity
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9.2.2 Rogowski Coil Integrator
Figure 9-6 shows the OPA2182 configured as an active integrator, level shifter and precision voltage reference
buffer for a Rogowski coil used to indirectly measure the current of a protection relay with high accuracy. This
design has two main signal paths: the first path is used to accurately measure the current flowing through the
Rogowski coil, and a second high-speed path is used to detect a fast transient such as a short circuit. The
OPA2182 is selected for this application thanks to the low offset voltage (0.45 µV) and offset drift (0.003 µV/°C)
that minimize calibration requirements and maintain higher accuracy across the full temperature range. This
device also features flat noise across a wide frequency range which includes dc which improves accuracy and
repeatability across a wide range of input currents from the Rogowski coil. Additional information on this design
can be found in the Active Integrator for Rogowski Coil Reference Design with Improved Accuracy for Relay and
Breaker.
2.5 V
LDO
(LP2951ACSD/NOPB)
5-V
DC
supply
input
V
+
ÞVE_UNREG
Þ2.5 V
5 V
Charge pump
(TPS60403DBV)
LDO
(TPS72325DBVT)
V
Þ
GND
V+
VÞ
2.5 V
Þ2.5 V
Precision measurement
Level shifter (OPA2182)
Amplifier (OPA2182)
Active integrator (OPA2182)
Precision
measurement
output
RF
R
1
RF
RF
R
1
Rogowski
coil
output
Þ
C
Þ
RI
R
2
+V
Þ
RI
+V
+
+
R
3
+V
+
2.5 V
Þ2.5 V
V+
VÞ
Fast settling
Level shifter (OPA2182)
Active integrator (OPA2182)
Amplifier (OPA2182)
RF
R
1
RF
C
Fast settling
output
RF
R
1
Þ
Þ
RI
R
2
+V
Þ
RI
+
+V
R
3
+
+V
+
5 V
GND
Jumper
selection
Buffer (OPA2182)
GND
Voltage reference
(LM4040AIM3-2.5/NOPB)
REF_2.5 V
Þ
+V
+
TIDA-00777
Copyright © 2016, Texas Instruments Incorporated
Figure 9-6. Programmable Power Supply
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9.2.3 System Examples
9.2.3.1 24-Bit, Delta-Sigma, Differential Load Cell or Strain Gauge Sensor Signal Conditioning
The OPA2182 is used in a 24-bit, differential load cell or strain gauge sensor signal conditioning system
alongside the ADS1225. The OPA2182 amplifier is configured in a two-amp instrumentation-amplifier (IA)
configuration, and is band-limited to reduce noise and allow heavy capacitive drive. The load cell is powered by
an excitation voltage (denoted VEX) of 5 V and provides a differential voltage proportional to force applied. The
differential voltage can be quite small and both outputs are biased to VEX / 2.
In this example, the OPA2182 is employed here because of the excellent input offset voltage (0.45 µV) and
input offset voltage drift (0.003 µV/°C), the low broadband noise (5.7 nV/√Hz) and zero-flicker noise, and
excellent linearity and high input impedance. The two-amp IA configuration removes the dc bias and amplifies
the differential signal of interest and drives the 24-bit, delta-sigma ADS1225 analog-to-digital converter (ADC)
for acquisition and conversion. The ADS1225 features a 100-SPS data rate, single-cycle settling, and simple
conversion control with a dedicated START pin.
t ® RF
G = 1 +
RG
GND
GND
GND
GND
+
OPAx182
+5 V
+3 V
AVDD
VREFN
VREFP
œ
RTRACE
RTRACE
+15 V
C1
10 µF
DVDD
RF
10 kꢀ
DVDD
R1
1 kꢀ
START
SCLK
+OUT
+SENSE
œSENSE
AINP1
CF
1 µF
DRDY / DOUT
MSP430xxx
or other host
+5 V
RG
50 ꢀ
C2
1 µF
ADS1225
CF
1 µF
R2
1 kꢀ
+3 V
+
Load Cell
MODE
BUFEN
TEMPEN
GND
VEX
AINN1
œ
œOUT
RF
10 kꢀ
GND
GND
C3
10 µF
+15 V
œ
GND
GND
OPAx182
+
GND
Figure 9-7. 24-Bit Differential Load Cell or Strain Gauge Sensor Signal Conditioning Schematic
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9.2.4 Programmable Power Supply
Figure 9-6 shows the OPAx182 configured as a precision programmable power supply using the 16-bit, voltage
output DAC8581 and the OPA548 high-current amplifier. This application amplifies the digital-to-analog converter
(DAC) voltage by a value of five, and handles a large variety of capacitive and current loads. The OPAx182 in
the front-end provides precision and low drift across a wide range of inputs and conditions. Click the following
link to download the TINA-TI™ software file: Programmable Power-Supply Circuit.
C1
500 nF
R1
10 kꢀ
R4
40 kꢀ
R2
1 kꢀ
GND
C2
500 nF
+30V
+15V
œ
R3
10 kꢀ
OPA548
VOUT
œ
OPAx182
+
Output = 25V
DAC8581
+
œ30V
œ15V
Input = 5V
Copyright © 2017, Texas Instruments Incorporated
Figure 9-8. Programmable Power Supply
9.2.5 RTD Amplifier With Linearization
See the Analog Linearization of Resistance Temperature Detectors analog design journal for an in-depth
analysis of Figure 9-9. Click the following link to download the TINA-TI™ software file: RTD Amplifier with
Linearization.
15 V
(5 V)
Out
In
REF5050
1 µF
1 µF
R2
49.1 kΩ
R3
60.4 kΩ
R1
4.99 kΩ
0°C = 0 V
VOUT
OPAx182
200°C = 5 V
R5
105.8 kΩ(1)
RTD
Pt100
R4
1 kΩ
Copyright © 2017, Texas Instruments Incorporated
(1) R5 provides positive-varying excitation to linearize output.
Figure 9-9. RTD Amplifier With Linearization
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10 Power Supply Recommendations
The OPAx182 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +125°C. The Typical Characteristics presents parameters that can exhibit significant variance with
regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 40 V can permanently damage the device (see the Aboslute Maximum
Ratings).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or
high-impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp
itself. Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the
analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information, see The
PCB is a component of op amp design.
To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed
to in parallel with the noisy trace.
•
•
•
Place the external components as close as possible to the device. As illustrated in Figure 11-1, keep RF and
RG close to the inverting input to minimize parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
•
•
Clean the PCB following board assembly.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture
introduced into the device packaging during the cleaning process. A low temperature, post cleaning bake
at 85°C for 30 minutes is sufficient for most circumstances.
For the lowest offset voltage, avoid temperature gradients that create thermoelectric (Seebeck) effects in the
thermocouple junctions formed from connecting dissimilar conductors.
•
•
•
Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
Thermally isolate components from power supplies or other heat sources.
Shield operational amplifier and input circuitry from air currents, such as cooling fans.
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11.2 Layout Example
Place bypass
capacitors as close to
device as possible
(avoid use of vias)
Use ground pours for
shielding the input
signal pairs
GND
C3
C4
+V
R3
C3
R3
INœ
C4
+V
1
NC
œIN
+IN
Vœ
NC
V+
8
7
6
5
1
2
3
4
NC
œIN
+IN
Vœ
NC
V+
8
7
6
5
R1
R2
R1
2
3
4
INœ
œ
OUT
IN+
OUT
NC
OUT
OUT
NC
+
R2
-V
C1
C2
IN+
R4
GND
R4
-V
Place components
C1
C2
Use a low-
ESR,ceramic bypass
capacitor
close to device and to
each other to reduce
parasitic errors
Copyright © 2017, Texas Instruments Incorporated
Figure 11-1. Operational Amplifier Board Layout for Difference Amplifier Configuration
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 PSpice® for TI
PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create
subsystem designs and prototype solutions before committing to layout and fabrication, reducing development
cost and time to market.
12.1.1.2 TINA-TI™ Simulation Software (Free Download)
TINA-TI™ software is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine.
TINA-TI simulation software is a free, fully-functional version of the TINA™ software, preloaded with a library
of macromodels, in addition to a range of both passive and active models. TINA-TI software provides all the
conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI simulation software offers extensive
post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer
the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic
quick-start tool.
Note
These files require that either the TINA software or TINA-TI software be installed. Download the free
TINA-TI software from the TINA-TI software folder.
12.1.1.3 TI Precision Designs
TI Precision Designs are available online at http://www.ti.com/ww/en/analog/precision-designs/. TI Precision
Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of
operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured
performance of many useful circuits.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
•
•
•
•
•
•
•
•
Texas Instruments, Zero-drift Amplifiers: Features and Benefits application report
Texas Instruments, The PCB is a component of op amp design technical brief
Texas Instruments, Operational amplifier gain stability, Part 3: AC gain-error analysis technical brief
Texas Instruments, Operational amplifier gain stability, Part 2: DC gain-error analysis technical brief
Texas Instruments, Using infinite-gain, MFB filter topology in fully differential active filters technical brief
Texas Instruments, Op Amp Performance Analysis application bulletin
Texas Instruments, Single-Supply Operation of Operational Amplifiers application bulletin
Texas Instruments, Tuning in Amplifiers application bulletin
Texas Instruments, Shelf-Life Evaluation of Lead-Free Component Finishes application report
Texas Instruments, Feedback Plots Define Op Amp AC Performance application bulletin
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application report
Texas Instruments, Analog Linearization of Resistance Temperature Detectors technical brief
Texas Instruments, TI Precision Design TIPD102 High-Side Voltage-to-Current (V-I) Converter reference
guide
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
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12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TINA-TI™ and TI E2E™ are trademarks of Texas Instruments.
TINA™ is a trademark of DesignSoft, Inc.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
22-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA182IDR
OPA182IDT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
3000 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 105
-40 to 105
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 105
-40 to 105
OP182
250
75
RoHS & Green
RoHS & Green
SN
SN
SN
SN
SN
SN
SN
OP182
OP2182
26RQ
OPA2182ID
SOIC
D
8
OPA2182IDGKR
OPA2182IDGKT
OPA2182IDR
OPA4182IDR
OPA4182IDT
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
2500 RoHS & Green
250 RoHS & Green
8
26RQ
8
2500 RoHS & Green
3000 RoHS & Green
OP2182
OP4182
OP4182
SOIC
D
14
14
SOIC
D
250
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Dec-2021
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA182IDR
OPA182IDT
SOIC
SOIC
D
D
8
8
3000
250
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.8
16.4
16.4
6.4
6.4
5.3
5.3
6.4
6.5
6.5
5.2
5.2
3.4
3.4
5.2
9.5
9.5
2.1
2.1
1.4
1.4
2.1
2.3
2.3
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
OPA2182IDGKR
OPA2182IDGKT
OPA2182IDR
OPA4182IDR
OPA4182IDT
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
2500
250
8
8
2500
3000
250
SOIC
D
14
14
SOIC
D
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA182IDR
OPA182IDT
SOIC
SOIC
D
D
8
8
3000
250
366.0
366.0
366.0
366.0
366.0
366.0
366.0
364.0
364.0
364.0
364.0
364.0
364.0
364.0
50.0
50.0
50.0
50.0
50.0
50.0
50.0
OPA2182IDGKR
OPA2182IDGKT
OPA2182IDR
OPA4182IDR
OPA4182IDT
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
2500
250
8
8
2500
3000
250
SOIC
D
14
14
SOIC
D
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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