OPA2197-Q1 [TI]
汽车类双路 36V、精密轨到轨输入/输出、低失调电压运算放大器;
| 型号： | OPA2197-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类双路 36V、精密轨到轨输入/输出、低失调电压运算放大器 放大器 运算放大器 |
| 文件： | 总45页 (文件大小：3136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
OPAx197-Q1 36V 精密轨到轨输入/输出、低失调电压、
低输入偏置电流e-trim™ 运算放大器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准：
OPAx197-Q1 系列（OPA197-Q1、OPA2197-Q1 和
OPA4197-Q1）是新一代 36V e-trim™ 运算放大器的一
部分。OPAx197-Q1 系列 e-trim 运算放大器使用专有
的封装级修整方法，在塑模成型工艺之后的最后制造步
骤中实现失调和失调温度漂移。该方法可更大限度地减
少固有的输入晶体管不匹配的影响和在封装成型过程中
引入的误差。
– 温度等级1：–40°C 至+125°C，TA
• 低失调电压：±250µV（最大值）
• 低失调电压漂移：±0.2µV/°C
• 低噪声：1 kHz 时为5.5nV/√Hz
• 高共模抑制：140 dB
• 低偏置电流：±5pA
• 轨至轨输入和输出
• 宽带宽：10 MHz GBW
• 高压摆率：20V/µs
• 低静态电流：每个放大器1 mA
• 宽电源电压：±2.25V 至±18V，4.5V 至36V
• EMI/RFI 滤波输入
• 电源轨的差分输入电压范围
• 高容性负载驱动能力：1nF
• 行业标准封装：
这些器件具有出色的直流精度和交流性能，包括轨至轨
输入/输出、低失调电压（典型值为 ±5µV）、低温漂
（典型值为±0.2µV/°C）和10MHz 带宽。
OPAx197-Q1 具有独特功能，例如电源轨的差分输入
电压范围、高输出电流 (±65mA)、高达 1nF 的高容性
负载驱动以及高压摆率 (20V/µs)，是一款稳定可靠的
高性能运算放大器，适用于各种高电压工业应用。
器件信息
封装(1)
VSSOP (8)
TSSOP (14)
封装尺寸（标称值）
3.00mm × 3.00mm
5.00mm × 4.40mm
– 采用超小型8 引脚VSSOP 封装的单通道和双通
道
– 14 引脚TSSOP 四通道
器件型号
OPA197-Q1
OPA2197-Q1
OPA4197-Q1
2 应用
(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。
• 逆变器和电机控制
• 直流/直流转换器
• 车载充电器(OBC) 和无线充电器
• 电池管理系统(BMS)
100
66 Typical Units Shown
75
50
25
0
œ25
œ50
œ75
œ100
œ75 œ50 œ25
0
25
50
75
100 125 150
Temperature (°C)
C001
OPAx197-Q1 在整个温度范围内保持超低的输入失调电压
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS918
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
Table of Contents
7.3 Feature Description...................................................22
7.4 Device Functional Modes..........................................28
8 Application and Implementation..................................29
8.1 Application Information............................................. 29
8.2 Typical Applications.................................................. 29
9 Power Supply Recommendations................................33
10 Layout...........................................................................33
10.1 Layout Guidelines................................................... 33
10.2 Layout Examples.................................................... 34
11 Device and Documentation Support..........................35
11.1 Device Support........................................................35
11.2 Documentation Support.......................................... 35
11.3 接收文档更新通知................................................... 35
11.4 支持资源..................................................................35
11.5 Trademarks............................................................. 36
11.6 静电放电警告...........................................................36
11.7 术语表..................................................................... 36
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings ....................................... 6
6.2 ESD Ratings .............................................................. 6
6.3 Recommended Operating Conditions ........................6
6.4 Thermal Information: OPA197-Q1 ............................. 7
6.5 Thermal Information: OPA2197-Q1 ........................... 7
6.6 Thermal Information: OPA4197-Q1 ........................... 7
6.7 Electrical Characteristics: VS = ±4 V to ±18 V
(VS = 8 V to 36 V) .........................................................8
6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V
(VS = 4.5 V to 8 V) ......................................................10
6.9 Typical Characteristics..............................................12
7 Detailed Description......................................................21
7.1 Overview...................................................................21
7.2 Functional Block Diagram.........................................21
Information.................................................................... 36
4 Revision History
Changes from Revision * (March 2018) to Revision A (January 2021)
Page
• 添加了OPA4197-Q1 和相关内容........................................................................................................................1
Copyright © 2023 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
5 Pin Configuration and Functions
NC
–IN
+IN
V–
1
2
3
4
8
7
6
5
NC
–
V+
+
OUT
NC
Not to scale
图5-1. OPA197-Q1 DGK Package, 8-Pin VSSOP, Top View
Pin Functions: OPA197-Q1
PIN
I/O
DESCRIPTION
NAME
+IN
NO.
3
I
I
Noninverting input
Inverting input
2
–IN
NC
1, 5, 8
No internal connection (can be left floating)
Output
—
OUT
V+
6
7
4
O
Positive (highest) power supply
Negative (lowest) power supply
—
—
V–
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
OUT B
–IN B
+IN B
Not to scale
图5-2. OPA2197-Q1 DGK Package, 8-Pin VSSOP, Top View
Pin Functions: OPA2197-Q1
PIN
I/O
DESCRIPTION
NAME
+IN A
+IN B
–IN A
–IN B
OUT A
OUT B
V+
DGK (VSSOP)
3
5
2
6
1
7
8
4
I
I
Noninverting input, channel A
Noninverting input, channel B
Inverting input, channel A
Inverting input, channel B
Output, channel A
I
I
O
O
—
—
Output, channel B
Positive (highest) power supply
Negative (lowest) power supply
V–
Copyright © 2023 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
OUT A
–IN A
+IN A
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT D
–IN D
+IN D
V–
+IN B
–IN B
OUT B
+IN C
–IN C
OUT C
8
Not to scale
图5-3. OPA4197-Q1 PW Package, 14-Pin TSSOP, Top View
Pin Functions: OPA4197-Q1
PIN
I/O
DESCRIPTION
NAME
+IN A
+IN B
+IN C
+IN D
–IN A
–IN B
–IN C
–IN D
OUT A
OUT B
OUT C
OUT D
V+
NO.
3
I
I
Noninverting input, channel A
Noninverting input, channel B
Noninverting input, channel C
Noninverting input, channel D
Inverting input, channel A
Inverting input, channel B
Inverting input, channel C
Inverting input, channel D
Output, channel A
5
10
12
2
I
I
I
6
I
9
I
13
1
I
O
O
O
O
—
—
7
Output, channel B
8
Output, channel C
14
4
Output, channel D
Positive (highest) power supply
Negative (lowest) power supply
11
V–
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Single supply, VS = (V+)
40
±20
VS
Supply voltage
V
Dual supply, VS = (V+) –(V–)
Common-mode
(V+) + 0.5
(V–) –0.5
Signal input voltage
V
(V+) –(V–) +
Differential
0.2
Signal input current
Output short circuit(2)
Latch-up per JESD78D
Operating temperature
Junction temperature
Storage temperature
±10
mA
Continuous
Class IIA
TA
150
150
150
°C
°C
°C
–55
TJ
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
UNIT
OPA197-Q1, OPA2197-Q1
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD classification level 3A
±4000
±500
V(ESD)
Electrostatic discharge
V
Charge device model (CDM), per AEC Q100-011
CDM ESD classification level C4A
OPA4197-Q1
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD classification level 2
±2000
±750
V(ESD)
Electrostatic discharge
V
Charge device model (CDM), per AEC Q100-011
CDM ESD classification level C5
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
36
UNIT
V
Single supply, VS = (V+)
VS
TA
Supply voltage
±2.25
±18
125
Dual supply, VS = (V+) –(V–)
Operating temperature
°C
–40
Copyright © 2023 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
6.4 Thermal Information: OPA197-Q1
OPA197-Q1
THERMAL METRIC(1)
DGK (VSSOP)
8 PINS
180.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
67.9
102.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
10.4
ψJT
100.3
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA2197-Q1
OPA2197-Q1
THERMAL METRIC(1)
DGK (VSSOP)
8 PINS
158
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
48.6
78.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
3.9
ψJT
77.3
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA4197-Q1
OPA4197-Q1
THERMAL METRIC(1)
PW (TSSOP)
14 PINS
108.1
26.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
54.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
1.4
ψJT
53.3
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
MAX UNIT
6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V)
at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩconnected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
OFFSET VOLTAGE
±25
±30
±50
±10
±25
±50
±0.5
±0.8
±250
±350
TA = 0°C to 85°C
±400
µV
±250
TA = –40°C to +125°C
VOS
Input offset voltage
TA = 0°C to 85°C
±350
±500
VCM = (V+) –1.5 V
TA = –40°C to +125°C
TA = 0°C to 85°C
±2.5
µV/°C
±4.5
Input offset voltage
drift
dVOS/dT
PSRR
TA = –40°C to +125°C
Power-supply
rejection ratio
±0.3
±1.0 µV/V
TA = –40°C to +125°C
INPUT BIAS CURRENT
±5
±2
±20
±5
pA
nA
pA
nA
IB
Input bias current
Input offset current
TA = –40°C to +125°C
TA = –40°C to +125°C
±20
±2
IOS
NOISE
(V–) –0.1 V < VCM < (V+) –3
V
f = 0.1 Hz to 10 Hz
f = 0.1 Hz to 10 Hz
1.3
4
En
Input voltage noise
µVPP
(V+) –1.5 V < VCM < (V+) + 0.1
V
f = 100 Hz
f = 1 kHz
f = 100 Hz
f = 1 kHz
10.5
5.5
(V–) –0.1 V < VCM < (V+) –3
V
Input voltage noise
density
en
nV/√Hz
32
(V+) –1.5 V < VCM < (V+) + 0.1
V
12.5
Input current noise
density
in
f = 1 kHz
1.5
fA/√Hz
INPUT VOLTAGE
Common-mode
voltage
(V–) –
VCM
(V+) + 0.1
V
0.1
120
114
100
86
140
126
120
100
(V–) –0.1 V < VCM < (V+) –3 V
(V–) < VCM < (V+) –3 V, TA = –40°C to +125°C
Common-mode
rejection ratio
CMRR
dB
(V+) –1.5 V < VCM < (V+)
TA = –40°C to +125°C
INPUT IMPEDANCE
MΩ||
pF
ZID
ZIC
Differential
100 || 1.6
1 || 6.4
1013Ω||
Common-mode
pF
Copyright © 2023 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) (continued)
at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩconnected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OPEN-LOOP GAIN
120
114
126
120
134
126
140
134
(V–) + 0.6 V < VO < (V+) –0.6
V,
RL = 2 kΩ
TA = –40°C to +125°C
TA = –40°C to +125°C
Open-loop voltage
gain
AOL
dB
(V–) + 0.3 V < VO < (V+) –0.3
V,
RL = 10 kΩ
FREQUENCY RESPONSE
GBW
SR
Unity gain bandwidth
Slew rate
10
20
MHz
V/µs
G = 1, 10-V step
To 0.01%
G = 1, 10-V step
G = 1, 5-V step
G = 1, 10-V step
G = 1, 5-V step
1.4
0.9
2.1
1.8
µs
ts
Settling time
To 0.001%
µs
ns
Overload recovery
time
tOR
VIN × G = VS
200
Total harmonic
distortion + noise
THD+N
G = 1, f = 1 kHz, VO = 3.5 VRMS
0.00008%
OPA4197-Q1 at dc
150
130
dB
dB
Crosstalk
OPA4197-Q1, f = 100 kHz
OUTPUT
No load
5
15
95
110
Positive rail
Negative rail
RL = 10 kΩ
RL = 2 kΩ
No load
430
500
mV
15
Voltage output swing
from rail
VO
5
95
110
500
mA
RL = 10 kΩ
RL = 2 kΩ
430
ISC
Short-circuit current
Capacitive load drive
±65
CLOAD
See 节6.9
Open-loop output
impedance
ZO
375
f = 1 MHz, IO = 0 A; see 图6-29
Ω
POWER SUPPLY
1
1.2
mA
1.5
Quiescent current per
IQ
IO = 0 A
amplifier
TEMPERATURE
Thermal protection
TA = –40°C to +125°C
140
°C
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
MAX UNIT
6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V)
at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩconnected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
OFFSET VOLTAGE
±5
±8
±250
±350
±400
µV
TA = 0°C to 85°C
VCM = (V+) –3 V
±10
TA = –40°C to +125°C
VOS
Input offset voltage
(V+) –3.5 V < VCM < (V+) –1.5 V
See 节7.3.6
±10
±250
±350
±500
TA = 0°C to 85°C
±25
VCM = (V+) –1.5 V
±50
TA = –40°C to +125°C
Input offset voltage
drift
dVOS/dT
dVOS/dT
PSRR
±0.5
±0.8
±2
±2.5
VCM = (V+) –3 V
µV/°C
±4.5
TA = –40°C to +125°C
Input offset voltage
drift
VCM = (V+) –1.5 V
TA = –40°C to +125°C
Power-supply
rejection ratio
µV/V
INPUT BIAS CURRENT
±5
±2
±20
±5
pA
nA
pA
nA
IB
Input bias current
Input offset current
TA = –40°C to +125°C
TA = –40°C to +125°C
±20
±2
IOS
NOISE
En
1.3
4
(V–) –0.1 V < VCM < (V+) –3 V, f = 0.1 Hz to 10 Hz
(V+) –1.5 V < VCM < (V+) + 0.1 V, f = 0.1 Hz to 10 Hz
Input voltage noise
µVPP
f = 100 Hz
10.5
5.5
32
(V–) –0.1 V < VCM < (V+) –3
V
f = 1 kHz
f = 100 Hz
f = 1 kHz
Input voltage noise
density
en
nV/√Hz
(V+) –1.5 V < VCM < (V+) + 0.1
V
12.5
Input current noise
density
in
f = 1 kHz
1.5
fA/√Hz
INPUT VOLTAGE
Common-mode
voltage range
(V–) –
VCM
(V+) + 0.1
V
0.1
94
90
110
104
(V–) –0.1 V < VCM < (V+) –3
V
TA = –40°C to +125°C
TA = –40°C to +125°C
dB
Common-mode
rejection ratio
100
84
120
CMRR
(V+) –1.5 V < VCM < (V+)
100
(V+) –3 V < VCM < (V+) –1.5 V
See 节6.9
INPUT IMPEDANCE
MΩ||
pF
ZID
ZIC
Differential
100 || 1.6
1 || 6.4
1013Ω||
Common-mode
pF
Copyright © 2023 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V) (continued)
at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩconnected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OPEN-LOOP GAIN
110
100
110
110
120
114
126
120
(V–) + 0.6 V < VO < (V+) –0.6
V,
RL = 2 kΩ
dB
dB
TA = –40°C to +125°C
TA = –40°C to +125°C
Open-loop voltage
gain
AOL
(V–) + 0.3 V < VO < (V+) –0.3
V,
RL = 10 kΩ
FREQUENCY RESPONSE
GBW
SR
ts
Unity gain bandwidth
Slew rate
10
20
1
MHz
V/µs
µs
G = 1, 5-V step
Settling time
To 0.01%, VS = ±3 V, G = 1, 5-V step
VIN × G = VS
Overload recovery
time
tOR
200
ns
OPA4197-Q1 at dc
150
130
dB
dB
Crosstalk
OPA4197-Q1, f = 100 kHz
OUTPUT
No load
5
15
95
110
Positive rail
Negative rail
RL = 10 kΩ
RL = 2 kΩ
No load
430
500
mV
15
Voltage output swing
from rail
VO
5
95
110
500
mA
RL = 10 kΩ
RL = 2 kΩ
430
ISC
Short-circuit current
Capacitive load drive
±65
CLOAD
See 节6.9
Open-loop output
impedance
ZO
375
f = 1 MHz, IO = 0 A; see 图6-29
Ω
POWER SUPPLY
1
1.2
mA
1.5
Quiescent current per
IQ
IO = 0 A
amplifier
TEMPERATURE
Thermal protection
TA = –40°C to +125°C
140
°C
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
6.9 Typical Characteristics
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 100 pF, (unless otherwise noted)
表6-1. Table of Graphs
DESCRIPTION
Offset Voltage Production Distribution
FIGURE
图6-1 to 图6-6
图6-7 to 图6-8
图6-9
Offset Voltage Drift Distribution
Offset Voltage vs Temperature
Offset Voltage vs Common-Mode Voltage
Offset Voltage vs Power Supply
Open-Loop Gain and Phase vs Frequency
Closed-Loop Gain and Phase vs Frequency
Input Bias Current vs Common-Mode Voltage
Input Bias Current vs Temperature
Output Voltage Swing vs Output Current (maximum supply)
CMRR and PSRR vs Frequency
CMRR vs Temperature
图6-10 to 图6-12
图6-13
图6-14
图6-15
图6-16
图6-17
图6-18
图6-19
图6-20
PSRR vs Temperature
图6-21
0.1-Hz to 10-Hz Noise
图6-22
Input Voltage Noise Spectral Density vs Frequency
THD+N Ratio vs Frequency
图6-23
图6-24
THD+N vs Output Amplitude
图6-25
Quiescent Current vs Supply Voltage
Quiescent Current vs Temperature
Open Loop Gain vs Temperature
Open Loop Output Impedance vs Frequency
Small Signal Overshoot vs Capacitive Load (100-mV Output Step)
No Phase Reversal
图6-26
图6-27
图6-28
图6-29
图6-30, 图6-31
图6-32
Positive Overload Recovery
图6-33
Negative Overload Recovery
图6-34
Small-Signal Step Response (100 mV)
Large-Signal Step Response
图6-35, 图6-36
图6-37
Settling Time
图6-38 to 图6-41
图6-42
Short-Circuit Current vs Temperature
Maximum Output Voltage vs Frequency
Propagation Delay Rising Edge
Propagation Delay Falling Edge
Crosstalk vs Frequency
图6-43
图6-44
图6-45
图6-46
Copyright © 2023 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
6.9 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 100 pF, (unless otherwise noted)
50
40
30
20
10
0
22
20
18
16
14
12
10
8
Distribution Taken From 190 Amplifiers
6
4
2
0
Offset Voltage (µV)
Offset Voltage (V)
C013
TA = 125°C
图6-1. Offset Voltage Production Distribution at 25°C
图6-2. Offset Voltage Production Distribution at 125°C
Distribution Taken From 190 Amplifiers
Distribution Taken From 190 Amplifiers
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
Offset Voltage (µV)
Offset Voltage (µV)
TA = 85°C
TA = 0°C
图6-3. Offset Voltage Production Distribution at 85°C
图6-4. Offset Voltage Production Distribution at 0°C
50
50
Distribution Taken From 190 Amplifiers
Distribution Taken From 190 Amplifiers
45
45
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
0
0
Offset Voltage (µV)
Offset Voltage (µV)
TA = –25°C
TA = –40° C
图6-5. Offset Voltage Production Distribution at –25°C
图6-6. Offset Voltage Production Distribution at –40°C
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
6.9 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 100 pF, (unless otherwise noted)
50
40
30
20
10
0
30
25
20
15
10
5
Distribution Taken From 75 Amplifiers
Distribution Taken From 75 Amplifiers
0
Offset Voltage Drift (µV/ƒC)
TA = –40°C to +125°C
Offset Voltage Drift (µV/ƒC)
TA = 0°C to 85°C
图6-8. Offset Voltage Drift Distribution from 0°C to 85°C
图6-7. Offset Voltage Drift Distribution from
–40°C to +125°C
50
100
75
25
0
50
25
0
–25
–50
–75
–100
VCM = –18.1 V
–25
–50
–20
–15
–10
–5
0
5
10
15
20
–75 –50 –25
0
25
50
75
100 125 150
Common-Mode Voltage (V)
C001
Temperature (°C)
图6-10. Offset Voltage vs Common-Mode Voltage
图6-9. Offset Voltage vs Temperature
200
100
75
5 Typical Units Shown
150
100
50
VCM = +18.1 V
50
VCM = –18.1 V
P-Channel
25
0
0
–50
–100
–150
–200
–25
–50
–75
–100
N-Channel
VCM = +2.35 V
N-Channel
VCM = –2.35 V
Transition
Transition
P-Channel
–2.5 –2.0 –1.5 –1.0 –0.5 0.0 0.5 1.0 1.5 2.0 2.5
12.5
13.5
14.5
15.5
16.5
17.5
18.5
Common-Mode Voltage (V)
Common-Mode Voltage (V)
VS = ±2.25 V
图6-12. Offset Voltage vs Common-Mode Voltage
图6-11. Offset Voltage vs Common-Mode Voltage
Copyright © 2023 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
6.9 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 100 pF, (unless otherwise noted)
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
180
135
90
45
0
50
40
10 Typical Units Shown
Open-Loop Gain
30
20
10
Phase
0
–10
–20
–30
–40
–50
–20.0
0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0
Power Supply Voltage (V)
1
10
100
1k
10k 100k 1M
10M 100M
Frequency (Hz)
CLOAD = 15 pF
VS = ±2.25 V to ±18 V
图6-14. Open-Loop Gain and Phase vs Frequency
图6-13. Offset Voltage vs Power Supply
20
15
60.0
G = -100
G = +1
G = -1
10
5
IB–
40.0
G = -10
0
20.0
0.0
IB+
–5
–10
–15
–20
œ20.0
18.0
9.0
0.0
9.0
18.0
1000
10k
100k
1M
10M
Common-Mode Voltage (V)
C001
C003
Frequency (Hz)
图6-16. Input Bias Current vs Common-Mode Voltage
图6-15. Closed-Loop Gain and Phase vs Frequency
(V–) + 5
6000
IB+
IB -
Ios
5000
4000
3000
2000
1000
0
(V–) + 4
+125°C
(V–) + 3
(V–) + 2
– 40°C
(V–) + 1
(V–)
Ios
(V–) – 1
œ1000
0
10
20
30
40
50
60
70
80
œ75 œ50 œ25
0
25
50
75 100 125 150 175
Output Current (mA)
Temperature (°C)
C001
C001
图6-18. Output Voltage Swing vs Output Current (Maximum
图6-17. Input Bias Current vs Temperature
Supply)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
6.9 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 100 pF, (unless otherwise noted)
160.0
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
10
8
6
4
VS
= 2.25 V, VCM = V+ - 3 V
2
0
œ2
œ4
œ6
œ8
œ10
VS
= 18 V, VCM = 0 V
+PSRR
CMRR
-PSRR
1
10
100
1k
10k
100k
1M
œ75 œ50 œ25
0
25
50
75
100 125 150
C012
Frequency (Hz)
Temperature (°C)
C001
图6-19. CMRR and PSRR vs Frequency
图6-20. CMRR vs Temperature
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
µV
Peak-to-Peak Noise = VRMS × 6.6 = 1.30
Time (1 s/div)
pp
–75 –50 –25
0
25
50
75
100 125 150
Temperature (°C)
C001
C001
图6-21. PSRR vs Temperature
图6-22. 0.1-Hz to 10-Hz Noise
1000
0.1
0.01
–60
G = +1 V/V, RL = 10 kΩ
G = +1 V/V, RL = 2 kΩ
G = –1 V/V, RL = 10 kΩ
G = –1 V/V, RL = 2 kΩ
–80
VCM = V+ –100 mV
N-Channel Input
100
10
1
0.001
–100
–120
–140
0.0001
0.00001
VCM = 0 V
P-Channel Input
10
100
1k
10k
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
C002
VOUT = 3.5 VRMS
BW = 80 kHz
图6-24. THD+N Ratio vs Frequency
图6-23. Input Voltage Noise Spectral Density vs Frequency
Copyright © 2023 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
6.9 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 100 pF, (unless otherwise noted)
1.2
1.1
1.0
0.9
0.8
0.1
0.01
–60
–80
0.001
–100
–120
–140
0.0001
G = +1 V/V, RL = 10 kΩ
G = +1 V/V, RL = 2 kΩ
G = –1 V/V, RL = 10 kΩ
G = –1 V/V, RL = 2 kΩ
0.00001
0
4
8
12
16
20
24
28
32
36
0.01
0.1
1
10
Supply Voltage (V)
Output Amplitude (VRMS
)
f = 1 kHz, BW = 80 kHz
图6-26. Quiescent Current vs Supply Voltage
图6-25. THD+N vs Output Amplitude
1.2
3.0
2.0
VS = 4.5 V
VS = 36 V
1.1
1
1.0
VS = 18 V
0.0
VS = 2.25 V
–1.0
–2.0
–3.0
0.9
0.8
75
50
25
0
25
50
75
100 125 150
–75 –50 –25
0
25
50
75
100 125 150
Temperature (°C)
Temperature(°C)
C001
RL = 10 kΩ
图6-27. Quiescent Current vs Temperature
图6-28. Open-Loop Gain vs Temperature
10k
50
45
40
35
30
25
20
15
10
5
+ 18 V
-
RISO
+
-
OPA197-Q1
VIN
+
1k
100
10
CL
-18 V
0
RISO = 0 Ω
RISO = 25 Ω25
RISO = 50 Ω
0
10p
100p
1n
0
1
10
100
1k
10k 100k 1M
10M
Capacitive Load (F)
Frequency (Hz)
C016
RI = 1 kΩ
RF = 1 kΩ
G = –1
图6-30. Small-Signal Overshoot vs Capacitive Load (100-mV
图6-29. Open-Loop Output Impedance vs Frequency
Output Step)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
6.9 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 100 pF, (unless otherwise noted)
50
VIN
+ 18 V
+ 18 V
45
-
-
RISO
OPA197-Q1
VOUT
OPA197-Q1
40
35
30
25
20
15
10
5
+
+
+
-
+
-
RL
CL
VIN
-18 V
-18 V
37 VPP
Sine Wave
18.5 V)
(
VOUT
RISO = 0 Ω
0
RISO = 25 Ω
25
RISO = 50 Ω
50
0
Time (200μs/div)
10p
100p
1n
Capacitive Load (F)
G = 1
图6-32. No Phase Reversal
图6-31. Small-Signal Overshoot vs Capacitive Load (100-mV
Output Step)
+ 18
V
VOUT
-
+
VOUT
OPA197-Q1
VIN
+
VOUT
+ 18
V
-
-18
V
-
+
-
VOUT
OPA197-Q1
VIN
+
- 18
V
VIN
VIN
Time (200 ns/div)
Time (200 ns/div)
RI = 1 kΩ
RF = 10 kΩ
G = –10
RI = 1 kΩ
G = –10
RF = 10 kΩ
图6-33. Positive Overload Recovery
图6-34. Negative Overload Recovery
+ 18 V
-
+
OPA197-Q1
VIN
+
CL
-
- 18 V
+ 18 V
-
OPA197-Q1
+
+
VIN
RL
CL
-18 V
-
Time (100 ns/div)
Time (120 ns/div)
CL = 10 pF
G = 1
CL = 10 pF
RL = 1 kΩ
G = –1
图6-35. Small-Signal Step Response (100 mV)
图6-36. Small-Signal Step Response (100 mV)
Copyright © 2023 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
6.9 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 100 pF, (unless otherwise noted)
4
3
2
1
0
–1
+ 18 V
0.01% Settling = 1 mV
-
–2
+
-
OPA197-Q1
VIN
+
CL
–3
–4
-18 V
Step Applied at t = 0
1.25 1.5 1.75 2
0
0.25
0.5
0.75
1
Time (300 ns/div)
Time (μs)
CL = 10 pF
RL = 1 kΩ
G = –1
G = 1
图6-38. Settling Time (10-V Positive Step)
图6-37. Large-Signal Step Response
4
3
4
3
2
1
0
2
1
0
0.01% Settling = 500 μV
–1
–2
–3
–4
–1
0.01% Settling = 1 mV
–2
–3
–4
Step Applied at t = 0
1.2 1.4 1.6
Step Applied at t = 0
1.2 1.4 1.6 1.8 2
0
0.2
0.4
0.6
0.8
1
1.8
0
0.2 0.4 0.6 0.8
1
Time (μs)
Time (μs)
G = 1
G = 1
图6-39. Settling Time (5-V Positive Step)
图6-40. Settling Time (10-V Negative Step)
80
60
40
20
0
4
3
ISC, Source
ISC, Sink
2
1
0
0.01% Settling = 500 μV
–1
–2
–3
–4
Step Applied at t = 0
–75 –50 –25
0
25
50
75
100 125 150
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Temperature (°C)
Time (μs)
C001
G = 1
图6-42. Short-Circuit Current vs Temperature
图6-41. Settling Time (5-V Negative Step)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
6.9 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 100 pF, (unless otherwise noted)
30
Maximum output voltage without
slew-rate induced distortion.
VS
= 15 V
Overdrive = 100 mV
25
20
15
10
5
tpLH = 0.97 ꢀs
VS
= 5 V
VOUT Voltage
VS
=
2.25 V
0
Time (200 ns/div)
10k
100k
1M
Frequency (Hz)
10M
C033
C025
图6-43. Maximum Output Voltage vs Frequency
图6-44. Propagation Delay Rising Edge
-80
-100
-120
-140
-160
-180
VOUT Voltage
tpLH = 1.1 ꢀs
Overdrive = 100 mV
Time (200 ns/div)
1k
10k
100k
1M
C026
Frequency (Hz)
图6-45. Propagation Delay Falling Edge
图6-46. Crosstalk vs Frequency
Copyright © 2023 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
7 Detailed Description
7.1 Overview
The OPAx197-Q1 family of e-trim operational amplifiers use a proprietary method of package-level trim for offset
and offset temperature drift implemented during the final steps of manufacturing after the plastic molding
process. This method minimizes the influence of inherent input transistor mismatch, as well as errors induced
during package molding. The trim communication occurs on the output pin of the standard pinout, and after the
trim points are set, further communication to the trim structure is permanently disabled. 节 7.2 shows the
simplified diagram of the OPAx197-Q1.
Unlike previous e-trim op amps, the OPAx197-Q1 uses a patented two-temperature trim architecture to achieve
a very-low offset voltage of 25 µV (maximum) and low voltage offset drift of 0.5 µV/°C (maximum) over the full
specified temperature range. This level of precision performance at wide supply voltages makes these amplifiers
especially useful for high-impedance industrial sensors, filters, and high-voltage data acquisition.
7.2 Functional Block Diagram
+
NCH Input
Stage
œ
IN+
+
High Capacitive
Load
Compensation
VOUT
36-V
Differential
Front End
Output
Stage
Slew
Boost
œ
INœ
+
PCH Input
Stage
œ
e-trim™
Package Level Trim
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
7.3 Feature Description
7.3.1 Input Protection Circuitry
The OPAx197-Q1 use a unique input architecture to eliminate the need for input protection diodes but still
provide robust input protection under transient conditions. Conventional input diode protection schemes shown
in 图 7-1 can be activated by fast transient step responses, and can introduce signal distortion and settling-time
delays because of alternate current paths, as shown in 图 7-2. For low-gain circuits, these fast-ramping input
signals forward-bias back-to-back diodes, causing an increase in input current, and resulting in extended settling
time, as shown in 图7-3.
V+
V+
+
VIN+
VIN+
+
VOUT
VOUT
OPAx197-Q1
~0.7 V
36 V
-
VIN-
VIN-
-
V-
V-
Conventional Input Protection
Limits Differential Input Range
OPA197-Q1 Provides Full 36-V
Differential Input Range
Copyright © 2018, Texas Instruments Incorporated
图7-1. OPAx197-Q1 Input Protection Does Not Limit Differential Input Capability
1
Ron_mux
Vn = +10 V
RFILT
+10 V
Sn
D
1
2
~œ9.3 V
+10 V
CFILT
CS
CD
Vinœ
2
Ron_mux
Sn+1
Vn+1 = œ10 V RFILT
œ10 V
~0.7 V
Vout
CFILT
CS
Idiode_transient
Vin+
œ10 V
Input Low Pass Filter
Simplified Mux Model
Buffer Amplifier
图7-2. Back-to-Back Diodes Create Settling Issues
100
Standard Input Diode Structure
80
Extends Settling Time
60
40
0.1% Settling = 10 mV
20
0
–20
OPA197-Q1 Input Structure
Offers Fast Settling
–40
–60
–80
–100
0
5
10 15 20 25 30 35 40 45 50 55 60
Time (µs)
C040
图7-3. OPAx197-Q1 Protection Circuit Maintains Fast-Settling Transient Response
Copyright © 2023 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
The OPAx197-Q1 family of operational amplifiers provides a true high-impedance differential input capability for
high-voltage applications. This patented input protection architecture does not introduce additional signal
distortion or delayed settling time, making these devices the optimal op amps for multichannel, high-switched,
input applications. The OPAx197-Q1 tolerate a maximum differential swing (voltage between inverting and
noninverting pins of the op amp) of up to 36 V, making these devices an excellent choice for use as comparators
or in applications with fast-ramping input signals, such as multiplexed data-acquisition systems; see 图8-1.
7.3.2 EMI Rejection
The OPAx197-Q1 use integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the OPAx197-Q1 benefit from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz
to 6 GHz. 图 7-4 shows the results of this testing on the OPAx197-Q1. 表 7-1 shows the EMIRR IN+ values for
the OPAx197-Q1 at particular frequencies commonly encountered in real-world applications. Applications listed
in 表 7-1 may be centered on or operated near the particular frequency shown. Detailed information can also be
found in the TI application report EMI Rejection Ratio of Operational Amplifiers available for download from
www.ti.com.
160.0
PRF = -10 dBm
VSUPPLY = 18 V
VCM = 0 V
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
10M
100M
Frequency (Hz)
1G
10G
C017
图7-4. EMIRR Testing
表7-1. OPAx197-Q1 EMIRR IN+ For Frequencies of Interest
APPLICATION OR ALLOCATION
FREQUENCY
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF) applications
44.1 dB
Global system for mobile communications (GSM) applications, radio communication, navigation, GPS (to
1.6 GHz), GSM, aeronautical mobile, UHF applications
900 MHz
1.8 GHz
2.4 GHz
3.6 GHz
5 GHz
52.8 dB
61.0 dB
69.5 dB
88.7 dB
105.5 dB
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
Radiolocation, aero communication and navigation, satellite, mobile, S-band
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
7.3.3 Phase Reversal Protection
The OPAx197-Q1 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when
the input is driven beyond its linear common-mode range. This condition is most often encountered in
noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the
output to reverse into the opposite rail. The OPAx197-Q1 is a rail-to-rail input op amp; therefore, the common-
mode range can extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the
output limits into the appropriate rail. This performance is shown in 图7-5.
VIN
+ 18 V
-
OPA197-Q1
VOUT
+
+
-
-18 V
37 VPP
Sine Wave
18.5 V)
(
VOUT
Time (200μs/div)
图7-5. No Phase Reversal
7.3.4 Thermal Protection
The internal power dissipation of any amplifier causes the internal (junction) temperature to rise. This
phenomenon is called self heating. The absolute maximum junction temperature of the OPAx197-Q1 is 150°C
and exceeding this maximum temperature causes damage to the device. The OPAx197-Q1 have a thermal
protection feature that prevents damage from self heating. The protection works by monitoring the temperature
of the device and turning off the op amp output drive for temperatures above 140°C. 图7-6 shows an application
example for the OPAx197-Q1 that has significant self heating (159°C) because of the power dissipation (0.81
W). Thermal calculations indicate that for an ambient temperature of 65°C, the device junction temperature must
reach 187°C. The actual device, however, turns off the output drive to maintain a safe junction temperature. 图
7-6 shows how the circuit behaves during thermal protection. During normal operation, the device acts as a
buffer so the output is 3 V. When self heating causes the device junction temperature to increase above 140°C,
the thermal protection forces the output to a high-impedance state and the output is pulled to ground through
resistor RL.
Normal
Operation
3 V
TA = 65°C
+30 V
PD = 0.81W
Output
High-Z
RꢀJA = 116°C/W
TJ = 116°C/W × 0.81W + 65°C
TJ = 159°C (expected)
0 V
-
150°C
OPAx197-Q1
140ºC
+
IOUT = 30 mA
+
3 V
œ
RL
100 Ω
+
VIN
3 V
œ
Copyright © 2017, Texas Instruments Incorporated
图7-6. Thermal Protection
Copyright © 2023 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
7.3.5 Capacitive Load and Stability
The OPAx197-Q1 feature a patented output stage capable of driving large capacitive loads, and in a unity-gain
configuration, directly drive up to 1 nF of pure capacitive load. Increasing the gain enhances the ability of these
amplifiers to drive greater capacitive loads; see 图 7-7 and 图 7-8. The particular op-amp circuit configuration,
layout, gain, and output loading are some of the factors to consider when establishing whether an amplifier is
stable in operation.
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
+ 18 V
-
+ 18 V
RISO
OPA197-Q1
-
RISO
+
+
-
RL
CL
+
-
OPA197-Q1
VIN
-18 V
VIN
+
CL
-18 V
0
RISO = 0 Ω
RISO = 25 Ω25
RISO = 50 Ω
RISO = 0 Ω
0
RISO = 25 Ω
25
RISO = 50 Ω
50
0
0
10p
100p
Capacitive Load (F)
1n
10p
100p
Capacitive Load (F)
1n
图7-7. Small-Signal Overshoot vs Capacitive Load 图7-8. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step) (100-mV Output Step)
For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small (10-
Ωto 20-Ω) resistor, RISO, in series with the output, as shown in 图7-9. This resistor significantly reduces ringing
and maintains dc performance for purely capacitive loads. However, if a resistive load is in parallel with the
capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing
the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low
output levels. A high capacitive load drive makes the OPAx197-Q1 a great choice for applications such as
reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in 图 7-9 uses an isolation
resistor, RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased
phase margin, and results using the OPAx197-Q1 are summarized in 表 7-2. For additional information on
techniques to optimize and design using this circuit, TI Precision Design TIPD128 details complete design goals,
simulation, and test results.
+Vs
Vout
Riso
+
Cload
+
Vin
-Vs
œ
图7-9. Extending Capacitive Load Drive With the OPAx197-Q1
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
表7-2. OPAx197-Q1 Capacitive Load Drive Solution Using Isolation Resistor Comparison of Calculated
and Measured Results
PARAMETER
Capacitive Load
Phase Margin
RISO (Ω)
VALUE
100 pF
1000 pF
0.01 µF
0.1 µF
1 µF
45°
47
60°
45°
24
60°
45°
20
60°
51
45°
6.2
60°
45°
2
60°
4.7
360
100
15.8
Measured
Overshoot (%)
23.2 8.6
45.1°
10.4
22.5
9
22.1
8.7
23.1
8.6
21
8.6
Calculated PM
58.1°
45.8°
59.7°
46.1°
60.1°
45.2°
60.2°
47.2°
60.2°
For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files, simulation results, and test
results, see TI Precision Design TIPD128Capacitive Load Drive Solution using an Isolation Resistor.
7.3.6 Common-Mode Voltage Range
The OPAx197-Q1 are 36-V, true rail-to-rail input operational amplifiers with an input common-mode range that
extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel
and P-channel differential input pairs, as shown in 图 7-10. The N-channel pair is active for input voltages close
to the positive rail, typically (V+) – 3 V to 100 mV above the positive supply. The P-channel pair is active for
inputs from 100 mV below the negative supply to approximately (V+) – 1.5 V. There is a small transition region,
typically ( V+) –3 V to (V+) – 1.5 V, in which both input pairs are on. This transition region can vary modestly
with process variation, and within this region, PSRR, CMRR, offset voltage, offset drift, noise, and THD
performance may be degraded compared to operation outside this region.
+Vsupply
IS1
VINœ
PCH1
NCH4
NCH3
PCH2
VIN+
e-trimTM
FUSE BANK
VOS TRIM
VOS DRIFT TRIM
œVsupply
图7-10. Rail-to-Rail Input Stage
Copyright © 2023 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
To achieve the best performance for two-stage rail-to-rail input amplifiers, avoid the transition region when
possible. The OPAx197-Q1 use a precision trim for both the N-channel and P-channel regions. This technique
enables significantly lower levels of offset than previous-generation devices, causing variance in the transition
region of the input stages to appear exaggerated relative to offset over the full common-mode range, as shown
in 图7-11.
P-Channel
Region
Transition
Region
N-Channel
Region
P-Channel
Region
Transition
Region
N-Channel
Region
200
100
200
100
0
0
œ100
œ100
œ200
œ300
OPA197 e-Trim
Input Offset Voltage vs Vcm
œ200
œ300
Input Offset Voltage vs Vcm
without e-Trim Input
œ15.0 œ14.0
…
11.0
12.0
Common-Mode Voltage (V)
13.0
14.0
15.0
œ15.0 œ14.0
…
11.0
12.0
Common-Mode Voltage (V)
13.0
14.0
15.0
图7-11. Common-Mode Transition vs Standard Rail-to-Rail Amplifiers
7.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage
breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to
the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them
from accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. 图 7-12 shows an illustration of the ESD circuits contained in the OPAx197-Q1 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or
the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain
inactive during normal circuit operation.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
TVS
RF
+VS
VDD
OPAx197-Q1
100 Ω
100 Ω
R1
INœ
œ
RS
IN+
+
Power Supply
ESD Cell
RL
+
VIN
œ
VSS
œVS
TVS
Copyright © 2017, Texas Instruments Incorporated
图7-12. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event is very short in duration and very high voltage (for example, 1 kV, 100 ns), whereas an EOS event
is long duration and lower voltage (for example, 50 V, 100 ms). The ESD diodes are designed for out-of-circuit
ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).
During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit
(labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
7.3.8 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a
linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the
rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the OPAx197-Q1 is approximately 200 ns.
7.4 Device Functional Modes
The OPAx197-Q1 have a single functional mode and is operational when the power-supply voltage is greater
than 4.5 V (±2.25 V). The maximum power supply voltage for the OPAx197-Q1 is 36 V (±18 V).
Copyright © 2023 Texas Instruments Incorporated
28
Submit Document Feedback
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The OPAx197-Q1 family offers outstanding dc precision and ac performance. These devices operate up to 36-V
supply rails and offer true rail-to-rail input and output, ultra-low offset voltage and offset voltage drift, as well as
10-MHz bandwidth and high capacitive load drive. These features make the OPAx197-Q1 a robust, high-
performance operational amplifier for high-voltage industrial applications.
8.2 Typical Applications
8.2.1 16-Bit Precision Multiplexed Data-Acquisition System
图 8-1 shows a 16-bit, differential, 4-channel, multiplexed data-acquisition system. This example is typical in
industrial applications that require low distortion and a high-voltage differential input. The circuit uses the
ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along
with a precision, high-voltage, signal-conditioning front end, and a 4-channel differential multiplexer (mux). This
TI Precision Design details the process for optimizing the precision, high-voltage, front-end drive circuit using the
OPAx197-Q1 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864.
1
2
3
4
High-Impedance Inputs
No Differential Input Clamps
Fast Settling-Time Requirements
Attenuate High-Voltage Input Signal
Fast-Settling Time Requirements
Stability of the Input Driver
Attenuate ADC Kickback Noise
VREF Output: Value and Accuracy
Low Temp and Long-Term Drift
Very Low Output Impedance
Input-Filter Bandwidth
Voltage
Reference
OPAx197-Q1
+
CH0+
CH0-
RC Filter
Buffer
RC Filter
20-V,
10-kHz
Sine Wave
Reference Driver
+
Gain
Network
Gain
Network
OPAx197-Q1
OPAx197-Q1
+
4:2
Mux
REFP
+
VINP
OPAx197-Q1
Gain
Network
OPAx197-Q1
+
CH3+
OPAx197-Q1
+
Antialiasing
Filter
SAR
ADC
20-V,
10-kHz
Sine Wave
+
VINM
OPAx197-Q1
CH3-
n
CONV
16 Bits
400 kSPS
High-Voltage Level Translation
High-Voltage Multiplexed Input
Voltage
Divider
REF3240
OPA350
Shmidtt
Trigger
VCM Generation Circuit
Counter
Delay
n
Digital Counter For Multiplexer
5
Fast logic transition
Copyright © 2017, Texas Instruments Incorporated
图8-1. OPAx197-Q1 in 16-Bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for High-
Voltage Inputs With Lowest Distortion
8.2.1.1 Design Requirements
The primary objective is to design a ±20-V, differential, 4-channel, multiplexed data acquisition system with
lowest distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10-kHz, full-scale, pure sine-wave
input. The design requirements for this block design are:
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
• System supply voltage: ±15 V
• ADC supply voltage: 3.3 V
• ADC sampling rate: 400 kSPS
• ADC reference voltage (REFP): 4.096 V
• System input signal: A high-voltage differential input signal with a peak amplitude of 10 V and frequency (fIN)
of 10 kHz are applied to each differential input of the multiplexer.
8.2.1.2 Detailed Design Procedure
The purpose of this precision design is to design an optimal high voltage multiplexed data acquisition system for
highest system linearity and fast settling. The overall system block diagram is illustrated in 图8-1. The circuit is a
multichannel data acquisition signal chain consisting of an input low-pass filter, mux, mux output buffer,
attenuating SAR ADC driver, digital counter for mux and the reference driver. The architecture allows fast
sampling of multiple channels using a single ADC, providing a low-cost solution. The two primary design
considerations to maximize the performance of a precision multiplexed data acquisition system are the mux input
analog front-end and the high-voltage level translation SAR ADC driver design. However, carefully design each
analog circuit block based on the ADC performance specifications in order to achieve the fastest settling at 16-bit
resolution and lowest distortion system. 图 8-1 includes the most important specifications for each individual
analog block.
This design systematically approaches each analog circuit block to achieve a 16-bit settling for a full-scale input
stage voltage and linearity for a 10-kHz sinusoidal input signal at each input channel. The first step in the design
is to understand the requirement for extremely low impedance input-filter design for the mux. This understanding
helps in the decision of an appropriate input filter and selection of a mux to meet the system settling
requirements. The next important step is the design of the attenuating analog front-end (AFE) used to level
translate the high-voltage input signal to a low-voltage ADC input when maintaining amplifier stability. The next
step is to design a digital interface to switch the mux input channels with minimum delay. The final design
challenge is to design a high-precision, reference-driver circuit that provides the required REFP reference
voltage with low offset, drift, and noise contributions.
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, refer to TI
Precision Design TIPD151, 16-bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for High Voltage Inputs with Lowest
Distortion.
8.2.1.3 Application Curve
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–20
–15
–10
–5
0
5
10
15
20
ADC Differential Input (V)
图8-2. ADC 16-Bit Linearity Error for the Multiplexed Data Acquisition Block
8.2.2 Slew-Rate Limit for Input Protection
In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages.
By controlling the slew rate of the command voltages into the drive circuits, the load voltages ramps up and
down at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one
additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high
Copyright © 2023 Texas Instruments Incorporated
30
Submit Document Feedback
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
output current and slew rate of the OPAx197-Q1 make these devices the optimal amplifiers to achieve slew-rate
control for both dual- and single-supply systems.图8-3 shows the OPAx197-Q1 in a slew-rate limit design.
Op Amp Gain Stage
Slew Rate Limiter
C1
470 nF
R1
1.69 kΩ
VEE
VEE
R2
1.6 MΩ
-
OPAx197-Q1
V+
-
OPAx197-Q1
V+
VIN
+
VOUT
+
VCC
RL
10 kΩ
VCC
Copyright © 2017, Texas Instruments Incorporated
图8-3. Slew-Rate Limiter Uses One Op Amp
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, see TI
Precision Design TIPD140, Slew Rate Limiter Uses One Op Amp.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
8.2.3 Precision Reference Buffer
The OPAx197-Q1 feature high output-current-drive capability and low input offset voltage, making these devices
an excellent reference buffer to provide an accurate buffered output with ample drive current for transients. For
the 10-µF ceramic capacitor shown in 图 8-4, a 37.4-Ω isolation resistor (RISO), provides separation of two
feedback paths for optimal stability. Feedback path number one is through RF and is directly at the output
(VOUT). Feedback path number two is through RFx and CF and is connected at the output of the op amp. The
optimized stability components shown for the 10-µF load give a closed-loop signal bandwidth at VOUT of 4 kHz
and still provide a loop gain phase margin of 89°. Any other load capacitances require recalculation of the
stability components: RF, RFx , CF , and RISO
.
RF
1 kΩ
CF
39 nF
RFx
10 kΩ
RISO
37.4 Ω
-
VOUT
OPAx197-Q1
V+
+
CL
10 µF
+
VCC
VREF
2.5 V
Copyright © 2017, Texas Instruments Incorporated
图8-4. Precision Reference Buffer
Copyright © 2023 Texas Instruments Incorporated
32
Submit Document Feedback
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
9 Power Supply Recommendations
The OPAx197-Q1 are specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply
from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in 节6.9.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see Absolute Maximum
Ratings.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see 节10.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in
parallel with the noisy trace.
• Place the external components as close as possible to the device. As illustrated in 图10-2, keep RF and RG
close to the inverting input to minimize parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• For best performance, clean the PCB following board assembly.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture
introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at
85°C for 30 minutes is sufficient for most circumstances.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
10.2 Layout Examples
VIN
+
VOUT
RG
RF
图10-1. Schematic Representation
Place components close
to device and to each
other to reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
RF
VS+
N/C
N/C
RG
GND
œIN
+IN
Vœ
V+
OUTPUT
N/C
VIN
GND
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitors
图10-2. Operational Amplifier Board Layout for Noninverting Configuration
Copyright © 2023 Texas Instruments Incorporated
34
Submit Document Feedback
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ Simulation Software (Free Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™
simulation software is a free, fully functional version of the TINA software, preloaded with a library of macro
models in addition to a range of both passive and active models. TINA-TI simulation software provides all the
conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI simulation software offers extensive
post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the
ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-
start tool.
备注
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 TI Precision Designs
The OPA197 is featured in several Texas Instruments (TI) Precision Designs, available online at http://
www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s
precision analog applications experts and offer the theory of operation, component selection, simulation,
complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application report
• Texas Instruments, Capacitive Load Drive Solution using an Isolation Resistor reference design
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
OPA197-Q1, OPA2197-Q1, OPA4197-Q1
ZHCSHU3A –MARCH 2018 –REVISED JANUARY 2021
www.ti.com.cn
11.5 Trademarks
e-trim™, TINA-TI™, and TI E2E™ are trademarks of Texas Instruments.
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
所有商标均为其各自所有者的财产。
11.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
36
Submit Document Feedback
Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA197QDGKRQ1
OPA2197QDGKRQ1
OPA4197QPWRQ1
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
TSSOP
DGK
DGK
PW
8
8
2500 RoHS & Green
2500 RoHS & Green
2000 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
197
Samples
Samples
Samples
NIPDAUAG
NIPDAU
2197
14
O4197Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jan-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA197-Q1, OPA2197-Q1, OPA4197-Q1 :
Catalog : OPA197, OPA2197, OPA4197
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jan-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA197QDGKRQ1
OPA2197QDGKRQ1
OPA4197QPWRQ1
VSSOP
VSSOP
TSSOP
DGK
DGK
PW
8
8
2500
2500
2000
330.0
330.0
330.0
12.4
12.4
12.4
5.3
5.3
6.9
3.4
3.4
5.6
1.4
1.4
1.6
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
14
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jan-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA197QDGKRQ1
OPA2197QDGKRQ1
OPA4197QPWRQ1
VSSOP
VSSOP
TSSOP
DGK
DGK
PW
8
8
2500
2500
2000
366.0
366.0
356.0
364.0
364.0
356.0
50.0
50.0
35.0
14
Pack Materials-Page 2
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
©2020 ICPDF网 联系我们和版权申明